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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a octal 8-bit trimdac with power shutdown AD8801/ad8803 ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features low cost replaces eight potentiometers eight individually programmable outputs three-wire serial input power shutdown 25 m w including i dd and i ref midscale preset, AD8801 separate v refl range setting, ad8803 +3 v to +5 v single supply operation applications automatic adjustment trimmer potentiometer replacement video and audio equipment gain and offset adjustment portable and battery operated equipment general description the AD8801/ad8803 provides eight digitally controlled dc voltage outputs. this potentiometer divider trimdac ? allows replacement of the mechanical trimmer function in new designs. the AD8801/ad8803 is ideal for dc voltage adjustment applications. easily programmed by serial interfaced microcontroller ports, the AD8801 with its midscale preset is ideal for potentiometer replacement where adjustments start at a nominal value. appli- cations such as gain control of video amplifiers, voltage con- trolled frequencies and bandwidths in video equipment, geometric correction and automatic adjustment in crt com- puter graphic displays are a few of the many applications ideally suited for these parts. the ad8803 provides independent con- trol of both the top and bottom end of the potentiometer divider allowing a separate zero-scale voltage setting determined by the v refl pin. this is helpful for maximizing the resolution of de- vices with a limited allowable voltage control range. functional block diagram (dacs 2C7 omitted for clarity) internally the AD8801/ad8803 contain eight voltage output digital-to-analog converters, sharing a common reference volt- age input. each dac has its own dac register that holds its output state. these dac registers are updated from an internal serial-to-par- allel shift register that is loaded from a standard three-wire serial input digital interface. eleven data bits make up the data word clocked into the serial input register. this data word is decoded where the first 3 bits determine the address of the dac register to be loaded with the last 8 bits of data. the AD8801/ad8803 consumes only 5 m a from 5 v power supplies. in addition, in shutdown mode reference input current consumption is also re- duced to 5 m a while saving the dac latch settings for use after return to normal operation. the AD8801/ad8803 is available in 16-pin plastic dip and the 1.5 mm height so-16 surface mount packages. trimdac is a registered trademark of analog devices, inc. dac 8 v out v refh v refl . . . . . . AD8801/ad8803 v refl v refh o1 o8 shdn rs cs clk sdi gnd v dd 8 8 8 88 8 3 dac select 11-bit serial latch d ck rs 1 8 address 8-bit latch ck rs 8-bit latch ck rs dac 1 v out v refh v refl see the ad8802/ad8804 for a twelve channel version of this product.
rev. a C2C parameter symbol conditions min typ 1 max units static accuracy specifications apply to all dacs resolution n 8 bits integral nonlinearity error inl C1.5 1/2 +1.5 lsb differential nonlinearity dnl guaranteed monotonic C1 1/4 +1 lsb full-scale error g fse C4 C2.8 +0.5 lsb zero-code error v zse C0.5 0.1 +0.5 lsb dac output resistance r out 358 k w output resistance match d r/r o 1% reference input voltage range 2 v refh 0v dd v v refl pin available on ad8803 only 0 v dd v input resistance r refh digital inputs = 55 h , v refh = v dd 2k w reference input capacitance 3 c ref0 digital inputs all zeros 25 pf c ref1 digital inputs all ones 25 pf digital inputs logic high v ih v dd = +5 v 2.4 v logic low v il v dd = +5 v 0.8 v logic high v ih v dd = +3 v 2.1 v logic low v il v dd = +3 v 0.6 v input current i il v in = 0 v or +5 v 1 m a input capacitance 3 c il 5pf power supplies 4 power supply range v dd range 2.7 5.5 v supply current (cmos) i dd v ih = v dd or v il = 0 v 0.01 5 m a supply current (ttl) i dd v ih = 2.4 v or v il = 0.8 v, v dd = +5.5 v 1 4 ma shutdown current i refh shdn = 0 0.01 5 m a power dissipation p diss v ih = v dd or v il = 0 v, v dd = +5.5 v 27.5 m w power supply sensitivity psrr v dd = 5 v 10%, v refh = +4.5 v 0.001 0.002 %/% power supply sensitivity psrr v dd = 3 v 10%, v refh = +2.7 v 0.01 %/% dynamic performance 3 v out settling time (positive or negative) t s 1/2 lsb error band 0.6 m s crosstalk ct see note 5, f = 100 khz 50 db switching characteristics 3, 6 input clock pulse width t ch , t cl clock level high or low 15 ns data setup time t ds 5ns data hold time t dh 5ns cs setup time t css 10 ns cs high pulse width t csw 10 ns reset pulse width t rs 60 ns clk rise to cs rise hold time t csh 15 ns cs rise to next rising clock t cs1 10 ns notes 1 typical values represent average readings measured at +25 c. 2 v refh can be any value between gnd and v dd , for the ad8803 v refl can be any value between gnd and v dd . 3 guaranteed by design and not subject to production test. 4 digital input voltages v in = 0 v or v dd for cmos condition. dac outputs unloaded. p diss is calculated from (i dd v dd ). 5 measured at a v out pin where an adjacent v out pin is making a full-scale voltage change. 6 see timing diagram for location of measured values. all input control voltages are specified with t r = t f = 2 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. specifications subject to change without notice. AD8801/ad8803Cspecifications (v dd = +3 v 6 10% or +5 v 6 10%, v refh = +v dd , v refl = 0 v, C40 8 c t a +85 8 c unless otherwise noted)
AD8801/ad8803 rev. a C3C ordering guide package package model ftn temperature description option AD8801an rs C40 c to +85 c pdip-16 n-16 AD8801ar rs C40 c to +85 c so-16 r-16a ad8803an refl C40 c to +85 c pdip-16 n-16 ad8803ar refl C40 c to +85 c so-16 r-16a ad8803 pin descriptions pin name description 1v refh common high-side dac reference input 2 o1 dac output #1, addr = 000 2 3 o2 dac output #2, addr = 001 2 4 o3 dac output #3, addr = 010 2 5 o4 dac output #4, addr = 011 2 6 shdn reference inputs open circuit, active low, all dac outputs open circuit. dac latch settings maintained. 7 cs chip select input, active low. when cs returns high, data in the serial input register is decoded based on the address bits and loaded into the tar- get dac register. 8 gnd ground 9v refl common low-side dac reference input 10 clk serial clock input, positive edge triggered 11 sdi serial data input 12 o5 dac output #5, addr = 100 2 13 o6 dac output #6, addr = 101 2 14 o7 dac output #7, addr = 110 2 15 o8 dac output #8, addr = 111 2 16 v dd positive power supply, specified for operation at both +3 v and +5 v. absolute maximum ratings (t a = +25 c, unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3, +8 v v refx to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, v dd outputs (ox) to gnd . . . . . . . . . . . . . . . . . . . . . . . . 0 v, v dd digital input voltage to gnd . . . . . . . . . . . . . . . . . . 0 v, v dd operating temperature range . . . . . . . . . . . . . C40 c to +85 c maximum junction temperature (t j max) . . . . . . . . +150 c storage temperature . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . +300 c package power dissipation . . . . . . . . . . . . . (t j max C t a )/ q ja thermal resistance q ja, soic (so-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 c/w p-dip (n-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 c/w AD8801 pin descriptions pin name description 1v refh common dac reference input 2 o1 dac output #1, addr = 000 2 3 o2 dac output #2, addr = 001 2 4 o3 dac output #3, addr = 010 2 5 o4 dac output #4, addr = 011 2 6 shdn reference input open circuit, active low, all dac outputs open circuit. dac latch settings maintained. 7 cs chip select input, active low. when cs returns high, data in the serial input register is decoded based on the address bits and loaded into the tar- get dac register. 8 gnd ground 9 clk serial clock input, positive edge triggered 10 sdi serial data input 11 o5 dac output #5, addr = 100 2 12 o6 dac output #6, addr = 101 2 13 o7 dac output #7, addr = 110 2 14 o8 dac output #8, addr = 111 2 15 rs asynchronous preset to midscale output setting, active low. loads all dac latches with 80 h . 16 v dd positive power supply, specified for operation at both +3 v and +5 v. pin configurations v refh o1 v dd rs o4 shdn cs o6 o5 sdi o2 o3 o8 o7 gnd clk 1 2 16 15 5 6 7 12 11 10 3 4 14 13 89 top view (not to scale) AD8801 v refh o1 v dd o8 o4 shdn cs o5 sdi clk o2 o3 o7 o6 gnd v refl 1 2 16 15 5 6 7 12 11 10 3 4 14 13 89 top view (not to scale) ad8803 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although these devices feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. a C4C AD8801/ad8803 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 dac register load 1 0 1 0 1 0 +5v 0v sdi clk cs v out octal 8-bit trimdac, with shutdown figure 2a. timing diagram a x or d x a x or d x 1 0 1 0 1 0 +5v 0v sdi (data in) clk cs v out 1 lsb 1 lsb error band t s t csw t csh t cl t css t ch t ds t dh t cs1 detail serial data input timing ( rs = "1") figure 2b. detail timing diagram t s t rs 1 lsb 1 lsb error band 1 0 +5v 2.5v rs v out reset timing figure 2c. reset timing diagram table i. serial-data word format addr data b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb msb lsb 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 operation the AD8801/ad8803 provides eight channels of programmable voltage o utput adjustment capability. changing the programmed output voltage of each trimdac is accomplished by clocking in an 11-bit serial data word into the sdi (serial data input) pin. the format of this data word is three address bits, msb first, followed by eight data bits, msb first. table i provides the se- rial register data word format. the AD8801/ad8803 has the following address assignments for the addr decode which de- termines the location of dac register receiving the serial regis- ter data in bits b7 through b0: dac # = a 2 4 + a 1 2 + a 0 + 1 dac outputs can be changed one at a time in random se- quence. the fast serial-data loading of 33 mhz makes it possible to load all eight dacs in as little time as 3 m s (12 8 30 ns). the exact timing requirements are shown in figure 2. the AD8801 offers a midscale preset activated by the rs pin simplifying initial setting conditions at first power up. the ad8803 has both a v refh and a v refl pin to establish indepen- dent positive full-scale and zero-scale settings to optimize reso- lution. both parts offer a power shutdown shdn that places the dac structure in a zero power consumption state resulting in only leakage currents being consumed from the power supply, v ref inputs, and all 8 outputs. in shutdown mode the dacx latch settings are maintained. when returning to operational mode from power shutdown the dac outputs return to their previous voltage settings. msb o x 2r r p ch n ch to other dacs r 2r 2r 2r . . . . . . . . . gnd v refl lsb dac register d6 d0 d7 v refh figure 3. AD8801/ad8803 equivalent trimdac circuit programming the output voltage the output voltage range is determined by the external refer- ence connected to v refh and v refl pins. see figure 3 for a simplified diagram of the equivalent dac circuit. in the case of the AD8801, its v refl is internally connected to gnd and therefore cannot be offset. v refh can be tied to v dd and v refl can be tied to gnd establishing a basic rail-to-rail voltage out- put programming range. other output ranges are established by the use of different external voltage references. the general transfer equation that determines the programmed output voltage is: v o ( dx ) = ( dx )/256 ( v refh C v refl ) + v refl (1) where dx is the data contained in the 8-bit dacx latch.
AD8801/ad8803 rev. a C5C for example, when v refh = +5 v and v refl = 0 v the follow- ing output voltages will be generated for the following codes: dv ox output state (v refh = +5 v, v refl = 0 v) 255 4.98 v full-scale 128 2.50 v half-scale (midscale reset value) 1 0.02 v 1 lsb 0 0.00 v zero-scale reference inputs (v refh , v refl ) the reference input pins set the output voltage range of all eight dacs. in the case of the AD8801 only the v refh pin is avail- able to establish a user designed full-scale output voltage. the external reference voltage can be any value between 0 and v dd but must not exceed the v dd supply voltage. in the case of the ad8803, which has access to the v refl which establishes the zero-scale output voltage, any voltage can be applied between 0 v and v dd . v refl can be smaller or larger in voltage than v refh since the dac design uses fully bidirectional switches as shown in figure 3. the input resistance to the dac has a code dependent variation that has a nominal worst case measured at 55 h , which is approximately 2 k w . when v refh is greater than v refl , the refl reference must be able to sink current out of the dac ladder, while the refh reference is sourcing current into the dac ladder. the dac design minimizes reference glitch current maintaining minimum interference between dac channels during code changes. dac outputs (o1Co8) the eight dac outputs present a constant output resistance of approximately 5 k w independent of code setting. the distribu- tion of r out from dac to dac typically matches within 1%. however, device to device matching is process lot dependent having a 20% variation. the change in r out with temperature has a 500 ppm/ c temperature coefficient. during power shut- down all eight outputs are open circuited. dac reg #1 en addr dec dac dac reg #8 d10 d9 d8 d7 ser reg d d0 .. . .. . .. . dac 1 AD8801/ad8803 d7 d0 dac 8 d7 d0 8 r r v dd v refh o1 o2 o3 o4 o5 o6 o7 o8 cs clk sdi shdn gnd rs v refl . . . . . . . . . (AD8801 only) (ad8803 only) figure 4. block diagram digital interfacing the AD8801/ad8803 contains a standard three-wire serial in- put control interface. the three inputs are clock (clk), cs and serial data input (sdi). the positive-edge sensitive clk input requires clean transitions to avoid clocking incorrect data into the serial input register. standard logic families work well. if mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. fig- ure 4 block diagram shows more detail of the internal digital cir- cuitry. when cs is taken active low, the clock can load data into the serial register on each positive clock edge, see table ii. table ii. input logic control truth table cs clk register activity 1 x no effect. 0 p shifts serial register one bit loading the next bit in from the sdi pin. p x data is transferred from the serial register to the decoded dac register. see figure 5. note: p = positive edge, x = dont care. the data setup and data hold times in the specification table determine the data valid time requirements. the last 11 bits of the data word entered into the serial register are held when cs returns high. at the same time cs goes high it gates the address decoder which enables one of the eight positive edge triggered dac registers, see figure 5 detail. . . . dac 1 dac 2 dac 8 addr decode serial register cs clk sdi figure 5. equivalent control logic the target dac register is loaded with the last eight bits of the se- rial data word completing one dac update. eight separate 11-bit data words must be clocked in to change all eight output settings. all digital inputs are protected with a series input resistor and parallel zener esd structure shown in figure 6. this applies to digital input pins cs , sdi, rs , shdn , clk. logic 100 w figure 6. equivalent esd protection circuit digital inputs can be driven by voltages exceeding the AD8801/ ad8803 v dd value. this allows 5 v logic to interface directly to the part when it is operated at 3 v.
C6C code ?decimal inl ?lsb 1 ? 0 256 32 64 96 128 160 192 224 0.75 0 ?.25 ?.5 ?.75 0.5 0.25 t a = +85 c t a = +25 c t a = ?0 c v dd = +5v v refh = +5v v refl = 0v figure 7. inl vs. code code ?decimal 1 0.75 dnl ?lsb ? 0 256 64 128 192 0 ?.25 ?.5 ?.75 0.5 0.25 t a = ?0 c, +25 c, +85 c v dd = +5v v refh = +5v v refl = 0v figure 8. differential nonlinearity error vs. code frequency total unadjusted error ?lsb 1200 600 240 ?.4 ?.5 ?.3 ?.2 ?.1 ?.0 ?.9 ?.8 ?.7 ?.6 1080 720 480 260 960 840 0 120 v dd = +4.5v v ref = +4.5v v refl = 0v t a = +25 c ss = 2446 pcs figure 9. total unadjusted error histogram code ?decimal 200 0 0 256 32 i ref current ?? 64 96 128 160 192 224 100 50 150 v dd = +5v v refh = +2v v refl = 0v all other dacs set to zero scale t a = +25 c figure 10. input reference current vs. code 10k 1k 0 ?5 25 5 ?5 ?5 100 10 temperature ? c 65 125 105 85 45 i ref shutdown current ?na v dd = +5.5v v ref = 0v v dd = +5.5v v ref = +5.5v figure 11. shutdown current vs. temperature temperature ? c i dd supply current ?? 100k 0.001 ?5 125 ?5 ?5 5 25 45 65 85 105 10k 10 1 0.1 0.01 1k 100 v dd = +5.5v logic = +2.4v all digital pins tied together v dd = +5.5v logic = +5.5v all digital pins tied together figure 12. supply current vs. temperature rev. a AD8801/ad8803Ctypical performance characteristics
AD8801/ad8803 rev. a C7C 100 0.0001 2.5 0.01 0.001 0.5 0 0.1 1.0 10 2 1.5 1 logic input voltage ?volts 5 3 4.5 4 3.5 t a = +25 c all digital inputs tied together i dd supply current ?ma v dd = +5v v dd = +3v figure 13. supply current vs. logic input voltage 80 60 100 100k 10k 1k 10 40 20 frequency ?hz psrr ?db 0 v dd = +5v 0.5v p v refh = +2v code = 80 h t a = +25 c figure 14. power supply rejection vs. frequency 10 0% 100 90 0% v dd = +5v v ref = +2v time ?1?/div 2v 0v 5v 0v out1 cs figure 15. large-signal settling time 10 0% 100 90 output1: oo h ? ff h time ?0.2?/div output2 ?10mv/div v dd = +5v v ref = +2v f = 500khz figure 16. adjacent channel clock feedthrough 10 0% 100 90 output1: 7f h ? 80 h v dd = +5v v ref = +2v time ?0.2?/div out1 10mv/div cs 5v/div figure 17. midscale transition hours of operation at 150 c 0.01 ?.01 0 600 change in zero-scale error ?lsb 150 300 450 0 ?.005 0.005 v dd = +4.5v v ref = +4.5v ss = 162 pcs v refl = 0v figure 18. zero-scale error accelerated by burn-in
rev. a C8C AD8801/ad8803 hours of operation at 150 c 0.04 ?.04 0 600 150 300 450 0 ?.02 0.02 v dd = +4.5v v ref = +4.5v ss = 162 pcs x + 2 s change in full-scale error ?lsb x x ?2 s figure 19. full-scale error accelerated by burn-in hours of operation at 150 c 1.0 input resistance drift ?k w ?.0 0 600 150 300 450 0 ?.5 0.5 v dd = +4.5v v ref = +4.5v code = 55 h ss = 162 pcs x + 2 s x x ?2 s figure 20. ref input resistance accelerated by burn-in AD8801/ ad8803 v dd dgnd 10? 0.1? + +5v figure 22. recommended supply bypassing for the AD8801/ad8803 buffering the AD8801/ad8803 output in many cases, the nominal 5 k w output impedance of the AD8801/ad8803 is sufficient to drive succeeding circuitry. if a lower output impedance is required, an external amplifier can be added. several examples are shown in figure 23. one ampli- fier of an op291 is used as a simple buffer to reduce the output resistance of dac a. the op291 was chosen primarily for its rail-to-rail input and output operation, but it also offers opera- tion to less than 3 v, low offset voltage, and low supply current. the next two dacs, b and c, are configured in a summing ar- rangement where dac c provides the coarse output voltage setting and dac b can be used for fine adjustment. the inser- tion of r1 in series with dac b attenuates its contribution to the voltage sum node at the dac c output. applications supply bypassing precision analog products, such as the AD8801/ad8803, re- quire a well filtered power source. since the AD8801/ad8803 operate from a single +3 v to +5 v supply, it seems convenient to simply tap into the digital logic power supply. unfortunately, the logic supply is often a switch-mode design, which generates noise in the 20 khz to 1 mhz range. in addition, fast logic gates can generate glitches hundred of millivolts in amplitude due to wiring resistances and inductances. if possible, the AD8801/ad8803 should be powered directly from the system power supply. this arrangement, shown in fig- ure 21, will isolate the analog section from the logic switching transients. even if a separate power supply trace is not available, however, generous supply bypassing will reduce supply-line in- duced errors. local supply bypassing consisting of a 10 m f tan- talum electrolytic in parallel with a 0.1 m f ceramic capacitor is recommended (figure 22). ttl/cmos logic circuits +5v power supply 10? tant 0.1? AD8801/ ad8803 + figure 21. use separate traces to reduce power supply noise
AD8801/ad8803 rev. a C9C v h v l v h v l v h v l v refh v dd +5v gnd v refl digital interfacing omitted for clarity r1 100k w op291 AD8801/ ad8803 simple buffer 0v to 5v summer circuit with fine trim adjustment figure 23. buffering the AD8801/ad8803 output increasing output voltage swing an external amplifier can also be used to extend the output volt- age swing beyond the power supply rails of the AD8801/ad8803. this technique permits an easy digital interface for the dac, while expanding the output swing to take advantage of higher voltage external power supplies. for example, dac a of fig- ure 24 is configured to swing from C5 v to +5 v. the actual output voltage is given by: v out = 1 + r f r s ? ? ? d 256 5 v () 5 v where d is the dac input value (i.e., 0 to 255). this circuit can be combined with the fine/coarse circuit of figure 23 if, for example, a very accurate adjustment around 0 v is desired. a v dd v refh gnd v refl AD8801/ ad8803 b +5v +12v ?v op191 op193 r f 100k w r s 100k w ?v to +4.98v 0v to +10v 100k w 100k w +5v figure 24. increasing output voltage swing dac b of figure 24 is in a noninverting gain of two configura- tion, which increases the available output swing to +10 v. the feedback resistors can be adjusted to provide any scaling of the output voltage, within the limits of the external op amp power supplies. microcomputer interfaces the AD8801/ad8803 serial data input provides an easy inter- face to a variety of single-chip microcomputers ( m cs). many m cs have a built-in serial data capability that can be used for com- municating with the dac. in cases where no serial port is pro- vided, or it is being used for some other purpose (such as an rs-232 communications interface), the AD8801/ad8803 can easily be addressed in software. eleven data bits are required to load a value into the AD8801/ ad8803 (3 bits for the dac address and 8 bits for the dac value). if more than 11 bits are transmitted before the chip se- lect input goes high, the extra (i.e., the most-significant) bits are ignored. this feature is valuable because most m cs only transmit data in 8-bit increments. thus, the m c will send 16 bits to the dac instead of 11 bits. the AD8801/ad8803 will only re- spond to the last 11 bits clocked into the sdi input, however, so the serial data interface is not affected. an 8051 m c interface a typical interface between the AD8801/ad8803 and an 8051 m c is shown in figure 25. this interface uses the 8051s internal serial port. the serial port is programmed for mode 0 opera- tion, which functions as a simple 8-bit shift register. the 8051s port3.0 pin functions as the serial data output, while port3.1 serves as the serial clock. o1 o2 o3 o4 o5 o6 o7 o8 sdi sclk reset shdn cs v dd v refh gnd AD8801 +5v p3.0 p3.1 p1.3 p1.2 p1.1 serial data shift register rxd txd shift clock 1.1 1.2 1.3 port 1 sbuf 8051 ? 0.1? 10? + figure 25. interfacing the 8051 m c to an AD8801/ad8803, using the serial port when data is written to the serial buffer register (sbuf, at special function register location 99 h ), the data is automati- cally converted to serial format and clocked out via port3.0 and port3.1. after 8 bits have been transmitted, the transmit inter- rupt flag (scon.1) is set and the next 8 bits can be transmitted. the AD8801 and ad8803 require the chip select to go low at the beginning of the serial data transfer. in addition, the sclk input must be high when the chip select input goes high at the end of the transfer. the 8051s serial clock meets this require- ment, since port3.1 both begins and ends the serial data in the high state. software for the 8051 interface a software routine for the AD8801/ad8803 to 8051 interface is shown in listing 1. the routine transfers the 8-bit data stored at data memory location dac_value to the AD8801/ad8803 dac addressed by the contents of location dac_addr.
rev. a C10C AD8801/ad8803 ; ; this subroutine loads an AD8801/ad8803 dac from an 8051 microcomputer, ; using the 8051s serial port in mode 0 (shift register mode). ; the dac value is stored at location dac_val ; the dac address is stored at location dac_addr ; ; variable declarations ; port1 data 90h ;sfr register for port 1 dac_value data 40h ;dac value dac_addr data 41h ;dac address shift1 data 042h ;high byte of 16-bit answer shift2 data 043h ;low byte of answer shift_count data 44h ; ; org 100h ;arbitrary start do_8801: clr scon.7 ;set serial clr scon.6 ; data mode 0 clr scon.5 clr scon.1 ;clr transmit flag orl port1.1,#00001110b ;/rs, /shdn, /cs high clr port1.1 ;set the /cs low mov shift1,dac_addr ;put dac value in shift register acall byteswap ; mov sbuf,shift2 ;send the address byte addr_wait: jnb scon.1,addr_wait ;wait until 8 bits are sent clr scon.1 ;clear the serial transmit flag mov shift1,dac_value ;send the dac value acall byteswap ; mov sbuf,shift2 ; valu_wait: jnb scon.1,valu_wait ;wait again clr scon.1 ;clear serial flag setb port1.1 ;/cs high, latch data ret ; into AD8801 ; byteswap: mov shift_count,#8 ;shift 8 bits swap_loop: mov a,shift1 ;get source byte rlc a ;rotate msb to carry mov shift1,a ;save new source byte mov a,shift2 ;get destination byte rrc a ;move carry to msb mov shift2,a ;save djnz shift_count,swap_loop ;done? ret end listing 1. software for the 8051 to AD8801/ad8803 serial port interface
AD8801/ad8803 rev. a C11C the subroutine begins by setting appropriate bits in the serial control register to configure the serial port for mode 0 opera- tion. next the dacs chip select input is set low to enable the AD8801/ad8803. the dac address is obtained from memory location dac_addr, adjusted to compensate for the 8051s serial data format, and moved to the serial buffer register. at this point, serial data transmission begins automatically. when all 8 bits have been sent, the transmit interrupt bit is set, and the subroutine then proceeds to send the dac value stored at location dac_value. finally the chip select input is re- turned high, causing the appropriate AD8801/ad8803 output voltage to change, and the subroutine ends. the 8051 sends data out of its shift register lsb first, while the AD8801/ad8803 require data msb first. the subroutine there- fore includes a byteswap subroutine to reformat the data. this routine transfers the msb-first byte at location shift1 to an lsb-first byte at location shift2. the routine rotates the msb of the first byte into the carry with a rotate left carry in- struction, then rotates the carry into the msb of the second byte with a rotate right carry instruction. after 8 loops, shift2 contains the data in the proper format. the byteswap routine in listing 1 is convenient because the dac data can be calculated in normal lsb form. for example, producing a ramp voltage on a dac is simply a matter of re- peatedly incrementing the dac_value location and calling the ld_8801 subroutine. if the m cs hardware serial port is being used for other purposes, the AD8801/ad8803 can be loaded by using the parallel port. a typical parallel interface is shown in figure 26. the serial data is transmitted to the dac via the 8051s port1.7 output, while port1.6 acts as the serial clock. software for the interface of f igure 26 is contained in listing 2. the subroutine will send the value stored at lo cation dac_value to the a d8801/ad8803 dac addressed by location dac_addr. the program begins by setting the AD8801/ad8803s serial clock and chip select inputs high, then setting chip select low to start the serial interface process. the dac address is loaded into the accumulator and three rotate right shifts are per- formed. this places the dac address in the 3 msbs of the ac- cumulator. the address is then sent to the AD8801/ad8803 via the send_serial subroutine. next, the dac value is loaded into the accumulator and sent to the AD8801/ad8803. finally, the chip select input is set high to complete the data transfer. ; this 8051 m c subroutine loads an AD8801 or ad8803 dac with an 8-bit value, ; using the 8051s parallel port #1. ; the dac value is stored at location dac_value ; the dac address is stored at location dac_addr ; ; variable declarations port1 data 90h ;sfr register for port 1 dac_value data 40h ;dac value dac_addr data 41h ;dac address (0 through 7) loopcount data 43h ;count loops ; org 100h ;arbitrary start ld_8803: orl port1,#11110000b ;set clk, /cs and /shdn high, clr port1.5 ;set chip select low mov loopcount,#3 ;address is 3 bits mov a,dac_addr ; get dac address rr a ; rotate the dac rr a ;address to the most rr a ;significant bits (msbs) acall send_serial ;send the address mov loopcount,#8 ;do 8 bits of data mov a,dac_value acall send_serial ;send the data setb port1.5 ;set /cs high ret ;done send_serial: rlc a ;move next bit to carry mov port1.7,c ;move data to sdi clr port1.6 ;pulse the setb port1.6 ; clk input djnz loopcount,send_serial ;loop if not done ret; end listing 2. software for the 8051 to AD8801/ad8803 parallel port interface
rev. a C12C AD8801/ad8803 o1 o2 o3 o4 o5 o6 o7 o8 cs shdn v dd v refh gnd ad8803 +5v p1.7 p1.6 p1.5 p1.4 1.5 1.6 1.7 port 1 8051 ? 1.4 sdi clk v refl figure 26. an AD8801/ad8803-8051 m c interface using parallel port 1 unlike the serial port interface of figure 25, the parallel port in- terface only transmits 11 bits to the AD8801/ad8803. also, the byteswap subroutine is not required for the parallel inter- face, because data can be shifted out msb first. however, the results of the two interface methods are exactly identical. in most cases, the decision on which method to use will be deter- mined by whether or not the serial data port is available for communication with the AD8801/ad8803. an mc68hc11-to-AD8801/ad8803 interface like the 8051, the mc68hc11 includes a dedicated serial data port (labeled spi). the spi port provides an easy interface to the AD8801/ad8803 (figure 27). the interface uses three lines of port d for the serial data, and one or two lines from port c to control the shdn and rs (AD8801 only) inputs. sdi clk cs shdn rs ( AD8801 only) AD8801/ ad8803* mc68hc11 * mosi sck ss pc0 pc1 (pd3) (pd4) (pd5) *additional pins omitted for clarity figure 27. an AD8801/ad8803-to-mc68hc11 interface a software routine for loading the AD8801/ad8803 from a 68hc11 evaluation board is shown in listing 3. first, the mc68hc11 is configured for spi operation. bits cpha and cpol define the spi mode wherein the serial clock (sck) is high at the beginning and end of transmission, and data is valid on the rising edge of sck. this mode matches the requirements of the AD8801/ad8803. after the registers are saved on the stack, the dac value and address are transferred to ram and the AD8801/ad8803s cs is driven low. next, the dacs ad- dress byte is transferred to the spdr register, which automati- cally initiates the spi data transfer. the program tests the spif bit and loops until the data transfer is complete. then the dac value is sent to the spi. when transmission of the second byte is complete, cs is driven high to load the new data and address into the AD8801/ad8803.
AD8801/ad8803 rev. a C13C * * AD8801/ad8803 to m68hc11 interface assembly program * * m68hc11 register definitions * portc equ $1003 port c control register * 0,0,0,0;0,0,rs/, shdn/ ddrc equ $1007 port c data direction portd equ $1008 port d data register * 0,0,/cs,clk;sdi,0,0,0 ddrd equ $1009 port d data direction spcr equ $1028 spi control register * spie,spe,dwom,mstr;cpol,cpha,spr1,spr0 spsr equ $1029 spi status register * spif,wcol,0,modf;0,0,0,0 spdr equ $102a spi data register; read-buffer; write-shifter * * sdi ram variables: sdi1 is encoded from 0 (hex) to 7 (hex) * sdi2 is encoded from 00 (hex) to ff (hex) * AD8801/3 requires two 8-bit loads; upper 5 bits * of sdi1 are ignored. AD8801/3 address bits in last * three lsbs of sdi1. * sdi1 equ $00 sdi packed byte 1 0,0,0,0;0,a2,a1,a0 sdi2 equ $01 sdi packed byte 2 db7,db6,db5,db4;db3,db2,db1,db0 * * main program * org $c000 start of users ram in evb init lds #$cfff top of c page ram * * initialize port c outputs * ldaa #$03 0,0,0,0;0,0,1,1 * /rs-hi, /shdn-hi staa portc initialize port c outputs ldaa #$03 0,0,0,0;0,0,1,1 staa ddrc /rs and /shdn are now enabled as outputs * * initialize port d outputs * ldaa #$20 0,0,1,0;0,0,0,0 * /cs-hi,/clk-lo,sdi-lo staa portd initialize port d outputs ldaa #$38 0,0,1,1;1,0,0,0 staa ddrd /cs,clk, and sdi are now enabled as outputs * * initialize spi interface * ldaa #$53 staa spcr spi is master,cpha=0,cpol=0,clk rate=e/32 * * call update subroutine * bsr update xfer 2 8-bit words to ad8402 jmp $e000 restart buffalo * * subroutine update * update pshx save registers x, y, and a
rev. a C14C AD8801/ad8803 pshy psha * * enter contents of sdi1 data register * ldaa $0000 hi-byte data loaded from memory staa sdi1 sdi1 = data in location 0000h * * enter contents of sdi2 data register * ldaa $0001 low-byte data loaded from memory staa sdi2 sdi2 = data in location 0001h * ldx #sdi1 stack pointer at 1st byte to send via sdi ldy #$1000 stack pointer at on-chip registers * * reset AD8801 to one-half scale (ad8803 does not have a reset input) * bclr portc,y $02 assert /rs bset portc,y $02 de-assert /rs * * get AD8801/03 ready for data input * bclr portd,y $20 assert /cs * tfrlp ldaa 0,x get a byte to transfer via spi staa spdr write sdi data reg to start xfer * wait ldaa spsr loop to wait for spif bpl wait spif is the msb of spsr * (when spif is set, spsr is negated) inx increment counter to next byte for xfer cpx #sdi2+1 are we done yet ? bne tfrlp if not, xfer the second byte * * update AD8801 output * bset portd,y $20 latch register & update AD8801 * pula when done, restore registers x, y & a puly pulx rts ** return to main program ** listing 3. AD8801/ad8803 to mc68hc11 interface program source code
AD8801/ad8803 rev. a C15C outline dimensions dimensions shown in inches and (mm). 16-pin plastic dip package (n-16) 16 18 9 0.840 (21.33) 0.745 (18.93) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-pin narrow body soic package (r-16a) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 1 16 9 8 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 0.0099 (0.25) 0.0075 (0.19) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.3937 (10.00) 0.3859 (9.80)
c2026C18C4/95 printed in u.s.a. C16C

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