; even- or odd-number ed parity by uartcr1) are added to the transfer data. the transfer data formats are shown as follows. figure 11-2 transfer data format figure 11-3 caution on ch anging transfer data format note: in order to switch the transfer data format, perform transmit operations in the above figure 11-3 sequence except for the initial setting. start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit
page 125 TMP86FH46ANG 11.4 transfer rate the baud rate of uart is set of uartcr1. th e example of the baud rate are shown as follows. when tc3 is used as the uart transfer rate (when uartcr1 = ?110?), the tr ansfer clock and transfer rate are determined as follows: transfer clock [hz] = tc3 source clock [hz] / ttreg3 setting value transfer rate [baud] = transfer clock [hz] / 16 11.5 data sampling method the uart receiver keeps sampling input using the cloc k selected by uartcr1 until a start bit is detected in rxd pin input. rt clock star ts detecting ?l? level of the rxd pin. once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sampled at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to majority rule (the data are the same twice or more out of three samplings). figure 11-4 data sampling method table 11-1 transfer rate (example) brg source clock 16 mhz 8 mhz 4 mhz 000 76800 [baud] 38400 [baud] 19200 [baud] 001 38400 19200 9600 010 19200 9600 4800 011 9600 4800 2400 100 4800 2400 1200 101 2400 1200 600 rt0 1 2 3 4 5 6 7 8 9101112 1314 15  01234567891011 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9101112 1314 15  01234567891011 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd pin rxd pin
page 126 11. asynchronous serial interface (uart ) 11.6 stop bit length TMP86FH46ANG 11.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcr1. 11.7 parity set parity / no parity by uartcr1 and set parity type (odd- or even-numbered) by uartcr1. 11.8 transmit/receive operation 11.8.1 data transmit operation set uartcr1 to ?1?. read uartsr to check ua rtsr = ?1?, then write data in tdbuf (transmit data buffer). writing data in tdbuf zero-cl ears uartsr, transfers the data to the transmit shift register and the data are sequenti ally output from the txd pin. the data output include a one-bit start bit, stop bits whose number is specified in uartcr1 and a parity bit if parity addition is specified. select the data transfer baud rate using uartcr1. when data transmit st arts, transmit buffer empty flag uartsr is set to ?1? a nd an inttxd interrupt is generated. while uartcr1 = ?0? and from when ?1? is written to uartcr1 to when send data are written to tdbuf, the txd pin is fixed at high level. when transmitting data, first read uartsr, then write data in tdbuf. otherwise, uartsr is not zero-cleared and transm it does not start. 11.8.2 data receive operation set uartcr1 to ?1?. when data are received vi a the rxd pin, the receive data are transferred to rdbuf (receive data buffer). at this time, the data transmitted includes a start bit and stop bit(s) and a parity bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rdbuf (receive data buffer). then the receive buffer full flag ua rtsr is set and an intrxd interrupt is generated. select the data transfer baud rate using uartcr1. if an overrun error (oerr) occurs when data are received, the da ta are not transferre d to rdbuf (receive data buffer) but discarded; data in the rdbuf are not affected. note:when a receive operation is disabled by setting ua rtcr1 bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs , be sure to perform a re-receive operation.
page 127 TMP86FH46ANG 11.9 status flag 11.9.1 parity error when parity determined using the receive data bits diff ers from the received parity bit, the parity error flag uartsr is set to ?1?. the uartsr is cl eared to ?0? when the rdbuf is read after read- ing the uartsr. figure 11-5 generation of parity error 11.9.2 framing error when ?0? is sampled as the stop bit in the receive data, framing error flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the rdbuf is r ead after reading the uartsr. figure 11-6 generati on of framing error 11.9.3 overrun error when all bits in the next data are received while unread data are still in rdbuf, overrun error flag uartsr is set to ?1?. in this case, the receive data is discarded; data in rdbuf are not affected. the uartsr is cleared to ?0? when the rdbuf is read af ter reading the uartsr. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears perr. final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears ferr.
page 128 11. asynchronous serial interface (uart ) 11.9 status flag TMP86FH46ANG figure 11-7 generati on of overrun error note:receive operations are di sabled until the overrun error flag uartsr is cleared. 11.9.4 receive data buffer full loading the received data in rdbuf sets receive data buffer full flag uartsr to "1". the uartsr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 11-8 generation of receive data buffer full note:if the overrun error flag uartsr is set during the period between reading the uartsr and reading the rdbuf, it cannot be cleared by only reading the rdbuf. therefore, after reading the rdbuf, read the uartsr again to check whether or not the overrun er ror flag which should have been cleared still remains set. 11.9.5 transmit data buffer empty when no data is in the transmit buffer tdbuf, uartsr is set to ?1?, that is, when data in tdbuf are transferred to the transmit shif t register and data transmit star ts, transmit data buffer empty flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the tdbuf is written after reading the uartsr. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears oerr. rdbuf uartsr final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd pin uartsr intrxd interrupt rdbuf after reading uartsr then rdbuf clears rbfl.
page 129 TMP86FH46ANG figure 11-9 generation of transmit data buffer empty 11.9.6 transmit end flag when data are transmitted and no data is in tdbuf (uartsr = ?1?), transmit end flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the data transmit is stated after writing the tdbuf. figure 11-10 generation of transmit end flag and transmit data buffer empty shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 tdbuf txd pin uartsr inttxd interrupt after reading uartsr writing tdbuf clears tbep. shift register * 1yyyy *** 1 xx **** 1 x ***** 1 stop start 1yyyy0 bit 0 txd pin uartsr uartsr inttxd interrupt data write for tdbuf
page 130 11. asynchronous serial interface (uart ) 11.9 status flag TMP86FH46ANG
page 131 TMP86FH46ANG 12. 10-bit ad converter (adc) the TMP86FH46ANG have a 10-bit successive approximation type ad converter. 12.1 configuration the circuit configuration of the 10-bit ad converter is shown in figure 12-1. it consists of control register adccr1 and adccr2 , converted value register adcdr1 and adcdr2, a da converter, a sample-hold circuit, a compar ator, and a successive comparison circuit. note: before using ad converter, set appropriate value to i/o port register conbining a analog input port. for details, see the sec- tion on "i/o ports". figure 12-1 10-bit ad converter 2 4 10 8 ainds adrs r/2 r/2 r ack amd irefon ad conversion result register 1, 2 ad converter control register 1, 2 adbf eocf intadc sain n successive approximate circuit adccr2 adcdr1 adcdr2 adccr1  sample hold circuit a s en shift clock da converter analog input multiplexer y reference voltage analog comparator 2 3 control circuit avss varef avdd ain0 ain7
page 132 12. 10-bit ad converter (adc) 12.2 register configuration TMP86FH46ANG 12.2 register configuration the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects the analog channels and operatio n mode (software start or repeat) in which to per- form ad conversion and controls the ad converter as it starts operating. 2. ad converter control register 2 (adccr2) this register selects the ad conversion time and co ntrols the connection of the da converter (ladder resistor network). 3. ad converted value register 1 (adcdr1) this register used to store the digital value fter being converted by the ad converter. 4. ad converted value register 2 (adcdr2) this register monitors the oper ating status of the ad converter. note 1: select analog input channel during ad converter stops (adcdr2 = "0"). note 2: when the analog input channel is all use dis abling, the adccr1 should be set to "1". note 3: during conversion, do not perform port output instruction to maintain a precision for all of the pins because analog inp ut port use as general input port. and for port near to anal og input, do not input intense signaling of change. note 4: the adccr1 is automatically cleared to "0" after starting conversion. note 5: do not set adccr1 newly again during ad conv ersion. before setting adccr1 newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). note 6: after stop or slow/sleep mode are started, ad conver ter control register1 (adccr1) is all initialized and no data can be written in this register. therfore, to use ad converter again, set the adccr1 newly after returning to normal1 or normal2 mode. ad converter control register 1 adccr1 (001ch) 76543210 adrs amd ainds sain (initial value: 0001 0000) adrs ad conversion start 0: 1: - ad conversion start r/w amd ad operating mode 00: 01: 10: 11: ad operation disable software start mode reserved repeat mode ainds analog input control 0: 1: analog input enable analog input disable sain analog input channel select 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 reserved reserved reserved reserved reserved reserved reserved reserved
page 133 TMP86FH46ANG note 1: always set bit0 in adccr2 to "0" and set bit4 in adccr2 to "1". note 2: when a read instruction for adccr2, bi t6 to 7 in adccr2 read in as undefined data. note 3: after stop or slow/sleep mode are started, ad conver ter control register2 (adccr2) is all initialized and no data can be written in this register. therfore, to use ad converter again, set the adccr2 newly after returning to normal1 or normal2 mode. note 1: setting for " ? " in the above table are inhibited. fc: high frequency oscillation clock [hz] note 2: set conversion time setting should be kept more t han the following time by analog reference voltage (varef) . ad converter control register 2 adccr2 (001dh) 76543210 irefon "1" ack "0" (initial value: **0* 000*) irefon da converter (ladder resistor) connection control 0: 1: connected only during ad conversion always connected r/w ack ad conversion time select (refer to the following table about the con- version time) 000: 001: 010: 011: 100: 101: 110: 111: 39/fc reserved 78/fc 156/fc 312/fc 624/fc 1248/fc reserved table 12-1 ack setting and conversion time condition conversion time 16 mhz 8 mhz 4 mhz 2 mhz 10 mhz 5 mhz 2.5 mhz ack 000 39/fc - - - 19.5 s - - 15.6 s 001 reserved 010 78/fc - - 19.5 s 39.0 s - 15.6 s 31.2 s 011 156/fc - 19.5 s 39.0 s 78.0 s 15.6 s 31.2 s 62.4 s 100 312/fc 19.5 s39.0 s 78.0 s 156.0 s 31.2 s 62.4 s124.8 s 101 624/fc 39.0 s78.0 s 156.0 s - 62.4 s124.8 s- 110 1248/fc 78.0 s 156.0 s - - 124.8 s- - 111 reserved - varef = 4.5 to 5.5 v 15.6 s and more - varef = 2.7 to 5.5 v 31.2 s and more ad converted value register 1 adcdr1 (001fh) 76543210 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 (initial value: 0000 0000) ad converted value register 2 adcdr2 (001eh) 76543210 ad01 ad00 eocf adbf (initial value: 0000 ****)
page 134 12. 10-bit ad converter (adc) 12.2 register configuration TMP86FH46ANG note 1: the adcdr2 is cleared to "0" when reading the a dcdr1. therfore, the ad conversion result should be read to adcdr2 more first than adcdr1. note 2: the adcdr2 is set to "1" when ad conversion star ts, and cleared to "0" when ad conversion finished. it also is cleared upon entering stop mode or slow mode . note 3: if a read instruction is executed for a dcdr2, read data of bit3 to bit0 are unstable. eocf ad conversion end flag 0: 1: before or during conversion conversion completed read only adbf ad conversion busy flag 0: 1: during stop of ad conversion during ad conversion
page 135 TMP86FH46ANG 12.3 function 12.3.1 software start mode after setting adccr1 to ?01? (software start mode), set adccr1 to ?1?. ad conver- sion of the voltage at the analog input pin specified by adccr1 is thereby started. after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1, adcdr2) and at the same time adcdr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. adrs is automatically cleared afte r ad conversion has started. do not set adccr1 newly again (restart) during ad conversion. before setting adrs newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signa l (intadc) is generated (e.g., interrupt handling rou- tine). figure 12-2 software start mode 12.3.2 repeat mode ad conversion of the voltage at the analog input pin specified by adccr1 is performed repeatedly. in this mode, ad conversion is started by setti ng adccr1 to ?1? after setting adccr1 to ?11? (repeat mode). after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1, adcdr2) and at the same time adcdr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. in repeat mode, each time one ad conversion is complete d, the next ad conversion is started. to stop ad conversion, set adccr1 to ?00? (disable mode) by writing 0s. the ad convert operation is stopped immediately. the converted valu e at this time is not stored in the ad converted value register. adcdr1 status eocf cleared by reading conversion result conversion result read adcdr2 intadc interrupt request adcdr2 adccr1 1st conversion result 2nd conversion result indeterminate ad conversion start ad conversion start a dcdr1 a dcdr2 conversion result read conversion result read conversion result read
page 136 12. 10-bit ad converter (adc) 12.3 function TMP86FH46ANG figure 12-3 repeat mode 12.3.3 regi ster setting 1. set up the ad converter control register 1 (adccr1) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable fo r analog input control (ainds). ? specify amd for the ad converter control operation mode (software or repeat mode). 2. set up the ad converter control register 2 (adccr2) as follows: ? set the ad conversion time using ad conversion time (ack). for details on how to set the con- version time, refer to figure 12-1 and ad converter control register 2. ? choose irefon for da converter control. 3. after setting up (1) and (2) above, set ad conversion start (adrs) of ad converter control register 1 (adccr1) to ?1?. if software start mode has been selected, ad conversi on starts immediately. 4. after an elapse of the specified ad conversion time, the ad converted value is stored in ad con- verted value register 1 (adcdr1) and the ad conv ersion finished flag (e ocf) of ad converted value register 2 (adcdr2) is set to ?1?, upon wh ich time ad conversion interrupt intadc is gener- ated. 5. eocf is cleared to ?0? by a read of the conversion result. however, if reconverted before a register read, although eocf is cl eared the previous conversi on result is retained until the next conversion is completed. a dcdr1,adcdr2 eocf cleared by reading conversion result conversion result read a dcdr2 intadc interrupt request conversion operation a dccr1 indeterminate ad conversion start adccr1 ?11? ?00? 1st conversion result ad convert operation suspended. conversion result is not stored. 2nd conversion result 3rd conversion result a dcdr1 a dcdr2 2nd conversion result 3rd conversion result 1st conversion result conversion result read conversion result read conversion result read conversion result read conversion result read
page 137 TMP86FH46ANG 12.4 stop/slow modes during ad conversion when standby mode (stop or slow mode) is entered fo rcibly during ad conversi on, the ad convert operation is suspended and the ad converter is in itialized (adccr1 and adccr2 are initia lized to initial value). also, the conversion result is indeterminate. (conversion results up to the previous operation are cleared, so be sure to read the conversion results before entering standby mode (sto p or slow mode).) when restored from standby mode (stop or slow mode), ad conversion is not automatically restarted, so it is necessa ry to restart ad conversion. note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the analog reference voltage. example :after selecting the conversion time 19.5 s at 16 mhz and the analog input channel ain3 pin, perform ad con- version once. after checking eocf, read the converted value, store the lower 2 bits in address 0009eh nd store the upper 8 bits in address 0009fh in ram. the operation mode is software start mode. : (port setting) : ;set port register approrriately before setting ad converter registers. : : (refer to section i/o port in details) ld (adccr1) , 00100011b ; select ain3 ld (adccr2) , 11011000b ;select conversion time(312/fc) and operation mode set (adccr1) . 7 ; adrs = 1(ad conversion start) sloop : test (adcdr2) . 5 ; eocf= 1 ? jrs t, sloop ld a , (adcdr2) ; read result data ld (9eh) , a ld a , (adcdr1) ; read result data ld (9fh), a
page 138 12. 10-bit ad converter (adc) 12.5 analog input voltage and ad conversion result TMP86FH46ANG 12.5 analog input voltage and ad conversion result the analog input voltage is corresponded to the 10-bit dig ital value converted by the ad as shown in figure 12-4. figure 12-4 analog i nput voltage and ad c onversion result (typ.) 1 0 01 h 02 h 03 h 3fd h 3fe h 3ff h 2 3 1021 1022 1023 1024 analog input voltage 1024 ad conversion result varef avss
page 139 TMP86FH46ANG 12.6 precautions about ad converter 12.6.1 analog input pin voltage range make sure the analog input pins (ain0 to ain7) are used at voltages within varef to avss. if any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. the other analog input pins also are affected by that. 12.6.2 analog input shared pins the analog input pins (ain0 to ain7) are shared w ith input/output ports. when using any of the analog inputs to execute ad conversion, do not execute input/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversi on from degrading. not only these analog input sh ared pins, some other pins may also be affected by noise arising from input/o utput to and from adjacent pins. 12.6.3 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 12-5. the higher the output impedance of the analog input source, more easily they are susceptible to no ise. therefore, make sure the out- put impedance of the signal source in your design is 5 k ? or less. toshiba also recommends attaching a capac- itor external to the chip. figure 12-5 analog i nput equivalent circuit and exam ple of input pin processing da converter aini analog comparator internal resistance permissible signal source impedance internal capacitance 5 k ? (typ) c = 12 pf (typ.) 5 k ? (max) note) i = 7 to 0
page 140 12. 10-bit ad converter (adc) 12.6 precautions about ad converter TMP86FH46ANG
page 141 TMP86FH46ANG 13. key-on wakeup (kwu) in the TMP86FH46ANG, the stop mode is released by not only p20( int5 / stop ) pin but also four (stop2 to stop5) pins. when the stop mode is released by stop2 to stop5 pins, the stop pin needs to be used. in details, refer to the following section " 13.2 control ". 13.1 configuration figure 13-1 key-on wakeup circuit 13.2 control stop2 to stop5 pins can controlled by key-on wakeup c ontrol register (stopcr). it can be configured as enable/disable in 1-bit unit. when thos e pins are used for stop mode releas e, configure corresponding i/o pins to input mode by i/o port register beforehand. 13.3 function stop mode can be entered by setting up the system control register (syscr1), and can be exited by detecting the "l" level on stop2 to stop5 pins, which are enabled by stopcr, for releasing stop mode (note1). key-on wakeup control register stopcr76543210 (0031h) stop5 stop4 stop3 stop2 (initial value: 0000 ****) stop5 stop mode released by stop5 0:disable 1:enable write only stop4 stop mode released by stop4 0:disable 1:enable write only stop3 stop mode released by stop3 0:disable 1:enable write only stop2 stop mode released by stop2 0:disable 1:enable write only stopcr int5 stop stop mode release signal (1: release) (0031h) stop2 stop3 stop4 stop5 stop2 stop3 stop4 stop5
page 142 13. key-on wakeup (kwu) 13.3 function TMP86FH46ANG also, each level of the stop2 to stop5 pins can be co nfirmed by reading correspondi ng i/o port data register, check all stop2 to stop5 pins "h" that is enabled by stopcr before the stop mode is startd (note2,3). note 1: when the stop mode released by the edge release mo de (syscr1 = ?0?), inhibit input from stop2 to stop5 pins by key-on wakeup control register (stopcr) or must be set "h" level into stop2 to stop5 pins that are available input during stop mode. note 2: when the stop pin input is high or stop2 to stop5 pins input which is enabled by stopcr is low, executing an instruction which starts stop mode wi ll not place in stop mode but instead will immediately start the release sequence (warm up). note 3: the input circuit of key-on wakeup input and port i nput is separated?aso each input voltage threshold value is diffrent. therefore, a value comes from port input before stop mode start may be diffrent from a value which is detected by key-on wakeup input (figure 13-2). note 4: stop pin doesn?t have the control register such as stop cr, so when stop mode is released by stop2 to stop5 pins, stop pin also should be used as stop mode release function. note 5: in stop mode, key-on wakeup pin which is enabled as input mode (for releasing stop mode) by key-on wakeup control register (stopcr) may genarate the penet ration current, so the said pin must be disabled ad conversion input (analog voltage input). note 6: when the stop mode is released by stop2 to stop5 pins, the level of stop pin should hold "l" level (figure 13-3). figure 13-2 key-on wakeup input and port input figure 13-3 priority of stop pin and stop2 to stop5 pins table 13-1 release level (edge) of stop mode pin name release level (edge) syscr1="1" (note2) syscr1="0" stop "h" level rising edge stop2 "l" level don?t use (note1) stop3 "l" level don?t use (note1) stop4 "l" level don?t use (note1) stop5 "l" level don?t use (note1) port input external pin key-on wakeup input stop pin a) stop release stop mode stop mode stop pin "l" b) release stop mode stop mode in case of stop2 to stop5 stop2 pin
page 143 TMP86FH46ANG 14. flash memory TMP86FH46ANG has 16384byte flash memory (address: c000h to ffffh). the write and erase operations to the flash memory are controlled in the following three types of mode. - mcu mode the flash memory is accessed by the cpu control in the mcu mode. this mode is used for software bug correction and firmware change after shipment of the device since the write operation to the flash memory is available by retaining the application behavior. - serial prom mode the flash memory is accessed by the cpu control in th e serial prom mode. use of the serial interface (uart) enables the flash memory to be controlled by the small number of pins. TMP86FH46ANG in the serial prom mode supports on-board programming wh ich enables users to prog ram flash memory after the microcontroller is mounted on a user board. - parallel prom mode the parallel prom mode allows the flash memory to be accessed as a stand-alone flash memory by the program writer provided by the third party. high-speed access to th e flash memory is available by control- ling address and data signals directly. for the suppor t of the program writer, please ask toshiba sales rep- resentative. in the mcu and serial prom modes, the flash memory c ontrol register (flscr) is used for flash memory con- trol. this chapter describes how to acce ss the flash memory using the flash memo ry control register (flscr) in the mcu and serial prom modes.
page 144 14. flash memory 14.1 flash memory control TMP86FH46ANG 14.1 flash memory control the flash memory is controlled via the flash memory control register (flscr) and flash memory stanby control resister (flsstb). note 1: the command sequence of the flash me mory can be executed only when flsmd=" 0011b". in other cases, any attempts to execute the command sequence are ineffective. note 2: flsmd must be set to either "1100b" or "0011b". note 3: bits 3 through 0 in flscr are always read as don?t care. note 1: when fstb is set to 1, do not execute the read/write in struction to the flash memory bec ause there is a possibility that the expected data is not read or the program is not operated correctl y. if executing the read/write instruction, fstb is initial- ized to 0 automatically. note 2: if an interrupt is issued when fstb is set to 1, fstb is initialized to 0 automatically and then the vector area of the flash memory is read. note 3: if the idle0/1/2, sleep0/1/2 or stop mode is activated when fstb is set to 1, fstb is initialized to 0 automatically. in the idle0/1/2, sleep0/1/2 or stop mode, the standby function operates regardless of fstb setting. 14.1.1 flash memory command sequenc e execution control (flscr) the flash memory can be protected fr om inadvertent write due to program error or microcontroller misoper- ation. this write protection feature is realized by disabling flash memo ry command sequence execution via the flash memory control register (write protect). to enable command sequence execution, set flscr to ?0011b?. to disable comman d sequence execution, set flscr to ?1100b?. after reset, flscr is initialized to ?1100b? to disable command sequence execution. normally, flscr should be set to ?1100b? except when the flash memory needs to be written or erased. 14.1.2 flash memory stan dby control (flsstb) low power consumption is enabled by cutting off the steady-state current of the flash memory. in the idle0/1/2, sleep0/1/2 or stop mode, th e steady-state current of the flas h memory is cut off automatically. when the program is executed in the ram area (with out accessing the flash me mory) in the normal 1/2 or slow1/2 mode, the current can be cut off by the contro l of the register. to cut off the steady-state current of the flash memory, set flsstb to ?1? by the c ontrol program in the ram area. the procedures for controlling the flsstb regi ster are explained below. (steps1 and 2 are controlled by the program in the flash memory, and steps 3 through 8 are controlled by the write control program ex ecuted in the ram area.) flash memory control register flscr76543210 (0fffh) flsmd (initial value : 1100 ****) flsmd flash memory command sequence exe- cution control 1100: disable command sequence execution 0011: enable command sequence execution others: reserved r/w flash memory standby control register flsstb76543210 (0fe9h) fstb (initial value : **** ***0) fstb flash memory standby control 0: disable the standby function. 1: enable the standby function. write only
page 145 TMP86FH46ANG 1. transfer the control program of th e flsstb register to the ram area. 2. jump to the ram area. 3. disable (di) the interrupt mast er enable flag (imf = ?0?). 4. set flsstb to ?1?. 5. execute the user program. 6. repeat step 5 until the return requ est to the flash memory is detected. 7. set flsstb to ?0?. 8. jump to the flash memory area. note 1: the standby function is not operated by setting fl sstb with the program in the flash memory. you must set flsstb by the program in the ram area. note 2: to use the standby function by setting flsstb to ?1? with the program in the ram area, flsstb must be set to ?0? by the program in the ram area before returning the program control to the flash memory. if the program control is returned to the flash memory with flsstb set to ?1?, the program may misoperate and run out of control.
page 146 14. flash memory 14.2 command sequence TMP86FH46ANG 14.2 command sequence the command sequence in the mcu and the serial prom modes consists of six commands (jedec compatible), as shown in table 14-1. addresses specified in the command sequence are recogni zed with the lower 12 bits (excluding ba, sa, and ff7fh used for read protection). the upper 4 bits are used to specify the flash memory area, note 1: set the address and data to be written. note 2: the area to be erased is specified with the upper 4 bits of the address. 14.2.1 byte program this command writes the fl ash memory for each byte unit. the addresse s and data to be written are specified in the 4th bus write cycle. each byte can be programmed in a maximum of 40 s. the next command sequence cannot be executed until the write operation is completed. to check the completion of the write operation, per- form read operations repeat edly until the same data is read twice fr om the same address in the flash memory. during the write operation, any consecutive attempts to r ead from the same address is reversed bit 6 of the data (toggling between 0 and 1). note:to rewrite data to flash memory addresses at which dat a (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data. 14.2.2 sector erase (4-kbyte erase) this command erases the flash memory in units of 4 k bytes. the flash memory area to be erased is specified by the upper 4 bits of the 6th bus write cycle address. for example, to erase 4 kbytes from f000h to ffffh, specify one of the addresses in f000 h-ffffh as the 6th bus wr ite cycle. the sector erase command is effec- tive only in the mcu and serial prom modes, and it cannot be used in the parallel prom mode. a maximum of 30 ms is required to erase 4 kbytes. the next command sequence cannot be executed until the erase operation is completed. to check the completion of the erase operation, perf orm read operations repeat- edly for data polling until the same data is read twice from the same address in the flash memory. during the erase operation, any consecutive attempts to read from the same address is reversed bit 6 of the data (toggling between 0 and 1). table 14-1 command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle address data address data address data address data address data address data 1 byte program 555h aah aaah 55h 555h a0h ba (note 1) data (note 1) ---- 2 sector erase (4-kbyte erase) 555h aah aaah 55h 555h 80h 555h aah aaah 55h sa (note 2) 30h 3 chip erase (all erase) 555h aah aaah 55h 555h 80h 555h aah aaah 55h 555h 10h 4product id entry555haahaaah55h555h90h------ 5 product id exitxxhf0h---------- product id exit555haahaaah55h555hf0h------ 6read protect555haahaaah55h555ha5hff7fh00h----
page 147 TMP86FH46ANG 14.2.3 chip erase (all erase) this command erases the entire flash memory in appr oximately 30 ms. the next command sequence cannot be executed until the erase operation is completed. to check the completio n of the erase operation, perform read operations repeatedly for data polling until the same data is read twice from the same address in the flash memory. during the erase operation, any consecutive attemp ts to read from the same address is reversed bit 6 of the data (toggling between 0 and 1). after the chip is erased, all bytes contain ffh. 14.2.4 product id entry this command activates the product id mode. in the product id mode, the vendor id, the flash id, and the read protection status can be read from the flash memory. note: the value at address f002h (flash size) depends on the size of flash memory incorporated in each product. for example, if the product has 60-kbyte flash memory, "0eh" is read from address f002h. 14.2.5 product id exit this command is used to exit the product id mode. 14.2.6 read protect this command enables the r ead protection setting in the flash memory . when the read protection is enabled, the flash memory cannot be read in the parallel prom mode. in the seri al prom mode, the flash write and ram loader commands cannot be executed. to disable the read protection setting, it is necessary to execute the chip eras e command sequence. whether or not the read protection is enabled can be checked by reading ff7fh in the product id mode. for details, see table 14-2. it takes a maximum of 40 s to set read protection in the flash memory. the next command sequence cannot be executed until this operation is completed. to check the completion of the read protect operation, perform read operations repeatedly for data polling until the same data is read twice from the same address in the flash memory. during the read protect operation, any attempts to read from the same address is reversed bit 6 of the data (toggling between 0 and 1). table 14-2 values to be read in the product id mode address meaning read value f000h vendor id 98h f001h flash macro id 41h f002h flash size 0eh: 60 kbytes 0bh: 48 kbytes 07h: 32 kbytes 05h: 24 kbytes 03h: 16 kbytes 01h: 8 kbytes 00h: 4 kbytes ff7fh read protection status ffh: read protection disabled other than ffh: read protection enabled
page 148 14. flash memory 14.3 toggle bit (d6) TMP86FH46ANG 14.3 toggle bit (d6) after the byte program, chip erase, and read protect command sequence is executed, any consecutive attempts to read from the same address is reversed bit 6 (d6) of the data (toggling between 0 and 1) until the operation is com- pleted. therefore, this toggle bit provides a software mechanism to check the completion of each operation. usually perform read operations repeatedly for data polling until th e same data is read twice from the same address in the flash memory. after the byte program, chip erase, or read protect command sequence is executed, the initial read of the toggle bit always produces a "1".
page 149 TMP86FH46ANG 14.4 access to the flash memory area when the write, erase and read protect ions are set in the flash memory, read and fetch operations cannot be per- formed in the entire flash memory area. therefore, to perform these operations in the entire flash memory area, access to the flash memory area by the control program in the bootrom or ram area. (the flash memory pro- gram cannot write to the flash memory.) the serial prom or mcu mode is used to run the control program in the bootrom or ram area. note 1: the flash memory can be written or read for each by te unit. erase operations can be performed either in the entire area or in units of 4 kbytes, whereas read operations can be performed by an one transfer instruction. however, the command sequence method is adopted for write and erase operations, requiring several-byte transfer instruc- tions for each operation. note 2: to rewrite data to flash memory addresses at which data (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data. 14.4.1 flash memory contro l in the serial prom mode the serial prom mode is used to access to the fl ash memory by the contro l program provided in the bootrom area. since almost of all op erations relating to access to the flash memory can be controlled sim- ply by the communication data of th e serial interface (uart), these functio ns are transparent to the user. for the details of the serial prom mode, see ?serial prom mode.? to access to the flash memory by using peripheral func tions in the serial prom mode, run the ram loader command to execute the control prog ram in the ram area. the procedures to execute the control program in the ram area is shown in " 14.4.1.1 how to write to the flash memory by executing the control program in the ram area (in the ram loader mode within the serial prom mode) ". 14.4.1.1 how to write to the flash memory by executing the control program in the ram area (in the ram loader mode within the serial prom mode) (steps 1 and 2 are controlled by the bootrom, and steps 3 through 9 are controlled by the control program executed in the ram area.) 1. transfer the write control program to the ram area in the ram loader mode. 2. jump to the ram area. 3. disable (di) the interrup t master enable flag (imf "0"). 4. set flscr to "0011b" (to enable command sequence execution). 5. execute the erase command sequence. 6. read the same flash memory address twice. (repeat step 6 until the same data is re ad by two consecutive reads operations.) 7. execute the write command sequence. 8. read the same flash memory address twice. (repeat step 8 until the same data is read by two consecutive reads operations.) 9. set flscr to "1100b" (to disable command sequence execution). note 1: before writing to the flash memory in the ram area, disable interrupts by setting the interrupt master enable flag (imf) to "0". usually disable interrupts by executing the di instruction at the head of the write control program in the ram area. note 2: since the watchdog timer is disabled by the boot rom in the ram loader mode, it is not required to disable the watchdog timer by the ram loader program.
page 150 14. flash memory 14.4 access to the flash memory area TMP86FH46ANG example :after chip erasure, the program in the ram area writ es data 3fh to address f000h. di : disable interrupts (imf "0") ld (flscr),0011_1000b : enable command sequence execution. ld ix,0f555h ld iy,0faaah ld hl,0f000h ; #### flash memory chip erase process #### ld (ix),0aah : 1st bus write cycle ld (iy),55h : 2nd bus write cycle ld (ix),80h : 3rd bus write cycle ld (ix),0aah : 4th bus write cycle ld (iy),55h : 5th bus write cycle ld (ix),10h : 6th bus write cycle sloop1: ld w,(ix) cmp w,(ix) jr nz,sloop1 : loop until the same value is read. ; #### flash memory write process #### ld (ix),0aah : 1st bus write cycle ld (iy),55h : 2nd bus write cycle ld (ix),0a0h : 3rd bus write cycle ld (hl),3fh : 4th bus write cycle, (f000h)=3fh sloop2: ld w,(hl) cmp w,(hl) jr nz,sloop2 : loop until the same value is read. ld (flscr),1100_1000b : disable command sequence execution. sloop3: jp sloop3
page 151 TMP86FH46ANG 14.4.2 flash memory c ontrol in the mcu mode in the mcu mode, write operations are performed by executing the control program in the ram area. before execution of the control pr ogram, copy the control program into the ram area or obtain it from the external using the communication pin. the procedures to execute the cont rol program in the ram area in the mcu mode are described below. 14.4.2.1 how to write to the flash memory by executing a user write control program in the ram area (in the mcu mode) (steps 1 and 2 are controlled by the program in the flash memory, and steps 3 through 11 are controlled by the control program in the ram area.) 1. transfer the write contro l program to the ram area. 2. jump to the ram area. 3. disable (di) the interrup t master enable flag (imf "0"). 4. disable the watchdog timer, if it is used. 5. set flscr to "0011b" (to enable command sequence execution). 6. execute the erase command sequence. 7. read the same flash memory address twice. (repeat step 7 until the same data is read by two consecutive read operations.) 8. execute the write command sequence. 9. read the same flash memory address twice. (repeat step 9 until the same data is read by two consecutive read operations.) 10. set flscr to "1100b" (to disable command sequence execution). 11. jump to the flash memory area. note 1: before writing to the flash memory in the ram area, disable interrupts by setting the interrupt master enable flag (imf) to "0". usually disable interrupts by executing the di instruction at the head of the write control program in the ram area. note 2: when writing to the flash memory, do not in tentionally use non-maskable interrupts (the watchdog timer must be disabled if it is used). if a non-mask able interrupt occurs while the flash memory is being written, unexpected data is read from the flash memory (interrupt vector), resulting in malfunc- tion of the microcontroller.
page 152 14. flash memory 14.4 access to the flash memory area TMP86FH46ANG example :after sector eras ure (e000h-efffh), the program in the ram area writes data 3fh to address e000h. di : disable interrupts (imf "0") ld (wdtcr2),4eh : clear the wdt binary counter. ldw (wdtcr1),0b101h : disable the wdt. ld (flscr),0011_1000b : enable command sequence execution. ld ix,0f555h ld iy,0faaah ld hl,0e000h ; #### flash memory sector erase process #### ld (ix),0aah : 1st bus write cycle ld (iy),55h : 2nd bus write cycle ld (ix),80h : 3rd bus write cycle ld (ix),0aah : 4th bus write cycle ld (iy),55h : 5th bus write cycle ld (hl),30h : 6th bus write cycle sloop1: ld w,(ix) cmp w,(ix) jr nz,sloop1 : loop until the same value is read. ; #### flash memory write process #### ld (ix),0aah : 1st bus write cycle ld (iy),55h : 2nd bus write cycle ld (ix),0a0h : 3rd bus write cycle ld (hl),3fh : 4th bus write cycle, (1000h)=3fh sloop2: ld w,(hl) cmp w,(hl) jr nz,sloop2 : loop until the same value is read. ld (flscr),1100_1000b : disable command sequence execution. jp xxxxh : jump to the flash memory area. example :this write control program reads data from address f000h and stores it to 98h in the ram area. ld a,(0f000h) : read data from address f000h. ld (98h),a : store data to address 98h.
page 153 TMP86FH46ANG 15. serial prom mode 15.1 outline the TMP86FH46ANG has a 2048 byte bootrom (mask rom) for programming to flash memory. the bootrom is available in the serial prom mode, and controlled by test, boot and reset pins. communica- tion is performed via uart. the serial prom mode ha s seven types of operating mode: flash memory writing, ram loader, flash memory sum output, product id code output, flash memory status output, flash memory eras- ing and flash memory read protection setting. memory addr ess mapping in the serial pr om mode differs from that in the mcu mode. figure 15-1 shows memory address mapping in the serial prom mode. note: though included in above operating range, some of high fr equencies are not supported in the serial prom mode. for details, refer to ?table 15-5?. 15.2 memory mapping the figure 15-1 shows memory mapping in the serial prom mode and mcu mode. in the serial prom mode, the bootrom (mask rom) is mapped in addresses from 7800h to 7fffh. figure 15-1 memory address maps table 15-1 operating range in the serial prom mode parameter min max unit power supply 4.5 5.5 v high frequency (note) 2 16 mhz 003fh 0000h 64 bytes 2048 bytes 0040h 7800h 7fffh c000h ffffh ffffh sfr ram dbr sfr ram dbr bootrom flash memory serial prom mode mcu mode 16384 bytes 003fh 0000h 64 bytes 0040h flash memory c000h 16384 bytes 0fffh 0fffh 512 bytes 128 bytes 128 bytes 023fh 0f80h 0f80h 512 bytes 023fh
page 154 15. serial prom mode 15.3 serial prom mode setting TMP86FH46ANG 15.3 serial prom mode setting 15.3.1 serial prom mode control pins to execute on-board programming, act ivate the serial prom mode. table 15-2 shows pin setting to activate the serial prom mode. note: the boot pin is shared with the uart communication pin (rxd pin) in the serial prom m ode. this pin is used as uart communication pin after activating serial prom mode 15.3.2 pin function in the serial prom mode, tx d (p03) and rxd (p02 ) are used as a serial interface pin. note 1: during on-board programming with other parts mounted on a user board, be careful no to affect these communication control pins. note 2: operating range of high frequency in serial prom mode is 2 mhz to 16 mhz. table 15-2 serial prom mode setting pin setting test pin high boot/rxd pin high reset pin table 15-3 pin function in the serial prom mode pin name (serial prom mode) input/ output function pin name (mcu mode) txd output serial data output (note 1) p03 boot/rxd input/input serial prom mode control/serial data input p02 reset input/out- put serial prom mode control reset test input fixed to high test vdd, avdd power supply 4.5 to 5.5 v vss, avss power supply 0 v varef power supply leave open or apply input reference voltage. i/o ports except p03, p02 i/o these ports are in the high-impedance state in the serial prom mode. the input level is fixed to the port inputs with a hardware feature to prevent overlap current. (the port inputs are invalid.) to make the port inputs valid, set the pin of the spcr register to ?1? by the ram loader control pro- gram. xin input self-oscillate with an oscillator. (note 2) xout output
page 155 TMP86FH46ANG figure 15-2 serial prom mode pin setting note 1: for connection of other pins, refer to " t able 15-3 pin function in the serial prom mode ". 15.3.3 example connection for on-board writing figure 15-3 shows an example connection to perform on-board wring. figure 15-3 example conn ection for on-board writing note 1: when other parts on the application board effect th e uart communication in the serial prom mode, iso- late these pins by a jumper or switch. note 2: when the reset control circuit on the application board effect s activation of the serial prom mode, isolate the pin by a jumper or switch. note 3: for connection of other pins, refer to " t able 15-3 pin function in the serial prom mode ". vdd(4.5 v to 5.5 v) serial prom mode mcu mode vdd test reset external control pull-up xin xout vss gnd boot / rxd (p02) txd (p03) TMP86FH46ANG vdd(4.5 v to 5.5 v) serial prom mode mcu mode vdd test reset pc control pull-up level converter xin xout vss gnd external control board application board rc power-on reset circuit reset control other parts (note 1) (note 2) boot / rxd (p02) txd (p03)
page 156 15. serial prom mode 15.3 serial prom mode setting TMP86FH46ANG 15.3.4 activating t he serial prom mode the following is a procedure to ac tivate the serial prom mode. " figure 15-4 serial prom mode timing " shows a serial prom mode timing. 1. supply power to the vdd pin. 2. set the reset pin to low. 3. set the test pin and boot/rxd pins to high. 4. wait until the power supply and clock oscillation stabilize. 5. set the reset pin to high. 6. input the matching data (5ah) to the boot/rxd pin after setup sequence. for details of the setup timing, refer to " 15.16 uart timing ". figure 15-4 serial prom mode timing vdd test(input) reset(input) program setup time for serial prom mode (rxsup) high level setting matching data don't care reset mode serial prom mode input boot/rxd (input)
page 157 TMP86FH46ANG 15.4 interface specifications for uart the following shows the uart communication format used in the serial prom mode. to perform on-board programming, the communication format of the write controller must also be set in the same manner. the default baud rate is 9600 bps regardless of operating frequency of the microcontroller. the baud rate can be modified by transmitting the baud rate modification data shown in table 1-4 to TMP86FH46ANG. the table 15-5 shows an operating frequency and baud rate. the frequencies which are not described in table 15-5 can not be used. - baud rate (default): 9600 bps - data length: 8 bits - parity addition: none - stop bit: 1 bit table 15-4 baud rate modification data baud rate modification data 04h 05h 06h 07h 0ah 18h 28h baud rate (bps) 76800 62500 57600 38400 31250 19200 9600
page 158 15. serial prom mode 15.4 interface specifications for uart TMP86FH46ANG note 1: ?ref. frequency? and ?rating? show frequencies availabl e in the serial prom mode. though the frequency is supported in the serial prom mode, the serial prom mode may not be activated correctly due to the frequency difference in the external controller (such as pers onal computer) and oscillator, and load capacitance of communication pins. note 2: it is recommended that the total frequency difference is within 3% so that auto detection is performed correctly by the ref- erence frequency. note 3: the external controller must transmit the matching dat a (5ah) repeatedly till the auto detection of baud rate is perform ed. this number indicates the number of times t he matching data is transmitted for each frequency. table 15-5 operating frequency and baud rate in the serial prom mode (note 3) reference baud rate (bps) 76800 62500 57600 38400 31250 19200 9600 baud rate modification data 04h 05h 06h 07h 0ah 18h 28h ref. fre- quency (mhz) rating (mhz) baud rate (bps) (%)(bps)(%)(bps)(%)(bps)(%)(bps)(%)(bps)(%)(bps)(%) 1 21.91 to 2.10------------9615+0.16 2 43.82 to 4.19--------312500.0019231+0.169615+0.16 4.193.82 to 4.19--------32734+4.7520144+4.921 0072 +4.92 3 4.91524.70 to 5.16------ 38400 0.00 - - 19200 0.00 9600 0.00 54.70 to 5.16------ 39063 +1.73 - - 19531 +1.73 9766 +1.73 4 65.87 to 6.45------------9375-2.34 6.1445.87 to 6.45------------96000.00 5 7.3728 7.05 to 7.74 - - - 57600 0.00 - - - - 19200 0.00 9600 0.00 6 8 7.64 to 8.39 - - 62500 0.00 - - 38462 +0.16 31250 0.00 19231 +0.16 9615 +0.16 7 9.8304 9.40 to 10.32 76800 0.00 ---- 38400 0.00 - - 19200 0.00 9600 0.00 10 9.40 to 10.32 78125 +1.73 ---- 39063 +1.73 - - 19531 +1.73 9766 +1.73 8 12 11.75 to 12.90 - - - - 57692 +0.16 - - 31250 0.00 18750 -2.34 9375 -2.34 12.288 11.75 to 12.90 - - - - 59077 +2.56 - - 32000 +2.40 19200 0.00 9600 0.00 12.5 11.75 to 12.90 - - 60096 -3.85 60096 +4.33 - - 30048 -3.85 19531 +1.73 9766 +1.73 9 14.7456 14.10 to 15.48 - - - - 57600 0.00 38400 0.00 - - 19200 0.00 9600 0.00 10 16 15.27 to 16.77 76923 +0.16 62500 0.00 - - 38462 +0.16 31250 0.00 19231 +0.16 9615 +0.16
page 159 TMP86FH46ANG 15.5 operation command the eight commands shown in table 15-6 are used in the serial prom mode. after reset release, the TMP86FH46ANG waits for the matching data (5ah). 15.6 operation mode the serial prom mode has seven types of modes, that are (1) flash memory erasin g, (2) flash memory writing, (3) ram loader, (4) flash memory sum output, (5) product id code output, (6) flash memory status output and (7) flash memory read protection setting modes. description of each mode is shown below. 1. flash memory erasing mode the flash memory is erased by the chip erase (erasing an entire flash area) or sector erase (erasing sectors in 4-kbyte units). the erased area is filled with ffh. when the read protection is enabled, the sector erase in the flash erasing mode can not be performed. to disabl e the read protection, perfor m the chip erase. before erasing the flash memory, tmp86fh4 6ang checks the passwords except a blank product. if the password is not matched, the flash memory erasing mode is not activated. 2. flash memory writing mode data is written to the specified flas h memory address for each byte unit. the external controller must trans- mit the write data in the intel hex format (binary). if no error is encountered till the end record, TMP86FH46ANG calculates the checksum for the entir e flash memory area (c000h to ffffh), and returns the obtained result to the ex ternal controller. when the read prot ection is enabled, the flash memory writing mode is not activated. in this case, perform the chip erase command beforehand in the flash mem- ory erasing mode. before activating the flash me mory writing mode, TMP86FH46ANG checks the pass- word except a blank product. if the password is not matched, flash memory writing mode is not activated. 3. ram loader mode the ram loader transfers the data in intel hex format sent from the external controller to the internal ram. when the transfer is completed normally, the ram loader calculates the checksum. after transmit- ting the results, the ram loader jump s to the ram address specified with the first data record in order to execute the user program. when the read protection is enabled, the ram loader mode is not activated. in this case, perform the chip erase beforehand in the fl ash memory erasing mode. before activating the ram loader mode, tmp86fh46 ang checks the password except a blank product. if the password is not matched, flash ram loader mode is not activated. 4. flash memory sum output mode the checksum is calculated for the entire flash memory area (c000h to ffffh), and the result is returned to the external controller. since the bootrom does not support the oper ation command to read the flash memory, use this checksum to identify programs when managing revisions of application programs. 5. product id code output the code used to identify the product is output. the code to be output consists of 13-byte data, which includes the information indicating th e area of the rom incorporated in the product. the external control- ler reads this code, and recognizes the product to write. (in the case of TMP86FH46ANG, the addresses from c000h to ffffh become the rom area.) table 15-6 operation command in the serial prom mode command data operating mode description 5ah setup matching data. execute this command after releasing the reset. f0h flash memory erasing erases the flash memory area (address c000h to ffffh). 30h flash memory writing writes to the flash memory area (address c000h to ffffh). 60h ram loader writes to the specified ram area (address 0050h to 023fh). 90h flash memory sum output outputs the 2-byte checksum upper byte and lower byte in this order for the entire area of the flash memory (address c000h to ffffh). c0h product id code output outputs the product id code (13-byte data). c3h flash memory status output outputs the status code (7-byte data) such as the read protection condition. fah flash memory read protection setting enables the read protection.
page 160 15. serial prom mode 15.6 operation mode TMP86FH46ANG 6. flash memory status output mode the status of the area from ffe0h to ffffh, and the read protection co ndition are output as 7-byte code. the external controller reads this code to recognize the flash memory status. 7. flash memory read protection setting mode this mode disables reading the flash memory data in parallel prom mode. in the serial prom mode, the flash memory writing and ram loader modes are disabled. to disable th e flash memory read protection, perform the chip erase in th e flash memory erasing mode.
page 161 TMP86FH46ANG 15.6.1 flash memory erasi ng mode (operati ng command: f0h) table 15-7 shows the flash memory erasing mode. note 1: ?xxh 3? indicates that the device enters the halt condition after transmitting 3 bytes of xxh. note 2: refer to " 15.13 specifying the erasure area ". note 3: refer to " 15.8 checksum (sum) ". note 4: refer to " 15.10 passwords ". note 5: do not transmit the password string for a blank product. note 6: when a password error occurs, TMP86FH46ANG stops ua rt communication and enters the halt mode. therefore, when a password error occurs, initialize TMP86FH46ANG by the reset pin and reactivate the serial prom mode. note 7: if an error occurs during transfer of a password address or a password string, TMP86FH46ANG stops uart communica- tion and enters the halt condition. therefore, when a pass word error occurs, initialize TMP86FH46ANG by the reset pin and reactivate the serial prom mode. description of the flash memory erasing mode 1. the 1st through 4th bytes of the transmitted and r eceived data contain the same data as in the flash memory writing mode. table 15-7 flash memory erasing mode transfer byte transfer data from the external controller to TMP86FH46ANG baud rate transfer data from TMP86FH46ANG to the external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: no data transmitted 3rd byte 4th byte baud rate change data (table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (f0h) - modified baud rate modified baud rate - ok: echo back data (f0h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte 8th byte password count storage address bit 15 to 08 (note 4, 5) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 9th byte 10th byte password count storage address bit 07 to 00 (note 4, 5) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 11th byte 12th byte password comparison start address bit 15 to 08 (note 4, 5) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 13th byte 14th byte password comparison start address bit 07 to 00 (note 4, 5) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted) 15th byte : m?th byte password string (note 4, 5) - modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted n?th - 2 byte erase area specification (note 2) modified baud rate - n?th - 1 byte - modified baud rate ok: checksum (upper byte) (note 3) error: nothing transmitted n?th byte - modified baud rate ok: checksum (lower byte) (note 3) error: nothing transmitted n?th + 1 byte (wait for the next operation command data) modified baud rate -
page 162 15. serial prom mode 15.6 operation mode TMP86FH46ANG 2. the 5th byte of the received data contains th e command data in the flash memory erasing mode (f0h). 3. when the 5th byte of the receive d data contains the operation command data shown in table 15-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in this case, f0h). if the 5th byte of the received data does not contai n the operation command data, the device enters the halt condition after sending 3 bytes of the operation command error code (63h). 4. the 7th thorough m'th bytes of the transmitted and received data contai n the same data as in the flash memory writing mode. in the case of a blank produc t, do not transmit a password string. (do not transmit a dummy password string.) 5. the n?th - 2 byte contains the erasure area specification data. the upper 4 bits and lower 4 bits specify the start address and end address of the erasure area, respectively. for the detailed description, see ?1.13 specifying the erasure area?. 6. the n?th - 1 byte and n?th byte contain the upper and lower bytes of the checksum, respectively. for how to calculate the checksum, refer to ?1.8 checksum (sum)?. checksum is calculated unless a receiving error or intel hex format error occurs. after sending the e nd record, the external controller judges whether the transmission is completed corr ectly by receiving the checksum sent by the device. 7. after sending the checksum, the device waits for the next operation command data.
page 163 TMP86FH46ANG 15.6.2 flash memory writing mode (operation command: 30h) table 15-8 shows flash memory writing mode process. note 1: ?xxh 3? indicates that the device enters the halt condition after sending 3 bytes of xxh. for details, refer to " 15.7 error code ". note 2: refer to " 15.9 intel hex format (binary) ". note 3: refer to " 15.8 checksum (sum) ". note 4: refer to " 15.10 passwords ". note 5: if addresses from ffe0h to ffffh are filled with ?ffh?, the passwords are not compared because the device is consid- ered as a blank product. transmitting a password string is not requi red. even in the case of a blank product , it is required to specify the password count storage address and the password comparison start address. transmit these data from the external controller. if a password error occurs due to incorr ect password count storage address or password comparison start address, TMP86FH46ANG stops uart communication and enters the halt condition. therefore, when a password error occurs, initialize TMP86FH46ANG by the reset pin and reactivate the serial rom mode. note 6: if the read protection is enabled or a password error occurs, TMP86FH46ANG stops uart communication and enters the halt confition. in this case, initialize TMP86FH46ANG by the reset pin and reactivate the serial rom mode. note 7: if an error occurs during the reception of a password address or a password string, TMP86FH46ANG stops uart com- munication and enters the halt condition. in th is case, initialize TMP86FH46ANG by the reset pin and reactivate the serial prom mode. table 15-8 flash memory writing mode process transfer byte transfer data from external controller to TMP86FH46ANG baud rate transfer data from TMP86FH46ANG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (30h) - modified baud rate modified baud rate - ok: echo back data (30h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte 8th byte password count storage address bit 15 to 08 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 9th byte 10th byte password count storage address bit 07 to 00 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 11th byte 12th byte password comparison start address bit 15 to 08 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 13th byte 14th byte password comparison start address bit 07 to 00 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted) 15th byte : m?th byte password string (note 5) - modified baud rate - ok: nothing transmitted error: nothing transmitted m?th + 1 byte : n?th - 2 byte intel hex format (binary) (note 2) modified baud rate - - n?th - 1 byte - modified baud rate ok: sum (upper byte) (note 3) error: nothing transmitted n?th byte - modified baud rate ok: sum (lower byte) (note 3) error: nothing transmitted n?th + 1 byte (wait state for the next operation com- mand data) modified baud rate -
page 164 15. serial prom mode 15.6 operation mode TMP86FH46ANG description of the flash memory writing mode 1. the 1st byte of the received data contains the ma tching data. when the serial prom mode is acti- vated, TMP86FH46ANG (her eafter called device), waits to recei ve the matching data (5ah). upon reception of the matching data, the device automatically adjusts the uart?s initial baud rate to 9600 bps. 2. when receiving the matching data (5ah), the device transmits an ech o back data (5ah) as the second byte data to the external controller. if the devi ce can not recognize the matching data, it does not transmit the echo back data and waits for the matc hing data again with automatic baud rate adjust- ment. therefore, the external cont roller should transmit the matching data repeatedly till the device transmits an echo back data. the transmission repe tition count varies depending on the frequency of device. for details, refer to table 15-5. 3. the 3rd byte of the received data contains the baud ra te modification data. the five types of baud rate modification data shown in table 15-4 are available. even if baud rate is not modified, the external controller should transmit the initial baud rate data (28h: 9600 bps). 4. only when the 3rd byte of the received data contai ns the baud rate modificat ion data corresponding to the device's operating frequency, th e device echoes back data the valu e which is the same data in the 4th byte position of the received data. after the ech o back data is transmitted, baud rate modification becomes effective. if the 3rd byte of the received data does not co ntain the baud rate modification data, the device enters the halts condition after se nding 3 bytes of baud rate modification error code (62h). 5. the 5th byte of the received data contains the command data (30h) to write the flash memory. 6. when the 5th byte of the received data contains the operation command data shown in table 1-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in this case, 30h). if the 5th byte of the received da ta does not contain the op eration command data, the device enters the halt condition after sending 3 bytes of the operation command error code (63h). 7. the 7th byte contains the data for 15 to 8 bits of the password count storage address. when the data received with the 7th byte has no receiving error, the device does not send any data. if a receiving error or password error occurs, the device does not send any data and enters the halt condition. 8. the 9th byte contains the data for 7 to 0 bits of the password count storage address. when the data received with the 9th byte has no receiving error, the device does not send any data. if a receiving error or password error occurs, the device does not send any data and enters the halt condition. 9. the 11th byte contains the data for 15 to 8 bits of the password comparison start address. when the data received with the 11th byte has no receiving erro r, the device does not send any data. if a receiv- ing error or password error occurs, the device does not send any data and enters the halt condition. 10. the 13th byte contains the data for 7 to 0 bits of the password comparison start address. when the data received with the 13th byte ha s no receiving error, the device does not send any data. if a receiv- ing error or password error occurs, the device does not send any data and enters the halt condition. 11. the 15th through m?th bytes contain the passwor d data. the number of passwords becomes the data (n) stored in the password count storage address. the external password data is compared with n- byte data from the address specified by the passwor d comparison start addre ss. the external control- ler should send n-byte password data to the device. if the passwords do not match, the device enters the halt condition without returning an error code to the external controller . if the addresses from ffe0h to ffffh are filled with ?f fh?, the passwords are not conpare d because the device is consid- ered as a blank product. 12. the m?th + 1 through n?th - 2 bytes of the receive d data contain the binary data in the intel hex for- mat. no received data is echoed back to the extern al controller. after receiv ing the start mark (3ah for ?:?) in the intel hex format, the device starts data record reception. ther efore, the received data except 3ah is ignored until the start mark is received. afte r receiving the start mark, the device receives the data record, that consists of data lengt h, address, reco rd type, write data and checksum. since the device starts checksum cal culation after receiving an end r ecord, the external controller should wait for the checksum afte r sending the end record. if a recei ving error or intel hex format error occurs, the device enters the halts condition without returning an error code to the external con- troller. 13. the n?th - 1 and n?th bytes contain the checksum upper and lower bytes. for details on how to calcu- late the sum, refer to " 15.8 checksum (sum) ". the checksum is calculated only when the end record is detected and no receivi ng error or intel hex format er ror occurs. after sending the end
page 165 TMP86FH46ANG record, the external controller ju dges whether the transmission is co mpleted correctly by receiving the checksum sent by the device. 14. after transmitting the checksu m, the device waits for the next operation command data. note 1: do not write only the address from ffe0h to ffffh when all flash memory data is the same. if only these area are written, the subsequent operation can not be executed due to password error. note 2: to rewrite data to flash memory addresses at whic h data (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data.
page 166 15. serial prom mode 15.6 operation mode TMP86FH46ANG 15.6.3 ram loader mode (o peration command: 60h) table 15-9 shows ram loader mode process. note 1: ?xxh 3? indicates that the device enters the halt condition after sending 3 bytes of xxh. for details, refer to " 15.7 error code ". note 2: refer to " 15.9 intel hex format (binary) ". note 3: refer to " 15.8 checksum (sum) ". note 4: refer to " 15.10 passwords ". note 5: if addresses from ffe0h to ffffh are filled with ?ffh?, the passwords are not compared because the device is consid- ered as a blank product. transmitting a password string is not requi red. even in the case of a blank product , it is required to specify the password count storage address and the password comparison start address. transmit these data from the external controller. if a password error occurs due to incorr ect password count storage address or password comparison start address, TMP86FH46ANG stops uart communication and enters the halt condition. therefore, when a password error occurs, initialize TMP86FH46ANG by the reset pin and reactivate the serial rom mode. note 6: after transmitting a password string, the external c ontroller must not transmit only an end record. if receiving an end record after a password string, the device may not operate correctly. note 7: if the read protection is enabled or a password error occurs, TMP86FH46ANG stops uart communication and enters the halt condition. in this case, initialize TMP86FH46ANG by the reset pin and reactivate the serial prom mode. table 15-9 ram loader mode process transfer bytes transfer data from external control- ler to TMP86FH46ANG baud rate transfer data from TMP86FH46ANG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (60h) - modified baud rate modified baud rate - ok: echo back data (60h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte 8th byte password count storage address bit 15 to 08 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 9th byte 10th byte password count storage address bit 07 to 00 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 11th byte 12th byte password comparison start address bit 15 to 08 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 13th byte 14th byte password comparison start address bit 07 to 00 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 15th byte : m?th byte password string (note 5) - modified baud rate - ok: nothing transmitted error: nothing transmitted m?th + 1 byte : n?th - 2 byte intel hex format (binary) (note 2) modified baud rate modified baud rate - - n?th - 1 byte - modified baud rate ok: sum (upper byte) (note 3) error: nothing transmitted n?th byte - modified baud rate ok: sum (lower byte) (note 3) error: nothing transmitted ram - the program jumps to the start address of ram in which the first transferred data is written.
page 167 TMP86FH46ANG note 8: if an error occurs during the reception of a password address or a password string, TMP86FH46ANG stops uart com- munication and enters the halt condition. in th is case, initialize TMP86FH46ANG by the reset pin and reactivate the serial prom mode. description of ram loader mode 1. the 1st through 4th bytes of the transmitted and recei ved data contains the same data as in the flash memory writing mode. 2. in the 5th byte of the received data contains the ram loader command data (60h). 3. when th 5th byte of the received data contains the operation command data shown in table 1-6, the device echoes back the value which is the same data in the 6th byte position (in this case, 60h). if the 5th byte does not contain the operation command data, the device enters the halt condition after send- ing 3 bytes of operation command error code (63h). 4. the 7th through m?th bytes of the transmitted and received data contai n the same data as in the flash memory writing mode. 5. the m?th + 1 through n?th - 2 bytes of the received data contain the binary data in the intel hex for- mat. no received data is echoed back to the extern al controller. after receiv ing the start mark (3ah for ?:?) in the intel hex format, the device starts data record reception. ther efore, the received data except 3ah is ignored until the start mark is received. afte r receiving the start mark, the device receives the data record, that consists of data lengt h, address, reco rd type, write data and checksum. the writing data of the data record is written in to ram specified by address. since the device starts checksum calculation after receiving an end record, the external contro ller should wait for the check- sum after sending the end record. if a receiving error or intel hex format error occurs, the device enters the halts condition without returning an error code to the external controller. 6. the n?th - 1 and n?th bytes contain the checksum upper and lower bytes. for details on how to calcu- late the sum, refer to " 15.8 checksum (sum) ". the checksum is calculated only when the end record is detected and no receivi ng error or intel hex format er ror occurs. after sending the end record, the external controller ju dges whether the transmission is co mpleted correctly by receiving the checksum sent by the device. 7. after transmitting the checksum to the external controller, the boot program jumps to the ram address that is specified by the first received data record. note 1: to rewrite data to flash memory addresses at whic h data (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data.
page 168 15. serial prom mode 15.6 operation mode TMP86FH46ANG 15.6.4 flash memory sum out put mode (operati on command: 90h) table 15-10 shows flash memory sum output mode process. note 1: ?xxh 3? indicates that the device enters the halt condition after sending 3 bytes of xxh. for details, refer to " 15.7 error code ". note 2: refer to " 15.8 checksum (sum) ". description of the flash memory sum output mode 1. the 1st through 4th bytes of the transmitted and recei ved data contains the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the command data in the flash memory sum output mode (90h). 3. when the 5th byte of the received data contains the operation command data shown in table 1-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in this case, 90h). if the 5th byte of the received da ta does not contain the op eration command data, the device enters the halt condition after transmitting 3 bytes of operation command error code (63h). 4. the 7th and the 8th bytes contain the upper and lowe r bits of the checksum, respectively. for how to calculate the checksum, refer to " 15.8 checksum (sum) ". 5. after sending the checksum, the device waits for the next operation command data. table 15-10 flash memo ry sum output process transfer bytes transfer data from external control- ler to TMP86FH46ANG baud rate transfer data from TMP86FH46ANG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (90h) - modified baud rate modified baud rate - ok: echo back data (90h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte - modified baud rate ok: sum (upper byte) (note 2) error: nothing transmitted 8th byte - modified baud rate ok: sum (lower byte) (note 2) error: nothing transmitted 9th byte (wait for the next operation com- mand data) modified baud rate -
page 169 TMP86FH46ANG 15.6.5 product id code output mode (operation command: c0h) table 15-11 shows product id code output mode process. note: ?xxh 3? indicates that the device enters th e halt condition after sending 3 bytes of xxh. for details, refer to " 15.7 error code ". description of product id code output mode 1. the 1st through 4th bytes of the transmitted and r eceived data contain the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the product id code output mode command data (c0h). 3. when the 5th byte contains the operation command data shown in table 15-6, the device echoes back the value which is the same data in the 6th byte positio n of the received data (i n this case, c0h). if the 5th byte data does not contain the operation command data, the device enters the halt condition after sending 3 bytes of operation command error code (63h). 4. the 9th through 19th bytes contain the product id code. for details, refer to " 15.11 product id code ". table 15-11 product id code output process transfer bytes transfer data from external controller to TMP86FH46ANG baud rate transfer data from TMP86FH46ANG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (c0h) - modified baud rate modified baud rate - ok: echo back data (c0h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte modified baud rate 3ah start mark 8th byte modified baud rate 0ah the number of transfer data (from 9th to 18th bytes) 9th byte modified baud rate 02h length of address (2 bytes) 10th byte modified baud rate 1dh reserved data 11th byte modified baud rate 00h reserved data 12th byte modified baud rate 00h reserved data 13th byte modified baud rate 00h reserved data 14th byte modified baud rate 01h rom block count (1 block) 15th byte modified baud rate c0h first address of rom (upper byte) 16th byte modified baud rate 00h first address of rom (lower byte) 17th byte modified baud rate ffh end address of rom (upper byte) 18th byte modified baud rate ffh end address of rom (lower byte) 19th byte modified baud rate 22h checksum of transferred data (9th through 18th byte) 20th byte (wait for the next operation command data) modified baud rate -
page 170 15. serial prom mode 15.6 operation mode TMP86FH46ANG 5. after sending the checksum, the device waits for the next operation command data.
page 171 TMP86FH46ANG 15.6.6 flash memory status out put mode (operati on command: c3h) table 15-12 shows flash memory status output mode process. note 1: ?xxh 3? indicates that the device enters the halt condition after sending 3 bytes of xxh. for details, refer to " 15.7 error code ". note 2: for the details on status code 1, refer to " 15.12 flash memory status code ". description of flash memory status output mode 1. the 1st through 4th bytes of the transmitted and r eceived data contain the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the flash memory status output mode command data (c3h). 3. when the 5th byte contains the operation command data shown in table 15-6, the device echoes back the value which is the same data in the 6th byte positio n of the received data (i n this case, c3h). if the 5th byte does not contain the operation command data, the device enters the halt condition after send- ing 3 bytes of operation command error code (63h). 4. the 9th through 13th bytes contain the status code. for details on the status code, refer to " 15.12 flash memory status code ". 5. after sending the status code, the device wa its for the next operation command data. table 15-12 flash memory status output mode process transfer bytes transfer data from external con- troller to TMP86FH46ANG baud rate transfer data from TMP86FH46ANG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (c3h) - modified baud rate modified baud rate - ok: echo back data (c3h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte modified baud rate 3ah start mark 8th byte modified baud rate 04h byte count (from 9th to 12th byte) 9th byte modified baud rate 00h to 03h status code 1 10th byte modified baud rate 00h reserved data 11th byte modified baud rate 00h reserved data 12th byte modified baud rate 00h reserved data 13th byte modified baud rate checksum 2?s complement for the sum of 9th through 12th bytes 9th byte checksum 00h: 00h 01h: ffh 02h: feh 03h: fdh 14th byte (wait for the next operation com- mand data) modified baud rate -
page 172 15. serial prom mode 15.6 operation mode TMP86FH46ANG 15.6.7 flash memory read protection setting mode (operation command: fah) table 15-13 shows flash memory read protection setting mode process. note 1: ?xxh 3? indicates that the device enters the halt condition after sending 3 bytes of xxh. for details, refer to " 15.7 error code ". note 2: refer to " 15.10 passwords ". note 3: if the read protection is enabled for a blank product or a password error occurs for a n on-blank product, TMP86FH46ANG stops uart communication and enters the halt mode. in this case, initialize TMP86FH46ANG by the reset pin and reac- tivate the serial prom mode. note 4: if an error occurs during reception of a password addr ess or a password string, TMP86FH46ANG stops uart communi- cation and enters the halt mode. in this ca se, initialize TMP86FH46ANG by the reset pin and reactivate the serial prom mode. description of the flash memory read protection setting mode 1. the 1st through 4th bytes of the transmitted and r eceived data contain the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the command data in th e flash memory status output mode (fah). 3. when the 5th byte of the received data contains the operation command data shown in table 1-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in table 15-13 flash memory read protection setting mode process transfer bytes transfer data from external con- troller to TMP86FH46ANG baud rate transfer data from TMP86FH46ANG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (fah) - modified baud rate modified baud rate - ok: echo back data (fah) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte 8th byte password count storage address 15 to 08 (note 2) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 9th byte 10th byte password count storage address 07 to 00 (note 2) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 11th byte 12th byte password comparison start address 15 to 08 (note 2) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 13th byte 14th byte password comparison start address 07 to 00 (note 2) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 15th byte : m?th byte password string (note 2) - modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted n?th byte - modified baud rate ok: fbh (note 3) error: nothing transmitted n?+1th byte (wait for the next operation com- mand data) modified baud rate -
page 173 TMP86FH46ANG this case, fah). if the 5th byte does not contai n the operation command data, the device enters the halt condition after transmitting 3 bytes of operation command error code (63h). 4. the 7th through m?th bytes of the transmitted and received data contai n the same data as in the flash memory writing mode. 5. the n'th byte contains the status to be transmitted to the external controller in the case of the success- ful read protection.
page 174 15. serial prom mode 15.7 error code TMP86FH46ANG 15.7 error code when detecting an error, the device tr ansmits the error code to the external controller, as shown in table 15-14. note: if a password error occurs, tmp86f h46ang does not transmit an error code. 15.8 checksum (sum) 15.8.1 calculation method the checksum (sum) is calculated with the sum of all bytes, and the obtain ed result is returned as a word. the data is read for each byte unit and th e calculated result is returned as a word. example: the checksum which is transmitted by executing the fl ash memory write comman d, ram loader command, or flash memory sum output command is calculated in the manner, as shown above. table 15-14 error code transmit data meaning of error data 62h, 62h, 62h baud rate modification error. 63h, 63h, 63h operation command error. a1h, a1h, a1h framing error in the received data. a3h, a3h, a3h overrun error in the received data. a1h if the data to be calculated consists of the four bytes, the checksum of the data is as shown below. b2h a1h + b2h + c3h + d4h = 02eah sum (high)= 02h sum (low)= eah c3h d4h
page 175 TMP86FH46ANG 15.8.2 calculation data the data used to calculate the ch ecksum is listed in table 15-15. table 15-15 checksum calculation data operating mode calculation data description flash memory writing mode data in the entire area of the flash memory even when a part of the flash memory is written, the checksum of the entire flash memory area (c000h to fffh) is calcu- lated. the data length, address, record type and checksum in intel hex format are not included in the checksum. flash memory sum output mode ram loader mode ram data written in the first received ram address through the last received ram address the length of data, address, record type and checksum in intel hex format are not included in the checksum. product id code output mode 9th through 18th bytes of the transferred data for details, refer to " 15.11 product id code ". flash memory status output mode 9th through 12th bytes of the tran sferred data for details, refer to " 15.12 flash memory status code " flash memory erasing mode all data in the erased area of the flash memory (the whole or part of the flash memory) when the sector erase is exec uted, only the erased area is used to calculate the checksum. in the case of the chip erase, an entire area of the flash memory is used.
page 176 15. serial prom mode 15.9 intel hex format (binary) TMP86FH46ANG 15.9 intel hex format (binary) 1. after receiving the checksum of a data record, the device waits for the start mark (3ah ?:?) of the next data record. after receiving the checksum of a data reco rd, the device ignores the data except 3ah transmitted by the external controller. 2. after transmitting the checksum of en d record, the external controller mu st transmit nothing, and wait for the 2-byte receive data (upper and lower bytes of the checksum). 3. if a receiving error or intel hex fo rmat error occurs, the device enters the halt condition without returning an error code to the external controller. the in tel hex format error occurs in the following case: when the record type is not 00h, 01h, or 02h when a checksum error occurs when the data length of an extended record (record type = 02h) is not 02h when the device receives the data reco rd after receiving an extended record (record type = 02h ) with extended address of 1000h or larger. when the data length of the end record (record type = 01h) is not 00h 15.10passwords the consecutive eight or mo re-byte data in the flash memory ar ea can be specified to the password. TMP86FH46ANG compares the data string specified to the password with the password string transmitted from the external controller. the area in which passwords can be specified is locat ed at addresses c000h to ff9fh. the area from ffa0h to ffffh can not be specified as the passwords area. if addresses from ffe0h through fff fh are filled with ?ffh?, the passw ords are not compared because the product is considered as a blank product. even in this case, the password count stor age addresses and password comparison start address must be specified. table 15-16 shows the password setting in the blank product and non- blank product. note 1: when addresses from ffe0h through ffffh are filled wi th ?ffh?, the product is re cognized as a blank product. note 2: the data including the same consecutive data (three or mo re bytes) can not be used as a password. (this causes a pass- word error data. TMP86FH46ANG transmits no data and enters the halt condition.) note 3: *: don?t care. note 4: when the above condition is not met, a password error oc curs. if a password error occurs , the device enters the halt con - dition without returning the error code. note 5: in the flash memory writing mode or ram loader mode, the blank product receives the intel hex format data immediately after receiving pcsa without receiving password strings. in this case, the subsequent processing is performed correctly because the blank product ignores the data exc ept the start mark (3ah ?:?) as the intel hex format data, even if the exter- nal controller transmits the dummy password string. however, if the dummy password string contains ?3ah?, it is detected as the start mark erroneously. the micr ocontroller enters the halt mode. if this causes the problem, do not transmit the dummy password strings. note 6: in the flash memory erasing mode, t he external controller must not transmit the password string for the blank product. table 15-16 password setting in the blank product and non-blank product password blank product (note 1) non-blank product pnsa (password count storage address) c000h pnsa ff9fh c000h pnsa ff9fh pcsa (password comparison start address) c000h pcsa ff9fh c000h pcsa ffa0 - n n (password count) *8 n password string setting not required (note 5) required (note 2)
page 177 TMP86FH46ANG figure 15-5 password comparison 15.10.1password string the password string transmitted from th e external controller is compared w ith the specified data in the flash memory. when the password string is not matched to the data in the flash memory, the device enters the halt condition due to the password error. 15.10.2handling of password error if a password error occurs, the device enters the halt c ondition. in this case, reset the device to reactivate the serial prom mode. 15.10.3password management during program development if a program is modified many times in the development stage, confusion may arise as to the password. therefore, it is recommended to use a fixed password in the program development stage. example :specify pnsa to f000h, and the pa ssword string to 8 bytes from address f001h (pcsa becomes f001h.) password section code abs = 0f000h db 08h : pnsa definition db ?code1234? : password string definition 08h 01h 02h 03h 04h 05h 08h f012h f107h f108h flash memory f109h f10ah f10bh f10ch uart f0h 12h f1h 07h 01h 02h 03h 04h 05h 06h 07h 08h pnsa pcsa password string 06h 07h f10dh f10eh "08h" becomes the umber of passwords 8 bytes compare example pnsa = f012h pcsa = f107h password string = 01h,02h,03h,04h,05h 06h,07h,08h rxd pin
page 178 15. serial prom mode 15.11 product id code TMP86FH46ANG 15.11product id code the product id code is the 13-byte data containing the start address and the end address of rom. table 15-17 shows the product id code format. 15.12flash memory status code the flash memory status code is the 7-byte data including the read protection status and the status of the data from ffe0h to ffffh. table 15-18 shows the flash memory status code. table 15-17 product id code format data description in the case of TMP86FH46ANG 1st start mark (3ah) 3ah 2nd the number of transfer data (10 bytes from 3rd to 12th byte) 0ah 3rd address length (2 bytes) 02h 4th reserved data 1dh 5th reserved data 00h 6th reserved data 00h 7th reserved data 00h 8th rom block count 01h 9th the first address of rom (upper byte) c0h 10th the first address of rom (lower byte) 00h 11th the end address of rom (upper byte) ffh 12th the end address of rom (lower byte) ffh 13th checksum of the transferred data (2?s compliment for the sum of 3rd through 12th bytes) 22h table 15-18 flash memory status code data description in the case of TMP86FH46ANG 1st start mark 3ah 2nd transferred data count (3rd through 6th byte) 04h 3rd status code 00h to 03h (see figure below) 4th reserved data 00h 5th reserved data 00h 6th reserved data 00h 7th checksum of the transferred data (2?s compliment for the sum of 3rd through 6th data) 3rd byte 00h 01h 02h 03h checksum 00h ffh feh fdh status code 1 76543210 rpena blank (initial value: 0000 00**)
page 179 TMP86FH46ANG some operation commands are limited by the flash memory stat us code 1. if the read pr otection is enabled, flash memory writing mode command and ram loader mode co mmand can not be executed. erase all flash memory before executing these command. note: m : the command can be executed. pass: the command can be executed with a password. : the command can not be executed. (after echoing the command back to the exter nal controller, TMP86FH46ANG st ops uart communication and enters the halt condition.) rpena flash memory read pro- tection status 0: 1: read protection is disabled. read protection is enabled. blank the status from ffe0h to ffffh. 0: 1: all data is ffh in the area from ffe0h to ffffh. the value except ffh is included in the area from ffe0h to ffffh. rpena blank flash memory writing mode ram loader mode flash memory sum output mode product id code output mode flash memory status output mode flash memory erasing mode read protec- tion setting mode chip erase sec- tor erase 00 mmmmmm 0 1 pass pass mmm pass pass 10 mmmm 11 mmm pass pass
page 180 15. serial prom mode 15.13 specifying the erasure area TMP86FH46ANG 15.13specifying the erasure area in the flash memory erasing m ode, the erasure area of the flas h memory is specified by n ? 2 byte data. the start address of an erasure area is specified by erasta, and the end address is specified by eraend. if erasta is equal to or smaller than eraend, the sector erase (erasure in 4 kbyte units) is executed. executing the sector erase while the read protection is enabled results in an infinite loop. if erasta is larger than eraend, th e chip erase (erasure of an entire flash memory area) is executed and the read protection is disabled. therefore, execute the chip erase (not sector erase) to disable the read protection. note: when the sector erase is executed for the area contai ning no flash cell, TMP86FH46ANG stops the uart commu- nication and enters the halt condition. 15.14port input control register in the serial prom mode, the input level is fixed to the all ports except p03 and p02 ports with a hardware feature to prevent overlap current to unused ports. (all port inpu ts and peripheral function inputs shared with the ports become invalid.) therefore, to access to the flash memory in the ram load er mode without uart communication, port inputs must be valid. to make port inputs valid, set the pin of the port input contro l register (spcr) to ?1?. the spcr register is not operated in the mcu mode. erasure area specification data (n ? 2 byte data) 76543210 erasta eraend erasta the start address of the erasure area 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: from 0000h from 1000h from 2000h from 3000h from 4000h from 5000h from 6000h from 7000h from 8000h from 9000h from a000h from b000h from c000h from d000h from e000h from f000h eraend the end address of the erasure area 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: to 0fffh to 1fffh to 2fffh to 3fffh to 4fffh to 5fffh to 6fffh to 7fffh to 8fffh to 9fffh to afffh to bfffh to cfffh to dfffh to efffh to ffffh
page 181 TMP86FH46ANG note 1: the spcr register can be read or written only in the seri al prom mode. when the write instruction is executed to the spcr register in the mcu mode, the port input control can not be performed. when the read instruction is executed for the spcr register in the mcu mode, read data of bit7 to 1 are unstable. note 2: all i/o ports except p03 and p02 po rts are controlled by the spcr register. port input control register spcr (0feah) 76543210 pin (initial value: **** ***0) pin port input control in the serial prom mode 0 : invalid port inputs (the input level is fixed with a hardware feature.) 1 : valid port inputs r/w
page 182 15. serial prom mode 15.15 flowchart TMP86FH46ANG 15.15flowchart start setup receive uart data receive data = 5ah adjust the baud rate (adjust the source clock to 9600 bps) no yes transmit uart data (transmit data = 5ah) receive uart data modify the baud rate based on the receive data receive data = 30h (flash memory writing mode) receive data = 60h (ram loader mode) receive uart data (intel hex format) transmit uart data (checksum of an entire area) receive uart data transmit uart data (transmit data = 60h) receive uart data (intel hex format) jump to the start address of ram program transmit uart data (checksum of an entire area) receive data = c0h (product id code output mode) transmit uart data (transmit data = c0h) flash memory write process ram write process transmit uart data (product id code) transmit uart data (echo back the baud rate modification data) verify the password (compare the receive data and flash memory data) read protection check protection disabled read protection check protection disabled infinite loop infinite loop ng protection enable ng receive data = c3h (flash memory status output mode) transmit uart data (transmit data = c3h) receive data = f0h (flash memory erasing mode) transmit uart data (transmit data = f0h) infinite loop ng chip erase (erase on entire area) transmit uart data (checksum of an entire area) receive data = fah (read protection setting mode) transmit uart data (transmit data = fah) read protection setting read protection check blank product check infinite loop ng blank product check blank product check non-blank product non-blank product ok blank product ok blank product check non-blank product ok ok blank product check non-blank product blank product protection enable blank product disable read protection blank product receive uart data receive data sector erase (block erase) upper 4 bits x 1000h to lower 4 bits x 1000h transmit uart data (checksum of the erased area) upper 4 bits > lower 4 bits transmit uart data (transmit data = 30h) transmit uart data (transmit data = 90h) receive data = 90h (flash memory sum output mode) verify the password (compare the receive data and flash memory data) transmit uart data (checksum) verify the password (compare the receive data and flash memory data) verify the password (compare the receive data and flash memory data) transmit uart data (status of the read protection and blank product) transmit uart data (transmit data = fbh) read protection check upper 4 bits < lower 4 bits protection enabled infinite loop protection disabled
page 183 TMP86FH46ANG 15.16uart timing table 15-19 uart timing-1 (vdd = 4.5 to 5.5 v, fc = 2 to 16 mhz, topr = -10 to 40c) parameter symbol clock frequency (fc) minimum required time at fc = 2 mhz at fc = 16 mhz time from matching data reception to the echo back cmeb1 approx. 930 465 s58.1 s time from baud rate modification data reception to the echo back cmeb2 approx. 980 490 s61.3 s time from operation command reception to the echo back cmeb3 approx. 800 400 s 50 s checksum calculation time cksm approx. 7864500 3.93 s 491.5 s erasure time of an entire flash memory ceall - 30 ms 30 ms erasure time for a sector of a flash memory (in 4-kbyte units) cesec - 15 ms 15 ms table 15-20 uart timing-2 (vdd = 4.5 to 5.5 v, fc = 2 to 16 mhz, topr = -10 to 40c) parameter symbol clock frequency (fc) minimum required time at fc = 2 mhz at fc = 16 mhz time from the reset release to the acceptance of start bit of rxd pin rxsup 2100 1.05 ms 131.3 ms matching data transmission interval cmtr1 28500 14.2 ms 1.78 ms time from the echo back of matching data to the acceptance of baud rate modification data cmtr2 380 190 s 23.8 s time from the echo back of baud rate modification data to the acceptance of an operation command cmtr3 650 325 s 40.6 s time from the echo back of operation command to the acceptance of password count storage addresses (upper byte) cmtr4 800 400 s50 s reset pin rxd pin rxsup (5ah) cmeb1 (5ah) cmtr2 (28h) (28h) cmeb2 cmtr3 (30h) (30h) cmeb3 cmtr4 txd pin rxd pin txd pin (5ah) (5ah) (5ah) cmtr1
page 184 15. serial prom mode 15.16 uart timing TMP86FH46ANG
page 185 TMP86FH46ANG 16. input/output circuitry 16.1 control pins the input/output circuitries of the TMP86FH46ANG control pins are shown below. note: the test pin of the TMP86FH46ANG does not have a pull-down resistor. fix the test pin at low-level. control pin i/o input/output circuitry remarks xin xout input output resonator connecting pins (high-frequency) r f = 1.2 m ? (typ.) r o = 1.5 k ? (typ.) xtin xtout input output resonator connecting pins (low-frequency) r f = 6 m ? (typ.) r o = 220 k ? (typ.) reset i/o hysteresis input pull-up resistor r in = 220 k ? (typ.) r = 1 k ? (typ.) test input without pull-down resistor r = 1 k ? (typ.) fix the test pin at low-level fc rf r o osc. enable xin xout vdd vdd fs rf r o osc. enable xtin xten xtout vdd vdd
               r vdd
page 186 16. input/output circuitry 16.2 input/output ports TMP86FH46ANG 16.2 input/output ports port i/o input/output circuitry remarks p0 i/o sink open drain output high current output hysteresis input r = 100 ? (typ.) p1 i/o tri-state i/o hysteresis input r = 100 ? (typ.) p2 i/o sink open drain output high current output hysteresis input r = 100 ? (typ.) p3 i/o tri-state i/o r = 100 ? (typ.) p4 i/o tri-state i/o high current output (nch) r = 100 ? (typ.)
 

     
   

  
 
      


 

    
   

  
 
      


 
      


page 187 TMP86FH46ANG 17. electrical characteristics 17.1 absolute maximum ratings the absolute maximum ratings are rated values which must not be exceeded during operat ion, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rati ng is exceeded, a device may break down or its performance may be degraded, causi ng it to catch fire or explode resul ting in injury to the user. thus, when designing products which include this de vice, ensure that no absolute maximu m rating value will ever be exceeded. (vss = 0 v) parameter symbol pins ratings unit supply voltage v dd -0.3 to 6.5 v input voltage v in -0.3 to v dd + 0.3 v output voltage v out1 -0.3 to v dd + 0.3 v output current (per 1 pin) i out1 p1, p3, p4 ports -1.8 ma i out2 p1, p3 ports 3.2 i out3 p0, p2, p4 ports 30 output current (total) i out1 p1, p3 ports 60 i out2 p0, p2, p4 ports 80 power dissipation [topr = 85 c] p d 250 mw soldering temperature (time) tsld 260 (10 s) c storage temperature tstg -55 to 125 operating temperature topr -40 to 85
page 188 17. electrical characteristics 17.1 absolute maximum ratings TMP86FH46ANG 17.2 recommended op erating conditions the recommended operating co nditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is us ed under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ac/dc values etc.), malfunction may occur. thus, when designing products which include this device, ensure that the r ecommended operating conditions for the device are always adhered to. 17.2.1 serial prom mode 17.2.2 mcu mode (except flas h programming or erasing) (v ss = 0 v, topr = -10 to 40 c) parameter symbol pins condition min max unit supply voltage v dd normal1, 2 modes 4.5 5.5 v input high voltage v ih1 except hysteresis input v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 input low voltage v il1 except hysteresis input v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input v dd 0.25 clock frequency fc xin, xout 2.0 16.0 mhz (v ss = 0 v, topr = -40 to 85 c) parameter symbol pins ratings min max unit supply voltage (condition 1) v dd fc = 16 mhz normal1, 2 modes idle0, 1, 2 modes 4.5 5.5 v fc = 8 mhz normal1, 2 modes idle0, 1, 2 modes 3.0 fs = 32.768 khz slow1, 2 modes sleep0, 1, 2 modes stop mode supply voltage (condition 2) (note1) fc = 8 mhz normal1, 2 modes idle0, 1, 2 modes 2.7 3.0 fs = 32.768 khz slow1, 2 modes sleep0, 1, 2 modes stop mode input high level v ih1 except hysteresis input v dd 4.5 v v dd 0.70 v dd v v ih2 hysteresis input v dd 0.75 v ih3 v dd < 4.5 v v dd 0.90 input low level v il1 except hysteresis input v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input v dd 0.25 v il3 v dd < 4.5 v v dd 0.10 clock frequency fc xin, xout v dd = 2.7 to 3.0v (note1) 1.0 8.0 mhz v dd = 3.0 to 5.5v v dd = 4.5 to 5.5v 16.0 fs xtin, xtout v dd = 2.7 to 3.0v (note1) 30.0 34.0 khz v dd = 3.0 to 5.5v note 1: when the supply voltage v dd is less than 3.0 v, the operating temperature topr must be in a range of -20 c to 85 c.
page 189 TMP86FH46ANG 17.2.3 mcu mode (flash programming or erasing) (v ss = 0 v, topr = -10 to 40 c) parameter symbol pins ratings min max unit supply voltage v dd normal1, 2 modes 4.5 5.5 v input high level v ih1 except hysteresis input v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 input low level v il1 except hysteresis input v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input v dd 0.25 clock frequency fc xin, xout 1.0 16.0 mhz
page 190 17. electrical characteristics 17.1 absolute maximum ratings TMP86FH46ANG 17.3 dc characteristics note 1: typical values show those at topr = 25 c and v dd = 5 v. note 2: input current i in1 : the current through pull-down resistor is not included. note 3: i dd does not include i ref . note 4: the supply currents of slow2 and sleep2 modes are equivalent to those of idle0, idle1 and idle2 modes. note 5: when a program is executing in the flash memory or w hen data is being read from the flash memory, the flash memory operates in an intermittent manner, causing peak curr ents in the operation current, as shown in figure 17-1. in this case, the supply current i dd (in normal1, normal2 and slow1 modes) is defined as the sum of the average peak current and mcu current. note 6: when designing the power supply, make sure that p eak currents can be supplied. in slow1 mode, the difference between the peak current and the average current becomes large. (v ss = 0 v, topr = -40 to 85 c) parameter symbol pins condition min typ. max unit hysteresis voltage v hs hysteresis input v dd = 5.5 v, v in = 5.5 v/0 v ?0.9? v input current i in1 test ??2 a i in2 sink open drain, tri?state port i in3 reset , stop input resistance r in2 reset pull?up v dd = 5.5 v, v in = 0 v 100 220 450 k ? output leakage current i lo1 sink open drain port v dd = 5.5 v, v out = 5.5 v ??2 a i lo2 tri?state port v dd = 5.5 v, v out = 5.5 v/0 v ??2 output high voltage v oh tri?state port v dd = 4.5 v, i oh = -0.7 ma 4.1 ? ? v output low voltage v ol except xout, p3, p5 v dd = 4.5 v, i ol = 1.6 ma ??0.4 output low curren i ol high current port (p3, p5 port) v dd = 4.5 v, v ol = 1.0 v ?20?ma supply current in normal1, 2 modes i dd v dd = 5.5 v v in = 5.3 v/0.2 v fc = 16 mhz fs = 32.768 khz when a program operates on flash memory (note5,6) ?12.618 ma when a program operates on ram (flsstb=0) ?6.59 supply current in idle 0, 1, 2 modes ?4.56.5 supply current in slow1 mode v dd = 3.0 v v in = 2.8 v/0.2 v fs = 32.768 khz when a program operates on flash memory (note5,6) ? 20.0 50.0 a when a program operates on ram (flsstb=0) ? 14.0 28.0 when a program operates on ram (flsstb=1) ?9.0? supply current in sleep1 mode ?5.015.0 supply current in sleep0 mode ?4.013.0 supply current in stop mode v dd = 5.5 v v in = 5.3 v/0.2 v ?0.510 peak current for slow1 mode (note5,6) i ddp-p v dd = 5.5 v ?10? ma v dd = 3.0 v ?2?
page 191 TMP86FH46ANG figure 17-1 intermittent operation of flash memory n program coutner (pc) n+1 n+2 n+3 1 machine cycle (4/fc or 4/fs) mcu current i [ma] ddp-p typ. current momentary flash current max. current sum of average momentary flash current and mcu current
page 192 17. electrical characteristics 17.1 absolute maximum ratings TMP86FH46ANG 17.4 ad characteristics note 1: the total error includes all errors except a quanitization error, and is defined as a maximum deviation from the ideal c on- version line. note 2: conversion time is defferent in recommended value by power supply voltage. note 3: the voltage to be input on the ain input pin must not exceed the range between v aref and v ss . if a voltage outside this range is input, conversion values will become unstable and conversion values of other channels will also be affected. note 4: analog reference voltage range: ? v aref = v aref - v ss note 5: when ad converter is not us ed, fix the avdd and varef pin on the v dd level. (v ss = 0.0 v, 4.5 v v dd 5.5 v, topr = -40 to 85 c) paramete symbol condition min typ. max unit analog reference voltage v aref a vdd - 1.0 ? a vdd v power supply voltage of analog control circuit a vdd v dd a vss v ss analog reference voltage range (note 4) ? v aref 3.5 ? ? analog input voltage v ain v ss ? v aref power supply current of analog refer- ence voltage i ref v dd = a vdd = v aref = 5.5 v v ss = a vss = 0.0 v ?0.61.0ma non linearity error v dd = a vdd = 5.0 v, v ss = a vss = 0.0 v v aref = 5.0 v ??2 lsb zero point error ??2 full scale error ??2 total error ??2 (v ss = 0 v, 3.0 v v dd < 4.5 v, topr = -40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd - 1.0 ? a vdd v power supply voltage of analog control circuit a vdd v dd a vss v ss analog reference voltage range (note 4) ? v aref 2.5 ? ? analog input voltage v ain v ss ? v aref power supply current of analog refer- ence voltage i ref v dd = a vdd = v aref = 4.5 v v ss = a vss = 0.0 v ?0.50.8ma non linearity error v dd = a vdd = 3.0 v v ss = a vss = 0.0 v v aref = 3.0 v ??2 lsb zero point error ??2 full scale error ??2 total error ??2 (v ss = 0 v, 2.7 v v dd < 3.0 v, topr = -20 to 85 c) (note6) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd - 0.5 ? a vdd v power supply voltage of analog control circuit a vdd v dd a vss v ss analog reference voltage range (note 4) ? v aref 2.5 ? ? analog input voltage v ain v ss ? v aref power supply current of analog refer- ence voltage i ref v dd = a vdd = v aref =2.7 v v ss = a vss = 0.0 v ?0.30.5ma non linearity error v dd = a vdd = 2.7 v v ss = a vss = 0.0 v v aref = 2.7 v ??2 lsb zero point error ??2 full scale error ??2 total error ??2
page 193 TMP86FH46ANG note 6: when the supply voltage v dd is less than 3.0 v, the operating temperature topr must be in a range of -20 c to 85 c.
page 194 17. electrical characteristics 17.6 flash characteristics TMP86FH46ANG 17.5 ac characteristics note 1: when the supply voltage v dd is less than 3.0 v, the operating temperature topr must be in a range of -20 c to 85 c. 17.6 flash characteristics 17.6.1 write characteristics (v ss = 0 v, 4.5 v v dd 5.5 v, topr = -40 to 85 c) parameter symbol condition min typ. max unit machine cycle time tcy normal1, 2 modes 0.25 ? 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep0, 1, 2 modes high-level clock pulse width t wch for external clock operation (xin input) fc = 16 mhz ? 31.25 ? ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width t wsl (v ss = 0 v, 3.0 v v dd < 4.5 v, topr = -40 to 85 c) (note1) (v ss = 0 v, 2.7 v v dd < 3.0 v, topr = -20 to 85 c) (note1) paramete symbol condition min typ. max unit machine cycle time t cy normal1, 2 modes 0.5 ? 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep0, 1, 2 modes high-level clock pulse width t wch for external clock operation (xin input) fc = 8 mhz ? 62.5 ? ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width t wsl (v ss = 0 v) paramete condition min typ. max. unit number of guaranteed writes to flash memory v ss = 0 v, topr = -10 to 40 c ? ? 100 times
page 195 TMP86FH46ANG 17.7 recommended osc illating conditions note 1: to ensure stable oscillation, the re sonator position, load capacitance, etc. must be appropriate. because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted. note 2: when using the device (oscillator) in places exposed to high elec tric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition. note 3: the product numbers and specifications of the resonators by murata manufacturing co., ltd. are subject to change. for up-to-date information, please refer to the following url: http://www.murata.com 17.8 handling precaution - the solderability test conditions for lead-free produc ts (indicated by the suffix g in product name) are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used note: the pass criteron of the above test is as follows: solderability rate until forming 95 % - when using the device (oscillator) in plac es exposed to high electric fields such as cathode-ray tubes, we recommend elec- trically shielding the package in order to maintain normal operating condition. xtin xtout (2) low-frequency oscillation xin xout c 1 c 2 (1) high-frequency oscillation c 1 c 2
page 196 17. electrical characteristics 17.8 handling precaution TMP86FH46ANG
page 197 TMP86FH46ANG 18. package dimension p-sdip42-600-1.78 unit: mm
page 198 18. package dimension TMP86FH46ANG
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