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front_end interface: if input carrier frequency: f = 1.84 mhz single internal 6 bit a/d converter qpsk demodulation input symbol frequency: fs = 1.84 msymbols/s digital nyquist root filter: - roll-off value of 0.4 digital carrier loop: - on-chip quadrature demodulator and tracking loop - lock detector - c/n indicator digital timing recovery: - internal timing error evaluation, filter and correction digital agc: - internal signal power estimation and filter - output control signal for agc (1 bit pwm) forward error correction: inner decoder: - viterbi soft decoder for convolutional codes, constraint length m=7, rate 1/2 deinterleaver block outer decoder: - reed-solomon decoder for 32 parity bytes; correction of up to 16 byte errors - block lengths: 255 - energy dispersal descrambler back_end interface: broadcast channel selection audio service component selection to mpeg decoder service component selection control: i 2 c serial bus control interface decryption: wes scheme supported description designed for world space satellites digital audio receivers, the STA002 digital receiver front-end integrates all the blocks needed to demodulate incoming digital satellite audio signals from the tuner: analog to digital converter, qpsk demodu- lator, signal power estimator, automatic gain con- trol, viterbi decoder, deinterleaver, reed-solo- mon decoder and energy dispersal descrabler. its advanced error correction functions guarantees a low error rate even with small low gain receiver antennas. additional functions include the selection of broadcast channel, service components and audio components for source decoding: - the mpeg audio bitstream is provided at the serial audio output port. - the broadcast channel is provided to the serial data output port. - the service component is provided at the sc output interface. world space encryption scheme is supported for pay programs and paging. january 2002 ? tqfp44 STA002 starman ? channel decoder 1/43
a/d qpsk lock agc tdm frame controller frame sync. tscc management prc management tdm_clk tdm viterbi de-interleaver reed solomon source decoder interface microprocessor interface scl m_clk sck d96au541c rxi rnxi sda sc mangement bc_clk bc sc data interface sdo sen scen scdo scck bc/tscc intr reset mintr bc data interface bcck bcdo bcsync bcdin pll/clock distribution fig. 1: channel decoder block diagram d97au671a 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 nrxi rxi a_vdd agc test 1 vdd 12 13 14 15 16 a_gnd m_clk gnd clk_test test 2 test 3 lock vdd sda scl gnd test 4 vdd gnd intr reset test 5 sck sen vdd mintr test 6 test 7 bcdin bcsync gnd sdo scen vdd bcdo bcck test 8 gnd vdd scck gnd test 9 scdo fig. 2: pin connection STA002 2/43
pin description type pin name type function pad description 1, 11, 12 test (1:3) i test pin cmos input pad buffer with pull-down 22 23, 25, 33, 34, 44 test (4:9) i test pin 2 agc o agc output cmos 2ma output driver 3, 14, 21, 26, 38, 40 vdd positive supply voltage 4 a_vdd analog positive supply voltage 5 rxi i if signal input analog pad buffer 6 nrxi i if signal input analog pad buffer 7 a_gnd analog ground 9 m_clk i master clock analog pad buffer with comparator 10 clk_test not connected cmos input pad buffer 13 lock o carrrier lock indicator cmos 2ma output driver 15 sda i/o data + ack cmos schmitt trigger bdir pad bufer 16 scl i serial clock cmos input pad schmitt triggered 8, 17, 19, 30, 35, 42 gnd negative supply voltage 18 intr o interrupt cmos 2ma output driver 20 reset i master reset cmos input pad buffer with pull-up 24 mintr o mpeg interrupt cmos 2ma output driver 27 sen o mpeg enable cmos 2ma output driver 28 sck o mpeg clock cmos 2ma output driver 29 sdo o mpeg bit output cmos 2ma output driver 31 bcsync o broadcast channel sync cmos 2ma output driver 32 bcdin i broadcast channel data input cmos input pad buffer 36 bcck o broadcast channel clock cmos 2ma output driver 37 bcdo o broadcast channel data output cmos 2ma output driver 39 scen o service component enable cmos 2ma output driver 41 scck o service component clock cmos 2ma output driver 43 scdo o service component data output cmos 2ma output driver note: pin 1, 11, 12 and 22 must be connected to ground in functional mode. thermal data symbol parameter value unit r th j-amb thermal resistance junction to ambient 85 c/w absolute maximum ratings symbol parameter value unit v dd power supply -0.3 to 4 v v i voltage on input pins -0.3 to v dd +0.3 v v o voltage on output pins -0.3 to v dd +0.3 v t stg storage temperature -40 to +150 c t oper operative ambient temp -20 to +85 c STA002 3/43
electrical characteristics: v dd = 3.3v 0.3v; t amb = 0 to 70c; rg = 50 w unless otherwise specified dc operating conditions symbol parameter value v dd power supply voltage 2.7 to 3.6v t j operating junction temperature -20 to 125c general interface electrical characteristics symbol parameter test condition min. typ. max. unit note i il low level input current without pull-up device v i = 0v -10 10 m a1 i ih high level input current without pull-up device v i = v dd -10 10 m a1 v esd electrostatic protection leakage < 1 m a 2000 v 2 note 1: the leakage currents are generally very small, < 1na. the value given here is a maximum that can occur after an electrostatic stress on the pin. note 2: human body model. dc electrical characteristics symbol parameter test condition min. typ. max. unit note v il low level input voltage 0.2*v dd v v ih high level input voltage 0.8*v dd v v ol low level output voltage i ol = xma 0.4v v 1, 2 v oh high level output voltage 0.85*v dd v 1, 2 note 1: takes into account 200mv voltage drop in both supply lines. note 2: x is the source/sink current under worst case conditions and is reflected in the name of the i/o cell according to the drive c apability. pull_up & pull_down characteristics symbol parameter test condition min. typ. max. unit note i pu pull-up current v i = 0v -25 -66 -125 m a1 i pu pull-up current v i = v dd 25 66 125 m a1 r pu equivalent pull-up resistance v i = 0v 50 k w r pu equivalent pull-down resistance v i = v dd 50 k w note 1: min. condition: v dd = 2.7v, 125c min process max. condition: v dd = 3.6v, -20c max. m_ clk electrical characteristics (pin number 9) symbol parameter min. typ. max. unit v il low level input voltage v dd -1.7 v v ih high level input voltage v dd -0.9 v v ref input reference voltage v dd -1.3 v power dissipation symbol parameter test condition min. typ. max. unit note pd power dissipation @ v dd = 3v m_clk = 39,0269mhz 80 mw STA002 4/43
1 44 43 test9 scdi 200 41 scck 200 200 39 sen 200 37 bcdo 200 36 bcck bcsync 200 31 200 29 sdi 200 28 sck 200 27 sen 200 24 mintr 200 18 intr agc 200 13 200 2 3 8 5 6 9 10 11 34 test8 33 test7 32 bcdin 25 test6 23 test5 22 test4 20 reset 16 scl 12 test3 15 sda 100nf 4.7 m f 4.7 m f 100nf 100nf 100nf 100nf 100nf 14 17 100nf 21 19 100nf 26 30 100nf 38 35 100nf 40 42 4 7 100nf vdd v ss v ss v ss av ss av ss av ss 4.7 m f 4.7 m f 100nf d99au1011 100nf 100nf 100nf 100nf avdd vdd vdd vdd vdd vdd vdd avdd rxi nrxi m_clk test_clk test2 test1 lock fig. 3: test circuit i ol i oh c l v ref v dd output d98au967 figure 4. test load circuit output i ol i oh c l v ref sda 5ma 100pf 3.6v other outputs 100 m a 100 m a 100pf 1.5v test load STA002 5/43
functional description the STA002 integrates all the functions needed to demodulate the signal coming from the rf fe; with reference to the block diagram (fig 1), STA002 includes the following functions: microprocessor interface data transmission from microcontroller to the de- vice takes place through the 2 wires (sda and scl) i2c bus interface. STA002 acts always as a slave in all its communications. interface to the front-end this block receives from the rf front-end the qpsk modulated signal, centered at 1.84 mhz (2nd if frequency). this signal is over sampled using the master clock and converted to digital on 6 bits in 2s complement format. the same fre- quency is also used to provide the clock signal for the qpsk demodulator block. qpsk this block is composed by: - agc1 - quadrature demodulator - carrier recovery - timing recovery - frequency sweep generator - agc2 - lock indicator - carrier to noise estimator to assure flexibility and to cover different working conditions most of the parameters of each func- tion can be programmed through the i2c inter- face. tdm demultiplexer the tdm frame is divided into 3 fields. the first is the master frame preamble (mfp) which contains the synchronisation word. the second, the time slot control channel (tscc), contains information about the organization of the prime rate channel data which follows. the third, is the data field; it contains 96 prime rate channels of 16 kbit/s each; up to 8 prime rate channels are grouped into one broadcast chan- nel. the tdm demultiplexer executes the extraction and decoding of one broadcast channel from the tdm stream, according to the instructions com- ing from the microcontroller. the decoding flow is the following: - tdm synchronization the master frame synchronization block receives the demodulated symbol stream from the qpsk demodulator and performs the alignment detect- ing the master frame preamble. the known syncronization word is also used to correct the phase ambiguity intrinsic in qpsk de- modulation. - tscc extraction the information of the prime rate channels to broadcast channels allocation are contained in the tscc field which is synchronised with the mfp. in this stage all the information related to the tscc are extracted and made available for the microcontroller via the i2c interface. - prc extraction and bc recovery this block, after the broadcast channel (bc) se- lection, performs the extraction and synchronisa- tion of the prime rate channels (prc) belonging to the selected bc. the extracted prcs are aligned and grouped into one bc data stream. - fec decoder the extracted bc is decoded using a concate- nated forward error correction approach. the fec circuitry utilizes three error correction stages: a rate 1/2 viterbi decoder, a 255x4 bytes convolutional deinterleaver and a 255/223 reed solomon decoder. the rs input blocks are 255 bytes long with 32 parity bytes. up to 16 errored bytes can be fixed in each rs block. bc demultiplexer every bc contains up to 8 service components; the service control header (sch) field contains all the information related to the organization of the service components. this stage provides the extraction of the sch from the bc. the sch is available through i2c bus to the mi- crocontroller for the selection of the desired audio service component, which is then supplied di- rectly to the mpeg source decoder via the audio service component interface. device operation 1. i 2 c bus specification the STA002 supports the i2c protocol. this pro- tocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the others as the slave. the master will always initi- ate the transfer and will provide the serial clock STA002 6/43
for synchronisation. the STA002 is always a slave device in all its communications. 1. 1 communication protocol 1.1.0 data transition or change data changes on the sda line must only occur when the scl clock is low. sda transitions while the clock is high are used to identify start or stop condition. 1.1.1 start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condi- tion must precede any command for data transfer. 1.1.2 stop condition stop is identified by low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition termi- nates communications between STA002 and the bus master. 1.1.3 acknowledge bit an acknowledge bit is used to indicate a success- ful data transfer. the bus transmitter, either mas- ter or slave, will release the sda bus after send- ing 8 bits of data. during the 9th clock pulse the receiver pulls the sda bus low to acknowledge the receipt of 8 bits of data. some registers do not give acknowledge when the data is not available. 1.1.4 data input during the data input the STA002 samples the sda signal on the rising edge of the clock scl. for correct device operation the sda signal has to be stable during the rising edge of the clock and the data can change only when the scl line is low. 1.2 device addressing to start communication between the master and the STA002, the master must initiate with a start condition. following this the master sends onto the sda line 8 bits (msb first) corresponding to the device select address and read or write mode. the 7 most significant bits are the device address identifier, corresponding to the i2c bus definition. for the STA002 these are fixed as 1101010. the 8th bit (lsb) is the read or write operation bit (rw; set to 1 in read mode and to 0 in write mode). after a start condition the STA002 identifies on the bus the device address and if matching it will acknowledges the identification on sda bus during the 9th bit time. the following 2 bytes after the device identifica- tion byte are the internal space address. 1.3 write operation (see fig. 5) following a start condition the master sends a device select code with the rw bit set to 0. the STA002 gives the acknowledge and waits for the 2 bytes of internal address. the least signifi- cant 10 bits of the 2 bytes address provides ac- cess to any of the internal registers. the most significant bit means incremental mode (1 = autoincremental, 0 = no) and the other bits are set to zero. after the receiption of each of the internal bytes address the STA002 again responds with an ac- knowledge. 1.3.1 byte write in the byte write mode the master sends one data byte and this is acknowledged by STA002. the master then terminates the transfer by generating a stop condition. 1.3.2 multibyte write the multibyte write mode can start from any inter- nal address. the master sends the data and each one is acknowledged by the STA002. the trans- fer is terminated by the master generating a stop condition. 1.4 read operation (see fig. 6) 1.4.1 current byte address read the STA002 has an internal byte address counter. each time a byte is written or read, this counter, according to the autoincremental bit set- ting, is incremented or not. for the current byte address read mode, follow- ing a start condition the master sends the de- vice address with the rw bit set to 1. the STA002 acknowledges this and outputs the byte addressed by the internal byte address counter. the counter is then incremented or not depend- ing on the autoincremental bit. the master does not acknowledge the received byte, but termi- nates the transfer with a stop condition. 1.4.2 random byte address read a dummy write is performed to load the byte ad- dress into the internal address register. STA002 7/43
this is followed by another start condition from the master and the device address repeated with the rw bit set to 1. the STA002 acknowledges this and outputs the byte addressed by the inter- nal byte address counter. the master does not acknowledge the received byte, but terminates the transfer with a stop condition. 1.4.3 sequential address read this mode can be initiated with either a current address read or a random address read. how- ever in this case the master does acknowledge the data byte output and the STA002 continues to output the next byte in sequence. to terminate the stream of bytes the master does not acknowledge the last received byte, but termi- nates the transfer with a stop condition. the output data stream is from consecutive byte addresses, with the internal byte address counter automatically incremented after each byte output. dev ack start d97au669 rw byte ack byte ack data in ack stop byte write dev ack start rw byte ack byte ack data in ack stop multibyt write data in ack fig. 5: write mode sequence dev ack start d97au670 rw data no ack stop current address read dev ack start rw byte ack byte ack dev ack stop random address read data no ack start rw dev ack start data ack data ack stop sequential current read data no ack dev ack start rw byte ack byte ack dev ack sequential random read data ack start rw data ack no ack stop data rw= high fig. 6: read mode sequence 1.5 register map (8 bit register) 1.5.1 register address list (by function) function start address end address hex_cod bin hex_cod bin sch 000h 0000000000 03fh 0000111111 rfu 040h 0000111111 07fh 0001111111 qpsk 080h 0010000000 09fh 0010011111 rfu 0a0h 0010100000 0ffh 0011111111 sch_mem 100h 0100000000 1ebh 0111101011 rfu 1ech 0111101100 1ffh 0111111111 tdm_multiplex 200h 1000000000 23fh 1000111111 rfu 240h 1001000000 2ffh 1011111111 tscc_mem 300h 1100000000 3c1h 1111000001 rfu 3c2h 1111000010 3ffh 1111111111 STA002 8/43
1.5.2 sch registers hex_cod dec_cod register name type reset value 000h 0 bri_reg & nsc_reg (note 1) r 001h 1 ec_reg (note 1) r 002h 2 afci 1_reg (note 1) r 003h 3 afci 2_reg (note 1) r 004h 4 sof_sf_reg (note 1) r 005h 5 adf1_reg (7:0) (note 1) r 006h 6 adf1_reg (15:8) (note 1) r 007h 7 adf2_reg (7:0) (note 1) r 008h 8 adf2_reg (15:8) (note 1) r 009h 9 adf2_reg (23:16) (note 1) r 00ah 10 adf2_reg (31:24) (note 1) r 00bh 11 adf2_reg (39:32) (note 1) r 00ch 12 adf2_reg (47:40) (note 1) r 00dh 13 adf2_reg (55:48) (note 1) r 00eh 14 adf2_reg (63:56) (note 1) r 00fh 15 sel_sc_reg r/w 98h 010h 16 iw_reg (7:0) (note 2) w 41h 011h 17 iw_reg (15:8) (note 2) w 42h 012h 18 iw_reg (23:16) (note 2) w 43h 013h 19 iw_reg (31:24) (note 2) w 44h 014h 20 iw_reg(39:32) (note 2) w 45h 015h 21 iw_reg (47:40) (note 2) w 46h 016h 22 iw_reg (55:48) (note 2) w 47h 017h 23 iw_reg (63:56) (note 2) w 48h 018h 24 em_reg r/w 00h 019h 25 piwe_reg (7:0) (note 2) r/w 00h 01ah 26 piwe_reg (15:8) (note 2) r/w 00h 01bh 27 bcin_delay_reg r/w 00h 01ch 28 bc_alarm_reg r/w 20h 01dh 29 test_purpose r/w 01eh 30 rfu 01fh 31 rfu 020h 32 test purpose r/w 021h 33 test purpose r/w 022h 34 test purpose r/w 023h 35 test purpose r/w 024h 36 test purpose r/w 025h 37 test purpose r/w 026h 38 test purpose r/w 027h 39 test purpose r/w 028h 40 test purpose r/w 029h 41 test purpose r/w note 1: no acknowledge when data is not available note 2: when updated all bytes must be written STA002 9/43
1.5.2 sch registers hex_cod dec_cod register name type reset value 02ah 42 test purpose r/w 02bh 43 test purpose r/w 02ch 44 test purpose r/w 02dh 45 test purpose r/w 02eh 46 test purpose r/w 02fh 47 test purpose r/w 030h 48 test purpose r/w 031h 49 test purpose r/w 032h 50 test purpose r/w 033h 51 test purpose r/w 034h 52 test purpose r/w 035h 53 test purpose r/w 036h 54 test purpose r/w 037h 55 test purpose r/w 038h 56 piw_ram (7:0) (note1) w 00h 039h 57 piw_ram (15:8) (note1) w 00h 03ah 58 piw_ram (23:16) (note1) w 00h 03bh 59 piw_ram (31:24) (note1) w 00h 03ch 60 piw_ram (39:32) (note1) w 00h 03dh 61 piw_ram (47:40) (note1) w 00h 03eh 62 piw_ram (55:48) (note1) w 00h 03fh 63 piw_ram (63:56) (note1) w 00h note 1: when updated all bytes must be written STA002 10/43
1.5.3 qpsk registers hex_cod dec_cod register name type reset value 080h 128 qpsk_control1 r/w 10h 081h 129 qpsk_control2 r/w 90h 082h 130 agc1 _ref1 (note 1) r/w 06h 083h 131 agc1 _ref2 (note 1) r/w 01h 084h 132 agc1_beta r/w 00h 085h 133 agc1_intg r/w 7fh 086h 134 agc2 _ref r/w 16h 087h 135 agc2 _beta r/w 00h 088h 136 agc2_intg r/w 23h 089h 137 cn_cnt r/w ffh 08ah 138 symfreq1 (note 1) r/w d3h 08bh 139 symfreq2 (note 1) r/w 11h 08ch 140 symfreq3 (note 1) r/w 0ch 08dh 141 timfltpar r/w 48h 08eh 142 timintg r/w 00h 08fh 143 carfltpar r/w 57h 090h 144 iffreq1 (note 1) r/w 37h 091h 145 iffreq2 (note 1) r/w 1dh 092h 146 iffreq3 (note 1) r/w c1h 093h 147 iffreq4 (note 1) r/w 00h 094h 148 carintg r/w 00h 095h 149 rampctrl r/w 01h 096h 150 carfreq1 r 097h 151 carfreq2 r 098h 152 carfreq3 r 099h 153 flag r 09ah 154 rfu 09bh 155 rfu 09ch 156 rfu 09dh 157 rfu 09eh 158 rfu 09fh 159 rfu note 1: when updated all bytes must be written STA002 11/43
1.5.4 sch_mem registers hex_cod dec_cod register name type reset value 100h 256 sc1_lenght & sc1_type r 101h 257 sc1_ec & sc1_pt r 102h 258 sc1_pt r 103h 259 language 1 r 104h 260 sc2_lenght & sc2_type r 105h 261 sc2_ec & sc2_pt r 106h 262 sc2_pt r 107h 263 language 2 r 108h 264 sc3_lenght & sc3_type r 109h 265 sc3_ec & sc3_pt r 10ah 266 sc3_pt r 10bh 267 language 3 r 10ch 268 sc4_lenght & sc4_type r 10dh 269 sc4_ec & sc4_pt r 10eh 270 sc4_pt r 10fh 271 language 4 r 110h 272 sc5_lenght & sc5_type r 111h 273 sc5_ec & sc5_pt r 112h 274 sc5_pt r 113h 275 language 5 r 114h 276 sc6_lenght & sc6_type r 115h 277 sc6_ec & sc6_pt r 116h 278 sc6_pt r 117h 279 language 6 r 118h 280 sc7_lenght & sc7_type r 119h 281 sc7_ec & sc7_pt r 11ah 282 sc7_pt r 11bh 283 language 7 r 11ch 284 sc8_lenght & sc8_type r 11dh 285 sc8_ec & sc8_pt r 11eh 286 sc8_pt r 11fh 287 language8 r 120h 288 dynamic label r 121h 289 dynamic label r 122h 290 dynamic label r 123h 291 dynamic label r 124h 292 dynamic label r 1e7h 487 dynamic label r 1e8h 488 dynamic label r 1e9h 489 dynamic label r 1eah 490 dynamic label r 1ebh 491 dynamic label r note: no acknowledge when data is not available for all the sch_mem registers STA002 12/43
1.5.5 tdm_multiplex registers hex_cod dec_cod register name type reset value 200h 512 tdm_trsh 1 r/w 4bh 201h 513 tdm_trsh 2 r/w 43h 202h 514 prc_trsh 1 r/w 2ah 203h 515 prc_trsh 2 r/w 23h 204h 516 viterbi_error_control r/w 00h 205h 517 sp_trsh 2 r/w 13h 206h 518 prc_maxdelay r/w 06h 207h 519 tdm_alarm r/w 00h 208h 520 prc_alarm r/w 00h 209h 521 bc_sel 1 (note) r/w 01h 20ah 522 bc_sel2 (note) r/w 00h 20bh 523 control r/w 00h 20ch 524 int_mask r/w 00h 20dh 525 error_ reg r/w 00h 20eh 526 status reg r 20fh 527 prc_active_reg r 210h 528 prc_ lock_reg r 211h 529 prc_delay_reg r 212h 530 rs_error_control r/w 00h 213h 531 vit_error1 r/w 214h 532 vit_error2 r/w 215h 533 rs_byte_error1 r/w 216h 534 rs_byte_error2 r/w 217h 535 rs_block_error r/w 218h 536 test_purpose r/w 219h 537 test_purpose r/w 21ah 538 test_purpose r/w 21bh 539 test_purpose r/w 21ch 540 test_purpose r/w 21dh 541 test_purpose r/w 21eh 542 pll_int_reg r/w 00h 21fh 543 test_purpose r/w 220h 544 reserved r/w 07h 221h 545 reserved r/w 1ch 222h 546 reserved r/w 4ah 223h 547 reserved r/w 03h 224h 548 reserved r/w 18h 225h 548 reserved r/w 25h 226h 550 reserved r/w 2eh 227h 551 reserved r/w 3eh 228h 552 reserved r/w 18h 229h 553 reserved r/w 0dh 22ah 554 reserved r/w 18h 22bh 555 reserved r/w 12h 22ch 556 reserved r/w 0ah 22dh 557 reserved r/w 0ch note: when updated all bytes must be written STA002 13/43
2. if interface the master clock (m_clk) is the source of all the STA002 internal timings. m_clk is internally divided to drive the a/d con- verter and to provide the clock signal for the qpsk block. the if input signal, centered at 1.84mhz, is over- sampled at a frequency f ck of m_clk/4 or m_clk/2 according to STA002 presettings. 2.1 pll this fully integrated pll includes the phase/fre- quency detector, the charge pump, the filter and the vco. the pll output frequency f ck can be selected via i 2 c interface according to the pll_int_reg. reg. name: pll_int_reg internal address: 21e h reset value : 00h type: r/w msb lsb x x b5 b4 b3 b2 b1 b0 description: pll and intr pin control register 1.5.5 tdm_multiplex registers (continued) hex_cod dec_cod register name type reset value 22eh 558 reserved r 0eh 22fh 559 reserved r 12h 230h 560 reserved r 32h 231h 561 reserved r 0ch 232h 562 reserved r 1ch 233h 563 reserved r 2fh 234h 564 reserved r 0ah 235h 565 reserved r 0bh 236h 566 reserved r 2ah 237h 567 reserved r 09h 23ch 568 test_purpose r 09h 23dh 569 test_purpose r 09h 237eh 570 test_purpose r 09h 1.5.6 tscc_mem registers hex_cod dec_cod register name type reset value 300h 768 tscw 1 (7:0) r 301h 769 tscw 1 (15:8) r 302h 770 tscw 2 (7:0) r 303h 771 tscw 2 (15:8) r 304h 772 tscw 3 (7:0) r 305h 773 tscw 3 (15:8) r 306h 774 tscw 4 (7:0) r 307h 775 tscw 4 (15:8) r 3bch 956 tscw 95 (7:0) r 3bdh 957 tscw 95 (15:8) r 3beh 958 tscw 96 (7:0) r 3bfh 959 tscw 96 (15:8) r 3c0h 960 tscw id (7:0) r 3c1h 961 tscw id (15:8) r STA002 14/43
b1 b0 pll output clock (adc input) 0 0 1 1 0 1 0 1 m_clk (pin 9) 2xm_clk (pin9) test purpose test purpose b5 b4 intr pin control 0 0 1 1 0 1 0 1 normal function (from error_reg) bc_lock signal on intr pin mfp_lock signal on intr pin prcp_all_lock on intr pin b3, b2: test purpose 2.2 a/d converter this block performs the analog to digital conver- sion of the incoming if input signal. the adc has a resolution of 6 bit and is based on the so called half flash architecture to reduce both area and power consumption. the sampling rate depends on the m_clk (mas- ter clock) frequency and on the pll presetting. 3. qpsk demodulator 3.1 quadrature demodulator the final base-band demodulation is performed in this block. the samples of the if input signal are multiplied by the sine and cosine functions to get the two in- phase (i) and quadrature (q) components of the qpsk signal. the phase ambiguity inherent in qpsk is solved in the frame synchronisation part. a programmable bit allows to multiply by -1 the quadrature component in order to accomodate qpsk modulation with another convention of ro- tation sense (this is equivalent to a permutation of i and q components). the sine and cosine functions are generated by an nco using a phase accumulator and a look- up table. 3.2. interpolator nyquist filter the i and q components are filtered by a digital nyquist root filter with the following features: separate i and q stream, fck/fsym samples per symbols; raised root cosine shape with roll-off factor of 40%; separate i and q output stream, 1 sample per symbol. this filter performs both the nyquist filter function (matched with the one in the transmission side) and the interpolation function to compute the opti- mum output sample. 3.3. timing recovery the timing loop is completely implemented digi- tally and comprises the timing detector working at symbol rate, a loop filter, the timing nco and the nyquist/interpolator filters. the loop is controlled by two parameters, al- pha_tmg and beta_tmg contained in the timfltpar register. 3.3.1 timing loop registers timing loop filter parameter register (timfltpar) internal address: 8d h reset value: 48h msb lsb b7 b6 b5 b4 b3 b2 b1 b0 alpha_tmg beta_tmg timing frequency registers (timintg) internal address: 8e h reset value: 0ah msb lsb b7 b6 b5 b4 b3 b2 b1 b0 signed number the value of this register, when the system is locked, is an image of the frequency offset. timing nco frequency setting (symfreq) internal address: 8c h 8b h 8a h reset value : 0ch 11h d3h msb lsb b23 b22 b21 b20 b19 b18 b17 b16 symfreq3 msb lsb b15 b14 b13 b12 b11 b10 b9 b8 symfreq2 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 symfreq1 this register is divided into three bytes. the lsb byte is named symfreq1, the msb is named symfreq3. STA002 15/43
the 22 bits value to be written into this register is given by: symfreq = int ? ? f sym f ck 2 22 ? ? for example if m_clk = 39,02687179mhz, fck = m_clk/4 symfreq = 790995 = (c11d3)hex which is the reset value. 3.3.2 loop equations this timing loop is a second order one. the natu- ral frequency and the damping factor may be cal- culated by the following formulas: f n = ? ``````````` k o k d b m 2 p where b is programmed by the timing register beta_tmg: b = 2 beta_tmg-14 fsym (fsym = 1.84mhz) where m is the reference value of the agc2 loop (see agc2_ref register), k d is the timing detec- tor gain and ko is the constant of the timing nco: k o = 2 p 2 22 f ck the damping factor is: x = a 2 ? ````` ` k o k d m b where a is programmed by the timing register al- pha_tmg: a = 2 alpha_tmg beta_tmg can only take value from 0 to 15; if beta_tmg is 0 the loop reduces to a first order one. alpha_tmg can take any value from 0 to 7. if both alpha_tmg and beta_tmg are 0 then the timing loop is open. the timing phase detector gain k d depends on the signal to noise ratio and is given in the follow- ing figure: (see par. 3.8 for the c/n definition) k d = 0.356 for a noise free input signal. the natural frequency and the damping factor can be rewritten as: f n = 2.064 ? ```` f ck ? `````````````` m k d 2 beta_tmg x = 0.0577 ? ```` f ck ? ````` m k d 2 beta_tmg 2 alpha_tmg table 1 gives the natural frequency and the damping factor for the nominal amplitude m = 22, k d = 0.356 and m_clk = 39.02687179mhz. in high noise conditions the value of k d may be reduced up to 25% of its nominal (noise free) value; it is recommended to start with a damping factor, calculated without noise, greater than the usual value of 0.7. 3.4. carrier recovery also the carrier recovery is completely imple- mented digitally and comprises a phase and fre- quency detector, a loop filter, a nco and a sine/cosine look-up table. the carrier nco is the local oscillator for the in- put quadrature demodulator. 3.4.1 carrier loop registers carrier loop filter parameter register (carfltpar) internal address: 8f h reset value: 57h msb lsb b7 b6 b5 b4 b3 b2 b1 b0 alpha_car beta_car 0 5 10 c/n(db) 0 0.1 0.2 0.3 (kd) d97au724 phase detector gain STA002 16/43
carrier frequency registers (carintg) internal address: 94 h reset value: 00h msb lsb b7 b6 b5 b4 b3 b2 b1 b0 signed number this register is formed by the 8 integrator msbs of the carrier loop filter. the value of this register, when the system is locked, is an image of the frequency offset. it may be read or written at any time by the micro. when written the integrator lsbs are reset. carrier nco frequency setting register (iffreq) internal address: 93 h 92 h 91 h 90 h reset value : 00h c1h 1dh 37h msb lsb b31 b30 b29 b28 b27 b26 b25 b24 iffreq4 msb lsb b23 b22 b21 b20 b19 b18 b17 b16 iffreq3 msb lsb b15 b14 b13 b12 b11 b10 b9 b8 iffreq2 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 iffreq1 this register is divided into four bytes. the lsb byte is named iffreq1, the msb is named iffreq4. the 26 bits value to be written into this register is given by: iffreq = int ? ? if f ck 2 26 ? ? for example if m_clk = 39.02687179mhz, fck = m_clk/4 iffreq = 12655927 = (c11d37) hex which is the reset value. actual carrier frequency register (carfreq) internal address: 96 h, 97 h, 98 h msb lsb b23 b22 b21 b20 b19 b18 b17 b16 car freq 3 msb lsb b15 b14 b13 b12 b11 b10 b9 b8 car freq 2 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 car freq 1 this register contains the actual carrier frequency value when the system is locked. it is divided into 3 registers: carfreq3, down to 1 (carfreq3 is the msb). this register may be read at any time and it is useful to store the value of the recovered carrier. if the system unlocks (due, to a lack of signal etc.) the carrier nco could be initialized with this value to speed-up the tracking process. 3.4.2 loop parameters like the timing loop the carrier loop is a second table 1. timing loop parameters (m= 22; k d = 0.356; m_clk = 39.02687179mhz) beta_tmg 012345678910 fn(hz) na 25 36 51 72 102 144 204 288 408 577 alpha_tmg damping factor 0 1 2 3 4 5 6 7 na na na na na na na na na 0.71 1.42 2.85 5.70 11.4 22.8 45.6 na 0.50 1.01 2.01 4.03 8.06 16.1 32.2 na 0.36 0.71 1.42 2.85 5.70 11.4 22.8 na 0.25 0.50 1.01 2.01 4.03 8.06 16.1 na 0.18 0.36 0.71 1.42 2.85 5.70 11.4 na 0.13 0.25 0.50 1.01 2.01 4.03 8.06 na 0.09 0.18 0.36 0.71 1.42 2.85 5.70 na 0.06 0.13 0.25 0.50 1.01 2.01 4.02 na 0.04 0.09 0.18 0.36 0.71 1.42 2.85 na 0.03 0.06 0.13 0.25 0.50 1.01 2.01 STA002 17/43
order system controlled by two parameters, al- pha-car and beta-car, contained in the carfltpar register. the natural frequency and the damping factor are given in the following formulas: f n = ? `````` ` m k o k d b 2 p where b is programmed by the carrier register beta_car: b = 2 beta_car-4 fsym (fsym = 1.84mhz) m is the reference value of the agc2 loop (see agc2_ref register), k d is the phase detector gain and ko is the constant of the carrier nco: k o = 2 p 2 26 f ck the damping factor is x = a 2 ? ````` mk o k d b where a is programmed by the carrier register al- pha_car: a = 2 alpha_car+6 beta_car can only take value from 0 to 15; if beta_car is 0 the loop becames a first order one. alpha_car can take any value from 0 to 9. if both alpha_car and beta_car are 0 then the loop is open. k d depends on the signal to noise ratio and is given in the figure in next column. (see par. 3.8 for c/n definition) k d = 1.26 for a noise free input signal. the natural frequency and the damping factor can be rewritten as: f n = 16.515 ? ```` f ck ? `````````````` m k d 2 beta_car x = 0.0289 ? ```` f ck 2 alpha_car ? ````` m k d 2 beta_car table 2 gives the natural frequency and the damping factor for the nominal amplitude m = 22, k d = 1.26 and m_clk = 39.02687179mhz. in presence of noise the value of k d may be re- duced of up to 60%; it is recommended to start with a damping factor, without noise, greater than the usual value of 0.7. 3.4.3 phase and frequency detector parameter the carrier phase error is calculated by the fol- lowing formula : e = i sgn(q) - q sgn(i). this value is computed (at symbol rate) if the ac- tual i and q components are greater than a pro- grammed threshold otherwise the previous value is mantained. in this way the detector outputs a dc value proportional to the frequency offset be- tween the incoming signal and the local oscillator. the threshold value may be programmed by the pfdthr parameter inside the qpsk_con- trol2 register: table 2. carrier loop parameters (m = 22; k d = 1.26; m_clk = 39.02687179mhz) beta_car 0 1 2 345678910 fn(khz) na 0.38 0.54 0.77 1.09 1.54 2.17 3.07 4.35 6.15 8.69 alpha_car damping factor 0 1 2 3 4 5 na na na na na na na 0.67 1.34 2.69 5.37 10.7 na 0.47 0.95 1.90 3.80 7.60 na 0.34 0.67 1.34 2.69 5.37 na 0.24 0.47 0.95 1.90 3.80 na 0.17 0.34 0.67 1.34 2.69 na 0.12 0.24 0.47 0.95 1.90 na 0.08 0.17 0.34 0.67 1.34 na 0.06 0.12 0.24 0.47 0.95 na 0.04 0.08 0.17 0.34 0.67 na 0.03 0.06 0.12 0.24 0.47 0 5 10 c/n(db) 0 0.6 0.8 1 (kd) 1.2 d97au725 phase detector gain STA002 18/43
qpsk_control2 register internal address: 81 h reset value: 90h msb lsb b7 b6 b5 b4 b3 b2 b1 b0 pfdthr cnthr sn the threshold value depends on the signal level at the nyquist filter output. a good value for this parameter is given by: pfdthr = 0.4 agc2ref where agc2ref is the reference value for the agc2 loop. 3.4.4 internal ramp parameter in presence of a frequency offset greater than the pull-in range of the carrier loop or in presence of low signal to noise ratio the tracking performance of the loop itself may became rather slow. to help the loop in tracking this frequency offset an internal ramp can be activated by i 2 c bus. this ramp can be switched on or off by setting the swon parameter 1 or 0 respectively. when swon=0 the output value of the ramp is null. the sweep rate can be calculated by the follow- ing formula: df dt = 2 swstep stepper + 1 f ck 2 2 26 where swstep can only take 0 and 1 values and stepper can be programmed in a range from 0 to 15. msb lsb x x b5 b4 b3 b2 b1 b0 b5 : swon; 1 = 2 ramp on; 0 = 2 ramp off b4 : swstep b3 - b0 : stepper ramp control register (rampctrl) internal address: 95 h reset value: 01h 3.5. agc1 3.5.1 agc1 control to avoid a degradation of the signal to noise ratio a constant if level is necessary at the channel decoder input. the agc1 outputs a signal to control the variable gain amplifier in the rf front-end in order to mantain a fixed level at the adc input. the input signal power (computed after the a/d conversion) is compared to a programmable threshold; the difference is scaled by the agc1beta coefficient then integrated. the result is converted into a pulse width modula- tion signal to drive the agc output pin; it may be filtered by a simple rc filter to control the gain command of a variable gain amplifier before the a to d conversion. the 8 integrator msbs (agc1_ intg register) may be read or written at any time by the micro; when written, the lsbs are reset. the integrator value is the level of the agc out- put, after low pass filtering; it gives an image of the input signal power. the sign of the loop can be controlled by the agc1chs control bit in the qpsk_control1 register in order to adapt the loop to a positive or negative slope of the variable gain amplifier. 3.5.2 registers agc1 reference level register (agc1_ref) internal address: 83 h 82h reset value : 01h 06h msb lsb xxxxxxb9b8 agc1_ref2 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 agc1_ref1 this register is divided into two bytes. the lsb byte is named agc1_ref1, the msb is named agc1_ref2. the reset value of this register (262) maintains the peak signal input level equal to the half range of the adc. agc1 integrator gain register (agc1_beta) internal address: 84 h reset value: 00h msb lsb x x x x x b2 b1 b0 agc1_beta the agc1 loop gain b agc1 is given by: b agc1 = 2 agc1_beta the parameter agc1_beta can only take values from 0 to 5. when agc1_beta is set to "111" the loop gain is null. this condition is useful to open the agc1 loop. STA002 19/43
agc1 integrator value register (agc1_intg) internal address: 85 h reset value: 00h msb lsb b7 b6 b5 b4 b3 b2 b1 b0 signed number to open the agc1 loop this register must be re- set and the agc1_beta parameter must be "111". 3.6. agc2 3.6.1 agc2 control the agc2 loop is used at the output of the nyquist / interpolator filter for power optimization in the signal bandwith. the modulus of the complex signal at the output of the nyquist filter is compared to a programma- ble threshold and then scaled by the agc2_beta coefficient and integrated. the integrated error drives two multiplier at the output of both the nyquist filters in order to man- tain constant the level signal at the demodulator output. 3.6.2 register agc2 reference level register (agc2_ref) internal address: 86 h reset value : 16 h msb lsb x x b5 b4 b3 b2 b1 b0 agc2_ref the value written in this register corresponds to the modulud of the output complex signal (i,q). agc2 integrator gain register (agc2_beta) internal address: 87 h reset value: 00h msb lsb xxxxxb2b1b0 agc2_beta the agc2 loop gain b agc2 can be controlled by this register: b agc2 = 2 agc2_beta the parameter agc2_beta can take values from 0 to 6. when agc2_beta is set to "111" the loop gain is null and the agc2 amplifier gain keeps the last value. agc2 integrator value register (agc2_intg) internal address: 88 h reset value: 00h msb lsb b7 b6 b5 b4 b3 b2 b1 b0 signed number to open the agc2 loop this register must be re- set and the agc2_beta parameter must be "111". the agc2 reference level value impacts the value of the following functions: - carrier to noise indicator; - the carrier loop; - the timing loop 3.7. lock indicator this 1 bit carrier lock flag may be read at any time. this flag is available at the chip output and can be also read by the micro in the flag register a low logic level at the lock indicator means that a qpsk signal is found.the lock indicator flag controls , internally, the ramp block. the sweep function is disable whenever a lock condition is detected. 3.8. carrier to noise indicator a register is used to estimate the carrier to noise level c/n in a range from 4 to 17db. remark: in the worldstar system the correspon- dence between c/n, eb/no (energy per net-bit to noise ratio) and eb/no| qpsk (energy per channel- bit to noise ratio) are the following: c/n = eb/no| qpsk + 3db = eb/no - 0.6db the c/n indicator may be used to optimize the antenna pointing or to give an idea of the rf si- gal quality. this is based on the measure of the scattering of the qpsk constellation: a 10 bit counter is incremented when the scattering is ex- ceeding a certain value. after a programmable time interval the 8msb of the counter are loaded in the corresponding i 2 c-bus register. the register value strongly depends on the agc2_ref parameter. 3.8.1 c/n register (cncnt) this register contains a value proportional to the signal to noise ratio at the nyquist filter output (eb/no| qpsk ). STA002 20/43
the relation between c/n and the required value (cncnt) is given in the table 3 for three agc2 reference levels. a value of 255 means overflow. 3.8.2 control register there are two parameters to control the c/n esti- mator circuit cnthr and sn located in the qpsk _control 2 register. the cnthr parameter (2 bits) sets the threshold value under which the circuit is activated. the sn parameter (2bits) sets the measure time internal. both there two parameters are given in the fol- lowing tables: cnthr threshold 00 01 10 11 8 12 16 na sn time interval in symbols 00 01 10 11 1024 4096 16384 65536 a suitable value of the threshold and time inter- val must be chosen to have a good level of confi- dence of the c/n estimate. to increase the measure accuracy is advisable to average several values. before starting the measure the cncnt register must be reset and can be read after the selected time internal. a flag bit (cnflag) is set to 1 to indicate that a value is available in the cncnt register. 3.9 control registers qpsk_control1 register internal address: 80 h reset value: 10h msb lsb x b6b5b4b3 x x x b6 : agc1chs b5 : car chs b4 :timchs b3 : qchp agc1chs changes the polarity of the agc sig- nal at output pin. carchs and timchs change the sign of the carrier tracking loop and symbol tracking loop re- spectively. qchs inverts the sign of the q component. qpsk_control2 register internal address: 81 h reset value: 90h msb lsb b7 b6 b5 b4 b3 b2 b1 b0 pfdthr cnthr sn table 3. correspondence between c/n and the cncnt register contents. c/n(db) eb/no|qpsk cnthr = 8 cnthr = 12 cnthr = 16 m = agc2_ ref 16 22 26 16 22 26 16 22 26 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 161 155 148 140 132 122 113 105 92 84 71 65 58 49 42 34 32 30 121 112 102 91 79 68 55 46 33 26 20 14 9 5 3.4 2.4 1.5 0.9 101 93 84 73 61 50 38 28 20 13 8 6 3.2 1.6 0.9 0.5 0.25 0.07 na na na na na na na na na na na na na na na na na na 177 173 168 161 155 148 141 134 125 118 112 103 93 84 77 70 66 61 151 145 138 130 120 110 100 89 79 67 57 51 40 32 27 23 19 13 na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na 193 192 190 186 184 180 177 174 170 165 161 158 154 149 144 141 137 131 the value are the average of 1000 readings of the cncnt register. STA002 21/43
this register controls the phase and frequency detector threshold (see par. 3.4.3) and the c/n indicator (see 3.8.2) flag register internal address: 99 h lock cnflag reserved this is a read only register when the lock bit is 0 then the carrier is locked. when the cnflag bit is 1 then the c/n estimation is available. 4. tdm demultiplexing 4.1 tdm_multiplex registers. reg name: tdm_trsh1 internal address: 200 h type: r/w reset value: 4bh msb lsb x b6b5b4b3b2b1b0 description: master frame preamble recognition - synchronization threshold level. definition of the minimum number of tdm pre- amble bits to be recognized before enabling the frame synchronization. reg name: tdm_trsh2 internal address: 201 h type: r/w reset value: 43h msb lsb x b6b5b4b3b2b1b0 description: master frame preamble recognition - warning flag threshold level. definition of the minimum number of tdm pre- amble bits to be recognized before setting an alarm condition. reg name: tdm_alarm internal address: 207 h type: r/w reset value: 00h msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description: tdm finite state machine control reg- ister (see table 4). reg name: prc_trsh1 internal address: 202 h type: r/w reset value: 2ah msb lsb x x b5 b4 b3 b2 b1 b0 description: prime rate channel preamble recog- nition - synchronization threshold level. definition of the minimum number of prc pre- amble bits to be recognized before enabling prc synchronization. table 4: tdm fsm active states b7 b6 b5 b4 b3 b2 b1 b0 tdm fsm active states xxxxx0 0 0mf p_detection, mfp_presync, mfp_sync,alarm 1 (1 cycle) xxxxx0 0 1mf p_detection, mfp_presync, mfp_sync,alarm 1 (2 cycle) xxxxx0 0 0mf p_detection, mfp_presync, mfp_sync,alarm 1 (3 cycle) xxxxx0 0 1mf p_detection, mfp_presync, mfp_sync,alarm 1 (4 cycle) 000001xxmf p_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (1 cycles) 000011xxmf p_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (2 cycles) -----1xxmf p_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (n cycles) 111111xxmf p_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (32 cycles) STA002 22/43
reg name: prc_trsh2 internal address: 203 h type: r/w reset value: 23h msb lsb x x b5 b4 b3 b2 b1 b0 description: prime rate channel preamble recog- nition - warning flag threshold level. it defines the minimum number of prc preamble bits to be recognized before setting an alarm con- dition. reg name: prc_alarm internal address: 208 h type: r/w reset value: 00h msb lsb b7 b6 b5 b4 x x b1 b0 description: prc finite state machine control reg- ister (see table 5). reg name: prc_active_reg internal address: 20f h type: r msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description: it gives the list of active prc within one selected bc. b0 to b7 indicates prc0 to prc7 respectively. reg name: prc_lock_reg internal address: 210 h type: r msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description: lock status of each prc b0 to b7 indicates the lock status of prc0 to prc7 respectively. reg name: prc_delay_reg internal address: 211 h type: r msb lsb x x x x b3b2b1b0 description: prc maximum number of delay symbols it detects the maximum number of delay symbols among the prc within the same bc. table 5: prc_alarm b7 b6 b5 b4 b1 b0 prc fsm active states x x x x 0 0 prcp_detection, prcp_presync, prcp_sync x x x x 0 1 prcp_detection, prcp_presync, prcp_sync, alarm 1 0 0 0 0 1 0 sp_detection, sp_presync, sp_sync, alarm2 0 0 0 1 1 0 sp_detection, sp_presync, sp_sync, alarm2 (1 cycle) 0 0 1 0 1 0 sp_detection, sp_presync, sp_sync, alarm2 (2 cycles) 0 0 1 1 1 0 sp_detection, sp_presync, sp_sync, alarm2 (3 cycles) - - - - 1 0 sp_detection, sp_presync, sp_sync, alarm2 (n cycles) 1 1 1 1 1 0 sp_detection, sp_presync, sp_sync, alarm2 (16 cycles) 0 0 0 0 1 1 sp_detection, sp_presync, sp_sync, alarm1, alarm2 0 0 0 1 1 1 sp_detection, sp_presync, sp_sync, alarm1, alarm2 (1 cycle) 0 0 1 0 1 1 sp_detection, sp_presync, sp_sync, alarm1, alarm2 (2 cycles) 0 0 1 1 1 1 sp_detection, sp_presync, sp_sync, alarm1, alarm2 (3 cycles) - - - - 1 1 sp_detection, sp_presync, sp_sync, alarm1, alarm2 (n cycles) 1 1 1 1 1 1 sp_detection, sp_presync, sp_sync, alarm1, alarm2 (16 cycles) STA002 23/43
reg name: prc_maxdelay internal address: 206 h type: r/w reset value:06h msb lsb xxxxxb2b1b0 description: maximum accepted number of de- lay symbols among the prime rate channels be- longing to the same broadcast channel. reg name: sp_trsh2 internal address: 205 h type: r/w reset value: 13h msb lsb x x x b4 b3 b2 b1 b0 description: service control header preamble rec- ognition - warning flag threshold level. definition of the minimum number of sch pre- amble bits to be recognized before enabling sch synchronization reg name: bc_sel1, bc_sel2 internal address: 209 h , 20ah type: r/w reset value: 01h, 00h bc_sel1 (lsb) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 bc_sel2 (msb) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 description: broadcast channel selection b10 ....b0: bc number selection b11: test purpose b15 ... b12 : test purpose (must be set at 0 in functional mode) 4.2 interrupt/status registers reg name: control internal address: 20bh type: r/w reset value: 00h msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description: control register b0 : software reset on b1 : software reset enable b2 : set tdm out of frame b3 : error_reg reset on read enable b4 : set prc out of frame b5 : set bc out of frame b6, b7: test purpose reg name: int_mask internal address: 20ch type: r/w reset value: 00h msb lsb x b6b5b4b3b2b1b0 description: enable/disable interrupt on intr pin b0 : sccf interrupt mask b1 : max delay alarm mask b2 : illegal address mask b3 : tdm out of frame mask b4 : rs block error mask b5 : sch interrupt mask b6 : test purpose reg name: error_reg internal address: 20dh type: r/w reset value: 00h msb lsb x b6b5b4b3b2b1b0 description: interrupt register b0 : sccf interrupt on b1 : max delay alarm on STA002 24/43
b2 : illegal address on b3 : tdm out of frame on b4 : rs block error on b5 : sch interrupt on b6 : test purpose reg name: status reg internal address: 20eh type: r reset value: 00h msb lsb x x b5 b4 b3 b2 b1 b0 description: status register: b0 : tscc available b1 : bc lock b2 : sch available b3 : prc lock b4 : mfp lock b5 : sccf available 5. viterbi decoder and synchronization a viterbi decoder has been implemented in the STA002 in order to extract the most probable transmitted sequence using a trace back proce- dure. this viterbi decoder has been realized using 64- bit trace back depth and the soft decision ap- proach on the six-bit i and q components coming from the qpsk demodulator. the convolutive codes are generated by the poly- nomials gx = 171 oct and gy = 133 oct . the viterbi decoder computes for each symbol the metrics of the four possible paths, propor- tional to the square of the euclidian distance be- tween the recived i and q and the theoretical symbol value. four logical ram banks (implemented with eight ram blocks of 32x64 bits) have been used for the path memory. the decoding latency is 256 bits. a bit error (ber) estimator has been integrated in the viterbi block. corrected data bits at viterbi output are encoded according to the transmission convolutional code so that a "good" stream is obtained. these data are compared with the data stream coming from the qpsk demodulator after having stored it into a memory buffer to compensate the viterbi la- tency. the number of wrong bits is accumulated into a register according to a given time base ex- pressed in number of bits and, assuming that the ber at the output of the viterbi decoder is negli- gible with respect to the input ber, this count can be read by the system micro controller to evalu- ate the signal quality after qpsk demodulation. the error rate measurement is programmable throught the viterbi_error_control regis- ter and the error rate is available in the registers: - vit_ error 1 - vit_ error 2 reg name: viterbi_error_control internal address: 204 h type: r/w reset value: 00h msb lsb x x x x b3b2b1b0 description: viterbi input errors measurement windows length and error mode presetting. monitor windows length (bits) b1b0 = 00 01 10 11 1024 4096 16384 65536 error measurement mode b2 = 0 single acquisition mode b2 = 1 continuous acquisition mode b3 = 0 end measurement (single /continuous acquisition ) b3 = 1 single acquisition start reg name: vit_err0r1, vit_error2 internal address: 213 h , 214h type: r/w vit_error 1 (error counter low) msb lsb a7 a6 a5 a4 a3 a2 a1 a0 vit_error 2 (error counter high) msb lsb a15 a14 a13 a12 a11 a10 a9 a8 description: viterbi error counter register STA002 25/43
6. reed solomon decoder the sta 002 performs a real time block decoding operation both on the time slot control channel (tscc) field and on the broadcast channel (bc) stream by means of a programmable reed-solo- mon (rs) decoder. this decoder works on blocks of 255 words of 8 bit symbols where the first 223 words represent the information and the last 32 the code redun- dancy. the synchrobyte is the first byte of the block. all the correction capability of the code is used so it is possible the correction of blocks containing up to 16 errors while blocks with greater number of errors are flagged as corrupted. the rs decoder is programmable to support two different galois field generator polynomials as re- quired by worldspace specifications and includes an integrated ber estimator. monitoring the number of wrong words in each block and correlating this number with the block length, it is possible, provided that no corrupted blocks are present, to get an estimation of the signal quality at the viterbi decoder output. 6.1 tscc reed solomon decoder the code generator polynomial is: g(x) = ? j = 112 143 ( x - a 11j ) over the galois field generated by x 8 +x 7 +x 2 +x+1. 6.2 broadcast channel rs decoder and descrambler. the code generator polynomial is: g(x) = (x- w ) (x- w 1 ) (...) (x- w 31 ) over the galois field generated by: x 8 +x 4 +x 3 +x 2 +1=0 6.3 energy dispersal descrambler the descrambler generator polynomial is: x 9 +x 5 +1 reg name: rs_error_control internal address: 212h type: r/w reset value: 00h msb lsb x x x x b3b2b1b0 description: reed solomon input errors measure- ment windows length and error mode presettings monitor windows length (blocks) b1b0 = 00 01 10 11 3 64 256 1024 error measurement mode b2 = 0 single acquisition mode b2 = 1 continuous acquisition mode b3 = 0 end measurement (single /continuous acquisition b3 = 1 single acquisition start reg name: rs_byte_error1, rs_byte_error2 internal address: 215 h , 216h type: r/w rs_byte_err0r1 (error counter low) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 rs_byte_error 2 (error counter high) msb lsb x x b13 b12 b11 b10 b9 b8 description: rs byte error counter register reg name: rs_block_error internal address: 217h type: r/w msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description: rs block error counter register STA002 26/43
7. broadcast channel demultiplexer 7.1 sch register reg name: bri_reg & nsc_reg internal address: 000h type: r msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description: b7 to b4 indicate the bit rate of the bc (bri field in the sch) 0000: no valid data 0001: 16kbps .............................. 1000 : 128kbps 1001 - 1111: rfu b3 = 0 b2 to b0 indicate the number of service compo- nents (nsc field in the sch) 000: one service component 001: two service component ............................................... 111: eight service component reg name: ec_reg internal address: 001h type: r msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description: b7 to b4 = 0000 b3 to b0 indicate the encryption strategy (encryp- tion control field in the sch) 0000: no encryption 0001: static key 0010: esi, common key, subscription period a 0100: esi, broadcast channel specific key for subscription period a 0101: esi, broadcast channel specific key for subscription period b else: rfu reg name: afci1_reg internal address: 002h type: r msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description : b7 to b5 = 000 b4 to b0 indicate the auxiliary field content indica- tor 1 (aci1l field in the sch) 00000: not used 00001: 16 bit encryption key selector 00010: rds pi code 00011: associated broadcast channel reference (ps flag and asp) else: rfu reg name: afci2_reg internal address: 003h type: r msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description: b7 : 0 b6 to b0 indicate the auxiliary field content indica- tor 2 (aci2 field in the sch) 00000: not used 00001:64 bit encryption key selector 00010: service label else: rfu reg name: sof_sf_reg internal address: 0041h type: r msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description: b7 to b5 = 000 b4 indicate the adf2 multiframe start flag (sf field in the sch) 1: first segment of multiframe or no multiframe 0: intermediate segment of multiframe b3 to b0 indicate the segment offset and lenght field (sft field in the sch) if sf = 1 solf con- tains the total number of multiframe segments minus 1. STA002 27/43
0000: one segment multiframe 0001: two segment multiframe ................................................. 1111: 16 segment multiframe if sf = 0 solf contains the segment offset. reg name: adf1_reg internal address: 006h, 005h type: r adf1 (15:8) ( addr 006h) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 adf1 (7:0) ( addr 005h) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description: b15 to a0 contain the auxiliary data field1 (adf1 field in the sch) with content defined by afci1_reg) reg name: adf2_reg internal address: 00eh,00dh, 00ch, 00bh, 00ah, 009h, 008h, 007h, type: r adf2(63:56) (addr 00eh) msb lsb b63 b62 b61 b60 b59 b58 b57 b56 adf2(55:48) (addr 00dh) msb lsb b55 b54 b53 b52 b51 b50 b49 b48 adf2(47:40) (addr 00ch) msb lsb b47 b46 b45 b44 b43 b42 b41 b40 adf2(39:32) (addr 00bh) msb lsb b39 b38 b37 b36 b35 b34 b33 b32 adf2(31:24) (addr 00ah) msb lsb b31 b30 b29 b28 b27 b26 b25 b24 adf2(23:16) (addr 009h) msb lsb b23 b22 b21 b20 b19 b18 b17 b16 adf2(15:8) (addr 008h) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 adf2(7:0) (addr 007h) msb lsb a7 a6 a5 a4 a3 a3 a1 a0 description: b64 to b0 contain the auxiliary data field2 (adf2 field in the sch) with content defined by afci2_reg) reg name: sel_sc_reg internal address: 00fh type: r/w msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description : b7: =1 enable service component selection a = 0 disable b6 to b4 contain the service component selec- tion a 000: sc1 001: sc2 ............... 111: sc8 b3: =1 enable service component selection b = 0 disable b2 to b0 contain the service component selec- tion b 000: sc1 001: sc2 ............... 111: sc8 STA002 28/43
reg name: piw_ ram internal address: 03f,03e, 03d, 03c, 03b, 03a, 039, 038, type: w piw_ram (63:56) (addr 03f) msb lsb b63 b62 b61 b60 b59 b58 b57 b56 piw_ram (55:48) (addr 03e) msb lsb b55 b54 b53 b52 b51 b50 b49 b48 piw_ram (47:40) (addr 03d) msb lsb b47 b46 b45 b44 b43 b42 b41 b40 piw_ram (39:32) (addr 03c) msb lsb b39 b38 b37 b36 b35 b34 b33 b32 piw_ram (31:24) (addr 03b) msb lsb b31 b30 b29 b28 b27 b26 b25 b24 piw_ram (23:16) (addr 03a) msb lsb b23 b22 b21 b20 b19 b18 b17 b16 piw_ram (15:8) (addr 039) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 piw_ram (7:0) (addr 038) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description: b63 tob0 contain the prestored initialization word 0 which is the only one downloadable by the processor. reg name: em_reg internal address: 018h type: r/w msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description : encryption mode register b7 to b1 = not used rfu b0 indicate the encryption mode (1) 1: normal encryption mode 0: enable blocking (1) for more information refer to document number wst-wsg-dds-003-500000 chipset encryption implementation specification for world space receiver reg name: piwe_reg internal address: 01ah, 019h type: r/w piwe (15:8) (addr 01ah) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 piwe (7:0) (addr 019h) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description : b15 to b0 contain the 16 bit static key selector word. each bit piwe enables a certain static key. if bit a0 of piwe is set, the static key 0 will be en- abled for read out and so forth. reg name: bcin_delay_reg internal address: 01bh type: r/w default 00h msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description : bc input delay and bc input enable register b0: enables external bc input STA002 29/43
bc input delay (bytes) b2b1 = 00 01 10 11 1 2 3 4 b3: test purpose (must be set at 0 in functional mode) b7 to b4: test purpose reg name: bc_alarm_reg internal address: 01ch type: r/w default:20h msb lsb x x b5 b4 b3 b2 b1 b0 description: bc finite state machine control regis- ter (see table 6) b5 indicates the bc synchronization mode 1: sp preamble detection 0: synch from prc reg name: iw_reg internal address: 017, 016, 015, 014, 013, 012, 011, 010, type: w iw_reg (63:56) (addr 017) msb lsb b63 b62 b61 b60 b59 b58 b57 b56 iw_reg (55:48) (addr 016) msb lsb b55 b54 b53 b52 b51 b50 b49 b48 iw_reg (47:40) (addr 015) msb lsb b47 b46 b45 b44 b43 b42 b41 b40 iw_reg (39:32) (addr 014) msb lsb b39 b38 b37 b36 b35 b34 b33 b32 iw_reg (31:24) (addr 013) msb lsb b31 b30 b29 b28 b27 b26 b25 b24 iw_reg (23:16) (addr 012) msb lsb b23 b22 b21 b20 b19 b18 b17 b16 iw_reg (15:8) (addr 011h) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 iw_reg (7:0) (addr 010h) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description: b63 to b0 contain the initialization word iw. table 6: bc_alarm_reg b4 b3 b2 b1 b0 bc fsm active states 0 0 0 0 0 sp_detection, sp_presync, sp_sync 1 0 0 0 0 sp_detection, sp_presync, sp_sync, alarm_state (1 cycle) 1 0 0 0 1 sp_detection, sp_presync, sp_sync, alarm_state (2 cycles) 1 0 0 1 0 sp_detection, sp_presync, sp_sync, alarm_state (3 cycles) 1 0 0 1 1 sp_detection, sp_presync, sp_sync, alarm_state (4 cycles) 1 - - - - sp_detection, sp_presync, sp_sync, alarm_state (n cycles) 1 1 1 1 0 sp_detection, sp_presync, sp_sync, alarm_state (15 cycles) 1 1 1 1 1 sp_detection, sp_presync, sp_sync, alarm_state (16 cycles) STA002 30/43
sch_mem registers service component control field (sccf) reg name: service component 1 internal address: 100h, 101h, 102h, 103h type: r description : contains information about the service compo- nent of the broadcast channel sc1_lenght & sc1_type (addr 100h) msb lsb b31 b30 b29 b28 b27 b26 b25 b24 sc1_ec & sc1_pt (addr 101h) msb lsb b23 b22 b21 b20 b19 b18 b17 b16 sc1_pt (addr 102h) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 language 1 (addr 103h) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 b31 to b28 = sc length bit rate of the service component divided by 8 kbps: 0000: 8 kbps 0001: 16 kbps ............... 1111: 128 kbps b27 to b24 = sc type type of service component: 0000: mpeg 0001: general data 0100:jpeg 0101: mpeg 0101: low bit rate video 1111: invalid data else: rfu b23 = encryption flag 0: not encrypted sc 1: encrypted sc b22 to b8 = program type b7 to b0 = sc language reg name: service component 2 internal address: 104h, 105h, 106h, 107h type: r description : contains information about the service compo- nent of the broadcast channel sc2 _lenght & sc2_type(addr 104h) msb lsb b31 b30 b29 b28 b27 b26 b25 b24 sc2 _ec & sc2_pt (addr 105h) msb lsb b23 b22 b21 b20 b19 b18 b17 b16 sc2_pt (addr 106h) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 language 2 (addr 107h) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 b31 to b28 = sc length bit rate of the service component divided by 8 kbps: 0000: 8 kbps 0001: 16 kbps ............... 1111: 128 kbps b27 to b24 = sc type type of service component: 0000: mpeg 0001: general data 0100:jpeg 0101: low bit rate video 1111: invalid data else: rfu b23 = encryption flag 0: not encrypted sc 1: encrypted sc b22 to b8 = program type b7 to b0 = sc language STA002 31/43
reg name: service component 3 internal address: 108h, 109h, 10ah, 10bh type: r description : contains information about the service compo- nent of the broadcast channel sc3_lenght & sc3_type (addr 108h) msb lsb b31 b30 b29 b28 b27 b26 b25 b24 sc3 _ec & sc3_pt(addr 109h) msb lsb b23 b22 b21 b20 b19 b18 b17 b16 sc3_pt (addr 10ah) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 language 3 (addr 10bh) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 b31 to b28 = sc length bit rate of the service component divided by 8 kbps: 0000: 8 kbps 0001: 16 kbps ............... 1111: 128 kbps b27 to b24 = sc type type of service component: 0000: mpeg 0001: general data 0100:jpeg 0101: low bit rate video 1111: invalid data else: rfu b23 = encryption flag 0: not encrypted sc 1: encrypted sc b22 to b8 = program type b7 to b0 = sc language reg name: service component 4 internal address: 10ch, 10dh, 10eh, 10fh type: r description : contains information about the service compo- nent of the broadcast channel sc4_lenght & sc3_type (addr 10ch) msb lsb b31 b30 b29 b28 b27 b26 b25 b24 sc4_ec & sc3_pt (addr 10dh) msb lsb b23 b22 b21 b20 b19 b18 b17 b16 sc4 _pt(addr 10eh) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 language 4 (addr 10fh) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 b31 to b28 = sc length bit rate of the service component divided by 8 kbps: 0000: 8 kbps 0001: 16 kbps ............... 1111: 128 kbps b27 to b24 = sc type type of service component: 0000: mpeg 0001: general data 0100: jpeg 0101: low bit rate video 1111: invalid data else: rfu b23 = encryption flag 0: not encrypted sc 1: encrypted sc b22 to b8 = program type b7 to b0 = sc language STA002 32/43
reg name: service component 5 internal address: 110h, 111h, 112h, 113h type: r description : contains information about the service compo- nent of the broadcast channel sc5 _lenght & sc5_type(addr 110h) msb lsb b31 b30 b29 b28 b27 b26 b25 b24 sc5_ec & sc5_pt(addr 111h) msb lsb b23 b22 b21 b20 b19 b18 b17 b16 sc5_pt (addr 112h) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 language 5(addr 113h) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 b31 to b28 = sc length bit rate of the service component divided by 8 kbps: 000: 8 kbps 001: 16 kbps ............... 1111: 128 kbps b27 to b24 = sc type type of service component: 0000: mpeg 0001: general data 0100: jpeg 0101: low bit rate video 1111: invalid data else: rfu b23 = encryption flag 0: not encrypted sc 1: encrypted sc b22 to b8 = program type b7 to b0 = sc language reg name: service component 6 internal address: 114h, 115h, 116h, 117h type: r description : contains information about the service compo- nent of the broadcast channel sc6 _lenght & sc6_type(addr 114h) msb lsb b31 b30 b29 b28 b27 b26 b25 b24 sc6 _ec & sc6_pt(addr 115h) msb lsb b23 b22 b21 b20 b19 b18 b17 b16 sc6_pt (addr 116h) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 language6 (addr 117h) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 b31 to b28 = sc length bit rate of the service component divided by 8 kbps: 0000: 8 kbps 0001: 16 kbps ............... 1111: 128 kbps b27 to b24 = sc type type of service component: 0000: mpeg 0001: general data 0100: jpeg 0101: low bit rate video 1111: invalid data else: rfu b23 = encryption flag 0: not encrypted sc 1: encrypted sc b22 to b8 = program type 7 to b0 = sc language STA002 33/43
reg name: service component 7 internal address: 118h, 119h, 11ah, 11bh type: r description : contains information about the service compo- nent of the broadcast channel sc7_lenght & sc7_type (addr 118h) msb lsb b31 b30 b29 b28 b27 b26 b25 b24 sc7 _ec & sc7_pt(addr 119h) msb lsb b23 b22 b21 b20 b19 b18 b17 b16 sc7_pt (addr 11ah) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 language7 (addr 11bh) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 b31 to b28 = sc length bit rate of the service component divided by 8 kbps: 0000: 8 kbps 0001: 16 kbps ............... 1111: 128 kbps b27 to b24 = sc type type of service component: 0000: mpeg 0001: general data 0100: jpeg 0101: low bit rate video 1111: invalid data else: rfu b23 = encryption flag 0: not encrypted sc 1: encrypted sc b22 to b8 = program type b7 to b0 = sc language reg name: service component 8 internal address: 11ch, 11dh, 11eh, 11fh type: r description : contains information about the service compo- nent of the broadcast channel sc8 _lenght & sc38_type(addr 11ch) msb lsb b31 b30 b29 b28 b27 b26 b25 b24 sc8 _ec & sc8_pt(addr 11dh) msb lsb b23 b22 b21 b20 b19 b18 b17 b16 sc8 _pt (addr 11eh) msb lsb b15 b14 b13 b12 b11 b10 b9 b8 language8 (addr 11fh) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 b31 to b28 = sc length bit rate of the service component divided by 8 kbps: 0000: 8 kbps 0001: 16 kbps ............... 1111: 128 kbps b27 to b24 = sc type type of service component: 0000: mpeg 0001: general data 0100: jpeg 0101: low bit rate video 1111: invalid data else: rfu b23 = encryption flag 0: not encrypted sc 1: encrypted sc b22 to b8 = program type b7 to b0 = sc language STA002 34/43
8. general information 8.1 decription the STA002 supports a crypto-scheme named wes (world space encrypton scheme) it is composed of two functional blocks: - csg (crypto sequence generator) implemented in the STA002 decoder - iwg (initialization word generator) processed by external hardware such as a microcontroller or a smart card. the csg module produces the pseudo-casual sequence by an algorithm based on the galois ar- rithmetic. this algorithm is derived in 2 phases: 1) key expansion 2) pseudo casual sequence generation in the expansion phase activated every frame the iwg 8 bytes key is used to initialize a 16 bytes array. the scrambling procedure, invoked every byte, implements a pseudo random algorithm. the xor operation between the output of the module the encrypted bytes completes the de- cryption procedure. the 8 bytes keyword is loaded before the start of the new frame to the i 2 c bus interface. 8.2. broadcast channel interface the broadcast channel interface consists of 4 wires: output clock (bcck), output bc data (bcdo), output bc frame sync. (bcsync) and input bc data (bcdin). the data trasmitted and recived via the broadcast channel interface are 8 bit bursts. the most significant bit is transmitted first. fig.7 shows the broadcast channel serial data out (bcdo) burst of 8 bit (msb first). the data bits are valid at the negative slope of the clock line (bcck). the bcsync signal indicates the first byte of the broadcast channel service preamble (04h) allow- ing an easy syncronization to external modules using the bc data. the input bc line (bcdi) must have the same format of the bc output (bcdo). the data bit must be valid on the negative edge of the output clock line (bcck). the maximum delay allowed from the output data and the input data is 4 bytes (4 bursts of 8 bits). the input delay is programmable via i2c bus with the bcin_delay_reg register (01bh). 8.3 service component interfaces the STA002 provides two service component in- terfaces which support the same protocol: - sc data interface (scen, scdo, scck) - source decoder interface (sen, sdo, sck) the service component interfaces consists of 3 wires each. output clock (scck/sck), sc data (scdo/sdo) and sc byte sync (scen/sen). the data transmitted via the service component interface are 8 bit bursts. the most significant bit is transmitted first. as shown in fig.8 the service component serial data out (scdo/sdo) combines burst of 8 bit length (msb first). the data bit are valid at the negative edge of the clock line (scck/ sck). the slope change of the scen/sen indicates the most significative bit of the 8 bit service compo- nent burst. the scen/sen signal is used if required for the data bits alignement only. 76543210 76543210 76543210 76543210 abcd t clk t clk-off 76543210 76543210 76543210 76543210 xyab programmable delay from bc-out data to bc-in data max 4 byte d97au744a t clk-off < 1.2ms t clk ~ 6.5 m s bcck bcdo bcsync bcdi fig. 7: format of the broadcast channel interface (bc) STA002 35/43
76543210 76543210 76543210 76543210 abcd t clk t clk-off d97au745 t clk-off < 15ms t clk ~ 6.5 m s scck/sck scdo/sdo scen/sen fig. 8: format of the service component interface channel decoder m p rf front end mpeg decoder micro interface d96au547c iic source decoder interface sck sdi sen rf interface bc data interface rxi rnxi m_clk agc lock bcck bcdo bcsync scck scdo mintr sc data interface bcdin scl sda intr reset scen channel decoder interfaces block diagram STA002 36/43
sync for mfp verification sync 2112 symbols data multiplex sch mfp ver tscc read data read tdm state machine tdm synchronisation state machine mfp detection pre sync start internal timing 251712 symbols 96 sy tdm frame 138 ms sync tscc viterbi & rs decoded tscc available i2c interface bc selection prc extraction from 1 to8 prc channels tscc data multiplex mfp tscc tscc tscc mfp data multiplex mfp data multiplex data multiplex mfp mfp data multiplex tscc mfp tscc data multiplex mfp detection mfp tscc tscc field tscc field tscc field tscc field tscc field tscc field mfp ver mfp ver data read data read data read mfp ver data read mfp ver data read mfp ver data read tscc available prcp prcp data field prc frame 432 ms mfp lock prcp detection pre sync sync all prc extracted lock mfp lock data field prc synchronisation state machine data field data field sp sp data field data field protected bc frame 432 ms prc channels multipexing data field data field sp sp viterbi & rs & deinteleaver decoded bc frame 432 ms tdec t y tx sp detection pre sync sp detection sync mfp tscc tdm synchronisation state machine case 1 normal sync case 2 hw sync sp lock sp lock bc frame sync ta frame syncronization 8.4 frame syncronization times tx = mfp detection time: 0 to 138ms ta = tscc decodification time:= < 2ms ty = prcp detection time: 0 to 432ms tdec = viterbi decoding + reed solomon error correction + deinterleaving: ~55ms x prc number tdm syncronization time tdm lock = qpsk lock + tx + 138ms prc syncronization time prc lock = qpsk lock +tdm lock + ty + 432 ms bc syncronization time case 1 ( sw sync): the bc synchronization fsm asserts the lock sig- nal when the sp is detected two consecutive times. bc lock = qpsk lock + tdm lock + ty + tdec + 432 ms case 2 ( hw sync): the bc synchronization fsm asserts the lock sig- nal when the bc frame sync signal is as- serted by the prc alignment fsm and the sp is valid. bc lock = qpsk lock + tdm lock + ty + tdec note : about the bc synchronisation, the selection be- tween sw sync and hw syn is achievable through the register bc_alarm add 01ch bit b5. bit b5 = 1 indicates the sw sync bit b5 = 0 indi- cates hw sync. STA002 37/43
20 bit bc frame 432 ms sch d ata m u lt i pl ex sp sch sch sch sp d ata m u lt i pl ex sp d ata m u lt i pl ex d ata m u lt i pl ex sp sp d ata m u lt i pl ex sch sp sch data multiplex sp sch tdm synchronisation state machine ( case 1) sp detection pre sync sync tx tdm synchronisation state machine (case 2) sp detection sync tm sp bri ec aci1 aci2 nsc adf1 adf2 sf solf sccf-1 sccf-8 d y namic labels service control data service com p onent control field sch data field service com p onent multi p lex service com p onent multi p lex data field sccf interrupt sch interrupt reset b y sw sch available sccf available tsch tsccf sch & sccf interrupt tm = sccf/ sch not available setup ~ 32 ms tsch = sch interrupt time ~ 1 3.5 ms tsccf = sccf interrupt time ~ 432 7136 bri 128 + nsc 32ms bri = bit rate index ( from 1 to 8) nsc = number of service component ( from1 to 8) 8.5 loss of sync table mpf prc bc tscc available sch available sccf available tdm out of frame unlocked unlocked unlocked not available * * prc out of frame locked unlocked unlocked available * * bc out of frame locked locked unlocked available * * control register status register tdm oof b2 prc oof b4 bc oof b5 mfp lock b4 prc lock b3 bc lock b1 tscc available b0 sch available b2 sccf available b5 0 1 0 0 0 x 1 0 0 x x 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 1 1 1 * * * 1 * * * * meaningful only if all the sync levels (mfp, prc, bc) are locked otherwise not significant STA002 38/43
8.6 i/o cell description 1) cmos output pad buffer, 2ma, with slew rate control / pins number 2, 13, 18, 24, 27, 28, 29, 31, 36, 37, 39, 41, 43 a d98au920 z output pin max load z 50pf 2) cmos schmitt trigger bidir pad buffer, 4ma, with slew rate control / pin number 10 en a d98au921 zi io input pin capacitance output pin max load io 5pf io 100pf 3) cmos schmitt trigger input pad buffer / pin number 16 a d98au923 z input pin capacitance a 3.5pf 4) cmos input pad buffer with active pull-down / pins number 11, 11, 12 a d98au923 z input pin capacitance a 3.5pf 5) cmos input pad buffer / pins number 10, 22, 23, 25, 32, 33, 34, 44 a d98au906 z output pin capacitance a 3.5pf 6) cmos input pad buffer with active pull-up / pin number 20 a d98au907 z output pin capacitance a 3.5pf STA002 39/43
i/o cell description (continued) 7) analog pad buffer / pins number 5, 6 a d98au924 z output pin capacitance a 4pf 8) m_ckl input stage / pin number 9 a d98au925 z v ref output pin total capacitance a 4pf a d98au926 z rxi nrxi comparator 1 rxi nrxi comparator 2 rxi nrxi comparator 7 bz 9) rxi/nrxi input stage / pins number 5, 6 STA002 40/43
nrxi electrical characteristics symbol parameter min. typ. max. unit note c m common mode voltage v dd -0.5 v 1 c mr common mode voltage range v dd -2 v dd -0.3 v 2 d iv differential input voltage 1v peak to peak v note 1: va = vb open circuit voltage note 2; va = vb input pin capacitance a/ai 4pf 8.7 application note (registers preset) according to the choosen m_clk frequency some registers values must be changed. table 7 shows two different presets for m_clk = 39.0268mhz and m_clk = 14.72mhz table 7: hex_cod dec_cod register name m_clk = 39.0268mhz preset m_clk = 14.72mhz preset 80h 128 qpsk_control1 38h 38h 81h 129 qpsk_control2 50h 50h 82h 130 agc1_ref1 c8h c8h 83h 131 agc1_ref2 00h 00h 84h 132 agc1_beta 05h 05h 8ah 138 sym_freq1 d3h 00h 8bh 139 sym_freq2 11h 00h 8ch 140 sym_freq_ 0ch 10h 8dh 141 tim_flt_par 44h 44h 8fh 143 car_flt_par 22h 22h 90h 144 if_freq1 37h 00h 91h 145 if_freq2 1dh 00h 92h 146 if_freq3 c1h 00h 93h 147 if_freq4 00h 01h 95h 149 ramp_ctrl 20h 20h 200h 512 tdm_trsh1 3ch 3ch 201h 513 tdm_trsh2 3ch 3ch 202h 514 prc_trsh1 20h 20h 203h 515 prc_trsh2 20h 20h 21eh 542 pll_int_reg 00h 01h 220h 544 reserved1 06h 06h 223h 547 reserved4 02h 02h STA002 41/43
STA002 42/43
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics C printed in italy C all rights reserved purchase of i 2 c components of stmicrolectronics, conveys a license under the ph ilips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. starman ? is a trademark of world-space international network inc. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states.. http://www.st.com STA002 43/43

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