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semiconductor technical data pictureinpicture (pip) controller b suffix plastic package case 859 (sdip) 56 1 order this document by MC44461/d device operating temperature range package ordering information MC44461b t j = 65 to +150 c sdip for surface mount package availability, contact your local motorola sales office or authorized distributor. 1 motorola analog ic device data
the MC44461 pictureinpicture (pip) controller is a member of motorola's low cost pip family. it is ntsc compatible and contains all the analog signal processing, control logic and memory necessary to provide for the overlay of a small picture from a second non synchronized source onto the main picture of a television. all control and setup of the MC44461 is via a standard two pin i 2 c bus interface. the device is fabricated using bicmos technology. it is available in a 56pin shrink dip (sdip) package. the main features of the MC44461 are: ? two ntsc cvbs inputs ? switchable main and pip video signals ? single ntsc cvbs output allows simple tv chassis integration ? two pip sizes; 1/16 and 1/9 screen area ? freeze field feature ? variable pip position in 64x by 64y steps ? pip border with programmable color ? programmable pip tint and saturation control ? automatic main to pip contrast balance ? vertical filter ? integrated 64 k bit dram memory resulting in minimal rfi ? minimal rfi allows simple low cost application into tv ? i 2 c bus control no external variable adjustments needed ? operates from a single 5.0 v supply ? economical 56pin shrink dip package composite video simplified system diagram video processor cv 1 pip MC44461 iic tuner/if back panel composite video input r g b cv 2 cv cv in this document contains information on a new product. specifications and information herein are subject to change without notice. ? motorola, inc. 1996 rev 0
MC44461 2 motorola analog ic device data maximum ratings rating symbol value unit power supply voltage v dd 0.5 to +6.0 v power supply voltage v cc 0.5 to +6.0 v input voltage range v ir 0.5, v dd + 0.5 v output current i o 160 ma power dissipation maximum power dissipation @ 70 c p d 1.3 w thermal resistance, junctiontoair r q ja 59 c/w junction temperature (storage and operating) t j 65 to +150 c note: esd data available upon request. electrical characteristics (v cc = v dd = 5.0 v, t a = 25 c, unless otherwise noted.) characteristic symbol min typ max unit power supply total supply (pins 8, 15, 43 and 50) total i supply 100 160 ma video composite video input (pin 34 or 36) cvi 1.0 vpp composite video output (pin 49, unterminated) 2.0 vpp video output dc level (sync tip) 1.0 vdc video gain 6.0 db video frequency response (main video to 1.0 db) 10 mhz color bar accuracy 4.0 deg video crosstalk (@ 75% color bars) db main to pip 55 pip to main 55 output impedance 5.0 w horizontal timebase free run hpll frequency (pin 16) 15734 hz hpll pullin range 400 hz hpll jitter 4.0 ns burst gate timing (from trailing edge hsync, pin 24) 1.0 m s burst gate width 4.0 m s vertical timebase vertical countdown window 232/296 h lines vertical sync integration time 31 m s analog to digital converter resolution 6 bits integral nonlinearity 1 lsb differential nonlinearity +2/1 lsb adc y frequency response @ 5.0 db 1.0 mhz adc u, v frequency response @ 5.0 db 200 khz sample clock frequency (4/3 f sc ) 4.773 mhz
MC44461 3 motorola analog ic device data electrical characteristics (continued) (v cc = v dd = 5.0 v, t a = 25 c, unless otherwise noted.) characteristic unit max typ min symbol digital to analog converter resolution 6 bits integral nonlinearity 1 lsb differential nonlinearity +2/1 lsb tint dac control range (in 64 steps) 10 deg saturation dac control range (in 64 steps) 6.0 db ntsc decoder color kill threshold 24/16 db threshold hysteresis 3.0 1.0 db acc (chroma amplitude change, +3.0 db to 12 db) 0.5 db pip characteristics pip size 1/9 screen horizontal 114 pels 1/9 screen vertical 71 lines 1/16 screen horizontal 84 pels 1/16 screen vertical 53 lines border size horizontal 3 pels border size vertical 2 lines output pel clock (4 f sc ) 14.318 mhz position control range horizontal (% of main picture), 64 steps 100 % position control range vertical (% of main picture), 64 steps 100 % figure 1. representative block diagram this device contains approximately 500,000 active transistors. y v u yuv clamp input switch low pass filter band pass filter ntsc decoder pip switch 4x s/c osc + pll 16x s/c osc + pll yuv clamp ntsc encoder 4x s/c osc + pll filter tracking 6bit adc h and v timebase digital logic memory 8.0 k x 8 dram tint dac sat dac v dac y dac 3.0 mhz lpf 3.0 mhz lpf 3.0 mhz lpf 33 y v u 40 41 42 51 28 31 1 2 3 4 5 10 30 54 53 52 47 46 6 6 6 6 6 3 6 vert 57.28 mhz 90 0 14.32 mhz 90 0 36 34 37 49 38 39 7 44 45 multiplexer video 1 video 2 decoder acc main out decoder xtal decoder pll 16 f sc pll encoder phase encoder acc sync sep h pll h in v in scl sda reset vid 1/2 sel multi test encoder clamp caps encoder xtal encoder pll decoder clamp caps adc midref filter pll u dac
MC44461 4 motorola analog ic device data 0.1 figure 2. application circuit 40 39 38 37 36 35 34 33 46 45 44 43 42 41 32 31 30 29 48 47 56 55 54 53 52 51 50 49 1 2 3 4 5 6 9 10 11 12 13 14 15 16 7 8 17 18 19 20 21 22 23 24 25 26 27 28 n/c n/c n/c n/c n/c n/c n/c n/c v ss (dig) video 1/2 select n/c n/c n/c v dd (mem) v ss (mem) n/c h in v in scl sda reset test clk 16 f sc filter v dd (dig) n/c n/c n/c sync sep decoder pll decoder y cap decoder xtal decoder acc video in 1 analog gnd video in 2 filter pll analog gnd encoder xtal encoder pll encoder acc encoder phase analog v cc decoder v cap decoder u cap n/c n/c encoder v cap encoder u cap endoder y cap n/c video out v cc video out n/c h pll multi test n/c 0.01 0.01 0.01 0.1 m f 0.1 0.01 0.01 0.01 0.01 1000 100 k 75 x3 12 5.0 v video out 5.0 v 2700 0.068 68 k 0.22 0.1 0.1 video 1 video 2 75 75 0.01 0.0068 12 k 1.0 m f 1.0 m f 5.0 v video 1/2 select out 100 1000 100 2.2 m f 470 k horiz in vert in i 2 c ser cl i 2 c ser data 5.0 v x2 14.31818 mhz fox 14320 or equivalent x3 14.31818 mhz fox 14320 or equivalent MC44461 note: for proper noise isolation, power supply pins 8, 14, 43 and 50 should be bypassed by both high and low frequency capacitors. as a guideline, a 10 m f in parallel with a 0.1 m f at each supply pin is recommended. 0.01 10 m f 5.0 v 0.01 10 m f 0.01 10 m f 10 m f x2 12 47 k 1.0 k 1.0 k 1.0 k 1.0 k 5.0 v 5.0 v
MC44461 5 motorola analog ic device data pin function description pin equivalent internal circuit description 1 1 1.0 k horizontal reference in (h in ) cmos level pulse synchronous with tv horizontal retrace signal. this pulse may be active high or low since there is a polarity selector bit in an internal control register. this pulse should begin 0.5 to 0.75 m s after the beginning of the main video h sync period. its duty cycle should be less than 50%. 2 2 1.0 k vertical reference in (v in ) cmos level pulse synchronous with tv vertical retrace signal. this pulse may be active high or low since there is a polarity selector bit in an internal control register. this pulse should begin during the main video vertical interval and have a duration of at least .5h. 3 3 1.0 k serial clock (scl) cmos level i 2 c compatible slave only clock input. 100 khz maximum frequency. 50% duty cycle. see figure 4 for timing. see i 2 c register description for internal register descriptions and addresses. 4 4 1.0 k serial data (sda) cmos level i 2 c compatible slave only data input/output. as an output it is open collector. see figure 4 for timing. see i 2 c register description for internal register descriptions and addresses. 5 5 470 k 2.2 m f 5.0 reset the active low, power on reset initializes all internal registers to zero and resets the i 2 c interface. minimum active low time required for power on reset reset is 100 ms. 6 6 47 k 5.0 test clock 7 7 100 1000 100 pll filter filter for the 16x s/c pll which is phase locked to the 4x s/c oscillator. pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. in an application, no connection should be made to these pins.
MC44461 6 motorola analog ic device data pin function description (continued) pin description equivalent internal circuit 8 14, 43, 50 9 15, 35, 48 9 8 14, 43, 50 15, 35, 48 v ss v dd m v dd an v cc vid v cc m v ss an gnd an gnd v dd , v ss the four v dd pins must be externally connected to a 5.0 v ( 5%) supply. the four v ss lines must externally connect to their respective v dd bypass return(s) to ensure that no ground disturbances occur in operation. all supplies must be properly bypassed and isolated for the application. bypass capacitors of 10 m f in parallel with 0.1 m f for each supply are recommended as a general guideline. the 0.1 m f, high frequency bypass capacitors should be placed as close to the power pins as practical. 10 10 video 1/2 select output high output level indicates that video 1 is selected to be the main picture video. low output level indicates video 2 is selected to be the main picture video. 28 28 sync out outputs the video signal selected as the pip to be filtered and applied to the h and v timebase through the sync in pin. 29 29 sync in pip sync pulses are externally filtered and applied to the h and v timebase to allow h and v synchronization. 30 30 10 k multi test under control of i 2 c bus output signals for test and adjustment are provided through this pin. 31 31 0.0068 1.0 m f 12 k h pll connection for horizontal timebase pll filter. pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. in an application, no connection should be made to these pins.
MC44461 7 motorola analog ic device data pin function description (continued) pin description equivalent internal circuit 33 33 0.1 filter pll the on board reference filter produces a phase shift which is measured and applied to an internal filter pll. this capacitor connected to this pin stores the phase correction voltage for the pll which sets the 90 phase correction reference for the rest of the on chip filters. 36 and 34 19 k 2.0 k 0.1 composite video r video input 1 and 2 accepts ac coupled 1.0 vpp composite video input usually from a source generated inside the tv and an external video source. the series coupling capacitor also functions as the storage capacitor for the clamp voltage for the input circuit. it is necessary to return the input of this capacitor to ground through a dc low impedance to enable this clamp function. r = 50 to 100 w is acceptable. 37 37 0.22 decoder acc the decoder acc pin provides access to the internal chroma decoder automatic gain control amplifier. the acc capacitor filters the feedback loop of this amplifier. during pip burst gate time a voltage proportional to the burst gate magnitude is stored on the capacitor connected to this pin to compensate for input chroma level variation and provide a constant u and v output level to the a/d conversion stage. 38 38 14.3 mhz 12 decoder crystal 4x subcarrier crystal used to synchronize the decoding of the pip uv information prior to a/d conversion, subsampling and storage in the field memory. the crystal frequency is 14.31818 mhz. 39 39 2700 0.068 68 k decoder pll connection for decoder pll filter. pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. in an application, no connection should be made to these pins.
MC44461 8 motorola analog ic device data pin function description (continued) pin description equivalent internal circuit 44 2.0 k 0.01 44 encoder phase phase difference of the main to encoded burst is sampled and applied to the capacitor connected to this pin to shift the phase of the reencoded chrominance to match the main. 45 45 0.1 encoder acc the encoder acc pin provides access to the internal chroma reference sample and hold circuit, which stores the sampled value of the main channel chroma burst amplitude on this external acc capacitor. the acc amplifier matches the chroma amplitude of the insert picture to that of the main picture. 46 46 1000 0.1 m f 100 k encoder pll connection for encoder pll filter. see separate discussion for filter values. 47 38 14.3 mhz 12 encoder crystal 4x subcarrier crystal used to synchronize the encoding of the pip yuv from the field memory with the main video. the output from this pll is phase corrected to match the pip video signal to the main video at the pip switch. the crystal frequency is 14.31818 mhz. 49 4.8 k 49 75 composite video video out the selected video 1/2 input is available at the video out mixed with the pip overlay when selected. this signal is a nominal 2.0 v peaktopeak signal unterminated. this connection is intended to drive an external series 75 w load into a 75 w termination to ground to provide a 1.0 vpp signal at the termination. pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. in an application, no connection should be made to these pins.
MC44461 9 motorola analog ic device data pin function description (continued) pin description equivalent internal circuit 54, 53, 52, 42, 41, 40 0.01 encoder and decoder yuv caps during the internal h rate clamping time the yuv reference levels are set by the charge on the capacitors attached to these pins. the nominal value of these capacitors should be 0.01 m f. pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. in an application, no connection should be made to these pins. software control of the MC44461 communications to and from the MC44461 follows the i 2 c interface protocol defined by the philips corporation. in simple terms, the i 2 c is a two line, multimaster, bidirectional bus used for data transfer. although an i 2 c system can be multimaster, the MC44461 never functions as a master. the MC44461 has a write address of $24 and a flag read address of $25. a block diagram of the i 2 c interface is shown in figure 3. writing to the MC44461 registers can cause momentary jitter or other undesirable effects to the tv screen, writing should be done only during the vertical retrace (before line 20). write to control registers a write cycle consists of three bytes, with three acknowledge bits. 1) the first byte is always the write address for the MC44461 ($24). 2) the second byte defines the subaddress register, within the MC44461, to be updated; $00 through $0b. 3) the third byte is the data for that register. the communication begins when a start sequence (data line taken low while the clock line is high) is initiated by the master (mcu) and detected by the MC44461, generating an internal reset. the first byte is then generated, and if the address is correct ($24), an acknowledge is generated by the MC44461, which tells the master to continue to send data. the second byte is then entered, followed by an acknowledge. the third byte is the operative data which is stored in the designated register, followed by the third acknowledge. writing to multiple registers in a single write operation is permitted in the MC44461. the subaddress is autoincremented while receiving n data bytes + ack, ending with the stop sequence. the subaddress of the 11 registers are at $00 through $0b. subaddress latches read/ write latch chip address latch reset start bit recognition clock counter 8bit shift register flag data 19 registers acknowledge data clock 5 6 figure 3. i 2 c bus interface and decoder
MC44461 10 motorola analog ic device data figure 4. i 2 c data transfer msb msb ack ack 12 789 12 789 s slave address r/ w a subaddress a data a p data transferred (n bytes + acknowledge) a = acknowledge s = start p = stop start condition stop condition sda scl i 2 c register descriptions base write address = 24h base read address = 25h read register there are two active bits in the single read byte available from the MC44461 as follows: write vertical indicator (wvi0) d7 when 0 indicates that the write operation specified by the last i 2 c command has been completed. pip sync detect bit (psd0) d1 when 0 indicates that the pip video h pulses are present and the horizontal timebase oscillator is within acceptable limits. write registers read start position/write start position registers subaddress = 00h write raster position start bits (wps02) d0d2 establishes the horizontal beginning of the pip and its black level measurement gate. this beginning may be varied by approximately 3.0 m s. the position of this pulse may be observed through the multi test pin 30 (see test mode register subaddress 03h). read raster position bits (rps03) d4d7 establishes the clamp gate position for the black level reference for the main picture. this position may be varied by approximately 5.0 m s. the position of this pulse may be observed through the multi test pin 30 (see test mode register subaddress 03h). pip switch delay/vertical filter register subaddress = 01h pip switch delay bits (psd03) d0d3 delays the start of pip on time relative to the pip picture. these bits are used to center the pip border and pip picture in the horizontal direction. vertical filter bit (vfon) d4 when the filter is activated (vfon = 1) a three line weighted average is taken to provide the data stored in the field memory. border color register subaddress = 02h border color bits (bc02) d0d2 these bits control the color of the border. note that when using one of the saturated border colors it is possible to get objectionable dot crawl at the edge of the border in some tvs unless appropriate comb filtering is used in the tv circuitry. bc (2:0) border color 000 black 001 white 70% 010 no border (clear) 011 no border (clear) 100 blue 101 green 110 red 111 white test mode/main vertical and horizontal polarity register subaddress = 03h internal test mode register (itm02) d0d2 sets the multi test pin output to provide one of several internal signals for test and production alignment. also controls the test memory address counter. itm (2:0) multitest i/o and function 000 input analog test mode 001 input digital test mode 010 output sync detect 011 output pip switch 100 output pip h detect 101 output pip v detect 110 output pip clamp 111 output main clamp
MC44461 11 motorola analog ic device data main vertical polarity select bit (mvp0) d6 selects polarity of active level of vertical reference input. 0 = positive going, 1 = negative going. main horizontal polarity select bit (mhp0) d7 selects polarity of active level of horizontal reference input. 0 = positive going, 1 = negative going. pip freeze/pip size/main and pip video source register subaddress = 04h pip freeze bit (stil0) d4 when set to one, the most recently received field is continuously displayed until the freeze bit is cleared. pip size bit (psi90) d5 switches the pip size between 1/16 main size (when 0) and 1/9 main size (when 1). main video source select bit (msel0) d6 selects which video input will be applied to the pip switch as the main video out. pip video source select bit (psel0) d7 selects which video input will be applied to the video decoder to provide the pip video. msel/psel function 0 video 1 input to main/ video 1 input to pip 1 video 2 input to main/ video 2 input to pip pip on/pip blank register subaddress = 05h pip on bit (pon0) d0 when on (1) turns the pip on. pip blanking bit (pbl0) d4 when on (1) sets the pip to black. if the pip is off, then it will be black if it is turned on. overrides all other settings of the pip control. pip x position register subaddress = 06h x position bits (xps05) d0d5 moves the pip start position from the left to the right edge of the display in 64 steps. there is protection circuitry to prevent the pip from interfering with the main picture sync pulses. pip y position register subaddress = 07h y position bits (yps05) d0d5 moves the pip start position from the top to the bottom edge of the display in 64 steps. there is protection circuitry to prevent the pip from interfering with the main picture sync pulses. pip chroma level register subaddress = 08h chroma (c05) d0d5 the color of the pip can be adjusted to suit viewer preference by setting the value stored in these bits. a total of 64 steps varies the color from no color to maximum. this control acts in conjunction with the auto phase control. pip tint level register subaddress = 09h tint (t05) d0d5 an auto phase control compares the main color burst to the internally generated pseudo color burst so that the tints are matched. in addition to this, the tint of the pip can be varied 10 in a total of 64 steps by changing the value of these bits to suit viewer preference. pip luma delay register subaddress = 0ah y delay (ydl02) d0d2 since the chroma passes through a bandpass filter and the color decoder, it is delayed with respect to the luma signal. therefore, to time match the luma and chroma these bits are set to a single value determined to be correct in the application. pip fill/test register subaddress = 0ch pip fill bits (pipfill01) d0d1 may be used to fill the pip with one of three selectable solid colors test register bits (intc0 and macr0) d6d7 used for production test only. function control of the MC44461 the registers of the MC44461 may be programmed via the i 2 c bus. at power up, the registers are in an undefined state. the setup value given in the register table represents a nominal start point. the setup will put a 1/9 size pip, with white borders, in the lower right corner of the screen.
MC44461 12 motorola analog ic device data i 2 c register table sub setup data bit sub address setup values d7 d6 d5 d4 d3 d2 d1 d0 00h 45h rps3 rps2 rps1 rps0 wps2 wps1 wps0 01h 1ah vfon psd3 psd2 psd1 psd0 02h 07h bc2 bc1 bc0 03h 02h mhp0 mvp0 itm2 itm1 itm0 04h 20h psel0 msel0 psi90 stil0 05h 01h pbl0 pon0 06h 34h xps5 xps4 xps3 xps2 xps1 xps0 07h 24h yps5 yps4 yps3 yps2 yps1 yps0 08h 20h c5 c4 c3 c2 c1 c0 09h 20h t5 t4 t3 t2 t1 t0 0ah 02h ydl2 ydl1 ydl0 0bh 0ch 00h circuit description the MC44461 pictureinpicture (pip) controller is composed of an analog section, logic section and an 8192 x 8bit dram array. a block diagram showing details of all of these sections is shown in the representative block diagram. the analog section includes an input switch, sync processor, filters, plls, ntsc decoder, adc, dacs, ntsc encoder and output switch. all necessary controls are provided by registers in the logic section. these registers are set by external control through the i 2 c bus. in operation, the MC44461 overlays a single pip on the main video in either a 1/9th or 1/16th size. in 1/9th, the pip is 152 samples (114 y, 19 v, 19 u) by 70 lines and occupies 8094 bytes of the 8192 byte dram. the 1/16 size is 112 samples (84 y, 14 v, 14 u) by 52 lines and occupies 4452 bytes of the dram. an extra line of data is stored for each pip size to allow for interlace disorder correction. the 6:1:1 samples are formatted by the logic section as follows in order to efficiently utilize memory: byte 1: y0(5:0), v(1:0) byte 2: y1(5:0), v(3:2) byte 3: y2(5:0), v(5:4) byte 4: y3(5:0), u(1:0) byte 5: y4(5:0), u(3:2) byte 6: y5(5:0), u(5:4) refer to the block diagram. both the video inputs are applied to an input switch which is controlled by the i 2 c bus interface. either of the inputs is applied to the pip processing circuitry and either to the main video signal path of the output switch. the signal applied to the pip processor also provides the vertical sync reference to the pip processor. the pip output from the switch is applied to a 1.0 mhz cutoff low pass gmc biquad filter to extract the luminance signal and a similar bandpass filter to pass chroma to the decoder section. these filters are tracked to a master gmc cell using subcarrier as a reference. a singleended transconductance stage with relatively large signal handling ability (>2.5 vpp @ 4.5 v v cc ) is used to avoid potential noise problems. figure 5. ntsc decoder color killer in 90 acc switching pll filter xvco/ divide mult 1 mult 2 bg h uv 0 the ntsc decoder (figure 5) consists of two multipliers, a voltage controlled 4 x s/c crystal oscillator/divider, automatic color control (acc) block, color kill circuit and necessary switching. during burst gate time, the acc block in the ntsc decoder is calibrated with respect to burst magnitude by applying the output of multiplier 1 to the reference input of the acc block. the result is u and v outputs which are 0.6 v 0.5 db for burst amplitudes varying from 12 db to 3.0 db. the second multiplier serves as a phase detector during color burst to match the 90 degree output from the xvco to the 180 degree color burst and feed
MC44461 13 motorola analog ic device data a correction current to the pll filter. the phase is correct when the two signals are 90 degrees out of phase. during the h drive time, the output of the multipliers is fed to the yuv clamp, filtered to 200 khz and input along with the y signal to the multiplexer. the yuv samples are fed through a multiplexer to a single six bit a/d converter. the a/d is a flash type architecture and is capable of digitizing at a 20 mhz sample rate. it is comprised of an internal bandgap source voltage reference, a 64 tap resistor ladder comparator array, a binary encoder and output latches. once the multiplexer has switched, sufficient time is provided to allow the a/d converter to settle before the reading is latched. the encoder code is determined from the values of any comparators which are not metastable. the multiplexer and a/d converter receive and convert the yuv data at a 4f sc /3 rate for a 1/9th size picture or f sc for a 1/16th size picture. the samples are taken in the following way to simplify the control logic: y,v,y,u,y,v,y,u to provide a 6:1:1 format, one of three u and v samples is saved to memory giving a luminance sample rate of 2f sc /3 for a 1/9th picture and f sc /2 for a 1/16 picture. in the vertical direction, one line of every 3 (1/9th picture) or 4 (1/16th picture) are saved. in order to avoid objectionable artifacts, a piecewise vertical filter is used to take a weighted average on the luminance samples. for three lines (1/9th size) the weight is 1/4 + 1/2 + 1/4 and for four lines (1/16 size) it is 1/4 + 1/4 + 1/4 + 1/4. this filter also delays the luma samples correcting for the longer chroma signal path through the decoder. finally the logic incorporates a field generator to determine the current field in order to correct interlace disorders arising from a single field memory. a separate process runs in the logic section to create the pip window on the main picture. control signals are generated and sent to the memory controller to read data from the field memory. data from the eight bit memory are then demultiplexed into a six bit yuv format, borders are added, blanking is generated for the video clamps and sent to the y, u and v dacs. since the pip display is based on a data clock, it is important to minimize the main display clock skew on a line by line basis. skew is minimized in the MC44461 by reclocking the display timebase to the nearest rising or falling edge of a 16f sc clock. this produces a maximum line to line skew of approximately 8.0 ns which is not perceptible to the viewer. the pip write logic also incorporates a field generator for use by the memory controller for interlace disorder correction. interlace disorder can occur when the line order of the two fields of the pip image is swapped due to a mismatch with the main picture field or due to an incomplete field being displayed from memory. the main and pip field generators, along with monitoring, when the pip read address passes the pip write address, allows the read address to the memory to be modified to correct for interlace disorder. the read logic can provide various border colors: black, 75% white (light gray), 50% white (medium gray), red, green, blue or transparent (no border). in a system without an adaptive comb filter, borders which contain no chroma give the best results. also built into the read logic is a pip fill mode which allows the pip window to be filled with either a solid green, blue or red color as an aid in aligning the pip analog color circuitry. because the dac output video will be referenced during back porch time, the read processor zeroes the luminance value and sets the bipolar u and v values to midrange during periods outside the pip window to ensure clamping at correct levels. since the pip window is positioned relative to the main picture's vertical and horizontal sync, a safety feature turns off the window if the window encroaches upon the sync period, thus preventing erroneous clamping. the y, u and v dacs are all three of the same design. a binary weighted current source is used, split into two, three bit levels. in the three most significant bits, the current sources are cascaded to improve the matching to the three least significant current sources. analog transmission gates, switched by the biphase outputs of the data latches, feed the binary currents to the single ended current mirror. the output current is subsequently clamped and filtered for processing buy the ntsc encoder. the outputs of the u and v dacs are buffered and burst flag pulses added to both signals. the u burst flag is fixed to generate a 180 color burst at the modulator output. the v burst flag is variable under the control of an internal register set through the i 2 c bus to provide a variable tint. saturation is controlled by varying a register which sets the reference voltage to the u and v dacs. this is also under i 2 c bus control. by oversampling the u and v dacs, it was possible to use identical postdac filtering for y, u and v, thereby reducing the delay inequalities between y and uv and also simplifying the design. after filtering, the u and v signals are clamped to an internal reference voltage during horizontal blanking periods and fed to the u and v modulators. in the ntsc decoder, the y, u and v signals were scaled to use the entire a/d range. gain through the ntsc encoder is set to properly match these amplitudes. the phase of the reencoded chrominance must match that of the incoming main video signal at the input to the pip switch, so a separate first order pll is placed within the loop of the main video signal burst pll. the first order pll compares the phase of the main burst with that of the encoded burst and moves the oscillator phase so that they match. a special phase shift circuit allowing a continuous range of 180 was developed to do this. the amplitude of the reencoded chrominance signal must also match that of the main video signal. to do this, a synchronous amplitude comparator looks at both burst signals and adjusts the chrominance amplitude in the modulator section of the ntsc encoder. the y signal from the ydac is compared to the main video signal at black level during back porch time and clamped to this same black level voltage. the pip chrominance and luminance are then added together and fed to the pip output switch through a buffered output.
MC44461 14 motorola analog ic device data b suffix plastic package case 85901 (sdip) issue o outline dimensions 51.69 13.72 3.94 0.36 0.81 0.20 2.92 0 0.51 52.45 14.22 5.08 0.56 1.17 0.38 3.43 15 1.02 millimeters 2.035 0.540 0.155 0.014 0.032 0.008 0.115 0 0.020 2.065 0.560 0.200 0.022 0.046 0.015 0.135 15 0.040 -t- seating plane c d 56 pl e f j 56 pl k m g n 128 56 29 notes: 1. dimensions and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimensions a and b do not include mold flash. maximum mold flash 0.25 (0.010). min min max max inches dim a b c d e f g h j k l m n 15.24 bsc 0.600 bsc 1.778 bsc 7.62 bsc 0.070 bsc 0.300 bsc 0.89 bsc 0.035 bsc l h -a- -b- 0.25 (0.010) t a m s 0.25 (0.010) t b m s
MC44461 15 motorola analog ic device data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer.
MC44461 16 motorola analog ic device data how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 20912; phoenix, arizona 85036. 18004412447 or 6023035454 3142 tatsumi kotoku, tokyo 135, japan. 038135218315 mfax : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 MC44461/d ?

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