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TC9444F 2002-01-11 1 toshiba cmos digital integrated circuit silicon monolithic TC9444F single-chip karaoke ic ii the TC9444F is a karaoke chip for such applications as equipment for cd/ld players, mini component stereo sets, radio-cassette players, and vtrs. with its internal ad/da converter system, the TC9444F can offer such karaoke functions as echo, vocal canceling, and key control on a single chip in addition to such digital signal processing (dsp) features as sound field control and bass/treble control. because the program and coefficients are stored on internal rom, the ic can be controlled by simple settings. features incorporates an ad converter (three channels) with 2 times oversampling. thd: ? 65db s/n ratio: 80db (typ.) built-in pre-filter op-amp incorporates a 1 -bit ? -type da converter (two channels). thd: ? 86db s/n ratio: 93db (typ.) built-in tertiary analog post filter supports one port for digital input and one for digital output. incorporates 64 kbits of delay ram microcontroller interface: i 2 c bus mode as well as toshiba?s original three-lead mode built-in boot rom initializes coefficients at reset or via a boot command. [compatible software] microphone echo: variable delay time/level vocal cancellation: attenuates only vocals from standard source vocal change: vocals fade in/out depending on whether there is input from microphone vocal key control: for chorus and duet functions supports multi-sound sources: various modes pseudo stereo: monaural sources enhanced by sense of spaciousness key control: 1 4-step (max 1 octave) stereo key control compressor or bass boost: compression ratio selectable in range 6 to 36db. compression effect (amount of boost) can be varied smoothly. sound field control: uses delay ram to simulate such acoustic environments as churches, halls, sports stadiums, and discos. equalizer: characteristics switchable by coefficient or i/f bit settings 3d sound field: offers 3-d sound. weight: 1.08 g (typ.)
TC9444F 2002-01-11 2 block diagram/pin assignment aout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 60 exto exte extf gndl v dl v da1 lpfo1 mici vra1 ail lpfo2 vra2 lpfo3 ai r gnda1 lrcki bcki sdi lrcko bcko sdo v dd1 mcko mcks cks ext6 ext5 ext4 ext3 ext2 extc extb exta ext9 ext8 ext7 gndd2 59 58 57 56 55 54 48 test emp sda scl cs ifsel reset v dd2 49 50 51 52 53 46 47 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 28 27 30 29 26 25 24 23 22 21 20 18 17 19 aol vrl vr r ao r gnda r dz v da2 xo v d x gnd x xi ext0 gndd1 ext1 16 gndal analog post filter 2-ch 1 bit dac digital filter and -type modulator analog post filter 16-bit ad converter (three shared channels) 1/2 decimation filter multiplier/adder data ram key control 2 com- pressor selector coefficient rom timing gene. coefficient-offset ram boot rom program rom data i/o microcontroller interface 64 kbit dram 4096 w 16 b
TC9444F 2002-01-11 3 pin descriptions pin no. pin name i/o function remarks 1 exto o extended output port d 2 exte o extended output port e 3 extf o extended output port f 4 gndl dram ground 5 v dl dram power supply 6 v da1 adc power supply 7 lpfo1 o op-amp output for microphone input 8 mici i op-amp input for microphone input 9 vra1 adc reference voltage 1 10 ail i op-amp input for line l-channel 11 lpfo2 o op-amp output for line l-channel 12 vra2 adc reference voltage 2 13 lpfo3 o op-amp output for line r-channel 14 air i op-amp input for line r-channel 15 gnda1 adc ground 16 gndal dac l-channel ground 17 aol o dac l-channel output 18 vrl dac reference voltage 19 v da2 dac power supply 20 vrr dac reference voltage 21 aor o dac r-channel output 22 gndar dac r-channel ground 23 dz o digital zero input detection (?h? zero detection) 24 v dx oscillator block power supply 25 xo o oscillator connection 26 xi i oscillator connection or clock input 27 gndx oscillator block ground 28 gndd1 digital ground 1 29 ext0 o extended output port 0 30 ext1 o extended output port 1 31 ext2 o extended output port 2 32 ext3 o extended output port 3 33 ext4 o extended output port 4 34 ext5 o extended output port 5 35 ext6 o extended output port 6 36 cks i system clock selection (?h? 512 fs, ?l? 384 fs) schmitt input 37 mcks i mcko output clock selection (?h? 1/1, ?l? 1/2 divider) schmitt input 38 mcko o system clock output 39 v dd1 digital power supply 1 40 sdo o digital audio data output 41 bcko o bit clock output 42 lrcko o channel clock output 43 sdi i digital audio data input schmitt input
TC9444F 2002-01-11 4 pin no. pin name i/o function remarks 44 bcki i bit clock input schmitt input 45 lrcki i channel clock input schmitt input 46 v dd2 digital power supply 2 47 reset i (u) reset (?l? reset) with pull-up resistor schmitt input 48 ifsel i microcontroller interface selection (?h? three-lead mode, ?l? i 2 c mode) schmitt input 49 cs i three-lead mode: command send start signal i 2 c: chip select schmitt input 50 scl i microcontroller interface serial clock schmitt input 51 sda o microcontroller interface serial data schmitt input 52 emp de-emphasis setting (?h? on) schmitt input 53 test i (u) test mode setting (?h? fixed) with pull-up resistor schmitt input 54 gndd2 i digital ground 2 55 ext7 o extended output port 7 56 ext8 o extended output port 8 57 ext9 o extended output port 9 58 exta o extended output port a 59 extb o extended output port b 60 extc o extended output port c
TC9444F 2002-01-11 5 block operations 1. operating clocks the master clock can be selected between 5 1 2 or 384 fs using the cks pin. the master clock uses oscillator or external clock input, through the xi pin. regardless of a master clock, the number of digital signal processing steps are predetermined. however, the da converter?s operating clock varies according to the master clock mode. the mcks pin sets the mcko output, selecting 1 / 1 or 1 /2 divider of the xi pin. table 1.1 operating clock selection and da converter oversampling rate cks pin mcks pin xi input mcko output dac oversampling rate l 192 fs l h 384 fs 384 fs 192 fs l 256 fs h h 512 fs 512 fs 256 fs 2. digital audio data input/output 2.1 sync mode the data input/output bit clock and internal sync (master) mode or external sync (slave) mode are set using microcontroller interface bits synm 1 and synm2. initialization by reset sets master mode. table 2.1 sync mode and input/output bit clock settings synm2 synm1 sync mode bcki bcko 0 0 master (note 1) 64 fs (note 2) 0 1 slave 32 fs bcki 1 0 slave 48 fs bcki 1 1 slave 64 fs bcki note 1: see table 2.2. note 2: xi input divider clock
TC9444F 2002-01-11 6 2.2 data input formats table 2.2 and figure 2. 1 show the data input formats. microcontroller interface bits ibit 1 , ibit2, and ibit3 select the format. in master mode, the bcki clock rate varies through the range shown in 2.2. in slave mode, the bcki input clock is directly output through the ic internal buffer as the data output bit clock (bcko). therefore, when using the digital data output, input the clock shown in table 2.2. the iis-compatible format can accept up to 24 bits of data. when inputting data shorter than 24 bits, fix the lower bits to 0. table 2.2 data input formats synm2 synm1 ibit3 ibit2 ibit1 format bcki 0 0 0 0 0 msb first, right-justified mode, 16-bit data 32 fs to 128 fs 0 0 0 0 1 msb first, right-justified mode, 18-bit data 36 fs to 128 fs 0 0 0 1 0 msb first, right-justified mode, 20-bit data 40 fs to 128 fs 0 0 0 1 1 msb first, right-justified mode, 24-bit data 48 fs to 128 fs 0 0 1 0 0 master mode iis-compatible, 24 bits 64 fs 0 1 0 0 0 msb first, right-justified mode, 16-bit data 32 fs 0 1 0 0 1 prohibited 32 fs 0 1 0 1 0 prohibited 32 fs 0 1 0 1 1 prohibited 32 fs 0 1 1 0 0 iis-compatible, 16 bits 32 fs 1 0 0 0 0 msb first, right-justified mode, 16-bit data 48 fs 1 0 0 0 1 msb first, right-justified mode, 18-bit data 48 fs 1 0 0 1 0 msb first, right-justified mode, 20-bit data 48 fs 1 0 0 1 1 msb first, right-justified mode, 24-bit data 48 fs 1 0 1 0 0 iis-compatible, 24 bits 48 fs 1 1 0 0 0 msb first, right-justified mode, 16-bit data 64 fs 1 1 0 0 1 msb first, right-justified mode, 18-bit data 64 fs 1 1 0 1 0 msb first, right-justified mode, 20-bit data 64 fs 1 1 0 1 1 msb first, right-justified mode, 24-bit data 64 fs 1 1 1 0 0 slave mode iis-compatible, 24 bits 64 fs
TC9444F 2002-01-11 7 the microcontroller interface rls bit controls the polarity of the input/output channel clock (lrcki, lrcko). table 2.3 channel clock polarity rls operation 0 l-channel data input/output when lrcki and lrcko ?h? 1 l-channel data input/output when lrcki and lrcko ?l? figure 2.1 data input formats (bck 64 fs) a) (ibit3, ibit2, ibit1) (0, 0, 0): msb first, right-justified mode, 16-bit data lsb 0 lsb 0 msb 15 lsb 0 msb 15 sdi lrcki bcki lsb 0 lsb 0 msb 17 lsb 0 msb 17 sdi lrcki bcki lsb 0 lsb 0 msb 19 lsb 0 msb 19 sdi lrcki bcki lsb 0 lsb 0 msb 23 lsb 0 msb 23 sdi lrcki bcki msb 23 lsb 0 msb 23 lsb 0 msb 23 sdi lrcki bcki b) (ibit3, ibit2, ibit1) (0, 0, 1): msb first, right-justified mode, 18-bit data c) (ibit3, ibit2, ibit1) (0, 1, 0): msb first, right-justified mode, 20-bit data d) (ibit3, ibit2, ibit1) (0, 1, 1): msb first, right-justified mode, 24-bit data e) (ibit3, ibit2, ibit1) (1, 0, 0): iis-compatible, 24 bits max note 3: in either mode, sections where ?sdi? is omitted are don?t care (no internal data loading).
TC9444F 2002-01-11 8 2.3 zero data detection function common to l/r the TC9444F incorporates a function to output a zero detection flag from the dz pin when input data contain a string of digital zeros. this is used to forcibly mute the analog output. table 2.4 shows the time that elapses until data are detected as zero data. if digital zeros continue to be output during this period, a zero detection flag is set. moreover, setting the dzinh bit in the microcontroller interface mode command to ?h? halts zero detection, fixing the dz pin to ?l? and disabling the zero detection function (see the microcontroller interface section below). table 2.4 digital zero data detection time fs 32 khz 44.1 khz 48 khz detection time 1024 ms 743 ms 683 ms a reset sets the dz signal to ?h?. 2.4 data output formats table 2.5 and figure 2.2 show the data output formats. microcontroller interface bits obit 1 and obit2 select the format. in master mode, the bcki clock rate varies through the range shown in table 2.2. note, however, that bcko is fixed to 64 fs. in slave mode, the bcki input clock is directly output as the data output bit clock (bcko) through the ic internal buffer (see section 2.2). table 2.5 data output formats synm2 synm1 ibit2 ibit1 format bcki 0 0 0 0 msb first, right-justified mode, 16-bit data 64 fs 0 0 0 1 msb first, right-justified mode, 20-bit data 64 fs 0 0 1 0 msb first, right-justified mode, 24-bit data 64 fs 0 0 1 1 master mode iis-compatible, 24 bits 64 fs 0 1 0 0 msb first, right-justified mode, 16-bit data 32 fs ( bcki) 0 1 0 1 prohibited 32 fs ( bcki) 0 1 1 0 prohibited 32 fs ( bcki) 0 1 1 1 iis-compatible, 16 bits 32 fs ( bcki) 1 0 0 0 msb first, right-justified mode, 16-bit data 48 fs ( bcki) 1 0 0 1 msb first, right-justified mode, 20-bit data 48 fs ( bcki) 1 0 1 0 msb first, right-justified mode, 24-bit data 48 fs ( bcki) 1 0 1 1 iis-compatible, 24 bits 48 fs ( bcki) 1 1 0 0 msb first, right-justified mode, 16-bit data 64 fs ( bcki) 1 1 0 1 msb first, right-justified mode, 20-bit data 64 fs ( bcki) 1 1 1 0 msb first, right-justified mode, 24-bit data 64 fs ( bcki) 1 1 1 1 slave mode iis-compatible, 24 bits 64 fs ( bcki)
TC9444F 2002-01-11 9 (synm2, 1) (0, 0) or (1, 1) bcko 64 fs (synm2, 1) (1, 0) bcko 48 fs (synm2, 1) (0, 1) bcko 32 fs a) (obit2, obit1) (0, 0): msb first, right-justified mode, 16-bit data lsb 0 lsb 0 msb 15 lsb 0 msb 15 sdo lrcko bcko lsb 0 lsb 0 msb 19 lsb 0 msb 19 sdo lsb 0 lsb 0 msb 23 lsb 0 msb 23 sdo msb 23 lsb 0 msb 23 lsb 0 23 sdo b) (oibit2, obit1) (0, 1): msb first, right-justified mode, 20-bit data c) (obit2, obit1) (1, 0): msb first, right-justified mode, 24-bit data d) (obit2, obit1) (1, 1): iis-compatible, 24 bits max msb lsb 0 lsb 0 msb 15 lsb 0 msb 15 sdo lrcko bcko lsb 0 lsb 0 msb 19 lsb 0 msb 19 sdo lsb 0 lsb 0 lsb 0 sdo msb 23 msb 23 msb 23 sdo lsb 0 lsb 0 a) (obit2, obit1) (0, 0): msb first, right-justified mode, 16-bit data b) (oibit2, oibit1) (0, 1): msb first, right-justified mode, 20-bit data c) (obit2, obit1) (1, 0): msb first, right-justified mode, 24-bit data d) (obit2, obit1) (1, 1): iis-compatible, 24 bits max msb 23 msb 23 msb 23 lsb 0 figure 2.2 data output formats lsb 0 lsb 0 msb 15 sdo lrcko bcko a) (obit2, obit1) (0, 0): msb first, right-justified mode, 16-bit data b) (oibit2, obit1) (0, 1): msb first, right-justified mode, 20-bit data prohibited lsb 0 msb 15 msb 15 c) (obit2, obit1) (1, 0): msb first, right-justified mode, 24-bit data prohibited d) (obit2, obit1) (1, 1): iis-compatible, 24 bits max lsb 0 lsb 0 msb 15 sdo lsb 0 msb 15 msb 15
TC9444F 2002-01-11 10 3. microcontroller interface consisting of commands and data, the microcontroller interface block is designed as a simple and easy-to-use interface. this interface has two modes: i 2 c bus mode and three-lead mode. i 2 c bus mode can be switched by a dc setting via a pin. 3.1 commands one-byte (8-bit) commands are used to perform a range of settings. some commands are followed by one to three bytes of data. an initial reset sets the microcontroller interface block to master mode. boot rom data can be used to output a sound at reset (analog through mode). after power-on, reset at least once by setting the pin to low level. table 3.1 list of commands command ch cl data setting contents boot 0 0 initializes coefficient ram. mute 1 0 to 3 turns soft mute and ramclr on/off. keycon 2 0 to f key control; amount of key shift vc 3 0 to f 16-page bank vocal cancel/change, multi-sound source bksa 4 0 to 3 4-page bank function reserve bksb 5 0, 1 2-page bank function reserve emp 6 0 to f de-emphasis deci 7 0 to 3 delay ram decimation rate atime 8 0 to 3 level detection attack time rtime 9 0 to 6 level detection release time comp a 0 to f compressor function atta b 0 2-byte digital attenuator level a attb b 1 2-byte digital attenuator level b keycon2 b 2 2-byte controls an independent key or sets vibrato. exto b 3 2-byte extended output port data cram c 0, 1 3-byte writes coefficient ram. mode d 0 to 3 1-byte sets ic operating mode. note 4: the functions of some commands vary according to the internal program. also, some programs contain commands that need not be set. refer to the separate software datasheet. the commands are described below. the values in the table marked by an asterisk are the initial values at a reset. setting reset to ?l? also mutes the da converter output (op-amp feed-back causes the da converter to output vref). accordingly, to completely mute the analog output during operation, digitally mute the output using the mute command, then set reset to ?l?. reset
TC9444F 2002-01-11 11 3.2 boot command one-byte command to initialize coefficient ram. initializes coefficient ram values to the internal boot rom values, retaining the other command interface settings. after the boot command is received, initialization completes in a 1 -fs cycle. boot release is not required. when reset is made by setting the reset pin to ?l?, boot is still executed. 3.3 mute command one-byte command to clear data ram and delay ram, and to execute a soft mute using the digital attenuator. table 3.2 mute command cl ch 3 2 1 0 1 0 0 ramclr mute note 5: at a reset, the initial value is cl 0h. mute: mute ?h? sets soft mute. ramclr: ramclr ?h? clears data ram and delay ram. at a soft mute, the time constant is determined by the operation sampling frequency and the time constant selection bit set by the atta command. after the soft mute is released, the digital attenuator is restored to the set level. in data ram, sequentially writing all-zero data (fixing the input data to 000000h) while ramclr ?h? clears data ram. therefore, the number of fs cycles required to completely clear data ram depends on the program. normally, several cycles are required. for a program which is written to in one place only, a 1 28-word update takes no more than 3 ms. in delay ram, after ramclr h, 0000h is sequentially written to delay ram at subsequent write operations (init operation). when using delay ram to significantly change the effect of the sfc processing, to clear the data in ram, take the following steps. first set the mute bit. then, after waiting only the length of the digital attenuator time constant, set ramclr to ?h? to clear the data in ram. then set the ramclr and mute bits to ?l?. this will enable you to change the signal processing content without any switching noise. 3.4 keycon command one-byte command to control the amount of key shift. the cl value indicates the amount of key shift. the difference between the 20h command and the 28h command is the point at which key control processing completely stops. using the 20h command to turn key control off disables the use of internal delay ram in the key control processing, thus allowing delay ram to be allocated to other processing. the amount of key shift set by the keycon command applies to both l and r stereo key control and to monaural key control. the key shift is set in semitone steps. as delay ram is used in key control processing, when switching the key shift setting between 0 and a value other than 0, the signal is intermittent. the soft mute automatically comes on to avoid switching noise at this time. after the command is issued, the following steps are performed automatically. mute internal settings switched mute released this series of processing operations takes around 46 ms to execute.
TC9444F 2002-01-11 12 table 3.3 setting key shift amount ch cl setting content 2 0 key shift 0 (key control off) 2 1 1200 cent 2 2 600 cent 2 3 500 cent 2 4 400 cent 2 5 300 cent 2 6 200 cent 2 7 100 cent * 2 8 key shift 0 2 9 100 cent 2 a 200 cent 2 b 300 cent 2 c 400 cent 2 d 500 cent 2 e 600 cent 2 f 1200 cent 3.5 vc command one-byte command to set through, vocal cancel, and vocal change for each input source. refer to the separate software datasheet. 3.6 bksa command one-byte command to set four-page bank switching. 3.7 bksb command one-byte command to set two-page bank switching. 3.8 emph command this command selects an internal de-emphasis digital filter. the filter is either a digital filter selected, via software, by switching a dsp coefficient bank, or an internal da converter digital filter selected via hardware. the filter is set through the microcontroller interface. the filter is on only when the emp pin goes high. this command sets the filter on/off directly from the cd processor emp flag without passing through the microcontroller. as well as a de-emphasis filter, the dsp block filter can also be used as a high-pass filter for canceling dc offset. (the crom data determines the filter?s function.)
TC9444F 2002-01-11 13 table 3.4 emph command cl ch 3 2 1 0 6 esb2 esb1 esa2 esa1 note 6: at a reset, the initial value is cl 5h. table 3.5 settings with emph command cl ch esb2 esb1 esa2 esa1 setting block filter characteristics 6 0 0 dsp block bank 0 (fs 44.1 khz) * 6 0 1 dsp block bank 1 (off) 6 1 0 dsp block bank 2 (fs 48 khz) 6 1 1 dsp block bank 3 (fs 32 khz) 6 0 0 output dac block fs 44.1 khz * 6 0 1 output dac block off (through) 6 1 0 output dac block fs 48 khz 6 1 1 output dac block fs 32 khz 3.9 deci command one-byte command to select the decimation filter for delay processing in delay ram. at a reset, the initial value is 1 /3 decimation (cl 2). this command determines only the decimation filter band. the decimation rate in delay ram is determined by the ofram command value. table 3.6 deci command ch cl setting content 7 0 1/1 decimation 7 1 1/2 decimation * 7 2 1/3 decimation 7 3 1/4 decimation 3.10 atime command one-byte command to set the compressor block attack time. table 3.7 atime command attack time [ms] ch cl atk1 atk0 cb2, 1 0, 0 cb2, 1 0, 1 cb2, 1 1, 0 cb2, 1 1, 1 8 0 l l 4 3 2 1 8 1 l h 8 6 4 2 * 8 2 h l 16 12 8 4 8 3 h h 32 24 16 8
TC9444F 2002-01-11 14 3.11 rtime command one-byte command to set the compressor block release time. table 3.8 rtime command [s] release time ch cl rel1 rel1 rel0 cb2, 1 0, 0 cb2, 1 0, 1 cb2, 1 1, 0 cb2, 1 1, 1 9 0 l l l 1.1 0.5 0.3 0.1 * 9 1 l l h 1.6 1.0 0.7 0.3 9 2 h l l 2.6 2.0 1.3 0.6 9 3 l h h 4.6 4.1 2.6 1.1 9 4 h l l 8.7 8.2 5.2 2.2 9 5 h l h 16.9 16.3 10.4 4.5 9 6 h h l 33.3 32.6 20.8 9.0 3.12 comp command one-byte command to select the compressor function. table 3.9 comp command cl ch 3 2 1 0 a vchg cbs cb2 cb1 note 7: at a reset, the initial value is cl 8h. vchg: vchg ?h? selects (turns on) the vocal change function. cbs: selects the compression ratio. cbs ?l? selects a ratio of 24db; cbs ?h? selects 36db (refer to the table) cb2, 1: used for precise selection of the compression ratio. table 3.10 compression ratio settings cbs cb2 cb1 compression ratio 0 0 0 24db 0 0 1 18db 0 1 0 12db 0 1 1 6db 1 0 0 36db 1 0 1 27db 1 1 0 18db 1 1 1 9db noise can result when cb2, 1 are used to switch the compression ratio. to switch the ratio without clunking, refer to the software datasheet.
TC9444F 2002-01-11 15 3.13 atta command command to set the digital attenuator level by adding two-byte data. when the lower 1 4 bits of the data are set to 2000h, the attenuator level is 0db. the upper two bits are the attenuator time constant selection bits. these bits select the soft mute time constants. when switching using the mute or keycon command, the value set by atta is also valid for the automatic mute function. table 3.11 atta command ch cl d1 d0 b 0 dsa2 dsa1 ala13 ala12 ala11 ala10 ala09 ala08 ala07 ~ ala00 note 8: at a reset, the initial values are dsa 0h (23 ms) and ala [13:00] 2000h (0db). the following formula determines the data ala [ 1 3:00] depending on the level (level [db]) to be set. ala [ 1 3:00] 2000h * 1 0^ (level/20). table 3.12 attenuator setting level ala [13:00] output level 3fffh 6.020db 3000h 3.523db 2000h 0.000db 1fffh 0.001db 1ffeh 0.002db 16a7h 3.000db 1000h 6.021db 0002h 72.247db 0001h 78.268db 0000h db table 3.13 attenuator time constants time constant dsa2 dsa1 fs 32 khz fs 44.1 khz fs 48 khz l l 32 ms 23 ms 21 ms l h 128 ms 92 ms 86 ms h l 256 ms 186 ms 171 ms h h 512 ms 372 ms 341 ms time required for change from 0db to db.
TC9444F 2002-01-11 16 3.14 attb command command to set the cross fade level for the vibrato function on/off by adding two-byte data. when the lower 1 4 bits of the data are set to 2000h, the attenuator level is 0db. the upper two bits are the attenuator time constant selection bits. these bits select the soft mute time constants. table 3.14 attb command ch cl d1 d0 b 1 dsb2 dsb1 alb13 alb12 alb11 alb10 alb09 alb08 alb07 ~ alb00 note 9: at a reset, the initial values are dsb 0h (23 ms) and alb [13:00] 2000h (0db). the values are set in the same way as the settings for the atta command. 3.15 keycon2 command command to set the independent key control right channel or to set the vibrato function by adding two-byte data. because the initial reset sets ena to ?l?, l/r common key control by keycon is enabled at an initial reset. table 3.15 keycon2 command ch cl d1 d0 b 2 0 0 ena vib k2r11 k2r10 k2r09 k2r08 k2r07 ~ k2r00 note 10: at a reset, the initial values are d1 d2 0h. ena: set to ?h? when using independent key control or vibrato. vib: set to ?h? when using the vibrato function. k2r [11:00]: when keycon2 is used for independent key control, these bits set the key control rate. when keycon2 is used to select the vibrato function, these bits set the step value that determines the vibrato cycle.
TC9444F 2002-01-11 17 table 3.16 key control set by keycon2 (ena ?h?, vib ?l?) amount of key shift k2r [11:00] d1 d0 1200 cent 400 24 00 600 cent 1a8 21 a8 500 cent 157 21 57 400 cent 10a 21 0a 300 cent 0c2 20 c2 200 cent 07d 20 7d 100 cent 03d 20 3d 50 cent 01e 20 1e 40 cent 018 20 18 30 cent 012 20 12 20 cent 00c 20 0c 10 cent 006 20 06 10 cent ffa 2f fa 20 cent ff4 2f f4 30 cent fee 2f ee 40 cent fe9 2f e9 50 cent fe3 2f e3 100 cent ec7 2f c7 200 cent f90 2f 90 300 cent f50 2f 50 400 cent f2d 2f 2d 500 cent eff 2e ff 600 cent ed4 2e d4 1200 cent e00 2e 00 k2r [11:00] (2^ (n/1200 [cent]) 1.0) * 400h table 3.17 vibrato cycle set by keycon2 (ena ?h?, vib ?h?) cycle [hz] k2r [11:00] d1 d0 2 05d 30 5d 4 0ba 30 ba 8 175 31 75 k2r [11:00] n/22500 [hz] * 100000h
TC9444F 2002-01-11 18 3.16 exto command command to set the output data of the extended output port by adding two-byte data. the two-byte data are output in parallel directly from the ext0 to extf pins. the command is used to control the leds which display the key control on/off status and the amount of key shift. table 3.18 exto command ch cl d1 d0 b 3 extf exte extd extc extb exta ext9 ext8 ext7 ~ ext0 note 11: at a reset, the initial values are d1 d0 0h. 3.17 cram command command to write coefficient ram data by adding three-byte data. as in the following table, the value of the msb of the address is assigned to the lsb of the cl bits. table 3.19 cram command ch cl d2 d1 c 0 0 0 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ad17 ad16 d2 d1 d0 dt15 ~ dt08 dt07 ~ dt00 note 12: a reset or a boot command sets the coefficient ram value to its initial value. the r/w offset addresses of coefficient ram and delay ram are written as 1 8 bits of data. an address consists of three memory allocation bits, three decimation rate bits, and 1 2 offset address bits. because the content of these settings depends on the internal program, refer to the separate software datasheet. table 3.20 ofram command ch cl d2 d1 c 0 0 0 ad6 ad5 ad4 ad3 ad2 ad1 ad0 mal2 mal1 d2 d1 d0 mal0 deci2 deci1 deci0 dti1 ~ dt08 dt07 ~ dt00 note 13: a reset or a boot command sets the offset ram value to its initial value.
TC9444F 2002-01-11 19 in addition delay ram is properly used by mal [2:0] as ram of 1 024, 2048, and 4096 word, as shown in the following figure. table 3.21 block assignment and address range of delay ram mal2 mal1 mal0 block address range 0 0 0 a 3ffh to 000h 0 0 1 b 7ffh to 400h 0 1 0 c bffh to 800h 0 1 1 d fffh to c00h 1 0 0 e 7ffh to 000h 1 0 1 f fffh to c00h 1 1 g fffh to 000h table 3.22 setting of decimation ratio deci2 deci1 deci0 decimation ratio 0 0 0 1/1 0 0 1 1/2 0 1 0 1/3 0 1 1 1/4 the same or overlapping block cannot be accessed by different decimation ratio. moreover, decimation ratio set up here and decimation ratio set up by deci command need to be fundamentally made in agreement. deci bit set up with an offset address determines decimation ratio of memory access, and a setup to deci command determines the band of a decimation filter. note 14: since c block is assigned to keycontrol r-ch, and d block is assingned to keycontrol l-ch, it is neseccary to be set to key 0h when using it here. figure 3.1 block division of delay ram 1024 word fffh d 1024 word c00h c 1024 word 800h b 1024 word 400h a f e g 000h
TC9444F 2002-01-11 20 3.18 mode command command to set the ic operating mode by adding one-byte data. this command bundles parameters so that they need be set once only at power-on. the cl bits are also used to make settings. table 3.23 mode command ch cl d0 3 2 1 0 7 6 5 4 3 2 1 0 d 0 symm2 symm1 rls obit2 obit1 ibit3 ibit2 ibit1 mckinh dzinh adpd note 15: at a reset, the initial values are synm2 synm1 0, rls 1, d0 00h. (master mode, 16-bit input/output) synm1, 2: select sync mode rls: selects the channel clock polarity (when rls ?h? and lrck ?l? or when rls ?l? and lrck ?h?, l-channel data selected). obit1, 2: select the digital audio output format. ibit1, 2, 3: select the digital audio input format. mckinh: when ?h?, disables the mcko pin output (mck pin is fixed to low). dzinh: when ?h?, disables the digital zero detection output (dz pin is fixed to low). adpd: when ?h?, the ad converter power save and output are masked by setting them to digital zeros. the mckinh bit is used to halt the xi input clock (or the halved input clock) output from the mcko pin. the mcko pin uses a large output buffer for high-speed clock output. however, to suppress unnecessary output without using this pin, set mckinh to high. a function is supported to forcibly mute the dac output by checking whether digital data input from the sdi pin are all zeroes and by setting the dz pin high if all-zero input continues for a specified detection time (table 2.4). when digital input and analog input are switched, digital input zero detection becomes active, setting the dz pin to high. the dzinh bit is used to inhibit the dz pin from going high. setting the adpd bit to high halts the ad converter internal circuits and masks the ad converter output by setting to digital zeros. as some circuitry is halted at this time, the power dissipation drops slightly. 4. ad converter the TC9444F incorporates a successive approximation 1 6-bit ad converter with a two times oversampling rate. the ad converter performs three-channel interleave processing for the line input l/r-channels and the microphone input. the microphone input is designed to internally generate an echo effect. the microphone main signal and the microphone echo signal are combined outside the ic. the microphone main signal and the microphone echo component can also be added internally using a microphone through-path in the ic. when not using an ad converter, connect jumpers between the mici-lpfo 1 , ail-lpfo2, and air-lpfo3 pins. 5. da converter incorporates a -type modulation 1 -bit da converter and a tertiary analog post filter.
TC9444F 2002-01-11 21 6. reset timing after turning on the power supply, always perform a reset by setting the /reset pin to low. figure 6. 1 shows the reset and boot timing. when performing a power-on reset, note the timing shown in figure 6.2. 7. microcontroller interface signal timing microcontroller interface signal timing supports three-lead mode and i 2 c bus mode. 7.1 three-lead bus mode setting ifsel ?h? sets the microcontroller interface to three-lead bus mode. setting the cs signal ?l? enables control from the microcontroller. figure 7. 1 shows the interface timing when three-lead mode is selected. when transmitting two or more commands, be sure to set cs to h between each command. when writing to coefficient or offset ram, be sure to write the data word by word in 1 fs per word. as coefficient or offset ram cannot be updated in multiple-word batches, take particular care when updating filter coefficients. 7.2 i 2 c bus mode setting ifsel ?l? sets the microcontroller interface to i 2 c bus mode. in i 2 c bus mode, the cs pin can be fixed to ?l?. note that the cs pin signal can also be used as the chip select signal. the i 2 c slave address is: msb lsb 11 0 1 1 000 ^^^^^^^^^^^^^ data can only be written to this address. therefore, fix the lsb of read/write mode bits to 0. as i 2 c bus mode does not permit continuous writing, insert an end condition after each command, then a start condition to start writing data again. figure 6.2 power-on reset timing v dd 80% reset 40% t rst 1 ms figure 6.1 reset and boot t rw 0.2 s t boot 50 s boot operation completed. do not write to the coefficient or offset ram until boot is complete. reset
TC9444F 2002-01-11 22 four-byte commands d.c.: don?t care when consecutively transmitting two or more commands: two-byte commands when transmitting multiple commands t 1 t 2 t 3 t 4 t 5 t 6 cs scl sda d.c. c7 c6 c5 c4 c3 c2 c1 c0 da7 da6 da5 da4 da3 da2 da1 da0 db7 db6 db5 db4 db3 db2 db1 db0 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 d.c. d.c. d.c. d.c. id6 id5 id4 id3 id2 id1 id0 cm7 cm6 cm5 cm4 cm3 cm2 cm1 cm0 da7 da6 da5 da4 da3 da2 da1 da0 cs scl sda fixed to ?l? (usable as chip select) id7 figure 7.2 i 2 c interface timing (ifsel ?l?) id7 id6 id5 id4 id3 id2 id1 id0 cm7 cm6 cm5 cm4 cm3 cm2 cm1 cm0 id6 id5 id4 id3 id2 id1 id0 scl sda cm7 cm6 cm5 cm4 cm3 cm2 cm1 cm0 insert an end condition after each command, then transmit a start condition followed by id. id7 t 7 cs scl sda d.c. c7 c6 c5 c4 c3 c2 c1 c0 da7 da6 da5 da4 da3 da2 da1 da0 d.c. d.c. c7 c6 c5 c4 c3 c2 c1 c0 csn t 8 coefficient data 1 transmitted coefficient data 2 transmitted when transmitting two or more commands, be sure to set cs to ?h? between the commands. write the data to coefficient or offset ram word by word in 1 fs per word. figure 7.1 three-lead interface timing (ifsel ?h?) t 1 0.2 s: interface setup time t 2 0.2 s: shift clock ?l? time t 3 0.2 s: shift clock ?h? time t 4 0.2 s: data setup time t 5 0.2 s: data hold time t 6 0.2 s: interface hold time t 7 0.2 s: cs signal ?h? duration t 8 1/fs: coefficient, offset ram write cycle d.c.
TC9444F 2002-01-11 23 8. digital data input/output timing rising edge, falling edge master clock the mcko pin outputs the xi input clock or the xi input clock divided by two. sdo output sdo is output on the bcko falling edge with both internal and external synchronization. master mode bcko and lrcko are divided from the xi input clock. slave mode data input t r t f mcko 90% 10% t r t f lrcko bcko sdo 90% 10% mcko when mcks ?h? mcko when mcks ?l? t d1 t d1 xi bcko t d2 sdo a t 512 fs bcko lrcko t d3 t d4 xi synchronization width t dls a t 512 fs lrcki xi t d6 bcki bco lrcki lrcko t lrh lrcki bcki sdi t lrs t dls t dlh figure 7.3 digital data input/output timing
TC9444F 2002-01-11 24 maximum ratings (ta 25c) characteristics symbol rating unit power supply voltage v dd 0.3 to 6.0 v input voltage v in 0.3 to v dd 0.3 v power dissipation p d 500 mw operating temperature t opr 40 to 85 c storage temperature t stg 55 to 150 c electrical characteristics (unless otherwise specified, ta 25c, v dd 5.0 v) dc characteristics characteristics symbol test circuit test condition min typ. max unit operating voltage v dd ta 40 to 85c 4.5 5.0 5.5 v current consumption i dd xi 16.9 mhz, 384 fs mode 57 80 ma ?h? level v ih v dd 0.8 input voltage ?l? level v il digital input pins 0 v dd 0.2 v ?h? level i ih 1.0 input current ?l? level i il digital input pins 1.0 a ?h? level i oh1 when v oh 4.5 v 2.0 output current 1 (note 16) ?l? level i ol1 when v oh 0.5 v 2.0 ma ?h? level i oh2 when v oh 4.5 v 4.0 output current 2 (note 17) ?l? level i ol2 when v oh 0.5 v 4.0 ma pull-up resistors r up reset , test pin 50 k note 16: dz, ext0 to f, lrcko, bcko, sdo, sda pins in i 2 c bus mode, the sda pin is ?l? output only (open drain). note 17: mcko pin
TC9444F 2002-01-11 25 ac characteristics ad converter characteristics symbol test circuit test condition min typ. max unit maximum input level ain 1 v dd 5.0 v 1.15 1.20 v rms s/(n d) ratio s/n (ad) 1 50db, 1 khz sine wave input 72 80 db thd n thd (ad) 1 0db, 1 khz sine wave input 65 57 db crosstalk ct (ad) 1 68 60 db da converter characteristics symbol test circuit test condition min typ. max unit output level aout 1 1.2 v rms s/n ratio s/n (da) 1 30db, 1 khz sine wave input 84 93 db thd n thd (da) 1 0db, 1 khz sine wave input 86 78 db thd (da) 1 0db, 10 khz sine wave input 83 75 crosstalk ct (da) 1 90 82 db timings characteristics symbol test circuit test condition min typ. max unit cl 50 pf, lrcko, bcko, sdo 30 rise time t r mcko 20 ns cl 50 pf, lrcko, bcko, sdo 30 fall time t f mcko 20 ns t d1 xi mcko 20 common t d2 bcko sdo 5 t d3 xi bcko 15 in master mode t d4 xi lrcko 30 t d5 bcki bcko 30 delay time in slave mode t d6 lrcki lrcko 30 ns sdi setup time t dis 50 ns sdi hold time t dih 50 ns lrcki setup time t lrs 50 ns lrcki hold time t lrh 50 ns interface setup time t 1 0.2 s interface shift clock pulse width t 2 , t 3 0.2 s interface data setup time t 4 0.2 s interface data hold time t 5 0.2 s interface hold time t 6 0.2 s interface cs signal ?h? duration t 7 0.2 s coefficient and offset ram write cycle t 8 1/fs s power-on reset time t rst 1 ms reset pulse width t rw 0.2 s boot time t boot time required for boot 50 s
TC9444F 2002-01-11 26 test circuit TC9444F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 exto exte extf gndl v dl v da1 lpfo1 mici vra1 a il lpfo2 vra2 lpfo3 a ir gnda1 lrcki bcki sdi lrcko bcko sdo v dd1 mcko mcks cks ext6 ext5 ext4 ext3 ext2 extc extb ext a ext9 ext8 ext7 gndd2 test emp sd a scl cs ifsel reset v dd2 gndal aol vrl v da2 vrr aor gndar dz v dx xo xi gndx gndd1 ext0 ext1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 nc 6y 6a nc 5y 5a 4y 4a v cc 1y 1a 2y 2a 3y 3a gnd 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f sda scl cs rst gnd digital data input microcontroller interface digital data input sdi bcki lrcki mcko sdo anritsu mg22a tc4hc4050ap 16.9 mhz 100 f 100 f 47 f 47 f 3.3 f 470 33 pf 33 pf 2200 pf 10 k l-ch ou t 3.3 f 470 2200 pf 10 k r-ch ou t mic in 3.3 f 10 k 10 k 10 k 1200 pf 51 560 pf 220 pf 47 f l-ch in 3.3 f 10 k 10 k 10 k 1200 pf 51 560 pf 220 pf 47 f r-ch in 3.3 f 10 k 10 k 10 k 1200 pf 51 560 pf 220 pf 400 hz hpf 20 khz lpf 30 khz hpf shibasoku am51a analog input analog output
TC9444F 2002-01-11 27 package dimensions weight: 1.08 g (typ.)
TC9444F 2002-01-11 28 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707eb a restrictions on product use

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