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NJU6825 -1 - 02/11/22 162-common x 128rgb-segment, 4096-color stn lcd driver general description the NJU6825 is a stn lcd driver with 162-common x 128rgb-segment in 4096-color. it consists of 384(128xrgb)-segment, 162-common drivers, serial and parallel mpu interface circuits, internal power supply circuits, gradation palettes and 248,832-bit for graphic display data ram. each segment driver outputs 16-gradation level out of 32-gradation level of gradation palette. since the NJU6825 provides a low operating voltage of 1.7v and low operating current, it is ideally suited for battery-powered handheld applications. features 4096-color stn lcd driver lcd drivers 162 commons, 128x3 rgb-segments display data ram (ddram) 248,832-bit for graphic display color display mode 16 gradation level out of 32-gradation level of gradation palette black & white display mode 162 x 384 pixels in 16 gradation level or 162 x 384 pixels in b&w 256-color driving mode 8/16bit parallel interface directly-connective to 68/80 series mpu programmable 8- or 16-bit data bus length for display data 3-/4-line serial interface programmable duty and bias ratios programmable internal voltage booster (maximum 7-times) programmable contrast control using128-step evr various instructions display data read/write, display on/off, reverse display on/off, all pixels on/off, column address, row address, n-line inversion, initial display line, initial com line, read-modify-write, gradation mode control, increment control, data bus length, discharge on/off, duty cycle ratio, lcd bias ratio, boost level, evr control, power save on/off, etc low operating current low logic supply voltage 1.7v to 3.3v lcd driving supply voltage 5.0v to 18.0v c-mos technology package bumped chip / tcp preliminary package outline NJU6825cj
NJU6825 - 2 - pad location note1) the pads of (l), (r) and (c) are shorted mutually in the lsi. note2) the dmy pads are electrically open. chip center :x= 0 m, y= 0 m chip size :19.93mm x 3.06mm chip thickness :625 m 25 m bump size :32 m x 68 m(com/seg output), 47 m x 68 m(interface), 68 m x 68 m(dmy 0 , 109 , 110 , 111 , 112 , 113 , 114,115 ) bump pitch :45 m(min) bump height :14.0~22.5 m (typical 18 m) bump material :au alignment marks a: 30 m b: 6 m c: 120 m d: 27 m alignment mark coordinates x=-9831 m, y=-1396 m x= 9831 m, y=-1396 m resb v ssa (r) v ssa (c) v ssa (l) dmy 37 dmy 36 sel68 dmy 35 dmy 34 dmy 33 p/s dmy 32 dmy 31 v dda (r) v dda (c) v dda (l) dmy 30 dmy 29 test 2 dmy 28 dmy 27 v ss (r) v ss (c) v ss (l) dmy 26 rs dmy 25 dmy 24 dmy 23 dmy 22 csb dmy 21 dmy 19 dmy 20 dmy 18 dmy 1r7 dmy 16 dmy 15 dmy 14 dmy 13 v dd (r) v dd (l) dmy 12 v dd (c) com 150 dmy 0 dmy 113 segb 126 com 100 segc 126 sega 127 segb 127 segc 127 com 81 dmy 115 com 149 com 101 dmy 114 1 dmy 40 dmy 38 dmy 39 wrb sega 126 dmy 11 dmy 10 dmy 9 dmy 8 dmy 7 test 1 dmy 6 dmy 5 dmy 4 dmy 3 v ssa (r) v ssa (c) v ssa (l) dmy 2 com 161 dmy 1 a a c c b b d d
NJU6825 -3 - dmy 53 d 5 dmy 52 d 4 /spol dmy 51 d 3 /smode dmy 50 d 2 d 8 dmy 55 dmy 44 dmy 43 dmy 42 rdb dmy 41 dmy 45 v dd (l) v dd (c) v dd (r) dmy 46 dmy 47 d 0 /scl dmy 48 d 1 /sda dmy 49 d 7 dmy 54 d 6 d 9 dmy 56 d 10 dmy 57 d 11 dmy 58 d 12 dmy 59 d 13 dmy 60 d 14 dmy 61 d 15 dmy 62 v ss (l) dmy 63 v ss (r) v ss (c) cl dmy 64 dmy 66 dmy 65 flm dmy 67 x y v 1 (c) v 1 (l) v lcd (r) v lcd (c) v lcd (l) dmy 79 dmy 78 v ssh (r) v 2 (r) v 2 (c) dmy 71 clk dmy 69 dmy 70 fr dmy 72 dmy 73 osc 1 dmy 74 dmy 75 osc 2 dmy 76 dmy 77 v ssh (l) v ssh (c) v 2 (l) dmy 80 v 1 (r) v 3 (c) v 3 (l) dmy 81 v 3 (r) v 4 (c) v 4 (l) v reg (l) v 4 (r) v reg (r) v reg (c) dmy 83 dmy 82 v ref (c) v ref (l) dmy 84 v ref (r) v ba (c) v ba (l) dmy 85 v ba (r) dmy 87 dmy 86 v ee (l) v ee (c) dmy 68
NJU6825 - 4 - c 2 -(r) c 2 -(c) c 2 -(l) dmy 94 c 2 +(r) c 2 +(c) c 2 +(l) dmy 93 dmy 110 dmy 96 c 3 +(r) v ssh (c) v ssh (l) dmy 88 dmy 89 v ee (r) v ssh (r) dmy 90 dmy 91 c 1 +(l) c 1 +(c) c 1 +(r) dmy 92 c 1 -(l) c 1 -(c) c 1 -(r) c 3 +(c) c 3 +(l) dmy 95 c 3 -(c) c 3 -(l) dmy 97 c 3 -(r) c 4 +(c) c 4 +(l) dmy 98 c 4 +(r) c 4 -(c) c 4 -(l) dmy 99 c 4 -(r) c 5 +(c) c 5 +(l) dmy 100 c 5 +(r) c 5 -(c) c 5 -(l) dmy 101 c 5 -(r) c 6 +(c) c 6 +(l) c 6 -(r) c 6 -(c) c 6 -(l) c 6 +(r) dmy 102 com 69 dmy 109 com 68 com 20 dmy 111 com 19 dmy 112 com 0 sega 0 segb 0 segc 0 sega 1 segb 1 x y segc 1 dmy 103 dmy 105 dmy 104 dmy 107 dmy 106 v out (c) v out (l) com 80 v out (r) dmy 108
NJU6825 -5 - pad coordinates 1 chip size 19930 m x 3060 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x ( m) y ( m) pad no. terminal x ( m) y ( m) 1 dmy 0 -9581 -1396 52 v ss (r) -6510 -1396 103 dmy 55 -2250 -1396 2 com 150 -9518 -1396 53 dmy 27 -6330 -1396 104 d 8 -2130 -1396 3 com 151 -9473 -1396 54 dmy 28 -6270 -1396 105 dmy 56 -2010 -1396 4 com 152 -9428 -1396 55 test 2 -6210 -1396 106 d 9 -1890 -1396 5 com 153 -9383 -1396 56 dmy 29 -6150 -1396 107 dmy 57 -1770 -1396 6 com 154 -9338 -1396 57 dmy 30 -6090 -1396 108 d 10 -1650 -1396 7 com 155 -9293 -1396 58 v dda (l) -6030 -1396 109 dmy 58 -1530 -1396 8 com 156 -9248 -1396 59 v dda (c) -5970 -1396 110 d 11 -1410 -1396 9 com 157 -9203 -1396 60 v dda (r) -5910 -1396 111 dmy 59 -1290 -1396 10 com 158 -9158 -1396 61 dmy 31 -5850 -1396 112 d 12 -1170 -1396 11 com 159 -9113 -1396 62 dmy 32 -5790 -1396 113 dmy 60 -1050 -1396 12 com 160 -9068 -1396 63 p/s -5730 -1396 114 d 13 -930 -1396 13 com 161 -9023 -1396 64 dmy 33 -5670 -1396 115 dmy 61 -810 -1396 14 dmy 1 -8910 -1396 65 dmy 34 -5610 -1396 116 d 14 -690 -1396 15 dmy 2 -8850 -1396 66 dmy 35 -5550 -1396 117 dmy 62 -570 -1396 16 v ssa (l) -8790 -1396 67 sel68 -5490 -1396 118 d 15 -450 -1396 17 v ssa (c) -8730 -1396 68 dmy 36 -5430 -1396 119 dmy 63 -330 -1396 18 v ssa (r) -8670 -1396 69 dmy 37 -5370 -1396 120 v ss (l) -270 -1396 19 dmy 3 -8610 -1396 70 v ssa (l) -5310 -1396 121 v ss (c) -210 -1396 20 dmy 4 -8550 -1396 71 v ssa (c) -5250 -1396 122 v ss (r) -150 -1396 21 dmy 5 -8490 -1396 72 v ssa (r) -5190 -1396 123 dmy 64 30 -1396 22 dmy 6 -8430 -1396 73 dmy 38 -5130 -1396 124 cl 150 -1396 23 dmy 7 -8370 -1396 74 dmy 39 -5070 -1396 125 dmy 65 270 -1396 24 test 1 -8310 -1396 75 wrb -5010 -1396 126 dmy 66 330 -1396 25 dmy 8 -8250 -1396 76 dmy 40 -4950 -1396 127 flm 450 -1396 26 dmy 9 -8190 -1396 77 dmy 41 -4890 -1396 128 dmy 67 570 -1396 27 dmy 10 -8130 -1396 78 dmy 42 -4830 -1396 129 dmy 68 630 -1396 28 dmy 11 -8070 -1396 79 rdb -4770 -1396 130 fr 750 -1396 29 dmy 12 -8010 -1396 80 dmy 43 -4710 -1396 131 dmy 69 870 -1396 30 v dd (l) -7950 -1396 81 dmy 44 -4650 -1396 132 dmy 70 930 -1396 31 v dd (c) -7890 -1396 82 dmy 45 -4590 -1396 133 clk 1050 -1396 32 v dd (r) -7830 -1396 83 v dd (l) -4530 -1396 134 dmy 71 1170 -1396 33 dmy 13 -7650 -1396 84 v dd (c) -4470 -1396 135 dmy 72 1230 -1396 34 dmy 14 -7590 -1396 85 v dd (r) -4410 -1396 136 dmy 73 1290 -1396 35 dmy 15 -7530 -1396 86 dmy 46 -4230 -1396 137 osc 1 1350 -1396 36 dmy 16 -7470 -1396 87 dmy 47 -4170 -1396 138 dmy 74 1410 -1396 37 dmy 17 -7410 -1396 88 d 0 -4050 -1396 139 dmy 75 1470 -1396 38 dmy 18 -7350 -1396 89 dmy 48 -3930 -1396 140 osc 2 1650 -1396 39 resb -7290 -1396 90 d 1 -3810 -1396 141 dmy 76 1830 -1396 40 dmy 19 -7230 -1396 91 dmy 49 -3690 -1396 142 dmy 77 1890 -1396 41 dmy 20 -7170 -1396 92 d 2 -3570 -1396 143 v ssh (l) 1950 -1396 42 dmy 21 -7110 -1396 93 dmy 50 -3450 -1396 144 v ssh (c) 2010 -1396 43 csb -7050 -1396 94 d 3 -3330 -1396 145 v ssh (r) 2070 -1396 44 dmy 22 -6990 -1396 95 dmy 51 -3210 -1396 146 dmy 78 2250 -1396 45 dmy 23 -6930 -1396 96 d 4 -3090 -1396 147 dmy 79 2310 -1396 46 dmy 24 -6870 -1396 97 dmy 52 -2970 -1396 148 v lcd (l) 2370 -1396 47 rs -6810 -1396 98 d 5 -2850 -1396 149 v lcd (c) 2430 -1396 48 dmy 25 -6750 -1396 99 dmy 53 -2730 -1396 150 v lcd (r) 2490 -1396 49 dmy 26 -6690 -1396 100 d 6 -2610 -1396 151 v 1 (l) 2670 -1396 50 v ss (l) -6630 -1396 101 dmy 54 -2490 -1396 152 v 1 (c) 2730 -1396 51 v ss (c) -6570 -1396 102 d 7 -2370 -1396 153 v 1 (r) 2790 -1396
NJU6825 - 6 - pad coordinates 2 chip size 19930 m x 3060 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x ( m) y ( m) pad no. terminal x ( m) y ( m) 154 dmy 80 2850 -1396 205 dmy 95 6390 -1396 256 com 70 9473 -1396 155 v 2 (l) 2910 -1396 206 c 3 +(l) 6450 -1396 257 com 69 9518 -1396 156 v 2 (c) 2970 -1396 207 c 3 +(c) 6510 -1396 258 dmy 109 9581 -1396 157 v 2 (r) 3030 -1396 208 c 3 +(r) 6570 -1396 259 dmy 110 9831 -1143 158 v 3 (l) 3210 -1396 209 dmy 96 6630 -1396 260 com 68 9831 -1080 159 v 3 (c) 3270 -1396 210 c 3 -(l) 6690 -1396 261 com 67 9831 -1035 160 v 3 (r) 3330 -1396 211 c 3 -(c) 6750 -1396 262 com 66 9831 -990 161 dmy 81 3390 -1396 212 c 3 -(r) 6810 -1396 263 com 65 9831 -945 162 v 4 (l) 3450 -1396 213 dmy 97 6870 -1396 264 com 64 9831 -900 163 v 4 (c) 3510 -1396 214 c 4 +(l) 6930 -1396 265 com 63 9831 -855 164 v 4 (r) 3570 -1396 215 c 4 +(c) 6990 -1396 266 com 62 9831 -810 165 v reg (l) 3750 -1396 216 c 4 +(r) 7050 -1396 267 com 61 9831 -765 166 v reg (c) 3810 -1396 217 dmy 98 7110 -1396 268 com 60 9831 -720 167 v reg (r) 3870 -1396 218 c 4 -(l) 7170 -1396 269 com 59 9831 -675 168 dmy 82 3930 -1396 219 c 4 -(c) 7230 -1396 270 com 58 9831 -630 169 dmy 83 3990 -1396 220 c 4 -(r) 7290 -1396 271 com 57 9831 -585 170 v ref (l) 4050 -1396 221 dmy 99 7350 -1396 272 com 56 9831 -540 171 v ref (c) 4110 -1396 222 c 5 +(l) 7410 -1396 273 com 55 9831 -495 172 v ref (r) 4170 -1396 223 c 5 +(c) 7470 -1396 274 com 54 9831 -450 173 dmy 84 4230 -1396 224 c 5 +(r) 7530 -1396 275 com 53 9831 -405 174 v ba (l) 4290 -1396 225 dmy 100 7590 -1396 276 com 52 9831 -360 175 v ba (c) 4350 -1396 226 c 5 -(l) 7650 -1396 277 com 51 9831 -315 176 v ba (r) 4410 -1396 227 c 5 -(c) 7710 -1396 278 com 50 9831 -270 177 dmy 85 4470 -1396 228 c 5 -(r) 7770 -1396 279 com 49 9831 -225 178 dmy 86 4530 -1396 229 dmy 101 7830 -1396 280 com 48 9831 -180 179 dmy 87 4590 -1396 230 c 6 +(l) 7890 -1396 281 com 47 9831 -135 180 v ee (l) 4650 -1396 231 c 6 +(c) 7950 -1396 282 com 46 9831 -90 181 v ee (c) 4710 -1396 232 c 6 +(r) 8010 -1396 283 com 45 9831 -45 182 v ee (r) 4770 -1396 233 dmy 102 8070 -1396 284 com 44 9831 0 183 dmy 88 4950 -1396 234 c 6 -(l) 8130 -1396 285 com 43 9831 45 184 dmy 89 5010 -1396 235 c 6 -(c) 8190 -1396 286 com 42 9831 90 185 v ssh (l) 5190 -1396 236 c 6 -(r) 8250 -1396 287 com 41 9831 135 186 v ssh (c) 5250 -1396 237 dmy 103 8310 -1396 288 com 40 9831 180 187 v ssh (r) 5310 -1396 238 dmy 104 8370 -1396 289 com 39 9831 225 188 dmy 90 5370 -1396 239 dmy 105 8430 -1396 290 com 38 9831 270 189 dmy 91 5430 -1396 240 dmy 106 8490 -1396 291 com 37 9831 315 190 c 1 +(l) 5490 -1396 241 dmy 107 8550 -1396 292 com 36 9831 360 191 c 1 +(c) 5550 -1396 242 v out (l) 8610 -1396 293 com 35 9831 405 192 c 1 +(r) 5610 -1396 243 v out (c) 8670 -1396 294 com 34 9831 450 193 dmy 92 5670 -1396 244 v out (r) 8730 -1396 295 com 33 9831 495 194 c 1 -(l) 5730 -1396 245 dmy 108 8910 -1396 296 com 32 9831 540 195 c 1 -(c) 5790 -1396 246 com 80 9023 -1396 297 com 31 9831 585 196 c 1 -(r) 5850 -1396 247 com 79 9068 -1396 298 com 30 9831 630 197 dmy 93 5910 -1396 248 com 78 9113 -1396 299 com 29 9831 675 198 c 2 +(l) 5970 -1396 249 com 77 9158 -1396 300 com 28 9831 720 199 c 2 +(c) 6030 -1396 250 com 76 9203 -1396 301 com 27 9831 765 200 c 2 +(r) 6090 -1396 251 com 75 9248 -1396 302 com 26 9831 810 201 dmy 94 6150 -1396 252 com 74 9293 -1396 303 com 25 9831 855 202 c 2 -(l) 6210 -1396 253 com 73 9338 -1396 304 com 24 9831 900 203 c 2 -(c) 6270 -1396 254 com 72 9383 -1396 305 com 23 9831 945 204 c 2 -(r) 6330 -1396 255 com 71 9428 -1396 306 com 22 9831 990
NJU6825 -7 - pad coordinates 3 chip size 19930 m x 3060 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x ( m) y ( m) pad no. terminal x ( m) y ( m) 307 com 21 9831 1035 358 sega 9 7403 1396 409 sega 26 5108 1396 308 com 20 9831 1080 359 segb 9 7358 1396 410 segb 26 5063 1396 309 dmy 111 9831 1144 360 segc 9 7313 1396 411 segc 26 5018 1396 310 dmy 112 9581 1396 361 sega 10 7268 1396 412 sega 27 4973 1396 311 com 19 9518 1396 362 segb 10 7223 1396 413 segb 27 4928 1396 312 com 18 9473 1396 363 segc 10 7178 1396 414 segc 27 4883 1396 313 com 17 9428 1396 364 sega 11 7133 1396 415 sega 28 4838 1396 314 com 16 9383 1396 365 segb 11 7088 1396 416 segb 28 4793 1396 315 com 15 9338 1396 366 segc 11 7043 1396 417 segc 28 4748 1396 316 com 14 9293 1396 367 sega 12 6998 1396 418 sega 29 4703 1396 317 com 13 9248 1396 368 segb 12 6953 1396 419 segb 29 4658 1396 318 com 12 9203 1396 369 segc 12 6908 1396 420 segc 29 4613 1396 319 com 11 9158 1396 370 sega 13 6863 1396 421 sega 30 4568 1396 320 com 10 9113 1396 371 segb 13 6818 1396 422 segb 30 4523 1396 321 com 9 9068 1396 372 segc 13 6773 1396 423 segc 30 4478 1396 322 com 8 9023 1396 373 sega 14 6728 1396 424 sega 31 4433 1396 323 com 7 8978 1396 374 segb 14 6683 1396 425 segb 31 4388 1396 324 com 6 8933 1396 375 segc 14 6638 1396 426 segc 31 4343 1396 325 com 5 8888 1396 376 sega 15 6593 1396 427 sega 32 4298 1396 326 com 4 8843 1396 377 segb 15 6548 1396 428 segb 32 4253 1396 327 com 3 8798 1396 378 segc 15 6503 1396 429 segc 32 4208 1396 328 com 2 8753 1396 379 sega 16 6458 1396 430 sega 33 4163 1396 329 com 1 8708 1396 380 segb 16 6413 1396 431 segb 33 4118 1396 330 com 0 8663 1396 381 segc 16 6368 1396 432 segc 33 4073 1396 331 sega 0 8618 1396 382 sega 17 6323 1396 433 sega 34 4028 1396 332 segb 0 8573 1396 383 segb 17 6278 1396 434 segb 34 3983 1396 333 segc 0 8528 1396 384 segc 17 6233 1396 435 segc 34 3938 1396 334 sega 1 8483 1396 385 sega 18 6188 1396 436 sega 35 3893 1396 335 segb 1 8438 1396 386 segb 18 6143 1396 437 segb 35 3848 1396 336 segc 1 8393 1396 387 segc 18 6098 1396 438 segc 35 3803 1396 337 sega 2 8348 1396 388 sega 19 6053 1396 439 sega 36 3758 1396 338 segb 2 8303 1396 389 segb 19 6008 1396 440 segb 36 3713 1396 339 segc 2 8258 1396 390 segc 19 5963 1396 441 segc 36 3668 1396 340 sega 2 8213 1396 391 sega 20 5918 1396 442 sega 37 3623 1396 341 segb 3 8168 1396 392 segb 20 5873 1396 443 segb 37 3578 1396 342 segc 3 8123 1396 393 segc 20 5828 1396 444 segc 37 3533 1396 343 sega 4 8078 1396 394 sega 21 5783 1396 445 sega 38 3488 1396 344 segb 4 8033 1396 395 segb 21 5738 1396 446 segb 38 3443 1396 345 segc 4 7988 1396 396 segc 21 5693 1396 447 segc 38 3398 1396 346 sega 5 7943 1396 397 sega 22 5648 1396 448 sega 39 3353 1396 347 segb 5 7898 1396 398 segb 22 5603 1396 449 segb 39 3308 1396 348 segc 5 7853 1396 399 segc 22 5558 1396 450 segc 39 3263 1396 349 sega 6 7808 1396 400 sega 23 5513 1396 451 sega 40 3218 1396 350 segb 6 7763 1396 401 segb 23 5468 1396 452 segb 40 3173 1396 351 segc 6 7718 1396 402 segc 23 5423 1396 453 segc 40 3128 1396 352 sega 7 7673 1396 403 sega 24 5378 1396 454 sega 41 3083 1396 353 segb 7 7628 1396 404 segb 24 5333 1396 455 segb 41 3038 1396 354 segc 7 7583 1396 405 segc 24 5288 1396 456 segc 41 2993 1396 355 sega 8 7538 1396 406 sega 25 5243 1396 457 sega 42 2948 1396 356 segb 8 7493 1396 407 segb 25 5198 1396 458 segb 42 2903 1396 357 segc 8 7448 1396 408 segc 25 5153 1396 459 segc 42 2858 1396
NJU6825 - 8 - pad coordinates 4 chip size 19930 m x 3060 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x ( m) y ( m) pad no. terminal x ( m) y ( m) 460 sega 43 2813 1396 511 sega 60 518 1396 562 sega 77 -1778 1396 461 segb 43 2768 1396 512 segb 60 473 1396 563 segb 77 -1823 1396 462 segc 43 2723 1396 513 segc 60 428 1396 564 segc 77 -1868 1396 463 sega 44 2678 1396 514 sega 61 383 1396 565 sega 78 -1913 1396 464 segb 44 2633 1396 515 segb 61 338 1396 566 segb 78 -1958 1396 465 segc 44 2588 1396 516 segc 61 293 1396 567 segc 78 -2003 1396 466 sega 45 2543 1396 517 sega 62 248 1396 568 sega 79 -2048 1396 467 segb 45 2498 1396 518 segb 62 203 1396 569 segb 79 -2093 1396 468 segc 45 2453 1396 519 segc 62 158 1396 570 segc 79 -2138 1396 469 sega 46 2408 1396 520 sega 63 113 1396 571 sega 80 -2183 1396 470 segb 46 2363 1396 521 segb 63 68 1396 572 segb 80 -2228 1396 471 segc 46 2318 1396 522 segc 63 23 1396 573 segc 80 -2273 1396 472 sega 47 2273 1396 523 sega 64 -23 1396 574 sega 81 -2318 1396 473 segb 47 2228 1396 524 segb 64 -68 1396 575 segb 81 -2363 1396 474 segc 47 2183 1396 525 segc 64 -113 1396 576 segc 81 -2408 1396 475 sega 48 2138 1396 526 sega 65 -158 1396 577 sega 82 -2453 1396 476 segb 48 2093 1396 527 segb 65 -203 1396 578 segb 82 -2498 1396 477 segc 48 2048 1396 528 segc 65 -248 1396 579 segc 82 -2543 1396 478 sega 49 2003 1396 529 sega 66 -293 1396 580 sega 83 -2588 1396 479 segb 49 1958 1396 530 segb 66 -338 1396 581 segb 83 -2633 1396 480 segc 49 1913 1396 531 segc 66 -383 1396 582 segc 83 -2678 1396 481 sega 50 1868 1396 532 sega 67 -428 1396 583 sega 84 -2723 1396 482 segb 50 1823 1396 533 segb 67 -473 1396 584 segb 84 -2768 1396 483 segc 50 1778 1396 534 segc 67 -518 1396 585 segc 84 -2813 1396 484 sega 51 1733 1396 535 sega 68 -563 1396 586 sega 85 -2858 1396 485 segb 51 1688 1396 536 segb 68 -608 1396 587 segb 85 -2903 1396 486 segc 51 1643 1396 537 segc 68 -653 1396 588 segc 85 -2948 1396 487 sega 52 1598 1396 538 sega 69 -698 1396 589 sega 86 -2993 1396 488 segb 52 1553 1396 539 segb 69 -743 1396 590 segb 86 -3038 1396 489 segc 52 1508 1396 540 segc 69 -788 1396 591 segc 86 -3083 1396 490 sega 53 1463 1396 541 sega 70 -833 1396 592 sega 87 -3128 1396 491 segb 53 1418 1396 542 segb 70 -878 1396 593 segb 87 -3173 1396 492 segc 53 1373 1396 543 segc 70 -923 1396 594 segc 87 -3218 1396 493 sega 54 1328 1396 544 sega 71 -968 1396 595 sega 88 -3263 1396 494 segb 54 1283 1396 545 segb 71 -1013 1396 596 segb 88 -3308 1396 495 segc 54 1238 1396 546 segc 71 -1058 1396 597 segc 88 -3353 1396 496 sega 55 1193 1396 547 sega 72 -1103 1396 598 sega 89 -3398 1396 497 segb 55 1148 1396 548 segb 72 -1148 1396 599 segb 89 -3443 1396 498 segc 55 1103 1396 549 segc 72 -1193 1396 600 segc 89 -3488 1396 499 sega 56 1058 1396 550 sega 73 -1238 1396 601 sega 90 -3533 1396 500 segb 56 1013 1396 551 segb 73 -1283 1396 602 segb 90 -3578 1396 501 segc 56 968 1396 552 segc 73 -1328 1396 603 segc 90 -3623 1396 502 sega 57 923 1396 553 sega 74 -1373 1396 604 sega 91 -3668 1396 503 segb 57 878 1396 554 segb 74 -1418 1396 605 segb 91 -3713 1396 504 segc 57 833 1396 555 segc 74 -1463 1396 606 segc 91 -3758 1396 505 sega 58 788 1396 556 sega 75 -1508 1396 607 sega 92 -3803 1396 506 segb 58 743 1396 557 segb 75 -1553 1396 608 segb 92 -3848 1396 507 segc 58 698 1396 558 segc 75 -1598 1396 609 segc 92 -3893 1396 508 sega 59 653 1396 559 sega 76 -1643 1396 610 sega 93 -3938 1396 509 segb 59 608 1396 560 segb 76 -1688 1396 611 segb 93 -3983 1396 510 segc 59 563 1396 561 segc 76 -1733 1396 612 segc 93 -4028 1396
NJU6825 -9 - pad coordinates 5 chip size 19930 m x 3060 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x ( m) y ( m) pad no. terminal x ( m) y ( m) 613 sega 94 -4073 1396 664 sega 111 -6368 1396 715 com 81 -8663 1396 614 segb 94 -4118 1396 665 segb 111 -6413 1396 716 com 82 -8708 1396 615 segc 94 -4163 1396 666 segc 111 -6458 1396 717 com 83 -8753 1396 616 sega 95 -4208 1396 667 sega 112 -6503 1396 718 com 84 -8798 1396 617 segb 95 -4253 1396 668 segb 112 -6548 1396 719 com 85 -8843 1396 618 segc 95 -4298 1396 669 segc 112 -6593 1396 720 com 86 -8888 1396 619 sega 96 -4343 1396 670 sega 113 -6638 1396 721 com 87 -8933 1396 620 segb 96 -4388 1396 671 segb 113 -6683 1396 722 com 88 -8978 1396 621 segc 96 -4433 1396 672 segc 113 -6728 1396 723 com 89 -9023 1396 622 sega 97 -4478 1396 673 sega 114 -6773 1396 724 com 90 -9068 1396 623 segb 97 -4523 1396 674 segb 114 -6818 1396 725 com 91 -9113 1396 624 segc 97 -4568 1396 675 segc 114 -6863 1396 726 com 92 -9158 1396 625 sega 98 -4613 1396 676 sega 115 -6908 1396 727 com 93 -9203 1396 626 segb 98 -4658 1396 677 segb 115 -6953 1396 728 com 94 -9248 1396 627 segc 98 -4703 1396 678 segc 115 -6998 1396 729 com 95 -9293 1396 628 sega 99 -4748 1396 679 sega 116 -7043 1396 730 com 96 -9338 1396 629 segb 99 -4793 1396 680 segb 116 -7088 1396 731 com 97 -9383 1396 630 segc 99 -4838 1396 681 segc 116 -7133 1396 732 com 98 -9428 1396 631 sega 100 -4883 1396 682 sega 117 -7178 1396 733 com 99 -9473 1396 632 segb 100 -4928 1396 683 segb 117 -7223 1396 734 com 100 -9518 1396 633 segc 100 -4973 1396 684 segc 117 -7268 1396 735 dmy 113 -9581 1396 634 sega 101 -5018 1396 685 sega 118 -7313 1396 736 dmy 114 -9831 1143 635 segb 101 -5063 1396 686 segb 118 -7358 1396 737 com 101 -9831 1080 636 segc 101 -5108 1396 687 segc 118 -7403 1396 738 com 102 -9831 1035 637 sega 102 -5153 1396 688 sega 119 -7448 1396 739 com 103 -9831 990 638 segb 102 -5198 1396 689 segb 119 -7493 1396 740 com 104 -9831 945 639 segc 102 -5243 1396 690 segc 119 -7538 1396 741 com 105 -9831 900 640 sega 103 -5288 1396 691 sega 120 -7583 1396 742 com 106 -9831 855 641 segb 103 -5333 1396 692 segb 120 -7628 1396 743 com 107 -9831 810 642 segc 103 -5378 1396 693 segc 120 -7673 1396 744 com 108 -9831 765 643 sega 104 -5423 1396 694 sega 121 -7718 1396 745 com 109 -9831 720 644 segb 104 -5468 1396 695 segb 121 -7763 1396 746 com 110 -9831 675 645 segc 104 -5513 1396 696 segc 121 -7808 1396 747 com 111 -9831 630 646 sega 105 -5558 1396 697 sega 122 -7853 1396 748 com 112 -9831 585 647 segb 105 -5603 1396 698 segb 122 -7898 1396 749 com 113 -9831 540 648 segc 105 -5648 1396 699 segc 122 -7943 1396 750 com 114 -9831 495 649 sega 106 -5693 1396 700 sega 123 -7988 1396 751 com 115 -9831 450 650 segb 106 -5738 1396 701 segb 123 -8033 1396 752 com 116 -9831 405 651 segc 106 -5783 1396 702 segc 123 -8078 1396 753 com 117 -9831 360 652 sega 107 -5828 1396 703 sega 124 -8123 1396 754 com 118 -9831 315 653 segb 107 -5873 1396 704 segb 124 -8168 1396 755 com 119 -9831 270 654 segc 107 -5918 1396 705 segc 124 -8213 1396 756 com 120 -9831 225 655 sega 108 -5963 1396 706 sega 125 -8258 1396 757 com 121 -9831 180 656 segb 108 -6008 1396 707 segb 125 -8303 1396 758 com 122 -9831 135 657 segc 108 -6053 1396 708 segc 125 -8348 1396 759 com 123 -9831 90 658 sega 109 -6098 1396 709 sega 126 -8393 1396 760 com 124 -9831 45 659 segb 109 -6143 1396 710 segb 126 -8438 1396 761 com 125 -9831 0 660 segc 109 -6188 1396 711 segc 126 -8483 1396 762 com 126 -9831 -45 661 sega 110 -6233 1396 712 sega 127 -8528 1396 763 com 127 -9831 -90 662 segb 110 -6278 1396 713 segb 127 -8573 1396 764 com 128 -9831 -135 663 segc 110 -6323 1396 714 segc 127 -8618 1396 765 com 129 -9831 -180
NJU6825 - 10 - pad coordinates 6 chip size 19930 m x 3060 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) 766 com 130 -9831 -225 767 com 131 -9831 -270 768 com 132 -9831 -315 769 com 133 -9831 -360 770 com 134 -9831 -405 771 com 135 -9831 -450 772 com 136 -9831 -495 773 com 137 -9831 -540 774 com 138 -9831 -585 775 com 139 -9831 -630 776 com 140 -9831 -675 777 com 141 -9831 -720 778 com 142 -9831 -765 779 com 143 -9831 -810 780 com 144 -9831 -855 781 com 145 -9831 -900 782 com 146 -9831 -945 783 com 147 -9831 -990 784 com 148 -9831 -1035 785 com 149 -9831 -1080 786 dmy 115 -9831 -1144
NJU6825 - 11 - block diagram rs p/s sel68 csb wrb rdb test 1 resb v ss v dd v lcd , v 1 -v 4 v out v ba v ee mpu interface bus holder internal bus column address decoder display timing generator line counter line address decoder row address decoder display data ram (dd ram) 128x162x(4+4+4)bit segment driver clk fr flm cl common driver initial display line register 5 c 1 - c 1 + c 2 + c 2 - v ref c 3 + c 3 - c 4 + c 4 - sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 com 0 com 161 gradation circuit data latch circuit shift register row address register row address counter column address counter column address register d 7 d 4 /spol d 6 d 15 d 14 d 13 d 12 d 5 d 11 d 10 d 9 d 8 d 3 /smode d 0 /scl d 2 d 1 /sda ram interface pole control instruction decoder osc 1 c 5 + c 5 - c 6 + c 6 - register read control oscillator i/o buffer v ssh osc 2 v reg voltage re g ulator voltage booster test 2
NJU6825 - 12 - power supply circuits block diagram v ba v ref v out v ee voltage booster c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v reg + - + - + - + - + - reference voltage generator boost level register evr register v 1 v 2 v 3 v 4 v lcd + - gain control (1x-7x) + - voltage regulator e.v.r 1/2v reg
NJU6825 - 13 - terminal description 1 no. symbol i/o function 30-32, 83-85 v dd power power supply for logic circuits 50-52, 120-122 v ss power gnd for logic circuits 143-145, 185-187 v ssh power gnd for high voltage circuits 58-60 v dda power this terminal is internally connected to the v dd level. ? this terminal is used to fix the selection terminals to the v dd level. note) do not use this terminal for a main power supply. 16-18, 70-72 v ssa power this terminal is internally connected to the v ss level. ? this terminal is used to fix the selection terminals of the v ss level. note) do not use this terminal for a main gnd. 148-150, 151-153, 155-157, 158-160, 162-164 v lcd v 1 v 2 v 3 v 4 power/o lcd driving voltages ? when the internal voltage booster is not used, external lcd driving voltages (v 1 to v 4 and v lcd ) must be supplied on these terminals. the external voltages must be maintained with the following relation. v ss NJU6825 - 14 - terminal description 2 no. symbol i/o function 88 d 0 /scl i/o 90 d 1 /sda i/o 94 d 3 /smode i/o 96 d 4 /spol i/o 92, 98, 100,102 d 2 , d 5 , d 6 , d 7 i/o parallel interface: d 7 to d 0 : 8-bit bi-directional bus ? in the parallel interface mode (p/s=?1?), these terminals connect to 8-bit bi-directional mpu bus. serial interface: sda : serial data scl : serial clock smode : 3-/4-line serial interface mode selection spol : rs polarity selection (in the 3-line serial interface mode) ? in the 3-/4-line serial interface mode (p/s=?0?), the d0 terminal is assigned to the scl and the d 1 terminal to the sda. ? in the 3-line serial interface mode, the d 4 terminal is assigned to the spol. ? serial data on the sda is fetched at the rising edge of the scl signal in the order of the d 7 , d 6 ?d 0 , and the fetched data is converted into 8-bit parallel data at the falling edge of the 8th scl signal. ? the scl signal must be set to ?0? after data transmissions or during non-access. 104,106,108, 110,112,114, 116,118 d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 i/o 8-bit bi-directional bus ? in the 16-bit data bus mode, these terminals are assigned to the upper 8-bit data bus. ? in the serial interface mode or 8-bit data bus mode of the parallel interface, these terminals must be fixed to ?1? or ?0?. 43 csb i chip select active ?0? resister select ? this signal distinguishes transferred data as an instruction or display data as follows. rs h l distinct. instruction display data 47 rs i 79 rdb (e) i 80 series mpu interface (p/s=?1?, sel68=?0?) rdb signal. active ?0?. 68 series mpu interface (p/s=?1?, sel68=?1?) enable signal. active ?1?. 80 series mpu interface (p/s=?1?, sel68=?0?) wrb signal. active ?0?. 68 series mpu interface (p/s=?1?, sel68=?1?) r/w signal. r/w h l status read write 75 wrb (r/w) i
NJU6825 - 15 - terminal description 3 no. symbol i/o function mpu interface type select sel68 h l status 68 series 80 series 67 sel68 i parallel / serial interface mode selection p/s chip select data/instructio n data read/write serial clock h csb rs d0 to d7 rdb, wrb - l csb rs sda (d1) write only scl (d0) 63 p/s i ? since the d 15 to d 5 and d 2 terminals are in the high impedance in the serial inter face mode (p/s=?0?), they must be fixed to ?1? or ?0?. the rdb and wrb terminals also must be ?1? or ?0?. 124 cl i/o this terminal must be opened. 127 flm i/o this terminal must be opened. 130 fr i/o this terminal must be opened. 24 test 1 i maker test terminal this terminal should be fixed to ?0?. 55 test 2 i maker test terminal this terminal must be fixed to ?1?.
NJU6825 - 16 - terminal description 4 no. symbol i/o function segment output rev mode turn-off turn-on normal 0 1 reverse 1 0 ? these terminals output lcd driving waveforms in accordance with the combination of the fr signal and display data. in the b/w mode fr signal display data normal display mode v 2 v lcd v 3 v ss reverse display mode v lcd v 2 v ss v 3 331-714 sega 0 to sega 127 , segb 0 to segb 127 , segc 0 to segc 127 o common output ? these terminals output lcd driving waveforms in accordance with the combination of the fr signal and scanning data. data fr output level h h v ss l h v 1 h l v lcd l l v 4 311-330, 260-308, 246-257, 715-734, 737-785, 2-13 com 0 to com 161 o 137, 140 osc 1 osc 2 i o osc ? when the internal oscillator clock is used, osc 1 terminal must be fixed to ?1? or ?0?, and the osc 2 terminal must be opened. when the oscillation frequency from the internal oscillator is adjusted by an external resistor between osc 1 terminal and osc 2 ? when an external oscillator is used, external clock is input to the osc 1 terminal or an external resistor is connected between the osc 1 and osc 2 terminals. 133 clk i/o this terminal must be opened. (terminal no.14,15,20-23,25-29,33-38,40-42,44-46,48,49,53,54,56,57,61,62,64-66,68,69,73,74,76-78,80-82, 86,87,89,91,93,95,97,99,101,103,105,107,109,111,113,115,117,119,123,125,126,128,129,131,132,134-136, 138,139,141,142,146,147,154,161,168,169,173,177-179,183,184,188,189,193,197,201,205,209,213,217,221, 225,229,233,237-241,245,258,259,309,310,735,736, and 786 are dummy.)
NJU6825 - 17 - functional description (1) mpu interface (1-1) selection of parallel / serial interface mode the p/s terminal is used to select parallel or serial interface mode as shown in the following table. in the serial interface mode, it is not possible to read out display data from the ddram and status from the internal registers. table1 p/s p/s mode csb rs rdb wrb sel68 sda scl data h parallel i/f csb rs rdb wrb sel68 d 7 -d 0 (d 15 -d 0 ) l serial i/f csb rs - - - sda scl - note 1) ? -? mark: fix to ?1? or ?0?. (1-2) selection of mpu interface type in the parallel interface mode, the sel68 terminal is used to select 68- or 80-series mpu interface type as shown in the following table. table2 sel68 mpu type csb rs rdb wrb data h 68 series mpu csb rs e r/w d 7 -d 0 (d 15 -d 0 ) l 80 series mpu csb rs rdb wrb d 7 -d 0 (d 15 -d 0 ) (1-3) data distinction in the parallel interface mode, the combination of rs, rdb, and wrb (r/w) signals distinguishes transferred data between the lsi and mpu as instruction or display data, as shown in the following table. table3 68 series 80 series rs r/w rdb wrb function h h l h read out instruction data h l h l write instruction data l h l h read out display data l l h l write display data (1-4) selection of serial interface mode in the serial interface mode, the smode terminal is used to select the 3- or 4-line serial interface mode as shown in the following table. table4 smode serial interface mode h 3-line l 4-line
NJU6825 - 18 - (1-5) 4-line serial interface mode in the 4-line serial interface mode, when the chip select is active (csb=?0?), the sda and the scl are enabled. when the chip select is not active (csb=?1?), the sda and the scl are disabled and the internal shift register and the counter are being initialized. the 8-bit serial data on the sda is fetched at the rising edge of the scl signal (serial clock) in order of the d 7 , d 6 ?d 0 , and the fetched data is converted into the 8-bit parallel data at the rising edge of the 8th scl signal. in the 4-line serial interface mode, the transferred data on the sda is distinguished as display data or instruction data in accordance with the condition of the rs signal. table5 rs data distinction h instruction data l display data since the serial interface operation is sensitive to external noises, the scl should be set to ?0? after data transmissions or during non-access. to release a mal-function caused by the external noises, the chip- selected status should be released (csb=?1?) after each of the 8-bit data transmissions. the following figure illustrates the interface timing for the 4-line serial interface operation. fig1 4-line serial interface timing (1-6) 3-line serial interface mode in the 3-line serial interface mode, when the chip select is active (csb=?0?), the sda and scl are enabled. when the chip select is not active (csb=?1?), the sda and scl are disabled and the internal shift register and counter are being initialized. 9-bit serial data on the sda is fetched at the rising edge of the scl signal in order of the rs, d 7 , d 6 ?d 0 , and the fetched data is converted into the 9-bit parallel data at the rising edge of the 9th scl signal. in the 3-line serial interface mode, data on the sda is distinguished as display data or instruction data in accordance with the condition of the rs bit of sda data and the status of the spol, as follows. table6 spol=l spol=h rs data distinction rs data distinction l display data l instruction data h instruction data h display data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 valid 1 2 3 4 5 6 7 8 csb rs sda scl
NJU6825 - 19 - since the serial interface operation is sensitive to external noises, the scl must be set to ?0? after data transmissions or during non-access. to release a mal-function caused by the external noises, the chip- selected status should be released (csb=?1?) after each of 9-bit data transmissions. the following figure illustrates the interface timing of the 3-line serial interface operation. fig2 3-line serial interface timing rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 1 2 3 4 5 6 7 8 csb sda scl d 0 9
NJU6825 - 20 - (2) access to the ddram when the csb signal is ?0?, the transferred data from mpu is written into the ddram or instruction register in accordance with the condition of the rs signal. when the rs signal is ?1?, the transferred data is distinguished as display data. after the ?column address? and ?row address? instructions are executed, the display data can be written into the ddram by the ?display data write? instruction. the display data is written at the rising edge of the wrb signal in the 80 series mpu mode, or at the falling edge of the e signal in the 68 series mpu mode. table6 rs data l display ram data h internal command register in the sequence of the ?display data read? operation, the transferred data from mpu is temporarily held in the internal bus-holder, and then transferred to the internal data-bus. when the ?display data read? operation is executed just after the ?column address? and ?row address? instructions or ?display data write? instruction, unexpected data on the bus-holder is read out at the 1st execution, then the data of designated ddram address is read out from the 2nd execution. for this reason, a dummy read cycle must be executed to avoid the unexpected 1st data read. display data write operation display data read operation fig3 note) in the16-bit data bus mode, instruction data must be 16-bit as well as the display data. n n+2 d 0 to d 15 wrb bus holder wrb n n+1 n+2 n+3 n+4 n+1 n+3 n+4 internal d 0 to d 7 (d 0 to d 15 ) rdb n n n+1 n+2 wrb address set n dummy read data read n address data read n+1 address data read n+2 address
NJU6825 - 21 - (3) access to the instruction register each instruction resisters is assigned to each address between 0 h and f h , and the content of the instruction register can be read out by the combination of the ?instruction resister address? and ?instruction resister read?. fig4 (4) 8-/16-bit data bus length for display data (in the parallel interface mode) the 8- or 16-bit data bus length for display data is determined by the ?wls? of the ?data bus length? instruction. in the 16-bit data bus mode, instruction data must be 16-bit data (d 15 to d 0 ) as well as display data. however, for the access to the instruction register, the only lower 8-bit data (d 7 to d 0 ) of the 16-bit data is valid. for the access to the ddram, all of the 16-bit data (d 15 to d 0 ) is valid. table8 wls data bus length mode l 8-bit h 16-bit (5) initial display line register the initial display line resister specifies the line address, corresponding to the initial com line, by the ?initial display line? instruction. the initial com line signifies the common driver, starting scanning the display data in the ddram, and specified by the ?initial com line? instruction. the line address, established in the initial display line resister, is preset into the line counter whenever the flm signal becomes ?1?. at the rising edge of the cl signal, the line counter is counted-up and addressed 384- bit display data corresponding to the counted-up line address, is latched into the data latch circuit. at the falling edge of the cl signal, the latched data outputs to the segment drivers. d 0 to d 7 m n wrb instruction resister address set instruction resister contents read mn rdb instruction resister address set instruction resister contents read
NJU6825 - 22 - (6) ddram mapping the ddram is capable of 1,536-bit (12-bit x 128-segment) for the column address and 162-bit for the row address. in the gradation mode, each pixel for rgb corresponds to successive 3-segment drivers, and each segment driver has 16-gradation. therefore, the lsi can drive up to 128x162 pixels in 4096-color display (16-gradation x 16-gradation x 16-gradation). in the 8-bit data bus length mode column-address 0 h 1 h fe h ff h 0 h 7bit 5bit 7bit 5bit row-address a1 h 7bit 5bit 7bit 5bit column-address abs=?1? 0 h 1 h fe h ff h 0 h 4bit 8bit 4bit 8bit row-address a1 h 4bit 8bit 4bit 8bit column-address hsw=?1? 0 h 1 h be h bf h 0 h 8bit 8bit 8bit 8bit row-address a1 h 8bit 8bit 8bit 8bit column-address c256=?1? 0 h 1 h 7e h 7f h 0 h 8bit 8bit 8bit 8bit row-address a1 h 8bit 8bit 8bit 8bit fig5
NJU6825 - 23 - in the 16-bit data bus length mode column-address 0 h 7f h 0 h 12bit 12bit row-address a1 h 12bit 12bit fig6 in the b&w mode, only msb data from each 4-bit display data group in the ddram is used. therefore, 384 x 162 pixels in the b&w and 128 x 162 pixels in the 8-gradation are available. the range of the column address varies depending on data bus length. the range between 00 h and ff h is used in the 8-bit data bus length and the range between 00 h and 7f h is in the 16-bit data bus length. the increments for the column address and row address are set to the auto-increment mode by programming the ?axi? and ?ayi? registers of the ?increment control? instruction. in this mode, the contents of the column address and row address counters automatically increment whenever the ddram is accessed. the column address and row address counters, independent of the line counter. they are used to designate the column and row addresses for the display data transferred from mpu. on the other hand, the line counter is used to generate the line address, and output display data to the segment drivers, being synchronized with the display control timing of the flm and cl signals.
NJU6825 - 24 - - - a3 - - a2 - - a1 - - a0 d7 d7 b3 d6 d6 b2 d5 d5 b1 d4 d4 b0 d3 d3 c3 d2 d2 c2 d1 d1 c1 d0 d0 c0 - - a3 - - a2 - - a1 - - a0 d7 d7 b3 d6 d6 b2 d5 d5 b1 d4 d4 b0 d3 d3 c3 d2 d2 c2 d1 d1 c1 d0 d0 c0 - - a3 - - a2 - - a1 - - a0 d7 d7 b3 d6 d6 b2 d5 d5 b1 d4 d4 b0 d3 d3 c3 d2 d2 c2 d1 d1 c1 d0 d0 c0 - - a3 - - a2 - - a1 - - a0 d7 d7 b3 d6 d6 b2 d5 d5 b1 d4 d4 b0 d3 d3 c3 d2 d2 c2 d1 d1 c1 d0 d0 c0 palette b x=01h x=7eh palette a 8bit 0x 0x01 x x x=7eh x=01h 11 x=7fh x=00h seg127 palette b palette c palette c seg0 palette a palette a seg1 palette b palette c x=00h x=7fh palette a ram map 2 (256 color mode) seg126 palette b palette c wls abs hsw ref 256 mode 1 0 1 0 0 1 1 0 a3 a2 a1 a0 b3 b2 b1 b0 c3 c2 c1 c0 palette a palette b swap palette c segax segcx ref swap segax segcx segbx segbx d3 d7 d3 d3 d7 d7 d11 d11 d15 d15 a3 d2 d6 d2 d2 d6 d6 d10 d10 d14 d14 a2 d1 d5 d1 d1 d5 d5 d9 d9 d13 d13 a1 d0 d4 d0 d0 d4 d4 d8 d8 d12 d12 a0 d7 d3 d7 d7 d2 d2 d7 d7 d10 d10 b3 d6 d2 d6 d6 d1 d1 d6 d6 d9 d9 b2 d5 d1 d5 d5 d0 d0 d5 d5 d8 d8 b1 d4 d0 d4 d4 d7 d7 d4 d4 d7 d7 b0 d3 d7 d3 d3 d4 d4 d3 d3 d4 d4 c3 d2 d6 d2 d2 d3 d3 d2 d2 d3 d3 c2 d1 d5 d1 d1 d2 d2 d1 d1 d2 d2 c1 d0 d4 d0 d0 d1 d1 d0 d0 d1 d1 c0 d7 d3 d3 d3 d7 d7 d11 d11 d15 d15 a3 d6 d2 d2 d2 d6 d6 d10 d10 d14 d14 a2 d5 d1 d1 d1 d5 d5 d9 d9 d13 d13 a1 d4 d0 d0 d0 d4 d4 d8 d8 d12 d12 a0 d3 d7 d7 d7 d2 d2 d7 d7 d10 d10 b3 d2 d6 d6 d6 d1 d1 d6 d6 d9 d9 b2 d1 d5 d5 d5 d0 d0 d5 d5 d8 d8 b1 d0 d4 d4 d4 d7 d7 d4 d4 d7 d7 b0 d7 d3 d3 d3 d4 d4 d3 d3 d4 d4 c3 d6 d2 d2 d2 d3 d3 d2 d2 d3 d3 c2 d5 d1 d1 d1 d2 d2 d1 d1 d2 d2 c1 d4 d0 d0 d0 d1 d1 d0 d0 d1 d1 c0 d3 d7 d3 d3 d7 d7 d11 d11 d15 d15 a3 d2 d6 d2 d2 d6 d6 d10 d10 d14 d14 a2 d1 d5 d1 d1 d5 d5 d9 d9 d13 d13 a1 d0 d4 d0 d0 d4 d4 d8 d8 d12 d12 a0 d7 d3 d7 d7 d2 d2 d7 d7 d10 d10 b3 d6 d2 d6 d6 d1 d1 d6 d6 d9 d9 b2 d5 d1 d5 d5 d0 d0 d5 d5 d8 d8 b1 d4 d0 d4 d4 d7 d7 d4 d4 d7 d7 b0 d3 d7 d3 d3 d4 d4 d3 d3 d4 d4 c3 d2 d6 d2 d2 d3 d3 d2 d2 d3 d3 c2 d1 d5 d1 d1 d2 d2 d1 d1 d2 d2 c1 d0 d4 d0 d0 d1 d1 d0 d0 d1 d1 c0 d7 d3 d3 d3 d7 d7 d11 d11 d15 d15 a3 d6 d2 d2 d2 d6 d6 d10 d10 d14 d14 a2 d5 d1 d1 d1 d5 d5 d9 d9 d13 d13 a1 d4 d0 d0 d0 d4 d4 d8 d8 d12 d12 a0 d3 d7 d7 d7 d2 d2 d7 d7 d10 d10 b3 d2 d6 d6 d6 d1 d1 d6 d6 d9 d9 b2 d1 d5 d5 d5 d0 d0 d5 d5 d8 d8 b1 d0 d4 d4 d4 d7 d7 d4 d4 d7 d7 b0 d7 d3 d3 d3 d4 d4 d3 d3 d4 d4 c3 d6 d2 d2 d2 d3 d3 d2 d2 d3 d3 c2 d5 d1 d1 d1 d2 d2 d1 d1 d2 d2 c1 d4 d0 d0 d0 d1 d1 d0 d0 d1 d1 c0 mode x=00h x=7fh palette a seg127 palette b palette c palette a ram map 1 seg126 palette b palette c wls abs hsw palette c seg0 palette a 10 seg1 palette b palette c 00 palette b ref 256 x 1x 0 0 x=01h x=7eh palette a x=7eh x=01h x=7fh x=00h 1 1 1 1 x x 1 0 0 0 x=7fh x=00h x=7eh x=01h x=01h x=7eh x=00h x=7fh 0 0 x x 1 1 1 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 8bit 16bit 0 0 1 0 0 0 0 x=beh(l) x=bfh x=bdh x=beh(h) x=bfh x=beh x=bdh x=01h(l) x=02h x=00h x=01h(h) x=02h x=01h x=00h x=feh x=ffh x=fch x=fdh x=00h x=01h x=02h x=03h x=02h x=fch x=03h x=fdh x=00h x=feh x=01h x=ffh x=02h x=03h x=00h x=01h x=feh x=ffh x=fch x=fdh x=feh x=00h x=ffh x=01h x=fch x=02h x=fdh x=03h note1) in the 256-color mode, the vacant lsb bit is filled with "1". note2) the function of 256-color mode is different from that of fixed 8-gradation mode (fixed 256-color mode). note3) the written data in the dd ram in "c256"=0 is not compatible with the data in "c256"=1. note4) in the 256-color mode, only 8-bit length mode is available, but 16-bit is not.
NJU6825 - 25 - (7) window addressing mode in addition to the above usual ddram addressing, it is possible to access some part of ddram in using the window addressing mode, in which the start and end points are designated. the start point is determined by the ?column address? and ?row address? instructions, and the end point is determined by the ?window end column address? and ?window end row address? instructions, the setting example of the window addressing is listed, as follows. . 1. set win=1, axi=1 and ayi=1 by the ?increment control? instruction 2. set the start point by the ?column address? and ?row address? instructions 3. set the end point by the ?window end column address? and ?window end row address? instructions 4. enable to access to the ddram in the window addressing mode in the window addressing mode (win=1, axi=1, ayi=1), the read-modify-write operation is available by setting ?0? to the ?aim? register of the ?increment control? instruction. and in the window addressing mode, the following start and end point must be maintained to abide a malfunction. ax (column address of start point) < ex (column address of end point) < maximum of column address ay (row address of start point) < ey (row address of end point) < maximum of row address column address (x, y) start point end point row address window display area (x, y) whole ddram area fig7 (8) reverse display on/off the ?reverse display on/off? function is used to reverse the display data without changing the contents of the ddram. table9 rev display ddram data display data 0 0 0 normal 1 1 0 1 1 reverse 1 0 (9) segment direction the ?segment direction? function is used to reverse the assignment for the segment drivers and column address, and it is possible to reduce the restrictions for the placement of the lsi on the lcd modules.
NJU6825 - 26 - (10) the relationship among the ddram column address, display data and segment drivers in the color mode, and 16-bit data bus mode hsw abs ref swap column address / bit / segment assign * 0 0 0 x=00 h x=7f h * 0 1 1 x=7f h x=00 h d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign * 0 0 1 x=00 h x=7f h * 0 1 0 x=7f h x=00 h d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 hsw abs ref swap column address / bit / segment assign * 1 0 0 x=00 h x=7f h * 1 1 1 x=7f h x=00 h d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign * 1 0 1 x=00 h x=7f h * 1 1 0 x=7f h x=00 h d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127
NJU6825 - 27 - in the color mode, and 8-bit data bus mode hsw abs ref swap column address / bit / segment assign 0 0 0 0 x=00 h x=01 h x=fe h x=ff h 0 0 1 1 x=fe h x=ff h x=00 h x=01 h d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign 0 0 0 1 x=00 h x=01 h x=fe h x=ff h 0 0 1 0 x=fe h x=ff h x=00 h x=01 h d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 hsw abs ref swap column address / bit / segment assign 0 1 0 0 x=00 h x=01 h x=fe h x=ff h 0 1 1 1 x=fe h x=ff h x=00 h x=01 h d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign 0 1 0 1 x=00 h x=01 h x=fe h x=ff h 0 1 1 0 x=fe h x=ff h x=00 h x=01 h d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127
NJU6825 - 28 - 1 hsw 1 hsw 1 hsw 1 hsw * abs * abs * abs * abs 1 ref 1 ref 0 ref 0 ref 1 swa p 0 swa p 1 swa p 0 swa p d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 palette b palette c segb 126 segc 1 palette c segc 1 segb 127 sega 0 palette c segc 0 segb 1 segc 0 palette a segb 0 palette b segc 0 sega 1 palette a palette b sega 0 segb 0 segc 127 column-address / bit / segment assign x=beh x=bfh x=01h column-address / bit / segment assign x=01h palette c palette a x=bdh x=beh segc 126 sega 127 palette b palette a palette b palette c palette a sega 126 palette b palette a segb 1 palette b sega 1 palette c sega 127 palette c sega 126 palette c segc 127 palette a palette a x=00h column-address / bit / segment assign segb 0 palette b sega 0 palette c x=01h segc 1 palette a segb 1 palette b x=02h sega 1 palette c segc 126 palette a palette c x=bdh segb 126 palette b sega 126 palette c x=beh segc 127 palette a sega 0 palette a x=00h column-address / bit / segment assign segb 0 palette b segc 0 palette c x=01h sega 1 palette a segb 1 palette b x=02h segc 1 palette c sega 126 palette a x=bdh segb 126 palette b segc 126 palette c x=beh sega 127 palette a x=01h segb 127 palette b x=bfh segc 127 palette c segb 127 palette b x=bfh sega 127 x=01h x=02h x=00h x=02h x=00h segb 127 palette b segc 126 palette a segb 126 x=beh x=bfh x=bdh x=beh
NJU6825 - 29 - in the color mode, 8-bit data bus mode, and c256 mode (c256=1) hsw abs ref swap column address / bit / segment assign * * 0 0 x=00 h x=7f h * * 1 1 x=7f h x=00 h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign * * 0 1 x=00 h x=7f h * * 1 0 x=7f h x=00 h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127
NJU6825 - 30 - in the b&w mode, and 16-bit data bus mode hsw abs ref swap column address / bit / segment assign * 0 0 0 x=00 h x=7f h * 0 1 1 x=7f h x=00 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign * 0 0 1 x=00 h x=7f h * 0 1 0 x=7f h x=00 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 hsw abs ref swap column address / bit / segment assign * 1 0 0 x=00 h x=7f h * 1 1 1 x=7f h x=00 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign * 1 0 1 x=00 h x=7f h * 1 1 0 x=7f h x=00 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segc 0 segb 0 sega 0 segc 127 segb 127 sega 127
NJU6825 - 31 - in the b&w mode, and 8-bit data bus mode hsw abs ref swap column address / bit / segment assign 0 0 0 0 x=00 h x=01 h x=fe h x=ff h 0 0 1 1 x=fe h x=ff h x=00 h x=01 h d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign 0 0 0 1 x=00 h x=01 h x=fe h x=ff h 0 0 1 0 x=fe h x=ff h x=00 h x=01 h d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 hsw abs ref swap column address / bit / segment assign 0 1 0 0 x=00 h x=01 h x=fe h x=ff h 0 1 1 1 x=fe h x=ff h x=00 h x=01 h d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign 0 1 0 1 x=00 h x=01 h x=fe h x=ff h 0 1 1 0 x=fe h x=ff h x=00 h x=01 h d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segc 0 segb 0 sega 0 segc 127 segb 127 sega 127
NJU6825 - 32 - 1 hsw 1 hsw 1 hsw 1 hsw * abs * abs * abs * abs 1 ref 1 ref 0 ref 0 ref 1 swa p 0 swa p 1 swa p 0 swa p d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 x=beh x=bfh x=bdh x=beh column-address / bit / segment assign x=01h x=02h x=bdh x=beh x=bfh x=beh x=00h x=00h column-address / bit / segment assign x=01h x=02h x=bfh sega 0 x=bdh segc 126 x=01h x=02h x=00h x=02h x=00h column-address / bit / segment assign x=01h sega 0 column-address / bit / segment assign x=beh x=bfh x=01h x=bdh x=beh x=01h segb 0 segc 0 sega 1 segb 1 segc 1 sega 126 segb 126 segc 126 sega 127 segb 127 segc 127 segc 0 segb 0 sega 0 segc 1 segb 1 sega 1 segc 126 segb 126 sega 126 segc 127 segb 127 sega 127 segc 0 segb 0 segc 1 segb 1 sega 1 segb 126 sega 126 segc 127 segb 127 sega 127 sega 0 segb 0 segc 0 sega 1 segb 1 segc 1 sega 126 segb 126 segc 126 sega 127 segb 127 segc 127
NJU6825 - 33 - bit assignments between write and read data (in the 16-bit data bus mode) abs=0 write data d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 15 d 14 d 13 d 12 * d 10 d 9 d 8 d 7 * * d 4 d 3 d 2 d 1 * abs=1 write data d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data * * * * d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 examples of write and read data (in the 8 bit bus mode) abs=0, hsw=0, c256=0 (address; 00, 02??fc,fe h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 * d 2 d 1 d 0 abs=0, hsw=0, c256=0 (address; 01,03??fd,ff h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 * * d 4 d 3 d 2 d 1 * abs=1, hsw=0, c256=0 (address; 00, 02??fc,fe h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data * * * * d 3 d 2 d 1 d 0 abs=1, hsw=0, c256=0 (address; 01,03??fd,ff h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 abs=0, hsw=1, c256=0 (address; 00, 01??be,bf h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 abs=0, hsw=0, c256=1 (address; 00, 01?? 7e ,7f h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 *: invalid data
NJU6825 - 34 - (11) gradation palette in the gradation mode, either variable or fixed gradation mode is selected by programming the ?pwm? register of the ?gradation control? instruction. pwm=0: variable gradation mode (select 16 gradation levels out of 32-gradation level of the gradation palette) pwm=1: fixed gradation mode (fixed 8-gradation levels) in these mode, each of the gradation palettes aj, bj and cj can select 16-gradation level out of 32-gradation level by setting 5-bit data to the ?pa? registers in the ?gradation palette j? instructions (j=0 to fh). for instance, the gradation palettes aj correspond to the segai, the bj to segbi and the cj to segci (j=0 to 15, i=0 to 127).
NJU6825 - 35 - correspondence between display data and gradation palettes table 10 (palette aj, palette bj, palette cj (j=0 to 15)) (msb) display data (lsb) gradation palette default palette value 0 0 0 0 palette 0 0 0 0 0 0 0 0 0 1 palette 1 0 0 0 1 1 0 0 1 0 palette 2 0 0 1 0 1 0 0 1 1 palette 3 0 0 1 1 1 0 1 0 0 palette 4 0 1 0 0 1 0 1 0 1 palette 5 0 1 0 1 1 0 1 1 0 palette 6 0 1 1 0 1 0 1 1 1 palette 7 0 1 1 1 1 1 0 0 0 palette 8 1 0 0 0 1 1 0 0 1 palette 9 1 0 0 1 1 1 0 1 0 palette10 1 0 1 0 1 1 0 1 1 palette11 1 0 1 1 1 1 1 0 0 palette12 1 1 0 0 1 1 1 0 1 palette13 1 1 0 1 1 1 1 1 0 palette14 1 1 1 0 1 1 1 1 1 palette15 1 1 1 1 1 gradation palette table (variable gradation mode, pwm=?0?, mon=?0?) table 11 (palette aj, palette bj, palette cj (j=0 to 15)) palette value gradation level gradation palette palette value gradation level gradation palette 0 0 0 0 0 0 palette 0(default) 1 0 0 0 0 16/31 0 0 0 0 1 1/31 1 0 0 0 1 17/31 palette 0(default)8 0 0 0 1 0 2/31 1 0 0 1 0 18/31 0 0 0 1 1 3/31 palette 1(default) 1 0 0 1 1 19/31 palette 9(default) 0 0 1 0 0 4/31 1 0 1 0 0 20/31 0 0 1 0 1 5/31 palette 2(default) 1 0 1 0 1 21/31 palette 10(default) 0 0 1 1 0 6/31 1 0 1 1 0 22/31 0 0 1 1 1 7/31 palette 3(default) 1 0 1 1 1 23/31 palette 11(default) 0 1 0 0 0 8/31 1 1 0 0 0 24/31 0 1 0 0 1 9/31 palette 4(default) 1 1 0 0 1 25/31 palette 12(default) 0 1 0 1 0 10/31 1 1 0 1 0 26/31 0 1 0 1 1 11/31 palette 5(default) 1 1 0 1 1 27/31 palette 13(default) 0 1 1 0 0 12/31 1 1 1 0 0 28/31 0 1 1 0 1 13/31 palette 6(default) 1 1 1 0 1 29/31 palette 14(default) 0 1 1 1 0 14/31 1 1 1 1 0 30/31 0 1 1 1 1 15/31 palette 7(default) 1 1 1 1 1 31/31 palette 15(default)
NJU6825 - 36 - gradation palette table (fixed gradation mode, pwm=?1?, mon=?0?) table 12 8-gradation segment drivers (msb) display data (lsb) gradation level (msb) display data (lsb) gradation level 0 0 0 * 0/7 0 0 * * 0 0 1 * 1/7 0 0 * * 0/7 0 1 0 * 2/7 0 1 * * 0 1 1 * 3/7 0 1 * * 3/7 1 0 0 * 4/7 1 0 * * 1 0 1 * 5/7 1 0 * * 5/7 1 1 0 * 6/7 1 1 * * 1 1 1 * 7/7 1 1 * * 7/7 correspondence between display data and gradation level (b&w mode, mon=?1?) table 13 (msb) display data (lsb) gradation level 0 * * * 0 1 * * * 1 *:don?t care
NJU6825 - 37 - (12) gradation control and display data (12-1) gradation mode in the graduation mode, each pixel for rgb corresponds to successive 3 segment drivers, and each segment driver provides 16-gradation pwm output by controlling 4 bit display data of the ddram. accordingly, the lsi can drive up to 128x162 pixels in 4096-color (16-gradation x 16-gradation x 16- gradation = 4-bit x 4-bit x 4-bit). in addition, the lsi can transfer the display data for the rgb by 16-bit at once or 8-bit two-times. the data assignment between gradation palettes and segment drivers varies in accordance with setting for the ?swap? and ?ref? registers of the "display control (2)" instruction. (ref, swap)=(0, 0) or (1, 1) (i=0 to 127) note) ddram column address :2n h ,2n h +1 h (ref=?0?) :fe h -2n h , ff h -(2n h +1 h ) (ref=?1?) hsw=1; 00 h to bf h , c256=1; 00 h to 7f h gradation palette j =0 to 15 dis p la y data from mpu gradation control circuit display data in ddram msb lsb msb lsb msb lsb paltte aj palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 d 7 d 6 d 4 d 5 d 2 d 1 d 0 d 7 d 4 d 3 d 1 d 2 column address:2n h :2n+1 h ( d 3 d 2 d 0 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 ( d 7 d 6 d 4 d 5 d 3 d 2 d 1 d 0 d 7 d 6 d 4 ) d 5 hsw=1 ( d 7 d 6 * d 5 d 4 d 3 d 2 *d 1 d 0 * ) * c256=1 segai segbi segci
NJU6825 - 38 - (ref, swap)=(0, 1) or (1, 0) note) ddram column address : 2n h ,2n h +1 h (ref=?0?) : fe h -2n h , ff h -(2n h +1 h ) (ref=?1?) hsw=1; 00 h to bf h, c256=; 00 h to 7f h in the 16-bit data bus mode, the data assignments between the gradation palettes and the segment drivers vary in accordance with setting for the ?swap? and ?ref? bit of the "display control (2)" instruction as well as the assignment in the 8-bit data bus mode. (ref, swap)=(0, 0) or (1, 1) note) ddram column address :n h (ref=?0?) :7f h - n h (ref=?1?) gradation palette j =0 to 15 dis p la y data from mpu gradation control circuit display data in ddram segai segbi segci column address:2n h :2n+1 h (i=0 to 127) lsb msb lsb msb lsb msb palette aj palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 d 7 d 6 d 4 d 5 d 2 d 1 d 0 d 7 d 4 d 3 d 1 d 2 ( d 7 d 6 * d 5 d 4 d 3 d 2 * d 1 d 0 * ) * c256=1 ( d 3 d 2 d 0 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 ( d 7 d 6 d 4 d 5 d 3 d 2 d 1 d 0 d 7 d 6 d 4 ) d 5 hsw=1 segai segbi segci (i=0 to 127) msb lsb msb lsb msb gradation palette j =0 to 15 display data from mpu gradation control circuit display data in ddram lsb palette aj palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 column address ; n h
NJU6825 - 39 - gradation palette j =0 to 15 i= ( 0 to 127 ) dis p la y data from mpu gradation control circuit display data in ddram lsb msb lsb msb lsb msb segai segbi segci palette aj palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 d 1 5 d 14 d 12 d 1 3 d 1 0 d 9 d 8 d 7 d 4 d 3 d 1 d 2 column address ; n h ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 (ref, swap)=(0, 1) or (1, 0) note) ddram column address :n h (ref=?0?) :7f h -n h (ref=?1?)
NJU6825 - 40 - (12-2) b&w mode (mon=?1?) in the b&w mode, 3 bits of the msb data are used in both of the 16-bit and 8-bit data bus modes. in the 16-bit data bus mode (similarly 8-bit data bus access) (ref, swap)=(0, 0) or (1, 1) note) ddram column address : n h (ref=?0?) : 7f h -n h (ref=?1?) (ref, swap)=(0, 1) or (1, 0) note ) ddram column address : n h (ref=?0?) : 7f h -n h (ref=?1?) segai segbi segci msb lsb msb lsb msb gradation palette j =0 to 15 (i=0 to 127) dis p la y data in ddram gradation control circuit display data in ddram lsb palette aj palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 column address; n h d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 gradation palette j =0 to 15 (i=0 to 127) dis p la y data in ddram gradation control circuit display data in ddram lsb msb lsb msb lsb msb segai segbi segci palette aj palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 column address; n h d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 1 0 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1
NJU6825 - 41 - (13) display timing generator the display-timing generator creates the timing pulses such as the cl, the flm, the fr and the clk by dividing the oscillation frequency oscillate an external or internal resister mode. the each of timing pulses is outputted through the each output terminals by ?son? = 1. (14) lcd line clock (cl) the lcd line clock (cl) is used as a count-up signal for the line counter and a latch signal for the data latch circuit. at the rising edge of the cl signal, the line counter is counted-up and the 384-bit display data, corresponding to this line address, is latched into the data latch circuit. and at the falling edge of the cl signal, this latched data output on the segment drivers. read out timing of the display data, from ddram to the latch circuits is completely independent of the access timing to the mpu. for this reason, the mpu can access to the lsi regardless of an internal operation. (15) lcd alternate signal (fr) and lcd synchronous signal (flm) the fr and flm signals are created from the cl signal. the fr signal is used to alternate the crystal polarization on a lcd panel. it is programmed that the fr signal is toggle on every frame in the default setting or once every n lines in the n-line inversion mode. the flm signal is used to indicate a start line of a new display frame. it presets an initial display line address of the line counter when the flm signal becomes ?1?. (16) data latch circuit the data latch circuit is used temporarily store the display data that will output to the segment drivers. the display data in this circuit is updated in synchronization of the cl signal. the ?all pixels on/off?, ?display on/off? and ?reverse display on/off? instructions change the display data in this circuit but do not change the display data of the ddram.
NJU6825 - 42 - lcd driving waveforms (in the b&w mode, reverse display off, 1/163 duty) fig 8 com 1 com 0 seg 1 seg 0 seg 2 com 1 com 0 v 1 v 2 cl v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss seg 1 seg 0 v lcd v 3 v 4 v ss fr flm 163 1 2 4 35 163 12 4 35 163 1
NJU6825 - 43 - (17) common and segment drivers the lsi includes 384-segment drivers and 162-common drivers. the common drivers generate the lcd driving waveforms composed of the v lcd , v 1 , v 4 and v ss in accordance with the fr signal and scanning data. the segment drivers generate waveforms composed of the v lcd , v 2 , v 3 and v ss in accordance with the fr signal and display data. (18) oscillator the oscillator generates internal clocks for the display timing and the voltage booster. since the lsi has internal capacitor (c) and resistor (r) for the oscillation, external capacitor and resistor are not usually required. however, in case that an external resistor is used, the resister is connected between the osc 1 and osc 2 terminals. the external resistor becomes enabled by setting ?1? to the ?cks? register of ?data bus length? instruction. when the internal oscillator is not used, the external clocks with 50% duty cycle ratio must be input to the osc 1 terminal. in addition, the feed back resister for the oscillation is varied by programming the ?rf? register of the ?frequency control? instruction, so that it is possible to optimize the frame frequency for a lcd panel. setting examples of the mon (b&w /gradation) and the pwm (variable gradation /fixed gradation) are described, as follows. (18-1) internal oscillation mode (cks=0) symbol mon pwm display mode f 1 0 0 variable gradation mode f 2 0 1 fixed gradation mode f 3 1 * b&w mode *: don?t care (18-2) external resistor oscillation mode(cks=1) the internal clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the ?mon? and ?pwm? registers must be set as well. (18-3) external clock input mode (cks=1) the external clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the ?mon? and ?pwm? registers must be set as well. (19) power supply circuits the internal power supply circuits are composed of the voltage booster, the electrical variable resister (evr), the voltage regulator, reference voltage generator and the voltage followers. the condition of the power supply circuits is arranged by programming the ?dcon? and ?ampon? registers on the ?power control? instruction. for this arrangement, some parts of the internal power supply circuits are activated in using an external power supply, as shown in the following table. table 14 dcon ampon voltage booster voltage followers voltage regulator evr external voltage note 0 0 disable disable v out , v lcd , v 1 , v 2 , v 3 , v 4 1, 3 0 1 disable enable v out 2, 3 1 1 enable enable ? ? note1) the internal power circuits are not used. the external v out is required and the c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 +, c 5 -, c 6 +, c 6 -, v ref , v reg and v ee terminals must be open. note2) the internal power circuits except the voltage booster are used. the external v out is required and the c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 +, c 5 -, c 6 +, c 6 - and v ee terminals must be open. the reference voltage is required to v ref terminal. note3) the relation among the voltages should be maintained as follows. v out v lcd v 1 v 2 v 3 v 4 v ss
NJU6825 - 44 - (20) voltage booster the voltage booster generates maximum 7x voltage of the v ee level. it is programmed so that the boost level is selected out of 1x, 2x, 3x, 4x, 5x, 6x and 7x by the ?boost level select? instruction. the boosted voltage v out must not exceed beyond the value of 18.0v, otherwise the voltage stress may cause a permanent damage to the lsi. boosted voltages capacitor connections for the voltage booster 7-time boost 6-time boost 5-time boost 4-time boost 3-time boost 2-time boost fig 9 3-time boost 7-time boost v ss =0v v ee =3v v out =9v v out =17.5v v ss =0v v ee =2.5v c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v out + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v out + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v out + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v out + + + + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v out + + + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v out + + + + +
NJU6825 - 45 - (21) reference voltage generator the reference voltage generator is used to produce the reference voltage (v ba ), which is output from the v ba terminal and should be input to the v ref terminal. v ba = v ee x 0.9 (22) voltage regulator the voltage regulator, composed of the gain control circuit and an operational amplifier, and is used to gain the reference voltage (v ref ) and to create the regulated voltage (v reg ). the v reg is used as an input voltage to the evr circuit, which is programmed by the ?vu? register of the ?boost level? instruction. v reg = v ref x n (n: register value for the boost level) (23) electrical variable resister (evr) the evr is variable within 128-step, and is used to fine-tune the lcd driving voltage (v lcd ) by programming the ?dv? register in the ?evr control? instruction, so that it is possible to optimize the contrast level for a lcd panels. v lcd = 0.5 x v reg + m (v reg - 0.5 x v reg ) / 127 (m: register value for the evr) (24) lcd driving voltage generation circuit lcd driving voltage generation circuit generates the v lcd voltage levels as v lcd , v 1 , v 2 , v 3 and v 4 with internal e.v.r and the bleeder resistors. the bias ratio of the lcd driving voltage is selected out of 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11 and 1/12. in using the internal power supply, the capacitors ca 2 must be connected to the v lcd , v 1 , v 2 , v 3 and v 4 terminals, and the ca 2 value must be determined by the evaluation with actual lcd modules. in using the internal power supply, the external lcd driving voltages such as the v lcd , v 1 , v 2 , v 3 and v 4 are supplied and the external power supply circuits must be set to ?off? by dcon = ampon = "0". in this mode, voltage booster terminals such as c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 +, c 5 -, c 6 +, c 6 -, v ee , v ref and v reg must be opened. in case that the voltage booster is not used but only some parts of internal power supply circuits (voltage followers, voltage regulator and evr) are used, the c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 +, c 5 -, c 6 + and c 6 - terminals must be opened. and, the external power supply is input to the v out terminal, and the reference voltage to the v ref terminal. the capacitor ca 3 must connect to the v reg terminal for voltage stabilization.
NJU6825 - 46 - connections of the capacitors for the voltage boost fig 10 fig11 reference values ca 1 1.0 to 4.7 f ca 2 1.0 to 2.2 f ca 3 0.1 f note1) b grade capacitor is recommended for ca 1 -ca 3 . testing actual samples with an lcd panel is recommended to decide an optimum value of these capacitors. note2) parasitic resistance on the power supply lines (v dd , v ss , v ee , v ssh , v out , v lcd , v 1 , v 2 , v 3 and v 4 ) reduces the step-up efficiency of the voltage booster, and may have an impact on the lsi?s operation and display quality. to minimize this impact, use the shortest possible wires and place the capacitors to be as close as possible to the lsi. using only external power supply circuits using all of the internal power supply circuits (7-time boost) v 1 v 2 v 3 v 4 ca 3 v s ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 1 ca 1 v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd ca 2 ca 2 ca 2 ca 2 c 5 - c 5 + c 6 - c 6 + NJU6825 ca 3 v s v dd ca 1 v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 v lcd v 1 v 2 v 3 v 4 external power circuit c 5 - c 5 + c 6 - c 6 + NJU6825 v dd ca 1 ca 1 ca 2 ca 2 ca 2 ca 2
NJU6825 - 47 - fig 12 fig 13 reference value ca 1 1.0 to 4.7 f ca 2 1.0 to 2.2 f ca 3 0.1 f note1) b grade capacitor is recommended for ca 1 -ca 3 . testing actual samples with an lcd panel is recommended to decide an optimum value of these capacitors. note2) parasitic resistance on the power supply lines (v dd , v ss , v ee , v ssh , v out , v lcd , v 1 , v 2 , v 3 and v 4 ) reduces the step-up efficiency of the voltage booster, and may have an impact on the lsi?s operation and display quality. to minimize this impact, use the shortest possible wires and place the capacitors to be as close as possible to the lsi. using internal power supply circuits without the reference voltage generator(1) (7-time boost) using internal power supply circuit without the reference voltage generator(2) (7-time boost) v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 2 ca 2 ca 2 ca 2 c 5 - c 5 + c 6 - c 6 + ca 1 ca 1 NJU6825 v dd ca 1 thermistor v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 2 ca 2 ca 2 ca 2 c 5 - c 5 + c 6 - c 6 + ca 1 ca 1 NJU6825 v dd ca 1
NJU6825 - 48 - fig 14 reference value ca 1 1.0 to 4.7 f ca 2 1.0 to 2.2 f ca 3 0.1 f note1) b grade capacitor is recommended for ca 1 -ca 3 . testing actual samples with an lcd panel is recommended to decide an optimum value of these capacitors. note2) parasitic resistance on the power supply lines (v dd , v ss , v ee , v ssh , v out , v lcd , v 1 , v 2 , v 3 and v 4 ) reduces the step-up efficiency of the voltage booster, and may have an impact on the lsi?s operation and display quality. to minimize this impact, use the shortest possible wires and place the capacitors to be as close as possible to the lsi. . using internal power supply circuits without the voltage booster external power circuit ca 3 v ss v ss ca 2 ca 2 ca 2 ca 3 v ss v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 ca 2 ca 2 c 5 - c 5 + c 6 - c 6 + NJU6825 v dd c a 1 c a 1
NJU6825 - 49 - (25) partial display function the partial display function is used to partially specify some parts of display area on lcd panels. by using this function, lcd modules can work in lower duty cycle ratio, lower lcd bias ratio, lower boost level and lower lcd driving voltage. it is usually used to display a time and calendar, and is also used to optimize the lsi condition in accordance with the display size. it can be programmed to select the duty cycle ratio (1/16, 1/24, 1/32, 1/40, 1/48, 1/56, 1/64, 1/72, 1/80, 1/96, 1/112, 1/128, 1/133, 1/144, 1/160, 1/163 in case ?dse? is ?0?), the lcd bias ratio, the boost level and the evr value by the instructions. partial display image normal display partial display partial display sequence - boost level - evr value - lcd bias ratio - duty cycle ratio - initial display line - initial com line - other instructions njrc lcd driver low power and low voltage lcd driver optional status display off (on/off=?0?) internal power supply off (dcon=?0?, ampon=?0?) wait setting for lcd driving voltage-related functions setting for display-related functions internal power supply on (dcon=?1?, ampon=?1?) wait display on (on/off =?1?) partial display status
NJU6825 - 50 - (26) discharge circuit discharge circuit is used to discharge the electric charge of the capacitors on the v 1 to v 4 and v lcd terminals. this circuit is activated by setting ?0? to the ?dis? register of the ?discharge? instruction or by setting ?resb? terminal to ?0? level. the ?discharge on/off? instruction is usually required just after the internal power supply is turned off by setting ?0? into the ?dcon? and ?ampon? registers, or just after the external power supply is turned off. during the discharge operation, the internal or external power supply must not be turned on. (27) reset circuit the reset circuit initializes the lsi into the following default status. it is activated by setting the resb terminal to ?0? . the resb terminal is usually required to connect to the mpu reset terminal in order that the lsi can be initialized at the same timing of the mpu. default status 1. ddram display data :undefined 2. column address :(00) h 3. row address :(00) h 4. initial display line :(0) h (1st line) 5. display on/off :off 6. reverse display on/off :off (normal) 7. duty cycle ratio :1/163 duty (dse=0) 8. n-line inversion on/off :off 9. com scan direction :com 0 com 161 10. increment mode :off 11. reverse seg direction :off (normal) 12. swap mode :off (normal) 13. evr value :(0, 0, 0, 0, 0, 0, 0) 14. internal power supply :off 15. display mode :gradation display mode 16. lcd bias ratio :1/9 bias 17. gradation palette 0 :(0, 0, 0, 0, 0) 18. gradation palette 1 :(0, 0, 0, 1, 1) 19. gradation palette 2 :(0, 0, 1, 0, 1) 20. gradation palette 3 :(0, 0, 1, 1, 1) 21. gradation palette 4 :(0, 1, 0, 0, 1) 22. gradation palette 5 :(0, 1, 0, 1, 1) 23. gradation palette 6 :(0, 1, 1, 0, 1) 24. gradation palette 7 :(0, 1, 1, 1, 1) 25. gradation palette 8 :(1, 0, 0, 0, 1) 26. gradation palette 9 :(1, 0, 0, 1, 1) 27. gradation palette 10 :(1, 0, 1, 0, 1) 28. gradation palette 11 :(1, 0, 1, 1, 1) 29. gradation palette 12 :(1, 1, 0, 0, 1) 30. gradation palette 13 :(1, 1, 0, 1, 1) 31. gradation palette 14 :(1, 1, 1, 0, 1) 32. gradation palette 15 :(1, 1, 1, 1, 1) 33. gradation mode control :variable gradation mode 34. data bus length :8-bit data bus length 35. discharge circuit :off
NJU6825 - 51 - (28) power supply on/off sequences the following paragraphs describe power supply on/off sequences, which are to protect the lsi from over current. (28-1) using an external power supply power supply on sequence logic voltage (v dd ) must be always input first, and next the lcd driving voltages (v 1 to v 4 and v lcd ) are turned on. in using the external v out , the v dd must be input first, next the reset operation must be performed, and finally the v out can be input. power supply off sequence either the reset operation, cutting off the v 1 to v 4 and v lcd from the lsi by the resb terminal or the ?power control? instruction must be performed first, and next the v dd is turned off. it is recommended that a series-resister between 50 ? and 100 ? is added on the v lcd line (or v out line in using only the external v out voltage) in order to protect the lsi from the over current. (28-2) using the internal power supply circuits power supply on sequence the v dd must be input first, next the reset operation must be performed, and finally the v 1 to v 4 and v lcd can be turned on by setting ?1? to the ?dcon? and ?ampon? registers of the ?power control? instruction. power supply off sequence either the reset operation by the resb terminal or the ?power control? instruction must be performed first, and next the input voltage for the voltage booster (v ee ) and the v dd can be turned off. if the v ee is supplied from different power sources for v dd , the v ee is turned off first, and next the v dd is turned off.
NJU6825 - 52 - (29) referential instruction sequences (29-1) initialization in using the internal power supply circuits - evr value - lcd bias ratio - power control (dcon=?1?, ampon=?1?) (29-2) display data writing - initial display line - increment mode - column address - row address v dd , v ee power on wait for power-on stabilization reset input wait setting for lcd driving voltage-related functions end of initialization end of initialization setting for display-related functions display on (on/off =?1?) display data write
NJU6825 - 53 - (29-3) power off - all com/seg output v ss level. optional status power save or reset operation v ee , v dd power off wait discharge on
NJU6825 - 54 - (30) instruction table instruction table (1) code (80 series mpu i/f) code functions instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 display data write 0 0 1 0 0/1 0/1 0/1 write data write display data to ddram display data read 0 0 0 1 0/1 0/1 0/1 read data read display data from ddram column address (lower) [0 h ] 0 1 1 0 0 0 0 0 0 0 0 ax3 ax2 ax1 ax0 ddram column address column address (upper) [1 h ] 0 1 1 0 0 0 0 0 0 0 1 ax7 ax6 ax5 ax4 ddram column address row address (lower) [2 h ] 0 1 1 0 0 0 0 0 0 1 0 ay3 ay2 ay1 ay0 ddram row address row address (upper) [3 h ] 0 1 1 0 0 0 0 0 0 1 1 ay7 ay6 ay5 ay4 ddram row address initial display line (lower) [4 h ] 0 1 1 0 0 0 0 0 1 0 0 la3 la2 la1 la0 row address for an initial com line (scan start line) initial display line (upper) [5 h ] 0 1 1 0 0 0 0 0 1 0 1 la7 la6 la5 la4 row address for an initial com line (scan start line) n-line inversion (lower) [6 h ] 0 1 1 0 0 0 0 0 1 1 0 n3 n2 n1 n0 the number of n-line inversion n-line inversion (upper) [7 h ] 0 1 1 0 0 0 0 0 1 1 1 n7 n6 n5 n4 the number of n-line inversion display control (1) [8 h ] 0 1 1 0 0 0 0 1 0 0 0 shift mon all on on/ off shift: common direction mon: gradation or b/w display mode allon: all pixels on/off on/off: display on/off display control (2) [9 h ] 0 1 1 0 0 0 0 1 0 0 1 rev nlin swap ref rev: reverse display on/off nlin: n-line inversion on/off, swap: swap mode on/off ref: segment direction increment control [a h ] 0 1 1 0 0 0 0 1 0 1 0 win aim ayi axi win: window addressing mode on/off aim: read-modify-write on/off ayi: row auto-increment mode on/off axi: column auto-increment mode on/off power control [b h ] 0 1 1 0 0 0 0 1 0 1 1 amp on halt dc on acl ampon: voltage followers on/off halt: power save on/off dcon: voltage booster on/off acl: reset duty cycle ratio [c h ] 0 1 1 0 0 0 0 1 1 0 0 ds3 ds2 ds1 ds0 sets lcd duty cycle ratio boost level [d h ] 0 1 1 0 0 0 0 1 1 0 1 * vu2 vu1 vu0 sets boost level lcd bias ratio [e h ] 0 1 1 0 0 0 0 1 1 1 0 * b2 b1 b0 sets lcd bias ratio re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6825 - 55 - instruction table (2) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette a0/a8 (lower) [0 h ] 0 1 1 0 0 0 1 0 0 0 0 pa03/ pa83 pa02/ pa82 pa01/ pa81 pa00/ pa80 sets palette values to gradation palette a0(ps=0)/a8(ps=1) gradation palette a0/a8 (upper) [1 h ] 0 1 1 0 0 0 1 0 0 0 1 * * * pa04/ pa84 sets palette values to gradation palette a0(ps=0)/a8(ps=1) gradation palette a1/a9 (lower) [2 h ] 0 1 1 0 0 0 1 0 0 1 0 pa13/ pa93 pa12/ pa92 pa11/ pa91 pa10/ pa90 sets palette values to gradation palette a1(ps=0)/a9(ps=1) gradation palette a1/a9 (upper) [3 h ] 0 1 1 0 0 0 1 0 0 1 1 * * * pa14/ pa94 sets palette values to gradation palette a1(ps=0)/a9(ps=1) gradation palette a2/a10 (lower) [4 h ] 0 1 1 0 0 0 1 0 1 0 0 pa23/ pa103 pa22/ pa102 pa21/ pa101 pa20/ pa100 sets palette values to gradation palette a2(ps=0)/a10(ps=1) gradation palette a2/a10 (upper) [5 h ] 0 1 1 0 0 0 1 0 1 0 1 * * * pa24/ pa104 sets palette values to gradation palette a2(ps=0)/a10(ps=1) gradation palette a3/a11 (lower) [6 h ] 0 1 1 0 0 0 1 0 1 1 0 pa33/ pa113 pa32/ pa112 pa31/ pa111 pa30/ pa110 sets palette values to gradation palette a3(ps=0)/a11(ps=1) gradation palette a3/a11 (upper) [7 h ] 0 1 1 0 0 0 1 0 1 1 1 * * * pa34/ pa114 sets palette values to gradation palette a3(ps=0)/a11(ps=1) gradation palette a4/a12 (lower) [8 h ] 0 1 1 0 0 0 1 1 0 0 0 pa43/ pa123 pa42/ pa122 pa41/ pa121 pa40/ pa120 sets palette values to gradation palette a4(ps=0)/a12(ps=1) gradation palette a4/a12 (upper) [9 h ] 0 1 1 0 0 0 1 1 0 0 1 * * * pa44/ pa124 sets palette values to gradation palette a4(ps=0)/a12(ps=1) gradation palette a5/a13 (lower) [a h ] 0 1 1 0 0 0 1 1 0 1 0 pa53/ pa133 pa52/ pa132 pa51/ pa131 pa50/ pa130 sets palette values to gradation palette a5(ps=0)/a13(ps=1) gradation palette a5/a13 (upper) [b h ] 0 1 1 0 0 0 1 1 0 1 1 * * * pa54/ pa134 sets palette values to gradation palette a5(ps=0)/a13(ps=1) gradation palette a6/a14 (lower) [c h ] 0 1 1 0 0 0 1 1 1 0 0 pa63/ pa143 pa62/ pa142 pa61/ pa141 pa60/ pa140 sets palette values to gradation palette a6(ps=0)/a14(ps=1) gradation palette a6/a14 (upper) [d h ] 0 1 1 0 0 0 1 1 1 0 1 * * * pa64/ pa144 sets palette values to gradation palette a6(ps=0)/a14(ps=1) re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6825 - 56 - instruction table (3) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette a7/a15 (lower) [0 h ] 0 1 1 0 0 1 0 0 0 0 0 pa73/ pa153 pa72/ pa152 pa71/ pa151 pa70/ pa150 sets palette values to gradation palette a7(ps=0)/a15(ps=1) gradation palette a7/a15 (upper) [1 h ] 0 1 1 0 0 1 0 0 0 0 1 * * * pa74/ pa154 sets palette values to gradation palette a7(ps=0)/a15(ps=1) gradation palette b0/b8 (lower) [2 h ] 0 1 1 0 0 1 0 0 0 1 0 pb03/ pb83 pb02/ pb82 pb01/ pb81 pb00/ pb80 sets palette values to gradation palette b0(ps=0)/b8(ps=1) gradation palette b0/b8 (upper) [3 h ] 0 1 1 0 0 1 0 0 0 1 1 * * * pb04/ pb84 sets palette values to gradation palette b0(ps=0)/b8(ps=1) gradation palette b1/b9 (lower) [4 h ] 0 1 1 0 0 1 0 0 1 0 0 pb13/ pb93 pb12/ pb92 pb11/ pb91 pb10/ pb90 sets palette values to gradation palette b1(ps=0)/b9(ps=1) gradation palette b1/b9 (upper) [5 h ] 0 1 1 0 0 1 0 0 1 0 1 * * * pb14/ pb94 sets palette values to gradation palette b1(ps=0)/b9(ps=1) gradation palette b2/b10 (lower) [6 h ] 0 1 1 0 0 1 0 0 1 1 0 pb23/ pb103 pb22/ pb102 pb21/ pb101 pb20/ pb100 sets palette values to gradation palette b2(ps=0)/b10(ps=1) gradation palette b2/b10 (upper) [7 h ] 0 1 1 0 0 1 0 0 1 1 1 * * * pb24/ pb104 sets palette values to gradation palette b2(ps=0)/b10(ps=1) gradation palette b3/b11 (lower) [8 h ] 0 1 1 0 0 1 0 1 0 0 0 pb33/ pb113 pb32/ pb112 pb31/ pb111 pb30/ pb110 sets palette values to gradation palette b3(ps=0)/b11(ps=1) gradation palette b3/b11 (upper) [9 h ] 0 1 1 0 0 1 0 1 0 0 1 * * * pb34/ pb114 sets palette values to gradation palette b3(ps=0)/b11(ps=1) gradation palette b4/b12 (lower) [a h ] 0 1 1 0 0 1 0 1 0 1 0 pb43/ pb123 pb42/ pb122 pb41/ pb121 pb40/ pb120 sets palette values to gradation palette b4(ps=0)/b12(ps=1) gradation palette b4/b12 (upper) [b h ] 0 1 1 0 0 1 0 1 0 1 1 * * * pb44/ pb124 sets palette values to gradation palette b4(ps=0)/b12(ps=1) gradation palette b5/b13 (lower) [c h ] 0 1 1 0 0 1 0 1 1 0 0 pb53/ pb133 pb52/ pb132 pb51/ pb131 pb50/ pb130 sets palette values to gradation palette b5(ps=0)/b13(ps=1) gradation palette b5/b13 (upper) [d h ] 0 1 1 0 0 1 0 1 1 0 1 * * * pb54/ pb134 sets palette values to gradation palette b5(ps=0)/b13(ps=1) re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6825 - 57 - instruction table (4) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette b6/b14 (lower) [0 h ] 0 1 1 0 0 1 1 0 0 0 0 pb63/ pb143 pb62/ pb142 pb61/ pb141 pb60/ pb140 sets palette values to gradation palette b6(ps=0)/b14(ps=1) gradation palette b6/b14 (upper) [1 h ] 0 1 1 0 0 1 1 0 0 0 1 * * * pb64/ pb144 sets palette values to gradation palette b6(ps=0)/b14(ps=1) gradation palette b7/b15 (lower) [2 h ] 0 1 1 0 0 1 1 0 0 1 0 pb73/ pb153 pb72/ pb152 pb71/ pb151 pb70/ pb150 sets palette values to gradation palette b7(ps=0)/b15(ps=1) gradation palette b7/b15 (upper) [3 h ] 0 1 1 0 0 1 1 0 0 1 1 * * * pb74/ pb154 sets palette values to gradation palette b7(ps=0)/b15(ps=1) gradation palette c0/c8 (lower) [4 h ] 0 1 1 0 0 1 1 0 1 0 0 pc03/ pc83 pc02/ pc82 pc01/ pc81 pc00/ pc80 sets palette values to gradation palette c0(ps=0)/c8(ps=1) gradation palette c0/c8 (upper) [5 h ] 0 1 1 0 0 1 1 0 1 0 1 * * * pc04/ pc84 sets palette values to gradation palette c0(ps=0)/c8(ps=1) gradation palette c1/c9 (lower) [6 h ] 0 1 1 0 0 1 1 0 1 1 0 pc13/ pc93 pc12/ pc92 pc11/ pc91 pc10/ pc90 sets palette values to gradation palette c1(ps=0)/c9(ps=1) gradation palette c1/c9 (upper) [7 h ] 0 1 1 0 0 1 1 0 1 1 1 * * * pc14/ pc94 sets palette values to gradation palette c1(ps=0)/c9(ps=1) gradation palette c2/c10 (lower) [8 h ] 0 1 1 0 0 1 1 1 0 0 0 pc23/ pc103 pc22/ pc102 pc21/ pc101 pc20/ pc100 sets palette values to gradation palette c2(ps=0)/c10(ps=1) gradation palette c2/c10 (upper) [9 h ] 0 1 1 0 0 1 1 1 0 0 1 * * * pc24/ pc104 sets palette values to gradation palette c2(ps=0)/c10(ps=1) gradation palette c3/c11 (lower) [a h ] 0 1 1 0 0 1 1 1 0 1 0 pc33/ pc113 pc32/ pc112 pc31/ pc111 pc30/ pc110 sets palette values to gradation palette c3(ps=0)/c11(ps=1) gradation palette c3/c11 (upper) [b h ] 0 1 1 0 0 1 1 1 0 1 1 * * * pc34/ pc114 sets palette values to gradation palette c3(ps=0)/c11(ps=1) gradation palette c4/c12 (lower) [c h ] 0 1 1 0 0 1 1 1 1 0 0 pc43/ pc123 pc42/ pc122 pc41/ pc121 pc40/ pc120 sets palette values to gradation palette c4(ps=0)/c12(ps=1) gradation palette c4/c12 (upper) [d h ] 0 1 1 0 0 1 1 1 1 0 1 * * * pc44/ pc124 sets palette values to gradation palette c4(ps=0)/c12(ps=1) re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6825 - 58 - instruction table (5) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette c5/c13 (lower) [0 h ] 0 1 1 0 1 0 0 0 0 0 0 pc53/ pc133 pc52/ pc132 pc51/ pc131 pc50/ pc130 sets palette values to gradation palette c5(ps=0)/c13(ps=1) gradation palette c5/c13 (upper) [1 h ] 0 1 1 0 1 0 0 0 0 0 1 * * * pc54/ pc134 sets palette values to gradation palette c5(ps=0)/c13(ps=1) gradation palette c6/c14 (lower) [2 h ] 0 1 1 0 1 0 0 0 0 1 0 pc63/p c143 pc62/ pc142 pc61/ pc141 pc60/ pc140 sets palette values to gradation palette c6(ps=0)/c14(ps=1) gradation palette c6/c14 (upper) [3 h ] 0 1 1 0 1 0 0 0 0 1 1 * * * pc64/ pc154 sets palette values to gradation palette c6(ps=0)/c14(ps=1) gradation palette c7/c15 (lower) [4 h ] 0 1 1 0 1 0 0 0 1 0 0 pc73/ pc153 pc72/ pc152 pc71/ pc151 pc70/ pc150 sets palette values to gradation palette c7(ps=0)/c15(ps=1) gradation palette c7/c15 (upper) [5 h ] 0 1 1 0 1 0 0 0 1 0 1 * * * pc74/ pc154 sets palette values to gradation palette c7(ps=0)/c15(ps=1) initial com line [6 h ] 0 1 1 0 1 0 0 0 1 1 0 sc3 sc2 sc1 sc0 sets scan-starting common driver display control signal/ duty select [7 h ] 0 1 1 0 1 0 0 0 1 1 1 * * dse son son : display clock on/off dse : duty-1 on/off gradation mode control [8 h ] 0 1 1 0 1 0 0 1 0 0 0 pwm c256 fdc1 fdc2 pwm : variable/fixed gradation mode c256 : 256-color mode on/off fdc : boost clock data bus length [9 h ] 0 1 1 0 1 0 0 1 0 0 1 hsw abs cks wls hsw : high speed access on/off abs : abs m ode on/off cks : internal/external oscilation wls : display data length evr control (lower) [a h ] 0 1 1 0 1 0 0 1 0 1 0 dv3 dv2 dv1 dv0 sets evr level (lower bit) evr control (upper) [b h ] 0 1 1 0 1 0 0 1 0 1 1 * dv6 dv5 dv4 sets evr level (upper bit) frequency control [d h ] 0 1 1 0 1 0 0 1 1 0 1 * rf2 rf1 rf0 oscillation frequency discharge on/off [e h ] 0 1 1 0 1 0 0 1 1 1 0 * * * dis discharge the electric charge in capacitors on v 1 to v 4 and v lcd re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag instruction register address [c h ] 0 1 1 0 1 0 0 1 1 0 0 reading address sets instruction register address instruction register read 0 1 0 1 0/1 0/1 0/1 * * * * read data read out instruction register data note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. note 4) cks=0: internal oscillation mode (default) cks=1: external oscillation mode
NJU6825 - 59 - instruction table (6) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions window end column address (lower) [0 h ] 0 1 1 0 1 0 1 0 0 0 0 ex3 ex2 ex1 ex0 sets column address for end point window end column address (upper) [1 h ] 0 1 1 0 1 0 1 0 0 0 1 ex7 ex6 ex5 ex4 sets column address for end point window end row address (lower) [2 h ] 0 1 1 0 1 0 1 0 0 1 0 ey3 ey2 ey1 ey0 sets row address for end point window end row address (upper) [3 h ] 0 1 1 0 1 0 1 0 0 1 1 ey7 ey6 ey5 ey4 sets row address for end point initial reverse line (lower) [4 h ] 0 1 1 0 1 0 1 0 1 0 0 ls3 ls2 ls1 ls0 sets address for reverse line initial reverse line (upper) [5 h ] 0 1 1 0 1 0 1 0 1 0 1 ls7 ls6 ls5 ls4 sets address for reverse line last reverse line (lower) [6 h ] 0 1 1 0 1 0 1 0 1 1 0 le3 le2 le1 le0 sets address for reverse line last reverse line (upper) [7 h ] 0 1 1 0 1 0 1 0 1 1 1 le7 le6 le5 le4 sets address for reverse line reverse line display on/off [8 h ] 0 1 1 0 1 0 1 1 0 0 0 * * bt lrev bt : blink type setting lrev : reverse line display on/off gradation palette setting control [9 h ] 0 1 1 0 1 0 1 1 0 0 1 * * * ps upper 8 gradation setting lower 8 gradation setting pwm control [a h ] 0 1 1 0 1 0 1 1 0 1 0 pwm s pwm a pwm b pwm c sets pwm mode re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6825 - 60 - (31) instruction descriptions this chapter provides detail descriptions and instruction registers. nonexistent instruction codes must not be set into the lsi. (31-1) display data write the ?display data write? instruction is used to write 8-bit display data into the ddram. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 0/1 0/1 0/1 display data (31-2) display data read the ?display data read? instruction is used to read out 8-bit display data from the ddram, where the column address and row address must be specified beforehand by the ?column address? and ?row address? instructions. the dummy read is required just after the ?column address? and ?row address? instructions. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 0/1 0/1 0/1 display data (31-3) column address the ?column address? instruction is used to specify the column address for the display data?s reading and writing operations. it requires dual bytes for lower 4-bit and upper 4-bit data. the instruction for the lower 4-bit data must be executed first, next the instruction for the upper 4-bit. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 0 0 ax 3 ax 2 ax 1 ax 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 0 1 ax 7 ax 6 ax 5 ax 4 (31-4) row address the ?row address? instruction is used to specify the row address for the display data read and write operations. it requires dual bytes for lower 4-bit and upper 4-bit data. the instruction for the lower 4-bit data must be executed first, next the instruction for upper 4-bit. the row address is specified in between 00 h and a1 h . the setting for nonexistent row address between a2 h and ff h is prohibited. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 1 0 ay 3 ay 2 ay 1 ay 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 1 1 ay 7 ay 6 ay 5 ay 4
NJU6825 - 61 - (31-5) initial display line the ?initial display line? instruction is used to specify the line address corresponding to the initial com line. the initial com line specified by the ?initial com line? instruction and indicates the common driver that starts scanning the display data. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 0 0 la 3 la 2 la 1 la 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 0 1 la 7 la 6 la 5 la 4 la 7 la 6 la 5 la 4 la 3 la 2 la 1 la 0 line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : 1 0 1 0 0 0 0 1 161 (31-6) n-line inversion the ?n-line inversion? instruction is used to control the alternate rates of the liquid crystal direction. it is programmed to select the n value between 2 and 161, and the fr signal toggles once every n lines by setting ?1? into the ?nlin? register of the ?display control (2)? instruction. when the n-line inversion is disabled by setting ?0? into the ?nlin? register, the fr signal toggles by the frame. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 1 0 n3 n2 n1 n0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 1 1 n7 n6 n5 n4 n7 n6 n5 n4 n3 n2 n1 n0 n value 0 0 0 0 0 0 0 0 inhibited 0 0 0 0 0 0 0 1 2 : : : : 1 0 1 0 0 0 0 0 161
NJU6825 - 62 - n-line inversion timing (1/163 duty cycle ratio) n-line inversion off n-line inversion on (31-7) display control (1) the ?display control (1)? instruction is used to control display conditions by setting the ?display on/off?, ?all pixels on/off?, ?display mode? and ?common direction? registers. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 0 0 shift mon allon on/off on/off register on/off=0 : display off (all com/seg output vss level.) on/off=1 : display on all on register the ?all pixels on/off? register is used to turn on all pixels without changing display data of the ddram. the setting for the ?all pixels on/off? register has a priority over the ?reverse display on/off? register. allon=0 : normal allon=1 : all pixels turn on. mon register mon=0 : gradation mode mon=1 : b&w mode shift register shift=0 : com 0 com 161 shift=1 : com 161 com 0 cl flm fr 2nd line 163rd line 1st line 3rd line 1st line 162nd line cl fr n-line control 2nd line 1st line 1st line 3rd line 2nd line nst line
NJU6825 - 63 - (31-8) display control (2) the ?display control (2)? instruction is used to control the display conditions by setting the ?segment direction?, ?swap mode on/off?, ?n-line inversion on/off? and ?reverse display on/off? registers. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 0 1 rev nlin swap ref ref register the ?ref? register is used to reverse the assignment between segment drivers and column address, and it is possible to reduce restrictions for placement of the lsi on the lcd modules. for more information, see (10) ?the relation among the ddram column address, display data and segment drivers?. swap register the ?swap? register is used to reverse the arrangement of display data in the ddram. swap=0 : swap mode off (normal) swap=1 : swap mode on swap=?0? swap=?1? write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ram data d7 d6 d5 d4 d3 d2 d1 d0 d0 d1 d2 d3 d4 d5 d6 d7 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 nlin register the ?nlin? is used to enable or disable the n-line inversion. nlin=0 : n-line inversion off (the fr signal toggles by the flame.) nlin=1 : n-line inversion on (the fr signal toggles once every n frames.) rev register the ?rev? register is used to enable or disable the reverse display mode that reverses the polarity of display data without changing display data of the ddram. rev=0 : reverse display mode off rev=1 : reverse display mode on rev display ddram data display data 0 0 0 normal 1 1 0 1 1 reverse 1 0
NJU6825 - 64 - (31-9) increment control the ?increment control? instruction is used for the increment mode. in using the auto-increment mode, ddram address automatically increments (+1) whenever the ddram is accessed by the ?display data write? or ?display data read? instruction. therefore, once ?display data write? or ?display data read? instruction is established, it is possible to continuously access to the ddram without the ?column address? and ?row address? instructions. the settings for the ?aim?, ?axi? and ?ayi? registers are listed in the following tables. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 1 0 win aim ayi axi aim, ayi and axi registers aim increment mode note 0 auto-increment for both of the display data read and write operations 1 1 auto-increment for the display write operation (read modify write) 2 note 1) it is effective for usual operations accessing successive addresses. note 2) it is effective for the read-modify-write operation ayi axi increment mode note 0 0 no auto-increment 1 0 1 auto-increment for the column address 2 1 0 auto-increment for the row address 3 1 1 auto-increment for the column address and row address 4 note 1) auto-increment is disabled regardless of the ?aim? register. note 2) auto-increment of the column address is enabled in accordance with the ?aim? register. note 3) auto-increment of the row address is enabled in accordance with the ?aim? register. note 4) auto-increment of the column address and the row address are enabled. the row address increments whenever the column address reaches to the max h . 00 h max h a 1 h 00 h max h 00 h a 1 h 00 h column address row address max h in the 8-bit data bus mode : ff h max h in the 16-bit data bus mode : 7f h max h in the 8-bit data bus mode : ff h max h in the 16-bit data bus mode : 7f h
NJU6825 - 65 - win register the ?win? register is used to access to the ddram for the window display area, where the start point is determined by the ?column address? and ?row address? instructions, and the end point by the ?window end column address ?and ?window end row address? instructions. the setting sequence for the window display area is listed as follows. for more detail, see (7) ?window addressing mode?. win=0 :window addressing mode off win=1 :window addressing mode on 1. set win=1, axi=1, and ayi=1 by ?increment control? instruction. 2. set the start point by the ?column address? and ?row address? instructions 3. set the end point by the ?window end column address? and ?window end row address? instructions 4. enable to access to the ddram in the window addressing mode start address column address row address end address start address end address
NJU6825 - 66 - (31-10) power control csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 1 1 ampon halt dcon acl acl register the ?acl? register is used to initialize the internal power supply circuits. acl=0 : initialization off (normal) acl=1 : initialization on when the data of the ?acl register? is read out by the ?instruction register read? instruction, the read-out data is ?1? during the initialization and ?0? after the initialization. this initialization is performed by using the signal produced by 2 clocks on the osc 1 . for this reason, the wait time for 2 clocks of the osc 1 is necessary until next instruction. dcon register the ?dcon? register is used to enable or disable the voltage booster. dcon=0 : voltage booster off dcon=1 : voltage booster on halt register the ?halt? register is used to enable or disable the power save mode. it is possible to reduce operating current down to stand-by level. the internal status in the power save mode is listed below. halt=0 : power save off (normal) halt=1 : power save on internal status in the power save mode ? the oscillation circuits and internal power supply circuits are halted. ? all segment and common drivers output v ss level. ? the clock input into the osc 1 is inhibited. ? the display data in the ddram is maintained. ? the operational modes before the power save mode are maintained. ? the v 1 to v 4 and v lcd are in the high impedance. as a power save on sequence, the ?display off? must be executed first, next the ?power save on? instruction, and then all common and segment drivers output the v ss level. and as power save off sequence, the ?power save off? instruction is executed first, next the ?display on? instruction. if the ?power save off? instruction is executed in the display on status, unexpected pixels may instantly turn on. ampon register the ?ampon? register is used to enable or disable the voltage followers, voltage regulator and evr. ampon=0 : the voltage followers, voltage regulator and the evr off ampon=1 : the voltage followers, voltage regulator and the evr on
NJU6825 - 67 - (31-11) duty cycle ratio the ?duty cycle ratio? instruction is used to select lcd duty cycle ratio for the partial display function. the partial display function specifies some parts of display area on a lcd panel in the condition of lower duty cycle ratio, lower lcd bias ratio, lower boost level and lower lcd driving voltage. therefore, it is possible to optimize the lsi?s conditions with extremely low power consumption. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 1 0 0 ds 3 ds 2 ds 1 ds 0 duty cycle ratio ds 3 ds 2 ds 1 ds 0 dse=0 dse=1 row way displays 0 0 0 0 1/163 1/162 162 commons 0 0 0 1 1/161 1/160 160 commons 0 0 1 0 1/145 1/144 144 commons 0 0 1 1 1/133 1/132 132 commons 0 1 0 0 1/129 1/128 128 commons 0 1 0 1 1/113 1/112 112 commons 0 1 1 0 1/97 1/96 96 commons 0 1 1 1 1/81 1/80 80 commons 1 0 0 0 1/73 1/72 72 commons 1 0 0 1 1/65 1/64 64 commons 1 0 1 0 1/57 1/56 56 commons 1 0 1 1 1/49 1/48 48 commons 1 1 0 0 1/41 1/40 40 commons 1 1 0 1 1/33 1/32 32 commons 1 1 1 0 1/25 1/24 24 commons 1 1 1 1 1/17 1/16 16 commons the duty cycle ratio is controlled by the ?ds 3 to ds 0 ? registers of the ?duty cycle ratio? instruction and the ?dse? register of the ?display clock / duty-1? instruction. dse=?0? : the number of commons + 1 (duty cycle ratio in the default setting) dse=?1? : the number of commons (duty-1) when the ?dse? is ?0?, all common drivers output non-selective levels in period of last common. and the segment drivers output the same data for the last line as the for previous line: for instance they output the same data for the 162 nd and 163 rd lines when the duty cycle ratio is set to 1/163. for the setting of the ?dse? register, see (31-17) ?display clock / duty-1?. (31-12) boost level the ?boost level? is used to select the multiple of the voltage booster for the partial display function. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 1 0 1 * vu 2 vu 1 vu 0 vu 2 vu 1 vu 0 boost level 0 0 0 1-time (no boost) 0 0 1 2-time 0 1 0 3-time 0 1 1 4-time 1 0 0 5-time 1 0 1 6-time 1 1 0 7-time 1 1 1 inhibited
NJU6825 - 68 - (31-13) lcd bias ratio the ?lcd bias ratio? is used to select the lcd bias ratio for the partial display function. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 1 1 0 * b 2 b 1 b 0 b 2 b 1 b 0 lcd bias ratio 0 0 0 1/9 0 0 1 1/8 0 1 0 1/7 0 1 1 1/6 1 0 0 1/5 1 0 1 1/10 1 1 0 1/11 1 1 1 1/12 (31-14) re flag the ?re flag? registers are used to determine the contents for the re registers (re 2 , re 1 and re 0 ) and it is possible to access to the instruction registers. the data in the ?tst 0 ? register must be ?0?, and it is used maker tests only. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0
NJU6825 - 69 - (31-15) gradation palette a, b and c csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 0 0 pa 03 / pa 83 pa 02 / pa 82 pa 01 / pa 81 pa 00 / pa 80 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 0 1 * * * pa 04 / pa 84 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 1 0 pa13/ pa 93 pa 12 / pa 92 pa 11 / pa 91 pa 10 / pa 90 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 1 1 * * * pa 14 / pa 94 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 0 0 pa 23 / pa 103 pa 22 / pa 102 pa 21 / pa 101 pa 20 / pa 100 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 0 1 * * * pa 24 / pa 104 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 1 0 pa 33 / pa 113 pa 32 / pa 112 pa 31 / pa 111 pa 30 / pa 110 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 1 1 * * * pa 34 / pa 114 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 0 0 pa 43 / pa 123 pa 42 / pa 122 pa 41 / pa 121 pa 40 / pa 120
NJU6825 - 70 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 0 1 * * * pa 44 / pa 124 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 1 0 pa 53 / pa 133 pa 52 / pa 132 pa 51 / pa 131 pa 50 / pa 130 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 1 1 * * * pa 54 / pa 134 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 1 0 0 pa 63 / pa 143 pa 62 / pa 142 pa 61 / pa 141 pa 60 / pa 140 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 1 0 1 * * * pa 64 / pa 144 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 0 0 pa 73 / pa 153 pa 72 / pa 152 pa 71 / pa 151 pa 70 / pa 150 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 0 1 * * * pa 74 / pa 154 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 1 0 pb 03 / pb 83 pb 02 / pb 82 pb 01 / pb 81 pb 00 / pb 80 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 1 1 * * * pb 04 / pb 84
NJU6825 - 71 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 0 0 pb 13 / pb 93 pb 12 / pb 92 pb 11 / pb 91 pb 10 / pb 90 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 0 1 * * * pb 14 / pb 94 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 1 0 pb 23 / pb 103 pb 22 / pb 102 pb 21 / pb 101 pb 20 / pb 100 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 1 1 * * * pb 24 / pb 104 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 0 0 pb 33 / pb 113 pb 32 / pb 112 pb 31 / pb 111 pb 30 / pb 110 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 0 1 * * * pb 34 / pb 114 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 1 0 pb 43 / pb 123 pb 42 / pb 122 pb 41 / pb 121 pb 40 / pb 120 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 1 1 * * * pb 44 / pb 124 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 1 0 0 pb53/ pb 133 pb 52 / pb 132 pb 51 / pb 131 pb 50 / pb 130
NJU6825 - 72 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 1 0 1 * * * pb 54 / pb 134 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 0 0 pb 63 / pb 143 pb 62 / pb 142 pb61/ pb 141 pb 60 / pb 140 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 0 1 * * * pb 64 / pb 144 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 1 0 pb 73 / pb 153 pb 72 / pb 152 pb 71 / pb 151 pb 70 / pb 150 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 1 1 * * * pb 74 / pb 154 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 0 0 pc 03 / pc 83 pc 02 / pc 82 pc 01 / pc 81 pc 00 / pc 80 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 0 1 * * * pc 04 / pc 84 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 1 0 pc 13 / pc 93 pc 12 / pc 92 pc 11 / pc 91 pc 10 / pc 90 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 1 1 * * * pc 14 / pc 94
NJU6825 - 73 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 0 0 pc 23 / pc 103 pc 22 / pc 102 pc 21 / pc 101 pc 20 / pc 100 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 0 1 * * * pc 24 / pc 104 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 1 0 pc 33 / pc 113 pc 32 / pc 112 pc 31 / pc 111 pc 30 / pc 110 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 1 1 * * * pc 34 / pc 114 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 1 0 0 pc 43 / pc 123 pc 42 / pc 122 pc 41 / pc 121 pc 40 / pc 120 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 1 0 1 * * * pc 44 / pc 124 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 0 0 pc 53 / pc 133 pc 52 / pc 132 pc 51 / pc 131 pc 50 / pc 130 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 0 1 * * * pc 54 / pc 134 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 1 0 pc 63 / pc 143 pc 62 / pc 142 pc 61 / pc 141 pc 60 / pc 140
NJU6825 - 74 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 1 1 * * * pc 64 / pc 144 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 0 0 pc 73 / pc 153 pc 72 / pc 152 pc 71 / pc 151 pc 70 / pc 150 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 0 1 * * * pc 74 / pc 154 gradation palette table (variable gradation mode, pwm=?0? and mon=?0?) (palette aj, palette bj, palette cj, (j=0 to 15)) palette value gradation level note palette value gradation level note 0 0 0 0 0 0/31 gradation palette 0 initial value 1 0 0 0 0 16/31 0 0 0 0 1 1/31 1 0 0 0 1 17/31 gradation palette 8 initial value 0 0 0 1 0 2/31 1 0 0 1 0 18/31 0 0 0 1 1 3/31 gradation palette 1 initial value 1 0 0 1 1 19/31 gradation palette 9 initial value 0 0 1 0 0 4/31 1 0 1 0 0 20/31 0 0 1 0 1 5/31 gradation palette2 initial value 1 0 1 0 1 21/31 gradation palette 10 initial value 0 0 1 1 0 6/31 1 0 1 1 0 22/31 0 0 1 1 1 7/31 gradation palette 3 initial value 1 0 1 1 1 23/31 gradation palette 11 initial value 0 1 0 0 0 8/31 1 1 0 0 0 24/31 0 1 0 0 1 9/31 gradation palette 4 initial value 1 1 0 0 1 25/31 gradation palette 12 initial value 0 1 0 1 0 10/31 1 1 0 1 0 26/31 0 1 0 1 1 11/31 gradation palette 5 initial value 1 1 0 1 1 27/31 gradation palette 13 initial value 0 1 1 0 0 12/31 1 1 1 0 0 28/31 0 1 1 0 1 13/31 gradation palette 6 initial value 1 1 1 0 1 29/31 gradation palette 14 initial value 0 1 1 1 0 14/31 1 1 1 1 0 30/31 0 1 1 1 1 15/31 gradation palette 7 initial value 1 1 1 1 1 31/31 gradation palette 15 initial value
NJU6825 - 75 - (31-16) initial com line the ?initial com line? instruction is used to specify the common driver that starts scanning the display data. the line address, corresponding to the initial com line, is specified by the ?initial display line? instruction. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 1 0 sc 3 sc 2 sc 1 sc 0 sc3 sc2 sc1 sc0 initial com line (shift=0) initial com line (shift=1) 0 0 0 0 com 0 com 161 0 0 0 1 com 1 com 160 0 0 1 0 com 9 com 152 0 0 1 1 com 14 com 146 0 1 0 0 com 17 com 144 0 1 0 1 com 25 com 136 0 1 1 0 com 33 com 128 0 1 1 1 com 41 com 120 1 0 0 0 com 49 com 112 1 0 0 1 com 57 com 104 1 0 1 0 com 65 com 96 1 0 1 1 com 73 com 88 1 1 0 0 com 122 com 39 1 1 0 1 com 130 com 31 1 1 1 0 com 138 com 23 1 1 1 1 com 146 com 15 shift=0: positive scan direction (com 0 com 161 ) shift=1: negative scan direction (com 161 com 0 ) (31-17) display clock / duty-1 the ?display clock / duty-1? instruction is used to enable or disable the display clocks (cl, flm, fr, and clk), and to control on/off of the ?duty-1?. for more detail about the ?duty-1?, see (31-11) ?duty cycle ratio?. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 1 1 * * dse son son=0: cl, flm, fr, and clk outputs level ?0?. son=1: cl, flm, fr, and clk outputs are active. dse=0: duty - 1 off dse=1: duty - 1 on
NJU6825 - 76 - (31-18) gradation mode control the ?gradation mode control? is used to select display mode as follows. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 0 0 pwm c256 fdc1 fdc2 pwm register pwm=0: variable gradation mode (variable 16-gradation levels out of 32-gradation level of the gradation palette) pwm=1: fixed gradation mode (fixed 8-gradation levels) c256 register c256=0 256-color mode off (4,096-color in the default setting) c256=1 256-color mode on fdc1 and fdc2 register fdc1 fdc2 boost clock 0 0 1 0 1 2 1 0 4 1 1 1/2
NJU6825 - 77 - (31-19) data bus length the ?data bus length? instruction is used to select the 8- or 16- bit data bus length and determine the internal or external oscillation. in the 16-bit data bus mode, instruction data must be 16-bit (d 15 to d 0 ) as well as display data. however, for the access to the instruction registers, the lower 8-bit data (d 7 to d 0 ) of the 16-bit data is valid. for the access to the ddram, all of the 16-bit data (d 15 to d 0 ) is valid. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 0 1 hsw abs cks wls hsw register hsw =0: high speed access mode off. hsw=1: high speed access mode on (only in the 8-bit data bus length). abs register abs=0: abs mode off (normal) abs=1: abs mode on wls register wls=0: 8-bit data bus length wls =1: 16-bit data bus length cks register cks =0: internal oscillation (the osc 1 terminal must be fixd ?1? or ?0?.) cks =1: external oscillation (by the external clock into the osc 1 or external resister between the osc 1 and osc 2 . osc 2 should be open when clock is inputted from osc 1 .)
NJU6825 - 78 - (31-20) evr control the ?evr control? instruction is used to fine-tune the lcd driving voltage (v lcd ) so that it is possible to optimize the contrast level for a lcd panel. this instruction must be programmed by upper 3-bit data first, next lower 4-bit data. and it becomes enabled when the lower 4-bit data is programmed, so that it can prevent unexpected high voltage for the v lcd from being generated. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 1 0 dv 3 dv 2 dv 1 dv 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 1 1 * dv 6 dv 5 dv 4 dv 6 dv 5 dv 4 dv 3 dv 2 dv 1 dv 0 v lcd 0 0 0 0 0 0 0 low 0 0 0 0 0 0 1 : : : : : 1 1 1 1 1 1 1 high the formula of the v lcd is shown below. v lcd [v] = 0.5 x v reg + m (v reg ? 0.5 x v reg ) / 127 v ba = v ee x 0.9 v ba : output voltage of the reference voltage generator v reg = v ref x n v ref : input voltage of the voltage regulator v reg : output voltage of the voltage regulator n : register value for the voltage booster m : register value for the evr
NJU6825 - 79 - (31-21) frequency control the ?frequency control? instruction is used to control the frame frequency for a lcd panel. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 1 0 1 * rf 2 rf 1 rf 0 rfx register (x=0, 1, 2) the ?rfx? register is used to determine the feed back resister value for the internal oscillator and it is possible to adjust the frame frequency for the lcd modules. rf 2 rf 1 rf 0 feedback resistor value 0 0 0 reference value 0 0 1 0.8 x reference value 0 1 0 0.9 x reference value 0 1 1 1.1 x reference value 1 0 0 1.2 x reference value 1 0 1 inhibited 1 1 0 inhibited 1 1 1 inhibited (31-22) discharge on/off discharge circuit is used to discharge the electric charge of the capacitors on the v 1 to v 4 and the v lcd terminals. the ?discharge on/off? instruction is usually required just after the internal power supply is turned off by setting ?0? into the ?dcon? and ?ampon? registers, or just after the external power supply is turned off. during the discharge operation, the internal or external power supply must not be turned on. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 1 1 0 * * * dis dis=0: discharge off dis=1: discharge on
NJU6825 - 80 - (31-23) instruction register address the ?instruction register address? is used to specify the instruction register address, so that it is possible to read out the contents of the instruction registers in combination with the ?instruction register read? instruction. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 1 0 0 ra 3 ra 2 ra 1 ra 0 (31-24) instruction register read the ?instruction register read? instruction is used to read out the contents of the instruction register in combination with the ?instruction register address? instruction. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0/1 0/1 0/1 * * * * internal register data read (31-25) window end column address the ?window end column address? is used to specify the column address for the window end point. the lower 4-bit data is required to be programmed first and then the upper 4-bit data can be programmed. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 0 0 ex 3 ex 2 ex 1 ex 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 0 1 ex 7 ex 6 ex 5 ex 4 (31-26) window end row address set the ?window end row address? is used to specify the row address for the window end point. the lower 4-bit data is required to be programmed first and then the upper 4-bit data can be programmed. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 1 0 ey 3 ey 2 ey 1 ey 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 1 1 ey 7 ey 6 ey 5 ey 4
NJU6825 - 81 - (31-27) initial reverse line the ?initial reverse line? instruction is used to specify the initial reverse line address for the reverse line display. lower 4-bit data must be programmed first, next upper 4-bit data. it is programmed in between 00 h and a1 h and the line address beyond a1 h is inhibited. the address relation: lsi < lei (i=7 to 0) must be maintained in the reverse line display. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 0 0 ls 3 ls 2 ls 1 ls 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 0 1 ls 7 ls 6 ls 5 ls 4 (31-28) last reverse line the ?last reverse line? instruction is used to specify the last reverse line address for the reverse line display. lower 4-bit must be programmed first, next upper 4-bit data. it is programmed in between 00 h and a1 h and the line address beyond a1 h is inhibited. the address relation: lsi < lei (i=7 to 0) must be maintained in the reverse line display. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 1 0 le 3 le 2 le 1 le 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 1 1 le 7 le 6 le 5 le 4 (31-29) reverse line display on/off the ?reverse line display on/off? is used to enable or disable the reverse line display for the blink operation and determine the reverse line display mode. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 1 0 0 0 * * bt lrev lrev register the ?lrev? register is used to enable or disable the reverse line display. lrev =0: reverse line display off (normal) lrev =1: reverse line display on
NJU6825 - 82 - bt register the ?bt? register is used to determine the reverse line display mode in the reverse line display on (lrev=1) status. bt =0: normal reverse line display bt =1: blink once every 32 frames display examples in the lrev=?1? and bt=?1? !"""! "!!!" "!!!" !"""! "!!!! !"""" !"""! "!!!" !!!!" """"! "!!!" !"""! !"""! "!!!" !!!!! """"" njrc lcd driver low power and low voltage njrc lcd driver low power and low voltage blink once every 32 frames initial reverse line address last reverse line address blink once every 32 frames
NJU6825 - 83 - (31-30) gradation palette setting control csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 1 0 0 1 * * * ps ps=0: lower 8 gradation setting ps=1: upper 8 gradation setting (31-31) pwm control the ?pwm control? is used to determine the pwm type for the segment waveforms, where the type can be specified for each of the segai, segbi and segci (i=0-127) drivers. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 1 0 1 0 pwms pwma pwmb pwmc pwms register pwms=0: type 1 pwms=1: type 2 pwma, b and c registers the ?pwma, pwmb and pwmc? registers are used to select the type 1-o or type 1-e. pwmz=0 (z=a, b and c): type 1-o pwmz=1 (z=a, b and c): type 1-e pwm type1 (pwms=?0?) pwm type2 (pwms=?1?) odd line even line ?h? ?l? v lcd v 2 v 2 type-o type-e cl seg v lcd ?h? ?l? cl seg v 2 v lcd
NJU6825 - 84 - (32) the relationship between common drivers and row addresses row address assignment of common drivers is programmed by the ? shift ? register of the ? display control (1) ? , ? duty cycle ratio ?, ? internal display line ? and ? initial com line ? instructions when initial display line is ?0? if the ? shift ? is ? 0 ?, the scan direction is normal. when the ? la 0 to la 7 ? registers of the ? initial display line ?instruction is ? 0 ?, the ? my ? corresponding to the initial com line is ? 0 ? and is increasing during display. when initial display line is not ?0? if the ? shift ? is ? 1 ?, the scan direction is inversed. when the ? la 0 to la 7 ? registers of the ? initial display line ?instruction is not ? 0 ?, the ? my ? corresponding to the initial com line is this setting value and is increasing during display. the following are examples of setting the start-line 0 or 5 at 1/163(dse=0), 1/80(dse=1), or 1/16(dse=1) duty.
NJU6825 - 85 - (32-1) initial display line ?0?, 1/163 duty cycle (common forward scan, dse=?0?) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0000?, la 7 ?.la 0 =?00000000?(initial display line 0) dse=?0? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 0 161 153 148 145 137 129 121 113 105 97 89 40 32 24 16 com 1 0 com 2 com 3 com 4 com 5 com 6 com 7 com 8 161 com 9 0 com 10 com 11 com 12 com 13 161 com 14 0 com 15 com 16 161 com 17 0 : com 23 com 24 161 com 25 0 com 26 com 27 com 28 com 29 com 30 com 31 com 32 161 com 33 0 com 34 com 35 com 36 com 37 com 38 com 39 com 40 161 com 41 0 com 42 com 43 com 44 com 45 com 46 com 47 com 48 161 com 49 0 com 50 com 51 com 52 com 53 com 54 com 55 com 56 161 com 57 0 com 58 com 59 com 60 com 61 com 62 com 63 com 64 161 com 65 0 com 66 com 67 com 68 com 69 com 70 com 71 com 72 161 com 73 0 com 74 com 75 com 76 com 77 com 78 : com 120 com 121 161 com 122 0 : com 128 com 129 161 com 130 0 : com 136 com 137 161 com 138 0 com 139 com 140 com 141 com 142 com 143 com 144 com 145 161 com 146 0 com 147 com 148 com 149 com 150 com 151 com 152 com 153 com 154 com 155 com 156 com 157 com 158 com 159 com 160 com 161 161 160 152 147 144 136 128 120 112 104 96 88 39 31 23 15 (163 rd com period) *1 161 161 161 161 161 161 161 161 161 161 161 161 161 161 161 161 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 163 rd com period is not selected.
NJU6825 - 86 - (32-2) initial display line ?0?, 1/163 duty cycle (common backward scan, dse=?0?) shift=?1?(common backward scan), ds 3 , 2 , 1 , 0 =?0000?, la 7 ?.la 0 =?00000000?(initial display line 0) dse=?0? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 161 160 152 146 144 136 128 120 112 104 96 88 39 31 23 15 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 0 com 16 161 com 17 com 18 com 19 com 20 com 21 com 22 com 23 0 com 24 161 com 25 : com 31 0 com 32 161 : com 39 0 com 40 161 : com 88 0 com 89 161 com 90 com 91 com 92 com 93 com 94 com 95 com 96 0 com 97 161 com 98 com 99 com 100 com 101 com 102 com 103 com 104 0 com 105 161 com 106 com 107 com 108 com 109 com 110 com 111 com 112 0 com 113 161 com 114 com 115 com 116 com 117 com 118 com 119 com 120 0 com 121 161 com 122 com 123 com 124 com 125 com 126 com 127 com 128 0 com 129 161 com 130 com 131 com 132 com 133 com 134 com 135 com 136 0 com 137 161 com 138 com 139 com 140 com 141 com 142 com 143 com 144 0 com 145 161 com 146 0 com 147 161 com 148 com 149 com 150 com 151 com 152 0 com 153 161 com 154 com 155 com 156 com 157 com 158 com 159 com 160 0 com 161 0 161 153 147 145 137 129 121 113 105 97 89 40 32 24 16 (163 rd com period) *1 161 161 161 161 161 161 161 161 161 161 161 161 161 161 161 161 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 163 rd com period is not selected.
NJU6825 - 87 - (32-3) initial display line ?0?, 1/80 duty cycle (common forward scan, dse=?1?) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0111?, la 7 ?.la 0 =?00000000?(initial display line 0) dse=?1? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 0 40 32 24 16 com 1 0 : com 9 0 com 10 com 11 com 12 com 13 com 14 0 com 15 com 16 com 17 0 com 18 : com 25 0 com 26 : com 33 0 : com 39 79 com 40 com 41 0 : com 47 79 com 48 com 49 0 com 50 com 51 com 52 com 53 com 54 com 55 79 com 56 com 57 0 com 58 com 59 com 60 com 61 com 62 com 63 79 com 64 com 65 0 com 66 com 67 com 68 com 69 com 70 com 71 com 72 com 73 0 com 74 com 75 com 76 com 77 com 78 com 79 79 com 80 79 com 81 : com 88 79 com 89 com 90 com 91 com 92 com 93 79 com 94 com 95 com 96 79 com 97 : com 104 79 com 105 : com 112 79 com 113 : com 120 79 com 121 com 122 0 com 123 com 124 com 125 com 126 com 127 com 128 79 com 129 com 130 0 com 131 com 132 com 133 com 134 com 135 com 136 79 com 137 com 138 0 com 139 com 140 com 141 com 142 com 143 com 144 79 com 145 com 146 0 com 147 com 148 com 149 com 150 com 151 com 152 79 : com 160 com 161 39 31 23 15 ds: duty cycle ratio, sc: initial com line, la: initial display line
NJU6825 - 88 - (32-4) initial display line ?0?, 1/80 duty cycle (common backward scan, dse=?1?) shift=?1?(common backward scan), ds 3 , 2 , 1 , 0 =?0111?, la 7 ?.la 0 =?00000000?(initial display line 0) dse=?1? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 39 31 23 15 : com 9 79 com 10 com 11 com 12 com 13 com 14 com 15 0 com 16 com 17 79 com 18 com 19 com 20 com 21 com 22 com 23 0 com 24 com 25 79 com 26 com 27 com 28 com 29 com 30 com 31 0 com 32 com 33 79 com 34 com 35 com 36 com 37 com 38 com 39 0 com 40 com 41 79 : com 49 79 : com 57 79 : com 65 79 com 66 com 67 79 com 68 com 69 com 70 com 71 com 72 com 73 79 : com 81 79 com 82 79 com 83 com 84 com 85 com 86 com 87 com 88 0 : com 96 0 com 97 com 98 79 com 99 com 100 com 101 com 102 com 103 com 104 0 com 105 com 106 79 com 107 com 108 com 109 com 110 com 111 com 112 0 com 113 com 114 79 com 115 com 116 com 117 com 118 com 119 com 120 0 com 121 com 122 79 com 123 com 124 com 125 com 126 com 127 com 128 0 : com 136 0 : com 144 0 com 145 com 146 0 : com 152 0 : com 160 0 com 161 0 40 32 24 16 ds: duty cycle ratio, sc: initial com line, la: initial display line
NJU6825 - 89 - (32-5) initial display line ?0?, 1/16 duty cycle (common forward scan, dse=?1?) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?1111?, la 7 ?.la 0 =?00000000?(initial display line 0) dse=?1? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 0 com 1 0 com 2 : com 9 0 com 10 com 11 com 12 com 13 com 14 0 com 15 15 com 16 15 com 17 0 com 18 com 19 com 20 com 21 com 22 com 23 com 24 15 com 25 0 com 26 com 27 com 28 com 29 15 com 30 com 31 com 32 15 com 33 0 com 34 com 35 com 36 com 37 com 38 com 39 com 40 15 com 41 0 com 42 com 43 com 44 com 45 com 46 com 47 com 48 15 com 49 0 com 50 com 51 com 52 com 53 com 54 com 55 com 56 15 com 57 0 com 58 com 59 com 60 com 61 com 62 com 63 com 64 15 com 65 0 com 66 com 67 com 68 com 69 com 70 com 71 com 72 15 com 73 0 com 74 com 75 com 76 com 77 com 78 com 79 com 80 15 com 81 : com 88 15 : com 121 com 122 0 : com 130 0 com 131 com 132 com 133 com 134 com 135 com 136 com 137 15 com 138 0 : com 145 15 com 146 0 : com 153 15 : com 160 com 161 15 ds: duty cycle ratio, sc: initial com line, la: initial display line
NJU6825 - 90 - (32-6) initial display line ?0?, 1/16 duty cycle (common backward scan, dse=?1?) shift=?1?(common backward scan), ds 3 , 2 , 1 , 0 =?1111?, la 7 ?.la 0 =?00000000?(initial display line 0) dse=?1? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 15 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 15 com 9 com 10 com 11 com 12 com 13 com 14 com 15 0 com 16 15 com 17 com 18 com 19 com 20 com 21 com 22 com 23 0 com 24 15 com 25 com 26 com 27 com 28 com 29 com 30 com 31 0 : com 39 0 : com 73 15 : com 81 15 com 82 com 83 com 84 com 85 com 86 com 87 com 88 0 com 89 15 com 90 com 91 com 92 com 93 com 94 com 95 com 96 0 com 97 15 : com 104 0 com 105 15 com 106 com 107 com 108 com 109 com 110 com 111 com 112 0 com 113 15 : com 120 0 com 121 15 com 122 com 123 com 124 com 125 com 126 com 127 com 128 0 com 129 15 com 130 com 131 15 com 132 com 133 com 134 com 135 com 136 0 com 137 15 : com 144 0 com 145 15 com 146 15 0 com 147 com 148 com 149 com 150 com 151 com 152 0 : com 160 0 com 161 0 ds: duty cycle ratio, sc: initial com line, la: initial display line
NJU6825 - 91 - (32-7) initial display line ?5?, 1/163 duty cycle (common forward scan, dse=?0?) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0000?, la 7 ?.la 0 =?00000101?(initial display line 5) dse=?0? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 5 4 158 153 150 142 134 126 118 110 102 94 45 37 29 21 com 1 5 com 2 com 3 161 com 4 0 com 5 com 6 com 7 com 8 161 com 9 5 0 com 10 com 11 161 com 12 0 com 13 com 14 5 com 15 com 16 com 17 5 com 18 com 19 161 com 20 0 com 21 com 22 com 23 com 24 com 25 5 com 26 com 27 161 com 28 0 : com 33 5 com 34 com 35 161 com 36 0 : com 41 5 com 42 com 43 161 com 44 0 : com 49 5 com 50 com 51 161 com 52 0 com 53 com 54 com 55 com 56 com 57 5 com 58 com 59 1161 com 60 0 : com 65 5 com 66 com 67 161 com 68 0 com 69 com 70 com 71 com 72 com 73 5 : com 116 161 com 117 0 : com 122 5 com 123 com 124 161 com 125 0 com 126 com 127 com 128 com 129 com 130 5 com 131 com 132 161 com 133 0 com 134 com 135 com 136 com 137 com 138 5 com 139 com 140 161 com 141 0 com 142 com 143 com 144 com 145 com 146 5 : com 156 161 com 157 0 161 com 158 0 com 159 com 160 com 161 4 3 157 152 149 141 133 125 117 109 101 93 44 36 28 20 (163 rd com period) *1 161 161 161 161 161 161 161 161 161 161 161 161 161 161 161 161 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 163 rd com period is not selected.
NJU6825 - 92 - (32-8) initial display line ?5?, 1/163 duty cycle (common backward scan, dse=?0?) shift=?1?(common backward scan), ds 3 , 2 , 1 , 0 =?0000?, la 7 ?.la 0 =?00000101?(initial display line 5) dse=?0? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 4 3 157 151 149 141 133 125 117 109 101 93 44 36 28 20 com 1 com 2 com 3 0 com 4 0 161 com 5 161 : com 15 5 com 16 com 17 com 18 com 19 com 20 0 com 21 161 com 22 com 23 5 com 24 com 25 com 26 com 27 com 28 0 com 29 161 com 30 com 31 5 com 32 com 33 com 34 com 35 com 36 0 com 37 161 com 38 com 39 5 com 40 com 41 com 42 com 43 com 44 0 com 45 161 : com 88 5 com 89 com 90 com 91 com 92 com 93 0 com 94 161 com 95 com 96 5 com 97 com 98 com 99 com 100 com 101 0 com 102 161 com 103 com 104 5 com 105 com 106 com 107 com 108 com 109 0 com 110 161 com 111 com 112 5 com 113 com 114 com 115 com 116 com 117 0 com 118 161 com 119 com 120 5 : com 125 0 com 126 161 com 127 com 128 5 com 129 com 130 com 131 com 132 com 133 0 com 134 161 com 135 com 136 5 : com 141 0 com 142 161 com 143 com 144 5 com 145 com 146 5 com 147 com 148 com 149 0 com 150 161 com 151 0 com 152 5 161 com 153 com 154 com 155 com 156 com 157 0 com 158 161 com 159 com 160 5 com 161 5 4 158 152 150 142 134 126 118 110 102 94 45 37 29 21 (163 rd com period) *1 161 161 161 161 161 161 161 161 161 161 161 161 161 161 161 161 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 163 rd com period is not selected.
NJU6825 - 93 - (32-9) initial display line ?5?, 1/80 duty cycle (common forward scan, dse=?1?) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0111?, la 7 ?.la 0 =?00000101?(initial display line 5) dse=?1? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 5 45 37 29 21 com 1 5 : com 9 5 com 10 com 11 com 12 com 13 com 14 5 com 15 com 16 com 17 5 com 18 : com 25 5 com 26 : com 33 5 : com 39 84 com 40 com 41 5 : com 47 84 com 48 com 49 5 com 50 com 51 com 52 com 53 com 54 com 55 84 com 56 com 57 5 com 58 com 59 com 60 com 61 com 62 com 63 84 com 64 com 65 5 com 66 com 67 com 68 com 69 com 70 com 71 com 72 com 73 5 com 74 com 75 com 76 com 77 com 78 com 79 84 com 80 84 com 81 : com 88 84 com 89 com 90 com 91 com 92 com 93 84 com 94 com 95 com 96 84 com 97 : com 104 84 com 105 : com 112 84 com 113 : com 120 84 com 121 com 122 5 com 123 com 124 com 125 com 126 com 127 com 128 84 com 129 com 130 5 com 131 com 132 com 133 com 134 com 135 com 136 84 com 137 com 138 5 com 139 com 140 com 141 com 142 com 143 com 144 84 com 145 com 146 5 com 147 com 148 com 149 com 150 com 151 com 152 84 : com 160 com 161 44 36 28 20 ds: duty cycle ratio, sc: initial com line, la: initial display line
NJU6825 - 94 - (32-10) initial display line ?5?, 1/80 duty cycle (common backward scan, dse=?1?) shift=?1?(common backward scan), ds 3 , 2 , 1 , 0 =?0111?, la 7 ?.la 0 =?00000101?(initial display line 5) dse=?1? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 44 36 28 20 : com 9 84 com 10 com 11 com 12 com 13 com 14 com 15 5 com 16 com 17 84 com 18 com 19 com 20 com 21 com 22 com 23 5 com 24 com 25 84 com 26 com 27 com 28 com 29 com 30 com 31 5 com 32 com 33 84 com 34 com 35 com 36 com 37 com 38 com 39 5 com 40 com 41 84 : com 49 84 : com 57 84 : com 65 84 com 66 com 67 84 com 68 com 69 com 70 com 71 com 72 com 73 84 : com 81 84 com 82 84 com 83 com 84 com 85 com 86 com 87 com 88 5 : com 96 5 com 97 com 98 84 com 99 com 100 com 101 com 102 com 103 com 104 5 com 105 com 106 84 com 107 com 108 com 109 com 110 com 111 com 112 5 com 113 com 114 84 com 115 com 116 com 117 com 118 com 119 com 120 5 com 121 com 122 84 com 123 com 124 com 125 com 126 com 127 com 128 5 : com 136 5 : com 144 5 com 145 com 146 5 : com 152 5 : com 160 5 com 161 5 45 37 29 21 ds: duty cycle ratio, sc: initial com line, la: initial display line
NJU6825 - 95 - (32-11) initial display line ?5?, 1/16 duty cycle (common forward scan, dse=?1?) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?1111?, la 7 ?.la 0 =?00000101?(initial display line 5) dse=?1? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 5 com 1 5 com 2 : com 9 5 com 10 com 11 com 12 com 13 com 14 5 com 15 20 com 16 20 com 17 5 com 18 com 19 com 20 com 21 com 22 com 23 com 24 20 com 25 5 com 26 com 27 com 28 com 29 20 com 30 com 31 com 32 20 com 33 5 com 34 com 35 com 36 com 37 com 38 com 39 com 40 20 com 41 5 com 42 com 43 com 44 com 45 com 46 com 47 com 48 20 com 49 5 com 50 com 51 com 52 com 53 com 54 com 55 com 56 20 com 57 5 com 58 com 59 com 60 com 61 com 62 com 63 com 64 20 com 65 5 com 66 com 67 com 68 com 69 com 70 com 71 com 72 20 com 73 5 com 74 com 75 com 76 com 77 com 78 com 79 com 80 20 com 81 : com 88 20 : com 121 com 122 5 : com 130 5 com 131 com 132 com 133 com 134 com 135 com 136 com 137 20 com 138 5 : com 145 20 com 146 5 : com 153 20 : com 160 com 161 20 ds: duty cycle ratio, sc: initial com line, la: initial display line
NJU6825 - 96 - (32-12) initial display line ?5?, 1/16 duty cycle (common backward scan, dse=?1?) shift=?1?(common backward scan), ds 3 , 2 , 1 , 0 =?1111?, la 7 ?.la 0 =?00000101?(initial display line 5) dse=?1? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 20 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 20 com 9 com 10 com 11 com 12 com 13 com 14 com 15 5 com 16 20 com 17 com 18 com 19 com 20 com 21 com 22 com 23 5 com 24 20 com 25 com 26 com 27 com 28 com 29 com 30 com 31 5 : com 39 5 : com 73 20 : com 81 20 com 82 com 83 com 84 com 85 com 86 com 87 com 88 5 com 89 20 com 90 com 91 com 92 com 93 com 94 com 95 com 96 5 com 97 20 : com 104 5 com 105 20 com 106 com 107 com 108 com 109 com 110 com 111 com 112 5 com 113 20 : com 120 5 com 121 20 com 122 com 123 com 124 com 125 com 126 com 127 com 128 5 com 129 20 com 130 com 131 20 com 132 com 133 com 134 com 135 com 136 5 com 137 20 : com 144 5 com 145 20 com 146 20 5 com 147 com 148 com 149 com 150 com 151 com 152 5 : com 160 5 com 161 5 ds: duty cycle ratio, sc: initial com line, la: initial display line
NJU6825 - 97 - absolute maximum ratings parameter symbol condition terminal rating unit supply voltage (1) v dd v dd -0.3 to +4.0 v supply voltage (2) v ee v ee -0.3 to +4.0 v supply voltage (3) v out v out -0.3 to +19.0 v supply voltage (4) v reg v reg -0.3 to +19.0 v supply voltage (5) v lcd v lcd -0.3 to +19.0 v supply voltage (6) v 1 , v 2 , v 3 , v 4 v 1 , v 2 , v 3 , v 4 -0.3 to v lcd + 0.3 v input voltage v i v ss =0v ta = +25 c *1 -0.3 to v dd + 0.3 v storage temperature t stg -45 to +125 c note 1) d 0 to d 15 , csb, rs, rdb, wrb, osc 1 , resb, test 1, test 2 , terminals. note 2) to stabilize the voltage booster operation, decoupling capacitors must be connected between the v dd and v ss pins and between the v ee and v ssh pins. recommended operating conditions parameter symbol terminal min typ max unit note v dd1 1.7 3.3 v *1 v dd2 v dd 2.4 3.3 v *2 supply voltage v ee v ee 2.4 3.3 v *3 v lcd v lcd 5 18.0 v *4 v out v out 18.0 v v reg v reg v out 0.9 v operating voltage v ref v ref 2.1 3.3 v *5 operating temperature t opr -30 85 c note1) applies to the condition when the reference voltage generator is not used. note2) applies to the condition when the reference voltage generator is used. note3) applies to the condition when the voltage booster is used. note4) the following relationship among the supply voltages must be maintained. v ss NJU6825 - 98 - dc characteristics 1 v ss = 0v, v dd = +1.7 to +3.3v, ta = -30 to +85 c parameter sym bol condition min typ max unit note high level input voltage v ih 0.8 v dd v dd v *1 low level input voltage v il 0 0.2v dd v *1 high level output voltage v oh1 i oh = -0.4ma v dd - 0.4 v *2 low level output voltage v ol1 i ol = 0.4ma 0.4 v *2 high level output voltage v oh2 i oh = -0.1ma v dd - 0.4 v *3 low level output voltage v ol2 i ol = 0.1ma 0.4 v *3 input leakage current i li v i = v ss or v dd -10 10 a *4 output leakage current i lo v i = v ss or v dd -10 10 a *5 v lcd = 10v 1 2 driver on-resistance r on1 | ? v on | = 0.5v v lcd = 6v 2 4 k ? *6 stand-by current i stb csb=v dd , ta=25 c v dd = 3v 15 a *7 f osc1 625 763 900 *8 f osc2 141 172 203 *9 internal oscillation frequency f osc3 v dd = 3v ta = 2 5 c 20.5 25 29.5 khz *10 f r1 rf=10k ? 750 f r2 rf=51k ? 185 external oscillation frequency f r3 rf=390k ? 27.2 khz *11 voltage converter output voltage v out n-time booster (n=2 to 7) rl = 500k ? (v out - v ss ) (n x v ee ) x 0.95 v *12 supply current (1) i dd1 v dd = 2.5v, 7-time booster whole on pattern 870 1300 supply current (2) i dd2 v dd = 2.5v, 7-time booster checker pattern 1060 1590 supply current (3) i dd3 v dd = 3v, 6-time booster whole on pattern 760 1140 supply current (4) i dd4 v dd = 3v, 6-time booster checker pattern 930 1400 supply current (5) i dd5 v dd = 3v, 5-time booster whole on pattern 520 780 supply current (6) i dd6 v dd = 3v, 5-time booster checker pattern 650 980 supply current (7) i dd7 v dd = 3v, 4-time booster whole on pattern 360 540 supply current (8) i dd8 v dd = 3v, 4-time booster checker pattern 450 680 a *13 v ba operating voltage v ba v ee = 2.4 to 3.3v (0.9 v ee ) x 0.98 0.9 v ee (0.9 v ee ) x 1.02 v *14 v reg operating voltage v reg v ee = 2.4 to 3.3v v ref = 0.9 x v ee n-time booster (n=2 to 7) (v ref x n) x 0.97 (v ref x n) (v ref x n) x 1.03 v *15 v 2 -100 0 +100 v 3 -100 0 +100 v d12 -30 0 +30 v d34 -30 0 +30 output voltage v d24 -30 0 +30 mv *16
NJU6825 - 99 - clock and frame frequency display duty cycle ratio (1/d) parameter symbol display mode 1/163 to 1/97 1/81 to 1/57 1/49 to 1/33 1/25 to 1/17 note 16 gradation mode f osc / (62xd) f osc / (62xdx2) f osc / (62xdx4) f osc / (62xdx8) simplified 8 gradation mode f osc / (14xd) f osc / (14xdx2) f osc / (14xdx4) f osc / (14xdx8) internal clock f osc b&w mode f osc / (2xd) f osc / (2xdx2) f osc / (2xdx4) f osc / (2xdx8) 16 gradation mode f ck / (62xd) f ck / (62xdx2) f ck / (62xdx4) f ck / (62xdx8) simplified 8 gradation mode f ck / (14xd) f ck / (14xdx2) f ck / (14xdx4) f ck / (14xdx8) external clock f ck b&w mode f ck / (2xd) f ck / (2xdx2) f ck / (2xdx4) f ck / (2xdx8) flm
NJU6825 - 100 - applied terminals and conditions note 1) d 0 -d 15 , csb, rs, rdb, wrb, p/s, sel68, resb note 2) d 0 -d 15 note 3) cl, flm, fr, clk note 4) csb, rs, sel68, rdb, wrb, p/s, resb, osc 1 note 5) d 0 -d 15 in the high impedance note 6) sega 0 -sega 127 , segb 0 -segb 127 , segc 0 -segc 127 , com 0 -com 161 - defines the resistance between the com/seg terminals and each of the power supply terminals (v lcd , v 1 , v 2 , v 3 and v 4 ) at the condition of 0.5v deference and 1/9 lcd bias ratio. note 7) v dd - the oscillator is halted, csb=?1? (disabled), no-load on the com/seg drivers note 8) osc - defines the internal oscillation frequency at (rf 2 , rf 1 , rf 0 )=(0,0,0) in the variable gradation mode. note 9) osc - defines the internal oscillation frequency at (rf 2 , rf 1 , rf 0 )=(0,0,0) in the fixed gradation mode. note 10) osc - defines the internal oscillation frequency at (rf 2 , rf 1 , rf 0 )=(0,0,0) in the black & white mode. note 11) v dd =3v, ta=25 c note 12) v out - applies to the condition when the internal voltage booster, the internal oscillator and internal power circuits are used. - v ee =2.4v to 3.3v, evr= (1,1,1,1,1,1,1), 1/5 to 1/12 lcd bias, 1/163 duty cycle, no-load on com/seg drivers. - rl=500k ? between the v out and the v ss , ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?1?, ampon=?1? note 13) v dd - applies to the condition when using the internal oscillator and internal power circuits, no access between the lsi and mpu. - evr= (1,1,1,1,1,1,1), all pixels turned-on or checkerboard display in gradation mode. no-load on the com/seg drivers. - v dd =v ee , v ref =0.9v ee , ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?1?, ampon=?1?, nlin=?0? 1/163 duty cycle, ta=25 c note 14) v ba - applies to the condition that v ba =v ref and voltage booster n= 1. when dcon=?0?, v out =13.5v input. note 15) v reg - v ee =2.4v to 3.3v, v ref =0.9v ee , v out =18v, 1/5 to 1/12 lcd bias ratio, 1/163 duty cycle, evr=(1,1,1,1,1,1,1) - checkerboard display, no-load on the com/seg drivers, the voltage booster n=2 to 7 ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?0?, ampon=?1?, nlin=?0? note 16) v lcd , v 1 , v 2 , v 3 , v 4 - v ee =3.0v, v ref =0.9v ee , v out =15v, 1/5 to 1/12 lcd bias, evr= (1,1,1,1,1,1,1), display off, no- load on the com/seg drivers, voltage booster n=5, ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?0?, ampon=?1? v d12 : (1)-(2) v d34 : (3)-(4) v d24 : (2)-(4) (1) (2) (3) (4) v lcd v 1 v 2 v 3 v 4 v ss
NJU6825 - 101 ac characteristics write operation (80-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 90 35 35 ns ns ns wrb data setup time data hold time t ds8 t dh8 30 5 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 160 70 70 ns ns ns wrb data setup time data hold time t ds8 t dh8 40 5 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 180 80 80 ns ns ns wrb data setup time data hold time t ds8 t dh8 70 10 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as8 csb wrb rs d 0 to d 15 t ah8 t wrlw8 t wrhw8 t ds8 t dh8 t cyc8
NJU6825 - 102 - read operation (80-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 180 80 80 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 60 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 180 80 80 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 60 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 250 120 120 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 110 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as8 csb rs d 0 to d 15 t rdd8 t rdh8 t cyc8 rdb t wrlr8 t wrhr8 t ah8
NJU6825 - 103 write operation (68-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 90 35 35 ns ns ns e data setup time data hold time t ds6 t dh6 40 5 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 160 70 70 ns ns ns e data setup time data hold time t ds6 t dh6 50 5 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 180 80 80 ns ns ns e data setup time data hold time t ds6 t dh6 70 10 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as6 csb rs t ah6 r/w ( wrb ) d 0 to d 15 t ehw6 t elw6 t ds6 t dh6 t cyc6 e ( rdb )
NJU6825 - 104 - read operation (68-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 180 80 80 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 70 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 180 80 80 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 70 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 250 120 120 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 110 ns ns d0 to d15 note) each timing is specified based on 20% and 80% of v dd . t as6 csb rs t ah6 r/w (wrb) d 0 to d 15 t ehr6 t elr6 t rdd6 t rdh6 t cyc6 e (rdb)
NJU6825 - 105 serial interface (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw 50 20 20 ns ns ns scl address setup time address hold time t ass t ahs 20 20 ns ns rs data setup time data hold time t dss t dhs 20 20 ns ns sda csb ? scl time csb hold time t css t csh 20 20 ns ns csb (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw 50 20 20 ns ns ns scl address setup time address hold time t ass t ahs 20 20 ns ns rs data setup time data hold time t dss t dhs 20 20 ns ns sda csb ? scl time csb hold time t css t csh 20 20 ns ns csb (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw 80 35 35 ns ns ns scl address setup time address hold time t ass t ahs 35 35 ns ns rs data setup time data hold time t dss t dhs 35 35 ns ns sda csb ? scl time csb hold time t css t csh 35 35 ns ns csb note) each timing is specified based on 20% and 80% of v dd . t css csb rs t csh sda t slw t shw t dss t dhs t cycs scl t a hs t ass
NJU6825 - 106 - display control timing output timing (v dd =2.4 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal flm delay time t dflm cl=15pf 0 500 ns flm fr delay time t fr 0 500 ns fr cl delay time t dcl 0 200 ns cl output timing (v dd =1.7 to 2.4v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal flm delay time t dflm cl=15pf 0 1000 ns flm fr delay time t fr 0 1000 ns fr cl delay time t dcl 0 200 ns cl note) each timing is specified based on 20% and 80% of v dd . cl t dflm t fr flm t dflm fr clk t dcl
NJU6825 - 107 input clock timing (v dd =1.7 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal osc 1 ?h? level pulse width (1) t ckhw1 0.555 0.800 s osc 1 ?l? level pulse width (1) t cklw1 0.555 0.800 s osc 1 ? 1 osc 1 ?h? level pulse width (2) t ckhw2 2.46 3.54 s osc 1 ?l? level pulse width (2) t cklw2 2.46 3.54 s osc 1 ? 2 osc 1 ?h? level pulse width (3) t ckhw3 16.9 24.4 s osc 1 ?l? level pulse width (3) t cklw3 16.9 24.4 s osc 1 ? 3 note) each timing is specified based on 20% and 80% of v dd . note 1) applied to the variable gradation mode / mon=?0?,pwm=?0? note 2) applied to the fixed gradation mode / mon=?0?,pwm=?1? note 3) applied to the b&w mode / mon=?1? osc 1 t cklw t ckhw
NJU6825 - 108 - reset input timing (v dd =2.4 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal reset time t r 1.0 s resb ?l? level pulse width t rw 10.0 s resb (v dd =1.7 to 2.4v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal reset time t r 1.5 s resb ?l? level pulse width t rw 10.0 s resb note) each timing is specified based on 20% and 80% of v dd . t rw resb internal circuit status end of reset during reset t r
NJU6825 - 109 typical characteristic parameter symbol min typ max unit basic delay time of gate ta=+25 c, v ss =0v, v dd =3.0v 10 ns input output terminal type (a) input circuit terminals: csb, rs, rdb, wrb, sel68, p/s, resb (b) output circuit terminals: flm, cl, fr, clk (c) input/output circuit terminals: d 0 to d 15 v dd i v ss (0v) input signal o v dd v ss (0v) output control signal output signal i/o v dd v ss (0v) input signal v dd v ss (0v) output control signal output signal v ss (0v) input control signal
NJU6825 - 110 - (d) display output circuit terminals: sega 0 to sega 127 segb 0 to segb 127 segc 0 to segc 127 com 0 to com 161 o v lcd v ss (0v) output control signal 1 v 1 /v 2 v ss (0v) output control signal 3 v lcd v ss (0v) v 3 /v 4 output control signal 2 output control signal 4 v lcd
NJU6825 - 111 application circuit examples (1) mpu connections 80-type mpu interface 68-type mpu interface serial interface a 0 v cc a 1 to a 7 iorqb d 0 to d 7 rdb wrb resb gnd 7 decoder rs csb d 0 to d 7 rdb wrb resb v dd v ss 8 reset 1.7v to 3.3v (80-type mpu) a 0 v cc a 1 to a 15 vm a d 0 to d 7 e r/w resb gnd 15 decoder rs csb d 0 to d 7 rdb ( e ) wrb ( r/w ) resb v dd v ss 8 reset 1.7v to 3.3v (68-type mpu) a 0 v cc a 1 to a 7 port 1 port 2 resb gnd 7 decoder rs csb sd a scl resb v dd v ss reset 1.7v to 3.3v ( mpu )
NJU6825 - 112 - [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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