View LXT325TOLXT336_2020713.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

migrating from lxt325 to lxt336 quad receiver application note january 2001 order number: 249173-002 as of january 15, 2001, this document replaces the level one document known as an116 .
application note information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ? reserved ? or ? undefined. ? intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the migrating from lxt325 to lxt336 quad receiver ? quad receiver may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2001 *third-party brands and names are the property of their respective owners.
application note 3 migrating from lxt325 to lxt336 quad receiver contents 1.0 introduction .................................................................................................................. 5 1.1 major differences .................................................................................................. 5 1.2 pin comparisons ................................................................................................... 5 1.3 applications ........................................................................................................... 5 1.3.1 migrating to lxt336 receiver mode of operation ................................... 7 1.3.2 lxt336 monitoring mode of operation ..................................................11 figures 1 lxt325 receiver mode applications .................................................................... 8 2 lxt336 receiver mode applications .................................................................... 9 3 lxt325 monitor application ................................................................................12 4 lxt336 monitor application ................................................................................13 tables 1 pinout cross-mapping from the lxt325 to the lxt336 .......................................6 2 lxt336 configuration in t1 receiver mode of operation ..................................10 3 lxt336 configuration in e1 receiver mode of operation ..................................11 4 lxt336 configuration in t1 monitoring mode of operation................................14 5 lxt336 configuration in e1 monitoring mode of operation................................15
revision history revision date description -002 03/06/01 modified figures 2 & 4. modified lxt336 qfp pin #18 description tables 1, 3 & 5.
migrating from lxt325 to lxt336 quad receiver application note 5 1.0 introduction this application note provides information to convert an existing lxt325 based design to the lxt336. the lxt325 was the first intel quad receiver for both t1 and e1 applications. the lxt336 is a new quad t1/e1 receiver with some additional features that are not available on the lxt325. due to pin-out and functional differences between the lxt325 and lxt336, migration will require redesigning of the pcb 1.1 major differences ? the lxt336 offers both bipolar and unipolar mode, the lxt325 works in bipolar mode only. the lxt336 offers selectable ami/hdb3 decoders, the lxt325 offers ami decoding only. both devices have a pin called mode. however, the operation of this pin is different for each device. refer to the data sheets for details. receiver slicer ratio is selectable on the lxt325 (with mode pin), on the lxt336 slicer ratio is fixed to 50% for e1 and to 70% for t1 applications. los criteria are different for the lxt336 and the lxt325. the lxt336 los complies with the most recent standards; the lxt325 does not. package size is different for each device. the lxt325 comes in 28 pin dip, 28pin plcc and 44 pin qfp packages. the lxt336 is only available in a 64-pin qfp package. 1.2 pin comparisons table 1 provides a complete pin comparison between the lxt325 and the lxt336 to facilitate migration. it lists the signals available on the lxt325 and the corresponding (equivalent) signals on the lxt336. due to its increased functionality, the lxt336 has more i/o pins than the lxt325. 1.3 applications table 2 through table 5 list the lxt336 pin configuration for each of its four major applications: t1 receiver mode t1 monitoring mode e1 receiver mode e1 monitoring mode the lxt336 meets or exceeds the performance of the lxt325 when used in the recommended configurations. figure 1 through figure 4 show how to couple the device to the line and other details the designer should be aware of when converting from the lxt325 to the lxt336.
migrating from lxt325 to lxt336 quad receiver 6 application note note: there are significant differences in line coupling transformer requirements and other external components for both receiver and monitoring applications. refer to the lxt325 and lxt336 data sheets for details. table 1. pinout cross-mapping from the lxt325 to the lxt336 lxt325 lxt336 pin number pin name pin number pin name description/comments dip plcc qfp qfp 12 8rpos163 rpos0/ rdata0 receiver 1, receive positive data output. 2 3 9 rneg1 62 rneg0/bpv0 receiver 1, receive negative data output. 3 4 10 rclk1 64 rclk0 receiver 1, receive clock output. 45 13rpos260 rpos1/ rdata1 receiver 2, receive positive data output. 5 6 14 rneg2 59 rneg1/bpv1 receiver 2, receive negative data output. 6 7 15 rclk2 61 rclk1 receiver 2, receive clock output. 7 8 16 los3 27 los2 receiver 3, loss of signal output. 89 19rpos353 rpos2/ rdata2 receiver 3, receive positive data output. 9 10 20 rneg3 52 rneg2/bpv2 receiver 3, receive negative data output. 10 11 21 rclk3 54 rclk2 receiver 3, receive clock out- put. 11 12 24 rpos4 50 rpos3/ rdata3 receiver 4, receive positive data output. 12 13 25 rneg4 49 rneg3/bpv3 receiver 4, receive negative data output. 13 14 26 rclk4 51 rclk3 receiver 4, recovered clock output. 14 15 27, 28 gnd 3, 6, 8, 10, 14, 17, 31, 35, 39, 43, 46 gnd ground. 15 16 30 mclk 1 mclk master clock input. 16 17 31 mode - - mode selection input. this pin on lxt325 selects 50% or 70% slicer ratio. on the lxt336 the slicer ratio is set to 50% for e1 and 70% for t1 operation. 17 18 32 rtip4 29 rtip3 receiver 4, receive tip input. 18 19 35 rring4 28 rring3 receiver 4, receive ring input. 19 20 36 los4 30 los3 receiver 4, loss of signal output 20 21 37 rtip3 26 rtip2 receiver 3, receive tip input. 21 22 38 rring3 25 rring2 receiver 3, receive ring input.
migrating from lxt325 to lxt336 quad receiver application note 7 1.3.1 migrating to lxt336 receiver mode of operation figure 1 and figure 2 show the lxt325 and the lxt336 configured for receiver mode of operation. note the differences between the lxt325 and the lxt336. the following signals are significant: mode, clki, ubs and clke. table 2 specifies the pin-out to configure the lxt336 for t1 receiver mode. table 4 specifies the pin-out to configure the lxt336 for e1 receiver mode. 22 23 40 los2 24 los1 receiver 2, loss of signal output. 23 24 41 rtip2 23 rtip1 receiver 2, receive tip input. 24 25 42 rring2 22 rring1 receiver 2, receive ring input. 25 26 2 los1 21 los0 receiver 1, loss of signal output. 26 27 3 rtip1 20 rtip0 receiver 1, receive tip input. 27 28 4 rring1 19 rring0 receiver 1, receive ring input. 28 1 5, 6 vcc 11, 15, 34, 38, 41 vcc positive (+5v) supply. -- - - 18mode mode select input. refer to the lxt336 data sheet for details. tie this pin to gnd for e1 ami operation, high for e1 - hdb3 operation or connect it to 2.5v for t1 operation. -- - - 4 7 42 45 ubs0 ubs1 ubs2 ubs3 receiver 1, 2, 3, and 4 - unipolar- bipolar select input. these inputs are available only on the lxt336. connect to gnd. -- - - 32 clke clock edge select input. tie pin to vcc through a 10 k ? resistor. -- - - 2 5 44 47 clki0 clki1 clki2 clki3 clock input receiver1, 2, 3, and 4. connected to gnd when migrating from lxt325 to lxt336. -- 1, 7, 11, 12,17, 18, 22, 23, 29, 33, 34, 39, 43, 44 nc-not connected 9, 12, 13, 16, 33, 36, 37, 40, 48, 55, 56, 57, 58 nc-not connected all nc pins must be left open (not connected). table 1. pinout cross-mapping from the lxt325 to the lxt336 (continued) lxt325 lxt336 pin number pin name pin number pin name description/comments dip plcc qfp qfp
migrating from lxt325 to lxt336 quad receiver 8 application note figure 1. lxt325 receiver mode applications rtip1 rring1 rtip2 rring2 rring3 rtip3 rtip4 rring4 rx rx rx rx rx rx rx rx rpos1 rclk1 rneg1 rpos2 rclk2 rneg2 rpos3 rclk3 rneg3 rpos4 rclk4 rneg4 mclk gnd mode vcc +5v lxt 325 q-rcvr 1 : 1 : 1 1 : 1 : 1 1 : 1 : 1 1 : 1 : 1 1.544/2.048 mhz 0.1 f 33 f notes: rx = 200 ? for dsx-1 (100 ? , tp, t1) applications. rx = 240 ? for e1 (120 ? , tp, e1) applications. rx = 150 ? for e1 (75 ? , coax, e1) applications.
migrating from lxt325 to lxt336 quad receiver application note 9 figure 2. lxt336 receiver mode applications rtip0 rring0 rtip1 rring1 rring2 rtip2 rtip3 rring3 gnd vcc lxt 336 +5v 33 f 0.1 f 0.22uf 1:1** rx rx 0.22uf rx rx 0.22uf rx rx 0.22uf rx rx rneg3 rclk3 rpos3 rneg2 rclk2 rpos2 rneg1 rclk1 rpos1 rneg0 rclk0 rpos0 1.544/2.048 mhz mclk clki0, 1, 2, 3 clke 10 k ? +5v mode 10 k ? 10 k ? +5v ubs0, 1, 2, 3 1k ? * 1k ? * 1k ? * 1k ? * 1k ? * 1k ? * 1k ? * 1k ? * 1:1** 1:1** 1:1** shaded area: see table 1 for mode pin description. notes: rx = 50 ? 1% for t1 (100 ? , tp cable) applications. rx = 60 ? 1% for e1 (120 ? , tp cable) applications. rx = 37.5 ? 1% for e1 (75 ? , coax cable) applications. * the 1 k ? resistors on rtip and rring are optional and provide surge protection for the lxt336. the recommended value is between 100 ? and 1000 ? . ** each 1:1 line transformer shown above may be substituted with the 1:1:1 transformer used on the lxt325 design. this is accomplished by using one-half of the 1:1:1 transformer ? s secondary winding.
migrating from lxt325 to lxt336 quad receiver 10 application note table 2. lxt336 configuration in t1 receiver mode of operation pin# symbol i/o description 1 mclk di master clock. supply 1.544 mhz clock. 2, 5, 44, 47 clki0, 1, 2, 3 di connect to ground. 3, 6, 8,10, 14,17, 31, 35, 39, 43, 46 gnd s connect to power supply ground. 4, 7, 42, 45 ubs0, 1, 2, 3 di connect to ground. 9, 12, 13, 16, 33, 36, 37, 40, 48, 55, 56, 57, 58 nc - not connected. 11, 15, 34, 38, 41, vcc s +5v power supply. 18 mode di mode select input. connect this input to 2.5v signal. see figure 2 . 19 20 22 23 25 26 28 29 rring0 rtip0 rring1 rtip1 rring2 rtip2 rring3 rtip3 ai ai ai ai ai ai ai ai receive ring/tip inputs for port 0, 1, 2, and 3 (port 1, 2, 3, and 4 per lxt325). 21 24 27 30 los0 los1 los2 los3 do do do do loss of signal port 0. loss of signal port 1. loss of signal port 2. loss of signal port 3. 32 clke di clock edge select input. pull this pin high using a 10k ? resistor. 63 62 rpos0 rneg0 do do receive positive data port 0 (port 1 per lxt325). receive negative data port 0 (port 1 per lxt325). 60 59 rpos1 rneg1 do do receive positive data port 1 (port 2 per lxt325). receive negative data port 1 (port 2 per lxt325). 53 52 rpos2 rneg2 do do receive positive data port 2 (port 3 per lxt325). receive negative data port 2 (port 3 per lxt325). 50 49 rpos3 rneg3 do do receive positive data port 3 (port 4 per lxt325). receive negative data port 3 (port 4 per lxt325). 64 61 54 51 rclk0 rclk1 rclk2 rclk3 do do do do receive clock output port 0 (port 1 on lxt325). receive clock output port 1 (port 2 on lxt325). receive clock output port 2 (port 3 on lxt325). receive clock output port 3 (port 4 on lxt325).
migrating from lxt325 to lxt336 quad receiver application note 11 1.3.2 lxt336 monitoring mode of operation figure 3 and figure 4 show the lxt325 and the lxt336 configured for monitor mode of operation. note the differences between the lxt325 and the lxt336. the following signals are significant: mode, clki, ubs and clke. table 4 specifies the pin-out to configure the lxt336 for t1 monitor mode. table 5 specifies the pin-out to configure the lxt336 for e1 monitor mode. table 3. lxt336 configuration in e1 receiver mode of operation pin# symbol i/o description 1 mclk di master clock. supply 2.048 mhz clock. 2, 5, 44, 47 clki0, 1, 2, 3 di connect to ground. 3, 6, 8, 10, 14, 17, 31, 35, 39, 43, 46 gnd s connect to power supply ground. 4, 7, 42, 45 ubs0, 1, 2, 3 di connect to ground. 9, 12, 13, 16, 33, 36, 37, 40, 48, 55, 56, 57, 58 nc - not connected. 11, 15, 34, 38, 41, vcc s +5v power supply. 18 mode di mode select input. connect to vcc or gnd. see figure 2 . 19 20 22 23 25 26 28 29 rring0 rtip0 rring1 rtip1 rring2 rtip2 rring3 rtip3 ai ai ai ai ai ai ai ai receive ring/tip inputs for port 0, 1, 2, and 3 (port 1, 2, 3, and 4 per lxt325). 21 24 27 30 los0 los1 los2 los3 do do do do loss of signal port 0. loss of signal port 1. loss of signal port 2. loss of signal port 3. 32 clke di clock edge select input. pull this pin high using a 10k ? resistor. 63 62 rpos0 rneg0 do do receive positive data port 0 (port 1 per lxt325). receive negative data port 0 (port 1 per lxt325). 60 59 rpos1 rneg1 do do receive positive data port 1 (port 2 per lxt325). receive negative data port 1 (port 2 per lxt325). 53 52 rpos2 rneg2 do do receive positive data port 2 (port 3 per lxt325). receive negative data port 2 (port 3 per lxt325). 50 49 rpos3 rneg3 do do receive positive data port 3 (port 4 per lxt325). receive negative data port 3 (port 4 per lxt325). 64 61 54 51 rclk0 rclk1 rclk2 rclk3 do do do do receive clock output port 0 (port 1 on lxt325). receive clock output port 1 (port 2 on lxt325). receive clock output port 2 (port 3 on lxt325). receive clock output port 3 (port 4 on lxt325).
migrating from lxt325 to lxt336 quad receiver 12 application note figure 3. lxt325 monitor application tp tp tp tp tp tp tp tp rtip1 rring1 rtip2 rring2 rring3 rtip3 rtip4 rring4 rx rx rx rx rx rx rx rx rpos1 rclk1 rneg1 rpos2 rclk2 rneg2 rpos3 rclk3 rneg3 rpos4 rclk4 rneg4 mclk gnd mode vcc +5v lxt 325 q-rcvr 1 : 2 : 2 1 : 2 : 2 1 : 2 : 2 1 : 2 : 2 432 w 432 w 432 w 432 w 22 f 0.1 f cross-connect reference point
migrating from lxt325 to lxt336 quad receiver application note 13 figure 4. lxt336 monitor application tp tp tp tp +5v 432 w 432 w 432 w 432 w 33 f rtip0 rring0 rtip1 rring1 rring2 rtip2 rtip3 rring3 vcc lxt 336 0.1 f rx rx 1:2** rx rx 0.22 f rx rx 0.22 f cross-connect reference point tp tp tp tp 0.22 f 0.22 f 1k ? * 1k ? * 1k ? * 1k ? * rx rx gnd rneg3 rclk3 rpos3 rneg2 rclk2 rpos2 rneg1 rclk1 rpos1 rneg0 rclk0 rpos0 1.544/2.048 mhz mclk clki0, 1, 2, 3 clke +5v mode 10 k ? 10 k ? +5v ubs0, 1, 2, 3 10 k ? 1k ? * 1k ? * 1k ? * 1k ? * 1:2** 1:2** 1:2** shaded area: see table 1 for mode pin description. notes: rx = 200 ? 1% for t1 (100 ? , tp cable) applications. rx = 240 ? 1% for e1 (120 ? , tp cable) applications. rx = 150 ? 1% for e1 (75 ? , coax cable) applications. * the 1 k ? resistors on rtip and rring are optional and provide surge protection for the lxt336. the recommended value is between 100 ? and 1000 ? . ** each 1:2 line transformer shown above may be substituted with the 1:2:2 transformer used on the lxt325 design. this i accomplished by using one-half of the 1:2:2 transformer ? s secondary winding.
migrating from lxt325 to lxt336 quad receiver 14 application note table 4. lxt336 configuration in t1 monitoring mode of operation pin# symbol i/o description 1 mclk di master clock. supply 1.544 mhz clock. 2, 5, 44, 47 clki0, 1, 2, 3 di connect to ground. 3, 6, 8, 10, 14, 17,31, 35, 39, 43, 46 gnd s connect to power supply ground. 4, 7, 42, 45 ubs0, 1, 2, 3 di connect to ground. 9, 12, 13, 16, 33, 36, 37, 40, 48, 55, 56, 57, 58 nc - not connected. 11,15,34, 38,41, vcc s +5v power supply. 18 mode di mode select input. connect this input to 2.5v. see figure 4 . 19 20 22 23 25 26 28 29 rring0 rtip0 rring1 rtip1 rring2 rtip2 rring3 rtip3 ai ai ai ai ai ai ai ai receive ring/tip inputs for port 0, 1, 2, and 3 (port 1, 2, 3, and 4 per lxt325). 21 24 27 30 los0 los1 los2 los3 do do do do loss of signal port 0. loss of signal port 1. loss of signal port 2. loss of signal port 3. 32 clke di clock edge select input. pull this pin high using a 10k ? resistor. 63 62 rpos0 rneg0 do do receive positive data port 0 (port 1 per lxt325). receive negative data port 0 (port 1 per lxt325). 60 59 rpos1 rneg1 do do receive positive data port 1 (port 2 per lxt325). receive negative data port 1 (port 2 per lxt325). 53 52 rpos2 rneg2 do do receive positive data port 2 (port 3 per lxt325). receive negative data port 2 (port 3 per lxt325). 50 49 rpos3 rneg3 do do receive positive data port 3 (port 4 per lxt325). receive negative data port 3 (port 4 per lxt325). 64 61 54 51 rclk0 rclk1 rclk2 rclk3 do do do do receive clock output port 0 (port 1 on lxt325). receive clock output port 1 (port 2 on lxt325). receive clock output port 2 (port 3 on lxt325). receive clock output port 3 (port 4 on lxt325).
migrating from lxt325 to lxt336 quad receiver application note 15 table 5. lxt336 configuration in e1 monitoring mode of operation pin# symbol i/o description 1 mclk di master clock. supply 2.048 mhz clock. 2, 5, 44, 47 clki0, 1, 2, 3 di connect to ground. 3, 6, 8, 10, 14, 17, 31, 35, 39, 43, 46 gnd s connect to power supply ground. 4, 7, 42, 45 ubs0, 1, 2, 3 di connect to ground. 9, 12, 13, 16, 33, 36, 37, 40, 48, 55, 56, 57, 58 nc - not connected. 11, 15, 34, 38, 41, vcc s +5v power supply. 18 mode di mode select input. connect this input to vcc or gnd. see figure 4 . 19 20 22 23 25 26 28 29 rring0 rtip0 rring1 rtip1 rring2 rtip2 rring3 rtip3 ai ai ai ai ai ai ai ai receive ring/tip inputs for port 0, 1, 2, and 3 (port 1, 2,3, and 4 per lxt325). 21 24 27 30 los0 los1 los2 los3 do do do do loss of signal port 0. loss of signal port 1. loss of signal port 2. loss of signal port 3. 32 clke di clock edge select input. pull this pin high using a 10k ? resistor. 63 62 rpos0 rneg0 do do receive positive data port 0 (port 1 per lxt325). receive negative data port 0 (port 1 per lxt325). 60 59 rpos1 rneg1 do do receive positive data port 1 (port 2 per lxt325). receive negative data port 1 (port 2 per lxt325). 53 52 rpos2 rneg2 do do receive positive data port 2 (port 3 per lxt325). receive negative data port 2 (port 3 per lxt325). 50 49 rpos3 rneg3 do do receive positive data port 3 (port 4 per lxt325). receive negative data port 3 (port 4 per lxt325). 64 61 54 51 rclk0 rclk1 rclk2 rclk3 do do do do receive clock output port 0 (port 1 on lxt325). receive clock output port 1 (port 2 on lxt325). receive clock output port 2 (port 3 on lxt325). receive clock output port 3 (port 4 on lxt325).
migrating from lxt325 to lxt336 quad receiver 16 application note

▲Up To Search▲

Price & Availability of LXT325TOLXT336

	To Download LXT325TOLXT336 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .