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ordering number : en 4365b o3095ha (ot)/91994th (ot) no. 4365-1/29 overview the LC5852N is a high-performance four-bit single-chip built-in lcd driver microprocessor that provides a variety of attractive features including low-voltage operation and low power dissipation. the LC5852N was developed as an upwardly compatible version of the lc5851n and provides a rom capacity increased from 1024 to 2048 15- bit words and a ram capacity increased from 64 4 bits to 128 4 bits. applications system control and lcd display in cameras, radios and similar products system control and lcd display in miniature electronic test equipment and consumer health maintenance products the LC5852N is optimal for end products with lcd displays and, in particular, for battery operated products. features the LC5852N is an upwardly compatible version of the lc5851n and, as such, has the following features. extremely broad allowable operating ranges package dimensions unit: mm 3057-qip64a sanyo: qip64a [LC5852N] LC5852N sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan four-bit single-chip microcontroller with on-chip lcd drivers for small-scale control in medium-speed applications cmos lsi power supply option cycle time power supply voltage range note ext-v 10 ? v ss 2 = ?.0 to ?.5 v when using an 800 khz ceramic resonator ext-v 20 ? v ss 2 = ?.0 to ?.5 v when using a 400 khz ceramic resonator ext-v 61 ? v ss 2 = ?.3 to ?.5 v when using a 65 khz crystal oscillator ext-v 122 ?, 244 ? v ss 2 = ?.0 to ?.5 v when using a 32 khz crystal oscillator li 122 ?, 244 ? v ss 2 = ?.6 to ?.6 v * when using a 32 khz crystal oscillator ag 122 ?, 244 ? v ss 1 = ?.3 to ?.65 v when using a 32 khz crystal oscillator note: * when the backup flag is set, the bak pin is shorted to v ss 2. (see the user? manual for details.) low current drain halt mode (typical) ceramic oscillator (cf): 400 khz (5.0 v) 150 ? crystal oscillator (xtal): 32 khz (1.5 v, ag specifications) 2.0 ? (for lcd biases other than 1/3) 3.5 ? (for an lcd bias of 1/3) crystal oscillator (xtal): 32 khz (3.0 v, li specifications) 1.0 ? (for lcd biases other than 1/3) 5.0 ? (for an lcd bias of 1/3)
timer functions one six-bit programmable timer time base timer (for clock applications) standby functions clock standby function (halt mode) the LC5852N provides a halt function that reduces power dissipation. in halt mode, only the oscillator, divider and lcd driver circuits operate. all other internal operations are stopped. this mode allows the LC5852N to easily implement a low-power clock function. full standby function (hold mode) halt mode is cleared by two external factors and two internal factors. improved i/o functions external interrupt pins input pins that can clear halt mode (up to 9 pins) input ports with software controllable input resistors: up to 8 pins input ports with built-in floating prevention circuits: up to 8 pins lcd drivers; common: 4 pins, segment pins: 25 pins general-purpose i/o ports: 8 pins general-purpose inputs: 9 pins general-purpose outputs (1): 6 pins (alm pin, light pin) general-purpose outputs (2): 25 pins (when all 25 lcd segment ports are used as general- purpose outputs) pseudo-serial output port: 1 set (three pins: output, busy, clock) function over vie w program rom: 2048 15 bits on-chip ram: 128 4 bits all instructions execute in a single cycle halt mode clear and interrupt functions (external factors) changes in the s and m port input signals changes in the int pin input signal (internal factors) overflow from the clock divider circuit timer underflow subroutines can be nested up to four levels (including interrupts) powerful hardware to improve processing capabilities on-chip segment pla circuit and segment decoder: the lcd driver outputs can handle lcd panel segment display without incurring software overhead. all lcd driver output pins can be switched to be used as output ports. one six-bit programmable timer part of the ram area can be used as a working area. built-in clock oscillator and 15-stage divider (also used for lcd alternation signal generation) highly flexible lcd panel drive output pins (25) supported maximum number required drive types of segments common pins 1/3 bias?/4 duty ...... 100 segments .......... 4 pins 1/3 bias?/3 duty ...... 75 segments ............ 3 pins 1/2 bias?/4 duty ...... 100 segments .......... 4 pins 1/2 bias?/3 duty ...... 75 segments ............ 3 pins 1/2 bias?/2 duty ...... 50 segments ............ 2 pins static .......................... 25 segments ............ 1 pin the lcd output pins can be converted to use as general-purpose output pins. cmos type: 25 pins (maximum) p-channel open drain type: 3 pins (maximum) an oscillator appropriate for the system specifications can be selected. 32 or 65 khz crystal oscillator, or 400 or 800 khz ceramic oscillator deliver y f ormats qip-64a or chip product no. 4365- 2 /29 LC5852N
pin and pad assignment chip size: 4.19 3.66 mm pad size: 120 120 m chip thickness: 480 m (chip specification products) note: 1. the pin numbers are those for the qip-64a mass production package. 2. the pad coordinates given above take the center of the chip as the origin and specify the center of the pad. 3. testa pin (pin 2) in the qip-64a product must be connected to the minus side of the power supply. 4. test pin (pin 3) in the qip-64a product must be left open. 5. pad 27 in the chip product must either be connected to the minus side of the power supply or left open. 6. pads 28, 45 and 46 in the chip product must be left open. 7. if the chip product is used, the substrate must be connected to v dd . 8. do not use dip-soldering techniques to mount the qip-64a package product. no. 4365- 3 /29 LC5852N pin pad symbol coordinates no. no. x m y m 40 1 v dd 1899 138 41 2 bak 1899 358 42 3 v ss 1 1899 538 43 4 v ss 2 1899 718 44 5 alm 1899 898 45 6 light 1899 1078 46 7 s4 1899 1258 47 8 s3 1899 1438 48 9 i/o a1 1899 1630 49 10 i/o a2 1595 1630 50 11 i/o a3 1415 1630 51 12 i/o a4 1235 1630 52 13 i/o b1 1055 1630 53 14 i/o b2 875 1630 54 15 i/o b3 695 1630 55 16 i/o b4 515 1630 56 17 res 253 1630 57 18 int 73 1630 58 19 p1 ?07 1630 59 20 p2 ?87 1630 60 21 p3 ?07 1630 61 22 p4 ?87 1630 62 23 m1 ?067 1630 pin pad symbol coordinates no. no. x m y m 63 24 m2 ?247 1630 64 25 m3 ?427 1630 1 26 m4 ?899 1630 2 27 testa ?899 1450 3 28 test ?899 1270 4 29 cup1 ?899 1090 5 30 cup2 ?899 910 6 31 s2 ?899 730 7 32 s1 ?899 550 33 (v dd ) ?899 370 8 34 osc-in ?899 190 35 10p ?899 10 9 36 osc-out ?899 ?69 10 37 com1 ?899 ?49 38 com4 ?899 ?29 11 39 seg01 ?899 ?09 12 40 seg02 ?899 ?89 13 41 seg03 ?899 ?069 14 42 seg04 ?899 ?249 15 43 seg05 ?899 ?429 16 44 seg06 ?899 ?609 45 test ?553 ?630 46 test ?373 ?630 pin pad symbol coordinates no. no. x m y m 17 47 seg07 ?033 ?630 18 48 seg08 ?53 ?630 19 49 seg09 ?73 ?630 20 50 seg10 ?93 ?630 21 51 seg11 ?13 ?630 22 52 seg12 ?33 ?630 23 53 seg13 46 ?630 24 54 com4 226 ?630 25 55 seg14 459 ?630 26 56 seg15 639 ?630 27 57 seg16 819 ?630 28 58 seg17 999 ?630 29 59 seg18 1179 ?630 30 60 seg19 1359 ?630 31 61 seg20 1539 ?630 32 62 seg21 1719 ?630 33 63 seg22 1899 ?630 34 64 seg23 1899 ?54 35 65 seg24 1899 ?74 36 66 seg25 1899 ?94 37 67 com3 1899 ?14 38 68 com2 1899 ?34 39 69 v ss 3 1899 ?4
system block diagram LC5852N system block diagram no. 4365- 4 /29 LC5852N ac: accumulator alu: arithmetic and logic unit int ctl: interrupt control circuit pc: program counter tm: preset timer (6 bits) ir: instruction register halt: intermittent control circuit scg: system clock generator sts1: status register 1 sts2: status register 2 sts3: status register 3 cf: carry flag bcf: backup flag scf1: m port flag scf2: sts3 flag scf3: s port flag scf4: int signal change flag scf5: timer overflow flag ?5: contents of the fifteenth stage of the divider circuit scf7: divider circuit overflow flag
pin functions no. 4365- 5 /29 LC5852N pin i/o qip-64 function option at reset pin no. v dd bak v ss 1 v ss 2 v ss 3 cup1 cup2 osc-in osc-out 10p s1 s2 s3 s4 m1 m2 m3 m4 i/o a1 i/o a2 i/o a3 i/o a4 i/o b1 i/o b2 i/o b3 i/o b4 p1 p2 p3 p4 alm light input output input input i/o i/o output output output 40 41 42 43 39 4 5 8 9 7 6 47 46 62 63 64 1 48 49 50 51 52 53 54 55 58 59 60 61 44 45 power supply plus side lsi internal logic block minus power supply in li specification products, connect a capacitor between bak and v dd to prevent incorrect operation. power supply minus side external component connections differ depending on mask options and other factors. in products for ag use, connect v ss 1 to the power supply minus side. in other products, connect v ss 2 to the power supply minus side. the pins other than the minus pin are used for the lcd driver power supply. connections for the lcd drive voltage boost (cut) capacitor. used for real-time clock and the system clock. connected to osc-in or osc-out and used for the oscillator phase compensation capacitor. can only be used in the chip product. dedicated input port includes either a ?0 (32 ms), ? (8 ms), or ? (2 ms) chattering exclusion circuit (pla mask option). * these values are for the case where a 32.768 khz crystal is used. pull-down resistors are built in. dedicated input port input connections for acquiring data to internal ram pull-down resistors are built in. i/o port input connections for acquiring data to internal ram output connections for data output from internal ram the input or output state can be switched by two instructions. i/o port input connections for acquiring data to internal ram output connections for data output from internal ram the input or output state can be switched by two instructions. output port output connections for data output from internal ram dedicated output this pin can output a signal modulated either at 4 khz or 2 khz, or at 4 khz or 1 khz under program control. alternatively, an unmodulated signal can be output. * these values are for the case where a 32.768 khz crystal is used. dedicated output this pin can drive a power transistor. ag specifications li specifications ext-v specifications crystal oscillator use (xt option) ceramic resonator use (cf option) the cf option can only be specified for ext-v specification products. inclusion (or exclusion) of a low level hold transistor inclusion (or exclusion) of a low level hold transistor modulated signals (4 khz, 2 khz, or unmodulated) modulated signals (4 khz, 1 khz, or unmodulated) backup flag set backup flag cleared (depending on the power supply option) the pull-down resistor transistor is on. the pull-down resistor transistor is on. input mode input mode either a high- or low-level output. (undefined) low-level output low-level output continued on next page.
continued from preceding page. no. 4365- 6 /29 LC5852N pin i/o qip-64 function option at reset pin no. res int testa test seg1 seg2 to seg25 com1 com2 com3 com4 input input input output output 56 57 2 3 11 12 to36 10 38 37 24 lsi internal reset input reset can be performed on either a high or low input level. built-in pull-up or pull-down resistor note: the applied signal must be held for at least 500 s. external interrupt request input interrupt detection can be performed for either falling or rising edges. built-in pull-up or pull-down resistor test input qip-64 products: connect to the power supply ?side chip products: leave open or connect to the power supply ?side test input this pin must be left open. (it cannot be used in user systems.) lcd drive/general-purpose output pins lcd drive i static ii 1/2 bias ?1/2 duty iii 1/2 bias ?1/3 duty iv 1/2 bias ?1/4 duty v 1/3 bias ?1/3 duty vi 1/3 bias ?1/4 duty items i to v are specified as master options. general-purpose output mode (cmos output) lcd/general-purpose output control under program control is disabled by adoption of the segment pla. arbitrary combinations of lcd drive and general purpose outputs are possible. lcd common polarity drive outputs these pins are used as follows depending on the lcd drive method used. (note that these are typical specifications for 32.768 khz when ? is used for the alternation frequency.) note: an indicates that the corrsponding common pin is not used with that lcd drive method. lcd drive type. do not use hold mode in cf specification products that use the lcd driver. (the alternation frequency signal is stopped in hold mode.) pull-up or pull-down resistor selection pull-up or pull- down resistor selection signal change type (rising or falling) selection switching between lcd drive outputs and general- purpose outputs lcd drive method switching static 1/2 bias ? 1/2 duty 1/2 bias ? 1/3 duty 1/2 bias ? 1/4 duty 1/3 bias ? 1/3 duty 1/3 bias ? 1/4 duty general-purpose outputs cmos lcd drive all segments lit all segments off * set by a mask option general-purpose outputs high level low level * set by a mask option static 1/2 duty 1/3 duty 1/4 duty com1 m m m m com2 m m m com3 m m com4 m alternation 32 hz 32 hz 42.7 hz 32 hz frequency
application circuit examples 1. representative application for ag specification products (1/3 bias - 1/4 duty) 3. representative application for ext-v specification products (1/2 bias - 1/4 duty) 2. representative application for lithium specification products (1/2 bias - 1/4 duty) no. 4365- 7 /29 LC5852N
oscillator circuit options no. 4365- 8 /29 LC5852N option circuit form note cf 400 khz 800 khz xtal (32.768 khz) xtal (65 khz) the cycle time is 4 n times the f1 period (n : 2). the divider outputs (? to ?5) are used, for example, as the lcd drive waveform generation clock and as the s and k port chattering prevention clock. the cycle time is four times the f1 period. the divider outputs (? to ?5) are used, for example, as the lcd drive waveform generation clock, as the s and k port chattering prevention clock and as a clock time base. the 10p connection can only be used in chip products. the cycle time is four times the f1 period. (used when the cycle time is 61 s.) the divider outputs (? to ?5) are used, for example, as the lcd drive waveform generation clock and as the s and k port chattering prevention clock. the 10p connection can only be used in chip products.
crystal oscillator options int pin options res pin options no. 4365- 9 /29 LC5852N option circuit form note 32 khz 65 khz the resistor rd for use with a 32 khz frequency is built in. option circuit form note pull-up resistor, pull-down resistor, or resistor open selection rising edge, falling edge detection selection built-in resistor selection use of the pull-up resistor use of the pull-down resistor open signal change edge detection selection rising edge detection falling edge detection option circuit form note pull-up resistor, pull-down resistor, or resistor open and level selection built-in resistor and polarity selection pull-up resistor and reset on low pull-down resistor and reset on high both resistors open and reset on low both resistors open and reset on high
input port options the use of the low level hold transistor can be specified individually for each pin in the s1 to s4 and m1 to m4 ports. 1. the s port includes independent (in bit units) chattering exclusion circuits with periods of ?0, ?, or ?. 2. the m port includes chattering exclusion circuits that operate for halt mode clear request signals. these circuits exclude chattering for periods of ?0, ?, or ? when three of the ports are at the low level and a signal change occurs on the remaining port. lcd output options no. 4365- 10 /29 LC5852N option circuit form note use of the hold transistor (low level hold transistor) hold transistor unused (open) this option can be specified individually for each pin in s1 to s4 and m1 to m4. when use of the hold transistor is selected: this transistor is used to reduce the current drain in the pull-up or pull-down resistor when, for example, a push-button switch is used for s1 or a slide switch is used for s2. when the input open specifications are used, this transistor turns the resistor on prior to reading the input value and then turns the resistor off after the input value is read. if the input is floating when read, the low-level input hold transistor will operate and hold that level. when the hold transistor is unused: the pull-down transistor can be used as a pull-down resistor. the pull-down transistor can be turned on and off under program control. the pull-down resistor can be used in the on state without change. select the unused option if the input is connected to an external control signal line that will never go to the floating state. on reset the resistor will be in the on state during the reset period. the resistor will keep up the on state when reset is cleared. option circuit form lcd drive cmos output port p-channel open-drain output port used as lcd segment drive pins the lcd drive type is specified independently. the lcd drive type is common to all lcd drive pins and can be selected from the following set: static, 1/2 bias?/2 duty, 1/2 bias?/3 duty, 1/2 bias?/4 duty, 1/3 bias?/3 duty, or 1/3 bias?/4 duty. general-purpose cmos output ports general-purpose p-channel open-drain output ports this option can be specified for three specific ports using pla option specification. available ports...pads 64 to 66 (pins 34 to 36)
mask option overview 1. power supply specification selection ag (silver battery/1.5 v) specifications li (lithium battery/3.0 v) specifications ext-v specifications (the operating voltage range depends on the oscillator used) 2. oscillator selection crystal oscillator (32.768 khz) crystal oscillator (65.536 khz) ceramic oscillator 3. lcd drive static 1/2 bias?/2 duty 1/2 bias?/3 duty 1/2 bias?/4 duty 1/3 bias?/3 duty 1/3 bias?/4 duty note: the lcd ports can all be used as general-purpose outputs. in this case, specify the ?nuse?option. 6. lcd alternation frequency slow (osc/2048) typ (osc/1024) fast (osc/512) stop 5. s port low-level hold transistor level hold transistor present no level hold transistor 6. m port low-level hold transistor level hold transistor present no level hold transistor 7. s and m port chattering exclusion frequency slow (osc/1024) typ (osc/256) fast (osc/64) 8. int pin resistor selection and signal edge type selection pull-up resistor (negative) pull-down resistor (positive) open (negative) open (positive) 9. external reset res pin simultaneous input to s1 through s4 10. res pin pull-up resistor (low-level reset) pull-down resistor (high-level reset) open (low-level reset) open (high-level reset) 11. power-on reset function (internal reset) use unuse 12. timer input clock slow (osc/512) fast (osc/8) 13. alarm modulation base frequency slow (osc/8, osc/32) typ (osc/8, osc/16) 14. cycle time slow (osc/8) fast (osc/4) note: specify ?low?for this option if a ceramic oscillator is used. no. 4365- 11 /29 LC5852N
internal register functions no. 4365- 12 /29 LC5852N symbol r/w function initialization value at reset pc rom ram r/o r/w program counter the pc is an 11-bit counter that specifies the program memory (rom) address of the next instruction to be executed. normally, the pc is incremented on each instruction execution, from 000h to 7ffh. however, when a branch or subroutine call is executed, or when an interrupt or initializing reset occurs, the pc is set to a value corresponding to the particular operation. the table below shows how the pc is set for these operations. page: rom paging performed in 1024 word pages pages are specified with the sf and rf instructions. p0 ?p9: instruction code bits (immediate data) program memory the on-chip rom consists of 2048 15-bit words and holds the user programs to be executed. data memory the on-chip ram consists of 128 4-bit digits of static ram in two pages with 64 4-bit digits per page. this ram has the following features: ram addresses can be specified directly (immediate addressing) as values in the range 00h to 3fh. arithmetic operations can be performed between the ac and any ram location. due to the provision of the segment pla circuit, ram dedicated to display is not required. ram locations 38h to 3fh have a function that allows direct arithmetic operations with other data without using the ac. the ac is used for ram input, i.e., writing. undefined pc pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 operation initializing reset 0 0 0 0 0 0 0 0 0 0 0 int pin external interrupt 0 0 0 0 0 0 1 0 0 0 0 s or m port external 0 0 0 0 0 0 1 0 1 0 0 interrupt timer internal interrupt 0 0 0 0 0 0 1 1 0 0 0 divider internal interrupt 0 0 0 0 0 0 1 1 1 0 0 unconditional jump (jmp) page p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 conditional jump (bab0, bab1, bab2, bab3, page p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 baz, banz, bch, bcnh) subroutine call instruction page p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 (call) return instruction call address + 1 (rts, rtsr) continued on next page.
continued from preceding page. no. 4365- 13 /29 LC5852N symbol r/w function initialization value at reset ram ac stack apg opg tim r/w r/w r/w r/w r/w w accumulator stack pointer the stack consists of four 13-bit words supporting subroutine calls and interrupts up to four levels deep. p0 to p10: program counter (pc) apg: ram page flag opg: rom page flag ram page flag the ram page flag is a single bit that allows the ram to be expanded to two pages, where a single ram page is 64 4 bits. rom page flag the rom page flag is a single bit that allows the rom to be expanded to two pages, where a single rom page is 1024 15 bits. timer counter the timer is a 6-bit down counter. the timer is set from immediate data in an instruction. undefined undefined 01h 00h 00h undefined continued on next page.
continued from preceding page. no. 4365- 14 /29 LC5852N symbol r/w function initialization value at reset sts1 sts2 sts3 r/w r/o r/o status register 1 (sts1) status register 1 is a four-bit register whose bits are used as shown below. * the test flags cannot be used by application programs. status register 2 (sts2) status register 2 is a four-bit register whose bits are used as shown below. scf1: set when there was a change in an m port signal (when enabled by an ssw instruction). scf2: set when any bit in sts3 is set. scf3: set when there was a change in an s port signal (when enabled with an ssw instruction). status register 3 (sts3) status register 3 is a four-bit register whose bits are used as shown below. scf4: set when there was a change in the int pin signal (when enabled by an sic instruction). scf5: timer underflow (when enabled by an sic instruction) scf4: divider overflow (when enabled by an sic instruction) 00h undefined undefined
specifications these electrical specifications are provisional and subject to change. ext -v specifications absolute maximum ratings at v dd = 0 v allowable operating ranges at ta = ?0 to +70 c, v dd = 0 v no. 4365- 15 /29 LC5852N parameter symbol conditions/pins min typ max unit v ss 1 ?.0 +0.3 v maximum supply voltage v ss 2 ?.0 +0.3 v v ss 3 lcd drive method (1/3 bias) ?.5 +0.3 v v ss 3 lcd drive method (any method other than 1/3 bias) ?.0 +0.3 v s1 to 4, m1 to 4, i/oa1 to 4, i/ob1 to 4, int, res, maximum input voltage v in 1 oscin, 10p, testa (with i/oa1 to 4 and i/ob1 to 4 v ss 2 ?0.3 +0.3 v in input mode, 10p is for chip products) alm, light, p1 to 4, cup2, oscout, test, v out 1 i/oa1 to 4, i/ob1 to 4 v ss 2 ?0.3 +0.3 v maximum output voltage (with i/oa and i/ob in output mode) v out 2 segout, com1 to 4, cup1 v ss 3 v operating temperature topr ?0 +70 c storage temperature tstg ?0 +125 c parameter symbol conditions/pins min typ max unit v ss 1 ?.5 ?.3 v supply voltage v ss 2 32 khz crystal oscillator specifications ?.5 ?.0 v v ss 3 ?.25 ?.0 v v ss 1 ?.5 ?.3 v supply voltage v ss 2 65 khz crystal oscillator specifications ?.5 ?.3 v v ss 3 ?.25 ?.3 v v ss 1 ?.5 ?.7 v supply voltage v ss 2 external input used ?.5 ?.5 v v ss 3 ?.25 ?.5 v v ss 1 ?.5 ?.0 v supply voltage v ss 2 400 khz cf specifications ?.5 ?.0 v v ss 3 ?.25 ?.0 v input high level voltage v ih 1 all input ports except oscin 0.3 v ss 2 0 v input low level voltage v il 1 v ss 2 0.7 v ss 2 v input high level voltage v ih 2 oscin pin, when external input used, figure 8 0.2 v ss 2 0 v input low level voltage v il 2 v ss 2 0.8 v ss 2 v oscin/oscout, operating frequency fopg1 v ss 2 = ?.0 to ?.5 v 32 khz crystal oscillator, 32 33 khz figure 2 oscin/oscout, operating frequency fopg2 v ss 2 = ?.3 to ?.5 v 65 khz crystal oscillator, 60 66 khz figure 2 operating frequency fopg3 v ss 2 = ?.5 to ?.5 v oscin external input, 32 220 khz figure 8 operating frequency fopg4 v ss 2 = ?.0 to ?.5 v oscin/oscout, 360 400 440 khz cf 400 khz, figure 1 operating frequency fopg5 v ss 2 = ?.0 to ?.5 v oscin/oscout, 720 800 880 khz cf 800 khz, figure 1 continued on next page.
electrical characteristics at ta = ?0 to +70 c, v dd = 0 v note: * s1, s2, s3, s4, m1, m2, m3, m4 parameter symbol conditions/pins min typ max unit r in 1a v ss 2 = ?.9 v, low-level hold transistor * , 10 200 k v in = 0.8 v ss 2 figure 3 input resistance r in 1b v ss 2 = ?.9 v, low-level pull-in transistor * , 200 700 2000 k v in = v dd figure 3 r in 2a v ss 2 = ?.9 v, int pin pull-up resistor 200 700 2000 k v in = v ss 2 r in 2b v ss 2 = ?.9 v, int pin pull-down resistor 200 700 2000 k input resistance v in = v dd r in 3 v ss 2 = ?.9 v, res 5 50 k v in = v dd or v ss 2 output high level voltage v oh (1) v ss 2 = ?.4 v, alm ? ?.3 v i oh = 1 ma output low level voltage v ol (1) v ss 2 = ?.4 v, alm v ss 2 + 0.3 v ss 2 + 1 v i ol = 1 ma output high level voltage v oh (2) v ss 2 = ?.4 v, light, port p ? ?.3 v i oh = 0.3 ma output low level voltage v ol (2) v ss 2 = ?.4 v, light, port p v ss 2 + 0.3 v ss 2 + 1 v i ol = 0.5 ma output high level voltage v oh (3) v ss 2 = ?.4 v, i/o ports ? ?.3 v i oh = 0.1 ma output high level voltage v oh (4) v ss 2 = ?.4 v, i/o ports ?.6 ?.2 v i oh = ?0 a output low level voltage v ol (4) v ss 2 = ?.4 v, i/o ports v ss 2 + 0.3 v ss 2 + 1 v i ol = 0.1 ma segment driver output impedances ?when used as cmos output ports output high level voltage v oh (5) v ss 2 = ?.4 v, ? ?.3 v i oh = ?0 a output low level voltage v ol (5) v ss 2 = ?.4 v, v ss 2 + 0.3 v ss 2 + 1 v i ol = 100 a output high level voltage v oh (6) v ss 2 = ?.4 v, ? ?.3 v i oh = ? a output low level voltage v ol (6) v ss 2 = ?.4 v, v ss 2 + 0.3 v ss 2 + 1 v i ol = 20 a ?when used as p-channel open-drain output ports output high level voltage v oh (5) v ss 2 = ?.4 v, ? ?.3 v i oh = ?0 a output off leakage current i off v ss 2 = ?.9 v, 1 a v ol = v ss 2 ?static drive output high level voltage v oh (5) v ss 2 = ?.4 v, ?.2 v i oh = ?.4 a, all segments output low level voltage v ol (5) v ss 2 = ?.4 v, v ss 2 + 0.2 v i ol = 0.4 a output high level voltage v oh (7) v ss 2 = ?.4 v, ?.2 v i oh = ? a com1 output low level voltage v ol (7) v ss 2 = ?.4 v, v ss 2 + 0.2 v i ol = 4 a ?duplex drive (1/2 bias?/2 duty) output high level voltage v oh (5) v ss 2 = ?.4 v, ?.2 v i oh = ?.4 a all segments output low level voltage v ol (5) v ss 2 = ?.4 v, v ss 2 + 0.2 v i ol = 0.4 a output high level voltage v oh (7) v ss 2 = ?.4 v, ?.2 v i oh = ? a v ss 2 = ?.4 v, v ss 2/2 v ss 2/2 output middle level voltage v om i oh = ? a, com1, 2 ?0.2 + 0.2 v i ol = 4 a output low level voltage v ol (7) v ss 2 = ?.4 v, v ss 2 + 0.2 v i ol = 4 a no. 4365- 16 /29 LC5852N segment pads 62 to 64, qip64 pins 34 to 36 segment pads 62 to 64, qip64 pins 34 to 36 segment pads 38 to 41 and 44 to 61, qip64 pins 11 to 23 and 25 to 33 continued on next page.
continued from preceding page. electrical characteristics at ta = ?0 to +70 c, v dd = 0 v note: * s1, s2, s3, s4, m1, m2, m3, m4 no. 4365- 17 /29 LC5852N parameter symbol conditions min typ max unit ?1/2 bias?/3 duty and 1/2 bias?/4 duty methods output high level voltage v oh (5) v ss 2 = ?.4 v, ?.2 v i oh = ?.4 a all segments output low level voltage v ol (5) v ss 2 = ?.4 v, v ss 2 + 0.2 v i ol = 0.4 a output high level voltage v oh (7) v ss 2 = ?.4 v, ?.2 v i oh = ? a v ss 2 = ?.4 v, v ss 2/2 v ss 2/2 output middle level voltage v om i oh = ? a, ?0.2 + 0.2 v i ol = 4 a output low level voltage v ol (7) v ss 2 = ?.4 v, v ss 2 + 0.2 v i ol = 4 a ?1/3 bias?/3 duty and 1/3 bias?/4 duty methods output high level voltage v oh (5) v ss 2 = ?.4 v, ?.2 v i oh = ?.4 a v om 1-1 v ss 2 = ?.4 v, v ss 2/2 v ss 2/2 v output middle level voltage i oh = ?.4 a all segments ?0.2 + 0.2 v om 1-2 i ol = 0.4 a v ss 2 ?0.2 v ss 2 + 0.2 v output low level voltage v ol (5) v ss 2 = ?.4 v, v ss 3 + 0.2 v i ol = 0.4 a output high level voltage v oh (7) v ss 2 = ?.4 v, ?.2 v i oh = ? a v om 2-1 v ss 2 = ?.4 v, v ss 2/2 v ss 2/2 v output middle level voltage i oh = ? a ?.2 +0.2 v om 2-2 i ol = 4 a v ss 2 ?0.2 v ss 2 + 0.2 v output low level voltage v ol (7) v ss 2 = ?.4 v, v ss 3 + 0.2 v i ol = 4 a com1 to 3 (for 1/3 duty methods) com1 to 4 (for 1/4 duty methods) com1 to 3 (for 1/3 duty methods) com1 to 4 (for 1/4 duty methods) parameter symbol conditions min typ max unit r in 1a v ss 2 = ?.0 v, low-level hold transistor * , 10 45 150 k v in = 0.8 ?v ss 2 figure 3 r in 1b v ss 2 = ?.0 v, low-level pull-in transistor * , 100 350 1000 k v in = v dd figure 3 input resistance r in 2a v ss 2 = ?.0 v, int pin pull-up resistor 100 350 1000 k v in = v ss 2 r in 2b v ss 2 = ?.0 v, int pin pull-down resistor 100 350 1000 k v in = v dd r in 3 v ss 2 = ?.0 v, res 10 20 50 k v in = v dd or v ss 2 output high level voltage v oh (1) v ss 2 = ?.5 to ?.25 v, alm ? ?.3 v i oh = ?.5 ma output low level voltage v ol (1) v ss 2 = ?.5 to ?.25 v, alm v ss 2 + 0.3 v ss 2 + 1 v i ol = 1.5 ma output high level voltage v oh (2) v ss 2 = ?.5 to ?.25 v, light, port p ? ?.3 v i oh = ?.5 ma output low level voltage v ol (2) v ss 2 = ?.5 to ?.25 v, light, port p v ss 2 + 0.3 v ss 2 + 1 v i ol = 0.7 ma output high level voltage v oh (3) v ss 2 = ?.5 to ?.25 v, i/o ports ? ?.3 v i oh = ?.13 ma output high level voltage v oh (4) v ss 2 = ?.5 to ?.25 v, i/o ports ?.6 ?.2 v i oh = ?0 a output low level voltage v ol (4) v ss 2 = ?.5 to ?.25 v, i/o ports v ss 2 + 0.3 v ss 2 + 1 v i ol = 0.13 ma continued on next page.
continued from preceding page. no. 4365- 18 /29 LC5852N parameter symbol conditions min typ max unit segment driver output impedances ?when used as cmos output ports output high level voltage v oh (5) v ss 2 = ?.5 to ?.25 v, ? ?.3 v i oh = ?5 a output low level voltage v ol (5) v ss 2 = ?.5 to ?.25 v, v ss 2 + 0.3 v ss 2 + 1 v i ol = 150 a output high level voltage v oh (6) v ss 2 = ?.5 to ?.25 v, ? ?.3 v i oh = ?0 a output low level voltage v ol (6) v ss 2 = ?.5 to ?.25 v, v ss 2 + 0.3 v ss 2 + 1 v i ol = 60 a ?when used as p-channel open-drain output ports output high level voltage v oh (5) v ss 2 = ?.5 to ?.25 v, ? ?.3 v i oh = ?5 a output off leakage current i off v ss 2 = ?.5 to ?.25 v, 1 a v ol = v ss 2 ?static drive output high level voltage v oh (5) v ss 2 = ?.5 to ?.25 v, ?.2 v i oh = ?.4 a all segments output low level voltage v ol (5) v ss 2 = ?.5 to ?.25 v, v ss 2 + 0.2 v i ol = 0.4 a output high level voltage v oh (7) v ss 2 = ?.5 to ?.25 v, ?.2 v i oh = ? a com1 output low level voltage v ol (7) v ss 2 = ?3.5 to ?.25 v, v ss 2 + 0.2 v i ol = 4 a ?duplex drive (1/2 bias?/2 duty) output high level voltage v oh (5) v ss 2 = ?.5 to ?.25 v, ?.2 v i oh = ?.4 a all segments output low level voltage v ol (5) v ss 2 = ?.5 to ?.25 v, v ss 2 + 0.2 v i ol = 0.4 a output high level voltage v oh (7) v ss 2 = ?.5 to ?.25 v, ?.2 v i oh = ? a output middle level voltage v om 2-1 v ss 2 = ?.5 to ?.25 v, com1, 2 v ss 2/2 v ss 2/2 v i oh = ? a, i ol = 4 a ?0.2 +0.2 output low level voltage v ol (7) v ss 2 = ?.5 to ?.25 v, v ss 2 +0.2 v i ol = 4 a ?1/2 bias?/3 duty and 1/2 bias?/4 duty methods output high level voltage v oh (5) v ss 2 = ?.5 to ?.25 v, ?.2 v i oh = ?.4 a all segments output low level voltage v ol (5) v ss 2 = ?.5 to ?.25 v, v ss 2 + 0.2 v i ol = 0.4 a output high level voltage v oh (7) v ss 2 = ?.5 to ?.25 v, ?.2 v i oh = ? a output middle level voltage v om 2-1 v ss 2 = ?.5 to ?.25 v, v ss 2/2 v ss 2/2 v i oh = ? a, i ol = 4 a ?0.2 +0.2 output low level voltage v ol (7) v ss 2 = ?.5 to ?.25 v, v ss 2 + 0.2 v i ol = 4 a ?1/3 bias?/3 duty and 1/3 bias?/4 duty methods output high level voltage v oh (5) v ss 2 = ?.5 to ?.25 v, ?.2 v i oh = ?.4 a v om 1-1 v ss 2 = ?.5 to ?.25 v, v ss 2/2 v ss 2/2 v output middle level voltage i oh = ?.4 a, all segments ?0.2 +0.2 v om 1-2 i ol = 0.4 a v ss 2 ?0.2 v ss 2 + 0.2 v output low level voltage v ol (5) v ss 2 = ?.5 to ?.25 v, v ss 3 + 0.2 v i ol = 0.4 a output high level voltage v oh (7) v ss 2 = ?.5 to ?.25 v, ?.2 v i oh = ?.4 a v om 2-1 v ss 2 = ?.5 to ?.25 v, v ss 2/2 v ss 2/2 v output low level voltage i oh = ? a, i ol = 4 a ?0.2 +0.2 v om 2-2 v ss 2 ?0.2 v ss 2 + 0.2 v output low level voltage v ol (7) v ss 2 = ?.5 to ?.25 v, v ss 3 + 0.2 v i ol = 4 a segment pads 62 to 64, qip64 pins 34 to 36 segment pads 62 to 64, qip64 pins 34 to 36 com1 to 3 (for 1/3 duty methods) com1 to 4 (for 1/4 duty methods) com1 to 3 (for 1/3 duty methods) com1 to 4 (for 1/4 duty methods) segment pads 38 to 41 and 44 to 61, qip64 pins 11 to 23 and 25 to 33 continued on next page.
continued from preceding page. no. 4365- 19 /29 LC5852N parameter symbol conditions min typ max unit power supply leakage current i lek v ss 2 = v ss 3 = ?.5 v ta = 25 c 10 a input leakage current i in v ss 2 = ?.0 to +4.5 v v in = v ss 2 to v dd ? +1 a v ss 1 v ss 2 = ?.9 v c1 = c2 = c3 = 0.1 f, ?.45 ?.35 v output voltage v ss 3 v ss 2 = ?.9 v fopg = 32.768 khz, ta = 25 c, figure 7 ?.35 ?.1 v v ss 1 v ss 2 = ?.5 v c1 = c2 = c3 = 0.1 f, ?.25 ?.2 v output voltage v ss 3 v ss 2 = ?.5 v fopg = 32.768 khz, ta = 25 c, figure 7 ?.70 ?.6 v | i dd 1 | v ss 2 = ?.9 v, 3.0 6.0 a ta = 25 c, halt mode v ss 2 = ?.5 v, c1 = c2 = 0.1 f, cl = 25 k , power supply current ta = 25 c, halt mode, fopg = 32.768 khz, | i dd 2 | stack: figure 9, cg = 20 pf 7 13 a 1/3 bias?/3 duty: figure 7, other methods: figure 4 v ss 2 = ?.5 v, ta = 25 c, halt mode c1 = c2 = 0.1 f, cl = 25 k , power supply current | i dd 3 | stack: figure 9, fopg = 65.536 khz, 10 20 a 1/3 bias?/3 duty: cg = 10 pf figure 7, other methods: figure 4 c1 = c2 = 0.1 f, power supply current | i dd 4 | v ss 2 = ?.5 v, fopg = 400 khz, 90 150 a ta = 25 c, halt mode cg = cd = 100 pf or 330 pf, rf = 1 m , figure 6 c1 = c2 = 0.1 f, power supply current | i dd 5 | v ss 2 = ?.5 v, fopg = 800 khz, 130 200 a ta = 25 c, halt mode cg = cd = 100 pf, rf = 1 m , figure 6 ta = 25 c, c1 = c2 = 0.1 f, stack: figure 9, cl = 25 k , oscillator hold voltage | v hold 1 | 1/3 bias?/3 duty: fopg = 32.768 khz, 2.0 5.5 v figure 7, cg = 20 pf other methods: figure 4 c1 = c2 = 0.1 f, oscillator hold voltage | v hold 2 | ta = 25 c cl = 25 k , 2.3 5.5 v fopg = 65.536 khz, cg = 10 pf stack: figure 10, c1 = c2 = 0.1 f, 1/3 bias?/3 duty: cl = 25 k , figure 5, oscillator start voltage | vstt1 | figure 7, fopg = 32.768 khz, 2.2 v other methods: figure 4, cg = 20 pf ta = 25 c c1 = c2 = 0.1 f, cl = 25 k , oscillator start voltage | vstt2 | ta = 25 c figure 5, fopg = 65.536 khz, 2.6 v cg = 10 pf v ss 2 = ?.9 v, c1 = c2 = 0.1 f, cl = 25 k , 10 s oscillator start time tstt1 ta = 25 c, figure 5, fopg = 32.768 khz, v ss 2 = ?.5 v, cg = 20 pf 10 s ta = 25 c v ss 2 = ?.9 v, c1 = c2 = 0.1 f, cl = 25 k , 10 s oscillator start time tstt2 ta = 25 c, figure 5, fopg = 65.536 khz, v ss 2 = ?.5 v, cg = 10 pf 10 s ta = 25 c fopg = 400 khz, figure 6, oscillator start voltage | vstt4 | ta = 25 c cg = cd = 100 pf or 330 pf, 4.0 v rf = 1 m fopg = 400 khz, figure 6, oscillator hold voltage | v hold 4 | ta = 25 c cg = cd = 100 pf or 330 pf, 3.5 5.5 v rf = 1 m v ss 2 = ?.5 v, fopg = 400 khz, figure 6, oscillator start time tstt4 ta = 25 c cg = cd = 100 pf or 330 pf, 30 ms rf = 1 m continued on next page.
continued from preceding page. no. 4365- 20 /29 LC5852N parameter symbol conditions min typ max unit fopg = 800 khz, figure 6, oscillator start voltage | vstt5 | ta = 25 c cg = cd = 100 pf, 4.0 v rf = 1 m fopg = 800 khz, figure 6, oscillator hold voltage | v hold 5 | ta = 25 c cg = cd = 100 pf, 3.5 5.5 v rf = 1 m v ss 2 = ?.5 v, fopg = 800 khz, figure 6, oscillator start time tstt5 ta = 25 c cg = cd = 100 pf, 30 ms rf = 1 m 10p v ss 2 = ?.9 v 10p pin (chip products only) 10 pf oscillator correction capacitance 10p v ss 2 = ?.5 v 10p pin (chip products only) 10 pf 20p v ss 2 = ?.9 v oscout pin 20 pf 20p v ss 2 = ?.5 v oscout pin 20 pf figure 1 ceramic oscillator specifications figure 3 s1 to s4 and m1 to m4 input circuits figure 5 oscillator start voltage, oscillator start time and frequency stability test circuit figure 2 crystal oscillator specifications (32 khz or 65 khz) figure 4 power supply current and oscillator hold voltage test circuit figure 6 oscillator start voltage, oscillator start time, power supply current and oscillator hold voltage test circuit recommended ceramic oscillator s manufacturer murata kyocera item frequency type number cg (pf) cd (pf) rf (m ) type number cg (pf) cd (pf) rf (m ) 400 khz csb400p 100 100 1 kbr-400b 330 330 1 800 khz csb800j 100 100 1 kbr-800h 100 100 1
no. 4365- 21 /29 LC5852N figure 7 power supply current and oscillator hold voltage test circuit figure 9 power supply current and oscillator hold time test circuit figure 8 external input specifications
these electrical specifications are provisional and subject to change. ag specifications absolute maximum ratings at ta = 25 c, v dd = 0 v allowable operating ranges at ta = 25 2 c, v dd = 0 v electrical characteristics at ta = 25 2 c, v dd = 0 v note: * s1, s2, s3, s4, m1, m2, m3, m4 no. 4365- 22 /29 LC5852N parameter symbol conditions/pins min typ max unit v ss 1 ?.0 +0.3 v maximum supply voltage v ss 2 ?.0 +0.3 v v ss 3 lcd drive method (1/3 bias) ?.5 +0.3 v v ss 3 lcd drive method (methods other than 1/3 bias) ?.0 +0.3 v s1 to 4, m1 to 4, i/oa1 to 4, i/ob1 to 4, int, testa maximum input voltage v in 1 (with i/oa1 to 4 and i/ob1 to 4 in input mode), v ss 1 ?0.3 +0.3 v 1op, oscin, res, bak alm, light, p1 to 4, i/oa1 to 4, i/ob1 to 4, v out 1 cup2 (with i/oa1 to 4 and i/ob1 to 4 in output mode), v ss 1 ?0.3 +0.3 v maximum output voltage testa, oscout v out 3 segout, com1 to 4, cup1 v ss 1 ?0.3 +0.3 v operating temperature topr ?0 +65 c storage temperature tstg ?0 +125 c parameter symbol conditions/pins min typ max unit v ss 1 v bak = v ss 1 ?.65 ?.3 v supply voltage v ss 2 ?.3 ?.4 v v ss 3 lcd drive method (1/3 bias) ?.95 ?.7 v v ss 3 lcd drive method (methods other than 1/3 bias) v ss 3 = v ss 2 input high level voltage v ih s1 to 4, m1 to 4, i/oa1 to 4, i/ob1 to 4, res, int ?.2 0 v (with i/oa1 to 4 and i/ob1 to 4 in input mode) input low level voltage v il s1 to 4, m1 to 4, i/oa1 to 4, i/ob1 to 4, int v ss 1 v ss 1 + 0.2 v (with i/oa1 to 4 and i/ob1 to 4 in input mode) operating frequency fopg ta = ?0 to +65 c 32 33 khz parameter symbol conditions/pins min typ max unit r in 1a v ss 1 = ?.55 v, low-level hold transistor * , 10 50 200 k v il = v ss 1 + 0.2 v figure 1 r in 1b v ss 1 = ?.55 v low-level pull-down resistor * , 200 550 2000 k figure 1 input resistance r in 2a vss1 = ?.55 v, int pull-up resistor 200 400 2000 k v il = v ss 1 r in 2b v ss 1 = ?.55 v, int pull-down resistor 200 550 2000 k v ih = v dd r in 3 v ss 1 = ?.55 v, res pull-down resistor 5 50 k v ih = v dd output high level voltage v oh (1) v ss = ?.35 v, alm, light ?.65 v i oh = ?50 a output low level voltage v ol (1) v ss 1 = ?.35 v, alm, light v ss 1 v i ol = 250 a + 0.65 v ss = ?.55 v, i/oa1 to 4, i/ob1 to 4, output high level voltage v oh (2) i oh = ?0 a, p1 to 4 ?.2 v (with i/oa1 to 4 and i/ob1 to 4 in output mode) v ss 1 = ?.55 v, i/oa1 to 4, i/ob1 to 4, output low level voltage v ol (2) i ol = 20 a, p1 to 4 v ss 1 + 0.2 (with i/oa1 to 4 and i/ob1 to 4 in output mode) continued on next page.
continued from preceding page. no. 4365- 23 /29 LC5852N parameter symbol conditions/pins min typ max unit segment driver output impedances ?when used as cmos output ports output high level voltage v oh (3) v ss 1 = ?.55 v, ?.3 v i oh = ? a output low level voltage v ol (3) v ss 1 = ?.55 v, v ss 2 + 0.3 v i ol = 3 a ?when used as p-channel open drain outputs output high level voltage v oh (3) v ss 1 = ?.55 v, ? ?.3 v i oh = ? a output off leakage current i off v ss 1 = ?.55 v, 1 a v ol = v ss 1 ?static drive output high level voltage v oh (3) v ss 1 = ?.55 v, ?.2 v i oh = ?.4 a segout output low level voltage v ol (3) v ss 1 = ?.55 v, v ss 2 + 0.2 v i ol = 0.4 a output high level voltage v oh (4) v ss 1 = ?.55 v, ?.2 v i oh = ? a com1 output low level voltage v ol (4) v ss 1 = ?.55 v, v ss 2 + 0.2 v i ol = 4 a ?duplex drive (1/2 bias?/2 duty) output high level voltage v oh (3) v ss 1 = ?.55 v, ?.2 v i oh = ?.4 a segout output low level voltage v ol (3) v ss 1 = ?.55 v, v ss 2 + 0.2 v i ol = 0.4 a output high level voltage v oh (4) v ss 1 = ?.55 v, ?.2 v i oh = ? a output middle level voltage v om v ss 1 = ?.55 v, com1, 2 v ss 1 ?0.2 v ss 1 + 0.2 v i oh = ? a, i ol = 4 a output low level voltage v ol (4) v ss 2 = ?.55 v, v ss 2 + 0.2 v i ol = 4 a ?1/2 bias?/3 duty and 1/2 bias?/4 duty methods output high level voltage v oh (3) v ss 1 = ?.55 v, ?.2 v i oh = ?.4 a segout output low level voltage v ol (3) v ss 1 = ?.55 v, v ss 2 + 0.2 v i ol = 0.4 a output high level voltage v oh (4) v ss 1 = ?.55 v, ?.2 i oh = ? a output middle level voltage v om v ss 1 = ?.55 v, v ss 1 ?0.2 v ss 1 + 0.2 v i oh = ? a, i ol = 4 a output low level voltage v ol (4) v ss 2 = ?.55 v, v ss 2 + 0.2 v i ol = 4 a ?1/3 bias?/3 duty and 1/3 bias?/4 duty methods output high level voltage v oh (3) v ss 1 = ?.55 v, ?.2 v i oh = ?.4 a v ss 1 = ?.55 v, output m1 level voltage v om 1-3 i oh = ?.4 a, v ss 1 ?0.2 v ss 1 + 0.2 v i ol = 0.4 a segout v ss 1 = ?.55 v, output m2 level voltage v om 2-3 i oh = ?.4 a, v ss 2 ?0.2 v ss 2 + 0.2 v i ol = 0.4 a output low level voltage v ol (3) v ss 1 = ?.55 v, v ss 3 + 0.2 v i ol = 0.4 a output high level voltage v oh (4) v ss 1 = ?.55 v, ?.2 i oh = ? a output m1 level voltage v om 1-4 v ss 1 = ?.55 v, v ss 1 ?0.2 v ss 1 + 0.2 v i oh = ? a, i ol = 4 a output m2 level voltage v om 2-4 v ss 1 = ?.55 v, v ss 2 ?0.2 v ss 2 + 0.2 v i oh = ? a, i ol = 4 a output low level voltage v ol (4) v ss 2 = ?.55 v, v ss 3 + 0.2 v i ol = 4 a segment pads 38 to 41 and 44 to 61, qip64 pins 11 to 23 and 25 to 33 segment pads 62 to 64, qip64 pins 34 to 36 com1 to 3 (for 1/3 duty methods) com 1 to 4 (for 1/4 duty methods) com1 to 3 (for 1/3 duty methods) com 1 to 4 (for 1/4 duty methods) continued on next page.
continued from preceding page. no. 4365- 24 /29 LC5852N parameter symbol conditions/pins min typ max unit ?output voltage lcd drive: 1/3 bias methods v ss 2 v ss 1 = ?.35 v, fopg = 32.768 khz, ?.5 v (doubler) c1 to 4 = 0.1 f figure 7 (tripler) v ss 3 v ss 1 = ?.35 v, fopg = 32.768 khz, ?.75 v c1 to 4 = 0.1 f figure 7 lcd drive: 1/2 bias methods v ss 2 v ss 1 = ?.35 v, fopg = 32.768 khz, ?.5 v (doubler) c1 = c2 = 0.1 f figure 2 ?supply current (when the backup flag is cleared to zero) v ss 1 = ?.55 v, in halt mode, lcd drive: 1/3 bias methods | i dd | c1 to 4 = 0.1 f cl = 25 k , figure 7, 1.3 4.5 a cd = cg = 20 pf 32.768 khz, x?al lcd drive: methods v ss 1 = ?.55 v, in halt mode, other than 1/3 bias | i dd | c1 = c2 = 0.1 f cl = 25 k , figure 2, 1.1 4.5 a cd = cg = 20 pf 32.768 khz, x?al oscillator start voltage v ss 1 | vstt | cd = cg = 20 pf cl = 25 k , figure 3, 1.35 v 32.768 khz, x?al oscillator hold voltage v ss 1 | v hold | cd = cg = 20 pf cl = 25 k , figure 2, 1.3 1.6 v 32.768 khz, x?al oscillator start time tstt v ss 1 = ?.35 v, cl = 25 k , figure 3, 10 s cd = cg = 20 pf 32.768 khz, x?al oscillator correction capacitance 10p external connection (for chip products) 8 10 12 pf 20p oscout 16 20 24 pf
these electrical specifications are provisional and subject to change. li specifications absolute maximum ratings at ta = 25 2 c, v dd = 0 v allowable operating ranges at ta = 25 2 c, v dd = 0 v electrical characteristics at ta = 25 2 c, v dd = 0 v note: * s1, s2, s3, s4, m1, m2, m3, m4 no. 4365- 25 /29 LC5852N parameter symbol conditions/pins min typ max unit v ss 1 v bak = v ss 1 or v ss 2 ?.0 +0.3 v maximum supply voltage v ss 2 ?.0 +0.3 v v ss 3 lcd drive: 1/3 bias methods ?.5 +0.3 v v ss 3 lcd drive: methods other than 1/3 bias ?.0 +0.3 v v in 1 10p, oscin v bak ?0.3 +0.3 v maximum input voltage v in 2 s1 to 4, m1 to 4, i/ia1 to 4, i/ob1 to 4, res, int, v ss 2 ?0.3 +0.3 v testa, (with i/oa1 to 4 and i/ob1 to 4 in input mode) v out 1 test, oscout v bak ?0.3 +0.3 v maximum output voltage v out 2 alm, light, p1 to 4, i/oa1 to 4, i/ob1 to 4, cup2 v ss 2 ?0.3 +0.3 v (with i/oa1 to 4 and i/ob1 to 4 in output mode) v out 3 segout, com1 to 4, cup1 v ss 3 ?0.3 +0.3 v operating temperature topr ?0 +65 c storage temperature tstg ?0 +125 c parameter symbol conditions/pins min typ max unit r in 1a v ss 2 = ?.9 v, low-level hold transistor * , 10 200 k v il = v ss 2 + 0.4 v figure 1 r in 1b v ss 2 = ?.9 v, pull-down resistor * , 200 2000 k figure 4 input resistance r in 2a v ss 2 = ?.9 v, int pull-up resistor 200 2000 k v il = v ss 2 r in 2b v ss 2 = ?.9 v, int pull-down resistor 200 2000 k v ih = v dd r in 3 v ss 2 = ?.9 v, res pull-down resistor 5 50 k v ih = v dd parameter symbol conditions/pins min typ max unit v bak ?.6 ?.3 v v ss 2 v bak = v ss 2/2 (with the backup flag cleared to zero) ?.6 ?.6 v supply voltage v ss 2 v bak = v ss 2 (with the backup flag cleared to zero) ?.6 ?.3 v v ss 3 lcd drive: 1/3 bias methods ?.95 ?.7 v ss 3 lcd drive: methods other than 1/3 bias v ss 3 = v ss 2 input high level voltage v ih s1 to 4, m1 to 4, i/oa1 to 4, i/ob1 to 4, int ?.4 0 v (with i/oa1 to 4 and i/ob1 to 4 in input mode) input low level voltage v il s1 to 4, m1 to 4, i/oa1 to 4, i/ob1 to 4, int v ss 2 v ss 2 + 0.4 v (with i/oa1 to 4 and i/ob1 to 4 in input mode) operating frequency fopg ta = ?0 to +65 c 32 33 khz continued on next page.
continued from preceding page. no. 4365- 26 /29 LC5852N parameter symbol conditions/pins min typ max unit output high level voltage v oh (1) v ss 2 = ?.4 v, alm ?.65 v i oh = ?50 a output low level voltage v ol (1) v ss 2 = ?.4 v, alm v ss 2 v i oh = 250 a + 0.65 v ss 2 = ?.9 v, i/oa1 to 4, i/ob1 to 4, output high level voltage v oh (2) i oh = ?0 a, p1 to 4 ?.4 v (with i/oa1 to 4 and i/ob1 to 4 in output mode) v ss 2 = ?.9 v, i/oa1 to 4, i/ob1 to 4, output low level voltage v ol (2) i ol = 40 a, p1 to 4 v ss 2 + 0.4 v (with i/oa1 to 4 and i/ob1 to 4 in output mode) output high level voltage v oh (3) v ss 2 = ?.9 v, light ?.5 v i oh = ?50 a output low level voltage v ol (3) v ss 2 = ?.9 v, light v ss 2 + 1.5 v i ol = 150 a segment driver output impedances ?when used as cmos output ports output high level voltage v oh (4) v ss 2 = ?.9 v, ?.3 v i oh = ? a output low level voltage v ol (4) v ss 2 = ?.9 v, v ss 2 + 0.3 v i ol = 5 a ?when used as p-channel open-drain output ports output high level voltage v oh (4) v ss 2 = ?.4 v, ? ?.3 v i oh = ?0 a output off leakage current i off v ss 2 = ?.9 v, 1 a v ol = v ss 2 ?static drive output high level voltage v oh (4) v ss 2 = ?.9 v, ?.2 v i oh = ?.4 a all segout pins output low level voltage v ol (4) v ss 2 = ?.9 v, v ss 2 + 0.2 v i ol = 0.4 a output high level voltage v oh (5) v ss 2 = ?.9 v, ?.2 v i oh = ? a com1 output low level voltage v ol (5) v ss 2 = ?.9 v, v ss 2 + 0.2 v i ol = 4 a ?duplex drive (1/2 bias?/2 duty) output high level voltage v oh (4) v ss 2 = ?.9 v, ?.2 v i oh = ?.4 a all segout pins output low level voltage v ol (4) v ss 2 = ?.9 v, v ss 2 + 0.2 v i ol = 0.4 a output high level voltage v oh (5) v ss 2 = ?.9 v, ?.2 v i oh = ? a output middle level voltage v om v ss 2 = ?.9 v, com1 to 4 v ss 2/2 v ss 2/2 v i oh = ? a, i ol = 4 a ?0.2 +0.2 output low level voltage v ol (5) v ss 2 = ?.9 v, v ss 2 + 0.2 v i ol = 4 a ?1/2 bias?/3 duty and 1/2 bias?/4 duty methods output high level voltage v oh (4) v ss 2 = ?.9 v, ?.2 v i oh = ?.4 a all segout pins output low level voltage v ol (4) v ss 2 = ?.9 v, v ss 2 + 0.2 v i ol = 0.4 a output high level voltage v oh (5) v ss 2 = ?.9 v, ?.2 v i oh = ? a output middle level voltage v om v ss 2 = ?.9 v, v ss 2/2 v ss 2/2 v i oh = ? a, i ol = 4 a ?0.2 +0.2 output low level voltage v ol (5) v ss 2 = ?.9 v, v ss 2 + 0.2 v i ol = 4 a segment pads 38 to 41 and 44 to 61, qip64 pins 11 to 23 and 25 to 33 segment pads 62 to 64, qip64 pins 34 to 36 com1 to 3 (for 1/3 duty methods) com1 to 4 (for 1/4 duty methods) continued on next page.
continued from preceding page. no. 4365- 27 /29 LC5852N parameter symbol conditions/pins min typ max unit ?1/3 bias?/3 duty and 1/3 bias?/4 duty methods output high level voltage v oh (4) v ss 2 = ?.9 v, ?.2 v i oh = ?.4 a v ss 2 = ?.9 v, v ss 2/2 v ss 2/2 output m1 level voltage v om 1-4 i oh = ?.4 a, ?0.2 +0.2 v i ol = 0.4 a all segout pins v ss 2 = ?.9 v, output m2 level voltage v om 2-4 i oh = ?.4 a, v ss 2 ?0.2 v ss 2 + 0.2 v i ol = 0.4 a output low level voltage v ol (4) v ss 2 = ?.9 v, v ss 3 + 0.2 v i ol = 0.4 a output high level voltage v oh (5) v ss 2 = ?.9 v, ?.2 v i oh = ? a output m1 level voltage v om 1-5 v ss 2 = ?.9 v, v ss 2/2 v ss 2/2 v i oh = ? a, i ol = 4 a ?0.2 +0.2 output m2 level voltage v om 2-5 v ss 2 = ?.9 v, v ss 2 ?0.2 v ss 2 + 0.2 v i oh = ? a, i ol = 4 a output low level voltage v ol (5) v ss 2 = ?.9 v, v ss 3 + 0.2 v i ol = 4 a ?output voltage lcd drive: 1/3 bias methods v ss 1 v ss 2 = ?.9 v, fopg = 32.768 khz, ?.35 v (halver) c1 to 3 = 0.1 f figure 7 (tripler) v ss 3 v ss 2 = ?.9 v, fopg = 32.768 khz, ?.1 v c1 to 3 = 0.1 f figure 7 lcd drive: 1/2 bias methods v ss 1 v ss 2 = ?.9 v, fopg = 32.768 khz, ?.35 v (halver) c1 = c2 = 0.1 f figure 4 ?supply current (when the backup flag is cleared to zero) v ss 2 = ?.9 v, in halt mode, lcd drive: 1/3 bias methods | i dd | c1 to 3 = 0.1 f, cl = 25 k , figure 7, 0.8 3.0 a cd = cg = 20 pf 32.768 khz xtal lcd drive: methods v ss 2 = ?.9 v, in halt mode, other than 1/3 bias | i dd | c1 = c2 = 0.1 f, cl = 25k , figure 4, 0.7 3.0 a cd = cg = 20 pf 32.768 khz xtal oscillator start voltage v ss 2 | vstt | v bak = v ss 2, cl = 25 k , figure 5, 1.35 v cd = cg = 20 pf 32.768 khz xtal oscillator hold voltage v ss 2 v bak = v ss 2/2, cl = 25k , figure 4, (when the backup flag is | v hold (1) | cd = cg = 20 pf 32.768 khz xtal 2.6 3.6 v cleared to zero) (when the backup flag is | v hold (2) | v bak = v ss 2, cl = 25k , figure 4, 1.3 3.6 v cleared to zero) cd = cg = 20 pf 32.768 khz xtal oscillator start time tstt v bak = v ss 2 = ?.9 v, cl = 25k , figure 5, 10 s cd = cg = 20 pf 32.768 khz xtal oscillator correction capacitance 10p external connection 8 10 12 pf 20p oscout 16 20 24 pf com1 to 3 (for 1/3 duty methods) com1 to 4 (for 1/4 duty methods) figure 1 ceramic oscillator specifications figure 2 crystal oscillator specifications (32 khz or 65 khz)
no. 4365- 28 /29 LC5852N figure 3 s1 to s4 and m1 to m4 input circuits figure 5 oscillator start voltage, oscillator start time and frequency stability test circuit figure 7 power supply current and oscillator hold voltage test circuit figure 9 power supply current and oscillator hold time test circuit figure 4 power supply current and oscillator hold voltage test circuit figure 6 oscillator start voltage, oscillator start time, power supply current and oscillator hold voltage test circuit figure 8 external input specifications
no. 4365- 29 /29 LC5852N this catalog provides information as of february, 1997. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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