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s1d2502a01 video amp merged osd processor for monitors 0 preliminary video amp merged osd processor the s1d2502a01 is a very high frequency video amplifier & wide range osd processor 1 chip system with i 2 c bus control used in monitors. it contains 3 matched r/g/b video amplifiers with osd processor and provides flexible interfacing to i 2 c bus controlled adjustment systems. functions r/g/b video amplifier osd processor i 2 c bus control cut-off brightness control r/g/b sub contrast/cut-off control half tone features video amp part 3-channel r/g/b video amplifier, 175mhz @f-3db i 2 c bus control items ? contrast control: -38db ? sub contrast control for each channel: -12db ? brightness control ? osd contrast control: -38db ? cut-off brightness control (ac coupling) ? cut-off control for each channel (ac coupling) ? switch registers for sblk and video half tone and clp/blk polarity selection and int/ext clp selection and generated clp width control built in abl (automatic beam limitation) built in video input clamp, brt clamp built in video half tone (3mode) function on osd pictures capable of 8.0vp-p output swing improvement of rise & fall time (2.2ns) cut-off brightness control built in blank gate with spot killer clamp pulse generator osd intensity blk, clp polarity selection clamp gate with anti osd sagging 32-dip-600a ordering information device package operating temperature s1d2502a01-d0b0 32-dip-600a -20 c ? +75 c osd part built in 1k-byte sram 448 rom fonts (each font consists of 12 18 dots.) full screen memory architecture wide range pll available (15khz ? 96khz, reference 800 x 600) programmable vertical height of character programmable vertical and horizontal positioning character color selection up to 16 different colors programmable background color (up to 16 colors) character blinking, bordering and shadowing color blinking character scrolling fade-in and fade-out box drawing character sizing up to four times 76.8mhz pixel frequency from on-chip pll (reference 800 x 600)
video amp merged osd processor for monitors s1d2502a01 1 preliminary block diagram figure 1. functional block diagram latches d/ a rom (448 x 18 x 12) vdd vdda ram (480 x 16) data receiver osd pll control register display controller output stage font data timing controller frame ctrl rom ctrl band gap.ref multi (3 mode) half tone rgb osd fbl inte ht det. blk int clamp pulse gen. clp blk hflb clk h_pulse v_pulse i 2 c bus decoder 32 1 3 30 29 6 2 v/i 27 26 25 v/i v/i r cut off g cut off b cut off r/g/b osd fblk intensity 10 abl video input clamp video half tone sw sub cont. control video contras t osd input cilp. osd half tone sw osd cont. control i 2 c i 2 c i 2 c fblk fblk i 2 c clp ht det. 12 7 r osd + sub cont. control 24 birght control blk clp i 2 c 22 23 i 2 c cont. cntl g-channel b-channel clp ht det. fblk clp blk i 2 c clp ht det. fblk clp blk i 2 c 16 14 g osd b osd 13 15 8 5 4 9 11 28 31 20 21 17 18 vssa hflb vflb vco_in_p sda scl rct gct bct clp_in r out vcc2 r clp g clp g out b clp b out vss vcc3 gnd3 vref1 vref abl cont_cap rin gnd1 vcc1 gin bin rom address ram data 9 16 16 ctrl data 12 display ctrl h/v/clk ctrl h/v/clk ctrl frame ctrl rom ctrl amp out ctrl font 19 gnd2
s1d2502a01 video amp merged osd processor for monitors 2 preliminary pin configuration figure 2. pin configuration 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 hflb vdd sda scl vss rct gct bct rout rclp vcc2 gout gclp gnd2 bout bclp vflb vssa vco_in_p vref1 vref vdda cont_cap abl_in gnd3 clp_in vcc3 rin vcc1 gin gnd1 bin s1d2502a01
video amp merged osd processor for monitors s1d2502a01 3 preliminary table 1. pin configuration pin no. symbol i/o configuration 1 vflb i vertical flyback signal 2 vssa - ground (pll part) 3vco_in_pi this voltage is generated at the external loop filter and goes into the input stage of the vco. 4 vref1 o charge pump output 5 vref o pll regulator filter 6 vdda - +5v supply voltage for pll part 7 cont_cap - contrast control for amp part 8 abl - auto beam limit. 9 gnd3 - ground for video amp part(for amp control) 10 clp_in - video clamp pulse input 11 vcc3 - +12v supply voltage for video amp part(for amp control) 12 rin i video signal input (red) 13 vcc1 - +12v supply voltage for video amp(for main video signal process) 14 gin i video signal input (green) 15 gnd1 - ground for video amp part(for main video signal process) 16 bin i video signal input (blue) 17 bclp - b output clamp cap 18 bout o video signal output (blue) 19 gnd2 - ground for video amp part(for video output drive) 20 gclp - g output clamp cap 21 gout o video signal output (green) 22 vcc2 - +12v supply voltage for video amp part(for video output drive) 23 rclp - r output clamp cap 24 rout o video signal output (red) 25 bct - b cut-off output 26 gct - g cut-off output 27 rct - r cut-off output 28 vss - ground for digital part 29 scl i serial clock (i 2 c) 30 sda i/o serial data (i 2 c) 31 vdd - +5v supply voltage for digital part 32 hflb i horizontal flyback signal
s1d2502a01 video amp merged osd processor for monitors 4 preliminary pin description table 2. pin description pin no pin name schematic description 1 32 vflb hflb flb signal is in ttl level multi polarity input 3 4 5 vco_in_p vpef/ vref pll loop filter output bandgap ref. output 7 contrast cap (cont_cap) contrast cap range (0.1uf ? 5uf) 8abl_in abl input dc range (1 ? 4.5v) vflb hflb 4.0k 100 a vref i 2 c data 2k 250 a vref vref 100k vcc
video amp merged osd processor for monitors s1d2502a01 5 preliminary 10 clp_in multi polarity input clamp gate pulse ttl level input 12 14 16 red video input (rin) green video input (gin) blue video input (bin) max input video signal is 0.7 vpp 17 20 23 blue (b clamp cap) green (g clamp cap) red (r clamp) brightness controlling actives by charging and discharging of the external cap. (0.1 f) (during clamp gate) table 2. pin description (continued) pin no pin name schematic description 10k 50k vcc 12k 0.2k vcc video_in vcc clp 0.2k 0.2k iclamp
s1d2502a01 video amp merged osd processor for monitors 6 preliminary 18 21 24 blue video output (bout) green video output (gout) red video output (rout) video signal output 27 26 25 red cut-off control (rct) green cut-off control (gct) blue cut-off control (bct) cut-off control output 29 scl serial clock input port of i 2 c bus 30 sda serial data input port of i 2 c bus table 2. pin description (continued) pin no pin name schematic description isink 0.04k vcc video_out 0.5k 0.05k ctx 0.2k 0-600ua 0-200ua 50ua 100ua scl scl ack
video amp merged osd processor for monitors s1d2502a01 7 preliminary absolute maximum ratings (see 1) (ta = 25 c) thermal & esd parameter table 3. absolute maximum ratings no item symbol value unit min typ max 1 maximum supply voltage v cc - - 13.2 v v dd --6.5 2 operating temperature (see 2) topr -20 - 75 c 3 storage temperature tstg -65 150 c 4 operating supply voltage v ccop 11.4 12.0 12.6 v (see 3) v ddop 4.75 5.00 5.25 5 power dissipation p d -- w table 4. thermal & esd parameter no item symbol value unit min typ max 1 thermal resistance (junction-ambient) ja - 48 - c/w 2 junction temperature tj - 150 - c 3 human body model (c = 100p, r = 1.5k) hbm 2 - - kv 4 machine model (c = 200p, r = 0) mm 300 - - v 5 charge device model cdm 800 - - v
s1d2502a01 video amp merged osd processor for monitors 8 preliminary electrical characteristics dc electrical characteristics (tamb = 25 c, v cc = 12v, v dd = v dda = 5v, abl input voltage = 5v, hflb input signal = s3, load resistors = 470 ? , except osd part current 35 ma, unless otherwise stated) table 5. dc electrical characteristics parameter symbol conditions value unit min typ max supply current i cc (see 4) 100 125 130 ma minimum supply current i cc min v cc = 11.4v 95 110 120 ma maximum supply current i cc max v cc = 12.6v 105 130 140 ma abs supply current i cc abs v cc = 13.2v - - 175 ma video input bias voltage v bias 1.8 2.1 2.4 v video black level voltage (por) v blackpor 1.20 1.50 1.80 v black level voltage channel difference (por) ? v blackpor (see 5) ? 10 - - % video black level voltage (ffh) v blackff 04 = ffh (see 13) 2.2 2.7 3.2 v black level voltage channel difference (ffh) ? v blackff ? 10 - - % video black level voltage (00h) v black00 04 = 00h - 0.2 0.5 v black level voltage channel difference (00h) ? v black00 ? 10 - - % spot killer voltage vspot v cc = var. 9.20 10.4 11.2 v cut-off current (ffh) ictff pin25, 26, 27 = 12v 09 ? 0b: ffh 0c: 00h 500 625 750 a cut-off current (00h) ict00 pin25, 26, 27 = 12v 09 ? 0c: 00h -2.05.0 a cut-off brightness current (ffh) ictbrtff pin25, 26, 27 = 12v 09 ? 0b: 00h 0c: ffh 100 180 260 a cut-off brightness current (80h) ictbrt80 pin25, 26, 27 = 12v 09 ? 0b: 00h 0c: 80h 50 90 130 a cut-off offset current 1 ics1 pin25, 26, 27 = 12v 09 ? 0c: 00h 0e: 11h 25 50 75 a
video amp merged osd processor for monitors s1d2502a01 9 preliminary total external cut-off current range cut-off offset current 2 ics2 pin25, 26, 27 = 12v 09 ? 0c: 00h 0e: 12h 50 100 130 a soft blk output voltage vsblk 0d: 80h 0e: 14h -0.20.5v clamp cap voltage (por) vcap 6.0 7.0 8.0 v table 5. dc electrical characteristics (continued) parameter symbol conditions value unit min typ max red cut-off creen cut-off blue cut-off cut-off brightness cs2 cs1 cut-off offset switch 600ua 200ua 100ua 50ua 150ua
s1d2502a01 video amp merged osd processor for monitors 10 preliminary ac electrical characteristics (tamb = 25 c, v cc = 12v, v dd = v dda = 5v, abl input voltage = 5v, hflb input signal = s3, load resistors = 470 ? , vin = 0.7vpp manually adjust video output pins 18, 21 and 24 to 4v dc for the ac test (see 11) unless otherwise stated (see 12) ) table 6. ac electrical characteristics parameter symbol conditions value unit min typ max contrast max. output voltage vcff 03, 05, 06, 07 = ffh 04, 08 ? 0c = 80h rgb input = s1 5.0 5.7 6.4 vpp contrast max. output channel difference ? vcff ? 10 - - % contrast center output voltage vc80 03, 04, 08 ~ 0c = 80h 05, 06, 07 = ffh rgb input = s1 2.52.853.2vpp contrast center output channel difference ? vc80 ? 10 - - % contrast max. - center attenuation c c = 20log (vc80/vcff) -8 -6 -4 db sub contrast center output voltage vd80 03 = ffh 04 ? 0c = 80h rgb input = s1 2.3 2.6 2.9 vpp sub contrast center output channel difference ? vd80 ? 10 - - % sub contrast min. output voltage vd00 03 = ffh, 05 ? 07: 00h 04, 08 ? 0c = 80h rgb input = s1 1.3 1.6 1.9 vpp sub contrast min. output channel difference ? vd00 ? 10 - - % sub contrast max. - min. attenuation d d = 20log (vd00/vcff) -14 -12 -10 db abl control range abl (see 15) -12 -10 -8 db r/g/b video rising time (see 7) tr (video) 03, 05 ~ 07: ffh 04, 08 ~ 0c: 80h rgb input = s2 -2.22.8ns r/g/b video falling time (see 7) tf (video) - 2.2 2.8 ns r/g/b blank output rising time (see 7) tr (blank) por hflb: s4 - 6.0 12.0 ns r/g/b blank output falling time (see 7) tf (blank) - 8.0 15.0 ns r/g/b video band width (see 7, 8) f (-3db) (see 16) 175 - - mhz video amp 50mhz cross talk ct_50m (see7, 9) (see 17) --25-20db video amp 130mhz cross talk ct_130m (see7, 9) (see 18) --15-10db absolute gain match avmatch (see 6) -1 - 1 db gain change between amplifier avtrack (see 7) -1 - 1 db
video amp merged osd processor for monitors s1d2502a01 11 preliminary osd electrical charcteristics (tamb = 25 c, v cc = 12v, v dd = v dda = 5v, hflb input voltage = s3, load rosistors = 470 ? , v-amp test registor?s fblk, osd input conditions unless otherwise stated) table 7. osd electrical chaacteristics parameter symbol conditions value unit min typ max osd contrast max. output voltage vocff 08 = ffh osd rgb output conditions 5.4 6.4 7.4 vpp osd contrast max. output channel difference ? vocff ? 10 - - % osd contrast center output voltage voc80 08 = 80h osd rgb output conditions 2.7 3.2 3.7 vpp osd contrast center output channel difference ? voc80 ? 10 - - % r/g/b osd rising time tr (osd) 08: ffh - 4.0 5.0 ns r/g/b osd falling time tf (osd) - 4.0 5.0 ns ht video level htvideo abl = 6v rgb input = s1 03, 05 ? 08: ffh 0d: 01h osd black conditions input htvideo = 20log(v htvideo /v cff ) -6.0 -4.5 -3.0 db ht video output channel difference ? htvideo ? 15 - - % ht osd level htosd abl = 6v 05 ? 08: ffh 0d: 0fh osd white condition input htosd = 20log (v htosd / v ocff ) -7.0 -5.5 -4.0 db ht osd output channel difference ? htosd ? 15 - - %
s1d2502a01 video amp merged osd processor for monitors 12 preliminary operation timings table 8. operation timings parameter symbol min typ max unit input signal hflb, vflb horizontal flyback signal frequency f hflb --120khz vertical flyback signal frequency f vflb --200 hz i 2 c interface sda, scl (refer to figure 3) scl clock frequency f scl --300khz hold time for start condition t hs 500 - - ns set up time for stop condition t sus 500 - - ns low duration of clock t low 400 - - ns high duration of clock t high 400 - - ns hold time for data t hd 0--ns set up time for data t sud 500 - - ns time between 2 access t ss 500 - - ns fall time of sda t fsda --20ns rise time of both scl and sda t rsda ---ns figure 3. i 2 c bus timing diagram sda scl ths tsud tss thd thigh tlow tsus
video amp merged osd processor for monitors s1d2502a01 13 preliminary osd part electrical characteristics osd part dc electrical characteristics (ta = 25 c, v dda = v dd = 5v) table 9. osd part dc electrical characteristics parameter symbol min typ max unit supply voltage v dd 4.75 5.00 5.25 v supply current (no load on any output) i dd --25ma input voltage v ih 0.8v dd -- v v il --v ss + 0.4 v output voltage (lout = 1ma) v oh 0.8v dd -- v v ol --v ss + 0.4 v input leakage current i il -10 - 10 a vco input voltage v vco 2.5 v
s1d2502a01 video amp merged osd processor for monitors 14 preliminary notes: 1. absolute maximum rating indicates the limit beyond which damage to the device may occur. 2. operating ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. for guaranteed specifications and test conditions, see the electrical characteristics. the guaranteed specifications app ly only for the test conditions listed. some performance characteristics may degrade when the device is not operated under the listed test conditions. 3. v cc supply pins 11, 13, and 22 must be externally wired together to prevent internal damage during v cc power on/off cycles. 4. the supply current specified is the quiescent current for vcc 1 /vcc 2 and vcc 3 with rl = , the supply current for vcc2 (pin 22) also depends on the output load. 5. output voltage is dependent on load resistor. test circuit uses rl = 470 ? 6. measure gain difference between any two amplifiers vin = 700mvpp. 7. when measuring video amplifier bandwidth or pulse rise and fall times, a double sided full ground plane printed circuit board without socket is recommended. video amplifier 50mhz cross talk test also requires this printed circuit board. the reason for a double sided full ground plane pcb is that large measurement variations occur in single sided pcbs. 8. adjust input frequency from 10mhz (av max reference level) to the -3db frequency (f -3db). 9. measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. terminate the undriven amplifier inputs to simulate generator loading. repeat test at fin = 50mhz for cross talk 50mhz. 10. a minimum pulse width of 200 ns is guaranteed for a horizontal line of 15khz. this limit is guaranteed by design. if a lower line rate is used a longer clamp pulse may be required. 11. during the ac test the 4v dc level is the center voltage of the ac output signal. for example. if the output is 4vpp the signal will swing between 2v dc and 6v dc. 12. these parameters are not tested on each product which is controlled by an internal qualification procedure. 13. the conditions block?s 03, 04, 05... etc. signify sub address? 0f03, 0f04, 0f05... etc. 14. sub address 0f03, 0f05 ~ 0f07: ffh 0f04, 0f08 ~ 0f0c: 80h rgb input = s1, when the abl input voltage is 0v, the r/g/b?s output voltage is vr/vg/vb and uses the formula ablr = 20log (vr/v cffr ) 15. osd tst mode = high, clp operation off, rgb input = s5 (frequency sweep), rgb input clamp cap = 2.1v dc, rgb clamp cap (pin 23/20/17) = vcap voltage (7.0v), s5?s frequency 1mhz 130mhz sweep, -3db point = 20log (v 130mhz / v 1mhz ) 03, 05 ~ 07: ffh 04, 08 ~ 0c: 80h 0f: 80h 16. osd tst mode = high, clp operation off, rgb input clamp cap = 2.1v dc, rgb clamp cap (pin 23/20/17) = vcap voltage (7.0v), 03, 05 ~ 07: ffh 04, 08 ~ 0c: 80h 0f: 80h r input = s5 (50mhz) ct_50m = 20log (v outg /v outr ) or 20log (v outb / v outr ) 17. osd tst mode = high, clp operation off, rgb input clamp cap = 2.1v dc, rgb clamp cap (pin 23/20/17) = vcap voltage (7.0v), 03, 05 ~ 07: ffh 04, 08 ~ 0c: 80h 0f: 80h r input = s5 (130mhz) ct_150m = 20log (v outg /v outr ) or 20log (v outb /v outr )
video amp merged osd processor for monitors s1d2502a01 15 preliminary test signal format s1, s2 signal?s low level must be synchronized with the s3 signal?s sync. term. the input signal level uses the ic pin as reference. table 10. test signal format signal name input signal formal signal description s1 video gain measurement video = 1mhz/0.7vpp sync = 50khz s2 video tr/tf measurement f = 200khz v = 0.7vpp duty = 50% s3 hflb (posi & nega.) input f = 50khz t = 2us v = 0v/5v s4 osd level measurement blank tr/tf measurement f = 50khz v = 0v/5v s5 crosstalk test bandwidth measurement 1mhz/10mhz/50mhz/ 130mhz vref = input clamp voltage vi = 0.7vpp sync [v] 4us [t] video [v] [t] vpp 0.7 f = 200khz duty = 50% [t] t = 2us [v] f = 50khz 0v 5v [v] [t] f = 200khz duty = 50% [v] [t] vref [v] vi
s1d2502a01 video amp merged osd processor for monitors 16 preliminary test circuit figure 4. test circuit kb2502 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vflb vssa vco_in_p vref1 vref vdda cont_cap abl_in gnd3 clp_in vcc3 rin vcc1 gin gnd1 bin hflb vdd sda scl vss rct gct bct rout rclp vcc2 gout gclp gnd2 bout bclp 0.1u 75 bnc9 bnc8 bnc7 75 75 0.1u 100u 0.1u 100u 33 bnc6 100 abl 1u 100u 103 4.7u 27k sw1 1 2 30m 562 5.6k 33 bnc2 33 bnc1 33 bnc3 470 0.1u 470 0.1u 470 2k 2k 2k 33 33 4.7k 4.7k bnc5 bnc4 100u v cc = 12.0v magnetic core v dd = 5.0 v 0.1u 1m 1u s1d2502a01
video amp merged osd processor for monitors s1d2502a01 17 preliminary functional descriptions data transmission the interface between s1d2502a01 and mcu follows the i 2 c protocol. after the starting pulse, the transmission takes place in the following order: slave address with r/w bit, 2-byte register address, 2-byte data, and stop condition. an acknowledge signal is received for each byte, excluding only the start/stop condition. the 2-byte register address is composed of an 8-bit row address, and an 8-bit column address. the order of transmission for a 2-byte register address is 'row address column address'. the 2 bytes of data is because s1d2502a01 has a 16-bit base register configuration. s1d2502a01's slave address is bah. it is bbh in read mode, and bah in write mode. address bit pattern for display registers data (a) row address bit pattern r3 - r0: valid data for row address (b) column address bit pattern c4 - c0: valid data for column address x:don't care bit data transmission format a15 a14 a13 a12 a11 a10 a9 a8 xxxxr3r2r1r0 a7 a6 a5 a4 a3 a2 a1 a0 x x x c4 c3 c2 c1 c0 figure 5. data transmission format at writing operation figure 6. data transmission format at reading operation start slave address ack row address ack column address ack data byte n ack data byte n+1 ack stop start slave address ack row address ack column address ack stop start slave address ack data byte n ack data byte n+1 ack stop
s1d2502a01 video amp merged osd processor for monitors 18 preliminary sda / scl signal at communication figure 7. sda line and scl line (write operation) figure 8. sda line and scl line (read operation) sda a5 a4 a3 a2 a1 a0 a6 a7 a9 a8 a10 a11 a12 a13 a14 a15 r/w scl start iic slave address ack msb address ack lsb address ack scl d1 d0 d2 d3 d4 d5 d6 d7 sda d1 d0 d2 d3 d4 d5 d6 d7 ack data byte n(msb data) ack stop ack data byte n(lsb data) d1 d0 d2 d3 d4 d5 d6 d7 data byte n(msb data) ... ... sda a5 a4 a3 a2 a1 a0 a6 a7 a9 a8 a10 a11 a12 a13 a14 a15 r/w scl start iic slave address ack msb address ack lsb address ack scl d9 d8 d10 d11 d12 d13 d14 d15 sda d1 d0 d2 d3 d4 d5 d6 d7 ack data byte n(lsb) ack stop ack data byte n(msb) stop r/w start iic slave address
video amp merged osd processor for monitors s1d2502a01 19 preliminary memory map the display ram's address of the row and column number are assigned in order. the display ram is composed of 4 register groups (character & attribute register, row attribute register, frame control register, and v-amp control register). the display area in the monitor screen is 30 column 15 row, so the related character & attribute registers are also 30 column 15 row. each register has a character address and characteristics corresponding to the display location on the screen, and one register is composed of 16 bits. the lower 9 bits select the font from the 448 rom fonts, and the upper 7 bits give font characteristics to the selected font. the row attribute register takes up the display ram's 31st column. it provides raster color, raster color intensity, character color intensity, horizontal & vertical character size, box, border, and shadow features in units of row. the frame control registers are in the 16th row. it controls osd's display location, character height, scroll, and fade-in/out in units of frame. the v-amp control registers are also located in the 16th row. figure 9. memory map of display registers 00 01 02 03 06 00 01 00 01 02 13 14 12 27 28 29 character & attribute registers (30 x15 character display) frame control registers v-amp control registers 30 row attribute registers 15 0405 08 07 0910 11 12 13 14 15 16 v-amp test registers row row row test registers 31 row row row
s1d2502a01 video amp merged osd processor for monitors 20 preliminary register description binv box1 box0 b g r blink/fint c8 c7 c6 c5 c4 c3 c2 c1 c0 fed cba 9 876543210 character attribute character code (448 fonts) ? ? ? ? character & attribute register: row00 ~ 14, column00 ~ 29 rb rg rr rint cint hz2 hz0 vz1 vz0 f e d c b a9876543210 ? ? ? ? row attribute register: row00 ~ 14, column30 - bren inte cbil boxe bord sha raster color intensity character size - - erase en scrl scrt bli1 bli0 blit f e d c b a9876543210 ? ? ? ? frame control register 0: row15, column00 - fde fdet vpol hpol - - dot0 - fblk ch5 ch4 ch3 ch2 ch1 ch0 f e d c b a9876543210 ? ? ? ? frame control register 1: row15, column01 cp1 cp0 fpll hf2 hf1 hf0 dot1 pll control character height control hp0 vp7 vp6 vp5 vp4 vp3 vp2 vp1 vp0 f e d c b a9876543210 ? ? ? ? frame control register 2: row15, column02 hp7 hp6 hp5 hp4 hp3 hp2 hp1 horizontal start position vertical start position - vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 f e d c b a9876543210 ? ? ? ? v-amp control register: row15, column03 ~ 15 - ------- contrast control column03 - brt7 brt6 brt5 brt4 brt3 brt2 brt1 brt0 f e d c b a9876543210 - ------- brightness control column04 - rsb7 rsb6 rsb5 rsb4 rsb3 rsb2 rsb1 rsb0 f e d c b a9876543210 - ------- r sub contrast control column05 - gsb7 gsb6 gsb5 gsb4 gsb3 gsb2 gsb1 gsb0 f e d c b a9876543210 - ------- g sub contrast control column06
video amp merged osd processor for monitors s1d2502a01 21 preliminary figure 10. register description - bsb7 bsb6 bsb5 bsb4 bsb3 bsb2 bsb1 bsb0 f e d c b a9876543210 ? ? ? ? v-amp control register: row15, column03 ~ 15 - ------ b sub control column07 - osd7 osd6 osd5 osd4 osd3 osd2 osd1 osd0 f e d c b a9876543210 - ------ osd contrast control column08 - rwb7 rwb6 rwb5 rwb4 rwb3 rwb2 rwb1 rwb0 f e d c b a9876543210 - ------ r cut-off control column09 - gwb7 gwb6 gwb5 gwb4 gwb3 gwb2 gwb1 gwb0 f e d c b a9876543210 - ------ g cut-off control column10 - bwb7 bwb6 bwb5 bwb4 bwb3 bwb2 bwb1 bwb0 f e d c b a9876543210 - ------ b cut-off control column11 - cut7 cut6 cut5 cut4 cut3 cut2 cut1 cut f e d c b a9876543210 - ------ cut-off brightness control column12 - sb hs6 hs5 hs4 hs3 hs2 hs1 ht f e d c b a9876543210 - ------ half tone & soft blank control column13 - clps clpp blkp bpw2 bpw1 - cs2 cs1 f e d c b a9876543210 - ------ clamp, polarity & offset control column14 - - - - - tst hs9 hs8 hs7 f e d c b a9876543210 - ------ half tone control column15 ? - ? ; don?t care bit
s1d2502a01 video amp merged osd processor for monitors 22 preliminary table 11. register description registers bits description character & attribute registers (row 00 ? 14, column 00 ? 29) c8 ? c0 (bit 8 ? 0) character code address this is the address of 448 rom fonts. blink/fint (bit 9) character blinking/font intensity if row attribute register's inte bit is set to '1', this bit carries out the font intensity feature, and if not, the character blinking feature instead. in other words, to carry out character blinking, set the inte bit to '0'. select frame control register-0's blit bit as blinking time, and select bli1, bli0 bit as blinking duty. when giving intensity in units of font, refer to the table below. b, g, r (bit c ? a) character color the character color is chosen from 16 colors using these 3 bits and the row attribute register's cint bit. box1, box0 (bit e, d) character box drawing you can make 4 box drawing modes using these 2 bits in combination. the box drawings possible with font 'a' are shown below. refer to row attribute register's 'boxe' bit. binv (bit f) box inversion the white box turns black and black box turns white in the box drawing using box1, box0. blink/fint inte rint cint function 00--normal 01--normal 10--blink 1 1 0 1 character intensity 1 1 1 0 raster intensity 1 1 1 1 character & raster intensity box0 box1 a a a a a a a a a a a a o1 0 1 box off
video amp merged osd processor for monitors s1d2502a01 23 preliminary row attribute registers (row00?14, column30) vz1, vz0 (bit 1, 0) vertical character size control as shown above, the vertical character size is decided by using these two bits in combination. hz1, hz0 (bit 3, 2) horizontal character size control as shown above, the horizontal character size is decided by using these two bits in combination. however, unlike vz, the surrounding area (row) is taken over in the amount of the hz increase, so you must keep that in mind when changing font size. refer to character size. cint (bit 4) character color intensity when this bit is set to '1', the color intensity of the character on the same row becomes high. refer to blink/fint, inte, rint, and cint's combination chart in the previous page. (even if you change this bit, you can't check the intensity feature on the demo board. this is because the osd ic's output int is applied as the video pre amp's input, and the demo board doesn't apply the osd ic's int output to the pre amp.) rint (bit 5) raster color intensity when this bit is set to '1', the color intensity of the raster on the same row becomes high. refer to blink/fint, inte, rint, and cint's combination chart in the previous page. (like cint given above, you can't check rint's feature on the demo board.) table 11. register description (continued) registers bits description vz1 vz0 vertical character size 0 0 1x (1 time) 0 1 2x (2 times) 1 0 3x (3 times) 1 1 4x (4 times) hz1 hz0 horizontal character size 0 0 1x (1 time) 0 1 2x (2 times) 1 0 3x (3 times) 1 1 4x (4 times)
s1d2502a01 video amp merged osd processor for monitors 24 preliminary row attribute registers (row00 ? 14, column30) rb, rg, rr (bit 8 ? 6) raster color is determined by these bits the raster color is chosen from out of 16 colors using these 3 bits and the row attribute register's 'rint' bit. if 'boxe' bit is not '1', the setting of these three bits have no meaning. refer to 'boxe' bit shown below. sha character shadowing character shadowing feature is carried out if you set this bit to '1'. bord character bordering character bordering feature is carried out if you set this bit to '1'. boxe (bit b) box enable if you set this bit to '1', it uses the character & attribute register's 'binv', 'box1', and 'box0' bits to carry out box drawing, and if you set it to '0', the character & attribute register's bits f~d (binv, box1, box0) act as each raster color's b, g, and r. this has higher priority than selection by setting rb, rg, and rr bits. in other words, if the boxe bit is set to '0', the character & attribute register's binv, box1, and box0 each do the function of rb, rg, and rr to decide the raster color, and the original row attribute register's rb, rg, and rr don't do anything. cbli (bit c) color blink enable if this bit is '1', the color blinking effect is applied. color blinking is instead of normal blinking, 8 colors appear in order in the font's character part. its time and duty is controlled by 'blit', 'bli1', and 'bli0', like in character blinking. inte (bit d) intensity enable refer to the table on the combination of blink/fint, inte, rint, and cint bits in the explanation of the character & attribute register's blink/ fint bit. bren (bit e) back raster enable if the bren bit is '1' and the raster color is black, the raster is transparent. that is, the video back raster is shown. if not, the osd raster covers the video's back raster. refer to other color effect. bit f reserved table 11. register description (continued) registers bits description
video amp merged osd processor for monitors s1d2502a01 25 preliminary frame control registers ? 0 (row 15, column 00) blit (bit 0) blink time control if this bit is '1', blink time is 0.5sec, and if not, 1sec. bli1, bli0 (bit 2 ? 1) blinking duty control as the font blinks, there is a time when it is visible and invisible on screen. blinking duty is the ratio of the invisible time to the visible time, and is decided by the combination of these two bits. in other words, blinking duty is the length of time the font is shown on screen. scrt (bit 3) scroll time control if this bit is '1', scroll time is 0.5sec, and if not, 1sec. scrl (bit 4) scroll enable scrolling effect is controlled by this bit. if this bit is ?1?, scrolling effect is enabled. you must remember that scrolling can be turned on/off only when osd is enabled/disabled. en (bit 5) osd enable osd is enabled when this bit is '1'. in other words, if this bit isn't '1'osd is not output inspite of writing control data. we recommend that you enable the osd after setting the control registers (such as the character & attribute register) because of video and osd output timing. erase (bit 6) ram erasing if this bit is '1', the ram data (character & attribute registers and row attribute registers) is erased. the time spent in carrying out this operation is called erasing time, which can be calculated as follows. therefore, the maximum erasing time value is: table 11. register description (continued) registers bits description bli1 bli0 blinking duty 00 blink off 0 1 duty 25% 1 0 duty 50% 1 1 duty 75% erasing time = ram clock 480 (ram cell no.) ram clock = 12 dot clock dot clock = 1/(dot frequency) dot frequency = horizontal frequency resolution (mode) (erasing time) max = (12 480) / (15k 320) = 1.2ms
s1d2502a01 video amp merged osd processor for monitors 26 preliminary the purpose of bits 'hpol', and 'vpol' is to provide flexibility when using the s1d2502a01 ic. no matter which polarity you choose for the input signal, the ic will handle them identically, so you can select active high or active low according to your convenience. frame control registers ? 0 (row 15, column 00) hpol (bit b) polarity of horizontal fly back signal if this bit is '1', hflb's polarity is positive, and if '0', it is negative. in other words, this bit is set to '1' if active high, and '0' if active low. vpol (bit c) polarity of vertical fly back signal if this bit is '1', vflb's polarity is positive, and if '0', it is negative. in other words, this bit is set to '1' if active high, and '0' if active low. fdet (bit d) fade-in and fade-out time control if this bit is '1', fade-in/fade-out time is 0.5sec. if not, it is 1sec. fde (bit e) fade-in and fade-out enable this feature is enabled when this bit is '1'. the effect where the display goes from the center to the outside, or from the outside to the center in units of font, is called fade-in/fade-out. refer to fade-in/fade-out. you must remember that fade-in/fade-out, like scrolling on/off, only occurs when osd enabled/disabled. bit f reserved. table 11. register description (continued) registers bits description
video amp merged osd processor for monitors s1d2502a01 27 preliminary tabel 4. register description (continued) registers bits description frame control registers ? 1 (row 15, column 01) ch5 ? ch0 (bit 5 ? 0) character height control while the purpose of vz[1:0] (vertical character height) is to control the absolute size of the character, the purpose of ch[5:0] (character height) is to output osd of a uniform size even if the resolution changes. if you adjust the value in the range of ch = 18 ? ch = 63, each line's repeating number is decided (standard height ch = 18 is the reference value), by which the line is repeated. for more information on repeating number selection, refer to character height. fblk (bit 6) selection of the fblk output pin's configuration unlike pin description's fblk, if this bit is '0', the fblk pin output is high while the character and raster are being displayed and the character and raster are output as they are. if this bit is '1', the fblk pin output becomes high only when character is being displayed, so only the character is output. refer to 'figure 11. character/raster signal part. dot1, dot0 (bit 9, 8) resolution control (dots/line) as shown above, the number of dots per horizontal line is decided by a combination of these two bits. hf2?hf0 (bit c ? a) horizontal frequency pll's horizontal frequency is decided by the combination of these 3 bits. this is related to the selection of dot[1:0], so you can't numerically express the frequency range with only the hf[2:0] selection. for more information, please refer to hf bits selection. fpll (bit d) full range pll if this bit is '1', the osd_pll block's vco operates at full range (4.8mhz - 96mhz). if it is ?0', it operates within the region decided by the hf bit [c:a] explained above. if you can?t optimize osd screen decided by the hf bit in the high region, you may set the fpll bit to ?1?. dot1 dot0 no. of dots 0 0 320 dots/line 0 1 480 dots/line 1 0 640 dots/line 1 1 800 dots/line
s1d2502a01 video amp merged osd processor for monitors 28 preliminary fblk bit setting is explained at the figure below. frame control registers ? 1 (row 15, column 01) cp1, cp0 charge pump output current control this is the pll block's internal phase detector output status, converted into current. refer to pll control. the output is decided by the combination of these two bits. figure 11. character/raster signal part tabel 4. register description (continued) registers bits description cp1 cp0 charge pump current 0 0 0.50 ma 0 1 0.75 ma 1 0 1.00 ma 1 1 1.25 ma raster blue red character bordering character raster blue red green
video amp merged osd processor for monitors s1d2502a01 29 preliminary tabel 4. register description (continued) registers bits description frame control registers ? 2 (row 15, column 02) vp7 ? vp0 vertical start position control ( = vp[7:0] 4) signifies top margin height from the v-sync reference edge. hp7 ? hp0 horizontal start position control ( = hp[7:0] 6) signifies delay of the horizontal display from the h-sync reference edge to the character's 1st pixel location. v-amp control registers ? 0 (row 15, column 03) vc7 ? vc0 (bit7 ? 0) the contrast adjustment is made by contrdling simultaneously the gain of three internal variable gain amplifiers. the contrast adjustment allows to cover a typical range of 38db. v-amp control registers ? 1 (row 15, column 04) brt7 ? brt0 (bit7 ? 0) the brightness adjustment controls to add the same black level (pedestal) to the 3-channel r/g/b signals after contrast amplifier. v-amp control registers ? 2 (row 15, column 05) rsb7 ? rsb0 (bit7 ? 0) r channel sub contrast control. the sub contrast adjustment is used to adjust the white balance, and the gain of each channel is controlled. the sub contrast adjustment allows you to cover a typical tange of 12db. v-amp control registers - 3 (row 15, column 06) gsb7 ? gsb0 (bit7 ? 0) g channel sub contrast control. the sub contrast adjustment is used to adjust the white balance, and the gain of each channel is controlled. the sub contrast adjustment allows you to cover a typical tange of 12db. v-amp control registers - 4 (row 15, column 07) bsb7 ? bsb0 (bit7 ? 0) b channel sub contrast control. the sub contrast adjustment is used to adjust the white balance, and the gain of each channel is controlled. the sub contrast adjustment allows you to cover a typical tange of 12db. v-amp control registers - 5 (row 15, column 08) osd7 ? osd0 (bit7 ? 0) the osd contrast adjustment is made by contrdling simultaneously the gain of three internal variable gain amplifiers. the osd contrast adjustment allows to cover a typical range of 38db. v-amp control registers - 6 (row 15, column 09) rwb7 ? rwb0 (bit7 ? 0) r channel cut-off control. the cut-off adjustment is used to adjust the raster white balance. v-amp control registers - 7 (row 15, column 10) gwb7 ? gwb0 (bit7 ? 0) g channel cut-off control. the cut-off adjustment is used to adjust the raster white balance.
s1d2502a01 video amp merged osd processor for monitors 30 preliminary v-amp control registers - 8 (row 15, column 11) bwb7 ? bwb0 (bit7 ? 0) b channel cut-off control. the cut-off adjustment b used to adjust the raster white balance. v-amp control registers - 9 (row 15, column 12) cut7 ? cut0 (bit7 ? 0) the cut-off brightness adjustment is made by simultaneously controlling the external cut-off current. v-amp control registers - 10 (row 15, column 13) ht (bit 0) video & osd half tone enable. if you set this bit to ?1?, the half tone function is on. then you can see the video signal & osd raster. hs3 ? hs1 (bit3 ? 1) hs3 ? hs1 bits select osd raster color 1 to be half tone. to carry out half tone function, set the ht bit to ?1?. hs6 ? hs4 (bit6 ? 4) hs6 ? hs4 bits select osd raster color 2 to be half tone. to carry out half tone function, set the ht bit to ?1?. sb (bit 7) soft blanking enable if you set this bit ?1?, the r/g/b outputs go to gnd. tabel 4. register description (continued) registers bits description hs3 hs2 hs1 osd raster color 1 por grb 000000 blacko 001001 blue 010010 red 011011magenta 100100green 101101 cyan 110110yellow 111111white hs6 hs5 hs4 osd raster color 2 por grb 000000 blacko 001001 blue 010010 red 011011magenta 100100green 101101 cyan 110110yellow 111111white
video amp merged osd processor for monitors s1d2502a01 31 preliminary v-amp control registers - 11 (row 15, column 14) cs2 ? cs1 (bit1 ? bit0) cut-off offset current control bpw2 ? bpw1 (bit4 ? bit3) generated clamp pulse width control to carry out this function, set the clps bit to " 0 " blkp (bit 5) polarity of horizontral fly back signal if this bit is ?0?, hflb?s polarity is negative, and if ?1?, it is positive. clpp (bit 6) polarity of clamp pulse signal if this bit is ?0?, clp?s polarity is positive, and if ?1?, it is negative. this bit has meaning only if the clps bit is set to ?1?. clps (bit 7) clamp pulse generation enable if this bit is ?0?, clamp signal is made using the hflb signal, so there is no need to supply the clamp signal. and if ?1? you must supply external clamp signal. v-amp control registers - 12 (row 15, column 15) hs9 ? hs7 (bit2 ? bit 0) hs9 ? hs7 bits select osd raster color 3 to be half tone. to carry out half tone function, set the ht bit to " 1 ". tabel 4. register description (continued) registers bits description cs2 cs1 cut-off offset current por 00 0 o 01 50 a 10 100 a 11 150 a bpw2 bpw1 width por 000.33 s 010.66 s 101.00 so 111.33 s hs9 hs8 hs7 osd raster color 3 por grb 000000 blacko 001001 blue 010010 red 011011magenta 100100green 101101 cyan 110110yellow 111111white
s1d2502a01 video amp merged osd processor for monitors 32 preliminary video amp part address map register sub address (use limited to 1byte out of 2bytes) in normal status, you must set tst bit to ?0?. table 12. video amp part address map sub address [hex] function por value [hex] d7 d6 d5 d4 d3 d2 d1 d0 0f03 contrast control 80h 0f04 brightness control 80h 0f05 sub contrast control (r) 80h 0f06 sub contrast control (g) 80h 0f07 sub contrast control (b) 80h 0f08 osd contrast control 80h 0f09 cut-off control (r) 80h 0f0a cut-off control (g) 80h 0f0b cut-off control (b) 80h 0f0c cut-off brightness control 80h 0f0d sb hs6 hs5 hs4 hs3 hs2 hs1 ht 00h 0f0e clps clpp blkp bpw2 bpw1 - cs2 cs1 10h 0f0f - - - - tst hs9 hs8 hs7 00h
video amp merged osd processor for monitors s1d2502a01 33 preliminary contrast register (sub adrs: 03h) (vin = 0.7vpp, bright: 80h, subcont: ffh) brightness register (3-ch) (sub adrs: 04h) (cont: 80h, subcont: 80h) sub contrast register (r/g/b-ch) (sub adrs: 05/06/07h) (vin = 0.7vpp, bright: 40h, cont: ffh) osd contrast register (sub adrs: 08h) (vosd = ttl, bright: 80h, subcont: 80h) hex b7 b6 b5 b4 b3 b2 b1 b0 contrast (vpp) gain (db) int. value (hex) 0000000000 0 - 8010000000 2.85 - o ff11111111 5.2 - increment/bit 0.0223 hexb7b6b5b4b3b2b1b0 brightness (vpp) int. value (hex) 0000000000 0.2 8010000000 1.5 o ff11111111 2.7 increment/bit 0.01055 hexb7b6b5b4b3b2b1b0 sub contrast (vpp) gain (db) int. value (hex) 0000000000 - 8010000000 - o ff11111111 - increment/bit hexb7b6b5b4b3b2b1b0 osd contrast (vpp) gain (db) int. value (hex) 0000000000 0 - 8010000000 3.2 - o ff11111111 6.4 - increment/bit 0.025
s1d2502a01 video amp merged osd processor for monitors 34 preliminary cut-off brightness register (3-ch) (sub adrs: 0ch) cut-off register (r/g/b-ch) (sub adrs: 09/0a/0bh) (cont = 80h, subcont: 80h) hexb7b6b5b4b3b2b1b0 cut-off brightness ( a) int. value (hex) 0000000000 0 8010000000 100 o ff11111111 200 increment/bit 0.781 hexb7b6b5b4b3b2b1b0 cut-off ext ( a) int. value (hex) 0000000000 0 8010000000 300 o ff11111111 600 increment/bit 2.344
video amp merged osd processor for monitors s1d2502a01 35 preliminary addressing display ram structure whereas ?figure 9. memory map of display registers? showed a logical configuration, the figure above shows a 1kbyte sram (512 16 bit)'s practical and physical configuration. for facilitating internal calculations, addressing is done using exponents of 2, and the rows to the right of the 'row attribute registers', excepting only iff(255), are 'virtual registers' that are not used. if you set 'frame control register 0's 'erase' bit to '1', 480 areas are erased (excepting only the 16th line) in the figure above, and the 'erasing time' is measured with 480 areas as the standard. figure 12. display ram structure & monitor display position 0 32 64 96 448 480 481 482 483 484 511 477 478 479 125 126 127 93 94 95 61 62 63 29 30 31 row attribute register virtual register display ram address area frame/v-amp control registers row 0 1 2 3 . . . . 14 15 . . . . . . . . . . . . . . . . ....... ....... 496 495 ...
s1d2502a01 video amp merged osd processor for monitors 36 preliminary rom fonts s1d2502a01 provides 448 rom fonts for displaying osd icons, which allows the use of multi-language osd icons. font $000 is reserved for blank data. figure 13. composition of the rom fonts $000 $001 $010 $011 01 00 01 $00e $00f $01e $01f ef $1ae $1af $1be $1bf $1a0 $1a1 $1b0 $1b1 1a 1b 1c $1c0 $1c1 $1ce $1cf standard fonts multi color
video amp merged osd processor for monitors s1d2502a01 37 preliminary coloring if you have an intensity feature, the number of possible colors you can express becomes doubled. in other words, the number of colors you can represent with three colors blue, green, and red is 8 ( = 2 3 ), but with the intensity feature, it is 16 ( = 2 4 ). character color character color is assinged for each font, and the 4 components for expressing a color are listed below. raster color according to the 'boxe' bit setting, raster color can be assigned in units of font or row. there is a trade-off in either case. if 'boxe' bit is set to '1', the box drawing feature can be carried out in units of font, but the raster color can only be assigned in units of row. on the other hand, if 'boxe' bit is set to '0', the box drawing feature can't be carried out, but you can assign raster color in units of font. blue character & attribute register's b bit[c] green character & attribute register's g bit[b] red character & attribute register's r bit[a] intensity character & attribute register's blink/fint bit[9] row attribute register's inte bit[d] row attribute register's cint bit[4] if all 3 bits are set to '1', the character intensity feature is enabled. blue row attribute register's rb bit[8] if the row attribute register's 'boxe' bit is '1', and character & attribute register's 'binv' bit[f] if boxe' bit is '0'. green row attribute register's rg bit[7] if row attribute register's 'boxe' bit is '1', and character & attribute register's 'box1' bit[e] if 'boxe' bit is '0'. red row attribute register's rr bit[6] if row attribute register's 'boxe' bit is '1', and character & attribute register's 'box0' bit[d] if 'boxe' bit is '0'. intensity character & attribute register's blink/fint bit[9] row attribute register's inte bit[d] row attribute register's rint bit[5] if all 3 bits are set to '1', the raster intensity feature is enabled. notes for when making s1d2502a01 fonts address 000h is appointed as blank data. ram's initial values are all 0, and all bits are written as 0 when you erase the ram, so blank data means the initial value. in other words, blank data means 'do nothing'. you don't need to write any data for the space font, except for 000h. it just needs to be an undotted area.
s1d2502a01 video amp merged osd processor for monitors 38 preliminary other color effet the row attribute register's 'bren' bit's function is shown in the figure below. if you set the 'bren' bit of the row with the letter a as '0' after selecting a and b's raster color as black, the raster color black will be displayed. but if you set the 'bren' bit of the row with the letter b as '1', the raster color black becomes invisible, so the back raster color (gray) is displayed as if it is the raster color. color blinking is using a selective control bit in blink mode to replace normal blinking with 8 different colors appearing in order on the font's character. color blinking only replaces normal blinking, and blink time and blink duty are still applied at the same time. therefore, if the blink duty is not set to off, only 3 ~ 4 colors may appear according to the blink duty, instead of all 8. sizing/positioning character size row attribute register's hz bit[3:2] and vz bit[1:0] control the character's vertical and horizontal size by factors of 1/2/3/4 in units of row. vz is correctly expressed without regard to size since the next line is just pushed down in order, but hz decides the column that the font occupies according to the size. for example, if hz [1:0] = 0, 1, the font doubles in the horizontal direction, and one font takes up 2 columns. therefore, the column address must move in the same amount as the hz for the next font to be expressed correctly. in other words, if the horizontal size is doubled and takes up 2 columns, the next font must be put 2 columns back. figure 14. color effect by bren bit figure 15. character size by vz, hz bits bren bit = 0 & rastor color = black bren bit = 1 & rastor color = black bren bit = 1 & rastor color = light blue gray original vz 2 hz 2
video amp merged osd processor for monitors s1d2502a01 39 preliminary character height whereas the purpose of vz[1:0] (vertical character height) is to adjust the character's absolute size, the purpose of ch[5:0] (character height) is to output a uniformly sized osd even if the resolution changes. to express a character height of ch = 18 ~ ch = 63 after receiving ch[5:0]'s input from the frame control register-1, decide on each line's repeating number (standard height ch = 18) and repeat the lines. the following figure shows two examples of a height-controlled character. height control is carried out by repeating some of the lines. figure 16. character height standard font(12*18) standard font(12*18) standard font in high vertical resolution height-controlled font : added line standard font in more higher vertical resolution height-controlled font : added line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
s1d2502a01 video amp merged osd processor for monitors 40 preliminary repeating line-number can be found by the following formula. [# of the repeating lines = 2 + n m], where n = 1, 2, 3, ... and m = round{14 (ch[5:0]-18)}. 1. if ch[5:0] is greater than 32 and less than or equal to 46 (32 < ch[5:0] 46), all lines are repeated once or twice. the lines that are repeated twice are chosen by the following formula. [# of the repeating lines = 2 + n m], where n = 1, 2, 3, ... and m = round {14 (ch[5:0]-32)}. 2. if ch[5:0] is greater than 46 and less than or equal to 60 (46 < ch[5:0] 60), all lines are repeated two or three times. the lines that are repeated three times are chosen by the following formula. [# of the repeating lines = 2 + n m], where n = 1, 2, 3, ... and m = round {14 (ch[5:0]-46)}. 3. if ch[5:0] is greater than 60 and less than or equal to 64 (60 < ch[5:0] 64), all lines are repeated three or four times. the lines that are repeated four times are chosen by the following formula. [# of the repeating lines = 2 + n x m], where n = 1, 2, 3, ... and m = round {14 (ch[5:0]-60)}. ch's reference value is 18, and even if you input 0, it operates in the same way as when ch = 18. the repeating line-number is limited to 16. if the m value is less than or equal to 1, all lines of the standard font are repeated more than once. table 13. repeating line as controlling by ch bits character height repeating line ch = 18 - ch = 19 9 ch = 20, 21 6, 13 ch = 22 5, 11, 17 ch = 23 4, 9, 14, 19 ch = 24 3, 7, 11, 15, 19, 21 ch = 25, 26, 27 3, 7, 11, 13, 15, 19, 22 ch = 28 3, 6, 9, 12, 14, 18, 20, 23, 25 ch = 29 3, 6, 9, 11, 13, 15, 18, 21, 23, 25, 26 ch = 30 3, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 27 ch = 31 2, 5, 7, 9, 11, 13, 15, 17, 21, 23, 25, 27, 28 ch = 32, 33, 34, 35 2, 5, 7, 9, 11, 13, 15, 18, 21, 23, 25, 27, 28, 29 ch = 36 - ch = 37 18
video amp merged osd processor for monitors s1d2502a01 41 preliminary ch = 38, 39 12, 25 ch = 40 10, 20, 30 ch = 41 8, 16, 24, 32 ch = 42 6, 12, 18, 24, 30, 36 ch = 43, 44, 45 6, 12, 18, 24, 30, 36, 41 ch = 46 4, 8, 12, 17, 21, 25, 29, 33, 37, 41 ch = 47 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44 ch = 48 4, 8, 12, 16, 20, 23, 26, 29, 33, 37, 41, 45 ch = 49 4, 8, 12, 16, 19, 22, 25, 28, 31, 35, 39, 43, 47 ch = 50, 51, 52, 53 4, 8, 12, 15, 18, 21, 24, 27, 30, 33, 36, 40, 44, 48 ch = 54 - ch = 55 27 ch = 56, 57 18, 36 ch = 58 14, 28, 42 ch = 59 12, 23, 34, 45 ch = 60 9, 18, 26, 34, 43, 52 ch = 61, 62, 63 8, 16, 23, 30, 37, 44, 51 table 13. repeating line as controlling by ch bits character height repeating line (continued)
s1d2502a01 video amp merged osd processor for monitors 42 preliminary positioning the frame control register-2's hp bit [f:8] signifies delay of the horizontal display from the h-sync reference edge to the character's 1st pixel location, and is controlled by multiplying hp [f:8]'s range value by 6. also, vp bit[7:0] signifies the top margin height from the v-sync reference edge, and is controlled by multiplying 4 to the vp [7:0]'s range value. refer to the figure shown below. figure 17. frame composition with the osd characters 15 rows (=15 x 18 lines) hp[7:0] vp[7:0] (hflb) (vflb) background screen 30 columns (= 30 x 12 dots) osd characters
video amp merged osd processor for monitors s1d2502a01 43 preliminary visual effects box drawing set the row attribute register's boxe bit to '1' and enable the box feature. then set the character & attribute register's box bit to select one of 4 modes. or, use the character & attribute register's binv bit to inverse the white and black areas of the box mode selected by the box bit. the principle behind the boxing feature is shown below. out of the 12 horizontal dots and 18 vertical lines that make 1 character, make the first and 12th horizontal dots to hdot0/hdot11, and the first and 18th vertical lines to dotline-0h/dotline-17h in order to carry out box drawing for 1 dot outside the character. figure 18. box drawing box0 box1 a a a a a a a a a a a a o1 0 1 box off dotline_ 17 h dotline_ 0 h dotline_ 17 h dotline_ 0 h hdot11 dotline_ 17 h dotline_ 0 h hdot0 box<1:0> 01 box<1:0> 10 box<1:0> 11
s1d2502a01 video amp merged osd processor for monitors 44 preliminary bordering/shadowing the character border and shadow can only be black. character border is the effect where you make 1 pixel around the character, and character shadow is making 1 pixel to the right and below the character. scrolling scrolling is slowly displaying or erasing a character from the top line to the bottom. this effect makes it look as if 1 character line is scrolling up or down. figure 19. character bordering/shdowing figure 20. scrolling bordering shadowing
video amp merged osd processor for monitors s1d2502a01 45 preliminary fade-in/fade-out fade-in/fade-out is displaying from the center to the outside in units of font when osd display is on/off. each font's display is turned on/of without regard to size, in units of (12 18) dot. also, to control the fade in/out time, the v_pulse's 1/4, 1/8 clocks are used for counting. in other words, as control data, it takes 0.5sec if the frame control register - 0's 'fdet' bit is 1, and 1sec if 0. if it is difficult to visualize the fade-in / fade-out feature with the explanation and diagrams in this document, write the control data to the osd ic and verify the ic's operations. like the scrolling feature, fade in/out can only be verified when osd is enabled/disabled. figure 21. fade-in/fade-out fade in/out unit: font 6ck_time 6ck_time + 3ck_time display at 9ck_time row space
s1d2502a01 video amp merged osd processor for monitors 46 preliminary pll control introduction pll (phase lock loop) is feedback controlled circuit that maintains a constant phase difference between a reference signal and an oscillator output signal. generally, pll is composed as follow figure. - pfd (phase frequency detector) pfd compares the phase of the vco output frequency, with the phase of a reference signal frequency output pulse is generated in proportion to that phase difference. - lf (loop filter) lf smooths the output pulse of the phase detector and the resulting dc component is the vco input. - vco (voltage controlled oscillator) vco is controlled by loop filter output. the output of the vco is fed back to the phase frequency detector input for comparison which in turn controls the vco oscillating frequency to minimize the phase difference. - fd (frequency divider) fd divides too much different frequency that is oscillated from the vco to compare it with reference signal frequency. figure 22. block diagram of general pll pfd (phase frequency detector) lf (loop filter) vco (voltage controlled oscillator) fd (frequency detector) reference signal
video amp merged osd processor for monitors s1d2502a01 47 preliminary pll of the s1d2502a01 pll is composed of the phase detector, charge pump, vco, and n-divider as 4 sub-blocks. the following is the description of the input/output signals. - hflb (input) horizontal flyback signal is refrence signal of the pll built in s1d2502a01. the hflb signal's frequency range is 15 ~ 90khz, so the pll block must be a wide range pll that can cover hflb's entire frequency range. - vco (input) error signal that passes through an external loop filter is input into vco. operation voltage range is 1-4v. you can raise immunity towards external noise by lowering vco sensitivity. you can do this by making it have the maximum operation voltage range possible in the 5v power voltage. figure 23. block diagram of the pll built in s1d2502a01 phase detector charge pump vco n-divider loop filter vco_in (pin3) div_out hflb (pin32) cp_out (pin4) vco_out cp0 cp1 dot0 dot1 hf0 hf1 hf2 # composed of external components fhflb < 0.4v > 4.2v ~2us
s1d2502a01 video amp merged osd processor for monitors 48 preliminary - dot0, 1 (input) mode control signal that controls the number of dots per line in the frame control register. there are 4 modes: 320, 480, 640, and 800 dots/line. according to your choice of mode, the osd_pll block's n-divider is controlled by one of 320, 480, 640, or 800 divider. - hf0, 1, 2 (input) the horizontal sync frequency information is received from the micro controller through the frame control registers-1's bit c-a. - cp0, 1 (input) charge pump's output sourcing (or sinking) current control pin. this control data is received through frame control registers-1's bits e-d. - vco_out (output) vco output that becomes a system clock. it is the osd r, g, b output signal's dot frequency, and the standard signal for osd's various timings. also, it is input into the n-divider and makes a pll loop - cp_out (output) charge pump circuit's output. input into external loop filter. it becomes one of 3 states according to the standard signal input into the phase detector (hflb) and the divider output (div_out). - hflb div_out is lead: current sink - hflb lag: current source - hflb in-phase: high impedence fclk < 0.4v > 4.2v rise time : < 4ns fall time : < 4ns
video amp merged osd processor for monitors s1d2502a01 49 preliminary tunning factors of the s1d2502a01 pll pll external circuit you may follow the recommendations for pcb art work and input/output signal characteristic improvement in recommendation. the external circuit that has the most influence on s1d2502a01 pll block operation is pin 3 (vco_in) and pin 4 (cp_out)'s surrounding circuit. refer to osd pll block. because the pll circuit is basically a feedback circuit, there are many components that influence the characteristics. c1, r1, r2, and r3 do not have a localized effect. as you can see, they are connected to the pll control bits and influence the characteristics through their complicated relationships. the main functions of the time canstant and their reference values are as follows. figure 24. pll external circuit table 14. main function of time constant in pll external circuit time canstant recommended value main function c1 562 (or 103, 223) influences the damping ratio and controls the pll response time r1 5.6k ? (7.5k ? ) same as c1 r2 27k ? (or 33k ? ) charge pump current adjustment r3 (option) 30m ? (or 20m ? ) extend frequency range 3 4 r1 r2 c1 r3 (option)
s1d2502a01 video amp merged osd processor for monitors 50 preliminary pll control bit after configuring an external circuit using the recommended values, carry out programming using the recommended values for frequency range and control bits given in the table below. (ref: 800 600, c1: 562, r1: 5.6k, r2: 27k, r3: 30m) locking range as you can see the figure below, it is 2.35v that measured voltage at pin-3 to optimize osd quality. the proper voltage range is 1.5 ~ 3.25v. table 15. recommend values of pll control bit register set pll control bit freq. range cp1 cp0 fpll hf2 hf1 hf0 dot1 dot0 hex below 40khz 000010110b 40 - 50khz 1001001193 50 - 70khz 1001011197 above 70khz 100111119f figure 25. locking range 1.625v fmax f0 -2 1.625v 2 fl fc locking range ve (min) ve (max) 0.75v 1. 5v 2.37v 3. 25v 4v
video amp merged osd processor for monitors s1d2502a01 51 preliminary hf bits selection hf bits is not selecting from out of 8 (2 3 ) steps uniformly, but selecting the step shown in figure below. in example, at 800 mode, there are 5 steps that the frequency range is controlled by hf bits. after fixing time constants of the external circuit and pll control bits except hf bits, if hf bits are stepped up, the voltage measured at pin-3 drops. on the contrary, if hf bits are stepped down, the voltage rises. the voltage measured at pin-3 don't change by changing cp bits. external register at pin-4 the external register at pin-4 is the factor that changes greatly at pll tunning. the initial value of this external register value is decided as follows. at first, the external register is replaced variable-register (about 50k ? range). and then, set the lowest pll control bits at the lowest frequency allowed by set. and then, change variable-register to be 2.35v that optimum voltage is locking. and then, measure register value at this time. also, set the highest pll control bits at the highest frequency allowed by set. and then, change variable-register to be 2.35v that optimum voltage is locking. and then, measure register value at this time. you may decide the average of these two registers' value to initial value. table 16. hf bits selection div dot1 dot0 hf2 hf1 hf0 320 0 0 480 0 1 640 1 0 800 1 1
s1d2502a01 video amp merged osd processor for monitors 52 preliminary the table below shows that other factors change as changing external register's value. fixing factor variable factor change voltage current lock range time constants of the external circuit and pll control bits except rext (shift) (shift)
video amp merged osd processor for monitors s1d2502a01 53 preliminary recommendation 5v power routing s1d2502a01's osd part power is composed of analog vdd and digital vdd. to eliminate clock noise influence in the digital block, you need to separate the analog vdda and digital vdd. (bd102 use: refer to application circuit ) 12v power routing because s1d2502a01 is a wideband amp of above 150mhz, 12v power significantly affects the video characteristics. the effects from the inductance and capacitance are different for each board, and , therefore, some tuning is required to obtain the optimum performance. the output power, vcc2, must be separated from vcc1 and vcc3 using a coil, which is parallel-connected to the damping resistor.the appropriate coil value is between 20uh - 200uh. parallel-connected a variable resistor to the coil and control its resistance to obtain the optimum video waveform. (moreover, bd103 can tune using a coil and variable resistor to obtain the optimum video waveform. l103, r124, bd103: refer to application circuit) vcc1, vcc3 12v power use a 104 capacitor and large capacitor greater than 470uh for the power filter capacitor. 12v output stage power vcc2 do not use the power filter capacitor. 5v digital power vdd don't use a coil or magnetic core to the vdd input. make the power filter capacitor, an electric capacitor of greater than 50uf, single and connect it to vss, the digital gnd. output stage gnd2 care must be taken during routing because it ,as an amp output stage gnd, is an important factor of video oscillation. r/g/b clamp cap and r/g/b load resistor must be placed as close as possible to the gnd2 pin. gnd2 must be arranged so that it has the minimum gnd loop, which at one point must be connected to the main gnd. digital gnd vss when this is to be connected directly to the gnd2, it can cause the osd clock noise, so the loop connection should be routed as far away as possible. if the osd clock noise affects the screen, separate vss gnd from all gnd and connect it to the main board using a bead. again, the bead connection point should be placed as far away as possible to the gnd2. analog block the pll built in to s1d2502a01 is sensitive to noise due to the wide range pll characteristics. therefore, you need to isolate the analog block in the following manner. first make a separate land for the analog block (pin2 - pin6)'s ground, and connect it to the main ground through a 1m ? resistor. the analog gnd of both sides of a double faced pcb must be separated from the main ground. (separate pin 2's 5v analog gnd, which is the gnd for osd pll, from the main and digital gnds and connect it to the main gnd using about 1m ? resistor. gnd for pins 2 - 6 is the no. 2 vssa gnd.)
s1d2502a01 video amp merged osd processor for monitors 54 preliminary i 2 c control line (scl, sda line) i 2 c communication noise (noise generated in the osd display pattern when data is transmitted in the i 2 c line) may be generated because of an i 2 c control line that passes near the analog block. the i 2 c control lines near s1d2502a01 must be separated from the analog block as much as possible. furthermore, the i 2 c bus interference can be prevented by inserting a series resistor in the line. horizontal flyback signal display jittering can be generated if the horizontal signal (hflb) input to s1d2502a01 is not a clean signal. we recommend a short path and shielded cable for obtaining a clean signal. generally, the input horizontal signal (hflb) is generated by using a high voltage horizontal flyback signal. the effect from the high voltage flyback signal can be reduced by separating the r115 and r117 gnd, which determines the flyback signal slice level, from the transistor gnd, which generates the actual s1d2502a01 input horizontal signal. furthermore, the flyback signal sharpness must be maintained by minimizing the values of r115, r116 and r117 resistors, which set the horizontal signal slice level. values. (r115, r116, r117: refer to application circuit ) hflb input signal generator you can correct the circuit by reducing the resistors that sets the slice level of the horizontal signal in the hflb- generating circuit.
video amp merged osd processor for monitors s1d2502a01 55 preliminary application board circuit figure 26. application board circuit 70v 12v 70v vdd 5v 6.3v 5v 12_1v 12v 5v 12v 12v c119 102 c117 1nf rb13 82k dg04 1ss244 dr03 1ss244 db05 1n4148 dr05 1n4148 c109 103 c152 104 c124 103 rr03 470 rg15 47 db02 1n4148 r117 150 dr02 1n4148 cb02 104 cr05 104 q102 2n3904 2 1 3 qr01 2n5551c-y 2 1 3 cb04 1uf + r119 560 cb02 104 cg02 104 rb15 47 c103 470u f + r115 2k rr12 2.2k cg02 104 dg02 1n4148 rg11 100 driver ic bin 6 rout 1 gout 2 gin 7 gnd 5 rin 9 vbb 8 bout 3 vcc 4 rr02 75 rr09 75k qb02 2n5401c-y 2 1 3 cb05 104 db03 1ss244 sk102 dms-200d skr01 dms-200d rb03 470 r101 4.7k db01 1n4148 dr04 1ss244 rr15 47 c128 104 c123 103 c112 1uf + d102 1n4148 c121 104 qg02 2n5401c-y 2 1 3 c110 100uf + r103 390 bd102 rg02 75 rg09 75k bd103 rg03 470 rb12 2.2k rg12 2.2k db04 1ss244 r107 1k cn1 1 2 3 4 5 6 rg01 75 rg13 82k rb10 39 dg03 1ss244 cb05 104 c108 47uf + c126 1.8nf c118 330pf cr05 104 qr02 2n5401c-y 2 1 3 rg10 39 cg04 1uf + r102 100 sk101 wsp-401m skg01 dms-200d cn2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 l101 100uh c116 1nf r123 1m c102 1uf + rr01 75 rr11 100 r120 30m cr01 104 rr13 82k skb01 dms-200d rb02 75 c111 4.7uf + dg05 1n4148 r118 560 r104 390 rb01 75 c107 220uf + cr02 104 cg05 104 rb11 100 qg01 2n5551c-y 2 1 3 cr04 1uf + c120 1nf r116 10k rb09 75k cg05 104 r109 27k c114 103 r114 470 c160 47uf + qb01 2n5551c-y 2 1 3 c113 562 r108 5.6k rg20 4.7k c106 104 r124 220 c151 104 kb2502 vflb 1 vssa 2 vco_in 3 vref1 4 vref 5 vdda 6 cont_cap 7 abl_in 8 gnd 9 clp_in 10 vcc3 11 rin 12 vcc1 13 gin 14 gnd1 15 bin 16 bclp 17 bout 18 gnd2 19 gclp 20 gout 21 vcc2 22 rclp 23 rout 24 bct 25 gct 26 rct 27 vss 28 scl 29 sda 30 vdd 31 hflb 32 rr20 4.7k dg01 1n4148 rb20 4.7k l103 27uh dr01 1n4148 rr04 100 cr08 270pf cb08 270pf rb04 100 rg04 100 cg08 270pf rr04 100 cr08 270pf rb08 56 cb07 37pf cg07 37pf rg08 56 rr08 56 cr07 37pf rb14 75 rg14 75 rr14 75 lb01 0.15uh lg01 0.15uh lr01 0.15uh rr10 39 g2 g1 g2 b_ou t r_ou t g_ou t
s1d2502a01 video amp merged osd processor for monitors 56 preliminary typical application circuit figure 27. typical application circuit 5v 12v vdd 5v 70v 12v 6.3v 12_1v 5v 70v 12v 12v rb15 47 c108 47uf + db03 1ss244 cn1 1 2 3 4 5 6 c109 103 c114 103 r123 1m r109 27k r107 1k r102 100 c116 1nf cr01 104 cg02 104 cb02 104 l101 100uh r118 560 r119 560 dr05 1n4148 cg05 104 dg05 1n4148 cb05 104 cb05 104 qb02 2n5401c-y 2 1 3 db05 1n4148 rg15 47 rr15 47 rb14 75 lb01 0.15uh cb04 1uf + dg03 1ss244 dr03 1ss244 rr09 75k rg09 75k rb09 75k rb10 39 rg14 75 lg01 0.15uh cg04 1uf + rg10 39 rr14 75 lr01 0.15uh cr04 1uf + rr10 39 db04 1ss244 dg04 1ss244 dr04 1ss244 c111 4.7uf + rg02 75 d102 1n4148 rr02 75 db01 1n4148 qr01 2n5551c-y 2 1 3 r116 10k bd102 qb01 2n5551c-y 2 1 3 q102 2n3904 2 1 3 cr05 104 qr02 2n5401c-y 2 1 3 rb13 82k r103 390 driver ic bin 6 rout 1 gout 2 gin 7 gnd 5 rin 9 vbb 8 bout 3 vcc 4 rb02 75 c117 1nf qg01 2n5551c-y 2 1 3 cr05 104 r101 4.7k c110 100uf + qg02 2n5401c-y 2 1 3 rg11 100 rb11 100 cn2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 cg05 104 r120 30m rr11 100 c112 1uf + c123 103 dg02 1n4148 cg02 104 rg13 82k skb01 dms-200d c128 104 cb02 104 rb03 470 skr01 dms-200d cr02 104 skg01 dms-200d dr02 1n4148 c107 220uf + c160 47uf + r114 470 c121 104 rr01 75 rr03 470 rr12 2.2k rg12 2.2k rb12 2.2k rb01 75 c124 103 c119 102 r117 150 db02 1n4148 c102 1uf + r115 2k rg03 470 c118 330pf rg01 75 rr13 82k sk101 wsp-401m c152 104 c103 470u f + bd103 c126 1.8nf sk102 dms-200d c120 1nf r104 390 c113 562 r108 5.6k dg01 1n4148 c151 104 rb20 4.7k dr01 1n4148 rr20 4.7k kb2502 vflb 1 vssa 2 vco_in 3 vref1 4 vref 5 vdda 6 cont_cap 7 abl_in 8 gnd 9 clp_in 10 vcc3 11 rin 12 vcc1 13 gin 14 gnd1 15 bin 16 bclp 17 bout 18 gnd2 19 gclp 20 gout 21 vcc2 22 rclp 23 rout 24 bct 25 gct 26 rct 27 vss 28 scl 29 sda 30 vdd 31 hflb 32 c106 104 rg20 4.7k r124 220 l103 27uh b_out g_ou t r_ou t g1 g2 g2

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