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DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 1 of 49 features ? 8 channels of 24-bit ddx ? ? 100db snr and dynamic range ? 32khz to 192khz input sample rates ? sacd/dsd input (6 channel) ? 24-bit to 36-bit internal processing ? digital gain/attenuation +58db to ?100db in 0.5db steps ? up to 10 independent 32-bit user programmable biquads (eq) per channel ? i 2 c control ? 8 channel i 2 s inputs and outputs ? 3.3v single supply operation ? individual channel, master, and channel trim gain/attenuation ? bass/treble tone control ? dual 8-input mix, pre and post eq, per channel ? dual independent programmable limiters/compressors ? automodes? * 5-band graphic eq * 32 preset eq curves * all 5.1 bass management configs * 8 preset crossover filters * auto volume controlled loudness * 5.1 to 2 channel downmix * 3 preset volume curves * 2 preset anti-clipping modes * preset nighttime listening mode * preset tv agc ? input and i 2 s output channel mapping ? am noise reduction and pwm frequency shifting modes ? soft volume and muting ? auto zero detect and invalid input detect muting ? selectable ddx ? ternary or binary pwm output + variable pwm speeds ? internal processing loop-through for up to 40 biquads / 2-channels ? qsurround5.1* * provided only under license of qsound labs, inc. ddx ? multi-channel digital audio processor 1.0 general description the DDX-8001 is a single chip solution for digital audio processing and digital amplifie r control, featuring output capabilities for ddx ? (direct digital amplification). in conjunction with a ddx ? power device, it provides high- quality, high-efficiency, all digital amplification. the device is extremely versatile allowing for input of nearly all digital formats including 6.1/7.1 chann el, 192khz/24-bit dvd-audio, and sacd. in 5.1 applications the additional two channels can be used for line-out or headphone drive. also provided in the DDX-8001 are a full assortment of digital processing features. this includes up to 10 programmable 32-bit biquads (eq) per channel, bass/treble tone control, and dual 8-input mixing blocks per channel. automodes? enable a time-to-market advantage by substantially reducing the am ount of software development needed for certain functions. this includes all possible 5.1 bass management configurations with simple large/small/off control settings. new advanced am radio mode solves one of the most common concerns using switching power amplifiers. the serial audio data input and output interfaces accept all possible formats, including the popular i 2 s format. eight channels of ddx ? processing are provided with capabilities of controlling the output switch ing frequency or modulation. this high quality conversion from pcm audio to ddx?s patented tri-state pwm switchi ng waveform provides over 100db snr and dynamic range. the DDX-8001 is a 4 th generation ddx ? controller and is uniquely suited for the most demanding applications, providing an audiophile experience without parallel.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 2 of 49 table of contents 1.0 general des cription ............................................................................................................ ...........................1 1.1 pin func tion................................................................................................................... .........................................4 1.2 absolute maximu m ratings....................................................................................................... .................6 1.3 thermal data ................................................................................................................... ................................6 1.4 recommended dc oper ating condi tions ............................................................................................ 6 1.5 pin descri ption ................................................................................................................ ...............................7 1.6 audio perfo rma nce .............................................................................................................. ........................9 1.7 pin connection (top vi ew) ...................................................................................................... .....................11 2.0 DDX-8001 i 2 c bus specif ication............................................................................................................ ........12 2.1 communication prot ocol......................................................................................................... ...............12 2.2 device a ddressin g.............................................................................................................. .........................12 2.3 write operation ................................................................................................................ ...........................12 2.4 read oper ation................................................................................................................. ............................13 3.0 register de scription ........................................................................................................... .....................................15 3.1 configuration regist er a (addr ess 00h) ......................................................................................... .....................16 3.2 configuration register b : seri al input format s (addres s 01h) .................................................................. .......18 3.3 configuration register c : seri al output form ats (addr ess 02h) ................................................................. .....20 3.4 configuration register d : pwm output formatti ng (addre ss 03h) ................................................................. .21 3.5 configuration register e : binar y output select ion (add ress 04h) ............................................................... ....22 3.6 configuration regist er f (addr ess 05h)......................................................................................... .....................22 3.7 configuration regist er g (addr ess 06h) ......................................................................................... ....................23 3.8 configuration regist er h (addr ess 07h) ......................................................................................... ....................24 3.9 configuration regist er i (add ress 08h) ......................................................................................... ......................25 3.10 volume c ontrol................................................................................................................. ....................................25 3.11 input m apping.................................................................................................................. .....................................29 3.12 automode? r egister s............................................................................................................ .............................30 3.13 processing loop m odes .......................................................................................................... ............................34 3.14 processing by pass m odes ........................................................................................................ ..........................35 3.15 tone control (a ddress 2ch)..................................................................................................... ...........................35 3.16 dynamics co ntrol............................................................................................................... ..................................36 3.17 pwm output timing.............................................................................................................. ...............................38 3.18 i 2 s output channel mapping ....................................................................................................... ........................39 4.0 user programmabl e proce ssing ................................................................................................... ..........................40 4.1 eq ? biquad equatio n ........................................................................................................... ..............................40 4.2 pre-scale...................................................................................................................... ........................................40 4.3 post-scale ..................................................................................................................... .......................................41 4.4 mixing ......................................................................................................................... ..........................................41 4.5 calculating 24-bit signed fracti onal numbers from a db value................................................................... .....41 4.6 user defined coe fficient ram................................................................................................... ..........................42 5.0 design info rmatio n ............................................................................................................. .....................................47 6.0 package info rmation ............................................................................................................ ........................48 6.1 package outli ne draw ing ........................................................................................................ ............................48 6.2 marking conf igurat ion .......................................................................................................... ................................49 table of figures figure 1 - ic-level block diagram ............................................................................................. .............................. 4 figure 2 - channel sign al flow diagram ......................................................................................... ......................... 4 figure 3 - fft ?60db , 1khz output .............................................................................................. ............................ 9 figure 4 - fft inter-modulati on distortion 19khz and 20khz..................................................................... .............. 9 figure 5 - thd vs . power, 1khz................................................................................................. ............................... 9 figure 6 - thd vs. frequency, 1w............................................................................................... ............................. 9 figure 7 - fft ?60db , 1khz output .............................................................................................. .......................... 10
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 3 of 49 figure 8 - fft inter-mo dulation distortion ..................................................................................... ......................... 10 figure 9 - fft ?60db , 1khz output .............................................................................................. .......................... 10 figure 10 - fft inter-m odulation distorti on 19khz and 20khz.................................................................... ........... 10 figure 11 - thd vs. vo ltage rms , 1khz......................................................................................... ....................... 11 figure 12 - thd vs. frequency, 1vrms........................................................................................... ........................ 11 figure 13 ? pin conn ection diagram. ............................................................................................ ......................... 11 figure 14 - i 2 c write pr ocedure .............................................................................................................. ................ 14 figure 15 - i 2 c read pr ocedure ............................................................................................................... ............... 14 figure 16 - general serial input and output formats ............................................................................ ................. 18 figure 17 ? serial input data timing charac teristics........................................................................... ................... 20 figure 18 - processi ng channel mux ............................................................................................. ......................... 29 figure 19 - eq processing data path and au tomode usage ......................................................................... ........ 30 figure 20 - basic limiter a nd volume flow diagram. ............................................................................. ................ 37 figure 21 - bi quad filter ...................................................................................................... .................................... 40 figure 22 - mix bl ock diagram .................................................................................................. .............................. 41 figure 23 - schemat ic diagram.................................................................................................. ............................. 47 list of tables table 1 - pin descript ion and numbering ........................................................................................ ......................... 4 table 2 - regist er summary..................................................................................................... ............................... 15 table 3 - ir and mcs settings for input sample rate and cloc k rate............................................................. ..... 17 table 4 - ir bit settings as a function of input sample rate ................................................................... ................ 17 table 5 - clock output rate as a function of cos an d sample rate ............................................................... .... 17 table 6 ? first bit selection table............................................................................................ ............................... 19 table 7 - supported serial audio input formats ................................................................................. .................... 19 table 8 - serial input data timing characteristics (f s = 32 to 192khz)......................................................... ......... 19 table 9 - serial audio output data formats ..................................................................................... ...................... 21 table 10 - ddx ? output modes .................................................................................................................. ............ 21 table 12 - pwm output speed sele ctions......................................................................................... ..................... 23 table 13 - master volume offset as a function of mv (7..0) ..................................................................... .............. 28 table 14 - channel volume as a function of cxv (7..0) .......................................................................... ................ 28 table 15 - channel volume trim as a function of cxvt (4..0) .................................................................... .......... 29 table 16 - channel mapping as a function of cxim bits......................................................................... ................ 29 table 17 - au tomode eq......................................................................................................... ................................ 30 table 18 - auto mode vo lume..................................................................................................... ............................. 30 table 19 - automode gain compression/ limiters .................................................................................. ................ 30 table 20 - center and rear speaker size selection .............................................................................. ................ 31 table 21 - front and sub speaker se lection ..................................................................................... ..................... 32 table 22 - automode am switch ing frequency selection .......................................................................... ........... 32 table 23 - crossover fr equency selection ....................................................................................... ...................... 33 table 24 - preset eq selection ................................................................................................. .............................. 33 table 25 - graphic eq b oost/cut se lection...................................................................................... ...................... 34 table 26 - tone control boost/cut selection.................................................................................... ...................... 35 table 27 - channel limite r mapping se lection ................................................................................... .................... 37 table 28 - limiter atta ck rate selection ....................................................................................... .......................... 37 table 29 - limiter rele ase rate selection ...................................................................................... ........................ 37 table 30 - limiter attack thre shold selecti on (ac-m ode). ...................................................................... .............. 38 table 31 - limiter release th reshold selecti on (ac-mo de)...................................................................... ............ 38 table 32 - limiter attack thre shold selecti on (drc-m ode). ...................................................................... ............ 38 table 33 - limiter release thre shold selection (drc-mo de). ..................................................................... .......... 38 table 34 - channel output timing se lection. .................................................................................... ..................... 39 table 35 - channel i 2 s output mapping............................................................................................................... ... 40 table 36 - ram block for bi quads, mixing, and scal ing .......................................................................... ............... 45
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 4 of 49 figure 1 - ic-level block diagram channel mapping 1x,2x,4x interp biquads(eq) tone volume limiter 2x interp interp_rate 8 inputs from i2s ddx ddx output down sample i2s i2s output mix #1 mix #2 6 inputs from dsd channel mapping pcm conversion figure 2 - channel signal flow diagram 1.1 pin function table 1 - pin description and numbering pin i/o pin name description pad type 1 i mvo/dsd_clk master volume override/ ds d input clock 5v tolerant ttl input buffer 3, 12, 28, 35, 44, 52, 59 i vdd3 3.3v supply 3.3v digital power supply voltage 2, 4, 13, 27, 36, 45, 53, 60 gnd ground digital ground 5,14, 22, 26, 37, 46, 54, 61 nc no connect 6 i sdi_78/dsd_6 input serial data channels 7 & 8/ dsd input channel 6 5v tolerant ttl input buffer system timing out1a/b out2a/b out3a/b out4a/b out5a/b out6a/b out7a/b out8a/b lrcko bicko sdo12 sdo34 sdo56 sdo78 sa scl sda mvo power-down pwdn eapd pll system control ddx serial data out volume limiting serial data/ dsd in channel mapping mix treble, bass, eq i 2 c xti ckout lrcki bicki sdi12 sdi34 sdi56 sdi78 pllb
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 5 of 49 table 1 - pin description and numbering pin i/o pin name description pad type 7 i sdi_56/dsd_5 input serial data channels 5 & 6/ dsd input channel 5 5v tolerant ttl input buffer 8 i sdi_34/dsd_4 input serial data channels 3 & 4/ dsd input channel 4 5v tolerant ttl input buffer 9 i sdi_12/dsd_3 input serial data channels 1 & 2/ dsd input channel 3 5v tolerant ttl input buffer 10 i lrcki/dsd_2 input left/right clock/ dsd input channel 2 5v tolerant ttl input buffer 11 i bicki/dsd_1 input serial clock/ dsd input channel 1 5v tolerant ttl input buffer 15 i reset global reset 5v tolerant ttl schmitt trigger input buffer 16 i pll_bypass bypass phase locked loop 5v tolerant ttl input with pull-down 17 i sa select address (i2c) 5v tolerant ttl input with pull-down 18 i/o sda i2c serial data bidirectional buffer: 5 v tolerant ttl schmitt trigger input; 3.3v capable 2 ma slew-rate control output; 19 i scl i2c serial clock 5v tolerant ttl schmitt trigger input buffer 20 i xti clock input 5v tolerant ttl schmitt trigger input buffer 21 i filter_pll pll filter a nalog pad 23 gnda pll ground a nalog ground 24 i vdda pll supply 3.3v analog power supply voltage 25 o ckout clock output 3.3 v capable ttl tristate 4 ma output buffer 29 o out8b pwm channel 8 output b 3.3v capable ttl 2ma output buffer 30 o out8a pwm channel 8 output a 3.3v capable ttl 2ma output buffer 31 o out7b pwm channel 7 output b 3.3v capable ttl 2ma output buffer 32 o out7a pwm channel 7 output a 3.3v capable ttl 2ma output buffer 33 o out6b pwm channel 6 output b 3.3v capable ttl 2ma output buffer 34 o out6a pwm channel 6 output a 3.3v capable ttl 2ma output buffer 38 o out5b pwm channel 5 output b 3.3v capable ttl 2ma output buffer 39 o out5a pwm channel 5 output a 3.3v capable ttl 2ma output buffer 40 o out4b pwm channel 4 output b 3.3v capable ttl 2ma output buffer 41 o out4a pwm channel 4 output a 3.3v capable ttl 2ma output buffer 42 o out3b pwm channel 3 output b 3.3v capable ttl 2ma output buffer 43 o out3a pwm channel 3 output a 3.3v capable ttl 2ma output buffer 47 o out2b pwm channel 2 output b 3.3v capable ttl 2ma output buffer 48 o out2a pwm channel 2 output a 3.3v capable ttl 2ma output buffer 49 o out1b pwm channel 1 output b 3.3v capable ttl 2ma output buffer 50 o out1a pwm channel 1 output a 3.3v capable ttl 2ma output buffer 51 o eapd ext. amp power down 3.3v capable ttl 2ma output buffer 55 o bicko output serial clock 3.3v capable ttl 2ma output buffer 56 o lrcko output left/right clock 3. 3v capable ttl 2ma output buffer 57 o sdo_12 output serial data channels 1&2 3.3v capable ttl 2ma output buffer 58 o sdo_34 output serial data channels 3&4 3.3v capable ttl 2ma output buffer 62 o sdo_56 output serial data channels 5&6 3.3v capable ttl 2ma output buffer 63 o sdo_78 output serial data channels 7&8 3.3v capable ttl 2ma output buffer 64 i pwdn device powerdown 5v tolerant ttl schmitt trigger input buffer
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 6 of 49 1.2 absolute maximum ratings symbol parameter value unit v dd_3.3 3.3v digital power supply -0.5 to 4 v v dda 3.3v analog power supply -0.5 to 4 v v i voltage on input pins -0.5 to (vdd + 0.5) v v o voltage on output pins -0.5 to (vdd + 0.5) v v b voltage on 5v tolerant inputs and bi-directional pins (note 1) -0.5 to 5.5 v t stg storage temperature -40 to +150 c t a ambient operating temperature -20 to +85 c note 1 ?withstands -0.8v undershoot and 6.3v overshoots for 4ns max. 1.3 thermal data symbol parameter value unit r j-a thermal resistance junction to ambient 85 c/w 1.4 recommended dc op erating conditions symbol parameter value unit v dd _3.3 3.3v digital power supply voltage 3.0 to 3.6 v v dda 3.3v analog power supply 3.0 to 3.6 v t a operating ambient temperature 0 to 70 c 1.4.1 dc electrical characteristics: 3. 3v capable output buffers (note 2) (pins 18,25,29-34,38-43,47-51,55-58,62,63) symbol parameter test condition min. typ. max. unit v ol2 low level 2ma output ioi = 2ma 0.15 v v oh2 high level 2ma output ioh = -2ma v dd -0.15 v v ol4 low level 4ma output ioi = 4 ma 0.15 v v oh4 high level 4ma output ioh = -4 ma v dd -0.15 v note 2 - the min and max values comply to the jedec standard, which is 0.4v max for vol and 2.4 for voh. 1.4.2 dc electrical characteristic s: 5v tolerant input buffers (pins 1,6-11,15,18,19,20,64) symbol parameter test condition min. typ. max. unit v il low level input voltage 0.8 v v ih high level input voltage 2.0 v v hyst schmitt trigger hysteresis 0.4 v i il low level input current vi = 0v (note 3) 40 60 110 ua i ih high level input current vi = vdd_3.3 (note 3) 25 60 110 ua note 3 - min condition: vdd=3v, 125c, min process; max condition: vdd=3.6v, -40c, fast process. 1.4.3 operating characteristics symbol parameter test condition min. typ. max. unit i vdd_3.3 operating current 3.3v all 8-channels operating 73 ma i vdd_3.3 powerdown current 3.3v powerdown asserted 7 ma 1.4.4 electrical characteristics (vdd= 3.30.3v, t a =0 to 70c unless otherwise specified) symbol parameter test condition min. typ. max. unit v esd electrostatic protection leakage <1ua (note 4) 2000 v note 4 - human body model.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 7 of 49 1.4.5 timing characteristics (vdd= 3.30.3v, t a =0 to 70c unless otherwise specified) symbol parameter test condition min. typ. max. unit t reset reset hold time active low reset (pin 15) 100 nsec cko 48k clock out frequency w/ 48k/96k/192k fs cos1..0 = ?10? 12.288 mhz cko 44.1k clock out frequency w/ 44.1k/88.2k/176.4k fs cos1..0 = ?10? 11.2896 mhz cko free-run clock out free-run frequency no clock applied at xti (note 5) 2.3 3.5 mhz cko jitter short-term jitter rising ? rising edge 300 psec pk-pk note 5 - the DDX-8001 is designed to operate at a minimum free -run frequency when there is no clock applied at xti. this assu res proper i2c communication without a valid master clock. the device is not designed to process audio data without a valid clock applied at xti. 1.5 pin description 1.5.1 mvo/dsd_clk: master volume override and dsd input clock (pin 1) the master volume override enables the user to bypass the volume control on all channels. when mvo is pulled high, the master volume register is set to 00h, which corresponds to its full scale setting. the master volume register setting offsets the individual channel volume settings, which default to 0db. also, with mvo pulled high the eapd output will enable the power device. this mode is intended fo r testing purposes and applications where i 2 c is not available. when in dsd mode (ir=11), this input is used for the dsd input clock, which should be typically 2.8224mhz. when operating the device in dsd mode, this pin must be held low until the dsd input mode is selected via mcs and ir bits in configuration register a. 1.5.2 sdi_12 through 78/dsd data input s: serial data in (pins 6-9) pcm audio information enters the device here. six format choices are available including i 2 s, left- or right- justified, lsb or msb first, with word widths of 16, 18, 20 and 24 bits. when in dsd mode, these pins serve as the data inputs for channels 3 thru 6. 1.5.3 lrcki: left/right clock in/ dsd data input (pin 10) the left/right clock input is for the purp ose of data word framing. the clock frequency will be at the input sample rate fs. when in dsd mode, this pin serves as the data input for channel 2. 1.5.4 bicki: bit clock in/ dsd data input (pin 11) the serial or bit clock input is for the purpose of frami ng each data bit. the bit clock frequency is typically 64*fs, for example using i 2 s serial format. when in dsd mode, this pin serves as the data input for channel 1. 1.5.5 reset (pin 15) driving reset low sets all outputs low and returns all register settings to their defaults. the reset is asynchronous to the internal clock. 1.5.6 pll bypass (pin 16) pll bypass is used to steer the xti inpu t bypassing the internal pll circuit. th is pin will bypass the internal pll and the xti clock input will directly drive the internal devi ce clock. this is intended for testing purposes only.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 8 of 49 1.5.7 i 2 c (pins 17-19) the sa (select address), sda (i 2 c data) and scl (i 2 c clock) pins operate per the i 2 c specification. see section 2.0. fast-mode (400kb/sec) i2c communication is supported. 1.5.8 pll: phase locked loop the phase locked loop section provides the system timing signals and ckout. 1.5.8.1 xti: master clock in (pin 20) this is the master clock input. the master clock must be an integer multiple of the lr clock frequency. typically, the master clock frequency is 12.288 mhz (256*fs) for a 48khz sample rate, which is the default at power-up. care must be taken not to exceed an internal cloc k frequency of 98.304mhz; otherwise the device may not properly operate or be able to communicate. 1.5.8.2 pllf: pll filter (pin 21) pll filter connects to external filter components for pll loop compensation. refer to the schematic diagram, figure 23, for the recommended circuit. 1.5.8.3 vdda and gnda: phase locked loop power (pins 24, 23) the phase locked loop power is applied here. this +3.3 v supply must be well bypassed and filtered for noise immunity. the audio performance of the devic e is critically dependent upon the pll circuit. 1.5.8.4 ckout: clock out (pin 25) system synchronization and master clocks are provided by the ckout. this output may be used as a clock source for other devices in the system. 1.5.9 out1 through out8: pwm outputs (pins 29-34, 38-43, 47-50) the pwm outputs provide the input signal for the power devices. both patented ddx ? and binary pwm modes are supported. 1.5.10 eapd: external amp lifier power-down (pin 51) eapd (output) is used to control the operation of ddx ? power devices and for power-on and power-off sequencing. 1.5.11 bicko and lrcko: bit clock out and lr clock out (pins 55, 56) these clock signals are used to frame the i 2 s output audio data. when in dsd mode, these pins output at 176.4khz sample rate. 1.5.12 sdo_12 through 78: serial data out (pins 57, 58, 62, 63) pcm audio information exits the device here. six di fferent format choices are available including i 2 s, left- or right- justified, lsb or msb first, with word widths of 16, 18, 20 and 24 bits. 1.5.13 pwdn: device power-down (pin 64) pwdn puts the DDX-8001 into a low-power state via appropriate power-down sequence. pulling pwdn low begins power-down sequence, a so ft-mute is performed on all outputs , and eapd goes low ~30ms later.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 9 of 49 1.6 audio performance parameter from ddx-2160 output from i2s output from analog line ouput snr aw(typical) -100db -137db -99db dynamic range aw(typical) -100db -137db -99db thd (typical) 0.035% (1w, 1khz) 0.0000 2% (-10dbfs) 0.015% (1 vrms, 1khz) the eb-8001 test platform was used to produce the measur ements shown in the following sections. this platform was designed with the interest of testing and demonstr ating the DDX-8001 device in concert with the ddx-2160 power device(s). see the corresponding application not e for more detailed information including schematics concerning this evaluation board. 1.6.1 performance measured with ddx-2160 power device at vcc=34v, 8 ohm load. 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 3 - fft ?60db, 1khz output figure 4 - fft inter-modulation distortion 19khz and 20khz 60m 80 100m 200m 500m 1 2 5 10 20 50 w 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 0.001 1 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 % figure 5 - thd vs. power, 1khz fi gure 6 - thd vs. frequency, 1w
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 10 of 49 1.6.2 performance of i2s output : 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 7 - fft ?60db, 1khz output figur e 8 - fft inter-modulation distortion 1.6.3 performance of analog line output 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 9 - fft ?60db, 1khz output figure 10 - fft inter-modulation distortion 19khz and 20khz
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 11 of 49 1.6.3 performance of analog line output (continued) 100m 3 200m 300m 400m 500m 600m 700m 900m 1 2 v 0.001 1 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 0.001 1 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 % figure 11 - thd vs. voltage rms , 1khz figure 12 - thd vs. frequency, 1vrms 1.7 pin connection (top view) figure 13 ? pin connection diagram. pwdn sdo78 sdo56 nc gnd vdd3.3 sdoo34 sdo12 lrcko bicko nc gnd vdd3.3 eapd out1a out1b sa sda scl xti pllf nc gnd_pl vdd_pl ckout nc gnd vdd3.3 out8b out8a out7b out7a 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 mvo/dsd_cl k gnd vdd3.3 gnd nc sdi78/dsd_6 sdi56/dsd_5 sdi34/dsd_4 sdi12/dsd_3 lrcki/dsd_2 bicki/dsd_1 vdd3.3 gnd nc reset pllb out2a out2b nc gnd vdd3.3 out3a out3b out4a out4b out5a out5b nc gnd vdd3.3 out6a out6b
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 12 of 49 2.0 DDX-8001 i 2 c bus specification the DDX-8001 supports the i 2 c protocol. this protocol defines any dev ice that sends data on to the bus as a transmitter and any device that reads the data as a receiver . the device that controls the data transfer is known as the master and the other as the slave. the master always starts the transfer and provides the serial clock for synchronization. the DDX-8001 is always a slave device in all of its communications. 2.1 communication protocol 2.1.1 data transition or change data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high is used to identify a start or stop condition. 2.1.2 start condition start is identified by a high to low transition of the dat a bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. 2.1.3 stop condition stop is identified by a low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates co mmunication between DDX-8001 and the bus master. 2.1.4 data input during the data input the DDX-8001 samples the sda signal on the rising edge of clock scl. for correct device operation the sda signal must be stable during the risi ng edge of the clock and the data can change only when the scl line is low. 2.2 device addressing to start communication between the master and the DDX-8001, the master must initiate with a start condition. following this, the master sends 8-bits (msb first) onto the sda line corresponding to the device select address and read or write mode. the 7 most significant bits are the device address identifiers, corresponding to the i 2 c bus definition. in the ddx- 8001 the i 2 c interface has two device addresses depending on t he sa pin configuration, 0x40 or 0100000x when sa = 0, and 0x42 or 0100001x when sa = 1. the 8th bit (lsb) identifies read or write operation, rw. th is bit is set to 1 in read mode and 0 for write mode. after a start condition the DDX-8001 identifies the dev ice address on the bus. if a match is found, it acknowledges the identification on the sda bus during the 9th bit time. the byte following the device identification byte is the internal space address. 2.3 write operation following the start condition the master sends a device select code with the rw bit set to 0. the DDX-8001 acknowledges this and then the master writes the internal address byte. after receiving the internal byte address the DDX-8001 again responds with an acknowledgement. 2.3.1 byte write in the byte write mode the master sends one data byte. this is acknowledged by the DDX-8001. the master then terminates the transfer by generating a stop condition.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 13 of 49 2.3.2 multi-byte write the multi-byte write modes can start from any internal address. sequential data byte writes will be written to sequential addresses within the DDX-8001. the master generating a stop condition terminates the transfer. 2.4 read operation 2.4.1 current address byte read following the start condition the master sends a device select code with the rw bit set to 1. the DDX-8001 acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. 2.4.1.1 current address multi-byte read the multi-byte read modes can start from any internal address. sequential data bytes will be read from sequential addresses within the DDX-8001. the master acknowleges each data byte read and then generates a stop condition terminating the transfer. 2.4.2 random address byte read following the start condition the master sends a device select code with the rw bit set to 0. the DDX-8001 acknowledges this and then the master writes the internal address byte. after receiving the internal byte address the DDX-8001 again responds with an acknowledgement. the master then initiates another start condition and sends the device select code with the rw bit set to 1. the DDX-8001 acknowledges this and then responds by sending one byte of data. the master then termin ates the transfer by generating a stop condition. 2.4.2.1 random address multi-byte read the multi-byte read modes can start from any internal address. sequential data bytes will be read from sequential addresses within the DDX-8001. the master acknowleges each data byte read and then generates a stop condition terminating the transfer.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 14 of 49 write mode sequence dev-addr ack start rw sub-addr ack data in ack stop byte write dev-addr ack start rw sub-addr ack data in ack stop multibyte write data in ack figure 14 - i 2 c write procedure read mode sequence dev-addr ack start rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr a ck stop random address read data no a ck start rw dev-addr ack start data ack data ack stop sequential current read data no a ck dev-addr ack start rw sub-addr ack dev-addr a ck sequential random read data a ck start rw data a ck no a ck stop data rw= high figure 15 - i 2 c read procedure
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 15 of 49 3.0 register description table 2 - register summary address name d7 d6 d5 d4 d3 d2 d1 d0 0x00 confa cos1 cos0 dspb ir1 ir0 mcs2 mcs1 mcs0 0x01 confb saifb sai3 sai2 sai1 sai0 0x02 confc saofb sao3 sao2 sao1 sao0 0x03 confd mpc csz4 csz3 csz2 csz1 csz0 om1 om0 0x04 confe c8bo c7bo c6bo c5 bo c4bo c3bo c2bo c1bo 0x05 conff pwms2 pwms1 pw ms0 bql psl demp drc hpb 0x06 confg mpcv res res res ame cod sid pwmd 0x07 confh ecle res bcle ide zde sve zce nsbw 0x08 confi eapd psce 0x09 mmute mmute 0x0a mvol mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 0x0b c1vol c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 0x0c c2vol c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 0x0d c3vol c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 0x0e c4vol c4v7 c4v6 c4v5 c4v4 c4v3 c4v2 c4v1 c4v0 0x0f c5vol c5v7 c5v6 c5v5 c5v4 c5v3 c5v2 c5v1 c5v0 0x10 c6vol c6v7 c6v6 c6v5 c6v4 c6v3 c6v2 c6v1 c6v0 0x11 c7vol c7v7 c7v6 c7v5 c7v4 c7v3 c7v2 c7v1 c7v0 0x12 c8vol c8v7 c8v6 c8v5 c8v4 c8v3 c8v2 c8v1 c8v0 0x13 c1vtmb c1m c1vbp c1vt4 c1vt3 c1vt2 c1vt1 c1vt0 0x14 c2vtmb c2m c2vbp c2vt4 c2vt3 c2vt2 c2vt1 c2vt0 0x15 c3vtmb c3m c3vbp c3vt4 c3vt3 c3vt2 c3vt1 c3vt0 0x16 c4vtmb c4m c4vbp c4vt4 c4vt3 c4vt2 c4vt1 c4vt0 0x17 c5vtmb c5m c5vbp c5vt4 c5vt3 c5vt2 c5vt1 c5vt0 0x18 c6vtmb c6m c6vbp c6vt4 c6vt3 c6vt2 c6vt1 c6vt0 0x19 c7vtmb c7m c7vbp c7vt4 c7vt3 c7vt2 c7vt1 c7vt0 0x1a c8vtmb c8m c8vbp c8vt4 c8vt3 c8vt2 c8vt1 c8vt0 0x1b c12im c2im2 c2im1 c2im0 c1im2 c1im1 c1im0 0x1c c34im c4im2 c4im1 c4im0 c3im2 c3im1 c3im0 0x1d c56im c6im2 c6im1 c6im0 c5im2 c5im1 c5im0 0x1e c78im c8im2 c8im1 c8im0 c7im2 c7im1 c7im0 0x1f auto1 amdm amgc2 amgc1 amgc0 amv1 amv0 ameq1 ameq0 0x20 auto2 sub rss1 rss0 css1 css0 fss ambmxe ambmme 0x21 auto3 amam2 amam1 amam0 amame msa amps 0x22 preeq xo2 xo1 xo0 peq4 peq3 peq2 peq1 peq0 0x23 ageq ageq4 ag eq3 ageq2 ageq1 ageq0 0x24 bgeq bgeq4 bg eq3 bgeq2 bgeq1 bgeq0 0x25 cgeq cgeq4 cg eq3 cgeq2 cg eq1 cgeq0 0x26 dgeq dgeq4 dg eq3 dgeq2 dg eq1 dgeq0 0x27 fgeq egeq4 eg eq3 egeq2 egeq1 egeq0 0x28 bqlp c8blp c7blp c6blp c5 blp c4blp c3blp c2blp c1blp 0x29 mxlp c8mxlp c7mxlp c6mxlp c5mxlp c4mxlp c3mxlp c2mxlp c1mxlp 0x2a eqbp c8eqbp c7eqbp c6eqbp c5 eqbp c4eqbp c3eqbp c2eqbp c1eqbp 0x2b tonebp c8tcb c7tcb c6tcb c5tcb c4tcb c3tcb c2tcb c1tcb 0x2c tone ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 0x2d c1234ls c4ls1 c4ls0 c3ls1 c3ls0 c2ls1 c2ls0 c1ls1 c1ls0 0x2e c5678ls c8ls1 c8ls0 c7ls1 c7ls0 c6ls1 c6ls0 c5ls1 c5ls0 0x2f l1ar l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 0x30 l1atrt l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 0x31 l2ar l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 0x32 l2atrt l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 16 of 49 table 2 - register summary address name d7 d6 d5 d4 d3 d2 d1 d0 0x33 c12ot c2ot2 c2ot1 c2ot0 c1ot2 c1ot1 c1ot0 0x34 c34ot c4ot2 c4ot1 c4ot0 c3ot2 c3ot1 c3ot0 0x35 c56ot c6ot2 c6ot1 c6ot0 c5ot2 c5ot1 c5ot0 0x36 c78ot c8ot2 c8ot1 c8ot0 c7ot2 c7ot1 c7ot0 0x37 c12om c2om2 c2om1 c2om0 c1om2 c1om1 c1om0 0x38 c34om c4om2 c4om1 c4om0 c3om2 c3om1 c3om0 0x39 c56om c6om2 c6om1 c6om0 c5om2 c5om1 c5om0 0x3a c78om c8om2 c8om1 c8om0 c7om2 c7om1 c7om0 0x3b cfaddr1 cfa9 cfa8 0x3c cfaddr2 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 0x3d b1cf1 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 0x3e b1cf2 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 0x3f b1cf3 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 0x40 b2cf1 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 0x41 b2cf2 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 0x42 b2cf3 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 0x43 a1cf1 c3b23 c3b22 c3b21 c3b20 c3b19 c3b18 c3b17 c3b16 0x44 a1cf2 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 0x45 a1cf3 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 0x46 a2cf1 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 0x47 a2cf2 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 0x48 a2cf3 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 0x49 b0cf1 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 0x4a b0cf2 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 0x4b b0cf3 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 0x4c cfud wa w1 0x4d mpcc1 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 0x4e mpcc2 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 0x4f res res res res res res res res res 0x50 res res res res res res res res res 0x51 psc1 rcv11 rcv10 rcv9 rcv8 rcv7 rcv6 rcv5 rcv4 0x52 psc2 rcv3 rcv2 rcv1 rcv0 cnv11 cnv10 cnv9 cnv8 0x53 psc3 cnv7 cnv6 cnv5 cnv4 cnv3 cnv2 cnv1 cnv0 3.1 configuration register a (address 00h) d7 d6 d5 d4 d3 d2 d1 d0 cos1 cos0 dspb ir1 ir0 mcs2 mcs1 mcs0 1 0 0 0 0 0 1 1 3.1.1 master clock select bit r/w rst name description 2..0 r/w 011 mcs (2..0) master clock select : selects the ratio between the input i 2 s sample frequency and the input clock. the DDX-8001 will support sample rates of 32khz, 44.1khz, 48khz, 88.2khz, 96khz , 176.4khz, 192khz, and 2.8224mhz dsd. therefore the internal clock will be: ? 65.536mhz for 32khz ? 90.3168mhz for 44.1khz, 88.2khz, 176.4khz, and dsd ? 98.304mhz for 48khz, 96khz, and 192khz the external clock frequency provided to the xti pin must be an exact multiple of the input sample frequency (fs). the relationship between the input clock and the input sample rate is determined by both the mcsx and the irx (input rate) register bits. the mcsx bits determine the pl l factor generating the internal clock and the irx bits
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 17 of 49 determine the oversampling ratio used internally. care must be taken to not exceed an internal clock frequency of 98.304 mhz when changing mcs bits. table 3 - ir and mcs settings for input sample rate and clock rate mcs (2..0) input sample rate fs (khz) ir 1xx 011 010 001 000 32, 44.1, 48 00 128fs 256fs 384fs 512fs 768fs 88.2, 96 01 64fs 128f s 192fs 256fs 384fs 176.4, 192 10 64fs 128fs 192fs 256fs 384fs dsd 11 2fs 4fs 6fs 8fs 12fs 3.1.2 interpolation ratio select bit r/w rst name description 4..3 r/w 00 ir (1..0) interpolation ratio sele ct: selects internal interpolation ratio based on input i 2 s sample frequency the DDX-8001 has variable interpolation (oversampli ng) settings such that internal processing and ddx ? output rates remain consistent. the first processing block interpolates by either 4 times, 2 times, or 1 time (pass- through). the oversampling ratio of this inte rpolation is determined by the ir bits. table 4 - ir bit settings as a function of input sample rate input sample ratefs (khz) ir (1,0) 1 st stage interpolation ratio 32 00 4 times oversampling 44.1 00 4 times oversampling 48 00 4 times oversampling 88.2 01 2 times oversampling 96 01 2 times oversampling 176.4 10 pass-through 192 10 pass-through dsd 11 dsd -> 176.4khz conversion 3.1.3 dsp bypass bit r/w rst name description 5 r/w 0 dspb dsp bypass bit: 0 ? normal operation 1 ? bypass of eq and mixing functionality setting the dspb bit bypasses all the eq and mixing functionality of the DDX-8001 core. 3.1.4 clock output select bit r/w rst name description 7..6 r/w 10 cos (1..0) clock output select: selects the frequency of the clock output, ckout pin table 5 - clock output rate as a function of cos and sample rate input sample rate (khz) cos (1,0) 32, 44.1, 48 88.2, 96 176.4, 192 00 2048*fs 1024*fs 512*fs 01 512*fs 256*fs 128*fs 10 256*fs 128*fs 64*fs 11 128*fs 64*fs 32*fs
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 18 of 49 3.2 configuration register b : se rial input formats (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 saifb sai3 sai2 sai1 sai0 0 0 0 0 0 3.2.1 serial audio input interface format bit r/w rst name description 3..0 r/w 0000 sai (3..0) serial audio input interface format: determines the interface format of the input se rial digital audio interface. serial data interface the DDX-8001 serial audio input was designed to interfac e with standard digital audio components and to accept a number of serial data formats. the DDX-8001 always acts as a slave when receiving audio input from standard digital audio components. serial data for eight channels is pr ovided using 6 input pins: left/right clock lrcki (pin 10), serial clock bicki (pin 11), serial data 1 & 2 sdi12 (pin 9), serial data 3 & 4 sdi34 (pin 8), serial data 5 & 6 sdi56 (pin 7), and serial data 7 & 8 sdi78 (pin 6). the sai register (configuration register b ? 01h, bits d3 -d0) and the saifb register (configuration register b ? 01h, bit d4) are used to specify the serial dat a format. the default serial data format is i 2 s, msb-first. available formats are shown in figure 16 and the tables that follow. i 2 s left justified lrclk left right sclk sdata lsb msb lsb msb msb lrclk left right sclk sdata lsb msb lsb msb msb right justified lrclk left right sclk sdata lsb msb lsb msb msb figure 16 - general serial input and output formats for example, sai=1110 and saifb=1 would specif y right-justified 16-bit data, lsb-first.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 19 of 49 table 7 below lists the serial audio input form ats supported by DDX-8001 as related to bicki = 32/48/64fs, where the sampling ra te fs = 32/44.1/48/88. 2/96/176.4/192 khz. table 6 ? first bit selection table saifb format 0 msb-first 1 lsb-first note: serial input and output form ats are specified distinctly. table 7 - supported serial audio input formats bicki sai (3...0) saifb interface format 1100 x i 2 s 15bit data 32fs 1110 x left/right-justified 16bit data 0100 x i 2 s 23bit data 0100 x i 2 s 20bit data 1000 x i 2 s 18bit data 0100 0 msb first i 2 s 16bit data 1100 1 lsb first i 2 s 16bit data 0001 x left-justified 24bit data 0101 x left-justified 20bit data 1001 x left-justified 18bit data 1101 x left-justified 16bit data 0010 x right-justified 24bit data 0110 x right-justified 20bit data 1010 x right-justified 18bit data 48fs 1110 x right-justified 16bit data 0000 x i 2 s 24bit data 0100 x i 2 s 20bit data 1000 x i 2 s 18bit data 0000 0 msb first i 2 s 16bit data 1100 1 lsb first i 2 s 16bit data 0001 x left-justified 24bit data 0101 x left-justified 20bit data 1001 x left-justified 18bit data 1101 x left-justified 16bit data 0010 x right-justified 24bit data 0110 x right-justified 20bit data 1010 x right-justified 18bit data 64fs 1110 x right-justified 16bit data table 8 - serial input data timing characteristics (fs = 32 to 192khz) bicki frequency (slave mode) 12.5mhz max. bicki pulse width low (t0) (slave mode) 40 ns min. bicki pulse width high (t1) (slave mode) 40 ns min. bicki active to lrcki edge delay (t2) 20 ns min. bicki active to lrcki edge delay (t3) 20 ns min. sdi valid to bicki active setup (t4) 20 ns min. bicki active to sdi hold time (t5) 20 ns min.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 20 of 49 figure 17 ? serial input data timing characteristics 3.3 configuration register c : serial output formats (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 saofb sao3 sao2 sao1 sao0 0 0 0 0 0 3.3.1 serial audio output interface format bit r/w rst name description 3..0 r/w 0000 sao (3..0) serial audio output interface format: determines the interface format of the output serial digital audio interface. the DDX-8001 features a serial audio output interface t hat consists of 8 channels. the serial audio output always acts as a slave to the serial audio input interf ace and therefore all output clocks are synchronous with the input clocks. the output sample frequency (fs) is also equi valent to the input sample frequency. in the case of sacd/dsd input, the serial audio output will act as a mast er with an output fs of 176.4khz. the output serial format can be selected independently from the input fo rmat and is done via the sao and saofb bits found in configuration register c (02h). 3.3.2 serial audio output interface first bit bit r/w rst name description 4 r/w 0 saofb determines msb or lsb fi rst for all sao formats 0 ? msb first 1 ? lsb first bicki t0 t1 lrcki t2 t 3 sdi t4 t5
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 21 of 49 table 9 - serial audio output data formats bicki= bicko sao (3...0) interface format 0111 i 2 s data 32fs 1111 left/right-justified 16bit data 1110 i 2 s data 0001 left-justified data 1010 right-justified 24bit data 1011 right-justified 20bit data 1100 right-justified 18bit data 48fs 1101 right-justified 16bit data 0000 i 2 s data 0001 left-justified data 0010 right-justified 24bit data 0011 right-justified 20bit data 0100 right-justified 18bit data 64fs 0101 right-justified 16bit data 3.4 configuration register d : pwm output formatting (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 mpc csz4 csz3 csz2 csz1 csz0 om1 om0 1 1 0 0 0 0 1 0 3.4.1 ddx ? power output mode bit r/w rst name description 1..0 r/w 10 om (1..0) ddx power output mode: selects configuration of ddx ? output. the ddx ? power output mode selects how the ddx ? output timing is configured. different power devices can use different output modes. th e ddx-2060/2100/2160 recommended use is om = 10. when om=11 the csz bits determine the size of the ddx ? compensating pulse. table 10 - ddx ? output modes om (1,0) output stage ? mode 00 not used 01 not used 10 ddx-2060/2100/2160 11 variable compensation 3.4.2 ddx ? variable compensating pulse size csz(4..0) compensating pulse size 00000 0 clock period compensating pulse size 00001 1 clock period compensating pulse size ? ? 11111 31 clock period compensating pulse size the ddx ? variable compensating pulse size is intended to adapt to different power stage ics. contact apogee applications for support when deciding this function. 3.4.3 max power correction bit r/w rst name description 7 r/w 1 mpc max power correction: 0 ? mpc disabled 1 ? mpc enabled
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 22 of 49 setting the mpc bit corrects the ddx- 2060/2100/2160 power device at high power. this mode will lower the thd+n of a full ddx-2060 ddx ? system at maximum power output and slightly below. 3.5 configuration register e : bina ry output selection (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 c8bo c7bo c6bo c5bo c4bo c3bo c2bo c1bo 0 0 0 0 0 0 0 0 3.5.1 binary output enable registers bit r/w rst name description 0 r/w 0 c1bo 1 r/w 0 c2bo 2 r/w 0 c3bo 3 r/w 0 c4bo 4 r/w 0 c5bo 5 r/w 0 c6bo 6 r/w 0 c7bo 7 r/w 0 c8bo channels 1, 2, 3, 4, 5, 6, 7, & 8 binary output mode enable bits. 0 ? ddx ? ternary output modulation 1 ? binary output modulation each individual channel output can be set to output a bina ry pwm stream. in this mode output a of a channel will be considered the positive output and output b is the negative inverse. 3.6 configuration register f (address 05h) d7 d6 d5 d4 d3 d2 d1 d0 pwms2 pwms1 pwms0 bql psl demp drc hpb 0 0 0 0 0 0 0 0 3.6.1 high-pass filter bypass bit r/w rst name description 0 r/w 0 hpb high-pass filter bypass bit. 0 ? ac coupling high pass filter enabled 1 ? ac coupling high pass filter disabled the DDX-8001 features an internal digital high-pass filter for the purpose of dc blocking. the purpose of this filter is to prevent dc signals from passing through a ddx ? amplifier. dc signals can cause speaker damage. if hpb = 1, then this filter is made available as user-programmable biquad#1. 3.6.2 dynamic range comp ression/anti-clipping bit bit r/w rst name description 1 r/w 0 drc dynamic range compression/anti-clipping 0 ? limiters act in anti-clipping mode 1 ? limiters act in dynamic range compression mode both limiters can be used in one of two ways, anti-clippi ng or dynamic range compression. when used in anti- clipping mode the limiter threshold values are constant and dependent on the limiter settings. in dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level. 3.6.3 de-emphasis bit r/w rst name description 2 r/w 0 demp de-emphasis: 0 ? no de-emphasis 1 ? de-emphasis by setting this bit to high, or one (1), de-emphasis will im plemented on all channels. when this feature is used it takes the place of biquad #8 in each channel and any coefficients using biquad #8 will be ignored. dspb (dsp bypass, bit d5, cfa) bit must be set to 0 for de-emphasis to function.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 23 of 49 3.6.4 post-scale link bit r/w rst name description 3 r/w 0 psl post-scale link: 0 ? each channel uses individual post-scale value 1 ? each channel uses channel 1 post-scale value post-scale functionality is an attenuation placed after t he volume control and direct ly before the conversion to pwm. post-scale is used by the pscorrect? featur e and can also be used to limit the maximum modulation index and therefore the peak current. a setting of 1 in the psl register will result in the use of the value stored in channel 1 post-scale for all eight internal channels. 3.6.5 biquad coefficient link bit r/w rst name description 4 r/w 0 bql biquad link: 0 ? each channel uses coefficient values 1 ? each channel uses channel 1 coefficient values for ease of use, all channels can use the biquad coeffi cients loaded into the channel 1 coefficient ram space by setting the bql bit to 1. therefore, any eq updates only have to be performed once. 3.6.6 pwm speed mode bit r/w rst name description 7..5 r/w 000 pwms (2..0) pwm speed selection: table 12 - pwm output speed selections pwms (1..0) pwm output speed 000 normal speed (384khz) all channels 001 half speed (192khz) all channels 010 double speed (768khz) all channels 011 normal speed channels 1-6, double speed channels 7-8 100 odd speed (341.3khz) all channels 3.7 configuration register g (address 06h) d7 d6 d5 d4 d3 d2 d1 d0 mpcv res res res ame cod sid pwmd 0 0 0 0 0 0 0 0 3.7.1 output signal disables bit r/w rst name description 0 r/w 0 pwmd pwm output disable: 0 ? pwm output normal 1 - no pwm output 1 r/w 0 sid serial interface (i 2 s out) disable: 0 ? i 2 s output normal 1- no i 2 s output 2 r/w 0 cod clock output disable: 0 ? clock output normal 1- no clock output the output signal disable bits will turn off, driv ing low, the corresponding outputs at the pin. 3.7.2 am mode enable bit r/w rst name description 3 r/w 0 ame am mode enable: 0 ? normal ddx ? operation. 1 ? am reduction mode ddx ? operation.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 24 of 49 the DDX-8001 features a ddx ? processing mode that minimizes the am ount of noise generated in the frequency range of am radio. this mode is intended for use when ddx ? is operating in a device with an active am tuner. the snr of the ddx ? processing is reduced to ~83db in this mode, which is still greater than the snr of am radio. 3.7.3 max power correction variable bit r/w rst name description 7 r/w 0 mpcv max power correction variable: 0 ? use standard mpc coefficient 1 ? use mpcc bits for mpc coefficient by enabling mpc and setting mpcv = 1, the max power correction becomes variable. by adjusting the mpcc registers (address 0x4d-0x4e) it becomes possible to adjust the thd at maximum unclipped power to a lower value for a particular application. 3.8 configuration register h (address 07h) d7 d6 d5 d4 d3 d2 d1 d0 ecle res bcle ide zde sve zce res 0 1 1 1 1 1 1 0 3.8.1 zero-crossing volume enable bit r/w rst name description 1 r/w 1 zce zero-crossing volume enable: 1 ? volume adjustments will only occur at digital zero-crossings 0 ? volume adjustments will occur immediately the zce bit enables zero-crossing volume adjustments. when volume is adjusted on digital zero-crossings no clicks will be audible. 3.8.2 soft volume update enable bit r/w rst name description 2 r/w 1 sve soft volume enable: 1 ? volume adjustments will use soft volume 0 ? volume adjustments will occur immediately the DDX-8001 includes a soft volume algorithm that w ill step through the intermediate volume values at a predetermined rate when a volume change occurs. by setting sve=0 this can be bypassed and volume changes will jump from old to new value directly. 3.8.3 zero-detect mute enable bit r/w rst name description 3 r/w 1 zde zero-detect mute enable: setting of 1 enables the automatic zero-detect mute setting the zde bit enables the zero-detect automatic mute . when zde=1, the zero-detect circuit looks at the input data to each processing chan nel after the channel-mapping block. if any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted. 3.8.4 invalid input detect mute enable bit r/w rst name description 4 r/w 1 ide invalid input detect auto-mute enable: 0 ? disabled 1 ? enabled setting the ide bit enables this function, which looks at the input i 2 s data and clocking and will automatically mute all outputs if the signals are perceived as invalid.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 25 of 49 3.8.5 binary clock loss detection enable bit r/w rst name description 5 r/w 1 bcle binary output mode clock loss detection enable 0 ? disabled 1 ? enabled detects loss of input mclk in binary mode and will output 50% duty cycle to prevent audible artifacts when input clocking is lost. 3.8.6 auto-eapd on clock loss enable bit r/w rst name description 7 r/w 0 ecle auto eapd on clock loss 0 ? disabled 1 ? enabled when ecle is active, it issues a power device power down signal (eapd) on clock loss detection. 3.9 configuration register i (address 08h) d7 d6 d5 d4 d3 d2 d1 d0 eapd psce 0 0 3.9.1 pscorrect? enable bit r/w rst name description 0 r/w 0 psce power supply ripple correction enable: 0 ? normal operation 1 ? pscorrect? operation this feature utilizes an adc on sdi7 8 that provides power su pply ripple information for correction. registers psc1, psc2, psc3 are utilized in this mode. please refe r to pscorrect? application note for further details. 3.9.2 external amplifier power down bit r/w rst name description 7 r/w 0 eapd external amplifier power down: 0 ? external power stage power down active 1 ? normal operation eapd is used to actively power down a connected ddx ? power device. this register has to be written to 1 at start-up to enable the ddx ? power device for normal operation. 3.10 volume control 3.10.1 master controls 3.10.1.1 master mute register (address 09h) d7 d6 d5 d4 d3 d2 d1 d0 mmute 0 3.10.1.2 master volume register (address 0ah) d7 d6 d5 d4 d3 d2 d1 d0 mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 1 1 1 1 1 1 1 1 note : value of volume derived from mvol is dependent on amv automode volume settings.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 26 of 49 3.10.2 channel controls 3.10.2.1 channel 1 volume (address 0bh) d7 d6 d5 d4 d3 d2 d1 d0 c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 0 1 1 0 0 0 0 0 3.10.2.2 channel 2 volume (address 0ch) d7 d6 d5 d4 d3 d2 d1 d0 c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 0 1 1 0 0 0 0 0 3.10.2.3 channel 3 volume (address 0dh) d7 d6 d5 d4 d3 d2 d1 d0 c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 0 1 1 0 0 0 0 0 3.10.2.4 channel 4 volume (address 0eh) d7 d6 d5 d4 d3 d2 d1 d0 c4v7 c4v6 c4v5 c4v4 c4v3 c4v2 c4v1 c4v0 0 1 1 0 0 0 0 0 3.10.2.5 channel 5 volume (address 0fh) d7 d6 d5 d4 d3 d2 d1 d0 c5v7 c5v6 c5v5 c5v4 c5v3 c5v2 c5v1 c5v0 0 1 1 0 0 0 0 0 3.10.2.6 channel 6 volume (address 10h) d7 d6 d5 d4 d3 d2 d1 d0 c6v7 c6v6 c6v5 c6v4 c6v3 c6v2 c6v1 c6v0 0 1 1 0 0 0 0 0 3.10.2.7 channel 7 volume (address 11h) d7 d6 d5 d4 d3 d2 d1 d0 c7v7 c7v6 c7v5 c7v4 c7v3 c7v2 c7v1 c7v0 0 1 1 0 0 0 0 0 3.10.2.8 channel 8 volume (address 12h) d7 d6 d5 d4 d3 d2 d1 d0 c8v7 c8v6 c8v5 c8v4 c8v3 c8v2 c8v1 c8v0 0 1 1 0 0 0 0 0 3.10.2.9 channel 1 volume trim, mute, bypass (address 13h) d7 d6 d5 d4 d3 d2 d1 d0 c1m c1vbp c1vt4 c1vt3 c1vt2 c1vt1 c1vt0 0 0 0 1 0 0 0 0
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 27 of 49 3.10.2.10 channel 2 volume trim, mute, bypass (address 14h) d7 d6 d5 d4 d3 d2 d1 d0 c2m c2vbp c2vt4 c2vt3 c2vt2 c2vt1 c2vt0 0 0 0 1 0 0 0 0 3.10.2.11 channel 3 volume trim, mute, bypass (address 15h) d7 d6 d5 d4 d3 d2 d1 d0 c3m c3vbp c3vt4 c3vt3 c3vt2 c3vt1 c3vt0 0 0 0 1 0 0 0 0 3.10.2.12 channel 4 volume trim, mute, bypass (address 16h) d7 d6 d5 d4 d3 d2 d1 d0 c4m c4vbp c4vt4 c4vt3 c4vt2 c4vt1 c4vt0 0 0 0 1 0 0 0 0 3.10.2.13 channel 5 volume trim, mute, bypass (address 17h) d7 d6 d5 d4 d3 d2 d1 d0 c5m c5vbp c5vt4 c5vt3 c5vt2 c5vt1 c5vt0 0 0 0 1 0 0 0 0 3.10.2.14 channel 6 volume trim, mute, bypass (address 18h) d7 d6 d5 d4 d3 d2 d1 d0 c6m c6vbp c6vt4 c6vt3 c6vt2 c6vt1 c6vt0 0 0 0 1 0 0 0 0 3.10.2.15 channel 7 volume trim, mute, bypass (address 19h) d7 d6 d5 d4 d3 d2 d1 d0 c7m c7vbp c7vt4 c7vt3 c7vt2 c7vt1 c7vt0 0 0 0 1 0 0 0 0 3.10.2.16 channel 8 volume trim, mute, bypass (address 1ah) d7 d6 d5 d4 d3 d2 d1 d0 c8m c8vbp c8vt4 c8vt3 c8vt2 c8vt1 c8vt0 0 0 0 1 0 0 0 0 3.10.3 volume description the volume structure of the DDX-8001 consists of indivi dual volume registers for each channel, a master volume register, and individual channel volume trim registers. the channel volume settings are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels. these values are normally set at the initialization of the ic and not changed. the individual channel volumes are adjustable in 0.5db steps from +48db to -78 db. there is also an additi onal offset for each channel called the channel volume trim. the channel trim is normally controlled via the consumer for balancing the output of the channels in surround sound settings. the channel volume trim is adjustable independently on each channel from ?10db to +10db in 1 db steps. the master volume control is no rmally mapped to the master volume of the system. the values of these three settings are summed to find the actual gain/volume value for any given channel. as an example if c5v = 1eh or +33db, c5vt = 12h or ?2db , and mv = 2ah or ?21db, then the total gain for channel 5 = +10db. when set to 1, the master mute will mute all channels, whereas the individual channel mutes (cxm) will mute only that channel. both the master mute and the channel mutes provide a ?soft mute? with the volume ramping down to mute in 8192 samples from the maximum volume setting at the internal processing rate (~192khz). a ?hard
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 28 of 49 mute? can be obtained by commanding a value of all 1?s (ffh) to any channel volume register or the master volume register. when volume offsets are provided vi a the master volume regist er any channel whose total volume is less than ?100db will be muted. all changes in volume take place at zero-crossings when zce = 1 (configuration register h) on a per channel basis as this creates the smoothest possible volume transitions. when zce=0, volume updates will occur immediately. the DDX-8001 also features a soft-volume update function that will ramp the volume between intermediate values when the value is updated, when sve = 1 (configura tion register h). this fe ature can be disabled by setting sve = 0. each channel also contains an individual channel volume bypass. if a particular channel has volume bypassed via the cxvbp = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. each channel also contains a channel mute. if cxm = 1 a soft mute is performed on that channel. table 13 - master volume offset as a function of mv (7..0) mv (7..0) volume offset from channel value 00000000 (00h) 0db 00000001 (01h) -0.5db 00000010 (02h) -1db ? ? 01001100 (4ch) -38db ? ? 11111110 (feh) -127db 11111111 (ffh) hard master mute table 14 - channel volume as a function of cxv (7..0) cxv (7..0) volume 00000000 (00h) +48db 00000001 (01h) +47.5db 00000010 (02h) +47db ? ? 01100001 (5fh) +0.5db 01100000 (60h) 0db 01011111 (61h) -0.5db ? ? 11111110 (feh) -79.5 db 11111111 (ffh) hard channel mute
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 29 of 49 table 15 - channel volume trim as a function of cxvt (4..0) cxvt (4..0) volume 00000 (00h) +10db ? ? 00110 (06h) +10db 00111 (07h) +9db ? ? 01111 (0fh) +1db 10000 (10h) 0db 10001 (11h) -1db ? ? 11001 (19h) -9db 11010 (1ah) -10db ? ? 11111 (1fh) -10db 3.11 input mapping 3.11.1 channel input mapping channels 1 & 2 (address 1bh) d7 d6 d5 d4 d3 d2 d1 d0 c2im2 c2im1 c2im0 c1im2 c1im1 c1im0 0 0 1 0 0 0 3.11.2 channel input mapping channels 3 & 4 (address 1ch) d7 d6 d5 d4 d3 d2 d1 d0 c4im2 c4im1 c4im0 c3im2 c3im1 c3im0 0 1 1 0 1 0 3.11.3 channel input mapping channels 5 & 6 (address 1dh) d7 d6 d5 d4 d3 d2 d1 d0 c6im2 c6im1 c6im0 c5im2 c5im1 c5im0 1 0 1 1 0 0 3.11.4 channel input mapping channels 7 & 8 (address 1eh) d7 d6 d5 d4 d3 d2 d1 d0 c8im2 c8m1 c8im0 c7im2 c7im1 c7im0 1 1 1 1 1 0 each channel received via i 2 s can be mapped to any internal processing channel via the channel input mapping registers. this allows for flexibility in processing, si mplifies output stage designs, and enables crossovers to be performed. the default settings of these registers map each i 2 s input channel to its corresponding processing channel. table 16 - channel mapping as a function of cxim bits. cxim (2..0) serial input from 000 channel 1 001 channel 2 010 channel 3 011 channel 4 100 channel 5 101 channel 6 110 channel 7 111 channel 8 figure 18 - processing channel mux 8:1 mux channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 processing channel x cxim(2..0) 3
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 30 of 49 3.12 automode? registers prescale high- pas s filter biq uad #2 biqu ad #3 biq uad #4 biqu ad #5 biq uad #6 biqu ad #7 biq uad #8 bas s hard set to -18db when automode eq (ameq) hard set coeffecients when automode eq (ameq) har d s et coeffecients when automode bass management crossover (ambmxe) har d s et coeffecients when deemphasis enabled (demp) from mix#1 engine or previous channel biquad#10 output (cxblp) to mix#2 engine treble user progammable biquad #1 when high-pass bypassed (hpb) us er pr ogr ammable biquads #9 and #10 when tone bypassed (cxtcb) figure 19 - eq processing data path and automode usage 3.12.1 register ? automodes eq, volume, gc (address 1fh) d7 d6 d5 d4 d3 d2 d1 d0 amdm amgc2 amgc1 amgc0 amv1 amv0 ameq1 ameq0 0 0 0 0 0 0 0 0 table 17 - automode eq ameq (1,0) mode (biquad 2-6) 00 user programmable 01 preset eq ? peq bits 10 graphic eq ? xgeq bits 11 auto volume controlled loudness curve by setting ameq to any setting other than 00 enables automode eq. when set, biquads 1-5 are not user programmable. any coefficient settings for these biquad s will be ignored. also when automode eq is used the pre-scale value for channels 1-6 becomes hard-set to ?18db. table 18 - automode volume amv (1,0) mode (mvol) 00 mvol 0.5db 256 steps (standard) 01 mvol auto curve 30 steps 10 mvol auto curve 40 steps 11 mvol auto curve 50 steps table 19 - automode gain compression/limiters amgc (2..0) mode 000 user programmable gc 001 ac no clipping 010 ac limited clipping (10%) 011 drc nighttime listening mode 100 drc tv commercial/channel agc 101 ac 5.1 no clipping 110 ac 5.1 limited clipping (10%) amdm ? automode 5.1 downmix bit r/w rst name description 7 r/w 0 amdm 0 ? normal operation 1 ? channels 7-8 are 2 channel downmix of channels 1-6 the automode downmix setting uses channels 7-8 of mi x#1 engine and therefore these channels are hard-set and not allowed to be user set when in this mode.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 31 of 49 channels 1-6 must be arranged via channel mapping (cxi m) if necessary in the following manner for this operation: channel 1 ? left channel 2 ? right channel 3 ? left surround channel 4 ? right surround channel 5 ? center channel 6 ? lfe 3.12.2 register ? automodes bass management (address 20h) d7 d6 d5 d4 d3 d2 d1 d0 sub rss1 rss0 css1 css0 fss ambmxe ambmme 1 0 0 0 0 0 0 0 bit r/w rst name description 0 r/w 0 ambmme 0 ? automode bass management mix disabled 1 ? automode bass management mix enabled bit r/w rst name description 1 r/w 0 ambmxe 0 ? automode bass management crossover disabled 1 ? automode bass management crossover enabled setting the ambmme bit enables the proper mixing to take place for various preset bass management configurations. setting the ambmxe bit enables the proper cr ossover filtering in biquad #7 to take place. the crossover for bass management is always 2 nd order (12 db/octave) for the low-pass filter and 1 st order (6 db/octave) for the high-pass filter. the frequency of cros sover is determined by the xox bits in the preset eq register. all configurations of dolby bass-management can be perfo rmed in the ic. these different configurations are selected as they would be by the end-user on the basis of speake r size and/or on and off. the automode bass management settings utilize chann els 1-6 on the mix #1 engine, channels 1-6 biquad #6, and channels 1-2 on the mix#2 engine in c onfiguration #2. these functions cannot be user programmed while the bass management automode is active. not all settings are valid as some configurations are unlikely and do not have to be supported by dolby specification. automatic crossover settings are provided or custom crossovers can be implemented using the programmable biquads available. input channels must be mapped using the channel-mappi ng feature in the following manner for bass management to be performed properly. 1 ? left front 2 ? right front 3 ? left rear 4 ? right rear 5 ? center 6 ? lfe table 20 - center and rear speaker size selection register/setting 10 01 00 css ? center speaker size off large small rss ? rear speaker size off large small
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 32 of 49 table 21 - front and sub speaker selection register/setting 1 0 fss ? front speaker size large small sub ? subwoofer on off when ambmxe = 1, biquad #7 on channels 1-6 are utilized for bass-management crossover filter. this biquad is not user programmable in this mode. the xo settings det ermine the crossover frequency used. the crossover is 2 nd order for low-pass and 1 st order for high-pass with a ?3db cross po int. higher order filters can be obtained by programming coefficients in other biquads if desired. it is recommended to use settings of 120-160hz when using small, single driver satellite speakers, as the frequency response of these speakers is normally limited to this region. 3.12.3 register ? automode am/pre-scal e/bass management scale (address 21h) d7 d6 d5 d4 d3 d2 d1 d0 amam2 amam1 amam0 amame msa amps 0 0 0 0 0 1 bit r/w rst name description 0 r/w 1 amps automode pre-scale 1 ? -18db used for pre-scale when ameq /= 00 0 ? user defined pre-scale when ameq /= 00 bit r/w rst name description 1 r/w 0 msa bass management mix scale adjustment 0 ? -12db scaling on satellite channels in config #1 1 ? no scaling on satellite channels in config #1 bit r/w rst name description 4 r/w 0 amame automode am enable 0 ? switching frequency determined by pwms settings 1 ? switching frequency determined by amam settings table 22 - automode am switching frequency selection amam (2..0) 48khz/96khz input fs 44.1khz/88.2khz input fs 000 0.535mhz ? 0.720mhz 0.535mhz ? 0.670mhz 001 0.721mhz ? 0.900mhz 0.671mhz ? 0.800mhz 010 0.901mhz ? 1.100mhz 0.801mhz ? 1.000mhz 011 1.101mhz ? 1.300mhz 1.001mhz ? 1.180mhz 100 1.301mhz ? 1.480mhz 1.181mhz ? 1.340mhz 101 1.481mhz ? 1.600mhz 1.341mhz ? 1.500mhz 110 1.601mhz ? 1.700mhz 1.501mhz ? 1.700mhz when ddx ? is used concurrently with an am radio tuner, it is advisable to us e the amam bits to automatically adjust the output pwm switching rate dependent upon the spec ific radio frequency that the tuner is receiving. the values used in amam are also dependent upon the sample rate determined by the adc used. 3.12.4 register - preset eq settings (address 22h) d7 d6 d5 d4 d3 d2 d1 d0 xo2 xo1 xo0 peq4 peq3 peq2 peq1 peq0 1 0 1 0 0 0 0 0
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 33 of 49 table 23 - crossover frequency selection xo (2..0) bass management crossover frequency 000 70 hz 001 80 hz 010 90 hz 011 100 hz 100 110 hz 101 120 hz 110 140 hz 111 160 hz table 24 - preset eq selection peq (3..0) setting 00000 flat 00001 rock 00010 soft rock 00011 jazz 00100 classical 00101 dance 00110 pop 00111 soft 01000 hard 01001 party 01010 vocal 01011 hip-hop 01100 dialog 01101 bass-boost #1 01110 bass-boost #2 01111 bass-boost #3 10000 loudness 1 (least boost) 10001 loudness 2 10010 loudness 3 10011 loudness 4 10100 loudness 5 10101 loudness 6 10110 loudness 7 10111 loudness 8 11000 loudness 9 11001 loudness 10 11010 loudness 11 11011 loudness 12 11100 loudness 13 11101 loudness 14 11110 loudness 15 11111 loudness 16 (most boost) 3.12.5 graphic eq 3.12.5.1 register ? graphic eq 80hz band (address 23h) d7 d6 d5 d4 d3 d2 d1 d0 ageq4 ageq3 ageq2 ageq1 ageq0 0 1 1 1 1
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 34 of 49 3.12.5.2 register ? graphic eq 300hz band (address 24h) d7 d6 d5 d4 d3 d2 d1 d0 bgeq4 bgeq3 bgeq2 bgeq1 bgeq0 0 1 1 1 1 3.12.5.3 register ? graphic eq 1khz band (address 25h) d7 d6 d5 d4 d3 d2 d1 d0 cgeq4 cgeq3 cgeq2 cgeq1 cgeq0 0 1 1 1 1 3.12.5.4 register ? graphic eq 3khz band (address 26h) d7 d6 d5 d4 d3 d2 d1 d0 dgeq4 dgeq3 dgeq2 dgeq1 dgeq0 0 1 1 1 1 3.12.5.5 register ? graphic eq 8khz band (address 27h) d7 d6 d5 d4 d3 d2 d1 d0 egeq4 egeq3 egeq2 egeq1 egeq0 0 1 1 1 1 table 25 - graphic eq boost/cut selection xgeq (4..0) boost/cut 11111 +16 11110 +15 11101 +14 ? ? 10000 +1 01111 0 01110 -1 ? ? 00001 -14 00000 -15 3.13 processing loop modes 3.13.1 biquad internal channel loop-through (address 28h) d7 d6 d5 d4 d3 d2 d1 d0 c8blp c7blp c6blp c5blp c4blp c3blp c2blp c1blp 0 0 0 0 0 0 0 0 each internal processing channel can receive two possible inputs at the input to the biquad block. the input can be received either from the output of t hat channel?s mix#1 engine or from t he output of bass/treble (biquad#10) of the previous channel. in this scenario, channel 1 would receive channel 8. this enables the use of more than 10 biquads on any given channel at the loss of the nu mber of separate internal processing channels. cxblp: 0 ? input from channel x mix#1 engine output ? normal operation 1 ? input from channel x-1 bi quad #10 output ? loop operation 3.13.2 mix internal channel loop-through (address 29h) d7 d6 d5 d4 d3 d2 d1 d0 c8mxlp c7mxlp c6mxlp c5mxlp c4mxlp c3mxlp c2mxlp c1mxlp 0 0 0 0 0 0 0 0
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 35 of 49 each internal processing channel can receive two possible sets of inputs at the inputs to the mix#1 block. the inputs can be received from the outputs of the interpolation block as normally occurs (cxmxlp = 0) or the inputs can be received from the outputs of the mix#2 block. this enables the ability to perform additional filtering after the second mix block at the expense of losi ng this processing capability on the channel. cxmxlp: 0 ? inputs to channel x mix#1 engine from interpolation outputs ? normal operation 1 ? inputs from channel x mix#1 engine fr om mix#2 engine outputs ? loop operation 3.14 processing bypass modes 3.14.1 eq bypass (address 2ah) d7 d6 d5 d4 d3 d2 d1 d0 c8eqbp c7eqbp c6eqbp c5eqbp c4 eqcbp c3eqbp c2eqbp c1eqbp 0 0 0 0 0 0 0 0 eq control can be bypassed on a per channel basis. if eq control is bypassed on a gi ven channel the prescale and all 10 filters (high-pass, biquads, de-emphasis, bass management cross-ov er, bass, treble in any combination) are bypassed for that channel. cxeqbp: 0 ? perform eq on channel x ? normal operation 1 ? bypass eq on channel x 3.14.2 tone control bypass (address 2bh) d7 d6 d5 d4 d3 d2 d1 d0 c8tcb c7tcb c6tcb c5tcb c4tcb c3tcb c2tcb c1tcb 0 0 0 0 0 0 0 0 tone control (bass/treble) can be bypassed on a per channel basis. if tone control is bypassed on a given channel the two filters that tone control utilizes are made available as user programmable biquads #9 and #10. 3.15 tone control (address 2ch) d7 d6 d5 d4 d3 d2 d1 d0 ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 0 1 1 1 0 1 1 1 table 26 - tone control boost/cut selection btc (3..0)/ttc (3..0) boost/cut 0000 -12db 0001 -12db ? ? 0111 -4db 0110 -2db 0111 0db 1000 +2db 1001 +4db ? ? 1101 +12db 1110 +12db 1111 +12db
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 36 of 49 3.16 dynamics control 3.16.1 channel limiter select channels 1,2,3,4 (address 2dh) d7 d6 d5 d4 d3 d2 d1 d0 c4ls1 c4ls0 c3ls1 c3ls0 c2ls1 c2ls0 c1ls1 c1ls0 0 0 0 0 0 0 0 0 3.16.2 channel limiter select channels 5,6,7,8 (address 2eh) d7 d6 d5 d4 d3 d2 d1 d0 c8ls1 c8ls0 c7ls1 c7ls0 c6ls1 c6ls0 c5ls1 c5ls0 0 0 0 0 0 0 0 0 3.16.3 limiter 1 attack/release rate (address 2fh) d7 d6 d5 d4 d3 d2 d1 d0 l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 0 1 1 0 1 0 1 0 3.16.4 limiter 1 attack/release threshold (address 30h) d7 d6 d5 d4 d3 d2 d1 d0 l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 0 1 1 0 1 0 0 1 3.16.5 limiter 2 attack/release rate (address 31h) d7 d6 d5 d4 d3 d2 d1 d0 l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 0 1 1 0 1 0 1 0 3.16.6 limiter 2 attack/release threshold (address 32h) d7 d6 d5 d4 d3 d2 d1 d0 l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 0 1 1 0 1 0 0 1 3.16.7 dynamics control description the DDX-8001 includes 2 independent limiter blocks. the pu rpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from c lipping in anti-clipping mode, or to actively reduce the dynamic range for a better listening environment (such as a night-time listening mode, which is often needed for dvds.) the two modes are selected via the drc bit in configuration register f, bit 1 address 0x05. each channel can be mapped to limiter1, limiter2, or not mapped. if a channel is not mapped, that channel will clip normally when 0 db fs is exceeded. each limiter will l ook at the present value of each channel that is mapped to it, select the maximum absolute value of all these chann els, perform the limiting algorithm on that value, and then if needed adjust the gain of the mapped channels in unison. the limiter attack thresholds are determined by the lx at registers. when the attack thesehold has been exceeded, the limiter, when active, will automatically start reducing the gain. the rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. the gain reduction occurs on a peak-detect algorithm. the release of limiter, when the gain is again increased, is dependent on a rms-detect algorithm. the output of the volume/limiter block is passed through an rms filter. the output of this filter is compared to the release threshold, determined by the release threshold register . when the rms filter output falls below the release threshold, the gain is increased at a rate dependent upon the release rate register. the gain can never be increased past its set value and therefore the release will only occur if the limiter has alread y reduced the gain. the release threshold value can be used to set what is e ffectively a minimum dynamic range. this is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound ?lifeless?.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 37 of 49 in ac mode the attack and release thresholds are set rela tive to full-scale. in drc mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. gain attenuation saturation rms limiter gain/volume input output figure 20 - basic limiter and volume flow diagram. table 27 - channel limiter mapping selection cxls (1,0) channel limiter mapping 00 channel has limiting disabled 01 channel is mapped to limiter #1 10 channel is mapped to limiter #2 table 28 - limiter attack rate selection table 29 - limiter release rate selection lxa (3..0) attack rate db/ms lxr (3..0) release rate db/ms 0000 3.1584 fast 0000 0.5116 fast 0001 2.7072 0001 0.1370 0010 2.2560 0010 0.0744 0011 1.8048 0011 0.0499 0100 1.3536 0100 0.0360 0101 0.9024 0101 0.0299 0110 0.4512 0110 0.0264 0111 0.2256 0111 0.0208 1000 0.1504 1000 0.0198 1001 0.1123 1001 0.0172 1010 0.0902 1010 0.0147 1011 0.0752 1011 0.0137 1100 0.0645 1100 0.0134 1101 0.0564 1101 0.0117 1110 0.0501 1110 0.0110 1111 0.0451 slow 1111 0.0104 slow
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 38 of 49 anti-clipping mode table 30 - limiter attack threshold selection (ac-mode). table 31 - limiter release threshold selection (ac-mode). lxat (3..0) ac (db relative to fs) lxrt (3..0) ac (db relative to fs) 0000 -12 0000 - 0001 -10 0001 -29db 0010 -8 0010 -20db 0011 -6 0011 -16db 0100 -4 0100 -14db 0101 -2 0101 -12db 0110 0 0110 -10db 0111 +2 0111 -8db 1000 +3 1000 -7db 1001 +4 1001 -6db 1010 +5 1010 -5db 1011 +6 1011 -4db 1100 +7 1100 -3db 1101 +8 1101 -2db 1110 +9 1110 -1db 1111 +10 1111 -0db dynamic range compression mode table 32 - limiter attack threshold selection (drc-mode). table 33 - limiter release threshold selection (drc-mode). lxat (3..0) drc (db relative to volume) lxrt (3..0) drc (db relative to volume + lxat) 0000 -31 0000 - 0001 -29 0001 -38db 0010 -27 0010 -36db 0011 -25 0011 -33db 0100 -23 0100 -31db 0101 -21 0101 -30db 0110 -19 0110 -28db 0111 -17 0111 -26db 1000 -16 1000 -24db 1001 -15 1001 -22db 1010 -14 1010 -20db 1011 -13 1011 -18db 1100 -12 1100 -15db 1101 -10 1101 -12db 1110 -7 1110 -9db 1111 -4 1111 -6db 3.17 pwm output timing 3.17.1 channel 1&2 output timing (address 33h) d7 d6 d5 d4 d3 d2 d1 d0 c2ot2 c2ot1 c2ot0 c1ot2 c1ot1 c1ot0 1 0 0 0 0 0 3.17.2 channel 3&4 output timing (address 34h) d7 d6 d5 d4 d3 d2 d1 d0 c4ot2 c4ot1 c4ot0 c3ot2 c3ot1 c3ot0 1 1 0 0 1 0
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 39 of 49 3.17.3 channel 5&6 output timing (address 35h) d7 d6 d5 d4 d3 d2 d1 d0 c6ot2 c6ot1 c6ot0 c5ot2 c5ot1 c5ot0 1 0 1 0 0 1 3.17.4 channel 7&8 output timing (address 36h) d7 d6 d5 d4 d3 d2 d1 d0 c8ot2 c8ot1 c8ot0 c7ot2 c7ot1 c7ot0 1 1 1 0 1 1 the centering of the individual channel pwm output perio ds can be adjusted by the output timing registers. pwm slot settings can be chosen to insure that pulse transitions do not occur at the same time on different channels using the same power device. there are 8 po ssible settings, the appropriate setting varying based on the application and connections to the ddx ? power devices. table 34 - channel output timing selection. cxot (2..0) pwm slot 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 3.18 i 2 s output channel mapping 3.18.1 channel i 2 s output mapping channels 1 & 2 (address 37h) d7 d6 d5 d4 d3 d2 d1 d0 c2om2 c2om1 c2om0 c1om2 c1om1 c1om0 0 0 1 0 0 0 3.18.2 channel i 2 s output mapping channels 3 & 4 (address 38h) d7 d6 d5 d4 d3 d2 d1 d0 c4om2 c4om1 c4om0 c3om2 c3om1 c3om0 0 1 1 0 1 0 3.18.3 channel i 2 s output mapping channels 5 & 6 (address 39h) d7 d6 d5 d4 d3 d2 d1 d0 c6om2 c6om1 c6om0 c5om2 c5om1 c5om0 1 0 1 1 0 0 3.18.4 channel i 2 s output mapping channels 7 & 8 (address 3ah) d7 d6 d5 d4 d3 d2 d1 d0 c8om2 c8m1 c8om0 c7om2 c7om1 c7om0 1 1 1 1 1 0 each i 2 s output channel can receive data from any channel output of the volume block. which channel a particular i 2 s output receives is dependent upon that channel?s cxom register bits.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 40 of 49 table 35 - channel i 2 s output mapping cxom (2..0) serial output from 000 channel 1 001 channel 2 010 channel 3 011 channel 4 100 channel 5 101 channel 6 110 channel 7 111 channel 8 4.0 user programmable processing 4.1 eq ? biquad equation the biquads use the equation that follows. this is diagrammed in figure 21 below. y[n] = 2(b 0 /2)x[n] + 2(b 1 /2)x[n-1] + b 2 x[n-2] ? 2(a 1 /2)y[n-1] ? a 2 y[n-2] = b 0 x[n] + b 1 x[n-1] + b 2 x[n-2] ? a 1 y[n-1] ? a 2 y[n-2] where y[n] represents the output and x[n] represents the inpu t. multipliers are 28-bit signed fractional multipliers, with coefficient values in the range of 800000h (-1) to 7fffffh (0.9999998808). coefficients stored in the user defined coeffici ent ram are referenced in the following manner: cxhy0 = b 1 /2 cxhy1 = b 2 cxhy2 = -a 1 /2 cxhy3 = -a 2 cxhy4 = b 0 /2 the x represents the channel and the y the biquad number. for example c3h41 is the b 0 /2 coefficient in the fourth biquad for channel 3 figure 21 - biquad filter 4.2 pre-scale the pre-scale block which precedes the first biquad is used for attenuation when filt ers are designed that boost frequencies above 0dbfs. this is a single 28-bit signed multiplier, with 800000h = -1 and 7fffffh = 0.9999998808. by default, all pr e-scale factors are set to 800000h. + + + 2 2 -a 2 -a 1 /2 b 2 b 1 /2 b 0 /2 z - 1 z - 1 z - 1 z - 1 2 input output
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 41 of 49 note that the default pre-scale value inverts the signal phase. this should be understood when the output is taken from the i 2 s output interface. 4.3 post-scale the DDX-8001 provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. this is a 24-bit signed fractional multiplier. the scale factor for this multiplier is loaded into ram using the same i 2 c registers as the biquad coefficients and the bass- management. all channels can use the same settings as channel 1 by setting the post-scale link bit. 4.4 mixing the DDX-8001 provides two mixing blocks per channel, one located before the eq section and the other located after. each mix block has 8 mixing coefficients, which are each 24-bit signed fractional multipliers, that correspond to the 8 channels of input to the mixing block. these coefficients are accessible via the user controlled coefficient ram described below. 4.5 calculating 24-bit signed fractional numbers from a db value the pre-scale, mixing, and post-scale functions of t he DDX-8001 use 24-bit signed fractional multipliers to attenuate signals. these attenuations can also invert the ph ase and therefore range in value from ?1 to +1. it is possible to calculate the coefficient to utilize for a give n negative db value (attenuation) via the equations below. non-inverting phase numbers 0 to +1 : coefficient = round(8388607 * 10^(db/20)) inverting phase numbers 0 to ?1 : coefficient = 16777216 - round(8388607 * 10^(db/20)) as can be seen by the preceding equations, the value for positive phase 0db is 0x7fffff and the value for negative phase 0db is 0x800000. channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 cxmix1 cxmix2 cxmix3 cxmix4 cxmix5 cxmix6 cxmix7 cxmix8 channel x figure 22 - mix block diagram
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 42 of 49 4.6 user defined coefficient ram 4.6.1 coefficient address register 1 (address 3bh) d7 d6 d5 d4 d3 d2 d1 d0 cfa9 cfa8 0 0 4.6.2 coefficient address register 2 (address 3ch) d7 d6 d5 d4 d3 d2 d1 d0 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 0 0 0 0 0 0 0 0 4.6.3 coefficient b1data regist er bits 23..16 (address 3dh) d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 0 0 0 0 0 0 0 0 4.6.4 coefficient b1data regist er bits 15..8 (address 3eh) d7 d6 d5 d4 d3 d2 d1 d0 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 0 0 0 0 0 0 0 0 4.6.5 coefficient b1data register bits 7..0 (address 3fh) d7 d6 d5 d4 d3 d2 d1 d0 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 0 0 0 0 0 0 0 0 4.6.6 coefficient b2 data register bits 23..16 (address 40h) d7 d6 d5 d4 d3 d2 d1 d0 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 0 0 0 0 0 0 0 0 4.6.7 coefficient b2 data register bits 15..8 (address 41h) d7 d6 d5 d4 d3 d2 d1 d0 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 0 0 0 0 0 0 0 0 4.6.8 coefficient b2 data register bits 7..0 (address 42h) d7 d6 d5 d4 d3 d2 d1 d0 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 0 0 0 0 0 0 0 0 4.6.9 coefficient a1 data register bits 23..16 (address 43h) d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 0 0 0 0 0 0 0 0 4.6.10 coefficient a1 data register bits 15..8 (address 44h) d7 d6 d5 d4 d3 d2 d1 d0 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 0 0 0 0 0 0 0 0 4.6.11 coefficient a1 data register bits 7..0 (address 45h) d7 d6 d5 d4 d3 d2 d1 d0 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 0 0 0 0 0 0 0 0
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 43 of 49 4.6.12 coefficient a2 data register bits 23..16 (address 46h) d7 d6 d5 d4 d3 d2 d1 d0 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 0 0 0 0 0 0 0 0 4.6.13 coefficient a2 data register bits 15..8 (address 47h) d7 d6 d5 d4 d3 d2 d1 d0 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 0 0 0 0 0 0 0 0 4.6.14 coefficient a2 data register bits 7..0 (address 48h) d7 d6 d5 d4 d3 d2 d1 d0 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 0 0 0 0 0 0 0 0 4.6.15 coefficient b0 data register bits 23..16 (address 49h) d7 d6 d5 d4 d3 d2 d1 d0 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 0 0 0 0 0 0 0 0 4.6.16 coefficient b0 data register bits 15..8 (address 4ah) d7 d6 d5 d4 d3 d2 d1 d0 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 0 0 0 0 0 0 0 0 4.6.17 coefficient b0 data register bits 7..0 (address 4bh) d7 d6 d5 d4 d3 d2 d1 d0 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 0 0 0 0 0 0 0 0 4.6.18 coefficient write control register (address 4ch) d7 d6 d5 d4 d3 d2 d1 d0 wa w1 0 0 coefficients for eq and bass management are handled inter nally in the DDX-8001 via ram. access to this ram is available to the user via an i 2 c register interface. a collection of i 2 c registers are dedicated to this function. two registers contain a coefficient base address, five se ts of three registers stor e the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write of the coefficient (s) to ram. the following are instructions for reading and writing coefficients. reading a coefficient from ram ? write top 2-bits of address to i 2 c register 3bh ? write bottom 8-bits of address to i 2 c register 3ch ? read top 8-bits of coefficient in i 2 c address 3dh ? read middle 8-bits of coefficient in i 2 c address 3eh ? read bottom 8-bits of coefficient in i 2 c address 3fh reading a set of coefficients from ram ? write top 2-bits of address to i 2 c register 3bh ? write bottom 8-bits of address to i 2 c register 3ch ? read top 8-bits of coefficient in i 2 c address 3dh ? read middle 8-bits of coefficient in i 2 c address 3eh ? read bottom 8-bits of coefficient in i 2 c address 3fh ? read top 8-bits of coefficient b2 in i 2 c address 40h ? read middle 8-bits of coefficient b2 in i 2 c address 41h
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 44 of 49 ? read bottom 8-bits of coefficient b2 in i 2 c address 42h ? read top 8-bits of coefficient a1 in i 2 c address 43h ? read middle 8-bits of coefficient a1 in i 2 c address 44h ? read bottom 8-bits of coefficient a1 in i 2 c address 45h ? read top 8-bits of coefficient a2 in i 2 c address 46h ? read middle 8-bits of coefficient a2 in i 2 c address 47h ? read bottom 8-bits of coefficient a2 in i 2 c address 48h ? read top 8-bits of coefficient b0 in i 2 c address 49h ? read middle 8-bits of coefficient b0 in i 2 c address 4ah ? read bottom 8-bits of coefficient b0 in i 2 c address 4bh writing a single coefficient to ram ? write top 2-bits of address to i 2 c register 3bh ? write bottom 8-bits of address to i 2 c register 3ch ? write top 8-bits of coefficient in i 2 c address 3dh ? write middle 8-bits of coefficient in i 2 c address 3eh ? write bottom 8-bits of coefficient in i 2 c address 3fh ? write 1 to w1 bit in i 2 c address 4ch writing a set of coefficients to ram ? write top 2-bits of starting address to i 2 c register 3bh ? write bottom 8-bits of starting address to i 2 c register 3ch ? write top 8-bits of coefficient b1 in i 2 c address 3dh ? write middle 8-bits of coefficient b1 in i 2 c address 3eh ? write bottom 8-bits of coefficient b1 in i 2 c address 3fh ? write top 8-bits of coefficient b2 in i 2 c address 40h ? write middle 8-bits of coefficient b2 in i 2 c address 41h ? write bottom 8-bits of coefficient b2 in i 2 c address 42h ? write top 8-bits of coefficient a1 in i 2 c address 43h ? write middle 8-bits of coefficient a1 in i 2 c address 44h ? write bottom 8-bits of coefficient a1 in i 2 c address 45h ? write top 8-bits of coefficient a2 in i 2 c address 46h ? write middle 8-bits of coefficient a2 in i 2 c address 47h ? write bottom 8-bits of coefficient a2 in i 2 c address 48h ? write top 8-bits of coefficient b0 in i 2 c address 49h ? write middle 8-bits of coefficient b0 in i 2 c address 4ah ? write bottom 8-bits of coefficient b0 in i 2 c address 4bh ? write 1 to wa bit in i 2 c address 4ch the mechanism for writing a set of coefficients to ram provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acou stic side-effects. when using this technique, the 10-bit address would specify t he address of the biquad b1 coefficient (e.g. 0, 5, 10, 15, ?, 100, ? 395 decimal), and the DDX-8001 will generate the ram addresses as offsets from this base value to write the complete set of coefficient data.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 45 of 49 table 36 - ram block for biquads, mixing, and scaling index (decimal) index (hex) coefficient default 0 00h c1h10 (b1/2) 000000h 1 01h c1h11 (b2) 000000h 2 02h c1h12 (a1/2) 000000h 3 03h c1h13 (a2) 000000h 4 04h channel 1 ? biquad 1 c1h14 (b0/2) 400000h 5 05h channel 1 ? biquad 2 c1h20 000000h ? ? ? ? ? 49 31h channel 1 ? biquad 10 c1ha4 400000h 50 32h c2h10 000000h 51 33h channel 2 ? biquad 1 c2h11 000000h ? ? ? ? ? 99 63h channel 2 ? biquad 10 c2ha4 400000h 100 64h channel 3 ? biquad 1 c3h10 000000h ? ? ? ? ? 399 18fh channel 8 ? biquad 10 c8ha4 400000h 400 190h channel 1 ? pre- scale c1pres 7fffffh 401 191h channel 2 ? pre- scale c2pres 7fffffh 402 192h channel 3 ? pre- scale c3pres 7fffffh ? ? ? ? ? 407 197h channel 8 ? pre- scale c8pres 7fffffh 408 198h channel 1 ? post -scale c1psts 7fffffh 409 199h channel 2 ? post -scale c2psts 7fffffh ? ? ? ? ? 415 19fh channel 8 ? post -scale c8psts 7fffffh 416 1a0h channel 1 ? mi x#1 1 c1mx11 7fffffh 417 1a1h channel 1 ? mix#1 2 c1mx12 000000h ? ? ? ? ? 423 1a7h channel 1 ? mix#1 8 c1mx18 000000h 424 1a8h channel 2 ? mix#1 1 c2mx11 000000h 425 1a9h channel 2 ? mi x#1 2 c2mx12 7fffffh ? ? ? ? ? 479 1dfh channel 8 ? mi x#1 8 c8mx18 7fffffh 480 1e0h channel 1 ? mi x#2 1 c1mx21 7fffffh 481 1e1h channel 1 ? mix#2 2 c1mx22 000000h ? ? ? ? ? 487 1e7h channel 1 ? mix#2 8 c1mx28 000000h 488 1e8h channel 2 ? mix#2 1 c2mx21 000000h 489 1e9h channel 2 ? mi x#2 2 c2mx22 7fffffh ? ? ? ? ? 543 21fh channel 8 ? mi x#2 8 c8mx28 7fffffh variable max power correction (address 4dh-4eh): mpcc bits determine the 16 msbs of the mpc compensation co efficient. this coefficient is used in place of the default coefficient when mpcv = 1. d7 d6 d5 d4 d3 d2 d1 d0 mpcc15 mpcc14 mpcc 13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 0 0 1 0 1 1 0 1 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 1 1 0 0 0 0 0 0
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 46 of 49 pscorrect? (address 51h-53h): an adc is used to input ripple data to sdi78. the left channel (7) is used internally. no audio data can therefore be input on these channels (7 and 8). though all channel mapping and mixing from other inputs to channels 7 and 8 internally are still valid. ripple correction value ? rcv correction normalization value ? cnv d7 d6 d5 d4 d3 d2 d1 d0 rcv11 rcv10 rcv9 rcv8 rcv7 rcv6 rcv5 rcv4 0 0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 rcv3 rcv2 rcv1 rcv0 cnv11 cnv10 cnv9 cnv8 0 0 0 0 1 1 1 1 d7 d6 d5 d4 d3 d2 d1 d0 cnv7 cnv6 cnv5 cnv4 cnv3 cnv2 cnv1 cnv0 1 1 1 1 1 1 1 1
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 47 of 49 5.0 design information schematic diagram sdata3 out7a out7b out8a out8b clkout sdo_12 sdo_78 sdo_56 sdo_34 bick lrck vdda gnda lrck l1 600 ohm@100mhz 1 2 c6 100nf y5v r1 3.9k c8 100nf y5v c5 100nf y5v l2 600 ohm@100mhz 1 2 c11 100nf y5v c12 100nf y5v c2 100nf y5v c1 100nf y5v c7 100nf y5v + c9 22uf 6.3vdc + c3 2.2uf 6.3vdc r2 3.9k c4 100nf y5v c13 1200pf x7r c10 220pf npo r3 3.40k bick sdata2 sdata0 scl reset sdata1 out6b out6a mclk out5b out5a out3a out4b out4a out2b out2a out3b out1b out1a pwrdwn eapd +3.3v sda +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v u1 DDX-8001 vdd3.3_1 3 sdi_12/dsd_3 9 sdi_34/dsd_4 8 gnd_2 13 reset 15 sdi_56/dsd_5 7 sda 18 scl 19 sa 17 mvo/dsd_clk 1 vdd3.3_3 28 xti 20 gnd_3 27 nc 22 pll_bypass 16 pll_filter 21 gnda_pll 23 gnd_5 45 nc 46 out2_b 47 out2_a 48 out1_b 49 out1_a 50 gnd_7 60 nc 61 eapd 51 lrcko 56 sdo_12 57 sdo_34 58 sdo_56 62 bicko 55 gnd_6 53 vdd3.3_6 52 ckout 25 pwdn 64 sdi_78/dsd_6 6 bicki/dsd_1 11 lrcki/dsd_2 10 vdd3.3_2 12 nc 14 nc 26 nc 37 nc 54 sdo_78 63 vdd3.3_7 59 out3_a 43 out3_b 42 out4_a 41 out4_b 40 out5_a 39 out5_b 38 out6_a 34 out6_b 33 out7_a 32 out7_b 31 out8_a 30 out8_b 29 vdd3.3_5 44 test_mode 2 gnd_1 4 nc 5 vdd3.3_4 35 gnd_4 36 vdda3.3_pll 24 figure 23 - schematic diagram.
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 48 of 49 6.0 package information 6.1 package outline drawing
DDX-8001 specifications are subject to change without notice. 129 morgan drive, norwood, ma 02062 voice: (781) 551-9450 fax: (781) 440-9528 ema il: apogee@apogeeddx.com controlled document: p_903-000040_rev19 DDX-8001 data sheet.doc drn: preliminary page 49 of 49 6.2 marking configuration packages with date code (yww) = 514 & after legend: pplllwx traceability coding coo country of origin y assembly year ww assembly week pb-free (rohs compliant) (no symbol if not pb-free) information furnished in this publication is believed to be accu rate and reliable. however, apogee technology, inc. assumes no responsibility for its use, or for any infringements of patents or other rights of third parties that may result from its use. not intended f or medical and/or life support equipment? customers responsible fo r their own applications of apogee components? specifications in this publication a re subject to change without notice. this public ation supersedes and replaces all in formation previous supplied. ? apogee technology, inc. all rights reserved

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