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advisory march 1999 ambassador tm t8100 h.100/h.110 interface and time-slot interchanger this advisory details two changes to the ambassador tm t8100 h.100/h.110 interface and time-slot interchanger preliminary data sheet: ds98-195ntnb. change affecting page 15, section 2.1.3 address mode register problem: there is a minor bug in the t8100. if a write is issued to the address mode register (amr) address 0x70 (local bus, holding registers, and reset), the t8100s rdy line gets stuck low (not ready state). workaround: to solve this, issue another write command to any of the four direct registers (mcr, lar, amr, or idr) and the rdy signal will reset. change affecting page 38, section 2.4.2 dividers and rate multipliers there is an anomaly in the digital phase-lock loop (dpll) performance of the device. the behavior affects all versions of the t8100 but has been corrected in the t8100a, t8102, and t8105. this anomaly affects applica- tions that use the dpll for ct bus clock generation. when used for clocking, the dpll uses the 16.384 mhz internal oscillator to rate multiply an 8 khz input sig- nal. in order for the dpll to lock to the 8.000000 khz signal, the required internal oscillator frequency range should be centered at 16.388 mhz. a frequency of 16.384 mhz is too low for the dpll to perform properly. if this crystal adaptation is used for the dpll, there are several limitations. first, do not select the crystal as a fallback clock source. when the crystal is a clock source, the generated clocks are all multiples of the crystal. in that case, they will be offset by the same ratio as the crystal. second, do not use tclkout. it is also derived from the crystal and will be offset by the same ratio. third, the watchdogs will be slightly more sensitive due to the increased clock frequency. in designs affected by these limitations, conversion to the t8100a is recom- mended.
l u cent t echn o logies i n c. re s e r v es t h e r i g ht t o ma k e chan g es to t he p r oduct ( s) o r in f o r m ation c o ntain e d he r ein with o ut no t i c e . n o liability i s assum e d as a res u l t of t h eir us e or applicatio n . no rights u nde r a n y pa t ent acc o mpa n y the s a l e of a n y such p r oduct ( s) o r in f o r m a tion. ambassador is a trademark of lucent technologies inc. co p yright ? 199 9 luce n t t ec h nologie s inc. all rights res e r v ed ma r ch 19 9 9 a y 99-019ntnb ( r ep l a c es a y 99-011ntnb and must ac c ompa n y d s 98-195ntnb) f o r a d d i ti o n a l i n fo r m a t i o n , c o n ta c t y o u r m i c r o e l e c t r o n i c s g r o u p a cc o u n t m a n a ge r o r t h e f o l l o wi n g: i n terne t : http://ww w . lucent.com/mic r o e-m a il: do c m a ste r @mi c r o .lu c ent. c om n. a m erica : microelectronics grou p , lucent t echnologies i nc., 555 union boul e v ard, room 30l-15 p -ba, allent o wn , p a 18103 1 - 80 0 - 37 2 - 2 4 4 7 , f a x 6 10 -7 1 2 - 4 1 06 ( i n c an a d a: 1 - 8 0 0 - 5 5 3 - 2 44 8 , f a x 6 1 0 - 71 2 - 4 1 06) asia p a cif i c : microelectronics grou p , lucent t echnologies singapore pt e . l t d. , 77 s cience p a r k d r i v e , #03-18 cintech iii , singa p o r e 1 1 82 5 6 t el. ( 65 ) 7 7 8 8 8 33 , f a x ( 6 5 ) 7 7 7 74 9 5 c h i n a: m i c r o e l e c t r o n i cs g r o u p , l u c e n t t e c hn o l o g i e s ( c h i na ) c o ., lt d ., a- f2 , 2 3 / f , za o f o n g u n i v e r s e b u i l d i n g , 18 0 0 zho n g s h a n x i r o a d , s h a ng h a i 2 00 2 3 3 p . r. c h i na t el. ( 86 ) 21 64 4 0 0 4 6 8 , ext . 316 , f a x ( 86 ) 21 64 4 0 0 6 5 2 j a p a n: m i c r o e l e c t r o n i cs g r o u p , l u c e n t t e c h n o l og i e s j ap a n l t d ., 7 - 1 8 , h i ga s h i - g o ta n d a 2 -c h o m e , s h i n a g a w a - k u , t o k y o 1 4 1, j a p an t el. ( 81 ) 3 5 42 1 1 6 0 0 , f a x ( 8 1 ) 3 5 4 2 1 17 0 0 e u r o p e : d at a r e qu e s t s : m ic r o e l e c t r o n ic s g r ou p d a t a li n e : t e l. ( 4 4 ) 1 18 9 3 2 4 29 9 , f a x ( 4 4 ) 1 1 8 9 3 2 8 148 t e c h n i cal i n q u i r i e s : ge r ma n y : ( 4 9 ) 8 9 9 50 8 6 0 (m u n i c h ) , u n i t e d ki n gdo m : ( 4 4 ) 1 3 44 86 5 9 0 0 (ascot), f r a n ce : ( 3 3 ) 1 4 0 8 3 6 8 0 0 (p a r i s), s we d e n : ( 4 6) 8 5 9 4 6 07 00 (sto c k h o l m) , fi n land : ( 3 5 8 ) 9 4 3 54 28 0 0 (h e ls i n k i), i t a l y : ( 3 9 ) 0 2 6 6 0 8 13 1 (m i l a n), s p ai n : ( 3 4 ) 1 8 0 7 1 4 4 1 (mad r id)
preliminary data sheet august 1998 ambassador tm t8100 h.100/h.110 interface and time-slot interchanger 1 product overview 1.1 introduction increasingly, enhanced telephony services are pro- vided by equipment based on mass-market com- puter-telephony architectures. the h.100 time- division multiplexed (tdm) bus has emerged as the industry standard used in these systems. the ambassador t8100 is a single device that provides a complete interface for h.100/h.110-based systems. the t8100 will support the newer bus standards, h- mvip * and ectf h.100, but remain downward compatible with mvip -90 and dialogic s ? sc-bus. data can be buffered in either minimum delay or con- stant delay modes on a connection-by-connection basis. the t8100 will take advantage of new technology: it is based on 0.35 micron feature sizes and a robust standard-cell library. it utilizes associative memory (content addressable memories [cam]) in addition to traditional static ram and register file structures for the connection and data memories. the t8100 oper- ates on a single 3.3 v supply, but all inputs are 5 v tolerant and standard ttl output levels are main- tained. 1.2 features n complete solution for interfacing board-level cir- cuitry to the h.100 telephony bus n h.100 compliant interface; all mandatory signals n programmable connections to any of the 4096 time slots on the h.100 bus n up to 16 local serial inputs and 16 local serial outputs, programmable for 2.048 mbits/s, 4.096 mbits/s, and 8.192 mbits/s operation per chi specifications n programmable switching between local time slots, up to 1024 connections n programmable switching between local time slots and h.100 bus, up to 256 connections n choice of frame integrity or minimum latency switching on a per-time-slot basis frame integrity to ensure proper switching of wideband data minimum latency switching to reduce delay in voice channels n on-chip phase-locked loop (pll) for h.100, mvip , or sc-bus clock operation in master or slave clock modes n serial tdm bus rate and format conversion between most standard buses n optional 8-bit parallel input and/or 8-bit parallel output for local tdm interfaces n high-performance microprocessor interface provides access to device configuration regis- ters and to time-slot data supports both motorola ? nonmultiplexed and intel multiplexed/nonmultiplexed modes n two independently programmable groups of up to 12 framing signals each n 3.3 v supply with 5 v tolerant inputs and ttl-com- patible outputs n boundary-scan testing support n 208-pin, plastic sqfp package n 217-pin bga package (industrial temperature range) * mvip is a registered trademark of go-mvip, inc. ? dialogic is a registered trademark of dialogic corporation. ? motorola is a registered trademark of motorola, inc. intel is a registered trademark of intel corporation.
2 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 table of contents contents page 1 product overview .....................................................1 1.1 introduction ........................................................1 1.2 features .............................................................1 1.3 pin information ...................................................5 1.4 enhanced local stream addressing ................10 1.5 full h.100 stream address support ................10 1.6 onboard plls and clock monitors ..................11 1.7 phase alignment of referenced and generated frames ...........................................11 1.8 interfaces .........................................................11 1.8.1 microprocessors ..........................................11 1.8.2 framing groups ..........................................11 1.8.3 general-purpose register and i/o..............11 1.9 applications ......................................................11 1.10 application overview .....................................11 2 architecture and functional description.................12 2.1 register/memory maps ....................................14 2.1.1 main registers ............................................14 2.1.2 master control and status register ............14 2.1.3 address mode register...............................15 2.1.4 control register memory space .................16 2.2 local bus section ............................................21 2.2.1 constant frame delay and minimum delay connections ......................................22 2.2.2 serial and parallel .......................................23 2.2.3 data rates and time-slot allocation ..........23 2.2.4 lbs: local stream control, 0x0c ...............27 2.2.5 state counter operation .............................28 2.3 h-bus section ..................................................29 2.3.1 memory architecture ...................................29 2.3.2 cam operation and commands .................31 2.3.3 h-bus access..............................................35 2.3.4 l-bus access ..............................................36 2.3.5 h-bus rate selection and connection address format...........................................36 2.4 clocking section ..............................................36 2.4.1 clock and netref selection .....................38 2.4.2 dividers and rate multipliers.......................38 2.4.3 state machines ...........................................39 2.4.4 bit sliding (frame locking) .........................39 2.4.5 clock fallback .............................................39 2.4.6 clock control register definitions...............41 2.4.7 ckmd, cknd, ckrd: clocks, main, netref, resource dividers, 0x07, 0x08, and 0x09 .....................................................46 2.5 interface section ..............................................46 2.5.1 microprocessor interface.............................46 2.5.2 general-purpose register...........................47 2.5.3 framing groups ..........................................47 2.6 error registers .................................................50 2.7 the jtag test access port ............................51 2.7.1 overview of the jtag architecture .............51 2.7.2 overview of the jtag instructions..............51 contents page 2.7.3 elements of jtag logic............................. 52 2.8 testing and diagnostics .................................. 53 2.8.1 testing operations ..................................... 53 2.8.2 diagnostics................................................. 53 3 using the t8100 .................................................... 55 3.1 resets ............................................................. 55 3.1.1 hardware reset ......................................... 55 3.1.2 software reset........................................... 55 3.1.3 power-on reset......................................... 55 3.2 basic connections .......................................... 55 3.2.1 physical connections for h.110 ................. 56 3.2.2 h.100 data pin series termination............ 56 3.2.3 pc board considerations........................... 56 3.3 using the lar, amr, and idr for connections .................................................... 57 3.3.1 setting up local connections .................... 57 3.3.2 setting up h-bus connections................... 59 3.3.3 programming examples ............................. 62 3.2.4 miscellaneous commands ......................... 65 4 electrical characteristics ....................................... 66 4.1 absolute maximum ratings ............................ 66 4.2 handling precautions ...................................... 66 4.3 crystal oscillator ............................................. 67 4.4 dc electrical characteristics, h-bus (ectf h.100 spec., rev. 1.0) ........................ 67 4.4.1 electrical drive specificationsct_c8 and /ct_frame ........................................ 67 4.5 dc electrical characteristics, all other pins .... 68 4.6 h-bus timing (extract from h.100 spec., rev. 1.0) .............................................. 69 4.6.1 clock alignment ........................................ 69 4.6.2 frame diagram .......................................... 70 4.6.3 detailed timing diagram............................ 71 4.6.4 ac electrical characteristics, timing, h-bus (h.100, spec., rev. 1.0).................. 72 4.6.5 detailed clock skew diagram.................... 73 4.3.6 ac electrical characteristics, skew timing, h-bus (h.100, spec., rev. 1.0) ..... 73 4.6.7 reset and power on .................................. 73 4.7 ac electrical characteristics, local streams, and frames ...................................... 74 4.8 ac electrical characteristics, micro- processor timing ............................................. 75 4.8.1 microprocessor access intel multiplexed write and read cycles............................... 75 4.8.2 microprocessor access motorola write and read cycles ........................................ 76 4.8.3 microprocessor access intel demultiplexed write cycle ................................................. 77
preliminary data sheet august 1998 lucent technologies inc. 3 h.100/h.110 interface and time-slot interchanger ambassador t8100 table of contents (continued) contents page 5 outline diagram......................................................78 5.1 208-pin square quad flat package (sqfp) ...78 5.2 217-pin ball grid array (pbga) ......................79 6 ordering information...............................................79 appendix a. application of clock modes...................80 appendix b. minimum delay and constant delay connections ...........................................86 b.1 connection definitions .....................................86 b.2 delay type definitions ....................................87 b.2.1 exceptions to minimum delay.....................88 b.2.2 lower stream rates ...................................88 b.2.3 mixed minimum/constant delay .................89 figures page figure 1. pin diagram .................................................5 figure 2. 217 pbgatop view .................................6 figure 3. block diagram of the t8100 ......................13 figure 4. local bus section function .......................21 figure 5. local bus memory connection modes ......22 figure 6. local streams, memory structure .............24 figure 7. local memory, fill patterns .......................25 figure 8. simplified local memory state timing, 65.536 mhz clock ...................................28 figure 9. cam architecture ......................................30 figure 10. simplified h-bus state timing, 65.536 mhz clock ...................................32 figure 11. illustration of cam cycles .......................34 figure 12. clocking section ......................................37 figure 13. a, b, and c clock fallback state diagram ..................................................40 figure 14. frame group output options ..................49 figure 15. external connection to plls ...................55 figure 16. physical connections for h.110 ..............56 figure 17. local-to-local connection programming ..........................................58 figure 18. cam programming, h-bus-to-local connection ..............................................60 figure 19. clock alignment ......................................69 figure 20. frame diagram .......................................70 figure 21. detailed timing diagram .........................71 figure 22. detailed clock skew diagram .................73 figure 23. ac electrical characteristics, local streams, and frames .............................74 figures page figure 24. microprocessor access intel multi- plexed write cycle ................................. 75 figure 25. microprocessor access intel multi- plexed read cycle ................................. 75 figure 26. microprocessor access motorola write cycle ............................................. 76 figure 27. microprocessor access motorola read cycle ............................................ 76 figure 28. microprocessor access intel demultiplexed write cycle ..................... 77 figure 29. microprocessor access intel demultiplexed read cycle ..................... 77 figure 30. e1, ct bus master, compatibility clock master, clock source = 2.048 mhz from trunk .............................................. 81 figure 31. t1, ct bus master, compatibility clock master, clock source = 1.544 mhz from trunk .............................................. 82 figure 32. e1, slave to ct bus, clock source is either a 16 mhz or a 4 mhz or a 2 mhz and frame, netref source = 2.048 mhz from trunk ............ 83 figure 33. t1, slave to ct bus, clock source is either a 16 mhz or a 4 mhz or a 2 mhz and frame, netref source = 1.544 mhz from trunk ........................ 84 figure 34. constant delay connections, con[1:0] = 0x ........................................ 87 figure 35. minimum delay connections, con[1:0] = 0x ........................................ 88 figure 36. mixed minimum/constant delay con- nections, con[1:0 = 10] ......................... 89 figure 37. extended linear (mixed minimum/con- stant) delay, con[1:0] = 11 ................... 90
4 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 table of contents (continued) tables page table 1. pin descriptions: clocking and framing pins ..............................................................6 table 2. pin descriptions: local streams pins ...........8 table 3. pin descriptions: h-bus pins ........................8 table 4. pin descriptions: microprocessor interface pins ..............................................................9 table 5. pin descriptions: jtag pins .......................9 table 6. pin descriptions: power pins ......................9 table 7. pin descriptions: other pins ......................10 table 8. addresses of programming registers ........14 table 9. master control and status register ..........14 table 10. address mode register ............................15 table 11. control register memory space ..............16 table 12. ckm: clocks, main clock selection, 0x00 .........................................................17 table 13. ckn: clocks, netref selections, 0x01 .........................................................17 table 14. ckp: clocks, programmable outputs, 0x02 .........................................................17 table 15. ckr: clocks, resource selection, 0x03 .........................................................17 table 16. cks: clocks, secondary (fallback) selection, 0x04 ........................................17 table 17. ck32: clocks, locals 3 and 2, 0x05 ........17 table 18. ck10: clocks, locals 1 and 0, 0x06 ........17 table 19. ckmd: clocks, main divider; cknd: clocks, netref divider; ckrd: clocks, resource divider, 0x07, 0x08, 0x09 ........18 table 20. lbs: local stream control, 0x0c ............18 table 21. con: connection delay type, 0x0e .......18 table 22. hsl: h-bus stream control, low byte, 0x10 ...............................................18 table 23. hsh: h-bus stream control, high byte, 0x11 ...............................................18 table 24. gpr: general-purpose i/o register, 0x18 .........................................................18 table 25. frla: frame group a, start address low, 0x20 ................................................19 table 26. frha: frame group a, high address and control, 0x21 ....................................19 table 27. frlb: frame group b, start address low, 0x22 ................................................19 table 28. frhb: frame group b, high address and control, 0x23 ....................................19 table 29. frpl: frame group b, programmed output, low, 0x24 ...................................19 table 30. frph: frame group b, programmed output, high, 0x25 ..................................19 table 31. clkerr1: clock error register, error indicator, 0x28 .........................................20 table 32. clkerr2: clock error register, current status, 0x29 ............................................20 table 33. syserr: system error register, 0x2a ........................................................20 table 34. ckw: clock error/watchdog masking register, 0x2b .........................................20 tables page table 35. diag1: diagnostics register 1, 0x30 ..... 20 table 36. diag2: diagnostics register 2, 0x31 ..... 20 table 37. diag3: diagnostics register 3, 0x32 ..... 20 table 38. lbs: local stream control, 0x0c ........... 27 table 39. ckm: clocks, main clock selection, 0x00 ......................................................... 41 table 40. ckn: clocks, netref selections, 0x01 ......................................................... 42 table 41. ckp: clocks, programmable outputs, 0x02 ......................................................... 43 table 42. ckr: clocks, resource selection, 0x03 ......................................................... 44 table 43. cks: clocks, secondary (fallback) selection, 0x04 ........................................ 45 table 44. ck32 and ck10: clocks, locals 3, 2, 1, and 0, 0x05 and 0x06 .............................. 46 table 45. frha, frame group a high address and control, 0x21 ................................... 47 table 46. frhb, frame group b high address and control, 0x23 .................................... 47 table 47. frph: frame group b, programmed output, high, 0x25 .................................. 48 table 48. clkerr1 and clkerr2: error indicator and current status, 0x28 and 0x29 ......... 50 table 49. syserr: system error register, 0x2a ........................................................ 50 table 50. t8100 jtag instruction set ................... 51 table 51. t8100 jtag scan register .................... 52 table 52. time-slot bit decoding ............................ 57 table 53. idr: indirect data register, local connections only .................................... 58 table 54. idr: indirect data register, h-bus connections only ................................... 59 table 55. crystal oscillator ..................................... 67 table 56. alternative to crystal oscillator ............... 67 table 57. electrical drive specificationsct_c8 and /ct_frame ..................................... 67 table 58. dc electrical characteristics, all other pins .......................................................... 68 table 59. ac electrical characteristics, timing, h-bus (h.100, spec., rev. 1.0) .............. 72 table 60. ac electrical characteristics, skew timing, h-bus (h.100, spec., rev. 1.0) . 73 table 61. reset and power on ............................... 73 table 62. ac electrical characteristics, local streams, and frames .............................. 74 table 63. microprocessor access timing (see figure 24 through figure 29.) ................. 77 table 64. clock register programming profile for the four previous examples .................. 85 table 65. table of special cases (exceptions) ....... 88
lucent technologies inc. 5 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 1 product overview (continued) 1.3 pin information 5-6118bf figure 1. pin diagram ct_d28 ct_d30 vss ldo1 ldo3 ldo4 ldo6 ct_d27 vdd ct_d29 ct_d31 ldo0 ldo2 vdd ldo5 ldo7 vss ldo8 ldo9 ldo10 ldo11 vdd ldo12 ldo13 ldo14 ldo15 vss ldi1 ldi3 ldi5 ldi7 ldi8 ldi10 ldi12 ldi14 (nc) vss xcs ldi0 ldi2 ldi4 ldi6 vdd ldi9 ldi11 ldi13 ldi15 tclkout (nc) pll2gnd (nc) pll2vdd /c16+ vss fga1 fga3 fga5 fga6 fga8 /c4 vss /c16C fga0 fga2 fga4 vdd fga7 fga9 fga10 fga11 vss fgb0 fgb1 fgb2 fgb3 fgb4 fgb5 vdd fgb7 fgb9 fgb11 gp0 gp2 gp4 todjat/gp6 vdd (nc) (nc) vss fgb6 fgb8 fgb10 vss gp1 gp3 gp5 fromdjat/gp7 (nc) (nc) prirefout (nc) en1 4mhzin pll1vdd ct_d24 ct_d23 ct_d21 vdd ct_d18 ct_d16 ct_d15 ct_d26 ct_d25 vss ct_d22 ct_d20 ct_d19 ct_d17 vss ct_d14 ct_d13 ct_d12 vss ct_d11 ct_d10 (nc) ct_d9 ct_d8 vdd ct_d7 ct_d5 vss ct_d2 ct_d1 vss vss vss /fr_comp vss vss vss ct_d6 ct_d4 ct_d3 vdd ct_d0 /ct_frame_a ct_c8_a ct_netref /ct_frame_b ct_c8_b sclk sclkx2 vdd c2 vss (nc) xtalout vdd l_ref6 l_ref4 l_ref2 l_ref0 (nc) pll1gnd vss xtalin l_ref7 l_ref5 l_ref3 l_ref1 vss l_sc3 l_sc2 l_sc1 l_sc0 vdd a1 a0 ale cs rd (ds ) rdy (dtack ) vss d6 d4 d2 d0 clkerr vss tclk tdi trst wr (r /w) reset d7 d5 d3 d1 vdd syserr tts tms tdo dpue en2 (nc) 3mhzin 1 53 105 157
6 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 1 product overview (continued) 1.3 pin information (continued) 5-6626(f) figure 2. 217 pbgatop view table 1. pin descriptions: clocking and framing pins symbol pin ball type name/description l_ref[7:0] 4538 p3, n4, r1, p2, n3, m4, p1, n2 i local frame reference inputs. 50 k w internal pull-up. /c16+ /c16C 102 101 r14 p13 i/o h- mvip 16.384 mhz clock signals. differential 24 ma drive, schmitt in, 50 k w internal pull-up. u t r p n m l k j h g f e d c b a 1234567891011121314151617 33 29 26 24 22 20 17 13 10 6 2 1 34 30 27 23 21 18 14 11 7 3 v ss 184 100 108 v dd v ss v dd 123 131 135 v ss 142 145 148 36 32 28 25 19 15 12 9 4 v ss 183 180 39 31 v dd v ss v dd 16 8 5 v ss 182 179 176 181 178 175 173 177 174 172 171 169 170 168 167 v dd 166 165 164 v ss 163 161 162 v dd 157 159 160 154 153 156 158 146 150 152 155 143 147 149 151 v ss v ss v ss v ss v ss v ss v ss v ss v ss 106 110 113 115 119 122 126 129 133 137 v ss 140 104 107 111 117 120 124 128 132 136 v ss 141 144 109 112 114 116 118 121 125 127 130 134 138 139 47 46 42 38 35 48 v ss 45 41 37 52 49 v ss 44 40 56 53 50 v ss 43 84 87 90 v ss 97 88 91 v ss 96 101 92 v ss 95 99 103 93 94 98 102 105 63 60 58 54 66 64 61 62 68 67 65 v dd 70 69 71 v ss 72 73 74 v dd 75 76 78 77 79 80 82 85 81 83 86 89 59 57 55 51
lucent technologies inc. 7 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 1 product overview (continued) 1.3 pin information (continued) table 1. pin descriptions: clocking and framing pins (continued) symbol pin ball type name/description /c4 104 u16 i/o mvip 4.096 mhz clock. 8 ma drive, schmitt in, 50 k w internal pull-up. c2 106 t17 i/o mvip 2.048 mhz clock. 8 ma drive, schmitt in, 50 k w internal pull-up. sclk 110 r17 i/o sc-bus 2/4/8 mhz clock. 24 ma drive, schmitt in, 50 k w internal pull-up. sclkx2 108 p15 i/o sc-bus inverted 4/8 mhz clock (active-low). 24 ma drive, schmitt in, 50 k w internal pull-up. l_sc[3:0] 3633 m3, n1, m2, m1 o local selected clocks. 1.024 mhz, 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz, frame (8 khz), or sec- ondary (netref). 8 ma drive, 3-state. fga[5:0] 9499 r12, t13, u14, p12, r13, t14 o frame group a. 8 ma drive, 3-state. fga[11:6] 8792 t11, p11, r11, u12, t12, u13 fgb[5:0] 8085 u9, r9, u10, t10, r10, u11 o frame group b. 8 ma drive, 3-state. fgb[11:6] 7378 u6, t7, r8, u7, t8, u8 prirefout 58 p5 o output from primary clock selector/divider. 8 ma drive. pll1v dd 53 u1 pll #1 vco power. this pin must be connected to power, even if pll #1 is not used. pll1gnd 51 no ball for this signal, internally connected. pll #1 vco ground. this pin must be connected to ground, even if pll #1 is not used. en1 55 t3 i pll #1 enable. requires cap to v ss to form power-on reset, or may be driven with reset line. 50 k w internal pull-up. 4mhzin 54 u2 i pll #1 rate multiplier. can be 2.048 mhz or 4.096 mhz. 50 k w internal pull-up. pll2v dd 208 a2 pll #2 vco power. this pin must be connected to power if pll #2 is not used and 3mhzin is used. can be left float- ing only if both pll #2 and 3mhzin are not used. pll2gnd 206 no ball for this signal, internally connected. pll #2 vco ground. this pin must be connected to ground if pll #2 is not used and 3mhzin is used. can be left floating only if both pll #2 and 3mhzin are not used. en2 3 c2 i pll #2 enable. requires cap to v ss to form power-on reset, or may be driven with reset line. 50 k w internal pull-up. 3mhzin 1 a1 i pll #2 rate multiplier. input, 50 k w internal pull-up. xtalin 47 r2 i 16.384 mhz crystal connection or external clock input. xtalout 48 t1 o 16.384 mhz crystal, feedback connection. tclkout 203 c4 o selected output to drive framers. 8 ma drive, 3-state.
8 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 1 product overview (continued) 1.3 pin information (continued) table 2. pin descriptions: local streams pins table 3. pin descriptions: h-bus pins symbol pin ball type name/description ldi[15:8] ldi[7:0] 201194 192185 a3, b4, c5, d6, a4, b5, c6, a5 b6, a6, c7, d7, b7, a7, c8, b8 i local data input streams. 50 k w inter- nal pull-up. ldo[15:12] ldo[11:8] ldo[7:4] ldo[3:0] 182179 177174 172169 167164 c9, a9, b9, a10 b10, a11, c10, b11 d11, c11, b12, a13 b13, a14, c13, d12 o local data output streams. 8 ma drive, 3-state. symbol pin ball type name/description ct_d[31:28] ct_d[27:24] ct_d[23:20] ct_d[19:16] ct_d[15:12] ct_d[11:10] ct_d[9:8] ct_d[7:4] ct_d[3:2] ct_d[1:0] 162159 157154 152149 147144 142139 137136 134133 131128 126125 123122 a15, d13, c14, b15 a17, c16, d15, e14 c17, d16, e15, f14 d17, e16, f15, e17 f16, f17, g15, g14 g16, g17 h15, h16 h17, j15, j17, j16 k17, k16 l17, k15 i/o h-bus, data lines. variable rate 2 mbits/s, 4 mbits/s, 8 mbits/s. 5 v tolerant, pci compliant, 50 k w internal pull-up. to conform to h.100, connect an external 24 w series, 1/8 w resistor between each pin and the bus. also, data lines 1631 should be pro- grammed to 8 mbits/s. /ct_frame_a 120 l14 i/o h-bus, 8 khz, frame. 5 v tolerant, pci compliant, 24 ma drive, schmitt in. no pull-up. /ct_frame_b 114 p17 i/o h-bus, alternate 8 khz frame. 5 v tolerant, pci compliant, 24 ma drive. schmitt in. no pull-up. /fr_comp 115 m15 i/o h-bus, compatibility frame signal. 24 ma drive, schmitt in, 50 k w internal pull-up. ct_netref 116 n17 i/o h-bus, network reference. 8 khz, 2.048 mhz, or 1.544 mhz. 8 ma drive, slew rate limited, schmitt in. not internally pulled up. ct_c8_a 118 m16 i/o h-bus, main clock. 5 v tolerant, pci compliant, 24 ma drive, schmitt in. no pull-up. ct_c8_b 112 m14 i/o h-bus, alternate main clock. 5 v tolerant, pci compliant, 24 ma drive, schmitt in. no pull-up. dpue 4 d3 i data pull-up enable. high enables pull-ups on ct_dxx only for h.100, low disables for h.110. 50 k w internal pull-up.
lucent technologies inc. 9 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 1 product overview (continued) 1.3 pin information (continued) table 4. pin descriptions: microprocessor interface pins table 5. pin descriptions: jtag pins table 6. pin descriptions: power pins symbol pin ball type name/description reset 24 j1 i master reset (active-low). see section 3.1 resets. 50 k w internal pull- up. a[1:0] 3130 l4, l2 i microprocessor interface, address lines. internal 20 k w pull-down. d[7:0] 2215 h1, h2, g1, h3, g2, f1, g4, g3 i/o microprocessor interface, data lines. 8 ma drive, 50 k w internal pull-up. ale 29 l1 i address latch enable. internal 20 k w pull-down. cs 28 k3 i chip select (active-low). 50 k w internal pull-up. rd (ds ) 27 k2 i read strobe ( intel mode [active-low]), data strobe ( motorola [active- low]). 50 k w internal pull-up. wr (r/w ) 26 k1 i write strobe ( intel [active-low]), read/write select ( motorola [active- low]). 50 k w internal pull-up. rdy (dtack ) 25 j3 o data ready ( intel ), data transfer ( motorola [active-low]). 8 ma, open drain (user should add pull-up to this line). clkerr 13 e1 o clock error. logical or of clkerr register flags (only). 8 ma drive, 3-state syserr 12 f3 o system error. logical or of all clkerr and syserr register flags. 8 ma drive, 3-state. symbol pin ball type name/description tclk 9 e3 i jtag clock input. tms 8 f4 i jtag mode select. 50 k w internal pull-up. tdi 7 d2 i jtag data input. 50 k w internal pull-up. tdo 6 c1 o jtag data output. 8 ma drive, 3-state. trst 5e4i jtag reset (active-low). 50 k w internal pull-up. symbol pin ball type name/description v ss 11, 23, 37, 49, 57, 72, 86, 100, 103, 105, 109, 111, 113, 117, 119, 121, 127, 138, 143, 153, 163, 173, 184, 204 b2, b16, c3, c15, d4, d9, d14, h8, h9, h10, j4, j8, j9, j10, j14, k8, k9, k10, l15, n14, p4, p9, p14, p16, r3, r15, t2, t15, t16, u15, u17 chip ground. v dd 14, 32, 46, 63, 79, 93, 107, 124, 132, 148, 158, 168, 178, 193 a16, d8, d10, f2, h4, h14, k4, k14, l16, p8, p10, t9 3.3 v supply voltage .
10 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 1 product overview (continued) 1.3 pin information (continued) table 7. pin descriptions: other pins symbol pin ball type name/description gp[5:0] 6671 t5, r6, u5, t6, r7, p7 i/o general-purpose bidirectional regis- ter. 8 ma drive, schmitt in, 50 k w inter- nal pull-up. todjat/gp6 65 u4 i/o output from selector to drive djat (for netref) or gp register bit 6. 8 ma drive, schmitt in, 50 k w internal pull-up. fromdjat/gp7 64 r5 i/o smoothed input to netref divider and drivers or gp register bit 7. 8 ma drive, input, schmitt in, 50 k w internal pull-up. xcs 183 a8 o serial output from connection mem- ory. 8 ma drive, 3-state. tts 10 d1 i test type select. 0 = jtag, 1 = forced output test, internal pulldown. (nc) 2, 50, 52, 56, 59, 60, 61, 62, 135, 202, 205, 207 a12, b1, b3, b14, b17, c12, d5, e2, j2, l3, m17, n15, n16, p6, r4, r16, t4, u3 reserved, no connection. 1.4 enhanced local stream addressing local stream addressing has 1024 locations. separate connection and data memories maintain all necessary information for local stream interconnections. the streams may operate at maximum rate on eight physi- cal inputs and eight physical outputs. choices for slower input or output rates allow enabling of additional physical inputs or outputs for a maximum of 16 pins each. data rates are 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s. in addition to the enhanced serial streaming, the local memories may be used for 8-line-serial-in/1-byte-paral- lel-out, 1-byte-parallel-in/8-line-serial-out, or 1-byte- parallel-in/1-byte-parallel-out options. all three data rates are supported in the parallel modes. the addresses for the local memories have been simplified so that stream and time-slot designations are automati- cally translated to the appropriate memory address, regardless of rate or serial/parallel modes. 1.5 full h.100 stream address support the t8100 provides access to the full 4096 h.100 bus slots (32 streams x 128 slots) or any standard subset (h- mvip has a maximum 24 streams x 128 time slots, for example). the number of stored time-slot addresses is limited to 256 at any one time, but these may be updated on the fly. in addition, accesses to and from the h.100 bus can be directed through the 1024 local stream/time slots, giving a total space of 5120 time slots. data rates are programmable on each of the 32 physical streams, selected in groups of four. the rates are 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s.
lucent technologies inc. 11 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 1 product overview (continued) 1.6 onboard plls and clock monitors the t8100 uses rate multipliers and state machines to generate onboard frequencies for supporting the h.100, h- mvip , mvip , mc-1, and sc-buses. pins are provided for coupling the internal clock circuitry with commonly available clock adapters and jitter attenua- tors. if external resources are not available, an internal digital phase-locked loop (dpll) can be used to gener- ate all the bus frequencies and remain synchronized to an 8 khz reference. one of several clock input refer- ence sources may be selected, and separate input- active detection logic can identify the loss of the individ- ual input references. the entire clocking structure oper- ates from a 16.384 mhz crystal or external input. 1.7 phase alignment of referenced and generated frames if this resource is selected, special control logic will cre- ate bit-sliding in the data streams when the reference frame and generated frame are out of phase. the bit- sliding refers to removing a fraction of a bit time per frame until the frames are in phase. 1.8 interfaces 1.8.1 microprocessors the t8100 provides the user a choice of either motor- ola or intel interfacing through an 8-bit data bus, a 2-bit address bus, and multifunction control pins. all access to t8100 memory blocks and registers use indirect addressing. 1.8.2 framing groups two groups of programmable framing signals are avail- able. each group is composed of 12 sequenced lines operating in one of four modes. the t8100 supports 1-bit, 2-bit, 1-byte, and 2-byte pulse widths. starting position of the pulse sequences are also programma- ble. 1.8.3 general-purpose register and i/o a general-purpose register is provided as either a byte- wide input or byte-wide output through a separate set of pins. 1.9 applications n computer-telephony systems n enhanced service platforms n wan access devices n pbxs n wireless base stations 1.10 application overview the integration of computers and telecommunications has enabled a wide range of new communications applications and has fueled an enormous growth in communications markets. a key element in the devel- opment of computer-based communications equipment has been the addition of an auxiliary telecom bus to existing computer systems. most manufacturers of high-capacity, computer-based telecommunications equipment have incorporated some such telecom bus in their systems. typically, these buses and bus interfaces are designed to transport and switch n x 64 kbits/s low-latency telecom traffic between boards within the computer, independent of the com- puters i/o and memory buses. at least a half dozen of these pc-based telecom buses emerged in the early 1990s for use within equipment based on isa/eisa and mca computers. with the advent of the h.100 bus specification by the enterprise computer telephony forum, the computer- telephony industry has agreed on a single telecom bus for use with pci and compact pci computers. h.100 facilitates interoperation of components, thus providing maximum flexibility to equipment manufacturers, value- added resellers, system integrators, and others build- ing computer-based telecommunications applications.
12 12 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion the t8100 is an h.100-compliant device that provides a complete interface between the h.100 bus and a wide variety of telephony interface components, pro- cessors, and other circuits. the bus interface provides all signals needed for the h.100 bus, the h- mvip and mvip -90 buses, or the sc-bus. local interfaces include 16 serial inputs and 16 serial outputs based on the lucent technologies microelectronics group con- centration highway interface (chi). two built-in time- slot interchangers are included. the first provides a local switching domain with up to 1024 programmable connections between time slots on the local chi inputs and outputs. the second supports up to 256 program- mable connections between any time slot on the h.100 bus and any time slot in the local switching domain. the ambassador is configured via a microprocessor interface. this interface can also read and write time slot and device data. onboard clock circuitry, including a dpll, supports all h.100 clock modes including mvip and sc-bus compatibility clocks. the local chi interfaces support pcm rates of 2.048 mbits/s, 4.096 mbits/s, and 8.192 mbits/s. the t8100 has internal circuitry to support either minimum latency or multi-time-slot frame integrity. frame integrity is a requisite feature for applications that switch wide- band data (isdn h-channels). minimum latency is advantageous in voice applications. the t8100 has four major sections: n local busrefers to the local streams. n h-busrefers to the h.100/h.110/h- mvip and legacy streams. n interfacerefers to the microprocessor interface, frame groups, and general-purpose i/o (gpio). n timingthe rate multipliers, dpll, and clocking functions. figure 3 shows a t8100 block diagram. the t8100 operates on a 3.3 v supply for both the core and i/os, though the i/os are ttl compatible and 5 v tolerant.
lucent technologies inc. 13 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 5-6101.a (f) figure 3. block diagram of the t8100 h.100, h.110, h- mvip , mvip , sc-bus internal clocks and state counter s/p and p/s converters 256 location data sram three 256 location connection cams 1024 location data memory output logic and p/s convert input logic and s/p convert 1024 location connection memory timing and control microprocessor interface frame group interface logic frame groups addr[1:0] data[7:0] m p controls misc. i/o clocks and refs internal data internal address and control local out local in
14 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.1 register/memory maps in this section, a general overview of the registers and the indirect mapping to different memory spaces is described. more detailed descriptions for using the registers in software can be found in section 3.2 basic connec- tions. (throughout this document, all registers are defined with the msb on the left and the lsb on the right.) 2.1.1 main registers the address bits are used to map a large memory space. all registers default to 0 at powerup. table 8. addresses of programming registers 2.1.2 master control and status register table 9. master control and status register a1 a0 name description 0 0 mcr master control and status register (read/write) 0 1 lar lower address registerlower indirect address (time slot) (write only) 1 0 amr address mode registerupper address (stream) and address type (write only) 1 1 idr indirect data register (read/write) bit name description 7mr master (software) reset . a high reinitializes the t8100 registers. 6cer clock error reset . a high resets the error bits of the clkerr registers. 5ser system error reset . a high resets the error bits of the syserr register. (note that mr, cer, and ser are automatically cleared by the t8100 after the requested reset is com- plete.) 4ap active page . this bit identifies which of the double-buffered data memories are active. a zero indicates buffer 0; a one indicates buffer 1. the ap identifies which data buffer is being accessed during a write operation (i.e., input from local streams or input from h-bus). 3hbe h-bus enable . on powerup or software reset, all h-bus pins (including clocks) are disabled. hbe must be set high to reenable the 3-stated buffers. 2lbe local bus enable . same function as hbe for local data outputs. 1lce local clock enable . enables all other local functions: clocks, frame groups, etc. (note that the tclko is disabled during a master reset and is unaffected by hbe, lbe, or lce, though there are control bits for this signal in the ckp register, section 2.4.6 clock control register definitions.) 0cb cam busy . a status bit indicating microprocessor activity in any of the cam blocks. a high means that one (or more) of the cams is being accessed by the microprocessor. in most cases, this bit will read low since there are many internal operational cycles dedicated to the microprocessor, which allow it to finish quickly.
lucent technologies inc. 15 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.1 register/memory maps (continued) 2.1.3 address mode register the amr is defined in table 10 below where (aaaa) is the stream address and the lar is the time-slot address of the selected memory space. note: all unused amr values are reserved. table 10. address mode register bits 74 bits 30 register function 0000 0000 control registers. 0001 (aaaa) local bus, data memory 1. 0010 (aaaa) local bus, data memory 2. 0100 (aaaa) local bus, connection memory, time-slot field. 0101 (aaaa) local bus, connection memory, stream, and control bit field. 0111 0000 local bus, holding registers, reset. 1001 0000 cam, data memory 1. 1010 0000 cam, data memory 2. 1011 0000 cam, connection, time-slot field. 1011 0001 cam, connection, stream, and control bit field. 1011 0010 cam, connection, tag field. 1110 0000 cam, even, make connection (mkce). write to next free location. 1110 0001 cam, odd, make connection (mkco). write to next free location. 1110 0011 cam, local, make connection (mkcl). write to next free location. 1110 0100 cam, even, break connection (bkce). 1110 0101 cam, odd, break connection (bkco). 1110 0111 cam, local, break connection (bkcl). 1110 1000 cam, even, clear location (clle). requires lar. 1110 1001 cam, odd, clear location (cllo). requires lar. 1110 1011 cam, local, clear location (clll). requires lar. 1110 1100 cam, even, read location (rdce). requires lar, idr holds results. 1110 1101 cam, odd, read location (rdco). requires lar, idr holds results. 1110 1111 cam, local, read location (rdcl). requires lar, idr holds results. 1111 0000 cam, even, find entry (fene). idr holds results. 1111 0001 cam, odd, find entry (feno). idr holds results. 1111 0011 cam, local, find entry (fenl). idr holds results. 1111 1000 cam, even, reset (rsce). 1111 1001 cam, odd, reset (rsco). 1111 1011 cam, local, reset (rscl). 1111 1100 cam, holding registers, reset (rch). 1111 1111 cam, initialize (ci). reset all cam locations and holding registers.
16 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.1 register/memory maps (continued) 2.1.4 control register memory space function of lar values when amr = 0x00. all control registers reset to 0x00. table 11. control register memory space register address register mnemonic description refer to section 0, 0x00 ckm clocks, main clock selections 2.4.6 1, 0x01 ckn clocks, netref selections 2.4.6 2, 0x02 ckp clocks, programmable outputs 2.4.6 3, 0x03 ckr clocks, resource selection 2.4.6 4, 0x04 cks clocks, secondary (fallback) selection 2.4.6 5, 0x05 ck32 clocks, locals 3 and 2 2.4.6 6, 0x06 ck10 clocks, locals 1 and 0 2.4.6 7, 0x07 ckmd clocks, main divider 2.4.6 8, 0x08 cknd clocks, netref divider 2.4.6 9, 0x09 ckrd clocks, resource divider 2.4.6 1011, 0x0a0x0b (reserved) 12, 0x0c lbs local stream control 2.2.4 13, 0x0d (reserved) 14, 0x0e con connection delay type appendix b 15, 0x0f (reserved) 16, 0x10 hsl h-bus stream control, low byte 2.3.5 17, 0x11 hsh h-bus stream control, high byte 2.3.5 1823, 0x120x17 (reserved) 24, 0x18 gpr general-purpose i/o register 2.5.2 2531, 0x190x1f (reserved) 32, 0x20 frla frame group a, start address, low 2.5.3 33, 0x21 frha frame group a, high address and control 2.5.3 34, 0x22 frlb frame group b, start address, low 2.5.3 35, 0x23 frhb frame group b, high address and control 2.5.3 36, 0x24 frpl frame group b, programmed output, low 2.5.3 37, 0x25 frph frame group b, programmed output, high 2.5.3 3839, 0x260x27 (reserved) 40, 0x28 clkerr1 clock error register, error indicator 2.6 41, 0x29 clkerr2 clock error register, current status 2.6 42, 0x2a syserr system error register 2.6 43, 0x2b ckw clock error/watchdog masking register 2.4.6 & 2.6 4447, 0x2c0x2f (reserved) 48, 0x30 diag1 diagnostics register 1 2.8.2 49, 0x31 diag2 diagnostics register 2 2.8.2 50, 0x32 diag3 diagnostics register 3 2.8.2 51255, 0x330x0ff (reserved)
lucent technologies inc. 17 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.1 register/memory maps (continued) 2.1.4 control register memory space (continued) this section is a summary of the register functions. the reader is encouraged to read through the rest of this specification to learn the details of the individual regis- ters and their interactions with the overall architecture. table 12. ckm: clocks, main clock selection, 0x00 table 13. ckn: clocks, netref selections, 0x01 table 14. ckp: clocks, programmable outputs, 0x02 table 15. ckr: clocks, resource selection, 0x03 table 16. cks: clocks, secondary (fallback) selection, 0x04 table 17. ck32: clocks, locals 3 and 2, 0x05 table 18. ck10: clocks, locals 1 and 0, 0x06 bit description 7 phase alignment enable 6 phase alignment select 5 compatibility clock direction 4 input clock invert 3 input clock select, msb 2 input clock select 1 input clock select 0 input clock select, lsb bit description 7 output enable 6 i/o select 5 bypass select 4 input clock invert 3 input clock select, msb 2 input clock select 1 input clock select 0 input clock select, lsb bit description 7 tclk select, msb 6 tclk select 5 tclk select, lsb 4 ct_c8 pins, input type select 3 ct_c8a output enable 2 ct_c8b output enable 1 ct_c8 pins, output type select 0 (reserved) bit description 7 resource select, msb 6 resource select, lsb 5 pll #1 bypass 4 pll #1 rate select 3 pll #2 bypass 2 pll #2 rate select 1 sclk output select, msb 0 sclk output select, lsb bit description 7 secondary resource select, msb 6 secondary resource select, lsb 5 fallback type select, msb 4 fallback type select, lsb 3 fallback, force selection of secondary input 2 secondary input clock select, msb 1 secondary input clock select 0 secondary input clock select, lsb bit description 7 local clock 3 select, msb 6 local clock 3 select 5 local clock 3 select 4 local clock 3 select, lsb 3 local clock 2 select, msb 2 local clock 2 select 1 local clock 2 select 0 local clock 2 select, lsb bit description 7 local clock 1 select, msb 6 local clock 1 select 5 local clock 1 select 4 local clock 1 select, lsb 3 local clock 0 select, msb 2 local clock 0 select 1 local clock 0 select 0 local clock 0 select, lsb
18 18 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.1 register/memory maps (continued) 2.1.4 control register memory space (continued) table 19. ckmd: clocks, main divider; cknd: clocks, netref divider; ckrd: clocks, resource divider, 0x07, 0x08, 0x09 table 20. lbs: local stream control, 0x0c table 21. con: connection delay type, 0x0e table 22. hsl: h-bus stream control, low byte, 0x10 table 23. hsh: h-bus stream control, high byte, 0x11 table 24. gpr: general-purpose i/o register, 0x18 bit description 7 divide value, msb 6 divide value 5 divide value 4 divide value 3 divide value 2 divide value 1 divide value 0 divide value, lsb bit description 7 parallel/serial select, msb 6 parallel/serial select, lsb 5 local group a rate select, msb 4 local group a rate select, lsb 3 local group b rate select, msb 2 local group b rate select, lsb 1 local group c rate select, msb 0 local group c rate select, lsb bit description 7 reserved 6 reserved 5 reserved 4 reserved 3 reserved 2 reserved 1 disabled connection-by-connection delay setting 0 enable linear delay bit description 7 h-bus group d rate select, msb 6 h-bus group d rate select, lsb 5 h-bus group c rate select, msb 4 h-bus group c rate select, lsb 3 h-bus group b rate select, msb 2 h-bus group b rate select, lsb 1 h-bus group a rate select, msb 0 h-bus group a rate select, lsb bit description 7 h-bus group h rate select, msb 6 h-bus group h rate select, lsb 5 h-bus group g rate select, msb 4 h-bus group g rate select, lsb 3 h-bus group f rate select, msb 2 h-bus group f rate select, lsb 1 h-bus group e rate select, msb 0 h-bus group e rate select, lsb bit description 7 general-purpose i/o, msb 6 general-purpose i/o 5 general-purpose i/o 4 general-purpose i/o 3 general-purpose i/o 2 general-purpose i/o 1 general-purpose i/o 0 general-purpose i/o, lsb
lucent technologies inc. 19 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.1 register/memory maps (continued) 2.1.4 control register memory space (continued) table 25. frla: frame group a, start address low, 0x20 table 26. frha: frame group a, high address and control, 0x21 table 27. frlb: frame group b, start address low, 0x22 table 28. frhb: frame group b, high address and control, 0x23 table 29. frpl: frame group b, programmed output, low, 0x24 table 30. frph: frame group b, programmed output, high, 0x25 bit description 7 start address, bit 7, or programmed output, bit 7 6 start address, bit 6, or programmed output, bit 6 5 start address, bit 5, or programmed output, bit 5 4 start address, bit 4, or programmed output, bit 4 3 start address, bit 3, or programmed output, bit 3 2 start address, bit 2, or programmed output, bit 2 1 start address, bit 1, or programmed output, bit 1 0 start address, lsb, or programmed output, bit 0 bit description 7 rate select, msb 6 rate select, lsb 5 pulse width select, msb 4 pulse width select, lsb 3 frame invert, or programmed output, bit 11 2 start address, msb, or programmed output, bit 10 1 start address, bit 9, or programmed output, bit 9 0 start address, bit 8, or programmed output, bit 8 bit description 7 start address, bit 7 6 start address, bit 6 5 start address, bit 5 4 start address, bit 4 3 start address, bit 3 2 start address, bit 2 1 start address, bit 1 0 start address, lsb bit description 7 rate select, msb 6 rate select, lsb 5 pulse width select, msb 4 pulse width select, lsb 3 frame inversion select 2 start address, msb 1 start address, bit 9 0 start address, bit 8 bit description 7 programmed output, bit 7 6 programmed output, bit 6 5 programmed output, bit 5 4 programmed output, bit 4 3 programmed output, bit 3 2 programmed output, bit 2 1 programmed output, bit 1 0 programmed output, bit 0 bit description 7 group a output pins select, msb 6 group a output pins select, lsb 5 (reserved, use 0) 4 group b output pins select 3 programmed output, bit 11 2 programmed output, bit 10 1 programmed output, bit 9 0 programmed output, bit 8
20 20 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.1 register/memory maps (continued) 2.1.4 control register memory space (continued) table 31. clkerr1: clock error register, error indicator, 0x28 table 32. clkerr2: clock error register, current status, 0x29 table 33. syserr: system error register, 0x2a table 34. ckw: clock error/watchdog masking register, 0x2b table 35. diag1: diagnostics register 1, 0x30 table 36. diag2: diagnostics register 2, 0x31 table 37. diag3: diagnostics register 3, 0x32 bit description 7 c8a or frame a error 6 c8b or frame b error 5 fr_compn error 4 c16+ or c16C error 3 c4n or c2 error 2 sclkx2 error 1 sclk error 0netref error bit description 7 c8a or frame a fault status 6 c8b or frame b fault status 5 fr_compn fault status 4 c16+ or c16C fault status 3 c4n or c2 fault status 2 sclkx2 fault status 1 sclk fault status 0 netref fault status bit description 7 even cam underflow error (no match) 6 odd cam underflow error (no match) 5 local cam underflow error (no match) 4 even cam overflow or no-match error 3 odd cam overflow or no-match error 2 local cam overflow or no-match error 1 (reserved) 0 fallback enable indicator bit description 7 c8a and frame a error mask 6 c8b and frame b error mask 5 fr_compn error mask 4 c16+ and c16C error mask 3 c4n and c2 error mask 2 sclkx2 error mask 1 sclk error mask 0 netref error mask bit description 7 frame group a output select, msb 6 frame group a output select, lsb 5 frame group b output select, msb 4 frame group b output select, lsb 3 memory fill enable 2 memory fill pattern select, msb 1 memory fill pattern select, lsb 0 memory fill status bit (read only) bit description 7 frame groups cycle test enable 6 break state counter into subsections 5 bypass internal frame with fr_compn 4 (reserved) 3 enable state counter parallel load 2 parallel load value of state counter, msb 1 parallel load value of state counter, bit 9 0 parallel load value of state counter, bit 8 bit description 7 parallel load value of state counter, bit 7 6 parallel load value of state counter, bit 6 5 parallel load value of state counter, bit 5 4 parallel load value of state counter, bit 4 3 parallel load value of state counter, bit 3 2 parallel load value of state counter, bit 2 1 parallel load value of state counter, bit 1 0 parallel load value of state counter, lsb
lucent technologies inc. 21 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.2 local bus section figure 4 shows the local bus section function diagram. note: routing and muxing for the h-bus section is included since the h-bus requires access to the converters for local bus-to-h-bus or h-bus-to-local bus transfers (the h-bus is discussed in section 2.3 h-bus sec- tion). xcs is a pseudo serial stream, read out from the connection memory on each memory access. it is read out directly, i.e., not passing through any parallel/serial converters or holding registers, so it precedes the connection associated with it by one time slot. 5-6102f figure 4. local bus section function s/p bypass address buffer & decoder cam- local select p/s bypass parallel to serial (p/s) data buffer- register from cam serial to parallel (s/p) (1024 locations x bits) x 2 data memory connection buffer- register ctl bits (pattern mode) 1024 locations x 15 bits connection memory local stream local stream to cam internal each location: stream = 4 bits time slot = 7 bits time-slot enable bit constant/min delay bit pattern mode bit xcs bit internal (amr) + (lar) 8 8 11 11 10 10 11 8 8 address buffer & decoder 8 xcs address bus data bus inputs outputs
22 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.2 local bus section (continued) 2.2.1 constant frame delay and minimum delay connections the local bus section contains the local connection memory and the double-buffered local data memory. collec- tively, the connection memory and data memory are referred to as local memory since it is used for implementing local-to-local switching only. operation is similar to other time-slot interchangers. data is written into the memory in a fixed order and then read out according to the indirect addresses held in the connection memory. if any of the connections on the t8100 are operating in constant frame delay (also called constant delay) mode, then the output data is accessed from a second block of data memory. the input data will not be output until the next frame bound- ary has been crossed and the memory blocks have swapped functions. figure 5 shows an example of a set of con- nections which create the delay types referred to as minimum delay and constant delay. 5-6103f figure 5. local bus memory connection modes frame n data data block 0 0 1 2 3 1020 1021 1022 1023 write n read n minimum delay connection frame n C 1 data data block 1 0 1 2 3 1020 1021 1022 1023 read n C 1 constant delay connection frame n data data block 0 0 1 2 3 1020 1021 1022 1023 read n constant delay connection frame n C 1 data data block 1 0 1 2 3 1020 1021 1022 1023 write n + 1 read n + 1 minimum delay connection frame n + 1 frame n
lucent technologies inc. 23 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.2 local bus section (continued) 2.2.2 serial and parallel nominally, the memory will be accessed by serial data streams which will require conversion of serial-to-paral- lel (s/p) for write accesses and parallel-to-serial (p/s) for read accesses. since the local memory can have up to 16 serial inputs and 16 serial outputs, there will be a maximum of 16 s/p converters and 16 p/s converters operating simultaneously. if desired, eight of the s/p converters, local inputs 07, can be bypassed for a direct parallel write to the data memory. likewise, eight of the p/s converters, local outputs 07, can be bypassed for a direct parallel read of the data memory. unused s/p or p/s converters are nonfunctional in these modes. note: the normal serial-to-serial local streaming is not available simultaneously with any of the parallel modes. 2.2.3 data rates and time-slot allocation at its maximum, the t8100 will be able to process 1024 nonblocking-to-local connections. the data rate 8.192 mbits/s corresponds to 128 time slots, 4.096 mbits/s corresponds to 64 time slots, and 2.048 mbits/s corresponds to 32 time slots. since dif- ferent data rates require different amounts of memory, the local memory can be filled in a number of ways. a nonblocking switch permits any time slot on any stream to be switched to another time slot on any stream in any direction. the local streams are arranged in three groups: a, b, and c. group a corresponds to the local data pins 0 7, group b with local data pins 811, and group c with local data pins 1215. the groups may be operated at any of the three data rates: 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s; however, group b is activated only when group a is operating below 8.192 mbits/s. likewise, group c is activated when group b is operating below 8.192 mbits/s. note: in order to efficiently fill the memory, the mem- ory locations are read or filled in the same order regardless of their activation or rate. the streams are scanned in intervals equal to 8.192 mbits/s time slots: first group a from 0 through 7, then group b from 8 through 11, then group c from 12 through 15. if a group is active, the data is input from or output to the streams in that group. if a group is operat- ing below 8.192 mbits/s and has already been scanned (at the 8.192 mbits/s rate), then the data transfer opera- tion is ignored. for t8100 addressing, the user directly provides stream and time-slot information. the t8100 will map this into the physical memory, regardless of which stream groups are active or at what rate. while this makes programming simpler, it makes the internal operation more difficult to understand. several dia- grams are required to illustrate how the memory utiliza- tion works. unassigned time slots in the local output section are 3- stated. therefore, multiple lines can be connected together.
24 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.2 local bus section (continued) 2.2.3 data rates and time-slot allocation (continued) figure 6 below shows the overall structure of the local memory: note: both the connection and two data memories are arranged in four blocks of 256 locations each (i.e., 4 x [4 x 64]). the arrangement is important to establishing a memory fill pattern which supports all of the various groups and rates. the rows of each memory, which are split into four groups of 4, correspond to the 16 streams. the columns correspond to 64 time-slot addresses. 5-6104f figure 6. local streams, memory structure 4 4 4 4 64 4 4 4 4 64 location 0 connection location 15 each (small) square location 1023 data memory 0 data memory 1 each (small) to/from represents 15 bits of connection information square represents 1 byte of data local streams memory
lucent technologies inc. 25 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.2 local bus section (continued) 2.2.3 data rates and time-slot allocation (continued) examples of how the memory is filled are found in figure 7. note: again, the user needs only to provide stream and time-slot addresses; the t8100 will generate the internal memory addresses. both the connection and data memories are filled using the same algorithm. in the case where group c is running at 8.192 mbits/s, group b is at 4.096 mbits/s (or 2.048 mbits/s), and group a is at 2.048 mbits/s, then an additional virtual memory space of 4 x 64 locations is created by the t8100 from unused locations in other parts of the mem- ory. 5-6105f figure 7. local memory, fill patterns time slot 0 time slot 2 time slot 4 time slot 1 time slot 3 time slot 5 time slot 0 time slot 1 time slot 2 time slot 0 time slot 2 time slot 4 time slot 1 time slot 3 time slot 5 stream 03 stream 47 stream 03 stream 47 stream 03 stream 47 stream 811 stream 811 group a, group a, group a, 64 time slots 64 time slots group a at 8.192 mbits/s groups b and c off group a at 4.096 mbits/s group b at 8.192 mbits/s and group c off even odd group b, even group b, odd time slots time slots all time slots time slots time slots
26 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.2 local bus section (continued) 2.2.3 data rates and time-slot allocation (continued) 5-6106f figure 7. local memory, fill patterns (continued) in any of the parallel modes (s/p, p/s, p/p), the local memories treat parallel data as a series of sequential time slots (i.e., all one stream): 8.192 mbits/s corresponds to 1024 time slots, 4.096 mbits/s corresponds to 512 time slots, and 2.048 mbits/s corresponds to 256 time slots. the memory locations are scanned in order from 0 to 1023 at 8.192 mbits/s, even locations are scanned at 4.096 mbits/s (odd locations are skipped), and at 2.048 mbits/s, every second even location is scanned. time slot 0 time slot 1 time slot 2 time slot 0 time slot 1 time slot 2 time slot 0 time slot 1 time slot 2 stream 03 stream 47 stream 811 stream 1215 group a, 64 time slots group a at 4.096 mbits/s group b at 4.096 mbits/s group c at 4.096 mbits/s time slot 0 time slot 1 time slot 2 time slot 0 time slot 2 time slot 4 time slot 0 (used for group c) time slot 1 stream 03 stream 47 stream 811 stream 1215 group a, 64 time slots group a at 2.048 mbits/s group b at 4.096 mbits/s group c at 8.192 mbits/s group c, odd (virtual) time slots stream 1215 time slot 1 time slot 3 time slot 5 group c, group b, group b, group c, even time slots all time slots all time slots all time slots all time slots all time slots
lucent technologies inc. 27 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.2 local bus section (continued) 2.2.4 lbs: local stream control, 0x0c the normal mode of operation for local streams is serial in/serial out, but parallel modes are available. modes and data rates are controlled by register lbs. the mapping is shown below. see the preceding pages for a full descrip- tion. table 38. lbs: local stream control, 0x0c there are no additional registers required for addressing the local memory other than the main address registers (discussed in section 2.1 register/memory maps). the data and connection memory locations can be queried for their contents by indirect reads through the main address registers; however, the memory locations are referred to by the stream and time-slot designators, rather than physical address locations, to simplify the queries. reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lbs p/s sga sgb sgc symbol bit name/description p/s 76 p/s = 00. serial in/serial out. the sga bits control the group a pins, sgb bits control the group b pins, and sgc bits control the group c pins. as serial streams, input and output rates within the same group are constrained to be identical so both inputs and outputs share the same 2 bits for programming. the sgb bits are enabled when sga 1 11. the sgc bits are enabled when sgb 1 11. p/s = 01. serial in/parallel out. sga sets input (serial) rate using the rate definition within this table. sgb is reserved. sgc sets the output (parallel) rate using the rate definition within this table. p/s = 10. parallel in/serial out. sga sets input (parallel) rate. sgb is reserved. sgc sets output (serial) rate. p/s = 11. parallel in/parallel out. sga sets input (parallel) rate. sgb is reserved. sgc sets output (parallel) rate. sga 54 sga = 00, 3-state. sga = 01, 2.048 mbits/s. sga = 10, 4.096 mbits/s. sga = 11, 8.192 mbits/s. sgb 32 sgb = 00, 3-state. sgb = 01, 2.048 mbits/s. sgb = 10, 4.096 mbits/s. sgb = 11, 8.192 mbits/s. sgc 10 sgc = 00, 3-state. sgc = 01, 2.048 mbits/s. sgc = 10, 4.096 mbits/s. sgc = 11, 8.192 mbits/s.
28 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.2 local bus section (continued) 2.2.5 state counter operation all operations are synchronized to the master state counter. the state counter is in turn synchronized to the inter- nal frame signal and driven by an internal 65.536 mhz clock. in normal operation, the internal frame and clock are synchronized to either the h-bus or trunks (see section 2.4 clocking section, for a more detailed explanation of clocking options). the local memory states are illustrated in figure 8. the state counter is a modulo-8192 counter (7 bits for time slot, 4 bits for stream, 2 bits for state function) which can also be reset and loaded with other values for diagnostic purposes (as described in section 2.8 testing and diagnostics). the h-bus memories are also refer- enced to this state counter so that t8100 maintains synchronization with the h-bus to ensure proper access to the bus as well as ensure synchronization between the h-bus and local memory structures. the h-bus memories are discussed in section 2.3 h-bus section. 5-6107f figure 8. simplified local memory state timing, 65.536 mhz clock 61 ns l0 l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 l12 l13 l14 l15 976 ns connection h6 read microprocessor memory data sram clock h6 write h6 read micro- pro- micro- pro- 15.25 ns cessor cessor
lucent technologies inc. 29 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.3 h-bus section 2.3.1 memory architecture to access the h-bus, the t8100 uses a new twist on an existing approach to accessing large address spaces: the data is stored in an independent double- buffered sram which acts like the local data memory, but the connection information for the h-bus is held in three 256 location cams. two cams are used for two groups of 16 h-bus streams each, and one cam for all 16 local input/output pairs. each cam compares 16 streams for read and write and allows access time to the host microprocessor for updates to the connec- tions. thus, each stream is allotted three operations per 976 ns time slot, so there are a maximum of 48 accesses per cam per time slot. the cams must oper- ate for at least 20.34 ns/access* or faster. the selected technology operates at 13 ns/access maximum, so an internal clock speed of 15.26 ns (65.536 mhz) is used. for the following discussions, the reader should refer to figure 9. the combined comparison plus retrieval operations take 2 cam cycles, leaving little time for microprocessor updates. to circumvent this, a separate sram (actually, a register file) is tied to each cam. each entry of this register file is associated with an entry in the cam on a location-by-location basis. (for example, physical address 0xa7 in the cam is coupled with physical address 0xa7 of the register file.) the cams will have only the comparand field for stream and time-slot addresses, and the associated register files will hold the data field, which is comprised of a tag (an indirect pointer to the double-buffered data sram) and some control bits. using the associated sram allows the operations to be pipelined so that the data retrieval occurs while the cams are doing the next comparison. the sram is double-buffered to permit constant delay or minimum delay on a connection-by- connection basis, as described in section 2.2.1 con- stant frame delay and minimum delay connections and as illustrated in figure 5. * the h-bus presents a unique set of problems. a full nonblocking, double-buffered switch of 5120 locations has significant barriers in size and in control of memory access time. further, the traffic between the local bus and h-bus is generally limited to a small number of time slots at any given moment (120 full duplex is typical, although we are permitting 128 duplex or 256 simplex connections), but the requirement to access any time slot out of the full range of 5120 locations remains. to solve this, content addressable memo- ries (cam) are utilized. they provide access to the full 5120 loca- tions through an encoded width (13 bits), but require a depth equal to the maximum number of connections required (256).
30 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.3 h-bus section (continued) 2.3.1 memory architecture (continued) 5-6108f figure 9. cam architecture the maximum number of connections is set by the number of locations in the data sram and the cams. in this implementation, 256 simplex connections are permitted. since one connection requires two cam entries pointing to a common data location, the maximum number of connections could be reduced to 128 simplex if all connection entries reside within only one cam. the maximum number of connections is increased above 256 simplex if the connection type is broadcast, i.e., from one to many. cam-e ce-sram 11 1 aa 0 255 70 tt address tag h-bus: a12 = 0 cam-o co-sram 11 1 aa 0 255 7 0 tt address tag h-bus: 1 = 01 cam-l cl-sram 10 0 aa 0 255 7 0 tt address tag a12.a11 = 11 read/write valid entry marker pattern/normal data sram select 70 dd 70 dd data buffer 0 data buffer 1 0 255 data sram read/write and sram select h-bus local i/o pattern mode outputs tag to h-bus pattern mode outputs tag to local out this is the h-bus connection memory: 3 cams, maximum of 48 accesses per 976 ns time slot, requires <20 ns/access this is the h-bus data memory: effective access time < 10 ns even streams odd streams local 015 a0 = 0 a12 = 0 a0 = 1
lucent technologies inc. 31 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.3 h-bus section (continued) 2.3.2 cam operation and commands the three cams operate in parallel. each cams com- parand field is compared with the state counter (sec- tion 2.2.5 state counter operation) which holds the existing stream and time-slot value*. if there is a match, the cam issues a hit. if there is more than one match, then it is considered a multiple hit. likewise, no match is a miss. as a part of the state counter, a bit is toggled for read/write. the read/write bit is stored in the cam, so it becomes part of the value to be compared. if the comparison for a write yields a hit, then there is a request for write access to the data memory for the incoming data from the h-bus. if the comparison for a read yields a hit, then there is a request for a read access from the data memory for outgoing data to the h-bus. any multiple hit within one cam block is treated as a controlled error although it is not reported. the action taken is to acknowledge the hit which corre- sponds to the lowest physical address of the cam. a miss implies no action. a multiple hit is assigned to be more than one valid connection. these are prioritized such that the match with the lowest physical address (i.e., closest to cam location 0x0) is the address which is processed. thus, errors are handled in a controlled manner. multiple hits can occur because multiple loca- tions are assigned to the same time slot. bad software can cause this problem. a controlled error has no impact on performance, and the cam contents are not changed as a result of the error. the data srams are actually dual-port register files which will process both writes and reads on each clock cycle of the clock. the t8100 can process a read and write request from each cam and two microprocessor requests during the time of one address comparison. due to the fixed order of operations, the data sram cannot overflow or under- flow like the cams. the timing is shown in figure 10. * as mentioned in section 2.2.5 state counter operation, for each stream and time-slot value, the state counter goes through four functional states for each stream and time slot. these states are used to synchronize the cams, pipeline register files, data srams, and microprocessor accesses just as they are used to synchronize local memory operations and the frame groups. (microprocessor accesses to the memories are initiated asynchronously, though the actual microprocessor cycles are synchronous.)
32 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.3 h-bus section (continued) 2.3.2 cam operation and commands (continued) 5-6109f figure 10. simplified h-bus state timing, 65.536 mhz clock 61 ns h0 h2 h4 h6 h8 h10 h12 h14 h16 h18 h20 h22 h24 h26 h28 h30 976 ns clock 15.25 ns h12 write h12 read micro- pro- micro- pro- h13 h13 read micro- pro- micro- pro- l6 write l6 read micro- pro- micro- pro- cam-e cam-o cam-l c0-sram c1-sram cl-sram h12 write h12 read h13 h13 read micro- pro- l6 write l6 read micro- pro- micro- pro- cessor cessor cessor cessor write cessor cessor write cessor cessor cessor micro- pro- cessor micro- pro- cessor micro- pro- cessor h1 l0 h3 l1 h5 l2 h7 l3 h9 l4 h11 l5 h13 l6 h15 l7 h17 l8 h19 l9 h21 l10 h23 l11 h25 l12 h27 l13 h29 l14 h31 l15 data sram writes data sram reads even (h12) local (l6) micro- odd (h13) even (h12) odd (h13) micro- local (l6) pro- cessor pro- cessor
lucent technologies inc. 33 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.3 h-bus section (continued) 2.3.2 cam operation and commands (continued) a number of commands are available to control the cams. connections can be made or broken, entry data can be searched for, individual locations may be read or cleared, or the cams can be reset. the address mode register (amr) (see section 2.1 register/mem- ory maps) is used to issue the cam control commands. some commands require the use of the lower address register (lar), and some use the idr as a transfer reg- ister. the tags in each cams associated register file refer- ence the storage location of the data being transferred, so each cam/tag location also has control information. the three control bits are read-to/write-from data sram (i.e., a direction bit, located in the cam and used during the comparison operations), a pattern mode enable, which bypasses the data sram and out- puts the tag directly into the specified time slot for writes to the bus, and an sram buffer select that con- trols the minimum delay or constant delay select, equivalent to the local memorys selection of minimum or constant delay. in addition, the cam carries a valid entry bit. this is an identifier for the status of the cam (and corresponding register file) location. if the bit is low, as all validity bits are after a reset, then the location is available to be written into. when data is written into a location, then this bit is set, indicating that this is a valid entry. if spe- cific data is no longer valid, such as when a connection is broken, then the bit is cleared. the cam commands make use of either one or two cycles. the two cycles are described pictorially in fig- ure 11. the reader will note that matching and retrieval are actually separate cycles. the need for two cycles accounts for the requirement of the pipeline register files. detailed descriptions of the commands follow: the basic make connection command is referred to as mkcn, where n is the cam designator*. the mkcn uses two cam cycles: first, the cam is searched to determine where to find the next free location (as deter- mined by the validity bits), and during the second cycle, the next empty location is written into. the mkcn com- mand uses holding registers which convey the connec- tion information to the cam and its associated register file. the three holding registers contain the lower con- nection address (i.e., time slot), the upper connection address (stream plus control bits), and the tag. an attempt to write to a full cam (all 256 locations fully occupied) results in an overflow error flagged through the system error register, syserr (see section 2.6 error registers). note: a single mkcn command only specifies one half of a connection. the mkcn specifies the con- nection address and a pointer to the data mem- ory, but a second connection address and pointer to the same data memory location must also be provided for a complete connection. * the h-bus cam covering the 16 even-numbered h-bus streams is designated e, the h-bus cam covering the 16 odd-numbered h- bus streams is designated o, and the cam that services the 16 local stream pairs is designated l.
34 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.3 h-bus section (continued) 2.3.2 cam operation and commands (continued) 5-6110f figure 11. illustration of cam cycles apply comparand, i.e., stream + time slot one cycle cam operation: match comparand or get status flags retrieve physical location controls, e.g., search for empty one cycle cam operation: get comparand or tag, or change status flags controls apply physical location to cam, i.e., location 0255 retrieve comparand or data, i.e., get stream + time slot from cam or get tag from pipeline register file apply comparand, i.e., stream + time slot controls flags two cycle cam operations: identify comparand and retrieve tag or identify comparand and change status physical physical location location retrieve data, i.e., get tag from pipeline register file identify hit or empty (flags) then retrieve physical location in cam, i.e., location 0255 out in
lucent technologies inc. 35 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.3 h-bus section (continued) 2.3.2 cam operation and commands (continued) if the user determines that a stream/time slot is no longer valid, then the validity bit may be cleared by pre- senting the connection address to the cam and by using the bkcn, break connection, command. the connection that the user intends to break, which con- sists of the time slot, and the stream plus control bits, but not the tag, is transferred to the holding registers prior to issuing this command. this is a two-cycle com- mand: during the first cycle, the connection address is presented to the cam to identify which physical loca- tion holds that connection address, and then, in the second cycle, the validity bit is cleared for the identified physical location. if there is a miss, it flags a no-match error through the underflow bit in syserr. note: a complete connection break requires two bkcn commands, one for each half of the con- nection, as with the mkcn command. the clear location command, clln, is a one-cycle command. the lar contains the physical address (i.e., the physical cam location) to be cleared. when it is presented to the cam, the validity bit is cleared, return- ing the location to an empty status (i.e., it becomes available for new make connection commands). the clln can also be regarded as the second cycle of a break connection command. clln is valuable if several outputs are driven from a common input (broadcast) and the user wishes to break one of the output connec- tions, but leave the others intact. when the physical location in the cam is identified, either by software tracking or by use of the find entry command (later in this section), then the clln can be issued. if the user wishes to poll the cam for its contents, then the rdcn or read cam command can be used to query a particular location (0255) in a specific block using the lar for the location address. the contents of the cam and tag location are transferred to the holding registers, and then the time slot, stream plus control, and tag are returned (in sequence) from three consec- utive idr reads. the actual rdcn operation is one- cycle. the converse of the rdcn is the fenn, or find entry command. it can be thought of as the first cycle of a bkcn command. only time slot and stream plus con- trol bits are necessary for identifying the location. the tag is not needed. the value returned to the idr is the physical location of the entry in the cam block, if it is found. if the entry is not found, then the underflow error bit in the syserr register will be set. fenn is a one- cycle command. rscn is the reset cam command, and this renders all locations in one cam block invalid. this can be consid- ered a clln for all locations in the cam. two special resets are the rch command, which resets only the holding registers, and the ci command, which resets all three cam blocks and the holding registers. all resets are one-cycle. 2.3.3 h-bus access there are 32 bidirectional pins available for accessing the h-bus. the direction of the pins is selected by the cam read and write bits. data rates for the pins are selected in accordance with the h.100/h.110 specifica- tions. unassigned time slots on the h-bus are 3-stated. details about rate selection are provided below. two bits of the 13-bit address are used to select the cam block as indicated in figure 9. the remaining 11 bits plus a read/write bit form a comparand that is stored in a cam location.
36 36 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.3 h-bus section (continued) 2.3.4 l-bus access the input and output of the cam have the appropriate links to the local stream pins so that the h-bus streams may be routed to and from the local bus streams. the lbs register (section 2.2.4 lbs: local stream control, 0x0c) programs the local stream rates even if accessed by the cams. to address the local bus cam block, the two most significant address bits of the phys- ical address are set to the appropriate values as described in figure 9. the other bits form the com- parand along with a read/write bit. when the cam is outputting data to the local bus, it has priority over the local bus memory. in other words, if both the local bus and h-bus access the same local stream and time slot, the h-bus data memory will provide the actual data, not the local connection. 2.3.5 h-bus rate selection and connection address format operating rates are selected in a manner similar to the local side. two registers, hsh and hsl, shown below, define the operation of the 32 streams. again, sgx refers to stream groups: hsh holds sghsge where sgh programs streams 2831, sgg programs streams 2427, sgf programs streams 2023, and sge programs streams 1619. hsl holds sgdsga where sgd programs streams 1215, sgc programs streams 811, sgb programs streams 47, and sga programs streams 03. sgn = 00, 3-state sgn = 01, 2.048 mbits/s sgn = 10, 4.096 mbits/s sgn = 11, 8.192 mbits/s a quick summary: the cams and the pipeline register files operate as connection memories. the key cam operation is based on 11 bits of stream and time slot plus 1 bit of read/ write in the cam locations compared against the state counter which tracks the current stream and time slots (section 2.2.5 state counter operation). each h-bus cam is looking for matches on 16 of the 32 h-bus streams, and the local cam is looking for a match on 16 local inputs and 16 local outputs per time slot. thirteen bits are required to cover the 5120 possible time slots, but the msb, lsb combination is used to determine which h-bus cam is accessed: even h-bus (0, 0), odd h-bus (0, 1). the local h-bus is accessed by selecting the upper 2 msbs, both equal to 1. the cam address can be thought of as following this for- mat: this format is rate independent. the cam select field is part of the address mode register (amr) for cam com- mands (section 2.1.3 address mode register and sec- tion 2.3.2 cam operation and commands). program- ming examples for setting up connections can be found in section 3.2 basic connections. 2.4 clocking section the clocking section performs several functions which are detailed in the following paragraphs. in general, when the t8100 is a bus master, it will have one or more companion devices which provide the basic clock extraction and jitter attenuation from a source (such as a trunk). as a slave, the t8100 can work independently of, or in conjunction with, external resources. examples of different operating modes are provided in appendix a. refer to figure 12 for a block diagram of the t8100 clocking section. when the t8100 is used as a bus master, an input clock of a tolerance of 32 ppm is required. this can come from several sources. for example: n 32 ppm crystal tolerance is the suggested value if either the dpll is used or fallback to the oscillator is enabled while mastering the bus. otherwise, a crys- tal with a lesser tolerance can be used. n if a crystal is not used, a 16.384 mhz ( 32 ppm toler- ance or less) signal must be provided to the xtalin pin, and xtalout should be left unconnected. n the l_ref inputs can also be used and must con- form to 32 ppm in a bus master situation. sgh sgg sgf sge sgd sgc sgb sga cam select field time-slot field stream field 2 bits 7 bits 4 bits
lucent technologies inc. 37 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.4 clocking section (continued) 5-6111f * the path for xtalin divide-by-4 is for fallback only. figure 12. clocking section x16 x32 x16 4 mhz 2 mhz frame sync dpll netref divide-by-n divide register main divide-by-n divide register clock resource select divide by 4* gp6 gp7 resource divide-by-n divide register netref int/ext select bit slider controls bit slider state machines pll #1 pll #1 bypass rate select 65.536 mhz memory clock pll #2 pll #2 bypass rate select prirefout 4mhzin 3mhzin tclko tclk enable tclk select divide by 2 x 8 net- ref sel. ? by 8 netref select frame sel. these inputs form transceivers with the corresonding outputs /ct_frame_a /ct_frame_b /fr_comp clock sel. clock sel. and input state mach. l_ref0 l_ref7 ct_netref ct_c8_a ct_c8_b /c16 /c4 c2 sclk sclkx2 these inputs form transceivers with the corresponding outputs xtalin todjat/gp6 fromdjat/gp7 djat bypass (and gp6/7 enable) l_sc ctl frame frame sec8k frame frame en_b c8 c8 en_a netref en_netref ct_netref ct_c8_a /ct_frame_a ct_c8_b /ct_frame_b compatibility /ct16 c2 /c4 sclk sclk2 /fr_comp l_sc0 scsel (1 of 4 l_sc[1:3] not shown) 16.384 mhz 2.048 mhz 4.096 mhz 2.048 mhz 4.096 mhz 8.192 mhz 4.096 mhz 8.192 mhz 2.048 mhz 4.096 mhz 8.192 mhz 16.384 mhz dpll#2 ? 2 clocks direction internal control clocks and sync (fallback path*)
38 38 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.4 clocking section (continued) 2.4.1 clock and netref selection the inputs to the t8100 clocking come from three selectors. the clock selector and frame selector oper- ate from a common set of selection options in register ckm (see section 2.4.6 clock control register defini- tions for register details), where framea is selected along with clock c8a and frameb is selected along with clock c8b. typically, one of the local references (lref[0:7]) will be selected when the t8100 is operat- ing as a master, though the local oscillator is also avail- able. as a slave, the most common selections will be one of the bus types. each bus type has a state machine associated with it for determining the frame sync. all clock inputs are sampled to check for proper switching. if the expected clock edge does not occur, and there is no switching on ct_netref for 125 m s, a bit corresponding to the errant clock is set in the clk- err register (see section 2.6 error registers for more details). netref can be created from one of the local references or from the oscillator independent of the clock generation. 2.4.2 dividers and rate multipliers the clock and netref selections are routed to divid- ers*. in the case of netref, the divider is usually used to reduce a bit rate clock to 8 khz, so the most common divisors will be 1, 193 (1.544 mhz/8 khz), and 256 (2.048 mhz/8 khz), although a full range of values (from 1256) is possi- ble. for the clock selector, the signal will most often be routed through the main divider when the t8100 is operating as a master or through the resource divider when operating as a slave. both the main and resource dividers are fully programmable. the ultimate destination for the main or resource divider is intended to be pll #1. pll #1 accepts either a 2.048 mhz or 4.096 mhz input and will rate multiply up to 65.536 mhz. the divisor of the main or resource dividers is chosen in conjunction with the rate select of the pll, i.e., a divisor which generates a 4.096 mhz output and a rate selection of x16, or a divisor which generates a 2.048 mhz output and a rate selection of x32. this provides a great deal of flexibility in adapting to a variety of (external) clock adapters and jitter atten- uators while acting as a master, as well as slaving to several bus types. a digital pll that can rate multiply to either 2.048 mhz or 4.096 mhz from an 8 khz source in the absence of an external clock adapter is also provided. pll #1 can be bypassed for diagnostic purposes or if an external clock adapter is used that provides a high-speed output (65.536 mhz). the input to the dpll is for an 8 khz signal only. a second rate multiplier is provided for supporting t1 applications. it is optimized around either a 1.544 mhz or 3.088 mhz input rate which multiplies to 24.704 mhz and is then divided down to provide 50% duty cycle clocks of 12.352 mhz, though the direct 24.704 mhz is available as well. a bypass is provided so that an exter- nal clock can be buffered through the tclk output. the internal oscillator or the various outputs derived from pll #1 can also be selected for the tclk output. * if the a clocks have been selected as the clock source through the ckm register (described in section 2.4.6 clock control register definitions), then the ct_c8a is the signal sent to the main and resource dividers; likewise, selecting b clocks results in sending ct_c8b; the mvip selection sends /c4; the h- mvip selection sends the recovered /c16 (derived from differential inputs); select- ing sc2 sends sclkx2 ; and sc4/8 sends sclk to the dividers.
lucent technologies inc. 39 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.4 clocking section (continued) 2.4.3 state machines the purpose of the state machines is to generate internal control signals for the remainder of the t8100 circuitry and to provide all bus clocks when operating as a master. the state machines operate from the 65.536 mhz clock generated by pll #1, and they are time referenced to the frame sync derived from the selected clock and frame inputs. as a master, the time sync is based on the t8100s own generated frame. the dominant internal control signals are a noninverted 32.768 mhz clock, an inverted 16.384 mhz state clock, and a noninverted 122 ns wide sync pulse centered around the beginning of a frame. the memories are synchronized to the 65.536 mhz clock. 2.4.4 bit sliding (frame locking) the t8100 generates its own frame signal based on the incoming clock and frame references and its gener- ated clock signals. when slaving, it is sometimes nec- essary to align the edges of this generated frame signal to the incoming frame reference. to accomplish this, the t8100 will compare the referenced frames with the current state of its clock state machine, and if the difference exceeds one 65.536 mhz clock cycle, the entire stream will have a fraction of a bit time removed from each frame; this is referred to as bit sliding. the process will repeat until the measurements fall within one clock cycle. the actual bit sliding will take place by reducing the gener- ated frame by one 65.536 mhz clock cycle at the beginning of the frame. this means that the frame edges will phase-align at the rate of approximately 15.26 ns per frame. the maximum phase difference is slightly less than one frame or 124.985 s. thus, it will require approximately 8000 frames, or 1 second, to phase-align the frame. this is also mean time interval error (mtie) compliant; performing phase adjustment of 162 ns per 1.326 ms of total sample time. refer to the mtie specifications document (att 62411). the alternatives to bit sliding are snap alignment and no alignment. snap alignment refers to an instanta- neous phase alignment, i.e., a reset at the frame boundary. this mode is common to other devices. if no alignment is chosen, the t8100s generated frame is frequency-locked to the incoming frame sync, but not phase-aligned. 2.4.5 clock fallback the following conditions must be met before fallback is initiated: n fallback must be enabled in register cks. n failure of one or more of the clocks selected through the cksel bits in the ckm register. n all clocks which comprise the selection from cksel must be unmasked in register ckw (see section 2.6 error registers). the t8100 contains a fallback register which enables a backup set of controls for the clock resources during a clock failure. in addition, a fallback state machine pro- vides some basic decision-making for controlling some of the clock outputs when the feature is enabled. while slaving to the bus, the primary course of action in fall- back is the swap between the a-clocks and b-clocks as the primary synchronization sources. a slave may become a master only under software control; i.e., there is no automatic promotion mechanism. as a mas- ter, the t8100 can detect its own failures and remove its clocks from the bus. if it detects a failure on the other main set (e.g., b master detects failures on the a mas- ter), then it can assume the role as the primary syn- chronization source by driving all compatibility clocks (h- mvip and sc-bus). clock failures are flagged through the clkerr1 and clkerr2 registers (sec- tion 2.6 error registers). additional fallback details are discussed in relationship to the clock registers in the next section. the divide-by-4 block for xtalin, shown in figure 12, is used only for fallback. see figure 13 for a diagram of the basic state machine which controls the a, b, and c (compatibility) clocks.
40 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.4 clocking section (continued) 2.4.5 clock fallback (continued) 5-6112f figure 13. a, b, and c clock fallback state diagram diag_abc diag_ab c_only b_only b_error b_master a_error a_only a_master initial diagnostic/forced clocking fallback clocking, assumes fallback enabled in cks register b clocks fail b clocks fail a clocks fail a clocks fail a clocks b clocks fail reprogram a clocks reprogram b clocks diag_abc = drives a clocks, b clocks, and c clocks, no fallback permitted diag_ab = drives a clocks and b clocks, no fallback permitted c_only = drives c clocks only, no fallback permitted b_only = drives b clocks, can drive c clocks in fallback condition a_only = drives a clocks, can drive c clocks in fallback condition b_master = drives b and c clocks, all clocks shut off in fallback condition a_master = drives a and c clocks, all clocks shut off in fallback condition b_error = no clocking, waiting for b clocks to be reprogrammed a_error = no clocking, waiting for a clocks to be reprogrammed the t8100 enters and leaves these states fail based on register counters
lucent technologies inc. 41 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.4 clocking section (continued) 2.4.6 clock control register definitions table 39. ckm: clocks, main clock selection, 0x00 the first register, 0x00, is the clock main (ckm) register. there are ten registers to control the various aspects of clocking. * selecting a clocks synchronizes the t8100 to ct_c8a and /ct_framea; selecting b clocks synchronizes the t8100 to ct_c8b and /ct_frameb; mvip uses /c4, c2, and /fr_comp; h- mvip uses /c16+/C, /c4, c2, and /fr_comp; sc2 uses sclkx2 and /fr_comp; sc4/8 requires sclk, sclkx2 , and /fr_comp. mc-1 fallback clocks use the same inputs and state machine as the a clocks and b clocks with an inversion selected from register ckp. a pictorial view of the various clocks may be seen in section 4.6.1 clock alignme nt. reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ckm pae pas ccd cki cksel symbol bit name/description pae 7 phase alignment enable. pae = 0, retains frequency lock without phase alignment pae = 1, enables phase alignment pas 6 phase alignment. pas = 0, phase alignment, snap pas = 1, phase alignment, slide ccd 5 the ccd bit is the compatibility clock direction. this controls the i/o for the compatibility clocks /c16+/C, /c4, c2, sclk, sclkx2 , and /fr_comp (compatibility frame). the user can think of the ccd bit (in some respects) as a master/slave select for the compatibility clocks, though other registers require proper setup to establish true master or slave operation. the t8100 will assume control of this bit during a fallback if the previously designated compatibility clock master fails. ccd = 0, slave, monitors compatibility signals ccd = 1, master, drives compatibility signals note: if bit 4 of the programmable clocks register, ckp, is low, then the state machines of the a clock and b clock will assume this is an mc-1 system and interpret the clocks as /c4(l/r) and frame(l/r). if this bit is high, then it interprets the clocks as c8(a/b) and frame(a/b). cki 4 cki is used to invert the output of the clock selector, i.e., the signal which feeds the main divider, resource divider, and dpll: cki = 0, normal cki = 1, invert cksel 30 the decode for the clock selector (cksel) is illustrated below. these selections determine which input state machine is utilized*: cksel = 0000, internal oscillator cksel = 0001, ct_netref cksel = 0010, a clocks (c8a & framea); ectf or mc-1 cksel = 0011, b clocks (c8b & frameb); ectf or mc-1 cksel = 0100, mvip cksel = 0101, h- mvip cksel = 0110, sc-bus, 2 mhz cksel = 0111, sc-bus, 4 mhz or 8 mhz cksel = 10001111 selects local references 07
42 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.4 clocking section (continued) 2.4.6 clock control register definitions (continued) table 40. ckn: clocks, netref selections, 0x01 clock register 0x01 is ckn, the ct_netref select register. this register selects features for generating and rout- ing the ct_netref signal. reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ckn noe nio ndb nri nrsel symbol bit name/description noe 7 the noe bit enables the netref output: noe = 0, ct_netref output disabled (3-state) noe = 1, ct_netref output enabled (nio must be low) nio 6 the nio bit controls the internal/external selector. it selects either the netref divider for out- puts or the netref input. since the latter is used for routing netref to the local clock out- puts, it will automatically prevent the netref output from being enabled: nio = 0, select netref divider, i.e., netref as output nio = 1, select netref input (disables netref output) note: when the nio bit is high, general-purpose register (gpr), bits 6 and 7 are available. (the gpr is discussed in section 2.5.2 general-purpose register.) ndb 5 ndb = 0, todjat pin comes from netref selector, and fromdjat pin goes to netref divider ndb = 1, netref selector goes directly to netref divider nri 4 nri inverts the output of the netref selector. nri = 0, normal nri = 1, invert nrsel 30 the nrsel is similar to cksel but with fewer choices: nrsel = 0000, internal oscillator divided by 8 nrsel = 0001, internal oscillator nrsel = 00100111, (reserved) nrsel = 10001111, local references 07
lucent technologies inc. 43 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.4 clocking section (continued) 2.4.6 clock control register definitions (continued) table 41. ckp: clocks, programmable outputs, 0x02 clock register 0x02, ckp, is the programmed clocks register. it is used for programming the ct_c8 clocks and enabling its outputs. it is also used to program the tclk selector. ct_c8 may be operated as either 8 mhz (nor- mal or inverted) or 4 mhz (normal or inverted). the register format is as follows: * mc-1 is a multichassis communication standard based on mvip . the t8100 supports this standard. reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ckp pts c8is cae cbe c8c4 cfw symbol bit name/description pts 75 the three pts bits select the output sent to the tclk. this output is intended to be used for driving framers. pts = 000, 3-state pts = 001, oscillator, buffered output pts = 010, pll #2, direct output pts = 011, pll #2, output divided by 2 pts = 100, 2.048 mhz from state machines pts = 101, 4.096 mhz from state machines pts = 110, 8.192 mhz from state machines pts = 111, 16.384 mhz from state machines c8is 4 c8is is used to invert the synchronization on c8a and c8b when they are selected for input. the c8 and frame signals, which are also generated internally, are routed to both the ct_c8a and /ct_framea and to the ct_c8b and /ct_frameb. the cae and cbe pins enable these output pairs independently. the c8c4 pin selects 8.192 mhz or 4.096 mhz sig- nals to be output on c8a and c8b (for supporting for either ectf or mc-1* applications). cfw selects the output width of the compatibility frame. c8is = 0, mc-1 (a and b clocks inputs interpreted as /c4 with /frame) c8is = 1, ectf (a and b clocks inputs interpreted as c8 with /frame) cae 3 cae = 0, disable ct_c8a & /ct_framea outputs cae = 1, enable ct_c8a & /ct_framea outputs (the t8100 will auto- matically disable these on an a clock failure.) cbe 2 cbe = 0, disable ct_c8b & /ct_frameb outputs cbe = 1, enable ct_c8b & /ct_frameb outputs (the t8100 will auto- matically disable these on a b clock failure.) c8c4 1 c8c4 = 0, inverted 4.096 mhz (mc-1 output mode) c8c4 = 1, noninverted 8.192 mhz (ectf output mode) cfw 0 cfw = 0, (reserved) cfw = 1, (reserved)
44 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.4 clocking section (continued) 2.4.6 clock control register definitions (continued) table 42. ckr: clocks, resource selection, 0x03 clock register 0x03, ckr, is the clock resources register. it is used for selecting and programming miscellaneous internal resources, the two plls, the dpll, and the clock resource selector. it is also used to program the sclk/sclkx2 clock outputs. the register format is as follows: reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ckr crs p1b p1r p2b p2r scs symbol bit name/description crs 76 the crs[7:6] bits are used to select the input to pll #1. crs = 00, external input (through the 4 mhz in pin) crs = 01, resource divider crs = 10, dpll @ 2.048 mhz crs = 11, dpll @ 4.096 mhz p1b 5 p1b and p1r control pll #1. p1b = 0, normal pll #1 operation p1b = 1, bypass pll #1 p1r 4 p1r = 0, pll #1 rate multiplier = 16 p1r = 1, pll #1 rate multiplier = 32 p2b 3 p2b and p2r control pll #2. p2b = 0, normal pll #2 operation p2b = 1, bypass pll #2 p2r 2 p2r = 0, pll #2 rate multiplier = 8 p2r = 1, pll #2 rate multiplier = 16 scs 10 the scs[1:0] bits are used to program the outgoing sc-bus compatibility signals. scs = 00, sc-bus outputs 3-stated scs = 01, sclk @ 2.048 mhz, sclkx2 @ 4.096 mhz scs = 10, sclk @ 4.096 mhz, sclkx2 @ 8.192 mhz scs = 11, sclk @ 8.192 mhz, sclkx2 @ phase shifted 8.192 mhz
lucent technologies inc. 45 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.4 clocking section (continued) 2.4.6 clock control register definitions (continued) table 43. cks: clocks, secondary (fallback) selection, 0x04 clock register 0x04 is cks, the secondary clock selection register. this is also referred to as fallback. along with programming the cks register, ckw and cks should be programmed last. the register is defined as follows: * this bypasses the crs/frs multiplexer and is the default condition. it is equivalent to letting the t8100 free run on a clock failure. it assumes pll #1 has been set for x16. if pll #1 is set for x32, then use fcsel = 8 khz local reference, frs = 10, and fts = 10. reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cks frs fts ff fcsel symbol bit name/description frs 76 frs provides an alternate clock resource selection. fts determines the basic fallback mode. ff forces the use of the frs, fts, and fcsel. fcsel is used to select an alternate synchro- nization source. frs forces the clock resource selector to choose a new source for pll #1. frs = 00, external input (through the 4 mhz in pin) frs = 01, resource divider frs = 10, dpll @ 2.048 mhz frs = 11, dpll @ 4.096 mhz note: the decode is the same as that of the crs bits (in the clock resource register, ckr). fts 54 for fallback type select, the two fts bits are used to enable the automatic fallback. these work in conjunction with the various clocks as described in section 2.4.5 clock fallback. if the c8 input select (c8is of the ckp register above) is low, then the t8100 is assumed to be in an mc-1 system. thus, the a/b clocks can be interpreted as /c4l (or /c4r) for c8a and /c4r (or /c4l) for c8b. fts = 00, fallback from main clock to the oscillator divided by 4* when main clock fails. (main clock determined by cksel bits of the ckm register.) fts = 01, fallback disabled; this is not recommended for operation, it is intended for ini- tialization and diagnostic purposes only. fts = 10, fallback from main selection to secondary source (fcsel). fts = 11, fallback from a or b clock (ectf/mc-1) to secondary; this also enables the fallback state machine. when one of the selected bits goes high in the clkerr register (i.e., clock failure, see section 2.6 error registers), then clocks are changed to the selection indicated by fcsel, the a or b clocks are disabled (if applicable), and the compatibility clocks are either driven or disabled (if applicable). note that the change is sticky; once the fallback has occurred, it will stay in its new state until the system is reprogrammed. clearing the clkerr registers through the mcr (section 2.1.2 master control and status register) clears the fallback condition. a bit in the syserr register will also note when a fallback has occurred. ff 3 ff is used as a test of the fallback, but can also be used as a software-initiated fallback. ff = 0, normal operation ff = 1, force use of secondary (fallback) resources fcsel 20 the fcsel choices are a subset of the cksel values from the ckm register above. the list is presented below: fcsel = 000, internal oscillator divided by 4 fcsel = 001, internal oscillator fcsel = 010, a clocks (c8a & framea); ectf or mc-1 fcsel = 011, b clocks (c8b & frameb); ectf or mc-1 fcsel = 100, netref fcsel = 101111, selects local references 13
46 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.4 clocking section (continued) 2.4.6 clock control register definitions (continued) table 44. ck32 and ck10: clocks, locals 3, 2, 1, and 0, 0x05 and 0x06 registers 0x05 and 0x06 set up l_sc0, 1, 2, & 3. the outputs l_sc[3:0] can be used as bit clocks for the local streams or as a secondary netref. these are programmed using ck32 and ck10, which are presented below: reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ck32 lsc3 lsc2 ck10 lsc1 lsc0 register bit symbol name/description ck32 74 lsc3 lscn = 0000, output low lscn = 0001, local frame lscn = 0010, netref (sec8k) lscn = 0011, pll #2 1 2 lscn = 0100, 2.048 mhz lscn = 0101, 4.096 mhz lscn = 0110, 8.192 mhz lscn = 0111, 16.384 mhz lscn = 1000, output high lscn = 1001, local frame, inverted lscn = 1010, netref, inverted lscn = 1011, pll #2 1 2, inverted lscn = 1100, 2.048 mhz, inverted lscn = 1101, 4.096 mhz, inverted lscn = 1110, 8.192 mhz, inverted lscn = 1111, 16.384 mhz, inverted ck32 30 lsc2 ck10 74 lsc1 ck10 30 lsc0 2.4.7 ckmd, cknd, ckrd: clocks, main, netref, resource dividers, 0x07, 0x08, and 0x09 the remaining clock registers are used to program the three dividers. the main divider is programmed through ckmd; the netref divider, through cknd; and the resource divider, through ckrd. the dividers are fully programmable, but only binary divides (1, 2, 4, 8, etc.) and divide by 193 produce 50% duty-cycle out- puts. all other divisors will produce a pulse equal to one-half of a (selected) clock cycle in width. 0x00 => divide by 1 (bypass divider) 0x01 => divide by 2 : 0xc0 => divide by 193 : 0xff => divide by 256 in general, the register value is the binary equivalent of the divisor-minus-one; e.g., an intended divisor of 193 is reduced by 1 to 192, so the register is loaded with the binary equivalent of 192 which is 0xc0. 2.5 interface section 2.5.1 microprocessor interface the grouping of the read, write, chip select, and address latch enable signals, along with the data bus and the address bus, permit access to the t8100 using intel nonmultiplexed interface (ale = low), motorola nonmultiplexed interface (ale = high), or intel multi- plexed interface (ale = active). ale controls the micro- processor mode. all control and status registers and data and connection memory accesses are controlled through this interface. all accesses are indirect, follow- ing the pin descriptions in table 1 and table 2. pro- gramming examples and a more detailed discussion of the indirect accesses can be found in section 3 using the t8100.
lucent technologies inc. 47 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.5 interface section (continued) 2.5.2 general-purpose register a simple, general-purpose i/o register is available. the gpr has eight dedicated pins to the t8100. a write to the register forces it to operate as an output. it remains as an output until a read from the register is performed (which 3-states the output). the register powers up in the input state with a cleared register. the gpr corre- sponds with i/o pins gp[0:7]. gp6 and gp7 are unavailable if bit 5 of register ckn is low (see section 2.4.6 clock control register definitions). 2.5.3 framing groups two groups of frame pulses are available. each frame group consists of 12 lines which are enabled sequen- tially after a programmed starting point. they are denoted as group a and group b. this section describes framing group a. framing group b is made up of similar registers. each frame group is controlled by a pair of registers: frha and frla control the spacing of the 12 frame pulses, their pulse width, polarity, and the offset of the first pulse from the frame boundary. table 45. frha, frame group a high address and control, 0x21 table 46. frhb, frame group b high address and control, 0x23 reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frha rate type fai hi start symbol bit name/description rate 76 rate = 00, frame group disabled, 3-state rate = 01, 2.048 mbits/s rate = 10, 4.096 mbits/s rate = 11, 8.192 mbits/s type 54 type = 00, bit-wide pulse type = 01, double bit-wide pulse type = 10, byte-wide pulse type = 11, double byte-wide pulse fai 3 fai = 0, normal pulse fai = 1, inverted pulse hi start 20 hi start = upper 3 bits of group start address or programmed output reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frhb rate type fai hi start symbol bit name/description rate 76 rate = 00, frame group disabled, 3-state rate = 01, 2.048 mbits/s rate = 10, 4.096 mbits/s rate = 11, 8.192 mbits/s type 54 type = 00, bit-wide pulse type = 01, double bit-wide pulse type = 10, byte-wide pulse type = 11, double byte-wide pulse fai 3 fai = 0, normal pulse fai = 1, inverted pulse hi start 20 hi start = upper 3 bits of group start address
48 48 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.5 interface section (continued) 2.5.3 framing groups (continued) the 12 outputs of the frame group are pulsed in sequence, one every 8 bit times, where the bit time is set by the rate option. thus, the rate option controls the spacing between output pulses. the pulse width is set by the type option, and the pulse polarity is set by the fai bit. note that double byte-wide types will produce overlapping pulses. the remaining bits (3 hi-start bits in frha and 8 bits of frhb) make up an 11-bit start address that sets the offset of the groups first output (pin fga0) relative to the frame boundary. the offset is in increments of 61 ns (1/16.384 mhz). thus, 2 11 values corresponding to the 11-bit start address allow programming offsets from 0 ns to 125 m s. notice that the resolution is less than 1 bit. for example, if the frame group clock is pro- grammed to 2.048 mhz, the resolution is 0.125 of a bit. the frame boundary, shown in figure 19 through fig- ure 21, is the point where /ct_frame is low and ct_c8 is starting its low-to-high transition. at zero offset, the rising edge of the first frame group output is coincident with the rising edge of the 8 mhz, 4 mhz, and 2 mhz of the l_sc[3:0] clocks that occur in the center of the ct_frame. this defines the start of the frame, and the start of the first bit of the first time slot on both the ct bus and local input and local output buses. in addition to sequenced pulses, the frame groups can be used as simple programmed output registers. when group a is used as a programmed output, the bits are sent from the frla [0x20] and frha [0x21] registers. bits [0:7] of the programmed output come from bits [0:7] of frla [0x20]. bits [8:10] of the programmed output come from the high start (bits [0:2]) of frha [0x21], and bit 11 of the programmed output comes from the fai bit (bit 3) of frha [0x21]. when group b is used as a programmed output, bits 0:7 of the output come from bits 0:7 of separate register frpl [0x24], and bits [8:11] of the output come from bits 0:3 of another register frph [0x25]. the upper nibble of frph [0x25] also has output routing functions associ- ated with it. register frph [0x25] is illustrated below; see figure 14 for a diagram of the selection options. table 47. frph: frame group b, programmed output, high, 0x25 reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frph fao x fbo hi prog symbol bit name/description fao 76 fao = 00, frame group a bits [0:11] on output pins [0:11] fao = 01, programmed output a bits [0:11] on output pins [0:11] fao = 10, frame group a bits [0:5] on output pins [0:5], and frame group b bits [0:5] on output pins [6:11] fao = 11, programmed output a bits [0:5] on output pins [0:5], and frame group b bits [0:5] on output pins [6:11] x 5 x (reserved) fbo 4 fbo = 0, frame group b routed to group b output pins fbo = 1, programmed output b routed to group b output pins hi prog 30 high prog = upper 4 bits of programmed output b note: in the programmed output mode, the rate must not equal 00; otherwise, the outputs corresponding to the group bits are 3-stated; the rate will have no effect other than enabling the mode. type bits have no effect in the programmed modes.
lucent technologies inc. 49 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.5 interface section (continued) 2.5.3 framing groups (continued) 5-6113f figure 14. frame group output options fao frame group a, bits [0:5] programmed output a, bits [0:5] frame group a, bits [6:11] programmed output a, bits [6:11] frame group b, bits [0:5] frame group b, bits [0:11] programmed output b, bits [0:11] fbo fga[0:5] fga[6:11] fgb[0:11] t8100 internal signals t8100 output pins
50 50 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.6 error registers four error registers are present in the t8100: n clkerr1 [0x28] n clkerr2 [0x29] n ckw [0x2b] n syserr [0x2a] when programming the clock registers, writing to ckw and cks should be programmed last. these are the clock error, watchdog enable, and sys- tem error registers. the clkerr1 register is used to indicate failing clocks, and the clkerr2 indicates whether the failure is permanent or transient in nature. if the clocks fail, i.e., disappear or momentarily drop out, then corresponding bits in both registers will be set. if the clock is reestablished, i.e., a transient error, then the t bit(s) will clear, but the e bit(s) will remain set. all of the e bits are ored together and drive the clkerr pin. the clocks listed above are sampled by the 16.384 mhz internal clock. effectively, each clock has a watchdog. if the clock is switching, the watchdog clears. if the clocks stop, then the watchdog sets the appropriate e and t bits. if the clock is reestablished, then the e bits remain stuck, but the t bits clear with the watchdog. since fallback is triggered on the e bits, a transient clock can force a fallback. table 48. clkerr1 and clkerr2: error indicator and current status, 0x28 and 0x29 table 48 describes both clkerr1 and clkerr2: the ckw register works in conjunction with the two registers above and with the clock circuitry. it is used to enable the watchdogs for the clock lines. ckw uses the same mapping as clkerr1 and clkerr2, so, for example, a high in bit 7 will enable the watchdogs for ct_c8a and /ct_framea. ckw functions as a masking register for clkerr1 and clkerr2. if the appropriate bit is not set, then a failing clock will not be reported. the syserr register is shown below, the bits are ored together with the clkerr1 bits which, in turn, drives the syserr pin. the syserr bits are sticky as are the clkerr1 bits so they must be reset by clearing the register by setting a bit in the mcr (sec- tion 2.1 register/memory maps). table 49. syserr: system error register, 0x2a table 49 describes syserr: * this error bit is selective. it will only flag an error if the clocks that fail correspond to the selected clock mode. for example, if mvip mode is selected (in register ckm), the proper fallback mode has been set (in register cks), and the mvip clocks are not masked (register ckw, above), then fbe will go high when a failure is detected on /fr_compn, c2, or /c4. thus, unmasked, failing non- mvip clocks will be flagged in the clkerr1 and clkerr2 regis- ters but will not set the fbe flag in syserr. name bit name/description cae cat 7 ca => reports failures on ct_c8a or /ct_framea cbe cbt 6 cb => reports failures on ct_c8b or /ct_frameb cfe cft 5 cf => reports failures on /fr_comp c16e c16t 4 c16 => reports failures on /c16+ or /c16C c42e c42t 3 c42 => reports failures on /c4 or c2 sce sct 2 sc => reports failures on sclk sc2e sc2t 1 sc2 => reports failures on sclkx2 nre nrt 0 nr => reports failures on ct_netref name bit name/description cue 7 cue => even cam underflow, set by an unmatched comparison cuo 6 cuo => odd cam underflow, set by an unmatched comparison cul 5 cul => local cam underflow, set by an unmatched comparison coe 4 coe => even cam overflow, set by a write to a full cam coo 3 coo => odd cam overflow, set by a write to a full cam col 2 col => local cam overflow, set by a write to a full cam (res) 1 res reserved bit position fbe 0 fbe => fallback enabled, status which indicates that a clock error has occurred and fall- back operations are in effect*.
lucent technologies inc. 51 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.7 the jtag test access port 2.7.1 overview of the jtag architecture tap a 5-pin test access port, consisting of input pins tck, tms, tdi, tdo, and trst, provides the standard interface to the test logic. trst is an active-low signal that resets the circuit. tap controller the tap controller implements the finite state machine which controls the operation of the test logic as defined by the standard. the tms input value sampled on the rising edge of tck controls the state transitions. the state diagram underlying the tap controller is shown below. instruction register (jir) a 3-bit scannable jtag instruction register that communicates data or commands between the tap and the t8100 during test or hds opera- tions. boundary-scan register (jbsr) a 211-bit jtag boundary-scan register containing one scannable register cell for every i/o pin and every 3-state enable signal of the device, as defined by the standard. jbsr can capture from parallel inputs or update into parallel outputs for every cell in the scan path. jbsr may be config- ured into three standard modes of operation (extest, intest, and sample) by scanning the proper instruction code into the instruction reg- ister (jir). an in-depth treatment of the boundary-scan register, its physi- cal structure, and its different cell types is given in table 51. bypass register (jbpr) a 1-bit long jtag bypass register to bypass the boundary-scan path of nontargeted devices in board environments as defined by the standard. 2.7.2 overview of the jtag instructions the jtag block supports the public instructions as shown in the table below. table 50. t8100 jtag instruction set instruction mnemonics instruction codes public/private mode description extest 000 public select b-s register in extest mode sample 001 public select b-s register in sample mode reserved 010 reserved 011 reserved 100 reserved 101 reserved 110 bypass 111 public select bypass register
52 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional description (continued) 2.7 the jtag test access port (continued) 2.7.3 elements of jtag logic table 51. t8100 jtag scan register cell type signal name/function 66 i ck_3mhzin 67 o syserr 68 o clkerr 0 cc controls cells 67:68 6976 bdir d[0:7] 1 cc controls cells 69:76 77 i restn 78 o rdy 79 i wrn 80 i rdn 81 i csn 82 i ale 83 i a0 84 i a1 8588 o l_sc[0:3] 44 cc controls cells 85:88 8996 i l_ref[0:7] 97 i ck_4mhzin 98 o prirefout 45 cc controls cell 98 99 o testout1 100 o refclk1o 46 cc controls cells 99, 100 101 bdir fromdjat 43 cc controls cell 101 102 bdir todjat 42 cc controls cell 102 103108 bdir gp[5:0] 41 cc controls cells 103108 109120 o fgb[11:0] 63 cc controls cells 109120 121132 o fga[11:0] 64 cc controls cells 121132 133 bdir c16n_minusa 134 bdir c16n_plusa 135 bdir c4n 136 bdir c2 5 cc controls cells 133136 137 bdir sclkx2na 7 cc controls cell 137 138 bdir sclka 6 cc controls cell 138 139 bdir ct_c8_ba 140 bdir ct_frame_bna 3 cc controls cells 139140 141 bdir frn_compa 4 cc controls cell 141 142 bdir ct_netref 8 cc controls cell 142 143 bdir ct_c8_aa 144 bdir ct_frame_ana 2 cc controls cells 143144 145176 bdir ct_d[0:31] 940 cc controls cells 145176 177192 o ldo[0:15] 4762 cc controls cells 177192 193 o xcs 0 cc controls cell 193 194209 i ldi[0:15] 210 o pmctclko 65 cc controls cell 65 cell type signal name/function
lucent technologies inc. 53 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.8 testing and diagnostics there are several testing operations available for the t8100: n jtag n forced output testing n onboard diagnostics during manufacturing, the t8100 is run through stan- dard functional and electrical testing. 2.8.1 testing operations jtag is used primarily to test the array portion of the t8100. it will not provide coverage for the cams, regis- ter files, srams, or plls. in jtag, the manufacturer provides a drop-in control block and scan-chain which ties internal points to registers on the periphery of the t8100, which are, in turn, tied to the i/o pins. serial bit patterns are shifted into the t8100 through the tdi pin, and the results can be observed at the i/o and at a cor- responding jtag serial output, tdo. since this jtag conforms to the jtag standard, the tdi and tdo can be linked to the jtags of other devices for systemic testing. the tts pin must be low for jtag operations to work. the tts pin has an internal pull-down resistor that defaults the t8100 to jtag operations. in forced output testing, the outputs are set to a particu- lar state to measure their dc parameters. this can also be used in applications for board-level diagnostics. forced output testing is selected by setting the tts (test type select) pin high. in this mode, the jtag clock pin, tck, will act as an input pin. all outputs will be enabled, and each output provides either an inverting or normal response to the input pin. adjacent pins alternate inverting and normal function (i.e., a checker- board pattern). 2.8.2 diagnostics the t8100 has onboard diagnostic modes for testing the frame groups, srams and cams, and some inter- nal structures. these are intended for testing some of the t8100 resources while it is in an application envi- ronment (rather than a manufacturing test environ- ment). the diagnostics allow critical internal nodes to be out- put through the frame groups, or to have the frame groups operated in special cyclical manner, or to pro- vide automatic filling of all memories (including cams) with one of four selected patterns. the diagnostics are activated and selected using three registers: diag1 [0x30], diag2 [0x31], or diag3 [0x32]. diag1 is used to select the frame group pins as either monitors for internal nodes or normal operation (i.e., as frame groups or programmed outputs). diag1 is also used to control the memory fill diagnostic. diag2 and diag3 modify the normal operation of the frame groups and the main state counter. normally, the frame groups begin their cascade sequence when the state counter (i.e., the frame-synchronized master counter of the t8100) reaches a value equal to the frame groups starting address. diag2 and diag3 allow the state counter to be modified for one of two dif- ferent tests.
54 54 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 2 architecture and functional descrip- tion (continued) 2.8 testing and diagnostics (continued) 2.8.2 diagnostics (continued) the three registers are presented in order below: the register fields are interpreted as follows: dfadiagnostics, frame pin selects, group a: dfn = 00, normal operation dfn = 01, state counter bits [10:0] routed to frame group pins [10:0], pin 11 = l dfn = 10, even cam hit routed to pin 11, pin 10 has odd cam hit, pins [9:0] have local data memory address dfn = 11, pin 11 gets cue error bit, pin 10 gets cuo error bit, pin 9 gets cul error bit, pin 8 gets coe error bit, pins [5:0] get page pointers 8 mhz read, 8 mhz write, 4 mhz read, 4 mhz write, 2 mhz read, and 2 mhz write dfbdiagnostics, frame pin selects, group b: dfn = 00, normal operation dfn = 01, state counter bits [10:0] routed to frame group pins [10:0], pin 11 = l dfn = 10, cam state register [1:0] indicating four sub- states, routed to pins [11:10], and local con- nection memory address routed to pins [9:0] dfn = 11, pin 11 gets local cam hit flag, and pins [10:0] get cam state counter dmfdiagnostics, memory, fill test enable: dmf = 0, normal operation dmf = 1, fill all memories with the pattern selected by dmp dmpdiagnostics, memory, fill test pattern select: dmp = 00, checkerboard 0even locations get 0x55, odd locations get 0xaa dmp = 01, checkerboard 1even locations get 0xaa, odd locations get 0x55 dmp = 10, data locations equal address bits [7:0] (cams are filled with their physical address) dmp = 11, data locations equal inverted address bits [7:0] dmddiagnostics, memory, done indicator: this is a status bit which indicates that the chosen memory pattern has been written to all locations. addi- tional writes to the memory are disabled and reads are enabled. this condition remains until the user clears this bit. dfcdiagnostics, frame groups cycle test mode: dfc = 0, normal operation dfc = 1, cycle test mode enabled; forces the frame groups to constantly cycle without waiting for a frame signal to synchronize the start. dsbdiagnostics, state counter, break carry bits: dsb = 0, normal operation dsb = 1, breaks the carry bits between the subsec- tions of the state counter so that the state counter is operating as three counters run- ning in parallel. (this can be viewed on the frame pins using the dfn = 01 selection described above.) status counter bits [0:3] and [4:7] run as modulo-16 counters, and bits [8:10] run as a modulo-8 counter. dxfdiagnostics, external frame input: dxf = 0, normal operation dxf = 1, forces /fr_comp to act as a direct input signal for t8100 framing. this effectively bypasses the internally generated frame sig- nal. the user is again cautioned since the external frame can operate asynchronously to the generated clocks if care is not taken. dsediagnostics, state counter, enable parallel load: dse = 0, normal operation dse = 1, forces the state counter to load the value held in dsh and dsl and continuously cycle as a modulo-n counter where the n value is determined by (dsh and dsl). with the dse pin high, the state counter is no longer syn- chronized to the frame signal. dshdiagnostics, state counter, high bits of par- allel load: dsh = state counter bits [10:8] dsldiagnostics, state counter, low bits of par- allel load: dsl = state counter bits [7:0] dfa dfb dmf dmp dmd dfc dsb dxf (res.) dse dsh dsl
lucent technologies inc. 55 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 3 using the t8100 3.1 resets 3.1.1 hardware reset a hardware reset utilizes the (active-low) reset pin. on activation, it immediately places all outputs into 3-state. individual output sections must be reenabled by setting the appropriate bits high in the mcr register. internally, the local memory is in an undefined state, all cam empty bits are set, all state machines are reset, and all registers are cleared to zero. 3.1.2 software reset this is accomplished by setting the msb of the master control and status register (see section 2.1.2 master control and status register). the local and h-bus con- nections are rendered invalid, all registers are cleared except mcr, clkerr1, clkerr2, and syserr (these registers are cleared with separate mcr control bits); the state machines are also reset. applying the value 0xe0 to the mcr is a full software reset. applying 0x0e enables all pin groups (though individual pins still require setup). this soft reset is clocked by the crystal oscillator. 3.1.3 power-on reset no power-on reset is available. it is expected that the host microprocessor or applications board will provide an external control to the reset pin for performing a hardware reset. the plls must not be enabled prior to establishing a stable supply voltage. there are two methods to accomplish this: n tie the en1 and en2 pins to the same line that drives the reset which forces the plls into an off condi- tion while the t8100 resets asynchronously. n add external capacitors from en1 to ground and from en2 to ground. (the values of the capacitors should be 1 f or greater.) the capacitors will form rc cir- cuits with the en1 and en2 internal pull-ups and will charge up to enable the plls after several millisec- onds. the rc circuit affects the power-on reset for the plls. the long rise time provides some delay. 3.2 basic connections at a minimum, the t8100 requires power, ground, and a 16.384 mhz crystal (or 16.384 mhz crystal oscilla- tor). it is also recommended that the internal plls be treated as other analog circuits are, so the user should provide the appropriate filtering between the pll1v dd and v dd pins (as well as pll2v dd and v dd pins). the rdy pin is operated as an open collector output. it is actively driven low or into 3-state. the user should apply a pull-up (e.g., 10 k w ) to maintain standard microprocessor interfacing. it is recommended that the 10 k w be tied to 3.3 v (since the t8100s nominal v oh is 3.3 v), but the resistor may also be tied up to 5 v without damaging the device. pll connections are shown in figure 15. the h.100/h.110 clock signals, ct_c8_a, ct_c8_b, /ct_frame_a, /ct_frame_b, and ct_netref each require an individual external pull-up of 100 k w to 5 v or 50 k w to 3.3 v. 5-6114.af figure 15. external connection to plls t8100 rdy pllv dds pllgnd s v dd = 3.3 v 25 w tantalum 10 k w 50 k w netref, c8s, and frames 33 m f
56 56 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 3 using the t8100 (continued) 3.2 basic connections (continued) 3.2.1 physical connections for h.110 figure 16 shows the t8100 physical connections required for use in an h.110 environment. there are electrical differences between h.100 and h.110. for h.110, external components are required to meet spec- ifications. figure 16 shows the t8100 netref termi- nations and the required terminations for ct_c8a, ct_framea, ct_c8b, and ct_frameb. each sig- nal has a mechanism to short the 33 w series resistor and, in addition, a 10 k w pulldown resistor. the 50 k w internal pull-ups on the ct data bus are used for h.100. for h.110, the dpue pin should be tied low, disabling these internal pull-ups. h.110 requires the ct data bus to have pull-ups of 18 k w to 0.7 v. the control leads of the fet switches would typically go to the microprocessor. 3.2.2 h.100 data pin series termination all data bus lines must have a 24 w series resistor, even if only data lines 1631 are used at 8.192 mbits/s. 3.2.3 pc board considerations there are no special requirements for the thermal balls on the bga package when designing a printed-circuit board. 5-7142f figure 16. physical connections for h.110 18 k w v pull-up = 0.7 v ct_netref ct_framea ct_frameb ct_c8b ct_netrefb ct_netrefa sclkx2 ctd[0:31] rdy and pll ct_c8b sclk ct_frameb ct_framea sclk 33 w lucent t8100 connections are the same as in h.100 ct_c8a 10 k w ctc8a_src 33 w 10 k w ctc8a_src 33 w 10 k w ctc8b_src 33 w 10 k w ctc8b_src 0 w depopulate ct_c8a sclkx2 0 w depopulate ctd[0:31] 24 w dpue 0.7 v 18 k w 32 18 k w v pull-up = 0.7 v 24 w 24 w ctr_netb ctr_neta
lucent technologies inc. 57 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 3 using the t8100 (continued) 3.3 using the lar, amr, and idr for con- nections 3.3.1 setting up local connections local connections require a physical location in the local connection memory corresponding to the output stream and time slot. the location contains a pointer to a local data memory location which holds the actual data that has come in or will be sent out. the local memories are based on 1024 locations, so 10 bits are required to specify the physical memory location where a connection is placed or where data is stored. to sim- plify the programming, the user supplies 11 bits in a stream and time-slot format, which is converted by the t8100 to the appropriate physical location. relative to describing a connection, a data memory location corre- sponds with the from stream and time slot, and a connection memory location corresponds with the to stream and time slot. to program a connection, the user loads the data memory location into the connec- tion memory location, effectively identifying where the data resides. the user programs 7 bits of the lar for the time-slot value (or 8 bits for pattern mode) and the lowest 4 bits of the amr for the stream value; these will then be con- verted to the physical memory address. the upper bits of the amr select which field in the connection mem- ory is being written into. since the connection informa- tion itself is 15 bits, two transfers (i.e., two fields) must be made to the address in the connection memory. in each case, the transfer is an indirect write of data to the indirect data register, the idr: the first transfer is the lowest 7 bits (time-slot address) of the desired data memory location. it is placed in the idr after the lar and amr have been set up with the appropriate con- nection address. table 52 illustrates the decoding of the time-slot bits (address value in the table refers to the hex value of the 7 bits comprising time slot). when programming the registers for fallback, the cks and ckw registers should be programmed last. table 52. time-slot bit decoding address value 2 mbits/s time slot 4 mbits/s time slot 8 mbits/s time slot 0x00 0 0 0 0x01 1 1 1 0x02 2 2 2 0x03 3 3 3 0x04 4 4 4 0x05 5 5 5 0x06 6 6 6 0x07 7 7 7 0x08 8 8 8 0x09 9 9 9 0x0a 10 10 10 0x0b 11 11 11 0x0c 12 12 12 0x0d 13 13 13 0x0e 14 14 14 0x0f 15 15 15 0x10 16 16 16 0x11 17 17 17 :::: 0x1e 30 30 30 0x1f 31 31 31 0x20 na 32 32 :::: 0x3e na 62 62 0x3f na 63 63 0x40 na na 64 :::: 0x7e na na 126 0x7f na na 127
58 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 3 using the t8100 (continued) 3.3 using the lar, amr, and idr for connections (continued) 3.3.1 setting up local connections (continued) table 53. idr: indirect data register, local connections only the second transfer requires that data in the idr be defined as follows: after the second transfer is made, the entire 15 bits will be loaded into the connection memory; i.e., the second transfer triggers the actual memory access. figure 17 shows how the connections are made from the perspective of the registers and memory contents. if the user wishes to set up a pattern mode connection, then the first transfer is a full 8 bits (i.e., the pattern), rather than the 7-bit time-slot value. this pattern byte will be stored in the lowest 8 bits of the selected connection memory location. the pattern byte will be sent instead of a byte from local data memory during the output stream and time slot which corresponds to the connection memory location. 5-6115af figure 17. local-to-local connection programming reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 idr control address xcspmefmeche symbol bit name/description xcs 7 a programmable bit which is routed to the xcs pin one time slot prior to the data to which it relates. pme 6 a high enables the pattern mode; the lower 8 bits of the connection address (time slot and stream lsb) is routed to the time slot instead of data. fme 5 a high enables the use of the alternate data buffer; refer to appendix b for minimum and constant delay settings. che 4 enables the time-slot connection; a low in this bit forces 3-state during the time slot. address 30 all 4 bits are used for the stream address of the desired data memory location. 0000 0111 3, 27 3, 28 3, 29 3, 30 3, 31 connection memory 0100 0011 0001 1101 0000 0111 amr lar idr write to time-slot field in first transfer: 0000 0111 0001 1110 3, 27 3, 28 3, 29 3, 30 3, 31 connection memory 0101 0011 0001 1101 0001 1110 amr lar idr write to field in memory second transfer: local memory programming example: connect from 14, 7 to 3, 29 (stream, time slot) connection memory connection control/stream
preliminary data sheet august 1998 lucent technologies inc. 59 h.100/h.110 interface and time-slot interchanger ambassador t8100 3 using the t8100 (continued) 3.3 using the lar, amr, and idr for connections (continued) 3.3.2 setting up h-bus connections table 54. idr: indirect data register, h-bus connections only reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 idr control address r/w pmefme symbol bit name/description r/w 7 refers to the direction in the cam data memory. a read sends data to the bus; a write loads data from the bus. pme 6 pattern mode enable, similar to above, except the tag byte is output instead of the lower address bits. fme 5 data buffer selection for setting delay type. (refer to appendix b for minimum and constant delay setting.) address 40 all 5 bits are used for the stream address of the desired data memory location. the cam blocks are 256 locations each and the opera- tions for the cam blocks are selected by amr (see section 2.1.3 address mode register and section 2.3.2 cam operation and commands). since the block address is carried in the amr, this reduces the number of bits which are necessary to establish a connection. eleven (11) address bits, i.e., bits for stream and time- slot identification, the 8-bit tag (pointer to the h-bus data memory), and 3 control bits all need to be written into the selected cam block for setting up a connec- tion. (the empty bit is a status bit that is changed inter- nally as a result of operations on the cam.) three transfers, indirect writes through the idr, are required to set up a connection in the cam, though the method of transfer is different than with the local memory. since a specific physical address is not always necessary, the cam will automatically fill the first available slot. thus, the lar is not required for setting up the connection. (see the notes below.) the first transfer after program- ming the amr requires that the 7 bits which identify the time-slot number (refer to section 2.3.5 h-bus rate selection and connection address format for the proper format) be loaded into the idr. the second transfer uses a similar field description for the idr as presented for local connections (section 3.3.1 setting up local connections above). the address field con- tains the stream number (5 bits), and the control field contains only three control bits. the third (and final) transfer for cam connection setup is the transfer of the 8-bit tag field. the tag is loaded into the idr. the connection for the cam is actually set up, i.e., the memory access takes place, using a fourth write. it is an indirect write to the amr (again through the idr) which corresponds with the specific command and blocks the user requests. all cam commands require that the idr be loaded with the same command value as the amr rather than a dont care or dummy value. notes: if an address is to be matched, such as the break connection command, then only the first two transfers are required. the tag is unneces- sary for identifying a connection. the lar is only used to read or query a spe- cific location (i.e., 0255) in a particular cam block. refer to section 2.1.3 address mode register and section 2.3.2 cam operation and commands for details on these com- mands. for the cams, pattern mode is a 1/2 connection. only the intended output to the h-bus (or to the local pins) needs to be specified. the setup is the same as described above, three transfers to the holding regis- ters followed by the make connection command to the appropriate cam block. when the address is matched, the tag value (from the pipeline sram) will be sent as output to the bus. figure 18 illustrates how a cam connection is made from the perspective of registers and the memory loca- tions. note that each half of the connection, that is the from and the to, requires a separate setup, though each half will point to the same location in the h-bus data memory. following figure 18, some simple programming exam- ples are shown using pseudoassembler code. the local-to-local and h-bus-to-local switching examples from figure 17 and figure 18 are reused in code exam- ples #2 and #3. the connections are referred to in stream, time-slot format.
60 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 3 using the t8100 (continued) 3.3 using the lar, amr, and idr for connections (continued) 3.3.2 setting up h-bus connections (continued) 5-6116f a. first half of connection, h-bus side figure 18. cam programming, h-bus-to-local connection 0000 0111 1011 0000 xxxx xxxx 0000 0111 amr lar (unused) idr write to time-slot first transfer: cam programming example: connect from h-bus 14, 7 to local 3, 29, keep data in location 49 ctls/stream location usednot empty holding register time slot tag holding registers 1011 0001 xxxx xxxx 000 01110 amr lar (unused) idr write to controls/stream second transfer: ctls/stream holding register time slot tag holding registers 1011 0010 xxxx xxxx 0011 0001 amr lar (unused) idr write to tag third transfer: ctls/stream holding register time slot tag holding registers 1110 0000 xxxx xxxx 1110 0000 amr lar (unused) idr (must = amr) transfer holding load cam: ctls/stream registers to next free time slot tag holding registers : 0000 0111 000 01110 0000 0111 direction bit: from bus to data memory 000 01110 0000 0111 0011 0001 data location 49 location in even cam 0011 0001 0000 0111 000 01110 (not empty) (empty) (location usednot empty) (location not usedempty) 000 01110 0000 0111 even cam pipeline sram
lucent technologies inc. 61 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 3 using the t8100 (continued) 3.3 using the lar, amr, and idr for connections (continued) 3.3.2 setting up h-bus connections (continued) 5-6117f b. second half of connection, local side figure 18. cam programming, h-bus-to-local connection (continued) 0011 0001 1011 0000 xxxx xxxx 0001 1101 amr lar (unused) idr write to time-slot first transfer: cam programming example (continued): connect from h-bus 14, 7 to local 3, 29, keep data in location 49 ctls/stream location usednot empty holding register time slot tag holding registers 1011 0001 xxxx xxxx 100 00011 amr lar (unused) idr write to controls/stream second transfer: ctls/stream holding register time slot tag holding registers 1011 0010 xxxx xxxx 0011 0001 amr lar (unused) idr write to tag third transfer: ctls/stream holding register time slot tag holding registers 1110 0011 xxxx xxxx 1110 0011 amr lar (unused) idr (must = amr) transfer holding load cam: ctls/stream registers to next free time slot tag holding registers 0001 1101 100 00011 0001 1101 direction bit: to bus from data memory 100 00011 0001 1101 0011 0001 data location 49 location in local cam 0011 0001 0001 1101 100 00011 (not empty) (empty) (location usednot empty) (location not usedempty) 100 00011 0001 1101 next free location local cam pipeline sram
62 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 3 using the t8100 (continued) 3.3 using the lar, amr, and idr for connections (continued) 3.3.3 programming examples ;all programming examples included are in a pseudoassembler format. ;the basic commands used are the move direct and move indirect. ;a move direct command is indicated by the letters md followed by ;the register name, then the data. similarly, a move indirect command ;is indicated by the letters mi followed by the register name, then by ;data or another register reference (the register may not be indirect). ;the semicolon delineates comments. direct data is followed by the ;letter h for hex and b for binary. ;*******example #1 - set up clocks, local bus, h-bus, and framers ; ;*******misc. stuff ; md,amr,00h ;define control space ;all specific register names are equivalent ;to the lar addresses (from table 11) ; ; ;*******set up clocks ;**main clock register md,idr,0c2h ;load idr with values for bit slider on, slave mode, ;and synced to ectf bus a clocks mi,ckm,idr ;the data in idr is moved into ckm via the lar register. ; ;**netref registers md,idr,88h ;set up netref from local reference 0, 2.048 mhz bit clock in, divided value ;value out (i.e., 8 khz), enable the djat connections mi,ckn,idr ;move the data to ckn md,idr,0ffh ;set up netref divider with divide-by-256 mi,cknd,idr ;move the data to cknd ; ;**programmable clocks md,idr,26h ;this selects the oscillator for the tclko, a clock outputs off, and ;driving ectf b clocks mi,ckp,idr ;move the data ; ;**clock resources md,idr,40h ;synced to bus so select resource divider, x16 on pll #1 & x8 pll #2, sc clocks off mi,ckr,idr ;make it so md,idr,01h ;set up resource divider with divide-by-2 for 4 mhz signal into pll #1 mi,ckrd,idr ;move the data to divider ;
lucent technologies inc. 63 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 3 using the t8100 (continued) 3.3 using the lar, amr, and idr for connections (continued) 3.3.3 programming examples (continued) ;**secondary controls (fallback) md,idr,35h ;enable ectf fallback: become the new a clock master on a clock failure, ;synchronizes to a bit clock on local reference 1, but requires the main divider ;with external input (assumes a clad is between the divider and 4mhzin). mi,cks,idr ;move the data to cks md,idr,0ffh ;set up main divider with divide-by-256 mi,ckmd,idr ;move the data to divider ; ;**local clocks md,idr,0e4h ;local selected clock 3 gets inverted 8.192 mhz, lsc2 gets 2.048 mhz mi,ck32,idr ;move it to ck32 md,idr,80h ;lsc1 is high & lsc0 is low mi,ck10,idr ;move it to ck10 ; ;*******set up local streams ; md,idr,30h ;8 streams at 8 mbits/s mi,lbs,idr ;define input streams per idr ; ;*******set up h bus streams ; md,idr,0aah ;define h-bus streams 0 - 15 for 4 mbits/s mi,hsl,idr ;do it ; md,idr,0ffh ;define h-bus streams 16-31 for 8 mbits/s mi,hsh,idr ;engage ;*******set up framers ; md,idr,00h ;this sequence sets up group a mi,frla,idr ; to start coincident mi,frlb,idr ; with the frame mi,frph,idr ; boundary and group b md,idr,0f0h ; to start halfway through mi,frha,idr ; the frame. the groups md,idr,0f4h ; operate in normal framing mode mi,frhb,idr ; at 8 mbits/s and are double byte wide. ;note: frph sets up the correct routing. ; ;*******connect the t8100 to the outside world ; md,mcr,0eh ; enable h-bus streams & clock, local streams, local ; clocks including framers ; ;*******end of example #1
64 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 3 using the t8100 (continued) 3.3 using the lar, amr, and idr for connections (continued) 3.3.3 programming examples (continued) ;*******example #2 - setting up local connections ; ; use 8 mbits/s rate set up from example #1... ; send data from stream 7/time slot 60 to stream 0/time slot 2 ; the data is coming from data location stream 07h, time slot 3ch, and is ; being accessed by connection memory location stream 00h, time slot 02h ; in the next frame (unframed operation). ; md,lar,1dh ;set up lower address, i.e., time slot 29 md,amr,43h ; set up upper address bits (stream 3), and point to the ; the time slot field of the connection memory mi,idr,07h ;put a 7 in the time slot field of connection location 3,29 ; ;syntactically, mi,idr,data is a special case since idr is not the final recipient of the data ; md,amr,53h ;maintain the same upper address, but get ready to load the ; remaining connection info (upper bits + control) mi,idr,0001_1110b ;this decodes as follows: xcs bit low, pattern mode off ; (not set), frame bit low, time slot enabled, and stream = 1110b (14) ; ;*******end of example #2 ;*******example #3 - setting up h-bus connections ; ; use rate set up from example #1... ; send data from stream 14/time slot 7 of the h.100 bus to stream 3/time slot 29 ; on the local side. the data is coming in at 4 mbits/s from e-cam, and is sent ; out at 8 mbits/s to through l-cam. were using data memory location 49 to hold ; the actual data. lar is not used for the cam connection setups; it is used for ; reading specific cam locations or writing and reading the associated data ; memory locations. ; ;******set up the from connection ; md,amr,0b0h ;point to the time-slot holding register mi,idr,07h ;this is the time-slot value (7) for the h-bus address md,amr,0b1h ;point to the upper bits of the connection mi,idr,000_01110b :set up a write into data memory from ectf bus, ; disable pattern mode, minimum delay, ; and set stream number equal to 01110b (14). md,amr,0b2h ;point to tag field mi,idr,31h ;use location 49 of the associated data ram to store the data ; md,amr,0e0h ;write to next free location in the even cam mi,idr,0e0h ;the command is executed with the indirect to idr which ;uses the same command value as in the amr.
lucent technologies inc. 65 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 3 using the t8100 (continued) 3.3 using the lar, amr, and idr for connections (continued) 3.3.3 programming examples (continued) ; ;**optional: test cam busy bit** test: md,acc,mcr ;move mcr contents into (hosts) accumulator (for example) and,01h ;logical and, i.e., mask off all but lsb of the mcr register jnz test ;if the lsb is zero (not busy), continue, else jump back and ;retest ; continue: ; ;******set up the to connection ; md,amr,0b0h ;point to the time-slot holding register mi,idr,1dh ;this is the time-slot value (29) for the local address md,amr,0b1h ;point to the upper bits of the connection mi,idr,100_00011b :set up a read from data memory to local pins, ; disable pattern mode, minimum delay, and set ; stream number equal to 00011b (3). md,amr,0c2h ;point to tag field mi,idr,31h ;use location 49 of the associated data ram to store the data ; md,amr,0e3h ;write to next free location in the local cam mi,idr,0e3h ;the command is executed with the indirect to idr ; ; ; ;**cam busy bit can be tested here** ; ; ;*******end of example #3 3.2.4 miscellaneous commands these commands (i.e., 0x70, 0xf8, all reset commands in the amr register) require two writes: first the value is written to the amr register; then the same value is written to the idr register. after writing to the idr register, the command will be executed.
66 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 4 electrical characteristics 4.1 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. 4.2 handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. lucent employs a human-body model (hbm) and a charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used to define the model. no industry-wide standard has been adopted for cdm. however, a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely used and therefore can be used for comparison purposes. the hbm esd threshold presented here was obtained by using these circuit parameters: description symbol min max unit supply voltage v dd 3.6 v xtalin and xtalout pins v ss v dd v voltage applied to i/o pins v ss C 0.5 v dd + 3.4 v operating temperature: 208-pin sqfp 217-pin bga 0 - 40 70 85 c c storage temperature t stg C55 125 c hbm esd threshold voltage device rating t8100 2500 v
lucent technologies inc. 67 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 4 electrical characteristics (continued) 4.3 crystal oscillator table 55. crystal oscillator the t8100 requires a 16.384 mhz clock source. to supply this, a 16.384 mhz crystal can be connected between the rclk and xtalout pins. external 18 pf, 5% capacitors must be connected from xtalin and xtalout to v ss . crystal specifications are shown below. the 32 ppm tolerance is the suggested value if either the dpll is used or fallback to the oscillator is enabled while mastering the bus. otherwise, a crystal with a lesser tolerance can be used. table 56. alternative to crystal oscillator when xtalin is driven by a cmos signal instead of an oscillator, it must meet the requirements shown below: 4.4 dc electrical characteristics, h-bus (ectf h.100 spec., rev. 1.0) 4.4.1 electrical drive specificationsct_c8 and /ct_frame table 57. electrical drive specificationsct_c8 and /ct_frame v dd = 3.3 and v ss = 0.0 unless otherwise specified. pci-compliant data line i/o cells are used for the ct bus data lines. (see pci specification, rev. 2.1, chapter 4.) /c16, /c4, c2, sclk, sclkx2 , and /fr_comp all use the same driver/receiver pairs as those specified for the ct_c8 and /ct_frame signals, though this is not explicitly stated as a part of the h.100 specification. parameter value 5-6390(f) frequency 16.384 mhz oscillation mode fundamental, parallel resonant effective series resistance 40 w maximum load capacitance 14 pf shunt capacitance 7 pf maximum frequency tolerance and stability 32 ppm parameter value frequency 16.384 mhz maximum rise or fall time 5 ns minimum pulse width low high 20 ns 20 ns parameter symbol condition min max unit output high voltage v oh i out = C24 ma 2.4 3.3 v output low voltage v ol i out = 24 ma C0.25 0.4 v positive-going threshold vt+ 1.2 2.0 v negative-going threshold vtC 0.6 1.6 v hysteresis (vt+ C vtC) v hys 0.4v input pin capacitance c in 10 pf v ss 18 pf 18 pf 1 m w 16.384 mh z t8100 xtalin xtalout
68 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 4 electrical characteristics (continued) 4.5 dc electrical characteristics, all other pins table 58. dc electrical characteristics, all other pins v dd = 3.3 and v ss = 0.0 unless otherwise specified. * circuit simulation indicates a worst-case current of 450 ma. this parameter is not tested in production. description symbol min typ max condition unit supply current i dd 270 450* ma supply voltage v dd 3.0 3.6 v input high voltage v il 0.8 v input low voltage v ih 2.0 v input current i i 1 a input capacitance (input only) c i 5 pf input capacitance (i/o pins) c io 10 pf input clamp voltage v c C1.0 v output high voltage v oh 2.4 v output low voltage v ol 0.4 v output short-circuit current i os 100 v oh tied to gnd ma
lucent technologies inc. 69 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 4 electrical characteristics (continued) 4.6 h-bus timing (extract from h.100 spec., rev. 1.0) 4.6.1 clock alignment 5-6119f figure 19. clock alignment /ct_frame (a/b) ct_c8 (a/b) /fr_comp /c16 c2 /c4 sclk sclk sclkx2 sclkx2 sclk (2.048 mhz) (2.048 mhz mode) (4.096 mhz mode) (4.096 mhz mode) (8.192 mhz mode) (8.192 mhz mode) sclkx2 frame boundary
70 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 4 electrical characteristics (continued) 4.6 h-bus timing (extract from h.100 spec., rev. 1.0) (continued) 4.6.2 frame diagram 5-6120f note: bit 1 is the msb. bit 8 is the lsb. msb is always transmitted first in all transfers. figure 20. frame diagram 812345678 123456781 127 0 /ct_frame ct_c8 ct_dx time slot 125 m s frame boundary
lucent technologies inc. 71 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 4 electrical characteristics (continued) 4.6 h-bus timing (extract from h.100 spec., rev. 1.0) (continued) 4.6.3 detailed timing diagram 5-6121f figure 21. detailed timing diagram /ct_frame ct_c8 data out data in 2.0 v 0.6 v 2.0 v 0.6 v 2.4 v 0.4 v 1.4 v tfs tfh 1 bit cell tfp tc8h tc8i tc8p tzdo tdod ts127 bit 8 ts0 bit 1 tdoz tdv tsamp tdiv frame boundary
72 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 4 electrical characteristics (continued) 4.6 h-bus timing (extract from h.100 spec., rev. 1.0) (continued) 4.6.4 ac electrical characteristics, timing, h-bus (h.100, spec., rev. 1.0) table 59. ac electrical characteristics, timing, h-bus (h.100, spec., rev. 1.0) 1. the rise and fall times are determined by the edge rate in v/ns. a maximum edge rate is the fastest rate at which a clock tra nsitions. ct_netref has a separate requirement. (see section 2.4 clocking section.) 2. measuring conditions, data lines: v th (threshold voltage) = 1.4 v, v hi (test high voltage) = 2.4 v, v lo (test low voltage) = 0.4 v, input signal edge rate = 1 v/ns measuring conditions, clock and frame lines: vt+ (test high voltage) = 2.0 v, vtC (test low voltage) = 0.6 v , input signal edge rate = 1 v/ns. 3. test load200 pf. 4. when reset is active, every output driver is 3-stated. 5. tc8p minimum and maximum are under free-run conditions assuming 32 ppm clock accuracy. 6. noncumulative, tc8p requirements still need to be met. 7. measured at the transmitter. 8. measured at the receiver. 9. for reference only. 10. tdv = maximum clock cable delay + max. data cable delay + max. data hiz to output time = 12 ns + 35 ns + 22 ns = 69 ns. max. clock cable delay and maximum data cable delay are worst-case numbers based on electrical simulation. 11. tdoz and tzdo apply at every time-slot boundary. 12. f (phase correction) results from pll timing corrections. symbol parameter min typ max unit notes clock edge rate (all clocks) 0.25 2 v/ns 1, 2, 4 tc8p clock ct_c8 period 122.066 C f 122.074 + f ns 2, 4, 5 tc8h clock ct_c8 high time 49 C f 73 + f ns 2, 4, 6 tc8l clock ct_c8 low time 49 C f 73 + f ns 2, 4, 6 tsamp data sample point 90 ns 2, 4, 9 tdoz data output to hiz time C20 0 ns 2, 3, 4, 7, 11 tzdo data hiz to output time 0 22 ns 2, 3, 4, 7, 11 tdod data output delay time 0 22 ns 2, 3, 4, 7 tdv data valid time 0 69 ns 2, 3, 4, 8, 10 tdiv data invalid time 102 112 ns 2, 4 tfp /ct_frame width 90 122 180 ns 2, 4 tfs /ct_frame setup time 45 90 ns 2, 4 tfh /ct_frame hold time 45 90 ns 2, 4 f phase correction 0 10 ns 12
lucent technologies inc. 73 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 4 electrical characteristics (continued) 4.6 h-bus timing (extract from h.100 spec., rev. 1.0) (continued) 4.6.5 detailed clock skew diagram 5-6122f figure 22. detailed clock skew diagram 4.3.6 ac electrical characteristics, skew timing, h-bus (h.100, spec., rev. 1.0) table 60. ac electrical characteristics, skew timing, h-bus (h.100, spec., rev. 1.0) 1. test load200 pf. 2. assumes a and b masters in adjacent slots. 3. when static skew is 10 ns and, in the same clock cycle, each clock performs a 10 ns phase correction in opposite directions, a maximum skew of 30 ns will occur during that clock cycle. 4. meeting the skew requirements in table 10 and the requirements of section 2.3 h-bus section could require the plls generating ct_c8 to have different time constants when acting as primary and secondary clock masters. 4.6.7 reset and power on table 61. reset and power on symbol parameter min typ max unit notes tskc8 max skew between ct_c8 a and b 10 f ns 1, 2, 3, 4 tskcomp max skew between ct_c8_a and any compatibility clock 5 ns 1 symbol parameter min typ max unit trd output float delay from reset active 1 s trs reset active from power good 5 s vt+ vt+ ct_c8_a ct_c8_b tskc8 vt+ vt+ ct_c8_a compatibility tskcomp clocks vtC tskcomp
74 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 4 electrical characteristics (continued) 4.7 ac electrical characteristics, local streams, and frames table 62. ac electrical characteristics, local streams, and frames 5-6548f note: ldo7 is the msb, ldo0 is the lsb. msb is always transmitted first in all transfers. figure 23. ac electrical characteristics, local streams, and frames symbol description min max condition unit tpd data propagation delay 0 20 load = 50 pf ns ts data setup time 10 ns th data hold time 5 ns toff data 3-state off time 20 ns td0 data bit 0 3-state C20 0 ns 16.384 mhz 8.192 mhz 4.096 mhz 2.048 mhz local selected clocks lsc[3:0] (noninverted shown): local data streams: 8.192 mbits/s 8.192 mbits/s 4.096 mbits/s 4.096 mbits/s 2.048 mbits/s 2.048 mbits/s frame group: 3/4 point tpd 3/4 point tpd tpd 3/4 point ldo 0 ldi 0 ldo 0 ldo 0 ldo 7 ldo 6 ldo 5 ldo 4 ldo 3 ldo 7 ldi 7 ldi 6 ldi 5 ldi 4 ldi 7 ldi 6 ldo 6 ldo 5 ldo 7 ldo 6 ldi 7 td0 ts th td0 ts th ts th tpd td0
lucent technologies inc. 75 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 4 electrical characteristics (continued) 4.8 ac electrical characteristics, microprocessor timing 4.8.1 microprocessor access intel multiplexed write and read cycles for intel write and read cycles, when rdy is low, wait-states are inserted. rdy is brought high when tiacc is met. this is true for both read and write cycles. 5-6124.bf figure 24. microprocessor access intel multiplexed write cycle 5-6125.bf figure 25. microprocessor access intel multiplexed read cycle trdy tiacc a[1:0] d[7:0] ad[7:0] ale cs wr rdy tas tah tds tdh (rdy driven low during memory accesses only) tiacc trdy a[1:0] ad[7:0] ale cs rd rdy tas tah d[7:0] tdi tdv (rdy driven low during memory accesses only)
76 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 4 electrical characteristics (continued) 4.8 ac electrical characteristics, microprocessor timing (continued) 4.8.2 microprocessor access motorola write and read cycles 5-6126.bf figure 26. microprocessor access motorola write cycle 5-6127.bf figure 27. microprocessor access motorola read cycle a[1:0] d[7:0] r/w ds (rd ) cs dtack (rdy) tmacc tds tdh tas tah a[1:0] d[7:0] r/w ds (rd ) cs dtack (rdy) tmacc tdv tdi tah tas
lucent technologies inc. 77 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 4 electrical characteristics (continued) 4.8 ac electrical characteristics, microprocessor timing (continued) 4.8.3 microprocessor access intel demultiplexed write cycle 5-6128.cf figure 28. microprocessor access intel demultiplexed write cycle 5-6128.bf figure 29. microprocessor access intel demultiplexed read cycle table 63. microprocessor access timing (see figure 24 through figure 29.) symbol description min max condition unit tas address setup time 7 load = 100 pf ns tah address hold time 0 ns tdv data valid 13 ns tdi data invalid 0 11 ns trdy active to ready low ( intel ) 14 memory access ns tiacc active to ready high ( intel ) 145 255 memory access ns tmacc active to dtack low ( motorola ) 145 14 255 register access memory access ns tds data setup time 8 ns tdh data hold time 0 ns a[1:0] cs rdy wr d[7:0] tas tds tdh tah trdy tiacc (rdy driven low during memory accesses only) a[1:0] cs rdy rd d[7:0] tas tdv tdi tah trdy tiacc (rdy driven low during memory accesses only)
78 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 5 outline diagram 5.1 208-pin square quad flat package (sqfp) 5-2196(f) note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schematics to assist you r design efforts, please contact your lucent technologies microelectronics group account manager. 156 105 30.60 0.20 157 208 1 52 53 104 28.00 0.20 28.00 0.20 30.60 0.20 pin #1 identifier zone 4.10 max 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail b detail a 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200
lucent technologies inc. 79 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 5 outline diagram (continued) 5.2 217-pin ball grid array (pbga) 5-6562(f) 6 ordering information device part no. description package comcode t8100- - -sc ambassador h.100 interface 208-pin sqfp 108125873 t8100- - -bal ambassador h.100 interface 217-pin bga 108194184 0.36 0.04 1.17 0.05 2.13 0.19 seating plane solder ball 0.60 0.10 0.20 a b c d e f g h j k l m n p r t u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 16 spaces @ 1.27 = 20.32 a1 ball corner 16 spaces @ 1.27 = 20.32 0.75 0.15 pwb mold compound 23.00 0.20 23.00 0.20 19.50 +0.70 C0.00 19.50 +0.70 C0.00 a1 ball identifier zone side view bottom view top view
80 80 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 appendix a. application of clock modes in the diagrams that follow, four clock modes are illus- trated using figure 12, the t8100 clocking diagram, as the basis of each illustration. the key signal paths are shown in solid lines, and unused paths with narrow dashes. two examples also indicate fallback paths. a register profile (programming values) for all four exam- ples is on the last page of the appendix. in figure 30, the t8100 is operating as a bus master, so it must link to either an 8 khz recovered frame refer- ence or 2.048 mhz recovered bit clock reference from the e1 framers. in addition, the t8100 can provide one of the basic resource clocks to run the framers. in this case, the tclk is selecting the t8100s 16.384 mhz oscillator. the framers are returning a 2.048 mhz bit clock which is selected through the clock selector. it is not divided, so the main divider is bypassed (divide-by-1), the clock is smoothed through an external djat, and the smooth 2.048 mhz signal is routed to pll #1 through the clock resource selector. pll #1 multiplies the 2.048 mhz input up to 65.536 mhz which, in turn, runs the rest of the t8100, all bus clocks, and the local clocks (if desired). if the t8100 is not providing netref generation, then the netref from the bus is routed to the local clocks via the netref internal/external selector. since the netref generation resources are not needed here, the todjat and fromdjat pins are free for use with the general-purpose register as bits gp6 and gp7, respectively. figure 31 shows the t1 version of a bus master. in this scenario, a 1.544 mhz recovered bit clock from the framers is routed to a multiclock adapter (with built-in jitter attenuation) which produces smooth 4.096 mhz and 3.088 mhz outputs. the 4.096 mhz is routed up to pll #1 for a times-16 rate multiplication to 65.536 mhz. this drives the bus clocks and the local clocks. the smooth 3.088 mhz is also rate multiplied times 8. this produces a 24.704 mhz clock. this is divided back down to produce a smooth 12.352 mhz which is fed back to the framers. (pll outputs produce one tightly bound edge and one with significant phase jitter. dividing a higher-frequency signal based on its clean edge produces a lower frequency with two clean edges.) figure 32 shows an h- mvip slave arrangement for e1. in this example, the c16 differential clocks provide the main source for pll #1. the 16.384 mhz signal is divided down to 4.096 mhz and then rate multiplied up to 65.536 mhz for driving the rest of the t8100. the frame sync for the state machines is derived from the /frame and c16 inputs as well as the state informa- tion provided by c2 and /c4. note: the bit slider is enabled for a smooth phase alignment between the internal frame and the frame sync. the bus clocks are not driven, but the local clocks are available. a path for netref is shown as well, also based on a 2.048 mhz input. the signal is smoothed and then divided down to an 8 khz signal via the netref divider. the internal oscillator is again chosen for routing to the framers via tclk. figure 33 shows an h- mvip slave for t1. this is identi- cal to the e1 case with regard to slaving, and a netref path is illustrated in this example, too. the netref divider has been changed to accommodate the 1.544 mhz bit clock rate. the primary difference is the use of the c16 clock through the main divider to generate a 2.048 mhz signal which can be routed off- chip and adapted to a 1.544 mhz signal using an exter- nal device. the 1.544 mhz signal is returned to the t8100 via the 3mhzin for rate multiplication up to 24.704 mhz and then division to a clean 12.352 mhz signal which is routed to the framers via tclk.
lucent technologies inc. 81 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 appendix a. application of clock modes (continued) 5-6129af(r3) figure 30. e1, ct bus master, compatibility clock master, clock source = 2.048 mhz from trunk x16 x32 x8 x16 4 mhz 2 mhz frame sync dpll netref divide-by-n divide register main divide-by-n divide register clock resource select divide by 4 gp6 gp7 resource divide-by-n divide register netref int/ext select bit slider controls bit slider state machines pll #1 pll #1 bypass rate select 65.536 mhz pll #2 pll #2 bypass rate select prirefo 4mhzin 3mhzin tclk tclk enable tci select divide by 2 net- ref sel. ? by 8 netref select frame sel. /ct_frame a /ct_frame b /fr_comp clock sel. clock sel. and input state mach. lref0 lref7 ct_netref ct_c8 clkb /c16 /c4 c2 sclk sclk2 xtalin todjat/gp6 fromdjat/gp7 djat bypass (and gp6/7 enable) l_sc ctl frame frame sec8k frame frame en_b c8 c6 en_a netref en_netref ct_netref ct_c8a /ct_framea ct_c8b /ct_frameb compatibility clocks direction /ct16 c2 /c4 sclk sclk2 /fr_comp l_sc0 scsel framers 2mhz djat (fallback path) dpll#2-2 16.384 mhz 8.192 mhz 4.096 mhz 2.048 mhz 8.192 mhz 4.096 mhz 8.192 mhz 4.096 mhz 2.048 mhz 4.096 mhz 2.048 mhz 16.384 mhz (1 of 4 l_sc[1:3] not shown) 2.048 mhz
82 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 appendix a. application of clock modes (continued) 5-6130af(r4) figure 31. t1, ct bus master, compatibility clock master, clock source = 1.544 mhz from trunk x16 x32 x8 x16 4 mhz 2 mhz frame sync dpll netref divide-by-n divide register main divide-by-n divide register clock resource select divide by 4 gp6 gp7 resource divide-by-n divide register netref int/ext select bit slider control bit slider state machines pll #1 pll #1 bypass rate select 65.536 mhz pll #2 pll #2 bypass rate select prirefout 4mhzin 3mhzin tclk tclk enable tci select divide by 2 net- ref sel. ? by 8 netref select frame sel. /ct_frame_a /ct_frame_b /fr_comp clock sel. clock sel. and input state mach. l_ref0 l_ref7 ct_netref ct_c8 clkb /c16 /c4 c2 sclk sclk2 xtalin todjat/gp6 fromdjat/gp7 l_sc ctl frame frame sec8k frame frame en_b c8 c6 en_a netref en_netref ct_netref ct_c8_a /ct_frame_a ct_c8_b /ct_frame_b compatibility clocks direction /ct16 c2 /c4 sclk sclk2 /fr_comp l_sc0 scsel framers jitter attenuated (fallback path) dpll#2-2 16.384 mhz 8.192 mhz 4.096 mhz 2.048 mhz 8.192 mhz 4.096 mhz 8.192 mhz 4.096 mhz 2.048 mhz 4.096 mhz 2.048 mhz (xtalin still drives other internals.) multiclock adapter (1 of 4 l_sc[1:3] not shown) 16.384 mhz 1.544 mhz
lucent technologies inc. 83 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 appendix a. application of clock modes (continued) 5-6131af(r3) figure 32. e1, slave to ct bus, clock source is either a 16 mhz or a 4 mhz or a 2 mhz and frame, netref source = 2.048 mhz from trunk x16 x32 x8 x16 4 mhz 2 mhz frame sync dpll netref divide-by-n divide register main divide-by-n divide register clock resource select divide by 4 gp6 gp7 resource divide-by-n divide register netref int/ext select bit slider controls bit slider state machines pll #1 pll #1 bypass rate select 65.536 mhz pll #2 pll #2 bypass rate select prirefout 4mhzin 3mhzin tclk tclk enable tci select divide by 2 net- ref sel. ? by 8 netref select frame sel. / ct_frame_a / ct_frame_b /fr_comp clock sel. clock sel. and input state mach. l_ref0 l_ref7 ct_netref ct_c8 clkb /c16 /c4 c2 sclk sclk2 xtalin todjat/gp6 fromdjat/gp7 l_sc ctl frame frame sec8k frame frame en_b c8 c6 en_a netref en_netref ct_netref ct_c8_a /ct_frame_a ct_c8_b /ct_frame_b compatibility clocks direction /ct16 c2 /c4 sclk sclk2 /fr_com p l_sc0 scsel framers (fallback path) dpll#2-2 16.384 mhz 8.192 mhz 4.096 mhz 2.048 mhz 8.192 mhz 4.096 mhz 8.192 mhz 4.096 mhz 2.048 mhz 4.096 mhz 2.048 mhz 16.384 mhz 2 mhz djat djat bypass (and gp 6/7 enable) (1 of 4 l_sc[1:3] not shown) 2.048 mhz
84 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 appendix a. application of clock modes (continued) 5-6132af(r5) figure 33. t1, slave to ct bus, clock source is either a 16 mhz or a 4 mhz or a 2 mhz and frame, netref source = 1.544 mhz from trunk x16 x32 x8 x16 4 mhz 2 mhz frame sync dpll netref divide-by-n divide register main divide-by-n divide register clock resource select divide by 4 gp6 gp7 resource divide-by-n divide register netref int/ext select bit slider control bit slider state machines pll #1 pll #1 bypass rate select 65.536 mhz pll #2 pll #2 bypass rate select prirefout 4mhzin 3mhzin tclk tclk enable tcli select divide by 2 net- ref sel. ? by 8 netref select frame sel. / ct_frame_a / ct_frame_b /fr_comp clock sel. clock sel. and input state mach. l_ref0 l_ref7 ct_netref ct_c8 clkb /16 /c4 c2 sclk sclk2 xtalin todjat/gp6 l_sc ctl frame frame sec8k frame frame en_b c8 c8 en_a netref en_netref ct_netref ct_c8_a /ct_frame_a ct_c8_b /ct_frame_b compatibility clocks direction /ct16 c2 /c4 sclk sclk2 /fr_comp l_sc0 scsel framers (fallback path) dpll#2-2 16.384 mhz 8.192 mhz 4.096 mhz 2.048 mhz 8.192 mhz 4.096 mhz 8.192 mhz 4.096 mhz 2.048 mhz 4.096 mhz 2.048 mhz 16.384 mhz 1.5 mhz djat djat bypass (and gp6/7 enable) jitter attenuated multiclock adapter (1 of 4 l_sc[1:3] not shown) fromdjat/gp7 1.544 mhz
lucent technologies inc. 85 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 appendix a. application of clock modes (continued) table 64. clock register programming profile for the four previous examples the programming displays how similar the four basic modes of operation are. local outputs (ck32 and ck10) are obviously not constrained by the mode of operation. the primary difference between e1 and t1 is in the use of the pll #2 (which is optional). the primary difference between master and slave is in the clock path to pll #1, which is covered by registers ckm, ckr, ckmd, and ckrd. note: ckr does include an example of running pll #1 at x32 for e1 master and x16 for all other cases. the watchdogs have been set up to monitor all ct bus signals, though fallback (to the oscillator) is shown as enabled in all examples. it is recommended that the default condition, cks = 0x00, be used for systems which do not have specific fallback clocking schemes. also, while programming the t8100 on powerup, it is recommended that the watchdogs are disabled (ckw = 0x00) until the device is fully programmed to prevent false error conditions (uninitialized clocks, for example) from changing the operating mode. register name ct bus master (e1) ct bus master (t1) ct bus slave (e1) ct bus slave (t1) ckm 0010_1000b 0010_1000b 1100_0101b 1100_0101b ckn 0110_0000b 0110_0000b 1000_1111b 1000_1111b ckp 0010_0001b 0110_0001b 0010_0000b 0110_0000b ckr 0001_0000b 0000_0000b 0100_0000b 0100_0000b cks 0000_0000b 0000_0000b 0000_0000b 0000_0000b ck32 1001_0100b 1001_0100b 0010_0100b 0010_0100b ck10 1101_1111b 1101_1111b 1000_0000b 1011_1101b ckmd 0000_0000b 0000_0000b 0000_0000b 0000_0111b cknd 0000_0000b 0000_0000b 1111_1111b 1100_0000b ckrd 0000_0000b 0000_0000b 0000_0011b 0000_0011b watchdog: ckw 0011_1001b 0011_1001b 0011_1001b 0011_1001b
86 86 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 appendix b. minimum delay and con- stant delay connections b.1 connection definitions forward a forward connection is defined as one connection in which the output ( to ) time slot has a greater value than the input ( from ) time slot, or put another way, the delta between them is positive. reverse a reverse connection is defined as one connection in which the input ( from ) time slot has a lesser value than the output ( to ) time slot, and the delta between them is negative. so, for example, going from ts(1) to ts(38) is a for- ward connection, and the ts d is +37, but going from ts(38) to ts(1) is a reverse connection, with a ts d of C37: where ts d = ts( to ) C ts( from ). similarly, a delta can be introduced for streams which will have a bearing in certain exceptions (discussed later): str d = str( to ) C str( from ) there is only one combination which forms a ts d of +127 or C127: ts d = ts(127) C ts(0) = +127, and ts d = ts(0) C ts(127) = C127, but there are two combinations which form ts d s of +126 or C126: ts d = ts(127) C ts(1) = ts(126) C ts(0) = +126, and ts d = ts(1) C ts(127) = ts(0) C ts(126) = C126, there are three combinations which yield +125 or C125, and so on. the user can utilize the ts d to control the latency of the resulting connection. in some cases, the latency must be minimized. in other cases, such as a block of connections which must maintain some relative integ- rity while crossing a frame boundary, the required latency of some of the connections may exceed one frame (>128 time slots) to maintain the integrity of this virtual frame. the t8100 contains several bits for controlling latency. each connection has a bit which is used for selecting one of two alternating data buffers. these bits are set in the local connection memory for local switching or in the tag register files of the cam section for h-bus switching. there are also 2 bits in the con register, address 0x0e, which can control the buffer selection on a chip-wide basis. bit 1 of the register overrides the individual fme bits. bit 0 becomes the global, chip- wide, fme setting.
lucent technologies inc. 87 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 appendix b. minimum delay and con- stant delay connections (continued) b.2 delay type definitions constant delay in the t8100, this is a well-defined, predictable, and linear region of latency in which the to time slot is at least 128 time slots after the from time slot, but no more than 256 time slots after the from time slot. mathematically, constant delay latency is described as follows*, with l denoting latency, and fme set to the value indicated: forward connections, fme = 1: l = 128 + ts d (0 ts d 127) reverse connections, fme = 0: l = 256 + ts d (C127 ts d 0) * since ts d = ts(to) C ts(from), the user can modify the equations to solve for either ts(to) or ts(from). example: switching from ts(37) to ts(1) as a con- stant delay, the delta is C36, so fme is set to 0 and the resulting latency is 256 C 36 = 220 time slots. thus, the connec- tion will be made from ts(37) of frame(n) to ts(1) of frame(n + 2). simple summary: use constant delay for latencies of 128 to 256 time slots, set fme = 1 for forward connections, set fme = 0 for reverse connections. minimum delay this is the most common type of switching, but has a shorter range than constant delay, and the user must be aware of exceptions caused by interactions between the t8100's internal pipeline and the dual buffer- ing. the to time slot is at least three time slots after the from time slot, but no more than 128 time slots after the from time slot. exceptions exist at ts d s of +1, +2, C126, and C127. forward connections, fme = 0: l = ts d (3 ts d 127) reverse connections, fme = 1: l = 128 + ts d (C125 ts d 0) example: using the same switching from the example above, ts(37) to ts(1), the delta is C36, so fme is set to 1 to effect the minimum delay (setting to 0 effects constant delay), and the resulting latency is 128 C 36 = 92 time slots. the relative positions of the end time slots are the same in both minimum and con- stant delay (i.e., they both switch to ts[1]), but the actual data is delayed by an additional frame in the constant delay case. simple summary: use minimum delay for latencies of 3 to 128 time slots, set fme = 0 for forward connections, set fme = 1 for reverse connections. 5-6223 (f) figure 34. constant delay connections, con[1:0] = 0x applied delta (time slots) resulting latency C127 128 0 127 255 256 (time slots) f m e = 0 f m e = 1 129
88 88 lucent technologies inc. preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 appendix b. minimum delay and con- stant delay connections (continued) b.2 delay type definitions (continued) b.2.1 exceptions to minimum delay up until this point in the discussion, the strds have not been discussed because the to and from streams have been irrelevant in the switching process*. rather than try to list the exceptions mathematically, a table is provided. the latencies in these cases may exceed two frames due to the interaction of the intrinsic pipeline delays with the double buffering. table 65. table of special cases (exceptions) graphically, the minimum delay latency equations are illustrated below. the exceptions to the minimum delay have been included in the diagram, connected to the main function by dashed lines. b.2.2 lower stream rates the discussion has centered on 128 time-slot frames which correspond to 8.192 mbits/s data rates. how does one make similar predictions for lower stream rates? for 4.096 mbits/s, multiply the to and from time-slot values by two, i.e., time slot 0 at 4.096 mbits/s corre- sponds to time slot 0 at 8.192 mbits/s, and time slot 63 at 4.096 mbits/s corresponds to time slot 126 at 8.192 mbits/s. similarly, multiply values by four to convert 2.048 mbits/s values. the latency equations can then be applied directly. * the one universally disallowed connection on the t8100 is a ts d of 0 and a str d of 0. this is a stream and time-slot switching to itself. loopback on the local bus, e.g., ldo_0 to ldi_0 is permissible. fme value ts d latency for str d < 0 latency for str d 3 0 0 +1 257 257 0 +2 258 2 1 C126 258 2 1 C127 257 257 5-6224(f) figure 35. minimum delay connections, con[1:0] = 0x applied delta (time slots) resulting latency C127 0 127 127 128......256 (time slots) f m e = 1 f m e = 0 0 C126 258 257 2 2 2 special long latency connections (see text)
lucent technologies inc. 89 preliminary data sheet august 1998 h.100/h.110 interface and time-slot interchanger ambassador t8100 appendix b. minimum delay and con- stant delay connections (continued) b.2 delay type definitions (continued) b.2.3 mixed minimum/constant delay an interesting mix of delays occurs when the individual fme bits are overridden and a chip-wide selection for fme is used. in short, when the t8100 is placed in this mode, and when register bits con[1:0] = 10, forward connections provide minimum delay, reverse connec- tions provide constant delay. when con[1:0] = 11, reverse connections provide minimum delay, forward connections provide constant delay. the latter is inter- esting because, graphically, the ts d to latency map- ping appears as a linear monotonic function covering 255 time slots. (graphs are in the section which fol- lows.) the latency equations follow: con[1:0] = 10: forward connections: l = ts d (3 ts d 127). reverse connections: l = 256 + ts d (C127 ts d 0). con[1:0] = 11: forward and reverse: l = 128 + ts d (C125 ts d 127). table 65, table of special cases (exceptions), applies to the mixed delays in a similar manner. simply use bit 0 of con for the fme value in table 65. 5-6225(f) figure 36. mixed minimum/constant delay connections, con[1:0 = 10] applied delta (time slots) resulting latency C127 0 127 127 256 (time slots) f me = 0 fme = 0 0 C127 258 2 2 129 special long latency connections (see text) 128
prelimin a ry dat a sheet a ugust 1998 h.1 0 0/h. 1 10 interfa c e a nd time-slot inte r c hanger ambassador t8100 l u c e nt t e c h n o l o g ies i n c . re s e r v es t he r i ght to m ake c h an g es to the pro d u c t( s ) or i n f o r m a t i on c o nt a i n ed h ere i n w it h o u t n o t i ce. no l i a b i l i t y i s a s s u m e d as a re s u lt o f t h e i r u s e o r a p p l i c a t i on. no r i g h ts u n der a n y p at e n t a c c om p any the s a l e o f any s u c h p rod u c t(s) o r i n f o r m a t i on. ambassador is a trademark of lucent technologies inc. co p y r i g ht ? 19 9 8 l u c e n t t e c hn o l o g i es i n c. a l l r i gh t s re s e r v e d a ugust 1 9 98 ds98-1 9 5n t nb (replace s ds9 8 -130nt n b , d a 9 8-011ntn b , d a 98-01 4 n tn b , an d a y 98-01 5 n tnb) for add i tiona l informat i on, conta c t your m i croele c tronic s group ac c ount man a ger or the fol l ow i ng: i n ter n e t : http://ww w .lucent.com/mic r o e - m a i l : docmaster@mic r o.lucent.com n . ameri c a: m i croele c tronic s grou p , lucent t e c hnolog i es in c ., 555 union boul e v a r d , r oo m 30l-15p- b a, alle n t o w n, p a 18103 1-800-3 7 2-244 7 , f ax 610-712-4106 (i n c a n a d a: 1-800-55 3 - 2 44 8 , f ax 610-712-4106) a sia p a cific : m i croele c tronic s grou p , lucent t e c hnolog i es singa p ore p t e . ltd., 77 sci e nce p a r k d r i v e , #03-18 cintec h iii, singa p ore 11 8 256 t el. (6 5 ) 7 78 8833 , f ax (65) 777 74 9 5 c hi n a: m i croele c tronic s grou p , lucent t e c hnolog i es (china) c o . , ltd., a- f 2 , 23/ f , zao f ong uni v ers e b u i lding , 1800 zhong shan xi road, shangh a i 200233 p . r. ch i n a t el. (86) 2 1 6440 0468 , e xt. 316 , f ax (86) 21 6440 0 6 52 j a p a n: m i croele c tronic s grou p , lucent t e c hnolog i es j apan ltd. , 7-18, h i gash i - g otanda 2- c hom e , shinag a w a - k u , t ok y o 141, j apan t el. (8 1 ) 3 5421 1600 , f a x (81) 3 5 4 21 1700 e u r ope: data request s : microel e ct r oni c s g r o u p d a t a l i n e: t el. (44) 11 8 9 324 299 , f a x (44) 118 9 328 148 t e c hnica l inqui r i e s : ge r man y : (4 9 ) 8 9 95086 0 ( m uni c h), u n ited k in g d o m: ( 4 4) 1344 865 9 0 0 ( b r a c knel l ) , f r a n c e : ( 3 3 ) 1 48 83 68 0 0 (paris), sw e de n : (46) 8 600 7070 (sto c khol m ) , finla n d: (358) 9 4 354 280 0 ( h e l sin k i), i t a l y : (39) 2 6608131 (m i lan), s p ain : (34) 1 807 1 4 41 (mad r id) appendix b. mini m um del a y and constant del a y connections (conti n ued) b . 2 del a y t ype defini t ions (continued) b.2.3 mi x ed mini m um/constant del a y (conti n ued) 5 - 6 2 2 6 ( f ) figure 37. extended linear (mi x ed mini m um/constant) del a y , c on[1:0] = 11 a ppl i e d d e lt a ( t i m e sl ot s) 0 1 2 7 2 5 5 2 5 6 f me = 1 0 C 1 26 2 5 7 1 2 8 2 sp e c i a l l o n g l a t e n c y co n n e ctions ( s ee te x t) 258 C 127 r e s u l t i n g l a t e n cy ( t i m e s l o t s)

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