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m pd750108 4-bit single-chip microcontrollers m pd750104 m pd750106 m pd750108 m pd75p0116 document no. u11330ej2v1um00 (2nd edition) date published december 1999 j cp(k) 1996 user? manual printed in japan
users manual u11330ej2v1um00 [memo] users manual u11330ej2v1um00 ms-dos is a trademark of microsoft corporation. ibm dos, pc/at, and pc dos are trademarks of ibm corporation. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. users manual u11330ej2v1um00 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7d 98. 12 users manual u11330ej2v1um00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1 users manual u11330ej2v1um00 major changes page description throughout the m pd750104, m pd750106, m pd750108, and m pd75p0116 have already been developed. data bus pins (d0-d7) have been added. p.21 section 2.4 has been changed. pp.234 to 235 section 9.2 has been changed. p.236 section 9.3 has been changed. p.267 modification of the instruction list in 11.3 op code of each instruction . pp.303 to 304 the target for comparison, in the table of appendix a has been changed from the m pd75008 to the m pd750008. p.325 appendix f has been added. the mark * shows major revised points. users manual u11330ej2v1um00 preface readers this manual is intended for engineers who want to learn the capabilities of the m pd750104, m pd750106, m pd750108, and m pd75p0116 to develop application sys- tems based on them. purpose the purpose of this manual is to help users understand the hardware capabilities (shown below) of the m pd750104, m pd750106, m pd750108, and m pd75p0116. configuration this manual is roughly divided as follows: ? general ? pin functions ? architecture feature and memory map ? internal cpu functions ? peripheral hardware functions ? interrupt and test functions ? standby function ? reset function ? writing to and verifying program memory (prom) ? mask option ? instruction set guidance readers of this manual should have general knowledge of the electronics, logical circuit, and microcomputer fields. ? for users who have used the m pd750008: C> see appendix a to check for any difference in the functions and read the explanation of those differences. ? to check the functions of an instruction in detail when the reader knows its mnemonics: C> see the instruction index in appendix d . ? to check the functions of specific internal circuits, etc.: C> see appendix e . ? to understand the overall functions of the m pd750104, m pd750106, m pd750108, and m pd75p0116: C> read through all chapters sequentially. users manual u11330ej2v1um00 notation data bit significance : higher-order bits on the left side lower-order bits on the right side active low : xxx (pin and signal names are overscored.) memory map address : low-order address on the upper side high-order address on the lower side note : explanation of an indicated part of text caution : information requesting the user's special attention remark : supplementary information important and emphasized matter : described in bold face numeric value : binary .................. xxxx or xxxxb decimal ............... xxxx hexadecimal ....... xxxxh users manual u11330ej2v1um00 related documents some documents are preliminary editions, but they are not so specified in the tables below. documents related to devices document name document number japanese english m pd750104, 750106, 750108, 750104(a), 750106(a), u12301j u12301e 750108(a) data sheet m pd75p0116 data sheet u12603j u12603e m pd750108 users manual u11330j u11330e (this manual) m pd750008, 750108 instruction list u11456j 75xl series selection guide u10453j u10453e documents related to development tools document name document number japanese english hardware ie-75000-r/ie-75001-r users manual eeu-846 eeu-1416 ie-75300-r-em users manual u11354j u11354e ep-75008cu-r users manual eeu-699 eeu-1317 ep-75008gb-r user's manual eeu-698 eeu-1305 pg-1500 users manual u11940j eeu-1335 software ra75x assembler package users operation eeu-731 eeu-1346 manual language eeu-730 eeu-1363 pg-1500 controller pc-9800 series (ms-dos tm ) base eeu-704 eeu-1291 users manual ibm pc series (pc dos tm ) base eeu-5008 u10540e other documents document name document number japanese english semiconductors selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grade on nec semiconductor devices c11531j c11531e nec semiconductor device reliability and quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic c11892j c11892e discharge (esd) microcontroller-related products guide - by third parties u11416j caution the above related documents are subject to change without notice. be sure to use the latest edition when you design your system. * users manual u11330ej2v1um00 [memo] users manual u11330ej2v1um00 contents chapter 1 general ......................................................................................................................... 1 1.1 function overview .......................................................................................... 2 1.2 ordering information ................................................................................... 3 1.3 differences among m pd750108 subseries products ........................ 4 1.4 block diagram ................................................................................................... 5 1.5 pin configuration (top view) ...................................................................... 6 chapter 2 pin functions ............................................................................................................... 9 2.1 pin functions of the m pd750108 ................................................................. 9 2.2 pin functions ..................................................................................................... 13 2.2.1 p00-p03 (port0), p10-p13 (port1) ................................................... 13 2.2.2 p20-p23 (port2), p30-p33 (port3), p40-p43 (port4), p50-p53 (port5), p60-p63 (port6), p70-p73 (port7) ................... 13 2.2.3 p80, p81 (port8) ................................................................................... 14 2.2.4 ti0 ............................................................................................................. 14 2.2.5 pto0, pto1 ............................................................................................. 15 2.2.6 pcl ........................................................................................................... 15 2.2.7 buz ........................................................................................................... 15 2.2.8 sck, so/sb0, si/sb1 ............................................................................. 15 2.2.9 int4 .......................................................................................................... 15 2.2.10 int0, int1 ................................................................................................ 16 2.2.11 int2 .......................................................................................................... 16 2.2.12 kr0-kr3, kr4-kr7 ................................................................................. 17 2.2.13 cl1, cl2 .................................................................................................. 17 2.2.14 xt1, xt2 .................................................................................................. 17 2.2.15 reset ...................................................................................................... 18 2.2.16 vdd .......................................................................................................... 18 2.2.17 vss ........................................................................................................... 18 2.2.18 ic (for the m pd750104, m pd750106, and m pd750108 only) ................. 18 2.2.19 vpp (for the m pd75p0116 only) ............................................................. 18 2.2.20 md0-md3 (for the m pd75p0116 only) .................................................... 18 2.2.21 d0-d7 (for the m pd75p0116 only) .......................................................... 18 2.3 pin input/output circuits ............................................................................. 19 2.4 connection of unused pins ........................................................................ 21 chapter 3 features of the architecture and memory map ....................................... 23 3.1 data memory bank structure and addressing modes .................. 23 * users manual u11330ej2v1um00 3.1.1 data memory bank structur e ................................................................. . 2 3 3.1.2 data memory addressing mode s ........................................................... . 2 5 3.2 general register bank configuratio n ................................................ . 3 6 3.3 memory-mapped i/ o ......................................................................................... . 4 1 chapter 4 internal cpu function s ........................................................................................ . 4 7 4.1 mk i mode/mk ii mode switch function s .................................................. . 4 7 4.1.1 differences between mk i mode and mk ii mod e .................................. . 4 7 4.1.2 setting of the stack bank selection register (sbs ) ............................. . 4 8 4.2 program counter (pc ) ................................................................................ . 4 9 4.3 program memory (rom ) ................................................................................ . 5 0 4.4 data memory (ram): 512 words x 4 bit s ................................................. . 5 5 4.4.1 data memory configuratio n .................................................................... . 5 5 4.4.2 specification of a data memory ban k .................................................... . 5 6 4.5 general register: 8 x 4 bits x 4 bank s .................................................. . 5 8 4.6 accumulato r .................................................................................................... . 5 9 4.7 stack pointer (sp) and stack bank select register (sbs ) .......... . 6 0 4.8 program status word (psw ) ..................................................................... . 6 4 4.9 bank select register (bs ) ........................................................................... . 6 7 chapter 5 peripheral hardware function s ..................................................................... . 6 9 5.1 digital i/o port s ............................................................................................ . 6 9 5.1.1 types, features, and configurations of digital i/o port s ..................... . 7 0 5.1.2 i/o mode settin g ..................................................................................... . 7 6 5.1.3 digital i/o port manipulation instruction s .............................................. . 7 8 5.1.4 digital i/o port operatio n ....................................................................... . 8 1 5.1.5 specification of built-in pull-up resistor s ............................................. . 8 3 5.1.6 i/o timing of digital i/o port s ................................................................ . 8 4 5.2 clock generato r ............................................................................................ . 8 6 5.2.1 clock generator configuratio n ............................................................... . 8 6 5.2.2 functions and operations of the clock generato r ................................ . 8 7 5.2.3 system clock and cpu clock settin g ................................................... . 9 8 5.2.4 clock output circui t ................................................................................ . 1 0 0 5.3 basic interval timer/watchdog time r .................................................. . 1 0 3 5.3.1 configuration of the basic interval timer/watchdog time r .................. . 1 0 3 5.3.2 basic interval timer mode register (btm ) ........................................... . 1 0 3 5.3.3 watchdog timer enable flag (wdtm ) .................................................. . 1 0 5 5.3.4 operation of the basic interval time r .................................................... . 1 0 5 5.3.5 operation of the watchdog time r .......................................................... . 1 0 6 5.3.6 other function s ....................................................................................... . 1 0 7 users manual u11330ej2v1um00 5.4 clock timer ........................................................................................................ 108 5.4.1 configuration of the clock timer ............................................................. 109 5.4.2 clock mode register ................................................................................ 109 5.5 timer/event counter ...................................................................................... 111 5.5.1 configuration of timer/event counter .................................................... 111 5.5.2 8-bit timer/event counter mode operation ........................................... 117 5.5.3 notes on timer/event counter applications ........................................... 123 5.6 serial interface .............................................................................................. 126 5.6.1 serial interface functions ........................................................................ 126 5.6.2 configuration of serial interface .............................................................. 127 5.6.3 register functions ................................................................................... 130 5.6.4 operation halt mode ................................................................................ 138 5.6.5 three-wire serial i/o mode operations ................................................. 140 5.6.6 two-wire serial i/o mode ....................................................................... 147 5.6.7 sbi mode operation ................................................................................ 153 5.6.8 manipulation of sck pin output ............................................................. 182 5.7 bit sequential buffer .................................................................................... 184 chapter 6 interrupt and test functions ............................................................................ 187 6.1 configuration of the interrupt control circuit ........................... 187 6.2 types of interrupt sources and vector tables ............................. 189 6.3 various devices to control interrupt functions .......................... 191 6.4 interrupt sequence ....................................................................................... 199 6.5 multiple interrupt processing control ............................................. 200 6.6 processing of interrupts sharing a vector address ................. 202 6.7 machine cycles for starting interrupt processing .................... 204 6.8 effective use of interrupts ...................................................................... 206 6.9 interrupt applications ................................................................................. 206 6.10 test function .................................................................................................... 214 6.10.1 test sources ............................................................................................ 214 6.10.2 hardware to control test functions ....................................................... 214 chapter 7 standby function ..................................................................................................... 219 7.1 setting of standby modes and operation status ........................... 220 7.2 release of the standby modes ................................................................. 221 7.3 operation after a standby mode is released ................................... 223 7.4 selection of a mask option ........................................................................ 223 7.5 applications of the standby modes ....................................................... 224 users manual u11330ej2v1um00 chapter 8 reset function ........................................................................................................... 229 chapter 9 writing to and verifying program memory (prom) .................................. 233 9.1 operating modes when writing to and verifying the program memory ................................................................................................................. 234 9.2 writing to the program memory ............................................................. 234 9.3 reading the program memory ................................................................... 236 9.4 screening of one-time prom ...................................................................... 237 chapter 10 mask option ................................................................................................................. 239 10.1 pin ........................................................................................................................... 239 10.2 mask option of standby function ........................................................... 239 10.3 mask option for feedback resistor of subsystem clock .......... 240 chapter 11 instruction set .......................................................................................................... 241 11.1 unique instructions ....................................................................................... 241 11.1.1 geti instruction ....................................................................................... 241 11.1.2 bit manipulation instruction ..................................................................... 242 11.1.3 string-effect instructions .......................................................................... 242 11.1.4 number system conversion instructions ................................................ 243 11.1.5 skip instructions and the number of machine cycles required for a skip ........................................................................................................ 244 11.2 instruction set and operation ................................................................ 245 11.3 instruction codes of each instruction .............................................. 262 11.4 functions and applications of the instructions ............................ 268 11.4.1 transfer instructions ................................................................................ 268 11.4.2 table reference instructions ................................................................... 274 11.4.3 bit transfer instructions ........................................................................... 277 11.4.4 arithmetic/logical instructions ................................................................. 277 11.4.5 accumulator manipulation instructions ................................................... 283 11.4.6 increment/decrement instructions .......................................................... 283 11.4.7 compare instructions ............................................................................... 284 11.4.8 carry flag manipulation instructions ...................................................... 285 11.4.9 memory bit manipulation instructions ..................................................... 286 11.4.10 branch instructions .................................................................................. 288 11.4.11 subroutine stack control instructions ..................................................... 293 11.4.12 interrupt control instructions ................................................................... 297 11.4.13 i/o instructions ......................................................................................... 298 11.4.14 cpu control instructions ......................................................................... 299 11.4.15 special instructions .................................................................................. 299 users manual u11330ej2v1um00 appendix a functions of the m pd750008, m pd750108, and m pd75p0116 ........................... 303 appendix b development tools .................................................................................................. 305 appendix c masked rom ordering procedure .................................................................... 313 appendix d instruction index ...................................................................................................... 315 d.1 instruction index (by function) ............................................................... 315 d.2 instruction index (alphabetical order) ............................................... 318 appendix e hardware index ......................................................................................................... 321 e.1 hardware index (alphabetical order with respect to the hardware name) ............................................................................................... 321 e.2 hardware index (alphabetical order with respect to the hardware symbol) .......................................................................................... 323 appendix f revision history ........................................................................................................ 325 * users manual u11330ej2v1um00 list of figures (1/4) figure no. title page 2-1 pin input/output circuits ................................................................................................... 19 3-1 use of mbe = 0 mode and mbe = 1 mode ..................................................................... 24 3-2. data memory organization and addressing range of each addressing mode ............ 26 3-3 updating static ram addresses ...................................................................................... 30 3-4. example of register bank selection ................................................................................ 37 3-5. general register configuration (4-bit processing) ......................................................... 39 3-6 general register configuration (8-bit processing) ......................................................... 40 3-7 m pd750108 i/o map ......................................................................................................... 42 4-1 stack bank selection register format ............................................................................ 48 4-2 program counter organization ......................................................................................... 49 4-3 program memory map (in m pd750104) ........................................................................... 51 4-4 program memory map (in m pd750106) ........................................................................... 52 4-5 program memory map (in m pd750108) ........................................................................... 53 4-6 program memory map (in m pd75p0116) ......................................................................... 54 4-7 data memory map ............................................................................................................. 56 4-8 general register format .................................................................................................. 58 4-9 register pair format ......................................................................................................... 59 4-10 accumulator ....................................................................................................................... 59 4-11 format of stack pointer and stack bank select register .............................................. 61 4-12 data saved to the stack memory (mk i mode) ............................................................... 62 4-13 data restored from the stack memory (mk i mode) ....................................................... 62 4-14 data saved to the stack memory (mk ii mode) .............................................................. 63 4-15 data restored from the stack memory (mk ii mode) ..................................................... 63 4-16 program status word format ........................................................................................... 64 4-17 bank select register format ............................................................................................ 67 5-1 data memory addresses of digital ports ......................................................................... 69 5-2 configurations of ports 0 and 1 ........................................................................................ 71 5-3 configurations of ports 2 and 7 ........................................................................................ 72 5-4 configurations of ports 3n and 6n (n = 0 to 3) ................................................................ 73 5-5. configurations of ports 4 and 5 ........................................................................................ 74 5-6 configuration of port 8 ...................................................................................................... 75 5-7 formats of port mode registers ...................................................................................... 77 5-8 pull-up resistor specification register format .............................................................. 84 users manual u11330ej2v1um00 list of figures (2/4) figure no. title page 5-9 i/o timing chart of digital i/o ports ................................................................................ 84 5-10 on timing chart of built-in pull-up resistor connected by software ......................... 85 5-11 block diagram of the clock generator ............................................................................ 86 5-12 format of the processor clock control register ............................................................. 89 5-13 format of the system clock control register ................................................................. 90 5-14 external circuit for the main system clock oscillator ..................................................... 91 5-15 external circuit for the subsystem clock oscillator ........................................................ 91 5-16 examples of oscillator connections which should be avoided .................................... 92 5-17 subsystem clock oscillator .............................................................................................. 96 5-18 sub-oscillator control register (sos) format ................................................................ 97 5-19 changing the system clock and cpu clock ................................................................... 99 5-20 configuration of the clock output circuit ...................................................................... 100 5-21 format of the clock output mode register ................................................................... 101 5-22 application to remote control waveform output .......................................................... 102 5-23 block diagram of the basic interval timer/watchdog timer ........................................ 103 5-24 format of the basic interval timer mode register ........................................................ 104 5-25 format of the watchdog timer enable flag (wdtm) ................................................... 105 5-26 block diagram of the clock timer .................................................................................. 109 5-27 clock mode register format .......................................................................................... 110 5-28 block diagram of the timer/event counter (channel 0) ............................................... 112 5-29 block diagram of the timer counter (channel 1) ......................................................... 113 5-30 timer/event counter mode register (channel 0) format ............................................. 115 5-31 timer counter mode register (channel 1) format ....................................................... 116 5-32 timer/event counter output enable flag format ......................................................... 117 5-33 timer/event counter mode register setup ................................................................... 118 5-34 timer/event counter output enable flag setup ........................................................... 119 5-35 configuration of timer/event counter ............................................................................ 121 5-36 count operation timing .................................................................................................. 122 5-37 error at the start of the timer ........................................................................................ 123 5-38 example of the sbi system configuration ..................................................................... 127 5-39 block diagram of the serial interface ............................................................................ 128 5-40 format of serial operation mode register (csim) ....................................................... 130 5-41 format of serial bus interface control register (sbic) ............................................... 134 5-42 peripheral hardware of shift register ........................................................................... 137 5-43 example of three-wire serial i/o system configuration .............................................. 140 5-44 timing of three-wire serial i/o mode ........................................................................... 143 users manual u11330ej2v1um00 list of figures (3/4) figure no. title page 5-45 operations of relt and cmdt ..................................................................................... 144 5-46 transfer bit switching circuit ......................................................................................... 144 5-47 example of two-wire serial i/o system configuration ................................................ 147 5-48 timing of two-wire serial i/o mode .............................................................................. 150 5-49 operations of relt and cmdt ..................................................................................... 151 5-50 example of sbi system configuration ........................................................................... 153 5-51 timing of sbi transfer .................................................................................................... 155 5-52 bus release signal ......................................................................................................... 156 5-53 command signal ............................................................................................................. 156 5-54 address ............................................................................................................................ 156 5-55 slave selection using an address ................................................................................. 157 5-56 command ........................................................................................................................ 157 5-57 data ............................................................................................................................... .. 157 5-58 acknowledge signal ........................................................................................................ 158 5-59 busy and ready signals ................................................................................................. 159 5-60 operations of relt, cmdt, reld, and cmdd (master) ............................................ 164 5-61 operations of relt, cmdt, reld, and cmdd (slave) .............................................. 164 5-62 operation of ackt .......................................................................................................... 165 5-63 operation of acke .......................................................................................................... 165 5-64 operation of ackd ......................................................................................................... 166 5-65 operation of bsye .......................................................................................................... 167 5-66 pin configuration ............................................................................................................. 170 5-67 address transfer operation from master device to slave device (wup = 1) ............ 172 5-68 command transfer operation from master device to slave device ........................... 173 5-69 data transfer operation from master device to slave device ..................................... 174 5-70 data transfer operation from slave device to master device ..................................... 175 5-71 example of serial bus configuration ............................................................................. 177 5-72 transfer format of the read command ....................................................................... 178 5-73 transfer format of the write and end commands ................................................... 179 5-74 transfer format of the stop command ....................................................................... 179 5-75 transfer format of the status command .................................................................. 180 5-76 status format of the status command ...................................................................... 180 5-77 transfer format of the reset command ..................................................................... 181 5-78 transfer format of the chgmst command ................................................................. 181 5-79 master and slave operation in case of error ............................................................... 182 5-80 sck/p01 pin circuit configuration ................................................................................. 183 5-81 format of the bit sequential buffer ................................................................................ 184 users manual u11330ej2v1um00 list of figures (4/4) figure no. title page 6-1 block diagram of interrupt control circuit ..................................................................... 188 6-2 interrupt vector table ..................................................................................................... 189 6-3 interrupt priority specification register .......................................................................... 193 6-4 configurations of the int0, int1, and int4 circuits .................................................... 195 6-5 i/o timing of a noise eliminator .................................................................................... 196 6-6 format of edge detection mode registers .................................................................... 197 6-7 interrupt sequence .......................................................................................................... 199 6-8 multiple interrupt processing by a high-order interrupt ............................................... 200 6-9 multiple interrupt processing by changing the interrupt status flags ......................... 201 6-10 block diagram of the int2 and kr0 to kr7 circuits .................................................... 216 6-11 format of int2 edge detection mode register (im2) ................................................... 217 7-1 standby mode release operation ................................................................................. 221 8-1 configuration of reset functions ................................................................................... 229 8-2 reset operation by generation of reset signal ......................................................... 229 b-1 drawings of the ev-9200g-44 (reference) ................................................................... 310 b-2 recommended pattern on boards for the ev-9200g-44 (reference) ......................... 311 users manual u11330ej2v1um00 list of tables (1/2) table no. title page 2-1 digital i/o port pins ..............................................................................................................9 2-2 non-port pin functions ..................................................................................................... 11 2-3 connection of unused pins .............................................................................................. 21 3-1 addressing modes ............................................................................................................. 27 3-2 register bank to be selected with the rbe and rbs .................................................... 36 3-3 recommended use of register banks with normal routines and interrupt routines . 36 3-4 addressing modes applicable to peripheral hardware operation ................................. 41 4-1 differences between mk i mode and mk ii mode ............................................................ 47 4-2 stack area to be selected by the sbs ............................................................................ 60 4-3 psw flags saved/restored in stack operation ............................................................. 64 4-4 carry flag manipulation instructions ................................................................................ 65 4-5 information indicated by the interrupt status flag .......................................................... 66 4-6 register bank to be selected with the rbe and rbs .................................................... 68 5-1 types and features of digital ports ................................................................................. 70 5-2 i/o pin manipulation instructions ...................................................................................... 80 5-3 operations by i/o port manipulation instructions ............................................................ 82 5-4 specification of built-in pull-up resistors ....................................................................... 83 5-5 maximum time required to change the system clock and cpu clock ....................... 98 5-6 resolution and longest setup time .............................................................................. 120 5-7 serial clock selection and application (in the three-wire serial i/o mode) ............... 143 5-8 serial clock selection and application (in the two-wire serial i/o mode) ................. 151 5-9 serial clock selection and application (in the sbi mode) ............................................ 163 5-10 various signals used in the sbi mode .......................................................................... 168 6-1 interrupt sources ............................................................................................................. 189 6-2 set signals for interrupt request flags ......................................................................... 192 6-3 interrupt processing statuses of ist0 and ist1 ........................................................... 198 6-4 identifying interrupt sharing vector table address ...................................................... 202 6-5 test source ..................................................................................................................... 214 6-6 signals setting test request flags ............................................................................... 214 7-1 operation statuses in the standby mode ...................................................................... 220 users manual u11330ej2v1um00 list of tables (2/2) table no. title page 8-1 status of the hardware after a reset ............................................................................ 230 10-1 selecting mask option of pin ......................................................................................... 239 11-1 types of bit manipulation addressing modes and specification range ...................... 242 users manual u11330ej2v1um00 [memo] 1 users manual u11330ej2v1um00 chapter 1 general the m pd750104, m pd750106, m pd750108, and m pd75p0116 are 75xl series 4-bit single-chip microcontrollers. the 75xl series is a successor of the 75x series consisting of many products. these m pd750104, m pd750106, m pd750108, and m pd75p0116 are collectively called the m pd750108 subseries. the m pd750108 subseries is produced by replacing the main system clock oscillator of the m pd750008 subseries with an rc oscillator, enabling operation at the relatively low voltage of 1.8 v. the 75xl series takes over the cpus of the 75x series, realizing a wide range of operating voltages. in addition to having upward compatibility with existing products, the 75xl series is best suited for battery-driven applications. the m pd750104, m pd750106, m pd750108, and m pd75p0116 have the following features: ? built-in rc oscillator for main system clock oscillation, enabling the immediate start of processing after the release of standby mode. ? operable on low voltage: v dd = 1.8 to 5.5 v ? switchable instruction execution times (useful for power saving) 4, 8, 16, 64 m s (at 1 mhz) 2, 4, 8, 32 m s (at 2 mhz) 122 m s (at 32.768 khz) ? enhanced timers: 4 channels ? easy replacement (the functions and instructions of the m pd750008 are taken over.) the m pd75p0116, having the electrically programmable one-time prom, is pin-compatible with the m pd750104, m pd750106, and m pd750108. it is suitable for small-scale production or prototype production in system development. applications ? camera ? meter ? automobile ? pager remark this manual will explain only the m pd750108 when the m pd750108, m pd750104, m pd750106, and m pd75p0116 are functionally the same. users of the m pd750104, m pd750106, or m pd75p0116 should read m pd750108 as referring to m pd750104, m pd750106, or m pd75p0116. 1 2 m pd750108 user's manual users manual u11330ej2v1um00 1.1 function overview item function instruction execution ? 4, 8, 16, 64 m s (when the main system clock operates at 1 mhz) time ? 2, 4, 8, 32 m s (when the main system clock operates at 2 mhz) ? 122 m s (when the subsystem clock operates at 32.768 khz) internal memory rom 4096 x 8 bits ( m pd750104) 6144 x 8 bits ( m pd750106) 8192 x 8 bits ( m pd750108) 16384 x 8 bits ( m pd75p0116) ram 512 x 4 bits general register ? when operating in 4 bits: 8 x 4 banks ? when operating in 8 bits: 4 x 4 banks i/o port 34 8 cmos input pins can incorporate 25 pull-up resistors 18 cmos i/o pins that are specified with the software. four pins can directly drive the led. 8 n-ch open-drain i/o pins can withstand 13 v. eight pins can directly drive can incorporate pull-up resistors that the led. are specified with the mask option. note timer 4 ? 8-bit timer/event counter: 1 channel ? 8-bit timer counter: 1 channel (clock timer output function is provided) ? basic interval timer/watchdog timer: 1 channel ? clock timer: 1 channel serial interface ? three-wire serial i/o mode (switchable between the start lsb and the start msb) ? two-wire serial i/o mode ? sbi mode bit sequential buffer 16 bits clock output ? f , 125, 62.5, 15.6 khz (when the main system clock operates at 1 mhz) ? f , 250, 125, 31.3 khz (when the main system clock operates at 2 mhz) vectored interrupt external: 3, internal: 4 test input external: 1, internal: 1 system clock oscillator ? rc oscillator for the main system clock (with external resistor and capacitor) ? crystal oscillator for the subsystem clock standby function stop/halt mode operating ambient t a = C40?c to +85?c temperature supply voltage v dd = 1.8 to 5.5 v package 42-pin plastic shrink dip (600 mil) 44-pin plastic qfp (10 x 10 mm) note pull-up resistors, specified with the mask option, are not connected to the m pd75p0116. 3 chapter 1 general users manual u11330ej2v1um00 1.2 ordering information part number package on-chip rom m pd750104cu-xxx 42-pin plastic shrink dip (600 mil) masked rom m pd750104gb-xxx-3bs-mtx 44-pin plastic qfp (10 x 10 mm) masked rom m pd750106cu-xxx 42-pin plastic shrink dip (600 mil) masked rom m pd750106gb-xxx-3bs-mtx 44-pin plastic qfp (10 x 10 mm) masked rom m pd750108cu-xxx 42-pin plastic shrink dip (600 mil) masked rom m pd750108gb-xxx-3bs-mtx 44-pin plastic qfp (10 x 10 mm) masked rom m pd75p0116cu 42-pin plastic shrink dip (600 mil) one-time prom m pd75p0116gb-3bs-mtx 44-pin plastic qfp (10 x 10 mm) one-time prom remark xxx is a rom code number. 4 m pd750108 user's manual users manual u11330ej2v1um00 1.3 differences among m pd750108 subseries products item m pd750104 m pd750106 m pd750108 m pd75p0116 program counter 12 bits 13 bits 14 bits rom (byte) masked rom masked rom masked rom one-time prom 4096 6144 8192 16384 ram (x 4 bits) 512 mask pull-up resistors at incorporated none option ports 4 and 5 (whether to incorporate pull-up resistors can (cannot be be specified.) incorporated.) wait time applied available not available when stop mode is (2 9 /f cc or no wait) note (fixed to 2 9 /f cc .) note released by an interrupt selection to use yes no feedback resistors (whether to use feedback resistors can be (feedback resistors for subsystem clock specified.) are used) pin 6-9 (cu) p33-p30 p33/md3-p30/md0 connection 23-26 (gb) 20 (cu) ic v pp 38 (gb) 38-41 (cu) p43-p40 p43/d3-p40/d0 13-16 (gb) 34-37 (cu) p53-p50 p53/d7-p50/d4 8-11 (gb) others noise immunity and noise radiation vary with the circuit scale and mask layout. note 2 9 /f cc (256 m s at 2 mhz, 512 m s at 1 mhz) caution the noise immunity and noise radiation of the prom model differ from those of the mask rom model. if you replace the prom model with the rom model of the course of experimental production to mass production, perform thorough evaluation by using the cs model (not es model) of the mask rom model. * * 5 chapter 1 general users manual u11330ej2v1um00 1.4 block diagram notes 1. the program counter for the m pd750104 consists of 12 bits, 13 bits for the m pd750106 and m pd750108, and 14 bits for the m pd75p0116. 2. the rom capacity depends on the product. 3. ( ) : m pd75p0116 ti0 pto0 pto1 buz si/sb1 so/sb0 sck int0 int1 int2 basic interval timer/ watchdog timer intbt 8-bit timer/event counter 8-bit timer counter watch timer intt1 clocked serial interface intcsi interrupt control program counter note 1 rom note 2 program memory alu cy p00 - p03 bank decode and control general register f cc /2 n clock output control pcl/p22 clock divider clock generator sub main standby control xt1 xt2 cl1 cl2 v ss reset v dd cpu clock ic (v pp ) note 3 sbs p80, p81 p10 - p13 p20 - p23 p30 - p33 p40 - p43 p50 - p53 p60 - p63 p70 - p73 p30/md0 - note 3 p33/md3 int4 kr0 - kr7 intw intt0 tout0 tout0 reset ram data memory 512 x 4 bits sp port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 bit sequential buffer (16) 2 4 4 4 4 4 4 4 4 ( ) p40/d0 - note 3 p43/d3 ( ) p50/d4 - note 3 p53/d7 ( ) f 6 m pd750108 user's manual users manual u11330ej2v1um00 1.5 pin configuration (top view) (1) 42-pin plastic shrink dip (600 mil) m pd750104cu-xxx m pd750106cu-xxx m pd750108cu-xxx m pd75p0116cu note connect ic (v pp ) to v dd , keeping the wiring as short as possible. remark ( ) : m pd75p0116. xt1 xt2 reset cl1 cl2 p33 (/md3) p32 (/md2) p31 (/md1) p30 (/md0) p81 p80 p03/si/sb1 p02/so/sb0 p01/sck p00/int4 p13/ti0 p12/int2 p11/int1 p10/int0 ic (v pp ) note v dd v ss p40 (/d0) p41 (/d1) p42 (/d2) p43 (/d3) p50 (/d4) p51 (/d5) p52 (/d6) p53 (/d7) p60/kr0 p61/kr1 p62/kr2 p63/kr3 p70/kr4 p71/kr5 p72/kr6 p73/kr7 p20/pto0 p21/pto1 p22/pcl p23/buz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 7 chapter 1 general users manual u11330ej2v1um00 (2) 44-pin plastic qfp (10 x 10 mm) m pd750104gb-xxx-3bs-mtx m pd750106gb-xxx-3bs-mtx m pd750108gb-xxx-3bs-mtx m pd75p0116gb-3bs-mtx note connect ic (v pp ) to v dd , keeping the wiring as short as possible. remark ( ) : m pd75p0116. p72/kr6 p71/kr5 p70/kr4 p63/kr3 p62/kr2 p61/kr1 p60/kr0 p53 (/d7) p52 (/d6) p51 (/d5) p50 (/d4) p13/ti0 p00/int4 p01/sck p02/so/sb0 p03/si/sb1 p80 p81 p30 (/md0) p31 (/md1) p32 (/md2) p33 (/md3) p73/kr7 p20/pto0 p21/pto1 p22/pcl p23/buz v dd ic (v pp ) note p10/int0 p11/int1 p12/int2 nc nc p43 (/d3) p42 (/d2) p41 (/d1) p40 (/d0) v ss xt1 xt2 reset cl1 cl2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 8 m pd750108 user's manual users manual u11330ej2v1um00 pin name p00-p03 : port 0 ti0 : timer input 0 p10-p13 : port 1 pto0, 1 : programmable timer output 0, 1 p20-p23 : port 2 buz : buzzer clock p30-p33 : port 3 pcl : programmable clock p40-p43 : port 4 int0, 1, 4 : external vectored interrupt 0, 1, 4 p50-p53 : port 5 int2 : external test input 2 p60-p63 : port 6 cl1, 2 : rc oscillator p70-p73 : port 7 xt1, 2 : subsystem clock oscillation 1, 2 p80-p81 : port 8 nc : no connection kr0-kr7 : key return 0-7 ic : internally connected sck : serial clock v dd : positive power supply si : serial input v ss : ground so : serial output v pp : programming power supply sb0, 1 : serial bus 0, 1 md0-md3 : mode selection 0-3 reset : reset input d0-d7 : data bus 0-7 9 users manual u11330ej2v1um00 chapter 2 pin functions 2.1 pin functions of the m pd750108 table 2-1. digital i/o port pins (1/2) input/ also 8 bit upon i/o pin used function circuit output as i/o reset type note 1 p00 input int4 4-bit input port (port0). x input b p01 i/o sck for p01 to p03, built-in pull-up resistors f -a p02 i/o so/sb0 can be connected by software in units of f -b p03 i/o si/sb1 3 bits. m -c p10 input int0 4-bit input port (port1). x input b -c p11 int1 built-in pull-up resistors can be connected p12 int2 by software in units of 4 bits. p13 ti0 for p10/int0, the noise eliminator can be selected. p20 i/o pto0 4-bit i/o port (port2). x input e-b p21 pto1 built-in pull-up resistors can be connected p22 pcl by software in units of 4 bits. p23 buz p30 i/o (md0) note 2 programmable 4-bit i/o port (port3). x input e-b p31 (md1) note 2 i/o can be specified bit by bit. p32 (md2) note 2 built-in pull-up resistors can be connected p33 (md3) note 2 by software in units of 4 bits. notes 1. i/o circuits enclosed in circles have a schmitt-triggered input. 2. ( ): m pd75p0116 2 10 m pd750108 user's manual users manual u11330ej2v1um00 table 2-1. digital i/o port pins (2/2) input also 8 bit upon i/o pin output used function circuit as i/o reset type note 1 p40 note 2 i/o (d0) note 3 n-ch open-drain 4-bit i/o port (port4). o high level (when m-d withstand voltage is 13 v in open-drain a pull-up resistor (m-e) note 3 p41 note 2 (d1) note 3 mode. is provided) or a pull-up resistor can be provided bit high impedance p42 note 2 (d2) note 3 by bit (mask option) note 4 . data input/output pins for writing/ p43 note 2 (d3) note 3 verifying (lower 4 bits) of program memory (prom). p50 note 2 i/o (d4) note 3 n-ch open-drain 4-bit i/o port (port5). o high level (when m-d withstand voltage is 13 v in open-drain a pull-up resistor (m-e) note 3 p51 note 2 (d5) note 3 mode. is provided) or a pull-up resistor can be provided bit high impedance p52 note 2 (d6) note 3 by bit (mask option) note 4 . data input/output pins for writing/ p53 note 2 (d7) note 3 verifying (higher 4 bits) of program memory (prom). p60 i/o kr0 programmable 4-bit i/o port (port6). o input f -a p61 kr1 i/o can be specified bit by bit. p62 kr2 built-in pull-up resistors can be p63 kr3 connected by software in units of 4 bits. p70 i/o kr4 4-bit i/o port (port7). input f -a p71 kr5 built-in pull-up resistors can be p72 kr6 connected by software in units of p73 kr7 4 bits. p80 i/o 2-bit input port (port8). x input e-b p81 built-in pull-up resistors can be connected by software in units of 2 bits. notes 1. i/o circuits enclosed in circles have a schmitt-triggered input. 2. when pull-up resistors that can be specified with the mask option are not incorporated (when pins are used as n-ch open-drain input ports), the input leak low current increases when an input instruction or bit operation instruction is executed. 3. ( ): m pd75p0116 4. pull-up resistors, specified with the mask option, are not connected to the m pd75p0116. * * 11 chapter 2 pin functions users manual u11330ej2v1um00 table 2-2. non-port pin functions (1/2) input/ also upon i/o pin output used function reset circuit as type note 1 ti0 input p13 inputs external event pulse to the timer/event counter input b -c pto0 output p20 timer/event counter output input e-b pto1 p21 timer counter output pcl p22 clock output buz p23 arbitrary frequency output (for buzzer or system clock trimming) sck i/o p01 serial clock i/o input f -a so/sb0 p02 serial data output or serial data bus i/o f -b si/sb1 p03 serial data input or serial data bus i/o m -c int4 input p00 edge detection vectored interrupt input b (either a rising or falling edge is detected.) int0 input p10 edge detection vectored interrupt input asynchronous input b -c (the edge to be detected is selectable.) with noise for int0/p10, the noise eliminator eliminator can be selected. selectable int1 p11 asynchronous int2 p12 rising edge detection testable input asynchronous kr0-kr3 input p60-p63 falling edge detection testable input input f -a kr4-kr7 input p70-p73 falling edge detection testable input input f -a cl1 i/o pin for connecting a resistor (r) or capacitor (c) for main system clock oscillation. cl2 output an external clock cannot be input. xt1 input connection pin to a crystal for subsystem clock generation. when an external clock is used, it is input xt2 to xt1, and its inverted signal is input to xt2. xt1 can be used as the 1-bit input (test) pin. reset input system reset input (low-level active) b ic note 2 internally connected. connect to v dd , keeping the wiring as short as possible. v dd positive power supply v ss gnd potential v pp provided only in the m pd75p0116. program voltage application for program memory (prom) write/verify operation. +12.5 v is applied for prom write/verify operation. connect to v dd , keeping the wiring as short as possible. notes 1. the circuits enclosed in circles have a schmitt-triggered input. 2. used as the v pp pin for the m pd75p0116. 12 m pd750108 user's manual users manual u11330ej2v1um00 table 2-2. non-port pin functions (2/2) input/ also upon i/o pin output used function reset circuit as type note md0- input p30-p33 provided only in the m pd75p0116. input e-b md3 mode selection for program memory (prom) write/verify operation. d0-d3 i/o p40-p43 provided only in the m pd75p0116. data bus pins for input m-e d4-d7 p50-p53 program memory (prom) write/verify operation. nc no connection note the circuits enclosed in circles have a schmitt-triggered input. 13 chapter 2 pin functions users manual u11330ej2v1um00 2.2 pin functions 2.2.1 p00-p03 (port0) : input pins also used for int4, sck, so/sb0, and si/sb1 p10-p13 (port1) : input pins also used for int0-int2, and ti0 these are 4-bit input ports, which also have the following functions: (1) port 0 : vectored interrupt input (int4) serial interface i/o (sck, so/sb0, si/sb1) (2) port 1 : vectored interrupt input (int0, int1) edge detection test input (int2) external event pulse input (ti0) for timer/event counter when the serial interface function is used, the operation mode causes the dual-function pin of p0 to become an output pin. schmitt-triggered inputs are used for the pins of port 0 and port 1 to prevent malfunction due to noise. in addition, for p10, the noise eliminator can be selected. (see (3) of section 6.3 for details.) port 0 can be connected with built-in pull-up resistors in units of 3 bits (p01 to p03) by software. port 1 can be connected with built-in pull-up resistors in units of 4 bits (p10 to p13) by software. this is done by manipulating pull-up resistor specification register group a (poga). a reset signal places these pins in input mode. 2.2.2 p20-p23 (port2) : i/o pins also used for pto0, pto1, pcl, and buz p30-p33 (port3) : i/o pins also used for md0-md3 note p40-p43 (port4) : i/o pins also used for d0-d3 note p50-p53 (port5) : n-ch open-drain intermediate withstand voltage (13 v), i/o pins also used for d4-d7 note p60-p63 (port6) : i/o pins also used for kr0-kr3 p70-p73 (port7) : i/o pins also used for kr4-kr7 these are 4-bit i/o ports with output latches, which also have the following functions: 14 m pd750108 user's manual users manual u11330ej2v1um00 (1) port 2 : timer/event counter output (pto0) timer counter output (pto1) clock output (pcl) arbitrary frequency output (buz) (2) port 3 : mode selection for program memory (prom) write/verify operation (md0-md3) note (3) ports 4 and 5 : data bus for program memory (prom) write/verify operation (d0-d3, d4-d7) note (4) ports 6 and 7 : key interrupt input (kr0-kr3, kr4-kr7) note provided only in the m pd75p0116. ports 4 and 5 are n-ch open-drain intermediate withstand voltage (13 v) ports. the port mode register specifies i/o mode selection for each port. ports 2, 4, 5, and 7 can be specified in units of 4 bits. ports 3 and 6 can be specified bit by bit. ports 2, 3, 6, and 7 can be connected with built-in pull-up resistors, in units of 4 bits, by software. this can be done by manipulating pull-up resistor specification register group a (poga). for ports 4 and 5, the use of built-in pull-up resistors can be specified, bit by bit, with the mask option. however, pull-up resistors, specified with the mask option, are not connected to the m pd75p0116. ports 4 and 5, and ports 6 and 7 can be paired for 8-bit i/o. a reset signal places ports 2, 3, 6, and 7 in input mode (high-impedance), and drives ports 4 and 5 high (when a pull-up resistor, specified with the mask option, is incorporated). or, it causes ports 4 and 5 to enter the high-impedance state. 2.2.3 p80, p81 (port8) these are 2-bit i/o ports with output latches. built-in pull-up resistors can be connected to port 8, in units of 2 bits, by software. this can be done by manipulating pull-up resistor specification register group b (pogb). 2.2.4 ti0: input pin also used for port 1 this is an external event pulse input pin for programmable timer/event counter 0. to use this pin, select the external event pulse input as the count pulse (cp) in the timer/event counter mode register (tm0). a schmitt-triggered input is used for the ti0 pin. see (1) of section 5.5.1 for details. 15 chapter 2 pin functions users manual u11330ej2v1um00 2.2.5 pto0, pto1: output pin also used for port 2 these are the output pins of timer/event counter 0 and timer counter 1. square-wave pulses appear on this pin. to output a signal from the timer/event counter and timer counter, clear the output latch to 0, and set bit 2 for port mode register group b to 1. the timer start instruction clears the output of tout flip-flop to 0. see (3) of section 5.5.2 for details. 2.2.6 pcl: output pin also used for port 2 this is the programmable clock output pin. it is used to supply the clock pulse to a peripheral lsi circuit such as a slave microcontroller or a/d converter. a reset signal clears the clock output mode register (clom) to 0, disabling clock output, then the pin is placed in the normal mode to function as a normal port. see section 5.2.4 for details. 2.2.7 buz: output pin also used for port 2 an arbitrary frequency (2.048, 4.096, or 32.768 khz when the subsystem clock operates at 32.768 khz output on this pin can be used for sounding the buzzer or trimming the system clock frequency. this pin is used also as the p23 pin, and can be used only when bit 7 (wm.7) of the clock mode register (wm) is set to 1. a reset signal clears wm.7 to 0, and places this pin in the normal operation mode as a general port. see section 5.4.2 for details. 2.2.8 sck, so/sb0, si/sb1: i/o pins also used for port 0 these are i/o pins for serial interface. they operate according to the setting of the serial operation mode registers (csim). when three-wire serial i/o mode is selected, sck functions as cmos i/o, so functions as cmos output, and si functions as cmos input. when two-wire serial i/o mode is selected, sck functions as cmos i/o, and sb1 (sb0) functions as n-ch open-drain i/o. a reset signal stops serial interface operation and places these pins in the input port mode. a schmitt-triggered input is used for each pin. see section 5.6 for details. 2.2.9 int4: input pin also used for port 0 int4 is an external vectored interrupt input pin, which is rising edge active as well as falling edge active. when a signal applied to this pin goes from low to high or from high to low, the interrupt request flag is set. int4 is an asynchronous input, and can accept a signal with some high level width or low level width regardless of what the cpu clock is. the int4 pin can also be used to release the stop and halt modes. a schmitt-triggered input is used for this pin. 16 m pd750108 user's manual users manual u11330ej2v1um00 2.2.10 int0, int1: input pins also used for port 1 these are the edge detection vectored interrupt input pins. for int0, the noise eliminator can be selected. the edge to be detected can be selected using the edge detection mode registers (im0, im1). (1) int0 (bits 0 and 1 of im0) (a) rising edge active (b) falling edge active (c) both rising and falling edges active (d) external interrupt signal input disabled (2) int1 (bit 0 of im1) (a) rising edge active (b) falling edge active int0 and int1 are asynchronous inputs, and can accept a signal with some high level width regardless of what the cpu clock is. int0 can be provided with the noise eliminator function by software, and change the sampling clock that eliminates the noise at two levels. in this case, the width of the signal received by the cpu operation clock varies. a reset input clears im0 and im1 to 0, selecting rising edge active. the int0 and int1 pins can be used to release stop and halt modes. when the noise eliminator is selected, however, the int0 pin cannot be used to release stop and halt modes. schmitt-triggered inputs are used for the int0 and int1 pins. 2.2.11 int2: input pin also used for port 1 this is a rising edge active, external test input pin. when int2 is selected with the edge detection mode register (im2), or when the signal applied to this pin goes high, the internal test flag (irq2) is set. int2 is an asynchronous input, and can accept a signal with some high level width regardless of the operating clock of the cpu. a reset signal clears im2 to 0. in this case, the test flag (irq2) is set by a rising edge on the int2 pin. the int2 pin can also be used to release the stop and halt modes. a schmitt-triggered input is used for this pin. 17 chapter 2 pin functions users manual u11330ej2v1um00 2.2.12 kr0-kr3: input pins also used for port 6 kr4-kr7: input pins also used for port 7 kr0 to kr7 are key interrupt input pins. an interrupt is caused when parallel falling edges are detected on them. an interrupt source can be selected from among kr0-kr7, kr2-kr7, or kr4-kr7 by means of the edge detection mode register (im2). a reset signal places these pins in the port 6 and 7 input modes. 2.2.13 cl1, cl2 these pins are used for connection to a resistor (r) and capacitor (c) for main system clock generation. an external clock cannot be input. rc oscillation 2.2.14 xt1, xt2 these pins are used for connection to a crystal for subsystem clock oscillation. an external clock can also be applied. (a) crystal oscillation (b) external clock remark if the subsystem clock is not to be used, see (6) of section 5.2.2 . c r cl1 cl2 v ss pd750108 v ss xt1 xt2 crystal pd750108 (standard frequency: 32.768 khz) xt1 xt2 external clock pd750108 18 m pd750108 user's manual users manual u11330ej2v1um00 2.2.15 reset this is the pin for active-low reset input. the reset input is asynchronous. when a signal with certain low level width is applied to the pin, a reset signal is generated to cause a system reset, which has priority over any other operations. the reset signal is used for normal cpu initialize/start operation, and is also used to release stop or halt mode. a schmitt-triggered input is used for the reset input pin. 2.2.16 v dd this is the positive power supply pin. 2.2.17 v ss this is the ground pin. 2.2.18 ic (for the m pd750104, m pd750106, and m pd750108 only) the internally connected (ic) pin is used to set the m pd750108 to test mode for inspection prior to shipping. in normal operation, connect the ic pin to the v dd pin, keeping the writing as short as possible. when the wiring between the ic pin and the v dd pin is too long, or noise is generated on the ic pin, a potential difference may occur between the ic pin and the v dd pin. this may cause your program to malfunction. ? connect the ic pin to the v dd pin, keeping the wiring as short as possible. 2.2.19 v pp (for the m pd75p0116 only) this is a program voltage input pin for program memory (one-time prom) write/verify operation. for normal use, connect this pin to v dd , keeping the wiring as short as possible (shown above). +12.5 v is applied for prom write/verify operation. 2.2.20 md0-md3 (for the m pd75p0116 only) md0 to md3 select a mode for program memory (one-time prom) write/verify operation. 2.2.21 d0-d7 (for the m pd75p0116 only) these are the data bus pins for the program memory (one-time prom) write/verify operation. v dd v dd ic (v pp ) keep the wiring as short as possible * 19 chapter 2 pin functions users manual u11330ej2v1um00 2.3 pin input/output circuits figure 2-1 shows schematic diagrams of the i/o circuitry of the m pd750108. figure 2-1. pin input/output circuits (1/2) type b-c type a type d type b cmos input buffer v dd in p-ch n-ch schmitt trigger input with hysteresis in p.u.r.: pull-up resistor in p-ch p.u.r. enable p.u.r. v dd push-pull output which can be set to high-impedance output (off for both p-ch and n-ch) v dd p-ch n-ch out data output disable 20 m pd750108 user's manual users manual u11330ej2v1um00 figure 2-1. pin input/output circuits (2/2) type e-b type m-c type f-a type f-b type m-e * type m-d * p.u.r.: pull-up resistor p.u.r. v dd p.u.r. enable p-ch in/out data output disable type d type a p.u.r.: pull-up resistor p.u.r. v dd p.u.r. enable p-ch in/out data output disable type d type b p.u.r.: pull-up resistor v dd p-ch n-ch in/out v dd p-ch p.u.r. p.u.r. enable output disable (p-ch) data output disable output disable (n-ch) p.u.r.: pull-up resistor n-ch p.u.r. data output disable p.u.r. enable v dd p-ch in/out n-ch (withstand voltage of +13 v) in/out p-ch v dd note pull-up resistor that operates only when an input instruction is executed with no pull-up resistor contained by mask option. (current flows from v dd to the pins when at low level ) data output disable input instruction (withstand voltage of +13 v) p.u.r. note voltage limitation circuit p.u.r. (mask option) v dd n-ch (withstand voltage of +13 v) in/out p-ch v dd note pull-up resistor that operates only when an input instruction is executed. (current flows from v dd to the pins when at low level) data output disable input instruction (withstand voltage of +13 v) p.u.r. note voltage limitation circuit 21 chapter 2 pin functions users manual u11330ej2v1um00 2.4 connection of unused pins table 2-3. connection of unused pins pin name recommended connection p00/int4 to be connected to v ss or v dd p01/sck to be connected to v ss or v dd through p02/so/sb0 a resistor p03/si/sb1 to be connected to v ss p10/int0-p12/int2 to be connected to v ss or v dd p13/ti0 p20/pto0 input state: to be connected to v ss or p21/pto1 v dd through a resistor p22/pcl output state: to be left open p23/buz p30(/md0)-p33(/md3) note 1 p40-p43 to be connected to v ss . (a pull-up resistor, specified with the mask option, must not be p50-p53 connected.) p60/kr0-p63/kr3 input state: to be connected to v ss or p70/kr4-p73/kr7 v dd through a resistor p80-p81 output state: to be left open xt1 note 2 to be connected to v ss or v dd xt2 note 2 to be left open ic (v pp ) note 1 to be always connected directly to v dd notes 1. ( ): m pd75p0116 2. when the subsystem clock is not to be used, select sos.0 = 1 (the built-in feedback resistor will not be used). * 22 m pd750108 user's manual users manual u11330ej2v1um00 [memo] 23 users manual u11330ej2v1um00 chapter 3 features of the architecture and memory map the 75xl series architecture of the m pd750108 has the following features: ? internal ram of up to 4k words x 4 bits (12-bit address) ? peripheral hardware expansibility to provide these features, the following are used: (1) data memory bank structure (2) general register bank structure (3) memory-mapped i/o this chapter explains these topics. 3.1 data memory bank structure and addressing modes 3.1.1 data memory bank structure in the m pd750108, addresses 000h to 1ffh in data memory space are assigned to static ram (512 words x 4 bits), and addresses f80h to fffh are assigned to peripheral hardware (such as i/o ports and timers). to address a 12-bit location in this data memory space (4k x 4 bits), the m pd750108 uses such a memory bank structure that the low-order eight bits are specified with an instruction directly or indirectly, and the high- order four bits are used to specify a memory bank. to specify a memory bank (mb), two hardware items are incorporated: ? memory bank enable flag (mbe) ? memory bank select register (mbs) the mbs is a register used to select a memory bank, and the register can be set to 0, 1, or 15. the mbe is a flag used to determine whether the memory bank selected using the mbs is valid. as shown in figure 3-1, when the mbe is set to 0, a certain memory bank is always selected regardless of the setting of the mbs. when the mbe is set to 1, memory bank selection depends on the setting of the mbs, thus enabling data memory space expansion. in addressing data memory space, the mbe is usually set to 1 (mbe = 1), and data memory in the memory bank specified in the mbs is operated. however, the mbe = 0 mode or mbe = 1 mode can be selected for each step of processing for more efficient programming. 24 m pd750108 user's manual users manual u11330ej2v1um00 applicable program processing effect mbe = 0 mode ? interrupt processing mbs save/restoration becomes unnecessary. ? processing that repeats internal mbs modification becomes unnecessary. hardware and static ram operations ? subroutine processing mbs save/restoration becomes mbe = 1 mode ? usual program processing figure 3-1. use of mbe = 0 mode and mbe = 1 mode the contents of the mbe are automatically saved or restored at the time of subroutine processing, so that the mbe can be freely modified during subroutine processing. in interrupt processing, the mbe is automatically saved or restored, and when interrupt processing is started, the contents of the mbe can be specified for the interrupt processing by setting the interrupt vector table. this speeds up interrupt processing. the setting of the mbs can be modified for subroutine processing or interrupt processing by saving or restoring the mbs with the push or pop instruction. the mbe is set using the set1 or clr1 instruction. the mbs is set using the sel instruction. examples 1. the mbe is cleared, and a fixed memory bank is used. clr1 mbe ; mbe 25 chapter 3 features of the architecture and memory map users manual u11330ej2v1um00 3.1.2 data memory addressing modes with the architecture of the m pd750108, seven addressing modes summarized in figure 3-2 and table 3-1 are available to address data memory space efficiently for each bit length of data to be processed. these addressing modes enable more efficient programming. (1) 1-bit direct addressing (mem.bit) in this addressing mode, the operand of an instruction can directly specify any bit in the entire data memory space. a particular memory bank (mb) is always used in this addressing mode. in the mbe = 0 mode, when an address from 00h to 7fh is specified in the operand, memory bank 0 (mb = 0) is always used. when an address from 80h to ffh is specified, memory bank 15 (mb = 15) is always used. accordingly, both the data area ranging from 000h to 07fh and the peripheral hardware area ranging from f80h to fffh can be addressed in the mbe = 0 mode. in the mbe = 1 mode, mb = mbs, and specifiable data memory space can be expanded. this addressing mode can be applied to four instructions: bit set and reset instructions (set1 and clr1), and bit test instructions (skt and skf). example flag1 is set, flag2 is reset, and whether flag3 is zero is tested. flag1 equ 03fh.1 ; bit 1 at address 3fh flag2 equ 087h.2 ; bit 2 at address 87h flag3 equ 0a7h.0 ; bit 0 at address a7h set1 mbe ; mbe 27 chapter 3 features of the architecture and memory map users manual u11330ej2v1um00 table 3-1. addressing modes addressing mode representation specified address format 1-bit direct mem.bit bit specified by bit at the address specified by mb and mem. addressing ? when mbe = 0 and mem = 00h-7fh, mb = 0 mem = 80h-ffh, mb = 15 ? when mbe = 1, mb = mbs 4-bit direct mem address specified by mb and mem. addressing ? when mbe = 0 and mem = 00h-7fh, mb = 0 mem = 80h-ffh, mb = 15 ? when mbe = 1, mb = mbs 8-bit direct address specified by mb and mem (mem: even address). addressing ? when mbe = 0 and mem = 00h-7fh, mb = 0 mem = 80h-ffh, mb = 15 ? when mbe = 1, mb = mbs 4-bit register @hl address specified by mb and hl. indirect @hl+ in this case, mb = mbembs addressing @hlC hl+ automatically increments the l register after addressing. hlC automatically decrements the l register after addressing. @de address specified by de in memory bank 0 @dl address specified by dl in memory bank 0 8-bit register @hl address specified by mb and hl. (contents of the l register is indirect an even address.) addressing in this case, mb = mbembs bit fmem.bit bit specified by bit at the address specified by fmem. manipulation in this case, addressing fmem = fb0h-fbfh (interrupt-related hardware) ff0h-fffh (i/o ports) pmem.@l bit specified by the low-order two bits of the l register at the address specified by the high-order 10 bits of pmem and the high-order two bits of the l register. in this case, pmem = fc0h-fffh @h+mem.bit bit specified by bit at the address specified by mb, h, and the low- order four bits of mem. in this case, mb = mbembs stack addressing address specified by the sp in memory bank 0 or 1 selected by the sbs 28 m pd750108 user's manual users manual u11330ej2v1um00 (2) 4-bit direct addressing (mem) in this addressing mode, the operand of an instruction directly specifies any area in the data memory space in units of four bits. as with the 1-bit direct addressing mode, in the mbe = 0 mode, a fixed space consisting of the static ram area ranging from 000h to 07fh and the peripheral hardware area ranging from f80h to fffh can be addressed. in the mbe = 1 mode, mb = mbs, and specifiable data memory space can be expanded to the entire space. this addressing mode can be applied to the mov, xch, incs, in, and out instructions. caution less efficient program processing results if data associated with an i/o port is stored in the static ram area of bank 1 as in example 1. the modification of the mbs, as contained in example 2, becomes unnecessary in the programming if data associated with an i/o port is stored at addresses 00h to 7fh of bank 0. examples 1 . the data contained in buff is output on port 5. buff equ 11ah ; buff located at address 11ah set1 mbe ; mbe |