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1/12 L6561 january 2003 n very precise adjustable output overvoltage protection n micro power start-up current (50 m a typ.) n very low operating supply current(4ma typ.) n internal start-up timer n current sense filter on chip n disable function n 1% precision (@ t j = 25c) internal reference voltage n transition mode operation n totem pole output current: 400ma n dip8/so8 packages description L6561 is the improved version of the l6560 stan- dard power factor corrector. fully compatible with the standard version, it has a superior perfor- mant multiplier making the device capable of work- ing in wide input voltage range applications (from 85v to 265v) with an excellent thd. furthermore the start up current has been reduced at few tens of ma and a disable function has been implement- ed on the zcd pin, guaranteeing lower current consumption in stand by mode. realised in mixed bcd technology, the chip gives the following benefits: C micro power start up curren C 1% precision internal reference voltage (t j = 25c) C soft output over voltage protection C no need for external low pass filter on the current sense C very low operating quiescent current min- imises power dissipation the totem pole output stage is capable of driving a power mos or igbt with source and sink cur- rents of 400ma. the device is operating in tran- sition mode and it is optimised for electronic lamp ballast application, ac-dc adaptors and smps. minidip(dip8) so8 ordering numbers: L6561 L6561d L6561d013tr power factor corrector block diagram + - multiplier v ref2 over-voltage detection voltage regulator uvlo internal supply 7v + - 2.5v r1 r2 r s q +- driver starter + - zero current detector disable 2.1v 1.6v v cc 8 1 23 4 zcd v cc inv comp mult cs gd 7 5 gnd 6 d97in547d 20v 40k 5pf
L6561 2/12 absolute maximum ratings pin connection (top view) thermal data pin description symbol pin parameter value unit i vcc 8i q + i z ; (i gd = 0) 30 ma i gd 7 output totem pole peak current (2ms) 700 ma inv, comp mult 1, 2, 3 analog inputs & outputs -0.3 to 7 v cs 4 current sense input -0.3 to 7 v zcd 5 zero current detector 50 (source) -10 (sink) ma ma p tot power dissipation @t amb = 50 c (minidip) (so8) 1 0.65 w w t j junction temperature operating range -40 to 150 c t stg storage temperature -55 to 150 c symbol parameter so 8 minidip unit r th j-amb thermal resistance junction to ambient 150 100 c/w n. name function 1 inv inverting input of the error amplifier. a resistive divider is connected between the output regulated voltage and this point, to provide voltage feedback. 2 comp output of error amplifier. a feedback compensation network is placed between this pin and the inv pin. 3 mult input of the multiplier stage. a resistive divider connects to this pin the rectified mains. a voltage signal, proportional to the rectified mains, appears on this pin. 4 cs input to the comparator of the control loop. the current is sensed by a resistor and the resulting voltage is applied to this pin. 5 zcd zero current detection input. if it is connected to gnd, the device is disabled. 6 gnd current return for driver and control circuits. 7 gd gate driver output. a push pull output stage is able to drive the power mos with peak current of 400ma (source and sink). 8v cc supply voltage of driver and control circuits. inv comp mult cs 1 3 2 4 zcd gnd gd v cc 8 7 6 5 dip8
3/12 L6561 electrical characteristics (v cc = 14.5v; t amb = -25c to 125c;unless otherwise specified) symbol pin parameter test condition min. typ. max. unit supply voltage section v cc 8 operating range after turn-on 11 18 v v cc on 8 turn-on threshold 11 12 13 v v cc off 8 turn-off threshold 8.7 9.5 10.3 v hys 8 hysteresis 2.2 2.5 2.8 v supply current section i start-u 8 start-up current before turn-on (v cc =11v) 205090 m a i q 8 quiescent current 2.6 4 ma i cc 8 operating supply current c l = 1nf @ 70khz 4 5.5 ma in ovp condition v pin1 = 2.7v 1.4 2.1 ma iq 8 quiescent current v pin5 150mv, v cc > v cc off 1.4 2.1 ma 8v pin5 150mv, v cc < v cc off 20 50 90 m a v z 8 zener voltage i cc = 25ma 18 20 22 v error amplifier section v inv 1 voltage feedback input threshold t amb = 25c 2.465 2.5 2.535 v 12v < v cc < 18v 2.44 2.56 v line regulation v cc = 12 to 18v 2 5 mv i inv 1 input bias current -0.1 -1 ma g v voltage gain open loop 60 80 db gb gain bandwidth 1 mhz i comp 2 source current v comp = 4v, v inv = 2.4v -2 -4 -8 ma sink current v comp = 4v, v inv = 2.6v 2.5 4.5 ma v comp 2 upper clamp voltage i source = 0.5ma 5.8 v lower clamp voltage i sink = 0.5ma 2.25 v multiplier section v mult 3 linear operating voltage 0 to 3 0 to 3.5 v output max. slope v mult = from 0v to 0.5v v comp = upper clamp voltage 1.65 1.9 kgain v mult = 1v v comp = 4v 0.45 0.6 0.75 1/v current sense comparator v cs 4 current sense reference clamp v mult = 2.5v v comp = upper clamp voltage 1.6 1.7 1.8 v i cs 4 input bias current v os = 0 -0.05 -1 m a t d (h-l) 4 delay to output 200 450 ns 4 current sense offset 0 15 mv zero current detector v zcd 5 input threshold voltage rising edge (1) 2.1 v hysteresis (1) 0.3 0.5 0.7 v v zcd 5 upper clamp voltage i zcd = 20 m a 4.5 5.1 5.9 v v zcd 5 upper clamp voltage i zcd = 3ma 4.7 5.2 6.1 v v cs d v mult d -----------------
L6561 4/12 (1) parameter guaranteed by design, not tested in production. over voltage protection ovp the output voltage is expected to be kept by the operation of the pfc circuit close to its nominal value. this is set by the ratio of the two external resistors r1 and r2 (see fig. 2), taking into consideration that the non inverting input of the error amplifier is biased inside the L6561 at 2.5v. in steady state conditions, the current through r1 and r2 is: and, if the external compensation network is made only with a capacitor c comp , the current through ccomp equals zero.when the output voltage increases abruptly the current through r1 becomes: since the current through r2 does not change, d i r1 must flow through the capacitor c comp and enter the error amplifier. this current is monitored inside the L6561 and when reaches about 37 m a the output voltage of the multi- plier is forced to decrease, thus reducing the energy drawn from the mains. if the current exceeds 40 m a, the ovp protection is triggered (dynamic ovp), and the external power transistor is switched off until the current falls approximately below 10 m a. however, if the overvoltage persists, an internal comparator (static ovp) confirms the ovp condition keeping the external power switch turned off (see fig. 1).finally, the overvoltage that triggers the ovp function is: d v out = r 1 40 m a. v zcd 5 lower clamp voltage i zcd = ?3ma 0.3 0.65 1 v i zcd 5 sink bias current 1v v zcd 4.5v 2 m a i zcd 5 source current capability -3 -10 ma i zcd 5 sink current capability 3 10 ma v dis 5 disable threshold 150 200 250 mv i zcd 5 restart current after disable v zcd < v dis ; v cc > v ccoff -100 -200 -300 m a output section v gd 7 dropout voltage i gdsource = 200ma 1.2 2 v i gdsource = 20ma 0.7 1 v i gdsink = 200ma 1.5 v i gdsink = 20ma 0.3 v t r 7 output voltage rise time c l = 1nf 40 100 ns t f 7 output voltage fall time c l = 1nf 40 100 ns i gd off 7 igd sink current v cc =3.5v v gd = 1v 5 10 - ma output overvoltage section i ovp 2 ovp triggering current 35 40 45 m a static ovp threshold 2.1 2.25 2.4 v restart timer t start start timer 70 150 400 m s electrical characteristics (continued) (v cc = 14.5v; t amb = -25c to 125c;unless otherwise specified) symbol pin parameter test condition min. typ. max. unit i r1sc v out 2.5 C r1 ------------------------- - i r2 2.5v r2 ------------ === i r1 v outsc v out 2.5 C d + r1 ---------------------------------------------------- - i r1sc i r1 d + ==
5/12 L6561 typical values for r 1 , r 2 and c are shown in the application circuits. the overvoltage can be set indepen- dently from the average output voltage. the precision in setting the overvoltage threshold is 7% of the ov- ervoltage value (for instance d v = 60v 4.2v). disable function the zero current detector (zcd) pin can be used for device disabling as well. by grounding the zcd volt- age the device is disabled reducing the supply current consumption at 1.4ma typical (@ 14.5v supply volt- age). releasing the zcd pin the internal start-up timer will restart the device. figure 1. figure 2. overvoltage protection circuit v out nominal i sc 40 m a e/a output 2.25v dynamic ovp static ovp d97in592a over voltage 10 m a +vo d97in591 - + 2 r1 r2 ccomp. e/a 1 2.5v d i - + x pwm driver 2.25v 40 m a d i
L6561 6/12 figure 3. typical application circuit (80w, 110vac) figure 4. typical application circuit (120w, 220vac) figure 5. typical application circuit (80w, wide-range mains) 8 3 bridge 4 x 1n4007 r9 (*) 950k c1 1 m f 250v r10 10k c2 22 m f 25v fuse 4a/250v vac (85v to 135v) r3 (*) 240k d3 1n4150 d2 1n5248b r2 100 10nf c6 r1 t 5 6 L6561 7 21 c3 680nf r5 mos stp7na40 d1 byt03-400 r7 (*) 950k c5 100 m f 315v vo=240v po=80w + - d97in549b transformer t: core thomson-csf b1et2910a (etd 29 x 16 x 10mm) or equivalent (orega 473201a7) primary 90t of litz wire 10 x 0.2mm secondary 11t of #27 awg (0.15mm) g ap 1.8mm for a total primar y inductance of 0.7mh r6 (*) 0.31 1w r8 10k 1% + - c7 10nf ntc 4 (*) r3 = 2 x 120k w r6 = 0.619 w /2 r7 = 2 x 475k w , 1% r9 = 2 x 475k w 10 68k 8 3 bridge 4 x 1n4007 r9 (*) 1.82m c1 560nf 400v r10 10k c2 22 m f 25v fuse 2a/250v vac (175v to 265v) r3 (*) 440k d3 1n4150 d2 1n5248b r2 100 10nf c6 r1 t 5 6 L6561 7 21 c3 1 m f r5 mos stp5na50 d1 byt13-600 r7 (*) 998k c5 56 m f 450v vo=400v po=120w + - d97in550b transformer t: core thomson-csf b1et2910a (etd 29 x 16 x 10mm) or equivalent (orega 473201a8) primary 90t of litz wire 10 x 0.2mm secondary 7t of #27 awg (0.15mm) gap 1.25mm for a total primary inductance of 0.8mh r6 (*) 0.41 1w r8 6.34k 1% + - c7 10nf ntc (*) r3 = 2 x 220k w r6 = 0.82 w /2 r7 = 2 x 499k w , 1% r9 = 2 x 909k w 4 68k 10 8 3 bridge 4 x 1n4007 r9 (*) 1.24m c1 1 m f 400v r10 10k c2 22 m f 25v fuse 4a/250v vac (85v to 265v) r3 (*) 240k d3 1n4150 d2 1n5248b r2 100 12nf c6 r1 t 5 6 L6561 7 21 c3 1 m f r5 mos stp8na50 d1 byt13-600 r7 (*) 998k c5 47 m f 450v vo=400v po=80w + - d97in553b transformer t: core thomson-csf b1et2910a (etd 29 x 16 x 10mm) or equivalent (orega 473201a8) primary 90t of litz wire 10 x 0.2mm secondary 7t of #27 awg (0.15mm) gap 1.25mm for a total primary inductance of 0.8mh r6 (*) 0.41 1w r8 6.34k 1% + - c7 10nf ntc (*) r3 = 2 x 120k w r6 = 0.82 w /2 r7 = 2 x 499k w , 1% r9 = 2 x 620k w 4 68k 10
7/12 L6561 figure 6. demo board (evaL6561-80) electrical schematic figure 7. evaL6561-80: pcb and component layout (top view, real size 57x108mm) table 1. evaL6561-80: evaluation results. v in (vac) pin (w) v o (vdc) d vo (v d c ) po (w) h (%) w/o thd reducer with thd reducer pf thd (%) pf thd (%) 85 87.2 400.1 14 80.7 92.8 0.999 3.7 0.999 2.9 110 85.2 400.1 14 80.7 94.7 0.996 5.0 0.996 3.2 135 84.2 400.1 14 80.7 95.8 0.989 6.2 0.989 3.7 175 83.5 400.1 14 80.7 96.6 0.976 8.3 0.976 4.3 220 83.1 400.1 14 80.7 97.1 0.940 10.7 0.941 5.6 265 82.9 400.1 14 80.7 97.3 0.890 13.7 0.893 8.1 ntc 2.5 8 3 bridge w04m r1 750 k c1 1 f 400v r3 10 k c29 22 f 25v fuse 4a/250v r4 180 k d8 1n4150 d2 1n5248b r14 100 c5 12 nf r6 68 k t 5 6 L6561 7 21 r7 33 mos stp8nm50 4 r11 750 k c6 47 f 450v vo=400v po=80w - vac (85v to 265v) r9 0.41 1w r13 9.53 k + - c4 100 nf c2 10nf d1 stth1l06 d3 1n4148 c7 10 f 35 v r15 220 r16 91 k r50 12 k c3 470 nf r2 750 k r5 180 k r10 0.41 1w r12 750 k c23 1 f boost inductor spec (itacoil e2543/e) e25x13x7 core, 3c85 ferrite 1.5 mm gap for 0.7 mh primary inductance primary: 105 turns 20x0.1 mm secondary: 11 turns 0.1mm thd reducer (optional)
L6561 8/12 figure 8. ovp current threshold vs. temperature figure 9. undervoltage lockout threshold vs. temperature figure 10. supply current vs. supply voltage figure 11. voltage feedback input threshold vs. temperature -50 -25 0 25 50 75 100 125 t ( ?c ) 38 39 40 41 i ovp ( m a) d94in047a -25 0 25 50 75 100 125 t ( ?c ) 9 10 11 12 13 v cc-on (v) v cc-off (v) d94in044a d97in548a 0 5 10 15 20 v cc (v) 0 0.005 0.01 0.05 0.1 0.5 1 5 10 i cc (ma) c l = 1nf f = 70khz t a = 25?c d97in548a 0 5 10 15 20 v cc (v) 0 0.005 0.01 0.05 0.1 0.5 1 5 10 i cc (ma) c l = 1nf f = 70khz t a = 25?c
9/12 L6561 figure 12. output saturation voltage vs. sink current figure 13. output saturation voltage vs. source current figure 14. multiplier characteristics family 0 100 200 300 400 i gd (ma) 0 0.5 1.0 1.5 2.0 v pin7 (v) sink v cc = 14.5v d94in046 0 100 200 300 400 i gd (ma) 0 v cc -2.0 v cc -1.5 v cc -1.0 v cc -0.5 v pin7 (v) source v cc = 14.5v d94in053 v mult (pin3) (v) d97in555a 2.6 3.0 3.2 3.5 4.5 5.0 v comp (pin2) (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 v cs (pin4) (v) 4.0 2.8 upper voltage clamp
L6561 10/12 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 3.32 0.131 a1 0.51 0.020 b 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 d 10.92 0.430 e 7.95 9.75 0.313 0.384 e2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 f 6.6 0.260 i 5.08 0.200 l 3.18 3.81 0.125 0.150 z 1.52 0.060 minidip
11/12 L6561 dim. mm inch min. typ. max. min. typ. max. a 1.75 0.069 a1 0.1 0.25 0.004 0.010 a2 1.65 0.065 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.020 c1 45 (typ.) d (1) 4.8 5.0 0.189 0.197 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 f (1) 3.8 4.0 0.15 0.157 l 0.4 1.27 0.016 0.050 m 0.6 0.024 s8 (max.) (1) d and f do not include mold flash or protrusions. mold flash or potrusions shall not exceed 0.15mm (.006inch). so8 outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. stmicroelectronics acknowledges the trademarks of all companies referred to in this document. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 12/12 L6561

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