1/6 AN1214 application note december 2000 introduction designing a pfc circuit with a singular input voltage and a singular output power is a task that is rather straight forward and gives a very good set of component values when the design equations are used. the task becomes a little more difficult when a wide range pfc is needed and the specifications are tight. this is common in ap- plications such as lighting where there is a demand for good power factor ( >.99) and thd less than 10% in the full range of nominal operating conditions. the problem occurs since the design must be done for the worst case conditions which are a low input voltage and maximum output power. as we will see, this will diminish the performance of the pfc circuit when the input voltage is high and the output power is low. what must be done in this case is to look closely at the limits of the l6561 and external components and to optimize or compromise where needed. design tips multiplier operation . once the initial design is done and measurements have been made, the next step is to look at the operating parameters of the l6561 to see that it is working within its full capabilities without going over its linear operating range. a copy of the table we will be referring to is shown in fig. 1. for optimal operation the device should stay in the linear operation of the multiplier. as can be seen, there are three pins that should be measured in the worst case conditions. the first is with the lowest in- put voltage (low line) and the highest output power. the second is at the highest input voltage (high line) and the lowest output power. the first pin to be measured is the vcomp (pin2). this is the output of the error amplifier (figure 2) and will determine which curve will be referenced when measuring the other two parameters - vcs and vmult. once this is established, the peak voltage of the multiplier input (pin 3) should be measured and noted. next mea- sure the peak voltage of the current sense resistor (vcs - pin 4). looking at the graph in figure 1, de- termine which curve to use from the vcomp voltage. v mult (pin3) (v) d97in555a 2.6 3.0 3.2 3.5 4.5 5.0 v comp (pin2) (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 v cs (pin4) (v) 4.0 2.8 upper voltage clamp by cliff ortmeyer & claudio adragna design tips for l6561 power factor corrector in wide range this application note will describe some basic steps to optimize the design of the l6561 pfc for wide range voltage input (105v- 300v) while also having a broad output power range (65w - 105w). initial design steps are covered in application note an966. this is to serve as a supplement to that applica- tion note and also give an example of a wide range demo board optimized for the us market (110v - 277v). a deeper look at the control of the l6561 can also be found in application note an1089 control loop modeling of l6561-based tm pfc. figure 1. multiplier characteristics
AN1214 application note 2/6 next, note where the vcs and vmult are on the curve to make sure that they are in the linear operating region. if operation in the linear region is not met, adjust the variable that allows linear operation to be met. if however the device is operating in the linear region but is not allowing the full range of the multiplier to be used, then increasing one of the variables (the multiplier voltage for example) can help to maximize the full operating range of the multiplier. figure 2. multiplier block diagram. zero crossing dead time . once the multiplier operating parameters have been met, the input voltage as well as the input current should be looked at together. one problem to look for is a distortion of the current waveform especially at high line and low load. an example can be seen in figure 3. figure 3. current shape at zero crossing with high capacitance fet and slow turn-on diode. the main reason for this effect is that near zero-crossings the energy stored in the inductor is very low, not enough to charge up the drain node total capacitance (basically, the fets drain-to-source capacitance c oss and the inductors parasitic intrawinding capacitance) to turn the boost diode on. the turn-on speed of the boost diode adds to the problem as well. as a result, energy is exchanged between reactive components and there is no input-to-output transfer. this can be seen in figure 3. to minimize coss, the rds (on) of the fet should be maximized within the limits of acceptable conduction loss- es, and its voltage rating should be the minimum that still provides adequate breakdown capability. in fact, both d97in675 + - e/a 4 x curr.cmp 23 rs 1.7v
3/6 AN1214 application note a low rds (on) and a high voltage imply a higher c oss . inductor parasitic capacitance can be reduced by minimizing the number of winding layers. adding a layer of tape between winding layers can reduce the capacitance considerably. the use of a slotted bobbin is also very effective. also optimizing the diode can offer a positive contribution. a minimum junction capacitance will be somewhat beneficial, even though this is a minor contribution to the total drain capacitance. a major improvement can be offered by a diode with a well controlled die resistivity (such as turboswitch series) which has a lower peak forward voltage, so that it actually turns on just a few volts above the pfc output voltage. an example of the improvement given by optimizing the fet and the diode is shown in figure 4. figure 4. current shape at zero crossing with lower capacitance fet and turboswitch diode input capacitance (emi filtering). another source of error can be due to the input filter. since the voltage output from the rectifier bridge is used as the reference for the current to follow, any distortions in this waveform will translate into distortions of the current waveform, hence lower power factor or greater thd. one cause of this can be due to too large of a high frequency filter capacitor being used after the bridge. a high value capacitor can filter the rectified voltage and cause the voltage to deviate from a rectified sinusoid and even not reach zero at light load. this can be seen in figure 5. figure 5. non-discontinuous voltage error the obvious way of improving this is to lower the high frequency capacitor value. care must be taken not to lower the capacitance such that the effectiveness of the emi filter (in front of the diode bridge) is not degraded so as to not pass regulatory requirements. so, by lowering that capacitance, the hf filter capacitor in front of the diode bridge may need to be increased. switching frequency. one other method of using the full dynamic range of the l6561 is to reduce the minimum switching frequency of the fet. by using the lowest possible switching frequency of the l6561, a wider range
AN1214 application note 4/6 of switching frequencies are available to be used. this helps minimize the effects of the internal propagation delay as well as the offset of the current sense comparator. in this way the current will track the voltage wave- form better, in particular near the zero-crossings. this, however, must be weighed against the size increase of the inductor because a lower switching frequency implies a larger inductance value. when determining the lowest frequency, it must be noted that switching below 15khz is not recommended since this may interfere with the internal starter. a special construction technique of the inductor can offer the optimum compromise: one that allows the use of a low inductance value so as to minimize inductor size and, at the same time, have a lower switching frequency near zero-crossings. the price to pay for that is an additional step in the inductor manufacturing flow. it is the so-called step-gap core technique: the centre leg of one half of the ferrite core is ground so that the air gap thickness has a step change, as shown in fig. 6. at low inductor current the small thinner part of the air gap dictates a high inductance value (l1). as current increases above a certain value (i l1 ), the thinner part of the air gap will progressively saturate and the induc- tance will drop to a value (l2 5/6 AN1214 application note wide range example circuit an example circuit was designed with a varying voltage input of 110v to 277v and an output power of 65w to 105w. the techniques in this paper (except the step-gap core) were used to help bring the power factor and thd into acceptable levels. the example schematic and associated emi filter are shown below along with the measured results. figure 7. example schematic figure 8. emi filter table 1. example schematic results vin [v ac ) vout [v] iout [ma] pf thd [%] pin [w] pout [w] efficiency [%] 105 449 136 0.998 4.7 66.4 61.0 91.9 120 449 136 0.998 5.3 65.8 61.0 92.7 277 449 136 0.995 9.7 65.0 61.0 93.9 300 449 136 0.993 11.0 65.0 61.0 93.9 105 449 237 0.999 4.0 115.8 106.5 92.0 120 449 237 0.999 4.0 114.7 106.5 92.9 277 449 237 0.997 7.7 111.0 106.5 96.0 300 449 237 0.994 11.2 111.0 106.5 96.0 8 3 bridge 4 x 1n4007 r9 (*) 1.24m c1 33nf 630v r10 10k c2 22 m f 25v fuse 4a/250v vac (105v to 305v) r3 (*) 240k d3 1n4150 d2 1n5248b r2 100 12nf c6 r1 t 5 6 l6561 7 21 c3 1 m f r5 mos stp6nb50 d1 stta106 r7 (*) 998k c5' 47 m f 250v c5 47 m f 250v r11 1m r12 1m vo=450v po=105w + - d99in1098 transformer t: core thomson-csf b1et2910a (etd 29 x 16 x 10mm) or equivalent (orega 473201a8) primary 90t of litz wire 10 x 0.2mm secondary 7t of #27 awg (0.15mm) gap 1.25mm for a total primary inductance of 0.8mh r6 (*) 0.5 1w r8 5.6k 1% + - c7 10nf ntc (*) r3 = 2 x 120k w r6 = 1 w /2 r7 = 2 x 499k w , 1% r9 = 2 x 620k w 4 68k 10 c x d97in680 t1 t2 c y line pfc earth
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