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renesas 8-bit cisc single-chip microcomputer 740 family / 740 series 7540 group 8 rev. 1.10 revision date: may. 28, 2003 user?s manual www.renesas.com before using this material, please visit our website to confirm that this is the most current document available. rej09b0018-0110z
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revision history rev. date description page summary (1/1) 7540 group user? manual 1.00 sep. 17, 2002 1.10 may 28, 2003 first edition issued [pull-up control register] pull; note added. fig.15; note 2 eliminated. fig.17; (2) ports p0 1 ,p0 2 revised. fig.29; port p0 3 direction register block, port p0 1 direction register block and port p0 2 direction register block revised. (3) rc oscillation revised. fig.2.4.12; rti rts fig.2.4.16; prescaler x 1/4 1/2, cntr 0 pin output 4 mhz 4 khz fig.2.4.17; the second cpum setting 00000x00 2 11000x00 2 prescaler x 03 16 01 16 , note 2 revised. fig.2.4.26; the followings are revised. the second setting of cntr 0 interrupt enable bit and timer x interrupt enable bit. the second setting of timer x mode register. fig.3.3.5; nop added. 1-17 1-19 1-34 1-45 2-49 2-52 2-53 2-61 3-86
before using this manual this user? manual consists of the following three chapters. refer to the chapter appropriate to your conditions, such as hardware design or software development. chapter 3 also includes necessary information for systems development. you must refer to that chapter. 1. organization chapter 1 hardware this chapter describes features of the microcomputer and operation of each peripheral function. chapter 2 application this chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. chapter 3 appendix this chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the list of registers. as for the mask rom confirmation form, the rom programming confirmation form, and the mark specification form which are to be submitted when ordering, refer to the ?enesas technology corp homepage (http://www.renesas.com/en/rom). 2. structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows : note 2 : bit attributes......... the attributes of control register bits are classified into 3 bytes : read-only, write- only and read and write. in the figure, these attributes are represented as follows : : bit in which nothing is arranged 0 1 : name function at reset rw b 0 1 2 3 4 0 0 0 0 0 ? ? contents immediately after reset release bit attributes (note 1) processor mode bits stack page selection bit nothing arranged for these bits. these are write disabled bits. when these bits are read out, the contents are 0. fix this bit to 0. main clock (x in -x out ) stop bit internal system clock selection bit 0 0 : single-chip mode 1 0 : 1 1 : not available b1 b0 0 : 0 page 1 : 1 page 0 : operating 1 : stopped 0 : x in -x out selected 1 : x cin -x cout selected : bit that is not used for control of the corresponding function 0 note 1 :. contents immediately after reset release 0....... 0 at reset release 1....... 1 at reset release ?....... undefined at reset release ? ? ? ? 0 write (note 2) cpu mode register (cpum) [address : 3b 16 ] bits ? ? 3. supplementation for details of software, refer to the 740 family software manual. for development tools, refer to the renesas technology corp homepage (http://www.renesas.com/en/tools) .
7540 group user? manual i table of contents table of contents chapter 1 hardware description ............................................................................................................................... . 1-2 features ............................................................................................................................... ....... 1-2 application ............................................................................................................................... . 1-2 pin configuration .................................................................................................................. 1-3 functional block .................................................................................................................. 1-5 pin description ........................................................................................................................ 1-8 group expansion .................................................................................................................... 1-9 functional description .................................................................................................... 1-11 central processing unit (cpu) ............................................................................................ 1-11 memory ............................................................................................................................... ..... 1-15 i/o ports ............................................................................................................................... ... 1-17 interrupts ..................................................................................................................... ............ 1-21 key input interrupt (key-on wake-up) ............................................................................... 1-23 timers ............................................................................................................................... ....... 1-24 serial i/o ............................................................................................................................... .. 1-35 a-d converter ......................................................................................................................... 1-41 watchdog timer ..................................................................................................................... 1-42 reset circuit ........................................................................................................................... 1-43 clock generating circuit ....................................................................................................... 1-45 notes on programming ..................................................................................................... 1-49 processor status register .................................................................................................... 1-49 interrupts ..................................................................................................................... ............ 1-49 decimal calculations .............................................................................................................. 1-49 ports ............................................................................................................................... .......... 1-49 a-d conversion ...................................................................................................................... 1-49 instruction execution timing ................................................................................................. 1-49 cpu mode register ............................................................................................................... 1-49 state transition ...................................................................................................................... 1-49 notes on hardware ............................................................................................................ 1-49 handling of power source pin ............................................................................................. 1-49 one time prom version ..................................................................................................... 1-49 notes on peripheral functions .................................................................................. 1-50 interrupt ............................................................................................................................... 1-50 timers ............................................................................................................................... ... 1-50 timer a ............................................................................................................................... 1-50 timer x ............................................................................................................................... 1-50 timer y: programmable generation waveform mode .................................................. 1-50 timer z: programmable waveform generation mode .................................................. 1-50 timer z: programmable one-shot generation mode ................................................... 1-51 timer z: programmable wait one-shot generation mode .......................................... 1-51 serial i/o ............................................................................................................................. 1- 51 a-d converter .................................................................................................................... 1-51 notes on clock generating circuit ................................................................................. 1-52 data required for mask orders ................................................................................ 1-53 data required for rom programming orders .................................................... 1-53 rom programming method .............................................................................................. 1-53 functional description supplement ......................................................................... 1-54 interrupt ............................................................................................................................... .... 1-54 timing after interrupt ............................................................................................................. 1-55 a-d converter ......................................................................................................................... 1-56
ii 7540 group user? manual table of contents chapter 2 application 2.1 i/o port ............................................................................................................................... ...... 2-2 2.1.1 memory map ................................................................................................................... 2-2 2.1.2 relevant registers .......................................................................................................... 2-3 2.1.3 application example of key-on wake up (1) ............................................................... 2-7 2.1.4 application example of key-on wake up (2) ............................................................... 2-9 2.1.5 handling of unused pins ............................................................................................. 2-10 2.1.6 notes on input and output ports ................................................................................ 2-11 2.1.7 termination of unused pins ........................................................................................ 2-12 2.2 timer a ............................................................................................................................... ... 2-13 2.2.1 memory map ................................................................................................................. 2-13 2.2.2 relevant registers ........................................................................................................ 2-14 2.2.3 timer mode ................................................................................................................... 2-19 2.2.4 period measurement mode ......................................................................................... 2-22 2.2.5 event counter mode ..................................................................................................... 2-26 2.2.6 pulse width hl continuously measurement mode ................................................... 2-30 2.2.7 notes on timer a .......................................................................................................... 2-35 2.3 timer 1 ............................................................................................................................... .... 2-36 2.3.1 memory map ................................................................................................................. 2-36 2.3.2 relevant registers ........................................................................................................ 2-36 2.3.3 timer 1 operation description ..................................................................................... 2-39 2.3.4 notes on timer 1 .......................................................................................................... 2-39 2.4 timer x ............................................................................................................................... ... 2-40 2.4.1 memory map ................................................................................................................. 2-40 2.4.2 relevant registers ........................................................................................................ 2-41 2.4.3 timer mode ................................................................................................................... 2-46 2.4.4 pulse output mode ....................................................................................................... 2-50 2.4.5 event counter mode ..................................................................................................... 2-54 2.4.6 pulse width measurement mode ................................................................................ 2-58 2.4.7 notes on timer x .......................................................................................................... 2-62 2.5 timer y and timer z ........................................................................................................... 2-63 2.5.1 memory map ................................................................................................................. 2-63 2.5.2 relevant registers ........................................................................................................ 2-64 2.5.3 timer mode (timer y and timer z) ............................................................................ 2-73 2.5.4 programmable waveform generation mode (timer y and timer z) ....................... 2-77 2.5.5 programmable one-shot generation mode (timer z) ............................................... 2-84 2.5.6 programmable wait one-shot generation mode (timer z) ....................................... 2-91 2.5.7 notes on timer y and timer z .................................................................................... 2-99 2.6 serial i/o1 ................................................................................................................ ............ 2-101 2.6.1 memory map ............................................................................................................... 2-101 2.6.2 relevant registers ...................................................................................................... 2-101 2.6.3 serial i/o1 transfer data format ............................................................................... 2-105 2.6.4 application example of clock synchronous serial i/o1 ......................................... 2-106 2.6.5 application example of clock asynchronous serial i/o1 ....................................... 2-112 2.6.6 notes on serial i/o1 .................................................................................................. 2-118 2.7 serial i/o2 ................................................................................................................ ............ 2-120 2.7.1 memory map ............................................................................................................... 2-120 2.7.2 relevant registers ...................................................................................................... 2-120 2.7.3 application example of serial i/o2 ........................................................................... 2-123 2.7.4 notes on serial i/o2 .................................................................................................. 2-128 2.8 a-d converter ..................................................................................................................... 2-129 2.8.1 memory map ............................................................................................................... 2-129 2.8.2 relevant registers ...................................................................................................... 2-129 2.8.3 a-d converter application examples ........................................................................ 2-132 2.8.4 notes on a-d converter ............................................................................................ 2-134
7540 group user? manual iii table of contents 2.9 oscillation control ............................................................................................................. 2-135 2.9.1 memory map ............................................................................................................... 2-135 2.9.2 relevant registers ...................................................................................................... 2-135 2.9.3 application example of ring oscillator ..................................................................... 2-137 2.9.4 oscillation stop detection circuit .............................................................................. 2-139 2.9.5 state transition ........................................................................................................... 2-142 2.9.6 notes on oscillation stop detection circuit .............................................................. 2-145 chapter 3 appendix 3.1 electrical characteristics ..................................................................................................... 3-2 3.1.1 7540 group (general purpose) .................................................................................... 3-2 3.1.2 7540group (extended operating temperature version) ........................................... 3-13 3.1.3 7540group (extended operating temperature 125 ? version) ............................. 3-22 3.2 typical characteristics ....................................................................................................... 3-31 3.2.1 mask rom version ...................................................................................................... 3-31 3.2.2 one time prom version ............................................................................................ 3-52 3.3 notes on use ........................................................................................................................ 3-73 3.3.1 notes on input and output ports ................................................................................ 3-73 3.3.2 termination of unused pins ........................................................................................ 3-74 3.3.3 notes on timer ............................................................................................................. 3-75 3.3.4 notes on timer a ........................................................................................................ 3-75 3.3.5 notes on timer 1 .......................................................................................................... 3-75 3.3.6 notes on timer x ........................................................................................................ 3-76 3.3.7 notes on timer y and timer z .................................................................................... 3-77 3.3.8 notes on serial i/o1 .................................................................................................... 3-79 3.3.9 notes on serial i/o2 .................................................................................................... 3-81 3.3.10 notes on a-d converter ............................................................................................ 3-82 3.3.11 notes on oscillation stop detection circuit .............................................................. 3-83 3.3.12 notes on cpu mode register ................................................................................... 3-85 3.3.13 notes on interrupts .................................................................................................... 3 -86 3.3.14 notes on reset pin ................................................................................................. 3-87 3.3.15 notes on programming .............................................................................................. 3-88 3.3.16 programming and test of built-in prom version ................................................... 3-90 3.3.17 handling of power source pin ................................................................................. 3-90 3.3.18 notes on built-in prom version .............................................................................. 3-91 3.4 countermeasures against noise ...................................................................................... 3-92 3.4.1 shortest wiring length .................................................................................................. 3-92 3.4.2 connection of bypass capacitor across v ss line and v cc line ............................... 3-94 3.4.3 wiring to analog input pins ........................................................................................ 3-95 3.4.4 oscillator concerns ....................................................................................................... 3-95 3.4.5 setup for i/o ports ....................................................................................................... 3-96 3.4.6 providing of watchdog timer function by software .................................................. 3-97 3.5 list of registers ................................................................................................................... 3-98 3.6 package outline ................................................................................................................. 3-120 3.7 machine instructions ........................................................................................................ 3-122 3.8 list of instruction code ................................................................................................... 3-133 3.9 sfr memory map .............................................................................................................. 3-134 3.10 pin configurations ........................................................................................................ ... 3-135 3.11 differences between 7540 group and 7531 group ................................................. 3-139
iv 7540 group user? manual list of figures list of figures chapter 1 hardware fig. 1 pin configuration (32p6u-a type) ..................................................................................... 1-3 fig. 2 pin configuration (36p2r-a type) ..................................................................................... 1-3 fig. 3 pin configuration (32p4b-a type) ..................................................................................... 1-4 fig. 4 pin configuration (42s1m type) ........................................................................................ 1-4 fig. 5 functional block diagram (32p6u package) ................................................................... 1-5 fig. 6 functional block diagram (36p2r package) ................................................................... 1-6 fig. 7 functional block diagram (32p4b package) ................................................................... 1-7 fig. 8 memory expansion plan ..................................................................................................... 1-9 fig. 9 740 family cpu register structure ................................................................................. 1-11 fig. 10 register push and pop at interrupt generation and subroutine call ....................... 1-12 fig. 11 structure of cpu mode register ................................................................................... 1-14 fig. 12 switching method of cpu mode register .................................................................... 1-14 fig. 13 memory map diagram .................................................................................................... 1-15 fig. 14 memory map of special function register (sfr) ........................................................ 1-16 fig. 15 structure of pull-up control register ............................................................................. 1-17 fig. 16 structure of port p1p3 control register ....................................................................... 1-17 fig. 17 block diagram of ports (1) ............................................................................................ 1-19 fig. 18 block diagram of ports (2) ............................................................................................ 1-20 fig. 19 interrupt control ............................................................................................................... 1-22 fig. 20 structure of interrupt-related registers ........................................................................ 1-22 fig. 21 connection example when using key input interrupt and port p0 block diagram 1-23 fig. 22 structure of timer a mode register .............................................................................. 1-25 fig. 23 structure of timer x mode register .............................................................................. 1-26 fig. 24 timer count source set register ................................................................................... 1-26 fig. 25 structure of timer y, z mode register ......................................................................... 1-32 fig. 26 structure of timer y, z waveform output control register ......................................... 1-32 fig. 27 structure of one-shot start register .............................................................................. 1-32 fig. 28 block diagram of timer 1 and timer a ......................................................................... 1-33 fig. 29 block diagram of timer x, timer y and timer z ......................................................... 1-34 fig. 30 block diagram of clock synchronous serial i/o1 ........................................................ 1-35 fig. 31 operation of clock synchronous serial i/o1 function ................................................ 1-35 fig. 32 block diagram of uart serial i/o1 ............................................................................. 1-36 fig. 33 operation of uart serial i/o1 function ...................................................................... 1-36 fig. 34 structure of serial i/o1-related registers ..................................................................... 1-38 fig. 35 structure of serial i/o2 control registers ..................................................................... 1-39 fig. 36 block diagram of serial i/o2 ......................................................................................... 1-39 fig. 37 serial i/o2 timing (lsb first) ........................................................................................ 1-40 fig. 38 structure of a-d control register .................................................................................. 1-41 fig. 39 structure of a-d conversion register ........................................................................... 1-41 fig. 40 block diagram of a-d converter ................................................................................... 1-41 fig. 41 block diagram of watchdog timer ................................................................................. 1-42 fig. 42 structure of watchdog timer control register .............................................................. 1-42 fig. 43 example of reset circuit ................................................................................................. 1-43 fig. 44 timing diagram at reset ................................................................................................ 1-43 fig. 45 internal status of microcomputer at reset ................................................................... 1-44 fig. 46 external circuit of ceramic resonator ........................................................................... 1-45 fig. 47 external circuit of rc oscillation .................................................................................. 1-45 fig. 48 external clock input circuit ............................................................................................ 1-45
7540 group user? manual v fig. 49 processing of x in and x out pins at ring oscillator operation .................................... 1-45 fig. 50 structure of misrg ........................................................................................................ 1-46 fig. 51 block diagram of internal clock generating circuit (for ceramic resonator) ........... 1-47 fig. 52 block diagram of internal clock generating circuit (for rc oscillation) ................... 1-47 fig. 53 state transition ................................................................................................................ 1-48 fig. 54 programming and testing of one time prom version ............................................ 1-53 fig. 55 timing chart after an interrupt occurs ......................................................................... 1-55 fig. 56 time up to execution of the interrupt processing routine ........................................ 1-55 fig. 57 a-d conversion equivalent circuit ................................................................................. 1-57 fig. 58 a-d conversion timing chart .......................................................................................... 1-57 chapter 2 application fig. 2.1.1 memory map of registers relevant to i/o port ......................................................... 2-2 fig. 2.1.2 structure of port pi (i = 0, 2, 3) ................................................................................ 2-3 fig. 2.1.3 structure of port p1 ..................................................................................................... 2-3 fig. 2.1.4 structure of port pi direction register (i = 0, 2, 3) ................................................. 2-4 fig. 2.1.5 structure of port p1 direction register ...................................................................... 2-4 fig. 2.1.6 structure of pull-up control register .......................................................................... 2-5 fig. 2.1.7 structure of port p1p3 control register .................................................................... 2-5 fig. 2.1.8 structure of interrupt edge selection register .......................................................... 2-6 fig. 2.1.9 structure of interrupt request register 1 ................................................................... 2-6 fig. 2.1.10 structure of interrupt control register 1 .................................................................. 2-7 fig. 2.1.11 example of application circuit .................................................................................. 2-7 fig. 2.1.12 example of control procedure (1) ............................................................................ 2-8 fig. 2.1.13 example of control procedure (2) ............................................................................ 2-9 fig. 2.2.1 memory map of registers relevant to timer a ........................................................ 2-13 fig. 2.2.2 structure of port p0 direction register .................................................................... 2-14 fig. 2.2.3 structure of pull-up control register ........................................................................ 2-14 fig. 2.2.4 structure of timer a mode register ......................................................................... 2-15 fig. 2.2.5 structure of timer a register .................................................................................... 2-16 fig. 2.2.6 structure of interrupt edge selection register ........................................................ 2-16 fig. 2.2.7 structure of interrupt request register 1 ................................................................. 2-17 fig. 2.2.8 structure of interrupt request register 2 ................................................................. 2-17 fig. 2.2.9 structure of interrupt control register 1 .................................................................. 2-18 fig. 2.2.10 structure of interrupt control register 2 ................................................................ 2-18 fig. 2.2.11 setting method for timer mode .............................................................................. 2-20 fig. 2.2.12 example of control procedure ................................................................................ 2-21 fig. 2.2.13 setting method for period measurement mode (1) ............................................. 2-22 fig. 2.2.14 setting method for period measurement mode (2) ............................................. 2-23 fig. 2.2.15 example of peripheral circuit .................................................................................. 2-24 fig. 2.2.16 example of control procedure ................................................................................ 2-25 fig. 2.2.17 setting method for event counter mode (1) ......................................................... 2-26 fig. 2.2.18 setting method for event counter mode (2) ......................................................... 2-27 fig. 2.2.19 example of measurement method of frequency .................................................. 2-28 fig. 2.2.20 example of control procedure ................................................................................ 2-29 fig. 2.2.21 setting method for pulse width hl continuously measurement mode (1) ....... 2-30 fig. 2.2.22 setting method for pulse width hl continuously measurement mode (2) ....... 2-31 fig. 2.2.23 example of peripheral circuit .................................................................................. 2-32 fig. 2.2.24 operation timing when ringing pulse is input ...................................................... 2-32 fig. 2.2.25 example of control procedure (1) .......................................................................... 2-33 fig. 2.2.26 example of control procedure (2) .......................................................................... 2-34 list of figures
vi 7540 group user? manual list of figures fig. 2.3.1 memory map of registers relevant to timer 1 ........................................................ 2-36 fig. 2.3.2 structure of prescaler 1 ............................................................................................ 2-36 fig. 2.3.3 structure of timer 1 .................................................................................................. 2-37 fig. 2.3.4 structure of misrg ................................................................................................... 2-37 fig. 2.3.5 structure of interrupt request register 2 ................................................................. 2-38 fig. 2.3.6 structure of interrupt control register 2 .................................................................. 2-38 fig. 2.4.1 memory map of registers relevant to timer x ........................................................ 2-40 fig. 2.4.2 structure of port p0 direction register .................................................................... 2-41 fig. 2.4.3 structure of port p1 direction register .................................................................... 2-41 fig. 2.4.4 structure of timer x mode register ......................................................................... 2-42 fig. 2.4.5 structure of prescaler x ............................................................................................ 2-43 fig. 2.4.6 structure of timer x .................................................................................................. 2-43 fig. 2.4.7 structure of timer count source set register ......................................................... 2-44 fig. 2.4.8 structure of interrupt request register 1 ................................................................. 2-45 fig. 2.4.9 structure of interrupt control register 1 .................................................................. 2-45 fig. 2.4.10 setting method for timer mode .............................................................................. 2-47 fig. 2.4.11 connection of timer and setting of division ratio ................................................ 2-48 fig. 2.4.12 example of control procedure ................................................................................ 2-49 fig. 2.4.13 setting method for pulse output mode (1) ........................................................... 2-50 fig. 2.4.14 setting method for pulse output mode (2) ........................................................... 2-51 fig. 2.4.15 example of peripheral circuit .................................................................................. 2-52 fig. 2.4.16 connection of timer and setting of division ratio ................................................ 2-52 fig. 2.4.17 example of control procedure ................................................................................ 2-53 fig. 2.4.18 setting method for event counter mode (1) ......................................................... 2-54 fig. 2.4.19 setting method for event counter mode (2) ......................................................... 2-55 fig. 2.4.20 example of peripheral circuit .................................................................................. 2-56 fig. 2.4.21 method of measuring water flow rate ................................................................... 2-56 fig. 2.4.22 example of control procedure ................................................................................ 2-57 fig. 2.4.23 setting method for pulse width measurement mode (1) .................................... 2-58 fig. 2.4.24 setting method for pulse width measurement mode (2) .................................... 2-59 fig. 2.4.25 connection of timer and setting of division ratio ................................................ 2-60 fig. 2.4.26 example of control procedure ................................................................................ 2-61 fig. 2.5.1 memory map of registers relevant to timer y and timer z .................................. 2-63 fig. 2.5.2 structure of port p0 direction register .................................................................... 2-64 fig. 2.5.3 structure of port p3 direction register .................................................................... 2-64 fig. 2.5.4 structure of pull-up control register ........................................................................ 2-65 fig. 2.5.5 structure of port p1p3 control register .................................................................. 2-65 fig. 2.5.6 structure of timer y, z mode register .................................................................... 2-66 fig. 2.5.7 structure of prescaler y, prescaler z ..................................................................... 2-66 fig. 2.5.8 structure of timer y secondary, timer z secondary ........................................... 2-67 fig. 2.5.9 structure of timer y primary, timer z primary ..................................................... 2-67 fig. 2.5.10 structure of timer y, z waveform output control register ................................. 2-68 fig. 2.5.11 structure of one-shot start register ....................................................................... 2-68 fig. 2.5.12 structure of timer count source set register ....................................................... 2-69 fig. 2.5.13 structure of interrupt edge selection register ...................................................... 2-69 fig. 2.5.14 structure of cpu mode register ............................................................................ 2-70 fig. 2.5.15 structure of interrupt request register 1 ............................................................... 2-71 fig. 2.5.16 structure of interrupt request register 2 ............................................................... 2-71 fig. 2.5.17 structure of interrupt control register 1 ................................................................ 2-72 fig. 2.5.18 structure of interrupt control register 2 ................................................................ 2-72 fig. 2.5.19 setting method for timer mode .............................................................................. 2-74 fig. 2.5.20 example of peripheral circuit .................................................................................. 2-75
7540 group user? manual vii fig. 2.5.21 method of measuring water flow rate ................................................................... 2-75 fig. 2.5.22 example of control procedure ................................................................................ 2-76 fig. 2.5.23 timing diagram of programmable waveform generation mode ......................... 2-79 fig. 2.5.24 setting method for programmable waveform generation mode (1) .................. 2-80 fig. 2.5.25 setting method for programmable waveform generation mode (2) .................. 2-81 fig. 2.5.26 example of waveform output .................................................................................. 2-82 fig. 2.5.27 example of control procedure ................................................................................ 2-83 fig. 2.5.28 timing diagram of programmable one-shot generation mode ........................... 2-85 fig. 2.5.29 setting method for programmable one-shot generation mode (1) .................... 2-86 fig. 2.5.30 setting method for programmable one-shot generation mode (2) .................... 2-87 fig. 2.5.31 setting method for programmable one-shot generation mode (3) .................... 2-88 fig. 2.5.32 example of peripheral circuit .................................................................................. 2-89 fig. 2.5.33 example of operation timing ................................................................................... 2-89 fig. 2.5.34 example of control procedure ................................................................................ 2-90 fig. 2.5.35 timing diagram of programmable wait one-shot generation mode ................... 2-93 fig. 2.5.36 setting method for programmable wait one-shot generation mode (1) ............ 2-94 fig. 2.5.37 setting method for programmable wait one-shot generation mode (2) ............ 2-95 fig. 2.5.38 setting method for programmable wait one-shot generation mode (3) ............ 2-96 fig. 2.5.39 example of waveform generation and peripheral circuit .................................... 2-97 fig. 2.5.40 example of control procedure ................................................................................ 2-98 fig. 2.6.1 memory map of registers relevant to serial i/o ................................................... 2-101 fig. 2.6.2 structure of transmit/receive buffer register ...................................................... 2-101 fig. 2.6.3 structure of serial i/o1 status register ................................................................. 2-102 fig. 2.6.4 structure of serial i/o1 control register ................................................................ 2-102 fig. 2.6.5 structure of uart control register ........................................................................ 2-103 fig. 2.6.6 structure of baud rate generator ........................................................................... 2-103 fig. 2.6.7 structure of interrupt request register 1 ............................................................... 2-104 fig. 2.6.8 structure of interrupt control register 1 ................................................................ 2-104 fig. 2.6.9 serial i/o1 transfer data format ............................................................................. 2-105 fig. 2.6.10 setting method for clock synchronous serial i/o1 (1) ...................................... 2-107 fig. 2.6.11 setting method for clock synchronous serial i/o1 (2) ...................................... 2-108 fig. 2.6.12 connection diagram ............................................................................................... 2-109 fig. 2.6.13 timing chart ............................................................................................................ 2-109 fig. 2.6.14 control procedure of transmitter .......................................................................... 2-110 fig. 2.6.15 control procedure of receiver ............................................................................... 2-111 fig. 2.6.16 setting method for uart of serial i/o1 (1) ....................................................... 2-113 fig. 2.6.17 setting method for uart of serial i/o1 (2) ....................................................... 2-114 fig. 2.6.18 connection diagram ............................................................................................... 2-115 fig. 2.6.19 timing chart ............................................................................................................ 2-115 fig. 2.6.20 control procedure of transmitter .......................................................................... 2-116 fig. 2.6.21 control procedure of receiver ............................................................................... 2-117 fig. 2.6.22 sequence of setting serial i/o1 control register again ..................................... 2-119 fig. 2.7.1 memory map of registers relevant to serial i/o2 ................................................ 2-120 fig. 2.7.2 structure of port p1 direction register .................................................................. 2-120 fig. 2.7.3 structure of serial i/o2 control register ................................................................ 2-121 fig. 2.7.4 structure of serial i/o2 register ............................................................................. 2-121 fig. 2.7.5 structure of interrupt request register 2 ............................................................... 2-122 fig. 2.7.6 structure of interrupt control register 2 ................................................................ 2-122 fig. 2.7.7 setting method for serial i/o2 ................................................................................ 2-123 fig. 2.7.8 setting method for serial i/o2 ................................................................................ 2-124 fig. 2.7.9 connection diagram ................................................................................................. 2-125 fig. 2.7.10 timing chart ............................................................................................................ 2-125 list of figures
viii 7540 group user? manual fig. 2.7.11 control procedure of transmission side .............................................................. 2-126 fig. 2.7.12 control procedure of reception side .................................................................... 2-127 fig. 2.8.1 memory map of registers relevant to a-d converter .......................................... 2-129 fig. 2.8.2 structure of a-d control register ............................................................................ 2-129 fig. 2.8.3 structure of a-d conversion register (low-order) ................................................. 2-130 fig. 2.8.4 structure of a-d conversion register (high-order) ............................................... 2-130 fig. 2.8.5 structure of interrupt request register 2 ............................................................... 2-131 fig. 2.8.6 structure of interrupt control register 2 ................................................................ 2-131 fig. 2.8.7 relevant registers setting ....................................................................................... 2-132 fig. 2.8.8 connection diagram ................................................................................................. 2-133 fig. 2.8.9 control procedure ..................................................................................................... 2-133 fig. 2.8.10 connection diagram ............................................................................................... 2-134 fig. 2.9.1 memory map of registers relevant to oscillation control .................................... 2-135 fig. 2.9.2 structure of misrg ................................................................................................. 2-135 fig. 2.9.3 structure of watchdog timer control register ....................................................... 2-136 fig. 2.9.4 structure of cpu mode register ............................................................................ 2-136 fig. 2.9.5 setting method when the ring oscillator is used as the operation clock ......... 2-137 fig. 2.9.6 control procedure ..................................................................................................... 2-138 fig. 2.9.7 initial setting method for the oscillation stop detection circuit .......................... 2-140 fig. 2.9.8 setting method for the oscillation stop detection circuit in main processing .. 2-141 fig. 2.9.9 state transition .......................................................................................................... 2-142 fig. 2.9.10 example of mode transition .................................................................................. 2-143 fig. 2.9.11 control procedure ................................................................................................... 2-144 chapter 3 appendix fig. 3.1.1 switching characteristics measurement circuit diagram (general purpose) ....... 3-11 fig. 3.1.2 timing chart (general purpose) ............................................................................... 3-12 fig. 3.1.3 switching characteristics measurement circuit diagram (extended operating temperature) 3-20 fig. 3.1.4 timing chart (extended operating temperature version) ...................................... 3-21 fig. 3.1.5 switching characteristics measurement circuit diagram (extended operating temperature 125 ? version) ..................................................................................................................... 3-29 fig. 3.1.6 timing chart (extended operating temperature 125 ? version) ......................... 3-30 fig. 3.2.1 v cc -i cc characteristics (in double-speed mode: mask rom version) .................. 3-31 fig. 3.2.2 v cc -i cc characteristics (in high-speed mode: mask rom version) ...................... 3-31 fig. 3.2.3 v cc -i cc characteristics (in middle-speed mode: mask rom version) .................. 3-31 fig. 3.2.4 v cc -i cc characteristics (at wit instruction execution: mask rom version) ........ 3-32 fig. 3.2.5 v cc -i cc characteristics (at stp instruction execution: mask rom version) ....... 3-32 fig. 3.2.6 v cc -i cc characteristics (addition when operating a-d conversion, f(x in ) = 8 mhz in high-speed mode: mask rom version) .............................................................................. 3-33 fig. 3.2.7 v cc -i cc characteristics (addition when operating a-d conversion, f(x in ) = 6 mhz in double-speed mode: mask rom version) ......................................................................... 3-33 fig. 3.2.8v cc -i cc characteristics (when system is operating by ring oscillator, ceramic oscillation stop: mask rom version) .................................................................................................... 3-34 fig. 3.2.9 v cc -i cc characteristics (when system is operating by ring oscillator, at wit instruction execution, ceramic oscillation stop: mask rom version) ............................................... 3-34 fig. 3.2.10 f(x in )-i cc characteristics (in double-speed mode: mask rom version) ............. 3-35 fig. 3.2.11 f(x in )-i cc characteristics (in high-speed mode: mask rom version) ................. 3-35 fig. 3.2.12 f(x in )-i cc characteristics (in middle-speed mode: mask rom version) ............. 3-35 fig. 3.2.13 f(x in )-i cc characteristics (at wit instruction execution: mask rom version) ... 3-36 fig. 3.2.14 ta-i cc characteristics (when system is operating by ring oscillator, ceramic oscillation stop: mask rom version) .................................................................................................... 3-36 fig. 3.2.15 ta-i cc characteristics (when system is operating by ring oscillator, at wit instruction execution, ceramic oscillation stop: mask rom version) ............................................... 3-36 list of figures
7540 group user? manual ix list of figures fig. 3.2.16 v cc -v ihl characteristics (i/o port (cmos): mask rom version) ........................ 3-37 fig. 3.2.17 v cc -v ihl characteristics (i/o port (ttl): mask rom version) ............................ 3-37 fig. 3.2.18 v cc -v ihl characteristics (reset pin: mask rom version) ................................. 3-38 fig. 3.2.19 v cc -v ihl characteristics (x in pin: mask rom version) ......................................... 3-38 fig. 3.2.20 v cc -v il characteristics (cnv ss pin: mask rom version) ..................................... 3-38 fig. 3.2.21 v cc -hys characteristics (reset pin: mask rom version) ................................ 3-39 fig. 3.2.22 v cc -hys characteristics (sio pin: mask rom version) ...................................... 3-39 fig. 3.2.23 v cc -hys characteristics (int pin: mask rom version) ...................................... 3-39 fig. 3.2.24 v oh -i oh characteristics of p-channel (v cc = 3.0 v, normal port: mask rom version) .. 3-40 fig. 3.2.25 v oh -i oh characteristics of p-channel (v cc = 5.0 v, normal port: mask rom version) .. 3-40 fig. 3.2.26 v ol -i ol characteristics of n-channel (v cc = 3.0 v, normal port: mask rom version) ... 3-41 fig. 3.2.27 v ol -i ol characteristics of n-channel (v cc = 5.0 v, normal port: mask rom version) ... 3-41 fig. 3.2.28 v ol -i ol characteristics of n-channel (v cc = 3.0 v, led drive port: mask rom version) ............................................................................................................................... .................. 3-42 fig. 3.2.29 v ol -i ol characteristics of n-channel (v cc = 5.0 v, led drive port: mask rom version) ............................................................................................................................... .................. 3-42 fig. 3.2.30 v cc -iil characteristics (port ??input current when connecting pull-up transistor: mask rom version) .............................................................................................................. 3-43 fig. 3.2.31 v in -ii(ad) characteristics (a-d port input current during a-d conversion, f(x in ) = 8 mhz in high-speed mode: mask rom version) ................................................................ 3-44 fig. 3.2.32 v in -ii(ad) characteristics (a-d port input current during a-d conversion, f(x in ) = 6 mhz in double-speed mode: mask rom version) ............................................................ 3-44 fig. 3.2.33 v in -ii(ad) characteristics (a-d port input current during a-d conversion, f(x in ) = 4 mhz in double-speed mode: mask rom version) ............................................................ 3-44 fig. 3.2.34 v cc -r osc characteristics (ring oscillator frequency: mask rom version) .......... 3-45 fig. 3.2.35 ta-r osc characteristics (ring oscillator frequency: mask rom version) ........... 3-45 fig. 3.2.36 r-f(x in ) characteristics (rc oscillation frequency: mask rom version) ........... 3-46 fig. 3.2.37 c-f(x in ) characteristics (rc oscillation frequency: mask rom version) ........... 3-46 fig. 3.2.38 v cc -f(x in ) characteristics (rc oscillation frequency: mask rom version) ........ 3-47 fig. 3.2.39 ta-f(x in ) characteristics (rc oscillation frequency: mask rom version) ......... 3-47 fig. 3.2.40 definition of a-d conversion a cc uracy ................................................................... 3-48 fig. 3.2.41 a-d conversion accuracy typical characteristic example-1 (mask rom version) .. 3-49 fig. 3.2.42 a-d conversion accuracy typical characteristic example-2 (mask rom version) .. 3-50 fig. 3.2.43 a-d conversion a cc uracy typical characteristic example-3 (mask rom version) .. 3-51 fig. 3.2.44 v cc -i cc characteristics (in double-speed mode: one time prom version) ..... 3-52 fig. 3.2.45 v cc -i cc characteristics (in high-speed mode: one time prom version) ......... 3-52 fig. 3.2.46 v cc -i cc characteristics (in middle-speed mode: one time prom version) ..... 3-52 fig. 3.2.47 v cc -i cc characteristics (at wit instruction execution: one time prom version) .. 3-53 fig. 3.2.48 v cc -i cc characteristics (at stp instruction execution: one time prom version) .. 3-53 fig. 3.2.49 v cc -i cc characteristics (addition when operating a-d conversion, f(x in ) = 8 mhz in high-speed mode: one time prom version) ................................................................... 3-54 fig. 3.2.50 v cc -i cc characteristics (addition when operating a-d conversion, f(x in ) = 6 mhz in double-speed mode: one time prom version) ............................................................... 3-54 fig. 3.2.51 v cc -i cc characteristics (when system is operating by ring oscillator, ceramic oscillation stop: one time prom version) .......................................................................................... 3-55 fig. 3.2.52 v cc -i cc characteristics (when system is operating by ring oscillator, at wit instruction execution, ceramic oscillation stop: one time prom version) .................................... 3-55 fig. 3.2.53 f(x in )-i cc characteristics (in double-speed mode: one time prom version) .. 3-56 fig. 3.2.54 f(x in )-i cc characteristics (in high-speed mode: one time prom version) ...... 3-56 fig. 3.2.55 f(x in )-i cc characteristics (in middle-speed mode: one time prom version) .. 3-56 fig. 3.2.56 f(x in )-i cc characteristics (at wit instruction execution: one time prom version) ... 3-57 fig. 3.2.57 ta-i cc characteristics (when system is operating by ring oscillator, ceramic oscillation stop: one time prom version) .......................................................................................... 3-57
x 7540 group user? manual list of figures fig. 3.2.58 ta-i cc characteristics (when system is operating by ring oscillator, at wit instruction execution, ceramic oscillation stop: one time prom version) .................................... 3-57 fig. 3.2.59 v cc -v ihl characteristics (i/o port (cmos): one time prom version) ............. 3-58 fig. 3.2.60 v cc -v ihl characteristics (i/o port (ttl): one time prom version) .................. 3-58 fig. 3.2.61 v cc -v ihl characteristics (reset pin: one time prom version) ....................... 3-59 fig. 3.2.62 v cc -v ihl characteristics (x in pin: one time prom version) ............................... 3-59 fig. 3.2.63 v cc -v il characteristics (cnv ss pin: one time prom version) .......................... 3-59 fig. 3.2.64 v cc -hys characteristics (reset pin: one time prom version) ..................... 3-60 fig. 3.2.65 v cc -hys characteristics (sio pin: one time prom version) ........................... 3-60 fig. 3.2.66 v cc -hys characteristics (int pin: one time prom version) ........................... 3-60 fig. 3.2.67 v oh -i oh characteristics of p-channel (v cc = 3.0 v, normal port: one time prom version) ............................................................................................................................... .... 3-61 fig. 3.2.68 v oh -i oh characteristics of p-channel (v cc = 5.0 v, normal port: one time prom version) ............................................................................................................................... .... 3-61 fig. 3.2.69 v ol -i ol characteristics of n-channel (v cc = 3.0 v, normal port: one time prom version) ............................................................................................................................... .... 3-62 fig. 3.2.70 v ol -i ol characteristics of n-channel (v cc = 5.0 v, normal port: one time prom version) ............................................................................................................................... .... 3-62 fig. 3.2.71 v ol -i ol characteristics of n-channel (v cc = 3.0 v, led drive port: one time prom version) ............................................................................................................................... .... 3-63 fig. 3.2.72 v ol -i ol characteristics of n-channel (v cc = 5.0 v, led drive port: one time prom version) ............................................................................................................................... .... 3-63 fig. 3.2.73 v cc -iil characteristics (port ??input current when connecting pull-up transistor: one time prom version) .................................................................................................... 3-64 fig. 3.2.74 v in -ii(ad) characteristics (a-d port input current during a-d conversion, f(x in ) = 8 mhz in high-speed mode: one time prom version) ..................................................... 3-65 fig. 3.2.75 v in -ii(ad) characteristics (a-d port input current during a-d conversion, f(x in ) = 6 mhz in double-speed mode: one time prom version) ................................................. 3-65 fig. 3.2.76 v in -ii(ad) characteristics (a-d port input current during a-d conversion, f(x in ) = 4 mhz in double-speed mode: one time prom version) ................................................. 3-65 fig. 3.2.77 v cc -r osc characteristics (ring oscillator frequency: one time prom version) 3-66 fig. 3.2.78 ta-r osc characteristics (ring oscillator frequency: one time prom version) 3-66 fig. 3.2.79 r-f(x in ) characteristics (rc oscillation frequency: one time prom version) 3-67 fig. 3.2.80 c-f(x in ) characteristics (rc oscillation frequency: one time prom version) 3-67 fig. 3.2.81 v cc -f(x in ) characteristics (rc oscillation frequency: one time prom version) ... 3-68 fig. 3.2.82 ta-f(x in ) characteristics (rc oscillation frequency: one time prom version)3-68 fig. 3.2.83 definition of a-d conversion accuracy .................................................................. 3-69 fig. 3.2.84 a-d conversion accuracy typical characteristic example-1 (one time prom version) .. 3-70 fig. 3.2.85 a-d conversion accuracy typical characteristic example-2 (one time prom version) .. 3-71 fig. 3.2.86 a-d conversion accuracy typical characteristic example-3 (one time prom version) .. 3-72 fig. 3.3.1 sequence of setting serial i/o1 control register again ......................................... 3-80 fig. 3.3.2 connection diagram ................................................................................................... 3-82 fig. 3.3.3 state transition ............................................................................................................ 3-84 fig. 3.3.4 switching method of cpu mode register ............................................................... 3-85 fig. 3.3.5 sequence of switch the detection edge .................................................................. 3-86 fig. 3.3.6 sequence of check of interrupt request bit ............................................................ 3-86 fig. 3.3.7 structure of interrupt control register 2 .................................................................. 3-87 fig. 3.3.8 initialization of processor status register ................................................................ 3-88 fig. 3.3.9 sequence of plp instruction execution .................................................................. 3-88 fig. 3.3.10 stack memory contents after php instruction execution ................................... 3-88 fig. 3.3.11 status flag at decimal calculations ........................................................................ 3-89 fig. 3.3.12 programming and testing of one time prom version ...................................... 3-90
7540 group user? manual xi fig. 3.4.1 selection of packages ............................................................................................... 3-92 fig. 3.4.2 wiring for the reset pin ......................................................................................... 3-92 fig. 3.4.3 wiring for clock i/o pins ........................................................................................... 3-93 fig. 3.4.4 wiring for cnv ss pin ................................................................................................ 3-93 fig. 3.4.5 wiring for the v pp pin of the one time prom ..................................................... 3-94 fig. 3.4.6 bypass capacitor across the v ss line and the v cc line ........................................ 3-94 fig. 3.4.7 analog signal line and a resistor and a capacitor ................................................ 3-95 fig. 3.4.8 wiring for a large current signal line ...................................................................... 3-95 fig. 3.4.9 wiring of signal lines where potential levels change frequently ......................... 3-96 fig. 3.4.10 v ss pattern on the underside of an oscillator ...................................................... 3-96 fig. 3.4.11 setup for i/o ports ................................................................................................... 3-96 fig. 3.4.12 watchdog timer by software ................................................................................... 3-97 fig. 3.5.1 structure of port pi (i = 0, 2, 3) .............................................................................. 3-98 fig. 3.5.2 structure of port p1 ................................................................................................... 3-98 fig. 3.5.3 structure of port pi direction register (i = 0, 2, 3) ............................................... 3-99 fig. 3.5.4 structure of port p1 direction register .................................................................... 3-99 fig. 3.5.5 structure of pull-up control register ...................................................................... 3-100 fig. 3.5.6 structure of port p1p3 control register ................................................................ 3-100 fig. 3.5.7 structure of transmit/receive buffer register ...................................................... 3-101 fig. 3.5.8 structure of serial i/o1 status register ................................................................. 3-101 fig. 3.5.9 structure of serial i/o1 control register ................................................................ 3-102 fig. 3.5.10 structure of uart control register ...................................................................... 3-102 fig. 3.5.11 structure of baud rate generator ......................................................................... 3-103 fig. 3.5.12 structure of timer a mode register .................................................................... 3-104 fig. 3.5.13 structure of timer a register ............................................................................... 3-105 fig. 3.5.14 structure of timer y, z mode register ............................................................... 3-105 fig. 3.5.15 structure of prescaler y, prescaler z ................................................................. 3-106 fig. 3.5.16 structure of timer y secondary, timer z secondary ....................................... 3-106 fig. 3.5.17 structure of timer y primary, timer z primary ................................................. 3-107 fig. 3.5.18 structure of timer y, z waveform output control register ............................... 3-107 fig. 3.5.19 structure of prescaler 1 ........................................................................................ 3-108 fig. 3.5.20 structure of timer 1 .............................................................................................. 3-108 fig. 3.5.21 structure of one-shot start register ..................................................................... 3-109 fig. 3.5.22 structure of timer x mode register .................................................................... 3-110 fig. 3.5.23 structure of prescaler x ....................................................................................... 3-111 fig. 3.5.24 structure of timer x .............................................................................................. 3-111 fig. 3.5.25 structure of timer count source set register ..................................................... 3-112 fig. 3.5.26 structure of serial i/o2 control register .............................................................. 3-113 fig. 3.5.27 structure of serial i/o2 register ........................................................................... 3-113 fig. 3.5.28 structure of a-d control register .......................................................................... 3-114 fig. 3.5.29 structure of a-d conversion register (low-order) ............................................... 3-114 fig. 3.5.30 structure of a-d conversion register (high-order) ............................................. 3-115 fig. 3.5.31 structure of misrg ............................................................................................... 3-115 fig. 3.5.32 structure of watchdog timer control register ..................................................... 3-116 fig. 3.5.33 structure of interrupt edge selection register .................................................... 3-116 fig. 3.5.34 structure of cpu mode register .......................................................................... 3-117 fig. 3.5.35 structure of interrupt request register 1 ............................................................. 3-118 fig. 3.5.36 structure of interrupt request register 2 ............................................................. 3-118 fig. 3.5.37 structure of interrupt control register 1 .............................................................. 3-119 fig. 3.5.38 structure of interrupt control register 2 .............................................................. 3-119 list of figures
xii 7540 group user? manual list of figures fig. 3.10.1 32p6u-a package pin configuration .................................................................... 3-135 fig. 3.10.2 36p2r-a package pin configuration .................................................................... 3-136 fig. 3.10.3 32p4b package pin configuration ........................................................................ 3-137 fig. 3.10.4 42s1m package pin configuration ........................................................................ 3-138 fig. 3.11.1 memory map of 7540 group and 7531 group .................................................. 3-140 fig. 3.11.2 memory map of interrupt vector area of 7540 group and 7531 group ........ 3-141 fig. 3.11.3 timer function of 7540 group and 7531 group ................................................ 3-142
7540 group user? manual xiii list of tables chapter 1 hardware table 1 pin description ................................................................................................................. 1-8 table 2 list of supported products ........................................................................................... 1-10 table 3 push and pop instructions of accumulator or processor status register ............... 1-12 table 4 set and clear instructions of each bit of processor status register ....................... 1-13 table 5 i/o port function table ................................................................................................... 1-18 table 6 interrupt vector address and priority .......................................................................... 1-21 table 7 special programming adapter ...................................................................................... 1-53 table 8 interrupt sources, vector addresses and interrupt priority ....................................... 1-54 table 9 change of a-d conversion register during a-d conversion .................................... 1-56 chapter 2 application table 2.1.1 handling of unused pins ........................................................................................ 2-10 table 2.2.1 cntr1 active edge switch bit function ................................................................ 2-15 table 2.4.1 cntr0 active edge switch bit function ................................................................ 2-42 table 2.6.1 setting example of baud rate generator (brg) and transfer bit rate values .. 2-112 chapter 3 appendix table 3.1.1 absolute maximum ratings ....................................................................................... 3-2 table 3.1.2 recommended operating conditions (1) ................................................................ 3-3 table 3.1.3 recommended operating conditions (2) ................................................................ 3-4 table 3.1.4 electrical characteristics (1) ..................................................................................... 3-5 table 3.1.5 electrical characteristics (2) ..................................................................................... 3-6 table 3.1.6 a-d converter characteristics .................................................................................. 3-7 table 3.1.7 timing requirements (1) ........................................................................................... 3-8 table 3.1.8 timing requirements (2) ........................................................................................... 3-8 table 3.1.9 timing requirements (3) ........................................................................................... 3-9 table 3.1.10 switching characteristics (1) ................................................................................ 3-10 table 3.1.11 switching characteristics (2) ................................................................................ 3-10 table 3.1.12 switching characteristics (3) ................................................................................ 3-11 table 3.1.13 absolute maximum ratings ................................................................................... 3-13 table 3.1.14 recommended operating conditions (1) ............................................................ 3-14 table 3.1.15 recommended operating conditions (2) ............................................................ 3-15 table 3.1.16 electrical characteristics (1) ................................................................................ 3-16 table 3.1.17 electrical characteristics (2) ................................................................................ 3-17 table 3.1.18 a-d converter characteristics .............................................................................. 3-18 table 3.1.19 timing requirements (1) ....................................................................................... 3-19 table 3.1.20 timing requirements (2) ....................................................................................... 3-19 table 3.1.21 switching characteristics (1) ................................................................................ 3-20 table 3.1.22 switching characteristics (2) ................................................................................ 3-20 table 3.1.23 absolute maximum ratings ................................................................................... 3-22 table 3.1.24 recommended operating conditions (1) ............................................................ 3-23 table 3.1.25 recommended operating conditions (2) ............................................................ 3-24 table 3.1.26 electrical characteristics (1) ................................................................................ 3-25 table 3.1.27 electrical characteristics (2) ................................................................................ 3-26 list of tables
xiv 7540 group user? manual table 3.1.28 a-d converter characteristics .............................................................................. 3-27 table 3.1.29 timing requirements (1) ....................................................................................... 3-28 table 3.1.30 timing requirements (2) ....................................................................................... 3-28 table 3.1.31 switching characteristics (1) ................................................................................ 3-29 table 3.1.32 switching characteristics (2) ................................................................................ 3-29 table 3.3.1 programming adapters ........................................................................................... 3-91 table 3.3.2 prom programmer address setting ..................................................................... 3-91 table 3.5.1 cntr1 active edge switch bit function .............................................................. 3-104 table 3.5.2 cntr0 active edge switch bit function .............................................................. 3-110 table 3.11.1 differences between 7540 group and 7531 group ....................................... 3-139
chapter 1 hardware description features application pin configuration functional block pin description group expansion functional description notes on programming notes on use data required for mask orders rom programming method functional description supplement
hardware 1-2 7540 group user? manual description the 7540 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 7540 group has a serial i/o, 8-bit timers, a 16-bit timer, and an a-d converter, and is useful for control of home electric appli- ances and office automation equipment. features basic machine-language instructions ...................................... 71 the minimum instruction execution time ......................... 0.34 s (at 6 mhz oscillation frequency, double-speed mode for the shortest instruction) memory size rom ............................................ 8 k to 32 k bytes ram ............................................. 384 to 768 bytes programmable i/o ports ....................... 29 (25 in 32-pin version) interrupts ................................................. 15 sources, 15 vectors ................................. (14 sources, 14 vectors for 32-pin version) timers ............................................................................. 8-bit ? 4 ...................................................................................... 16-bit ? 1 serial i/o1 ................... 8-bit ? 1 (uart or clock-synchronized) serial i/o2 ( note 1 ) ..................... 8-bit ? 1 (clock-synchronized) a-d converter ............................................... 10-bit ? 8 channels .................................................... (6 channels for 32-pin version) clock generating circuit ............................................. built-in type (low-power dissipation by a ring oscillator enabled) (connect to external ceramic resonator or quartz-crystal oscilla- tor permitting rc oscillation) watchdog timer ............................................................ 16-bit ? 1 power source voltage x in oscillation frequency at ceramic oscillation, in double-speed mode at 6 mhz .................................................................... 4.5 to 5.5 v x in oscillation frequency at ceramic oscillation, in high-speed mode at 8 mhz .................................................................... 4.0 to 5.5 v at 4 mhz .................................................................... 2.4 to 5.5 v at 2 mhz .................................................................... 2.2 to 5.5 v x in oscillation frequency at rc oscillation in high-speed mode or middle-speed mode at 4 mhz .................................................................... 4.0 to 5.5 v at 2 mhz .................................................................... 2.4 to 5.5 v at 1 mhz .................................................................... 2.2 to 5.5 v power dissipation mask rom version ....................................... 22.5 mw (standard) one time prom version ................................ 30 mw (standard) operating temperature range ................................... ?0 to 85 ? (?0 to 85 ? for extended operating temperature version) (?0 to 125 ? for extended operating temperature 125 ? ver- sion ( note 2 )) application office automation equipment, factory automation equipment, home electric appliances, consumer electronics, car, etc. notes 1: serial i/o2 can be used in the following cases; (1) serial i/o1 is not used, (2) serial i/o1 is used as uart and brg output divided by 16 is selected as the synchronized clock. 2: in this version, the operating temperature range and total time are limited as follows; 55 ? to 85 ?: within total 6000 hours, 85 ? to 125 ?: within total 1000 hours. description/features/application
hardware 7540 group user? manual 1-3 fig. 2 pin configuration (36p2r-a type) packa g e t yp e: 36p2r-a 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 21 20 19 32 27 29 28 p0 0 /cntr 1 cnv ss x out x in v ss p0 1 /ty out p0 2 /tz out p0 3 /tx out p0 4 p3 0 (led 0 ) vcc v ref p0 5 p1 0 /r x d 1 p2 6 /an 6 p2 7 /an 7 p1 1 /t x d 1 p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p2 3 /an 3 p2 2 /an 2 p2 1 /an 1 p2 0 /an 0 p3 1 (led 1 ) p3 6 (led 6 )/int 1 p2 4 /an 4 p2 5 /an 5 p0 6 p0 7 p3 7 /int 0 reset m37540mx-xxxfp m37540mxt-xxxfp m37540mxv-xxxfp m37540e8fp m37540e8t-xxxfp m37540e8v-xxxfp p1 4 /cntr 0 p3 5 (led 5 ) p3 4 (led 4 ) p3 3 (led 3 ) p3 2 (led 2 ) pin configuration (top view) fig. 1 pin configuration (32p6u-a type) package type: 32p6u-a p0 7 p1 0 /r x d 1 p1 1 /t x d 1 p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 / an 0 p2 1 / an 1 32 31 30 29 28 27 26 25 p3 4 (led 4 ) p3 3 (led 3 ) p3 2 (led 2 ) p3 1 (led 1 ) p3 0 (led 0 ) v ss x out x in 9 10 11 12 13 14 15 16 2 8 7 6 5 3 1 4 v cc cnv ss reset p2 2 /an 2 p0 5 20 17 18 19 21 24 p0 2 /tz out p0 4 p0 3 /tx out p0 6 23 22 p0 1 /ty out p0 0 /cntr 1 p3 7 /int 0 m37540mx-xxxgp m37540mxt-xxxgp m37540mxv-xxxgp m37540exgp m37540e8t-xxxgp m37540e8v-xxxgp p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 v ref pin configuration
hardware 1-4 7540 group user s manual fig. 4 pin configuration (42s1m type) outline 42s1m 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 32 27 29 28 19 20 21 42 41 40 39 37 38 p0 0 /cntr 1 cnv ss x out x in v ss p0 1 /ty out p0 2 /tz out p0 3 /tx out p0 4 p3 0 (led 0 ) vcc v ref p0 5 p1 2 /s clk1 /s clk2 p2 5 /an 5 p2 6 /an 6 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 nc p2 2 /an 2 nc p2 1 /an 1 p2 0 /an 0 p3 1 (led 1 ) p3 6 (led 6 )/int 1 p2 3 /an 3 p2 4 /an 4 p0 6 p0 7 p3 7 /int 0 reset m37540rss nc p3 5 (led 5 ) p3 4 (led 4 ) p3 3 (led 3 ) p3 2 (led 2 ) nc p1 0 /r x d 1 p1 1 /t x d 1 nc nc p2 7 /an 7 fig. 3 pin configuration (32p4b-a type) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cnv ss p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 v cc x in x out v ss p1 1 /t x d 1 p1 0 /r x d 1 p0 7 p0 6 p0 5 p0 4 p3 0 (led 0 ) p2 5 /an 5 v ref reset p0 0 /cntr 1 p3 3 (led 3 ) p3 2 (led 2 ) p3 1 (led 1 ) m37540mx-xxxsp m37540exsp 32 p0 1 /ty out p0 2 /tz out p0 3 /tx out 14 15 16 p3 7 /int 0 p3 4 (led 4 ) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 package type: 32p4b pin configuration
hardware 7540 group user s manual 1-5 functional block fig. 5 functional block diagram (32p6u package) functional block diagram (package: 32p6u) x in out x si/o1(8) ram rom cpu a x y s pc h pc l ps v ss 11 reset 6 v cc 8 7 cnv ss p1(5) 30 28 26 29 27 32 31 p2(6) p3(6) 12 15 13 5 reset input i/o port p2 i/o port p1 i/o port p3 clock generating circuit clock input clock output 9 10 4 2 3 1 a-d converter (10) v ref watchdog timer reset 0 14 int 0 16 17 si/o2(8) cntr 0 i/o port p0 prescaler y (8) prescaler z (8) timer x (8) timer z (8) timer y (8) key-on wakeup ty out tz out prescaler x (8) cntr 1 timer a (16) p0(8) 25 23 21 19 24 22 20 18 int 0 timer 1 (8) prescaler 1 (8) tx out functional block
hardware 1-6 7540 group user s manual fig. 6 functional block diagram (36p2r package) functional block diagram (package: 36p2r) a-d converter (10) x in out x cpu v ss 18 reset 13 v cc 15 14 cnv ss p0(8) 34 32 30 28 33 31 29 27 p1(5) 31 35 2 36 7 5 6 4 p2(8) p3(8) 20 23 21 19 12 i/o port p2 i/o port p0 i/o port p1 i/o port p3 16 17 11 9 10 8 0 22 26 24 25 si/o1(8) ram rom a x y s pc h pc l ps reset input clock generating circuit clock input clock output v ref watchdog timer reset int 0 si/o2(8) cntr 0 prescaler y (8) prescaler z (8) timer x (8) timer z (8) timer y (8) key-on wakeup ty out tz out prescaler x (8) cntr 1 timer a (16) int 0 timer 1 (8) prescaler 1 (8) tx out int 1 functional block
hardware 7540 group user s manual 1-7 fig. 7 functional block diagram (32p4b package) functional block diagram (package: 32p4b) 16 11 13 12 p1(5) 31 31 2 32 5 4 p2(6) p3(6) 17 20 18 10 14 15 9 7 8 6 0 19 21 22 p0(8) 30 28 26 24 29 27 25 23 a-d converter (10) x in out x cpu v ss reset v cc cnv ss i/o port p2 i/o port p0 i/o port p1 i/o port p3 si/o1(8) ram rom a x y s pc h pc l ps reset input clock generating circuit clock input clock output v ref watchdog timer reset int 0 si/o2(8) cntr 0 prescaler y (8) prescaler z (8) timer x (8) timer z (8) timer y (8) key-on wakeup ty out tz out prescaler x (8) cntr 1 timer a (16) int 0 timer 1 (8) prescaler 1 (8) tx out functional block
hardware 1-8 7540 group user s manual pin description table 1 pin description function apply voltage of 2.2 to 5.5 v to vcc, and 0 v to vss. reference voltage input pin for a-d converter chip operating mode control pin, which is always connected to vss. reset input pin for active l input and output pins for main clock generating circuit connect a ceramic resonator or quartz crystal oscillator between the x in and x out pins. for using rc oscillator, short between the x in and x out pins, and connect the capacitor and resistor. if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. when the ring oscillator is selected as the main clock, connect x in pin to v ss and leave x out open. function expect a port function name power source (note 1) analog reference voltage cnvss reset input clock input i/o port p0 i/o port p1 pin vcc, vss v ref cnvss reset x in p0 0 /cntr 1 p0 1 /ty out p0 2 /tz out p0 3 /tx out p0 4 p0 7 notes 1: v cc = 2.4 to 5.5 v for the extended operating temperature version and the extended operating temperature 125 c version. 2: p2 6 /an 6 and p2 7 /an 7 do not exist for the 32-pin version, so that port p2 is a 6-bit i/o port. 3: p3 5 and p3 6 /int 1 do not exist for the 32-pin version, so that port p3 is a 6-bit i/o port. key-input (key-on wake up interrupt input) pins timer y, timer z, timer x and timer a function pin 8-bit i/o port. i/o direction register allows each pin to be individually pro- grammed as either input or output. cmos compatible input level cmos 3-state output structure whether a built-in pull-up resistor is to be used or not can be de- termined by program. 5-bit i/o port i/o direction register allows each pin to be individually pro- grammed as either input or output. cmos compatible input level cmos 3-state output structure cmos/ttl level can be switched for p1 0 , p1 2 and p1 3 8-bit i/o port having almost the same function as p0 cmos compatible input level cmos 3-state output structure 8-bit i/o port p1 0 /rxd 1 p1 1 /txd 1 p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 /an 0 p2 7 /an 7 p3 0 p3 5 p3 6 /int 1 p3 7 /int 0 i/o port p2 (note 2) i/o port p3 (note 3) serial i/o1 function pin serial i/o1 function pin serial i/o2 function pin timer x function pin input pins for a-d converter interrupt input pins i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level (cmos/ttl level can be switched for p3 6 and p3 7 ). cmos 3-state output structure p3 0 to p3 6 can output a large current for driving led. x out clock output whether a built-in pull-up resistor is to be used or not can be de- termined by program. pin description
hardware 7540 group user? manual 1-9 group expansion we plan to expand the 7540 group as follow: memory type support for mask rom version, one time prom version, and emulator mcu . memory size rom/prom size ................................................. 8 k to 32 k bytes ram size .............................................................. 384 to 768 bytes package 32p4b .................................................. 32-pin plastic molded sdip 32p6u-a ...................... 0.8 mm-pitch 32-pin plastic molded lqfp 36p2r-a ...................... 0.8 mm-pitch 36-pin plastic molded ssop 42s1m .................................... 42-pin shrink ceramic piggy back fig. 8 memory expansion plan 3 8 4 3 2 k r o m s i z e ( b y t e s ) r a m s i z e ( b y t e s ) 5 1 27 6 8 16 k 0 u n d e r d e v e l o p m e n t m 3 7 5 4 0 e 8 m37540m4 m37540m4t n o t e : p r o d u c t s u n d e r d e v e l o p m e n t t h e d e v e l o p m e n t s c h e d u l e a n d s p e c i f i c a t i o n m a y b e r e v i s e d w i t h o u t n o t i c e . 8k m 3 7 5 4 0 e 8 t m 3 7 5 4 0 e 8 v u n d e r d e v e l o p m e n t m 3 7 5 4 0 m 2 t m 3 7 5 4 0 m 2 m37540e2 u n d e r d e v e l o p m e n t m37540m2v m37540m4v group expansion
hardware 1-10 7540 group user s manual currently supported products are listed below. table 2 list of supported products part number (p) rom size (bytes) rom size for user () 8192 (8062) 16384 (16254) 8192 (8062) 32768 (32638) ram size (bytes) 384 512 384 768 768 package 32p4b 36p2r-a 32p6u-a 32p4b 36p2r-a 32p6u-a 32p4b 36p2r-a 32p6u-a 32p4b 36p2r-a 32p6u-a 42s1m remarks mask rom version mask rom version mask rom version (extended operating temperature version) mask rom version (extended operating temperature 125 c version) mask rom version mask rom version (extended operating temperature version) mask rom version (extended operating temperature 125 c version) mask rom version mask rom version mask rom version (extended operating temperature version) mask rom version (extended operating temperature 125 c version) mask rom version mask rom version (extended operating temperature version) mask rom version (extended operating temperature 125 c version) one time prom version (blank) one time prom version (blank) one time prom version (blank) one time prom version (blank) one time prom version (blank) one time prom version (shipped after programming, extended operating temperature version) one time prom version (shipped after programming, extended operating temperature 125 c version) one time prom version (blank) one time prom version (shipped after programming, extended operating temperature version) one time prom version (shipped after programming, extended operating temperature 125 c version) emulator mcu m37540m2-xxxsp m37540m2-xxxfp m37540m2t-xxxfp m37540m2v-xxxfp m37540m2-xxxgp m37540m2t-xxxgp m37540m2v-xxxgp m37540m4-xxxsp m37540m4-xxxfp m37540m4t-xxxfp m37540m4v-xxxfp m37540m4-xxxgp m37540m4t-xxxgp m37540m4v-xxxgp m37540e2sp* m37540e2fp* m37540e2gp* m37540e8sp m37540e8fp m37540e8t-xxxfp* m37540e8v-xxxfp* m37540e8gp m37540e8t-xxxgp* m37540e8v-xxxgp* m37540rss *: under development group expansion
hardware 7540 group user s manual 1-11 b7 b0 x b7 b0 s b7 b0 y b7 b0 pc l processor status register (ps) carry flag b7 b0 b7 b0 a b15 pc h zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag program counter stack pointer index register y index register x accumulator c z i d b t v n functional description central processing unit (cpu) the mcu uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine-language instructions or the series 740 user s manual for details on each instruction set. machine-resident 740 family instructions are as follows: 1. the fst and slw instructions cannot be used. 2. the mul and div instructions can be used. 3. the wit instruction can be used. 4. the stp instruction can be used. this instruction cannot be used while cpu operates by a ring os- cillator. accumulator (a) the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. index register x (x), index register y (y) both index register x and index register y are 8-bit registers. in the index addressing modes, the value of the operand is added to the contents of register x or register y and specifies the real address. when the t flag in the processor status register is set to 1 , the value contained in index register x becomes the address for the second operand. stack pointer (s) the stack pointer is an 8-bit register used during subroutine calls and interrupts. the stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. the lower eight bits of the stack address are determined by the contents of the stack pointer. the upper eight bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is 0 , then the ram in the zero page is used as the stack area. if the stack page selection bit is 1 , then ram in page 1 is used as the stack area. the stack page selection bit is located in the sfr area in the zero page. note that the initial value of the stack page selection bit varies with each microcomputer type. also some microcom- puter types have no stack page selection bit and the upper eight bits of the stack address are fixed. the operations of pushing reg- ister contents onto the stack and popping them from the stack are shown in fig. 9. program counter (pc) the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 9 740 family cpu register structure functional description
hardware 1-12 7540 group user s manual execute jsr on-going routine m (s) (pc h ) (s) (s 1) m (s) (pc l ) execute rts (pc l ) m (s) (s) (s 1) (s) (s + 1) (s) (s + 1) (pc h ) m (s) subroutine restore return address store return address on stack m (s) (ps) execute rti (ps) m (s) (s) (s 1) (s) (s + 1) interrupt service routine restore contents of processor status register m (s) (pc h ) (s) (s 1) m (s) (pc l ) (s) (s 1) (pc l ) m (s) (s) (s + 1) (s) (s + 1) (pc h ) m (s) restore return address i flag 0 to 1 fetch the jump vector store return address on stack store contents of processor status register on stack interrupt request (note) note : the condition to enable the interrupt interrupt enable bit is 1 interrupt disable flag is 0 table 3 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 10 register push and pop at interrupt generation and subroutine call functional description
hardware 7540 group user s manual 1-13 processor status register (ps) the processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. branch operations can be performed by testing the carry (c) flag, zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. after reset, the interrupt disable (i) flag is set to 1 , but all other flags are undefined. since the index x mode (t) and decimal mode (d) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. (2) zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . (3) interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . when an interrupt occurs, this flag is automatically set to 1 to prevent other interrupts from interfering until the current interrupt is serviced. (4) decimal mode flag (d) the d flag determines whether additions and subtractions are ex- ecuted in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. (5) break flag (b) the b flag is used to indicate that the current interrupt was gener- ated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to gener- ate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . the saved processor status is the only place where the break flag is ever set. (6) index x mode flag (t) when the t flag is 0 , arithmetic operations are performed be- tween accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. when the t flag is 1 , direct arithmetic operations and direct data trans- fers are enabled between memory locations, i.e. between memory and memory, memory and i/o, and i/o and i/o. in this case, the result of an arithmetic operation performed on data in memory lo- cation 1 and memory location 2 is stored in memory location 1. the address of memory location 1 is specified by index register x, and the address of memory location 2 is specified by normal ad- dressing modes. (7) overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location oper- ated on by the bit instruction is stored in the overflow flag. (8) negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 4 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag i flag sei cli d flag sed cld b flag t flag set clt v flag clv n flag functional description
hardware 1-14 7540 group user s manual [cpu mode register] cpum the cpu mode register contains the stack page selection bit. this register is allocated at address 003b16. switching method of cpu mode register switch the cpu mode register (cpum) at the head of program af- ter releasing reset in the following method. fig. 12 switching method of cpu mode register fig. 11 structure of cpu mode register oscillation mode selection bit (note 1) 0 : ceramic oscillation 1 : rc oscillation cpu mode register (cpum: address 003b 16 , initial value: 80 16 ) stack page selection bit 0 : 0 page 1 : 1 page clock division ratio selection bits b7 b6 0 0 : f( 2: these bits are used only when a ceramic oscillation is selected. note 1: the bit can be rewritten only once after releasing reset. after rewriting it is disable to write any data to the bit. however, by reset the bit is initialized and can be rewritten, again. (it is not disable to write any data to the bit for emulator mcu m37540rss .) do not use these when an rc oscillation is selected. after releasing reset switch the oscillation mode selection bit (bit 5 of cpum) switch the clock division ratio selection bits (bits 6 and 7 of cpum) main routine start with a built-in ring oscillator an initial value is set as a ceramic oscillation mode. when it is switched to an rc oscillation, its oscillation starts. select 1/1, 1/2, 1/8 or ring oscillator. wait by ring oscillator operation until establishment of oscillator clock when using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. when using an rc oscillation, wait time is not required basically (time to execute the instruction to switch from a ring oscillator meets the requirement). functional description
hardware 7540 group user s manual 1-15 memory special function register (sfr) area the sfr area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for a stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is a user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. fig. 13 memory map diagram 0100 16 0000 16 0040 16 0440 1 6 ff00 16 ffdc 1 6 fffe 16 ffff 16 3 8 4 5 1 2 7 6 8 xxxx 16 0 1 b f 1 6 0 2 3 f 1 6 0 3 3 f 1 6 8 1 9 2 1 6 3 8 4 3 2 7 6 8 e000 16 c000 16 8000 16 e 0 8 0 1 6 c 0 8 0 1 6 8 0 8 0 1 6 y y y y 1 6 zzzz 16 ram rom r e s e r v e d a r e a s f r a r e a not used i n t e r r u p t v e c t o r a r e a r o m a r e a reserved rom area (128 bytes) z e r o p a g e special page r a m a r e a r a m c a p a c i t y ( b y t e s ) address xxxx 16 r o m c a p a c i t y ( b y t e s ) a d d r e s s y y y y 1 6 reserved rom area a d d r e s s z z z z 1 6 functional description
hardware 1-16 7540 group user s manual fig. 14 memory map of special function register (sfr) note : do not access to the sfr area including nothing. 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) pull-up control register (pull) transmit/receive buffer register (tb/rb) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart control register (uartcon) baud rate generator (brg) port p1p3 control register (p1p3c) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 timer count source set register (tcss) a-d conversion register (low-order) (adl) prescaler 1 (pre1) timer 1 (t1) one-shot start register (ons) timer x mode register (txm) prescaler x (prex) timer x (tx) serial i/o2 control register (sio2con) serial i/o2 register (sio2) a-d control register (adcon) a-d conversion register (high-order) (adh) misrg watchdog timer control register (wdtcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt control register 1 (icon1) timer a mode register (tam) timer a (low-order) (tal) timer a (high-order) (tah) timer y, z mode register (tyzm) prescaler y (prey) timer y secondary (tys) timer y primary (typ) timer y, z waveform output control register (pum) prescaler z (prez) timer z secondary (tzs) timer z primary (tzp) interrupt request register 2 (ireq2) interrupt control register 2 (icon2) functional description
hardware 7540 group user? manual 1-17 functional description i/o ports [direction registers] pid the i/o ports have direction registers which determine the input/ output direction of each pin. each bit in a direction register corre- sponds to one pin, and each pin can be set to be input or output. when ??is set to the bit corresponding to a pin, this pin becomes an output port. when ??is set to the bit, the pin becomes an in- put port. when data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. pins set to input are float- ing, and permit reading pin values. if a pin set to input is written to, only the port latch is written to and the pin remains floating. [pull-up control register] pull by setting the pull-up control register (address 0016 16 ), ports p0 and p3 can exert pull-up control by program. however, pins set to output are disconnected from this control and cannot exert pull-up control. note: p2 6 /a n6 , p2 7 /an 7 , p3 5 and p3 6 do not exist for the 32-pin version. accordingly, the following settings are required; ?set direction registers of ports p2 6 and p2 7 to output. ?set direction registers of ports p3 5 and p3 6 to output. [port p1p3 control register] p1p3c by setting the port p1p3 control register (address 0017 16 ), a cmos input level or a ttl input level can be selected for ports p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 by program. fig. 16 structure of port p1p3 control register fig. 15 structure of pull-up control register port p1p3 control register (p1p3c: address 0017 16 , initial value: 00 16 ) b7 b0 p3 7 /int 0 input level selection bit 0 : cmos level 1 : ttl level p3 6 /int 1 input level selection bit 0 : cmos level 1 : ttl level p1 0 ,p1 2 ,p1 3 input level selection bit 0 : cmos level 1 : ttl level not used note: keep setting the p3 6 /int 1 input level selection bit to 0 (initial value) for 32-pin version. pull-up control register (pull: address 0016 16 , initial value: 00 16 ) p0 0 pull-up control bit b7 b0 0 : pull-up off 1 : pull-up on note : pins set to out p ut p orts are disconnected from p ull-u p control. p3 7 pull-up control bit p3 5 , p3 6 pull-up control bit p3 4 pull-up control bit p3 0 p3 3 pull-up control bit p0 4 p0 7 pull-up control bit p0 2 , p0 3 pull-up control bit p0 1 pull-up control bit
hardware 1-18 7540 group user s manual table 5 i/o port function table pin p0 0 /cntr 1 p0 1 /ty out p0 2 /tz out p0 3 /tx out p0 4 p0 7 p1 0 /rxd 1 p1 1 /txd 1 p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 /an 0 p2 7 /an 7 p3 0 p3 5 p3 6 /int 1 p3 7 /int 0 input/output i/o individual bits i/o format cmos compatible input level cmos 3-state output (note 1) non-port function key input interrupt timer x function output timer y function output timer z function output timer a function input serial i/o1 function input/output serial i/o2 function input/output timer x function input/output a-d conversion input external interrupt input related sfrs pull-up control register timer y mode register timer z mode register timer x mode register timer y,z waveform output control register timer a mode register serial i/o1 control register serial i/o1 control register serial i/o2 control register timer x mode register a-d control register interrupt edge selection register diagram no. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) notes 1: ports p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 are cmos/ttl level. 2: p2 6/ an 6 and p2 7 /an 7 do not exist for the 32-pin version. 3: p3 5 and p3 6 /int 1 do not exist for the 32-pin version. name i/o port p0 i/o port p1 i/o port p2 (note 2) i/o port p3 (note 3) functional description
hardware 7540 group user s manual 1-19 fig. 17 block diagram of ports (1) functional description (6)port p1 1 data bus port latch serial i/o1 output p1 1 /t x d 1 p-channel output disable bit (5)port p1 0 (4)ports p0 4 p0 7 (1)port p0 0 direction register data bus port latch pull-up control to key input interrupt generating circuit cntr 1 interrupt input (2)ports p0 1, p0 2 programmable waveform generation mode timer output (7)port p1 2 serial i/o1, serial i/o2 clock output serial i/o1 mode selection bit serial i/o1 enable bit serial i/o1 enable bit serial i/o1 synchronous clock selection bit s clk2 pin selection bit (3)port p0 3 direction register data bus port latch pull-up control to key input interrupt generating circuit direction register data bus port latch pull-up control to key input interrupt generating circuit timer output p0 3 /tx out output valid direction register data bus port latch pull-up control to key input interrupt generating circuit direction register data bus port latch serial i/o1 enable bit receive enable bit serial i/o1 input p1 0 , p1 2 , p1 3 input level selection bit direction register serial i/o1 enable bit transmit enable bit direction register data bus port latch serial i/o1, serial i/o2 clock input p1 0 , p1 2 , p1 3 input level selection bit * * * p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 input level are switched to the cmos/ttl level by the port p1p3 control register. p0 0 key-on wakeup selection bit when the ttl level is selected, there is no hysteresis characteristics.
hardware 1-20 7540 group user s manual fig. 18 block diagram of ports (2) pull-up control int interrupt input p3 input level selection bit (11) ports p3 0 p3 5 pull-up control (9) port p1 4 data bus serial i/o1 ready output serial i/o2 output serial i/o2 input s data2 pin selection bit port latch direction register s data2 output in operation signal cntr 0 interrupt input pulse output mode timer output p1 0 , p1 2 , p1 3 input level selection bit serial i/o mode selection bit serial i/o1 enable bit s rdy1 output enable bit p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 input level are switched to the cmos/ttl level by the port p1p3 control register. data bus port latch direction register data bus port latch direction register data bus port latch direction register a-d converter input analog input pin selection bit (12) ports p3 6 , p3 7 data bus port latch direction register * * (10) ports p2 0 p2 7 * (8) port p1 3 when the ttl level is selected , there is no h y steresis characteristics. functional description
hardware 7540 group user? manual 1-21 interrupts interrupts occur by 15 different sources : 5 external sources, 9 in- ternal sources and 1 software source. interrupt control all interrupts except the brk instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. when the interrupt enable bit and the in- terrupt request bit are set to ??and the interrupt disable flag is set to ?? an interrupt is accepted. the interrupt request bit can be cleared by program but not be set. the interrupt enable bit can be set and cleared by program. the reset and brk instruction interrupt can never be disabled with any flag or bit. all interrupts except these are disabled when the interrupt disable flag is set. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation upon acceptance of an interrupt the following operations are auto- matically performed: 1. the processing being executed is stopped. 2. the contents of the program counter and processor status reg- ister are automatically pushed onto the stack. 3. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. notes on use when setting the followings, the interrupt request bit may be set to ?? ?hen switching external interrupt active edge related register: interrupt edge selection register (address 003a 16 ) timer x mode register (address 2b 16 ) timer a mode register (address 1d 16 ) when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ??(disabled). ? set the interrupt edge select bit (active edge switch bit). ? set the corresponding interrupt request bit to ??after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ??(enabled). table 6 interrupt vector address and priority vector addresses (note 1) high-order priority low-order interrupt request generating conditions remarks interrupt source fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 note 1: vector addressed contain internal jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. 3: it is an interrupt which can use only for 36 pin version. non-maskable valid only when serial i/o1 is selected valid only when serial i/o1 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (valid at falling) external interrupt (active edge selectable) external interrupt (active edge selectable) stp release timer underflow non-maskable software interrupt at reset input at completion of serial i/o1 data receive at completion of serial i/o1 transmit shift or when transmit buffer is empty at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at falling of conjunction of input logical level for port p0 (at input) at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at timer x underflow at timer y underflow at timer z underflow at timer a underflow at completion of transmit/receive shift at completion of a-d conversion at timer 1 underflow not available at brk instruction execution 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 reset (note 2) serial i/o1 receive serial i/o1 transmit int 0 int 1 (note 3) key-on wake-up cntr 0 cntr 1 timer x timer y timer z timer a serial i/o2 a-d conversion timer 1 reserved area brk instruction functional description
hardware 1-22 7540 group user s manual fig. 19 interrupt control fig. 20 structure of interrupt-related registers interrupt disable flag i interrupt request interrupt request bit interrupt enable bit brk instruction reset b7 b0 b7 b0 b7 b0 interrupt edge selection register int 0 interrupt edge selection bit 0 : falling edge active 1 : rising edge active int 1 interrupt edge selection bit 0 : falling edge active 1 : rising edge active not used (returns 0 when read) p0 0 key-on wakeup enable bit 0 : key-on wakeup enabled 1 : key-on wakeup disabled (intedge : address 003a 16 , initial value : 00 16 ) interrupt request register 1 serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit int 0 interrupt request bit int 1 interrupt request bit key-on wake up interrupt request bit cntr 0 interrupt request bit cntr 1 interrupt request bit timer x interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 , initial value : 00 16 ) b7 b0 interrupt control register 1 serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit int 0 interrupt enable bit int 1 interrupt enable bit (do not write 1 to this bit for 32-pin version) key-on wake up interrupt enable bit cntr 0 interrupt enable bit cntr 1 interrupt enable bit timer x interrupt enable bit 0 : interrupts disabled 1 : interrupts enabled (icon1 : address 003e 16 , initial value : 00 16 ) interrupt request register 2 timer y interrupt request bit timer z interrupt request bit timer a interrupt request bit serial i/o2 interrupt request bit a-d conversion interrupt request bit timer 1 interrupt request bit not used (returns 0 when read) 0 : no interrupt request issued 1 : interrupt request issued (ireq2 : address 003d 16 , initial value : 00 16 ) b7 b0 interrupt control register 2 timer y interrupt enable bit timer z interrupt enable bit timer a interrupt enable bit serial i/o2 interrupt enable bit a-d conversion interrupt enable bit timer 1 interrupt enable bit not used (returns 0 when read) (do not write 1 to this bit) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 , initial value : 00 16 ) functional description
hardware 7540 group user s manual 1-23 key input interrupt (key-on wake-up) a key-on wake-up interrupt request is generated by applying l level to any pin of port p0 that has been set to input mode. in other words, it is generated when the and of input level goes from 1 to 0 . an example of using a key input interrupt is shown in figure 21, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports p0 0 to p0 3 as input ports. fig. 21 connection example when using key input interrupt and port p0 block diagram port pxx l level output pull register bit 3 = 0 port p0 7 latch port p0 7 direction register = 1 ** * p0 7 output key input interrupt request port p0 input read circuit * p-channel transistor for pull-up ** cmos output buffer pull register bit 3 = 0 port p0 6 latch port p0 6 direction register = 1 ** * p0 6 output pull register bit 3 = 0 port p0 5 latch port p0 5 direction register = 1 ** * p0 5 output pull register bit 3 = 0 port p0 4 latch port p0 4 direction register = 1 ** * p0 4 output pull register bit 2 = 1 port p0 3 latch port p0 3 direction register = 0 ** * p0 3 input pull register bit 2 = 1 port p0 2 latch port p0 2 direction register = 0 ** * p0 2 input pull register bit 1 = 1 port p0 1 latch port p0 1 direction register = 0 ** * p0 1 input pull register bit 0 = 1 port p0 0 latch port p0 0 direction register = 0 ** * p0 0 input falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection port p0 0 key-on wakeup selection bit functional description
hardware 1-24 7540 group user s manual timers the 7540 group has 5 timers: timer 1, timer a, timer x, timer y and timer z. the division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. all the timers are down count timers. when a timer reaches 0 , an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. when a timer underflows, the interrupt request bit corresponding to each timer is set to 1 . timer 1 timer 1 is an 8-bit timer and counts the prescaler output. when timer 1 underflows, the timer 1 interrupt request bit is set to 1 . prescaler 1 is an 8-bit prescaler and counts the signal which is the oscillation frequency divided by 16. prescaler 1 and timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. the value of prescaler 1 latch is set to prescaler 1 when prescaler 1 underflows.the value of timer 1 latch is set to timer 1 when timer 1 underflows. when writing to prescaler 1 (pre1) is executed, the value is writ- ten to both the prescaler 1 latch and prescaler 1. when writing to timer 1 (t1) is executed, the value is written to both the timer 1 latch and timer 1. when reading from prescaler 1 (pre1) and timer 1 (t1) is ex- ecuted, each count value is read out. timer 1 always operates in the timer mode. prescaler 1 counts the signal which is the oscillation frequency di- vided by 16. each time the count clock is input, the contents of prescaler 1 is decremented by 1. when the contents of prescaler 1 reach 00 16 , an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into prescaler 1 and count contin- ues. the division ratio of prescaler 1 is 1/(n+1) provided that the value of prescaler 1 is n. the contents of timer 1 is decremented by 1 each time the under- flow signal of prescaler 1 is input. when the contents of timer 1 reach 00 16 , an underflow occurs at the next count clock, and the timer 1 latch is reloaded into timer 1 and count continues. the di- vision ratio of timer 1 is 1/(m+1) provided that the value of timer 1 is m. accordingly, the division ratio of prescaler 1 and timer 1 is 1/((n+1) ? timer a timer a is a 16-bit timer and counts the signal which is the oscil- lation frequency divided by 16. when timer a underflows, the timer a interrupt request bit is set to 1 . timer a consists of the low-order of timer a (tal) and the high-or- der of timer a (tah). timer a has the timer a latch to retain the reload value. the value of timer a latch is set to timer a at the timing shown below. when timer a undeflows. when an active edge is input from cntr 1 pin (valid only when period measurement mode and pulse width hl continuously mea- surement mode). when writing to both the low-order of timer a (tal) and the high- order of timer a (tah) is executed, the value is written to both the timer a latch and timer a. when reading from the low-order of timer a (tal) and the high-or- der of timer a (tah) is executed, the following values are read out according to the operating mode. in timer mode, event counter mode: the count value of timer a is read out. in period measurement mode, pulse width hl continuously mea- surement mode: the measured value is read out. be sure to write to/read out the low-order of timer a (tal) and the high-order of timer a (tah) in the following order; read read the high-order of timer a (tah) first, and the low-order of timer a (tal) next and be sure to read out both tah and tal. write write to the low-order of timer a (tal) first, and the high-order of timer a (tah) next and be sure to write to both tal and tah. timer a can be selected in one of 4 operating modes by setting the timer a mode register. (1) timer mode timer a counts the oscillation frequency divided by 16. each time the count clock is input, the contents of timer a is decremented by 1. when the contents of timer a reach 0000 16 , an underflow oc- curs at the next count clock, and the timer a latch is reloaded into timer a. the division ratio of timer a is 1/(n+1) provided that the value of timer a is n. (2) period measurement mode in the period measurement mode, the pulse period input from the p0 0 /cntr 1 pin is measured. cntr 1 interrupt request is generated at rising/falling edge of cntr 1 pin input singal. simultaneousuly, the value in the timer a latch is reloaded intimer a and count continues. the active edge of cntr 1 pin input signal can be selected from rising or falling by the cntr 1 active edge switch bit .the count value when trigger input from cntr 1 pin is accepted is retained until timer a is read once. functional description
hardware 7540 group user s manual 1-25 (3) event counter mode timer a counts signals input from the p0 0 /cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. the active edge of cntr 1 pin input signal can be selected from rising or falling by the cntr 1 active edge switch bit . (4) pulse width hl continuously measurement mode in the pulse width hl continuously measurement mode, the pulse width ( h and l levels) input to the p0 0 /cntr 1 pin is measured. cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. the count value when trigger input from the cntr 1 pin is ac- cepted is retained until timer a is read once. timer a can stop counting by setting 1 to the timer a count stop bit in any mode. also, when timer a underflows, the timer a interrupt request bit is set to 1 . note on timer a is described below; note on timer a cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. when this bit is 0 , the cntr 1 interrupt request bit is set to 1 at the falling edge of the cntr 1 pin input signal. when this bit is 1 , the cntr 1 interrupt request bit is set to 1 at the rising edge of the cntr 1 pin input signal. however, in the pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. fig. 22 structure of timer a mode register timer a mode register (tam : address 001d 16 , initial value: 00 16 ) b7 b0 not used (return 0 when read) timer a operating mode bits b5 b4 0 0 : timer mode 0 1 : period measurement mode 1 0 : event counter mode 1 1 : pulse width hl continuously measurement mode cntr 1 active edge switch bit 0 : count at rising edge in event counter mode measure the falling edge period in period measurement mode falling edge active for cntr 1 interrupt 1 : count at falling edge in event counter mode measure the rising edge period in period measurement mode rising edge active for cntr 1 interrupt timer a count stop bit 0 : count start 1 : count stop timer x timer x is an 8-bit timer and counts the prescaler x output. when timer x underflows, the timer x interrupt request bit is set to 1 . prescaler x is an 8-bit prescaler and counts the signal selected by the timer x count source selection bit. prescaler x and timer x have the prescaler x latch and the timer x latch to retain the reload value, respectively. the value of prescaler x latch is set to prescaler x when prescaler x underflows.the value of timer x latch is set to timer x when timer x underflows. when writing to prescaler x (prex) is executed, the value is writ- ten to both the prescaler x latch and prescaler x. when writing to timer x (tx) is executed, the value is written to both the timer x latch and timer x. when reading from prescaler x (prex) and timer x (tx) is ex- ecuted, each count value is read out. timer x can can be selected in one of 4 operating modes by set- ting the timer x operating mode bits of the timer x mode register. (1) timer mode prescaler x counts the count source selected by the timer x count source selection bits. each time the count clock is input, the con- tents of prescaler x is decremented by 1. when the contents of prescaler x reach 00 16 , an underflow occurs at the next count clock, and the prescaler x latch is reloaded into prescaler x and count continues. the division ratio of prescaler x is 1/(n+1) pro- vided that the value of prescaler x is n. the contents of timer x is decremented by 1 each time the under- flow signal of prescaler x is input. when the contents of timer x reach 00 16 , an underflow occurs at the next count clock, and the timer x latch is reloaded into timer x and count continues. the di- vision ratio of timer x is 1/(m+1) provided that the value of timer x is m. accordingly, the division ratio of prescaler x and timer x is 1/((n+1) ? (2) pulse output mode in the pulse output mode, the waveform whose polarity is inverted each time timer x underflows is output from the cntr 0 pin. the output level of cntr 0 pin can be selected by the cntr 0 ac- tive edge switch bit. when the cntr 0 active edge switch bit is 0 , the output of cntr 0 pin is started at h level. when this bit is 1 , the output is started at l level. also, the inverted waveform of pulse output from cntr 0 pin can be output from tx out pin by setting 1 to the p0 3 /tx out output valid bit. when using a timer in this mode, set the port p1 4 and p0 3 direc- tion registers to output mode. (3) event counter mode the timer a counts signals input from the p1 4 /cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. the active edge of cntr 0 pin input signal can be selected from rising or falling by the cntr 0 active edge switch bit . functional description
hardware 1-26 7540 group user s manual (4) pulse width measurement mode in the pulse width measurement mode, the pulse width of the sig- nal input to p1 4 /cntr 0 pin is measured. the operation of timer x can be controlled by the level of the sig- nal input from the cntr 0 pin. when the cntr 0 active edge switch bit is 0 , the signal selected by the timer x count source selection bit is counted while the input signal level of cntr 0 pin is h . the count is stopped while the pin is l . also, when the cntr 0 active edge switch bit is 1 , the signal selected by the timer x count source selection bit is counted while the input signal level of cntr 0 pin is l . the count is stopped while the pin is h . timer x can stop counting by setting 1 to the timer x count stop bit in any mode. also, when timer x underflows, the timer x interrupt request bit is set to 1 . note on timer x is described below; note on timer x cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. when this bit is 0 , the cntr 0 interrupt request bit is set to 1 at the falling edge of cntr 0 pin input signal. when this bit is 1 , the cntr 0 interrupt request bit is set to 1 at the rising edge of cntr 0 pin input signal. fig. 23 structure of timer x mode register fig. 24 timer count source set register timer x mode register (txm : address 002b 16 , initial value: 00 16 ) cntr 0 active edge switch bit 0 : interrupt at falling edge count at rising edge (in event counter mode) 1 : interrupt at rising edge count at falling edge (in event counter mode) timer x operating mode bits b1 b0 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode not used (return 0 when read) timer x count stop bit 0 : count start 1 : count stop b7 b0 p0 3 /tx out output valid bit 0 : output invalid (i/o port) 1 : output valid (inverted cntr 0 output) timer count source set register (tcss : address 002e 16 , initial value: 00 16 ) b7 b0 timer x count source selection bits b1 b0 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : f(x in ) (note 1) 1 1 : not available timer y count source selection bits b3 b2 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : ring oscillator output (note 2) 1 1 : not available timer z count source selection bits b5 b4 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : timer y underflow 1 1 : not available fix this bit to 0 . not used (return 0 when read) notes 1: f(x in ) can be used as timer x count source when using a ceramic resonator or ring oscillator. do not use it at rc oscillation. 2: system operates using a ring oscillator as a count source by setting the ring oscillator to oscillation enabled by bit 3 of cpum. functional description
hardware 7540 group user s manual 1-27 timer y timer y is an 8-bit timer and counts the prescaler y output. when timer y underflows, the timer y interrupt request bit is set to 1 . prescaler y is an 8-bit prescaler and counts the signal selected by the timer y count source selection bit. prescaler y has the prescaler y latch to retain the reload value. timer y has the timer y primary latch and timer y secondary latch to retain the reload value. the value of prescaler y latch is set to prescaler y when prescaler y underflows.the value of timer y primary latch or timer y secondary latch are set to timer y when timer y underflows. as for the value to transfer to timer y, either of timer y primary or timer y secondary is selected depending on the timer y operating mode. when writing to prescaler y (prey), timer y primary (typ) or timer y secondary (tys) is executed, writing to latch only or latch and prescaler (timer) can be selected by the setting value of the timer y write control bit. be sure to set the timer y write con- trol bit because there are some notes according to the operating mode. when reading from prescaler y (prey) is executed, the count value of prescaler y is read out. when reading from timer y pri- mary (typ) is executed, the count value of timer y is read out. the count value of timer y can be read out by reading from the timer y primary (typ) even when the value of timer y primary latch or timer y secondary latch is counted. when reading the timer y secondary (tys) is executed, the undefined value is read out. timer y can be selected in one of 2 operating modes by setting the timer y operating mode bits of the timer y, z mode register. (1) timer mode prescaler y counts the count source selected by the timer y count source selection bits. each time the count clock is input, the con- tents of prescaler y is decremented by 1. when the contents of prescaler y reach 00 16 , an underflow occurs at the next count clock, and the prescaler y latch is reloaded into prescaler y. the division ratio of prescaler y is 1/(n+1) provided that the value of prescaler y is n. the contents of timer y is decremented by 1 each time the under- flow signal of prescaler y is input. when the contents of timer y reach 00 16 , an underflow occurs at the next count clock, and the timer y primary latch is reloaded into timer y and count continues. (in the timer mode, the contents of timer y primary latch is counted. timer y secondary latch is not used in this mode.) the division ratio of timer y is 1/(m+1) provided that the value of timer y is m. accordingly, the division ratio of prescaler y and timer y is 1/((n+1) ? latch only or latches and prescaler y and timer y primary can be selected by the setting value of the timer y write control bit. (2) programmable waveform generation mode in the programmable waveform generation mode, timer counts the setting value of timer y primary and the setting value of timer y secondary alternately, the waveform inverted each time timer y underflows is output from ty out pin. when using this mode, be sure to set 1 to the timer y write con- trol bit to select write to latch only . also, set the port p0 1 direction registers to output mode. the active edge of output waveform is set by the timer y output level latch (b5) of the timer y, z waveform output control register (pum). when 0 is set to b5 of pum, h interval by the setting value of typ or l interval by the setting value of tys is output alternately. when 1 is set to b5 of pum, l interval by the setting value of typ or h interval by the setting value of tys is output alternately. also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer y primary wave- form extension control bit (b2) and the timer y secondary waveform extension control bit (b3) of pum to 1 . as a result, the waveforms of more accurate resolution can be output. when b2 and b3 of pum are used, the frequency and duty of the output waveform are as follows; waveform frequency: fyout= duty: dyout= tmycl: timer y count source (frequency) typ: timer y primary (8bit) tys: timer y secondary (8bit) expyp: timer y primary waveform extension control bit (1bit) expys: timer y secondary waveform extension control bit (1bit) in the programmable waveform generation mode, when values of the typ, tys, expyp and expys are changed, the output wave- form is changed at the beginning (timer y primary waveform interval) of waveform period. when the count values are changed, set values to the tys, expyp and expys first. after then, set the value to typ. the val- ues are set all at once at the beginning of the next waveform period when the value is set to typ. (when writing at timer stop is executed, writing to typ at last is required.) notes on programmable waveform generation mode is described below; 2 ? ? ? ? ? ? functional description
hardware 1-28 7540 group user s manual notes on programmable generation waveform mode count set value in the programmable waveform generation mode, values of tys, expyp, and expys are valid by writing to typ because the set- ting to them is executed all at once by writing to typ. even when changing typ is not required, write the same value again. write timing to typ in the programmable waveform generation mode, when the set- ting value is changed while the waveform is output, set by software in order not to execute the writing to typ and the timing of timer underflow during the secondary interval simultanesously. usage of waveform extension function the waveform extension function by the timer y waveform exten- sion control bit can be used only when 00 16 is set to prescaler y. when the value other than 00 16 is set to prescaler y, be sure to set 0 to expyp and expys. timer y write mode when using this mode, be sure to set 1 to the timer y write con- trol bit to select write to latch only . timer y can stop counting by setting 1 to the timer y count stop bit in any mode. also, when timer y underflows, the timer y interrupt request bit is set to 1 . timer y reloads the value of latch when counting is stopped by the timer y count stop bit. (when timer is read out while timer is stopped, the value of latch is read. the value of timer can be read out only while timer is operating.) functional description
hardware 7540 group user s manual 1-29 timer z timer z is an 8-bit timer and counts the prescaler z output. when timer z underflows, the timer z interrupt request bit is set to 1 . prescaler z is an 8-bit prescaler and counts the signal selected by the timer z count source selection bit. prescaler z has the prescaler z latch to retain the reload value. timer z has the timer z primary latch and timer z secondary latch to retain the reload value. the value of prescaler z latch is set to prescaler z when prescaler z underflows.the value of timer z primary latch or timer z second- ary latch are set to timer z when timer z underflows. as for the value to transfer to timer z, either of timer z primary or timer z secondary is selected depending on the timer z operating mode. when writing to prescaler z (prez), timer z primary (tzp) or timer z secondary (tzs) is executed, writing to latch only or latches and prescaler z and timer z can be selected by the set- ting value of the timer z write control bit. be sure to set the write control bit because there are some notes according to the operat- ing mode. when reading from prescaler z (prez) is executed, the count value of prescaler z is read out. when reading from timer z pri- mary (tzp) is executed, the count value of timer z is read out. the count value of timer z can be read out by reading from the timer z primary (tzp) even when the value of timer z primary latch or timer z secondary latch is counted. when reading the timer z secondary (tzs) is executed, the undefined value is read out. timer z can be selected in one of 4 operating modes by setting the timer z operating mode bits of the timer y, z mode register. (1) timer mode prescaler z counts the count source selected by the timer z count source selection bits. each time the count clock is input, the con- tents of prescaler z is decremented by 1. when the contents of prescaler z reach 00 16 , an underflow occurs at the next count clock, and the prescaler z latch is reloaded into prescaler z. the division ratio of prescaler z is 1/(n+1) provided that the value of prescaler z is n. the contents of timer z is decremented by 1 each time the under- flow signal of prescaler z is input. when the contents of timer z reach 00 16 , an underflow occurs at the next count clock, and the timer z primary latch is reloaded into timer z and count continues. (in the timer mode, the contents of timer z primary latch is counted. timer z secondary latch is not used in this mode.) the division ratio of timer z is 1/(m+1) provided that the value of timer z is m. accordingly, the division ratio of prescaler z and timer z is 1/((n+1) ? latch only or latches and prescaler z and timer z primary can be selected by the setting value of the timer z write control bit. (2) programmable waveform generation mode in the programmable waveform generation mode, timer counts the setting value of timer z primary and the setting value of timer z secondary alternately, the waveform inverted each time timer z underflows is output from tz out pin. when using this mode, be sure to set 1 to the timer z write con- trol bit to select write to latch only . also, set the port p0 2 direction registers to output mode. the active edge of output waveform is set by the timer z output level latch (b4) of the timer y, z waveform output control register (pum). when 0 is set to b4 of pum, h interval by the setting value of tzp or l interval by the setting value of tzs is output al- ternately. when 1 is set to b4 of pum, l interval by the setting value of tzp or h interval by the setting value of tzs is output alternately. also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer z primary wave- form extension control bit (b0) and the timer z secondary waveform extension control bit (b1) of pum to 1 . as a result, the waveforms of more accurate resolution can be output. when b0 and b1 of pum are used, the frequency and duty of the output waveform are as follows; waveform frequency: fzout= duty: dzout= tmzcl: timer z count source (frequency) tzp: timer z primary (8bit) tzs: timer z secondary (8bit) expzp: timer z primary waveform extension control bit (1bit) expzs: timer z secondary waveform extension control bit (1bit) in the programmable waveform generation mode, when values of the tzp, tzs, expzp and expzs are changed, the output wave- form is changed at the beginning (timer z primary waveform interval) of waveform period. when the count values are changed, set values to the tzs, expzp and expzs first. after then, set the value to tzp. the val- ues are set all at once at the beginning of the next waveform period when the value is set to tzp. (when writing at timer stop is executed, writing to tzp at last is required.) 2 ? ? ? ? ? ? functional description
hardware 1-30 7540 group user s manual notes on the programmable waveform generation mode are de- scribed below; notes on programmable waveform generation mode count set value in the programmable waveform generation mode, values of tzs, expzp, and expzs are valid by writing to tzp because the set- ting to them is executed all at once by writing to tzp. even when changing tzp is not required, write the same value again. write timing to tzp in the programmable waveform generation mode, when the set- ting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer underflow during the secondary interval simultanesously. usage of waveform extension function the waveform extension function by the timer z waveform exten- sion control bit can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp and expzs. also, when the timer y underflow is selected as the count source, the waveform extension function cannot be used. timer z write mode when using this mode, be sure to set 1 to the timer z write con- trol bit to select write to latch only . (3) programmable one-shot generation mode in the programmable one-shot generation mode, the one-shot pulse by the setting value of timer z primary can be output from tz out pin by software or external trigger. when using this mode, be sure to set 1 to the timer z write control bit to select write to latch only . also, set the port p0 2 direction registers to output mode. in this mode, tzs is not used. the active edge of output waveform is set by the timer z output level latch (b5) of the timer y, z waveform output control register (pum). when 0 is set to b5 of pum, h pulse during the interval of the tzp setting value is output. when 1 is set to b5 of pum, l pulse during the interval of the tzp setting value is output. also, in this mode, the interval of the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting the timer z primary waveform extension control bit (b2) of pum to 1 . as a result, the waveforms of more accurate resolution can be output. in the programmable one-shot generation mode, the trigger by software or the external int 0 pin can be accepted by writing 0 to the timer z count stop bit after the count value is set. (at the time when 0 is written to the timer z count stop bit, timer z stops.) by writing 1 to the timer z one-shot start bit, or by inputting the valid trigger to the int 0 pin after the trigger to the int 0 pin be- comes valid by writing 1 to the int 0 pin one-shot trigger control bit, timer z starts counting, at the same time, the output of tz out pin is inverted. when timer z underflows, the output of tz out pin is inverted again and timer z stops. when also the trigger of int 0 pin is accepted, the contents of the one-shot start bit is changed to 1 by hardware. the falling or rising can be selected as the edge of the valid trig- ger of int 0 pin by the int 0 pin one-shot trigger edge selection bit. during the one-shot pulse output interval, the one-shot pulse out- put can be stopped forcibly by writing 0 to the timer z one-shot start bit. in the programmable one-shot generation mode, when the count values are changed, set value to the expzp first. after then, set the value to tzp. the values are set all at once at the beginning of the next one-shot pulse when the value is set to tzp. (when writ- ing at timer stop is executed, writing to tzp at last is required.) notes on the programmable one-shot generation mode are de- scribed below; notes on programmable one-shot generation mode count set value in the programmable one-shot generation mode, the value of expzp becomes valid by writing to tzp. even when changing tzp is not required, write the same value again. write timing to tzp in the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer un- derflow simultanesously. usage of waveform extension function the waveform extension function by the timer z waveform exten- sion control bit can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp. also, when the timer y underflow is selected as the count source, the waveform extension function cannot be used. timer z write mode when using this mode, be sure to set 1 to the timer z write con- trol bit to select write to latch only . functional description
hardware 7540 group user s manual 1-31 (4) programmable wait one-shot generation mode in the programmable wait one-shot generation mode, the one-shot pulse by the setting value of timer z secondary can be output from tz out pin by software or external trigger to int 0 pin after the wait by the setting value of the timer z primary. when using this mode, be sure to set 1 to the timer z write control bit to select write to latch only . also, set the port p0 2 direction registers to output mode. the active edge of output waveform is set by the timer z output level latch (b5) of the timer y, z waveform output control register (pum). when 0 is set to b5 of pum, after the wait during the in- terval of the tzp setting value, h pulse during the interval of the tzs setting value is output. when 1 is set to b5 of pum, after the wait during the interval of the tzp setting value, l pulse during the interval of the tzs setting value is output. also, in this mode, the intervals of the wait and the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting expzp and expzs of pum to 1 . as a result, the waveforms of more accurate resolution can be output. in the programmable one-shot generation mode, the trigger by software or the external int 0 pin can be accepted by writing 0 to the timer z count stop bit after the count value is set. (at the time when 0 is written to the timer z count stop bit, timer z stops.) by writing 1 to the timer z one-shot start bit, or by inputting the valid trigger to the int 0 pin after the trigger to the int 0 pin be- comes valid by writing 1 to the int 0 pin one-shot trigger control bit, timer z starts counting. while timer z counts the tzp, the initial value of the tz out pin output is retained. when timer z underflows, the value of tzs is reloaded, at the same time, the output of tz out pin is inverted. when timer z underflows, the output of tz out pin is inverted again and timer z stops. when also the trigger of int 0 pin is ac- cepted, the contents of the one-shot start bit is changed to 1 by hardware. the falling or rising can be selected as the edge of the valid trig- ger of int 0 pin by the int 0 pin one-shot trigger edge selection bit. during the wait interval and the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing 0 to the timer z one-shot start bit. in the programmable wait one-shot generation mode, when the count values are changed, set values to the tzs, expzp and expzs first. after then, set the value to tzp. the values are set all at once at the beginning of the next wait interval when the value is set to tzp. (when writing at timer stop is executed, writing to tzp at last is required.) notes on the programmable wait one-shot generation mode are described below; notes on programmable wait one-shot generation mode count set value in the programmable wait one-shot generation mode, values of tzs, expzp and expzs are valid by writing to tzp. even when changing tzp is not required, write the same value again. write timing to tzp in the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by soft- ware in order not to execute the writing to tzp and the timing of timer underflow during the secondary interval simultanesously. usage of waveform extension function the waveform extension function by the timer z waveform exten- sion control bit can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp and expzs. also, when the timer y underflow is selected as the count source, the waveform extension function cannot be used. timer z write mode when using this mode, be sure to set 1 to the timer z write con- trol bit to select write to latch only . timer z can stop counting by setting 1 to the timer z count stop bit in any mode. also, when timer z underflows, the timer z interrupt request bit is set to 1 . timer z reloads the value of latch when counting is stopped by the timer z count stop bit. (when timer is read out while timer is stopped, the value of latch is read. the value of timer can be read out only while timer is operating.) functional description
hardware 1-32 7540 group user s manual fig. 26 structure of timer y, z waveform output control register fig. 27 structure of one-shot start register fig. 25 structure of timer y, z mode register b7 b0 timer y, z mode register (tyzm : address 0020 16 , initial value: 00 16 ) timer y operating mode bit 0 : timer mode 1 : programmable waveform generation mode not used (return 0 when read) timer y write control bit 0 : write to latch and timer simultaneously 1 : write to only latch timer y count stop bit 0 : count start 1 : count stop timer z operating mode bits b5 b4 0 0 : timer mode 0 1 : programmable waveform generation mode 1 0 : programmable one-shot generation mode 1 1 : programmable wait one-shot generation mode timer z write control bit 0 : write to latch and timer simultaneously 1 : write to only latch timer z count stop bit 0 : count start 1 : count stop b7 b0 timer y, z waveform output control register (pum : address 0024 16 , initial value: 00 16 ) timer y primary waveform extension control bit 0 : waveform not extended 1 : waveform extended timer y secondary waveform extension control bit 0 : waveform not extended 1 : waveform extended timer z primary waveform extension control bit 0 : waveform not extended 1 : waveform extended timer z secondary waveform extension control bit 0 : waveform not extended 1 : waveform extended timer y output level latch 0 : l output 1 : h output timer z output level latch 0 : l output 1 : h output int 0 pin one-shot trigger control bit 0 : int 0 pin one-shot trigger invalid 1 : int 0 pin one-shot trigger valid int 0 pin one-shot trigger active edge selection bit 0 : falling edge trigger 1 : rising edge trigger b7 b0 one-shot start register (ons : address 002a 16 , initial value: 00 16 ) timer z one-shot start bit 0 : one-shot stop 1 : one-shot start not used (return 0 when read) functional description
hardware 7540 group user s manual 1-33 fig. 28 block diagram of timer 1 and timer a timer a (low-order) latch (8) timer a (low-order) (8) timer a (high-order) latch (8) timer a (high-order) (8) data bus p0 0 /cntr 1 cntr 1 active edge switch bit f(x in )/16 rising edge detected falling edge detected timer a operation mode bit timer a count stop bit prescaler 1 latch (8) prescaler 1 (8) timer 1 latch (8) timer 1 (8) f(x in )/16 data bus timer a interrupt request bit timer 1 interrupt request bit pulse width hl continuously measurement mode period measurement mode functional description
hardware 1-34 7540 group user? manual fig. 29 block diagram of timer x, timer y and timer z q q t toggle flip-flop timer y count stop bit programmable waveform gengeration mode f(x in )/16 f(x in )/2 timer y count source selection bits waveform extension function timer y primary waveform extension control bit p0 1 /ty out timer y output level latch q q t f(x in )/16 waveform extension function timer z primary waveform extenstion control bit p0 2 /tz out int 0 interrupt request bit p3 7 /int 0 f(x in )/2 timer z count stop bit ring oscillator clock ring (ring oscillator output in fig. 51, 52) q q p1 4 /cntr 0 r t f(x in )/16 f(x in )/2 timer x interrupt request bit toggle flip-flop timer x count stop bit pulse width measurement mode event counter mode cntr 0 interrupt request bit pulse output mode port p1 4 latch port p1 4 direction register cntr 0 active edge switch bit timer mode pulse output mode cntr 0 active edge switch bit timer x count source selection bits f(x in ) p0 3 / tx out prescaler x latch (8) prescaler x (8) timer x latch (8) timer x (8) data bus 0 1 0 1 writing to timer x latch pulse output mode p0 3 /tx out output valid port p0 3 latch port p0 3 direction register prescaler y latch (8) prescaler y (8) timer y primary latch (8) timer y (8) data bus timer y secondary latch (8) timer y interrupt request bit port p0 1 latch port p0 1 direction register timer y secondary waveform extension control bit prescaler z latch (8) prescaler z (8) timer z primary latch (8) timer z (8) data bus timer z secondary latch (8) timer z interrupt request bit timer z count source selection bits one-shot pulse trigger input int 0 pin trigger active edge selection bit programmable one-shot generation mode programmable wait one-shot generation mode timer z one-shot start bit timer z secondary waveform extenstion control bit port p0 2 latch port p0 2 direction register toggle flip flop timer z output level latch programmable waveform generation mode programmable one-shot generation mode programmable wait one-shot generation mode functional description
hardware 7540 group user s manual 1-35 fig. 30 block diagram of clock synchronous serial i/o1 fig. 31 operation of clock synchronous serial i/o1 function serial i/o serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o1 mode can be selected by setting the serial i/o1 mode selection bit of the serial i/o1 control register (bit 6) to 1 . for clock synchronous serial i/o1, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. 1/4 1/4 f/f p1 2 /s clk1 serial i/o1 status register serial i/o1 control register p1 3 /s rdy1 p1 0 /r x d 1 p1 1 /t x d 1 x in receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector transmit buffer register data bus address 0018 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit shift register d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd serial input rxd write pulse to receive/transmit buffer register (address 0018 16 ) overrun error (oe) detection notes 1: as the transmit interrupt (ti), which can be selected, either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes 1 . receive enable signal s rdy1 functional description
hardware 1-36 7540 group user s manual fig. 32 block diagram of uart serial i/o1 (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode selection bit of the serial i/o1 control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. x in 1/4 oe pe fe 1/16 1/16 data bus receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register data bus transmit shift register address 0018 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 st detector sp detector uart control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o1 synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o1 control register p1 2 /s clk1 serial i/o1 status register p1 0 /r x d 1 p1 1 /t x d 1 the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 33 operation of uart serial i/o1 function tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes 1 (at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes 1, can be selected to occur depending on the setting of the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes 1. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes ? ? functional description
hardware 7540 group user s manual 1-37 [transmit buffer register/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0 . [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o1 status register are initialized to 0 at reset, but if the transmit enable bit of the serial i/o1 control regis- ter has been set to 1 , the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register consists of eight control bits for the serial i/o1 function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is al- ways valid and sets the output structure of the p1 1 /txd 1 pin. [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. notes on serial i/o serial i/o interrupt when setting the transmit enable bit to 1 , the serial i/o transmit interrupt request bit is automatically set to 1 . when not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ? 0 (disabled). ? 1 . ? 0 after 1 or more instructions have been executed. ? 1 (enabled). i/o pin function when serial i/o1 is enabled. the functions of p1 2 and p1 3 are switched with the setting values of a serial i/o1 mode selection bit and a serial i/o1 synchronous clock selection bit as follows. (1) serial i/o1 mode selection bit 1 : clock synchronous type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit 0 : p1 2 pin turns into an output pin of a synchronous clock. 1 : p1 2 pin turns into an input pin of a synchronous clock. setup of a srdy1 output enable bit (srdy) 0 : p1 3 pin can be used as a normal i/o pin. 1 : p1 3 pin turns into a srdy output pin. (2) serial i/o1 mode selection bit 0 : clock asynchronous (uart) type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit 0 : p1 2 pin can be used as a normal i/o pin. 1 : p1 2 pin turns into an input pin of an external clock. when clock asynchronous (uart) type serial i/o is selected, it is p1 3 pin. it can be used as a normal i/o pin. functional description
hardware 1-38 7540 group user s manual fig. 34 structure of serial i/o1-related registers b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns 1 when read) serial i/o1 status register serial i/o1 control register b0 b0 brg count source selection bit (css) 0: f(x in ) 1: f(x in )/4 serial i/o1 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected, external clock input divided by 16 when uart is selected. s rdy1 output enable bit (srdy) 0: p1 3 pin operates as ordinary i/o pin 1: p1 3 pin operates as s rdy1 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o1 enable bit (sioe) 0: serial i/o1 disabled (pins p1 0 to p1 3 operate as ordinary i/o pins) 1: serial i/o1 enabled (pins p1 0 to p1 3 operate as serial i/o pins) b7 uart control register character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p1 1 /t x d 1 p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return 1 when read) b0 (sio1sts : address 0019 16 , initial value: 00 16 ) (sio1con : address 001a 16 , initial value: 00 16 ) (uartcon : address 001b 16 , initial value: e0 16 ) functional description
hardware 7540 group user s manual 1-39 serial i/o2 the serial i/o2 function can be used only for clock synchronous serial i/o. for clock synchronous serial i/o2 the transmitter and the receiver must use the same clock. when the internal clock is used, transfer is started by a write signal to the serial i/o2 register. note: serial i/o2 can be used in the following cases; (1) serial i/o1 is not used, (2) serial i/o1 is used as uart and brg output divided by 16 is selected as the synchronized clock. [serial i/o2 control register] sio2con the serial i/o2 control register contains 8 bits which control vari- ous serial i/o functions. set 0 to bit 3 to receive. at reception, clear bit 7 to 0 by writing a dummy data to the se- rial i/o2 register after completion of shift. fig. 35 structure of serial i/o2 control registers fig. 36 block diagram of serial i/o2 internal synchronous clock selection bits 000 : f(x in )/8 001 : f(x in )/16 010 : f(x in )/32 011 : f(x in )/64 110 : f(x in )/128 111 : f(x in )/256 b7 b0 not used (returns 0 when read) transfer direction selection bit 0 : lsb first 1 : msb first s clk2 pin selection bit 0 : external clock (s clk2 is an input) 1 : internal clock (s clk2 is an output) transmit / receive shift completion flag 0 : shift in progress 1 : shift completed note : when using it as a s data input, set the port p1 3 direction register to 0 . serial i/o2 control register (sio2con: address 0030 16 , initila value: 00 16 ) s data2 pin selection bit (note) 0 : i/o port / s data2 input 1 : s data2 output 1 0 0 1 0 1 1/8 1/16 1/32 1/64 1/128 1/256 x in data bus serial i/o2 interrupt request s data2 pin selection bit serial i/o counter 2 (3) serial i/o shift register 2 (8) s clk2 pin selection bit internal synchronous clock selection bits divider p1 2 /s clk2 p1 3 /s data2 p1 2 latch s clk2 pin selection bit s clk p1 3 latch s data2 pin selection bit functional description
hardware 1-40 7540 group user s manual serial i/o2 operation by writing to the serial i/o2 register (address 0031 16 ) the serial i/ o2 counter is set to 7 . after writing, the s data2 pin outputs data every time the transfer clock shifts from h to l . and, as the transfer clock shifts from l to h , the s data2 pin reads data, and at the same time the contents of the serial i/o2 register are shifted by 1 bit. when the internal clock is selected as the transfer clock source, the following operations execute as the transfer clock counts up to 8. serial i/o2 counter is cleared to 0 . transfer clock stops at an h level. interrupt request bit is set. shift completion flag is set. also, the s data2 pin is in a high impedance state after the data transfer is completed (refer to fig.37). when the external clock is selected as the transfer clock source, the interrupt request bit is set as the transfer clock counts up to 8, but external control of the clock is required since it does not stop. notice that the s data2 pin is not in a high impedance state on the completion of data transfer. also, after the receive operation is completed, the transmit/receive shift completion flag is cleared by reading the serial i/o2 register. at transmit, the transmit/receive shift completion flag is cleared and the transmit operation is started by writing to serial i/o2 regis- ter. fig. 37 serial i/o2 timing (lsb first) d 0 note : synchronous clock serial i/o2 register write signal transfer clock (note) s data2 at serial i/o2 input receive s data2 at serial i/o2 output transmit serial i/o2 interrupt request bit set transmit/receive shift completion flag set d 1 d 2 d 3 d 4 d 5 d 6 d 7 when the internal clock is selected as the transfer and the direction register of p1 3 /s data2 pin is set to the input mode, the s data2 pin is in a high impedance state after the data transfer is completed. functional description
hardware 7540 group user s manual 1-41 a-d converter the functional blocks of the a-d converter are described below. [a-d conversion register] ad the a-d conversion register is a read-only register that stores the result of a-d conversion. do not read out this register during an a- d conversion. [a-d control register] adcon the a-d control register controls the a-d converter. bit 2 to 0 are analog input pin selection bits. bit 4 is the ad conversion comple- tion bit. the value of this bit remains at 0 during a-d conversion, and changes to 1 at completion of a-d conversion. a-d conversion is started by setting this bit to 0 . [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and v ref by 1024, and outputs the divided voltages. [channel selector] the channel selector selects one of ports p2 7 /an 7 to p2 0 /an 0 , and inputs the voltage to the comparator. [comparator and control circuit] the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores its result into the a-d conversion register. when a-d conversion is completed, the con- trol circuit sets the ad conversion completion bit and the ad interrupt request bit to 1 . because the comparator is constructed linked to a capacitor, set f(x in ) to 500 khz or more during a-d con- version. fig. 38 structure of a-d control register fig. 39 structure of a-d conversion register fig. 40 block diagram of a-d converter a-d control register (adcon : address 0034 16 , initial value: 10 16 ) not used (returns 0 when read) not used (returns 0 when read) ad conversion completion bit 0 : conversion in progress 1 : conversion completed b7 b0 analog input pin selection bits 000 : p2 0 /an 0 001 : p2 1 /an 1 010 : p2 2 /an 2 011 : p2 3 /an 3 100 : p2 4 /an 4 101 : p2 5 /an 5 110 : p2 6 /an 6 (note) 111 : p2 7 /an 7 (note) note: these can be used only for 36 pin version. read 8-bit (read only address 0035 16 ) b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 (address 0035 16 ) read 10-bit (read in order address 0036 16 , 0035 16 ) b7 b0 b9 b8 (address 0036 16 ) b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 (address 0035 16 ) note: high-order 6-bit of address 0036 16 returns 0 when read. a-d control register (address 0034 16 ) channel selector a-d control circuit resistor ladder v ref comparator a-d interrupt request b7 b0 data bus 3 10 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 p2 6 /an 6 p2 7 /an 7 a-d conversion register (low-order) (address 0036 16 ) (address 0035 16 ) a-d conversion register (high-order) v ss functional description
hardware 1-42 7540 group user s manual watchdog timer the watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. the watchdog timer consists of an 8-bit watchdog timer h and an 8-bit watchdog timer l, being a 16-bit counter. standard operation of watchdog timer the watchdog timer stops when the watchdog timer control regis- ter (address 0039 16 ) is not set after reset. writing an optional value to the watchdog timer control register (address 0039 16 ) causes the watchdog timer to start to count down. when the watchdog timer h underflows, an internal reset occurs. accord- ingly, it is programmed that the watchdog timer control register (address 0039 16 ) can be set before an underflow occurs. when the watchdog timer control register (address 0039 16 ) is read, the values of the high-order 6-bit of the watchdog timer h, stp instruction disable bit and watchdog timer h count source se- lection bit are read. initial value of watchdog timer by a reset or writing to the watchdog timer control register (ad- dress 0039 16 ), the watchdog timer h is set to ff 16 and the watchdog timer l is set to ff 16 . operation of watchdog timer h count source selection bit a watchdog timer h count source can be selected by bit 7 of the watchdog timer control register (address 0039 16 ). when this bit is 0 , the count source becomes a watchdog timer l underflow sig- nal. the detection time is 131.072 ms at f(x in )=8 mhz. when this bit is 1 , the count source becomes f(x in )/16. in this case, the detection time is 512 0 after reset. operation of stp instruction disable bit when the watchdog timer is in operation, the stp instruction can be disabled by bit 6 of the watchdog timer control register (ad- dress 0039 16 ). when this bit is 0 , the stp instruction is enabled. when this bit is 1 , the stp instruction is disabled, and an inter- nal reset occurs if the stp instruction is executed. once this bit is set to 1 , it cannot be changed to 0 by program. this bit is cleared to 0 after reset. fig. 41 block diagram of watchdog timer fig. 42 structure of watchdog timer control register x in data bus 0 1 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) write "ff 16 " to the watchdog timer control register internal reset reset watchdog timer l (8) stp instruction write ff 16 to the watchdog timer control register watchdog timer control register (wdtcon: address 0039 16 , initial value: 3f 16 ) watchdog timer h (read only for high-order 6-bit) stp instruction disable bit 0 : stp instruction enabled 1 : stp instruction disabled watchdog timer h count source selection bit 0 : watchdog timer l underflow 1 : f(x in )/16 b7 b0 functional description
hardware 7540 group user s manual 1-43 reset circuit the microcomputer is put into a reset status by holding the re- set pin at the l level for 2 h level. the program starts from the address having the contents of address fffd 16 as high-order address and the con- tents of address fffc 16 as low-order address. in the case of f( fig. 43 example of reset circuit fig. 44 timing diagram at reset (note) 0.2 v cc 0 v 0 v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage vcc = 2.2 v data address 8-13 clock cycles reset address from the vector table 1 : a built-in ring oscillator applies about ring 2 mhz, 250 khz frequency clock at average of vcc = 5 v. 2 : the mark ? means that the address is changeable depending on the previous state. 3 : these are all internal signals except reset. notes ?? fffc fffd ad h ,ad l ??? ?? ad l ad h ??? clock from built-in ring oscillator ring functional description
hardware 1-44 7540 group user s manual fig. 45 internal status of microcomputer at reset prescaler 1 timer 1 one-shot start register timer x mode register prescaler x timer x timer count source set register serial i/o2 control register a-d control register misrg watchdog timer control register interrupt edge selection register cpu mode register interrupt request register 1 interrupt control register 1 processor status register program counter (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) contents of address fffc 16 (pc h ) (pc l ) ff 16 01 16 00 16 00 16 ff 16 ff 16 00 16 00 16 10 16 00 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 0030 16 0034 16 0038 16 0039 16 003a 16 003b 16 003c 16 003e 16 (ps) note x : undefined contents of address fffd 16 0011 1111 00 16 00 16 00 16 1000 0000 xxxx x1xx port p0 direction register port p1 direction register port p2 direction register port p3 direction register pull-up control register (1) (2) (3) (4) (5) register contents 00 16 00 16 00 16 00 16 0001 16 0003 16 0005 16 0007 16 0016 16 serial i/o1 control register uart control register (8) (9) serial i/o1 status register (7) 001a 16 001b 16 00 16 1110 0000 0019 16 1000 0000 xx x 0 0000 address port p1p3 control register (6) 0017 16 00 16 timer a mode register timer a (low-order) timer a (high-order) 00 16 ff 16 ff 16 001d 16 001e 16 001f 16 timer y, z mode register prescaler y timer y secondary 00 16 ff 16 ff 16 0020 16 0021 16 0022 16 timer y primary timer y, z waveform output control register prescaler z ff 16 00 16 ff 16 0023 16 0024 16 0025 16 timer z secondary ff 16 0026 16 timer z primary ff 16 0027 16 (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) serial i/o2 register 00 16 0031 16 interrupt request register 2 003d 16 00 16 interrupt control register 2 003f 16 00 16 (37) (38) (39) (40) functional description
hardware 7540 group user s manual 1-45 fig. 46 external circuit of ceramic resonator fig. 47 external circuit of rc oscillation x i n c o u t c in x o u t m 3 7 5 4 0 r d x i n x o u t c r m 3 7 5 4 0 fig. 48 external clock input circuit x in x o u t e x t e r n a l o s c i l l a t i o n c i r c u i t v cc v ss o p e n m37540 x i n x o u t m 3 7 5 4 0 open fig. 49 processing of x in and x out pins at ring oscillator op- eration clock generating circuit an oscillation circuit can be formed by connecting a resonator be- tween x in and x out , and an rc oscillation circuit can be formed by connecting a resistor and a capacitor. use the circuit constants in accordance with the resonator manufacturer's recommended values. (1) ring oscillator operation when the mcu operates by the ring oscillator for the main clock, connect x in pin to v ss and leave x out pin open. the clock frequency of the ring oscillator depends on the supply voltage and the operation temperature range. be careful that variable frequencies when designing application products. (2) ceramic resonator when the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins x in and x out at the shortest distance. a feedback resistor is built in be- tween pins x in and x out . (3) rc oscillation when the rc oscillation is used for the main clock, connect the x in pin and x out pin to the external circuit of resistor r and the capacitor c at the shortest distance. the frequency is affected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. (4) external clock when the external signal clock is used for the main clock, connect the x in pin to the clock source and leave x out pin open. select ceramic resonance by setting 0 to the oscillation mode selection bit of cpu mode register (address 003b 16 ). externally connect a damping resistor rd de- pending on the oscillation frequency. (a feedback resistor is built-in.) use the resonator manufacturer s recom- mended value because constants such as ca- pacitance depend on the resonator. note: connect the external circuit of resistor r and the capacitor c at the shortest distance. the frequency is af- fected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. note: the clock frequency of the ring oscillator depends on the supply voltage and the operation temperature range. be careful that variable fre- quencies and obtain the sufficient margin. note: functional description
hardware 1-46 7540 group user s manual oscillation stop detection circuit (note) the oscillation stop detection circuit is used for reset occurrence when a ceramic resonator or an oscillation circuit stops by discon- nection. when internal reset occurs, reset because of oscillation stop can be detected by setting 1 to the oscillation stop detection status bit. also, when using the oscillation stop detection circuit, a built-in ring oscillator is required. figure 53 shows the state transition. note: the oscillation stop detection circuit is not included in the emulator mcu m37540rss . fig. 50 structure of misrg misrg(address 0038 16 , initial value: 00 16 ) b7 b0 oscillation stabilization time set bit after release of the stp instruction 0: set 01 16 in timer1, and ff 16 in prescaler 1 automatically 1: not set automatically ceramic or rc oscillation stop detection function active bit 0: detection function inactive 1: detection function active reserved bits (return 0 when read) (do not write 1 to these bits) not used (return 0 when read) oscillation stop detection status bit 0: oscillation stop not detected 1: oscillation stop detected (1) oscillation control ?stop mode when the stp instruction is executed, the internal clock h level and the x in oscillator stops. at this time, timer 1 is set to 01 16 and prescaler 1 is set to ff 16 when the oscillation sta- bilization time set bit after release of the stp instruction is 0 . on the other hand, timer 1 and prescaler 1 are not set when the above bit is 1 . accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(x in )/16 is forcibly connected to the input of prescaler 1. when an external interrupt is accepted, oscillation is restarted but the internal clock h until timer 1 underflows. as soon as timer 1 underflows, the internal clock l level to the reset pin while oscillation becomes stable. also, the stp instruction cannot be used while cpu is operating by a ring oscillator. ?wait mode if the wit instruction is executed, the internal clock h level, but the oscillator does not stop. the internal clock re- starts if a reset occurs or when an interrupt is received. since the oscillator does not stop, normal operation can be started immedi- ately after the clock is restarted. to ensure that interrupts will be received to release the stp or wit state, interrupt enable bits must be set to 1 before the stp or wit instruction is executed. notes on clock generating circuit for use with the oscillation stabilization set bit after release of the stp instruction set to 1 , set values in timer 1 and prescaler 1 af- ter fully appreciating the oscillation stabilization time of the oscillator to be used. switch of ceramic and rc oscillations after releasing reset the operation starts by starting a built-in ring oscillator. then, a ceramic oscillation or an rc oscillation is se- lected by setting bit 5 of the cpu mode register. double-speed mode when a ceramic oscillation is selected, a double-speed mode can be used. do not use it when an rc oscillation is selected. cpu mode register bits 5, 1 and 0 of cpu mode register are used to select oscillation mode and to control operation modes of the microcomputer. in or- der to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing re- set. after rewriting it is disable to write any data to the bit. (the emulator mcu m37540rss is excluded.) also, when the read-modify-write instructions (seb, clb) are ex- ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. clock division ratio, x in oscillation control, ring oscillator control the state transition shown in fig. 52 can be performed by setting the clock division ratio selection bits (bits 7 and 6), x in oscillation control bit (bit 4), ring oscillator oscillation control bit (bit 3) of cpu mode register. be careful of notes on use in fig. 52. functional description
hardware 7540 group user? manual 1-47 fig. 51 block diagram of internal clock generating circuit (for ceramic resonator) fig. 52 block diagram of internal clock generating circuit (for rc oscillation) functional description s r q s r q 1/2 r s q r f 1 / 4 1 / 2 wit instruction s t p i n s t r u c t i o n timing (internal clock) s t p i n s t r u c t i o n interrupt request reset interrupt disable flag l h i g h - s p e e d m o d e m i d d l e - s p e e d m o d e prescaler 1 t i m e r 1 main clock division ratio selection bit d o u b l e - s p e e d m o d e r i n g o s c i l l a t o r m o d e r i n g o s c i l l a t o r r i n g x o u t x i n 1 / 8 main clock division ratio selection bit middle-, high-, low-speed mode r i n g o s c i l l a t o r m o d e reset s r q s r q 1/2 r s q 1/4 1 / 2 wit instruction stp instruction timing (internal clock) stp instruction i n t e r r u p t r e q u e s t reset i n t e r r u p t d i s a b l e f l a g l h i g h - s p e e d m o d e m i d d l e - s p e e d m o d e prescaler 1 t i m e r 1 main clock division ratio selection bit double-speed mode ring oscillator mode r i n g o s c i l l a t o r r i n g x o u t x i n delay 1/8 main clock division ratio selection bit middle-, high-, low-speed mode r i n g o s c i l l a t o r m o d e r e s e t
hardware 1-48 7540 group user s manual fig. 53 state transition s t o p m o d e wait mode w i t i n s t r u c t i o n o s c i l l a t i o n s t o p d e t e c t i o n c i r c u i t v a l i d c p u m 4 t o s t a t e 2 a f t e r s t a b i l i z i n g x i n o s c i l l a t i o n . ( 3 ) i n o p e r a t i o n c l o c k s o u r c e = r i n g o s c i l l a t o r , t h e m i d d l e - s p e e d m o d e i s s e l e c t e d f o r t h e c p u c l o c k d i v i s i o n r a t i o . ( 4 ) w h e n t h e s t a t e t r a n s i t i o n s t a t e 2 c p u m 7 6 n o p i n s t r u c t i o n c p u m 4 ? ? ? o p e r a t i o n c l o c k s o u r c e : f (x i n ) ( n o t e 1 ) f (x i n ) o s c i l l a t i o n e n a b l e d r i n g o s c i l l a t o r e n a b l e d s t a t e 3 o p e r a t i o n c l o c k s o u r c e : r i n g o s c i l l a t o r ( n o t e 3 ) f ( x i n ) o s c i l l a t i o n e n a b l e d r i n g o s c i l l a t o r e n a l b e d functional description
hardware 7540 group user s manual 1-49 notes on programming processor status register the contents of the processor status register (ps) after reset are undefined except for the interrupt disable flag i which is 1 . after reset, initialize flags which affect program execution. in particular, it is essential to initialize the t flag and the d flag because of their effect on calculations. interrupts the contents of the interrupt request bit do not change even if the bbc or bbs instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. for executing the instruction for the changed contents, execute one instruction before executing the bbc or bbs instruction. decimal calculations for calculations in decimal notation, set the decimal mode flag d to 1 , then execute the adc instruction or sbc instruction. in this case, execute sec instruction, clc instruction or cld in- struction after executing one instruction before the adc instruction or sbc instruction. in the decimal mode, the values of the n (negative), v (overflow) and z (zero) flags are invalid. ports the values of the port direction registers cannot be read. that is, it is impossible to use the lda instruction, memory opera- tion instruction when the t flag is 1 , addressing mode using direction register values as qualifiers, and bit test instructions such as bbc and bbs. it is also impossible to use bit operation instructions such as clb and seb and read/modify/write instructions of direction registers for calculations such as ror. for setting direction registers, use the ldm instruction, sta in- struction, etc. a-d conversion do not execute the stp instruction during a-d conversion. instruction execution timing the instruction execution time can be obtained by multiplying the frequency of the internal clock ?
hardware 1-50 7540 group user? manual notes on peripheral functions interrupt when setting the followings, the interrupt request bit may be set to ?? ?hen switching external interrupt active edge related register: interrupt edge selection register (address 003a 16 ) timer x mode register (address 2b 16 ) timer a mode register (address 1d 16 ) when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ??(disabled). ? set the interrupt edge select bit (active edge switch bit). ? set the corresponding interrupt request bit to ??after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ??(enabled). timers ?when n (0 to 255) is written to a timer latch, the frequency divi- sion ratio is 1/(n+1). ?when a count source of timer x, timer y or timer z is switched, stop a count of timer x. timer a cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. when this bit is ?? the cntr 1 interrupt request bit is set to ??at the falling edge of the cntr 1 pin input signal. when this bit is ?? the cntr 1 interrupt request bit is set to ??at the rising edge of the cntr 1 pin input signal. however, in the pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. timer x cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the falling edge of cntr 0 pin input signal. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the rising edge of cntr 0 pin input signal. timer y: programmable generation waveform mode ?count set value in the programmable waveform generation mode, values of tys, expyp, and expys are valid by writing to typ because the set- ting to them is executed all at once by writing to typ. even when changing typ is not required, write the same value again. ?write timing to typ in the programmable waveform generation mode, when the set- ting value is changed while the waveform is output, set by software in order not to execute the writing to typ and the timing of timer underflow during the secondary interval simultanesously. ?usage of waveform extension function the waveform extension function by the timer y waveform exten- sion control bit can be used only when ?0 16 ?is set to prescaler y. when the value other than ?0 16 ?is set to prescaler y, be sure to set ??to expyp and expys. ?timer y write mode when using this mode, be sure to set ??to the timer y write con- trol bit to select ?rite to latch only? timer y can stop counting by setting ??to the timer y count stop bit in any mode. also, when timer y underflows, the timer y interrupt request bit is set to ?? timer y reloads the value of latch when counting is stopped by the timer y count stop bit. (when timer is read out while timer is stopped, the value of latch is read. the value of timer can be read out only while timer is operating.) timer z: programmable waveform generation mode ?count set value in the programmable waveform generation mode, values of tzs, expzp, and expzs are valid by writing to tzp because the set- ting to them is executed all at once by writing to tzp. even when changing tzp is not required, write the same value again. ?write timing to tzp in the programmable waveform generation mode, when the set- ting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer underflow during the secondary interval simultanesously. ?usage of waveform extension function the waveform extension function by the timer z waveform exten- sion control bit can be used only when ?0 16 ?is set to prescaler z. when the value other than ?0 16 ?is set to prescaler z, be sure to set ??to expzp and expzs. also, when the timer y underflow is selected as the count source, the waveform extension function cannot be used. ?timer z write mode when using this mode, be sure to set ??to the timer z write con- trol bit to select ?rite to latch only? notes on peripheral functions
hardware 7540 group user s manual 1-51 count set value in the programmable one-shot generation mode, the value of expzp becomes valid by writing to tzp. even when changing tzp is not required, write the same value again. write timing to tzp in the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer un- derflow simultanesously. usage of waveform extension function the waveform extension function by the timer z waveform exten- sion control bit can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp. also, when the timer y underflow is selected as the count source, the waveform extension function cannot be used. timer z write mode when using this mode, be sure to set 1 to the timer z write con- trol bit to select write to latch only . count set value in the programmable wait one-shot generation mode, values of tzs, expzp and expzs are valid by writing to tzp. even when changing tzp is not required, write the same value again. write timing to tzp in the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by soft- ware in order not to execute the writing to tzp and the timing of timer underflow during the secondary interval simultanesously. usage of waveform extension function the waveform extension function by the timer z waveform exten- sion control bit can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp and expzs. also, when the timer y underflow is selected as the count source, the waveform extension function cannot be used. timer z write mode when using this mode, be sure to set 1 to the timer z write con- trol bit to select write to latch only . timer z can stop counting by setting 1 to the timer z count stop bit in any mode. also, when timer z underflows, the timer z interrupt request bit is set to 1 . timer z reloads the value of latch when counting is stopped by the timer z count stop bit. (when timer is read out while timer is stopped, the value of latch is read. the value of timer can be read out only while timer is operating.) serial i/o interrupt when setting the transmit enable bit to 1 , the serial i/o transmit interrupt request bit is automatically set to 1 . when not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ? 0 (disabled). ? 1 . ? 0 after 1 or more instructions have been executed. ? 1 (enabled). i/o pin function when serial i/o1 is enabled. the functions of p1 2 and p1 3 are switched with the setting values of a serial i/o1 mode selection bit and a serial i/o1 synchronous clock selection bit as follows. (1) serial i/o1 mode selection bit 1 : clock synchronous type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit 0 : p1 2 pin turns into an output pin of a synchronous clock. 1 : p1 2 pin turns into an input pin of a synchronous clock. setup of a srdy1 output enable bit (srdy) 0 : p1 3 pin can be used as a normal i/o pin. 1 : p1 3 pin turns into a srdy output pin. (2) serial i/o1 mode selection bit 0 : clock asynchronous (uart) type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit 0 : p1 2 pin can be used as a normal i/o pin. 1 : p1 2 pin turns into an input pin of an external clock. when clock asynchronous (uart) type serial i/o is selected, it is p1 3 pin. it can be used as a normal i/o pin.
hardware 1-52 7540 group user s manual 1 , set values in timer 1 and prescaler 1 af- ter fully appreciating the oscillation stabilization time of the oscillator to be used. switch of ceramic and rc oscillations after releasing reset the operation starts by starting a built-in ring oscillator. then, a ceramic oscillation or an rc oscillation is se- lected by setting bit 5 of the cpu mode register. double-speed mode when a ceramic oscillation is selected, a double-speed mode can be used. do not use it when an rc oscillation is selected. cpu mode register bits 5, 1 and 0 of cpu mode register are used to select oscillation mode and to control operation modes of the microcomputer. in or- der to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing re- set. after rewriting it is disable to write any data to the bit. (the emulator mcu m37540rss is excluded.) also, when the read-modify-write instructions (seb, clb) are ex- ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. clock division ratio, x in oscillation control, ring oscillator control the state transition shown in fig. 53 can be performed by setting the clock division ratio selection bits (bits 7 and 6), x in oscillation control bit (bit 4), ring oscillator oscillation control bit (bit 3) of cpu mode register. be careful of notes on use in fig. 53. notes on peripheral functions
hardware 7540 group user s manual 1-53 data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom order confirmation form * 2.mark specification form * 3.data to be written to rom, in eprom form (three identical cop- ies) or one floppy disk. data required for rom programming orders the following are necessary when ordering a one time prom production: 1.rom programming order confirmation form * 2.mark specification form * 3.data to be written to rom, in eprom form (three identical cop- ies) or one floppy disk. * for the mask rom confirmation rom programming order confir- mation and the mark specifications, refer to the renesas technology corp homepage (http://www.renesas.com/en/rom). rom programming method the built-in prom of the blank one time prom version can be read or programmed with a general-purpose prom programmer using a special programming adapter. set the address of prom programmer in the user rom area. the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 54 is recommended to verify programming. package 32p4b 32p6u-a 36p2r-a name of programming adapter pca7435spg02 pca7435gpg03 pca7435fpg02 table 7 special programming adapter fig. 54 programming and testing of one time prom version programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. caution: data required for mask orders/data required for rom programming orders/ rom programming method
hardware 1-54 7540 group user s manual functional description supplement interrupt 7540 group permits interrupts on the 14 sources for 42-pin version, 13 sources for 36-pin version and 12 sources for 32-pin version. it is vector interrupts with a fixed priority system. accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. this priority is determined by hardware, but variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. for interrupt sources, vector addresses and interrupt priority, refer to table 8. table 8 interrupt sources, vector addresses and interrupt priority functional description supplement vector addresses (note 1) high-order priority low-order interrupt request generating conditions remarks interrupt source fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 note 1: vector addressed contain internal jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. 3: it is an interrupt which can use only for 36 pin version. non-maskable valid only when serial i/o1 is selected valid only when serial i/o1 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (valid at falling) external interrupt (active edge selectable) external interrupt (active edge selectable) stp release timer underflow non-maskable software interrupt at reset input at completion of serial i/o1 data receive at completion of serial i/o1 transmit shift or when transmit buffer is empty at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at falling of conjunction of input logical level for port p0 (at input) at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at timer x underflow at timer y underflow at timer z underflow at timer a underflow at completion of transmit/receive shift at completion of a-d conversion at timer 1 underflow not available at brk instruction execution 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 reset (note 2) serial i/o1 receive serial i/o1 transmit int 0 int 1 (note 3) key-on wake-up cntr 0 cntr 1 timer x timer y timer z timer a serial i/o2 a-d conversion timer 1 reserved area brk instruction
hardware 7540 group user s manual 1-55 timing after interrupt the interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. figure 55 shows a timing chart after an interrupt occurs, and figure 56 shows the time up to execution of the interrupt processing routine. fig. 55 timing chart after an interrupt occurs fig. 56 time up to execution of the interrupt processing routine functional description supplement : cpu operation code fetch cycle : vector address of each interrupt : jump destination address of each interrupt : 00 16 or 01 16 sync b l , b h a l , a h sps data bus not used pc h pc l ps a l a h address bus s , sps s-2 , sps s-1, sps pc b l b h a l , a h sync rd wr
hardware 1-56 7540 group user s manual a-d converter a-d conversion is started by setting ad conversion completion bit to 0. during a-d conversion, internal operations are performed as follows. 1. after the start of a-d conversion, a-d conversion register goes to 00 16 . 2. the highest-order bit of a-d conversion register is set to 1, and the comparison voltage vref is input to the comparator. then, vref is compared with analog input voltage v in . 3. as a result of comparison, when vref < v in , the highest-order bit of a-d conversion register be- comes 1. when vref > v in , the highest-order bit becomes 0. by repeating the above operations up to the lowest- order bit of the a-d conversion register, an analog value converts into a digital value. a-d conversion completes at 122 clock cycles (20.34 1. relative formula for a reference voltage v ref of a-d converter and vref when n = 0 vref = 0 when n = 1 to 1023 vref = ? ? ? ? ? ? ?? ? ???? ? ? ?
hardware 7540 group user s manual 1-57 figure 56 shows a-d conversion equivalent circuit, and figure 57 shows a-d conversion timing chart. fig. 57 a-d conversion equivalent circuit fig. 58 a-d conversion timing chart functional description supplement ani (i=0 to 7: 36-pin version i=0 to 5: 32-pin version) c1 12 pf(typical) notes 1: this is a parasitic diode. 2: only the selected analog input pin is turned on. c2 1.5 pf(typical) chopper amp. a-d control circuit typical voltage generation circuit switch tree, ladder resistor 1.5 k ?
chapter 2 application 2.1 i/o port 2.2 timer a 2.3 timer 1 2.4 timer x 2.5 timer y and timer z 2.6 serial i/o1 2.7 serial i/o2 2.8 a-d converter 2.9 reset
7540 group user? manual 2-2 application 2.1 i/o port 2.1 i/o port this paragraph explains the registers setting method and the notes relevant to the i/o ports. 2.1.1 memory map fig. 2.1.1 memory map of registers relevant to i/o port 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0016 16 0017 16 pull-up control register (pull) port p1p3 control register (p1p3c) 003a 16 interrupt edge selection register (intedge) 003c 16 interrupt request register 1 (ireq1) 003e 16 interrupt control register 1 (icon1) port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d)
7540 group user s manual application 2-3 2.1 i/o port 2.1.2 relevant registers fig. 2.1.2 structure of port pi (i = 0, 2, 3) port pi b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi 0 port pi 1 port pi 2 port pi 3 port pi 4 port pi 5 port pi 6 port pi 7 in output mode write read port latch in input mode write : port latch read : value of pins port pi (pi) (i = 0, 2, 3) [address : 00 16 , 04 16 , 06 16 ] ? ? ? ? ? ? ? ? note: the 32-pin package versions have nothing to be allocated for the following: bits 6 and 7 of port p2 bits 5 and 6 of port p3. fig. 2.1.3 structure of port p1 port p1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p1 0 port p1 1 port p1 2 port p1 3 port p1 4 in output mode write read port latch in input mode write : port latch read : value of pins port p1 (p1) [address : 02 16 ] ? ? ? ? ? ? ? ? ?? ?? ?? nothing is allocated for these bits. when these bits are read out, the values are undefined.
7540 group user s manual 2-4 application 2.1 i/o port fig. 2.1.4 structure of port pi direction register (i = 0, 2, 3) port pi direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi direction register 0 0 0 0 0 0 0 0 port pi direction register (pid) (i = 0, 2, 3) [address : 01 16 , 05 16 , 07 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode ? ? ? ? ? ? ? ? note: the 32-pin package versions have nothing to be allocated for the following: bits 6 and 7 of p2d bits 5 and 6 of p3d. fig. 2.1.5 structure of port p1 direction register port p1 direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p1 direction register 0 0 0 0 0 ? ? ? port p1 direction register (p1d) [address : 03 16 ] 0 : port p1 0 input mode 1 : port p1 0 output mode 0 : port p1 1 input mode 1 : port p1 1 output mode 0 : port p1 2 input mode 1 : port p1 2 output mode 0 : port p1 3 input mode 1 : port p1 3 output mode 0 : port p1 4 input mode 1 : port p1 4 output mode ? ? ? ? ? ? ? ? nothing is allocated for these bits. when these bits are read out, the values are undefined. ? ? ?
7540 group user s manual application 2-5 2.1 i/o port fig. 2.1.6 structure of pull-up control register pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name p0 0 pull-up control bit 0 0 0 0 0 0 0 0 pull-up control register (pull) [address : 16 16 ] 0 : pull-up off 1 : pull-up on notes 1: pins set to output are disconnected from the pull-up control. 2: keep setting the p3 5 , p3 6 pull-up control bit to 1 (initial value: 0) for the 32-pin package versions. p0 1 pull-up control bit 0 : pull-up off 1 : pull-up on p0 2 , p0 3 pull-up control bit 0 : pull-up off 1 : pull-up on p0 4 p0 7 pull-up control bit 0 : pull-up off 1 : pull-up on p3 0 p3 3 pull-up control bit 0 : pull-up off 1 : pull-up on p3 4 pull-up control bit 0 : pull-up off 1 : pull-up on p3 5 , p3 6 pull-up control bit 0 : pull-up off 1 : pull-up on p3 7 pull-up control bit 0 : pull-up off 1 : pull-up on fig. 2.1.7 structure of port p1p3 control register port p1p3 control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name p3 7 /int 0 input level selection bit 0 0 0 0 0 0 0 0 port p1p3 control register (p1p3c) [address : 17 16 ] 0 : cmos level 1 : ttl level p3 6 /int 1 input level selection bit ( note ) 0 : cmos level 1 : ttl level p1 0 , p1 2 ,p1 3 input level selection bit 0 : cmos level 1 : ttl level nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? ? ? ? ? note: keep setting the p3 6 /int 1 input level selection bit to 0 (initial value) for the 32-pin package version.
7540 group user s manual 2-6 application 2.1 i/o port fig. 2.1.8 structure of interrupt edge selection register fig. 2.1.9 structure of interrupt request register 1 interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt edge selection register (intedge) [address : 3a 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? ? int 0 interrupt edge selection bit int 1 interrupt edge selection bit 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active p0 0 key-on wakeup enable bit ? ? ? 0 : key-on wakeup enabled 1 : key-on wakeup disabled interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 1 (ireq1) [address : 3c 16 ] serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued cntr 0 interrupt request bit cntr 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued int 0 interrupt request bit int 1 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued key-on wake up interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? timer x interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ?
7540 group user s manual application 2-7 2.1 i/o port fig. 2.1.10 structure of interrupt control register 1 interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 1 (icon1) [address : 3e 16 ] serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled cntr 0 interrupt enable bit cntr 1 interrupt enable bit int 0 interrupt enable bit int 1 interrupt enable bit key-on wake up interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer x interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 2.1.3 application example of key-on wake up (1) outline : the built-in pull-up resistor is used. specifications: system is returned from the wait mode when the key-on wakeup interrupt occurs by input of the falling edge to port p0i. note: only the falling edge is active for the key-on wakeup interrupt. figure 2.1.11 shows an example of application circuit, and figure 2.1.12 shows an example of control procedure. fig. 2.1.11 example of application circuit 7 5 4 0 g r o u p p0i(i:0 to 3) k e y o n p0 3 p 0 2 p0 1 p 0 0
7540 group user s manual 2-8 application 2.1 i/o port fig. 2.1.12 example of control procedure (1) key on key-on wakeup interrupt processing r t i s e t p u l l - u p c o n t r o l r e g i s t e r p u l l ( a d d r e s s 1 6 1 6 ) 111 p 0 0 p u l l - u p o n p 0 1 p u l l - u p o n p 0 2 , p 0 3 p u l l - u p o n s e t i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r i n t e d g e ( a d d r e s s 3 a 1 6 ) 0 k e y - o n w a k e u p e n a b l e d set 0 to the key-on wakeup interrupt request bit. wit power-down processing r e s e t 1 0 0 0 0 x 0 0 2 c p u m ( a d d r e s s 3 b 1 6 ) c l t c l d s e i w a i t u n t i l f ( x i n ) o s c i l l a t i o n i s s t a b i l i z e d ( n o t e ) x x 0 0 0 x 0 0 2 c p u m( a d d r e s s 3 b 1 6 ) cli i n i t i a l i z a t i o n p r o c e s s i n g c o n t i n u e d s e t 1 t o t h e k e y - o n w a k e u p i n t e r r u p t e n a b l e b i t . ( k e y - o n w a k e u p i n t e r r u p t e n a b l e d ) x: this bit is not used here. set it to 0 or 1 arbitrary. note: for the concrete time, ask the oscillator manufacture.
7540 group user s manual application 2-9 2.1 i/o port processing set pull-up control register, if necessary p u l l ( a d d r e s s 1 6 1 6 ) p 0 0 p u l l - u p o n / o f f p 0 1 p u l l - u p o n / o f f p 0 2 , p 0 3 p u l l - u p o n / o f f p 0 4 p 0 7 p u l l - u p o n / o f f r t i cli intedge(address 3a 16 ) 0 r e s e t sei cld clt cpum(address 3b 16 ) 10000x00 2 wait until f(x in ) oscillation is stabilized ( note 1 ) cpum(address 3b 16 ) xx000x00 2 s e t p o r t p 0 i u s i n g k e y - o n w a k e u p i n t e r r u p t t o i n p u t m o d e . s e t p o r t n o t u s i n g k e y - o n w a k e u p i n t e r r u p t t o o u t p u t m o d e . s e t i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( n o t e 2 ) k e y - o n w a k e u p e n a b l e d set 0 to the key-on wakeup interrupt request bit. i n i t i a l i z a t i o n s e t 1 t o t h e k e y - o n w a k e u p i n t e r r u p t e n a b l e b i t . ( k e y - o n w a k e u p i n t e r r u p t e n a b l e d ) x : t h i s b i t i s n o t u s e d h e r e . s e t i t t o 0 o r 1 a r b i t r a r y . notes 1: for the concrete time, ask the oscillator manufacture. 2: in this case, port p0 0 is used. key-on waleup interrupt processing routine processing fig. 2.1.13 example of control procedure (2) 2.1.4 application example of key-on wake up (2) outline : the key-on wakeup interrupt is used as the normal external interrupt. specifications: the key-on wakeup interrupt occurs by input of the falling edge to port p0i. if necessary, the built-in pull-up resistor is used. note: only the falling edge is active for the key-on wakeup interrupt. figure 2.1.13 shows an example of control procedure.
7540 group user s manual 2-10 application 2.1 i/o port 2.1.5 handling of unused pins table 2.1.1 handling of unused pins pins/ports name p0, p1, p2, p3 v ref x in x out handling set to the input mode and connect each to vcc or vss through a resistor of 1 k ? to 10 k ? . set to the output mode and open at l or h level. connect to vss (gnd). connect to v ss (gnd) when using a ring oscillator for main clock. open when using an external clock. open when using a ring oscillator for main clock.
7540 group user s manual application 2-11 2.1 i/o port 2.1.6 notes on input and output ports notes on using input and output ports are described below. (1) notes in stand-by state in stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an i/o port undefined . pull-up (connect the port to v cc ) or pull-down (connect the port to v ss ) these ports through a resistor. when determining a resistance value, note the following points: external circuit variation of output levels during the ordinary operation when using a built-in pull-up resistor, note on varied current values: when setting as an input port : fix its input level when setting as an output port : prevent current from flowing out to external. the output transistor becomes the off state, which causes the ports to be the high-impedance state. note that the level becomes undefined depending on external circuits. accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an i/o port are undefined . this may cause power source current. * 1 stand-by state : the stop mode by executing the stp instruction the wait mode by executing the wit instruction (2) modifying output data with bit managing instruction when the port latch of an i/o port is modified with the bit managing instruction* 2 , the value of the unspecified bit may be changed. the bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. accordingly, when these instructions are executed on a bit of the port latch of an i/o port, the following is executed to all bits of the port latch. as for a bit which is set for an input port : the pin state is read in the cpu, and is written to this bit after bit managing. as for a bit which is set for an output port : the bit value of the port latch is read in the cpu, and is written to this bit after bit managing. note the following : even when a port which is set as an output port is changed for an input port, its port latch holds the output data. as for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. * 2 bit managing instructions : seb , and clb instructions (3) usage for the 32-pin version ? fix the p3 5 , p3 6 pull-up control bit of the pull-up control register to 1 . ? keep the p3 6 /int 1 input level selection bit of the port p1p3 control register 0 (initial state).
7540 group user s manual 2-12 application 2.1 i/o port 2.1.7 termination of unused pins (1) terminate unused pins ? i/o ports : set the i/o ports for the input mode and connect them to v cc or v ss through each resistor of 1 k ? to 10 k ? . ports that permit the selecting of a built-in pull-up resistor can also use this resistor. set the i/ o ports for the output mode and open them at l or h . when opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. thus, the potential at these pins is undefined and the power source current may increase in the input mode. with regard to an effects on the system, thoroughly perform system evaluation on the user side. since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) termination remarks ? input ports and i/o ports : do not open in the input mode. the power source current may increase depending on the first-stage circuit. an effect due to noise may be easily produced as compared with proper termination ? and ? shown on the above. ? i/o ports : when setting for the input mode, do not connect to v cc or v ss directly. if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and v cc (or v ss ). ? i/o ports : when setting for the input mode, do not connect multiple ports in a lump to v cc or v ss through a resistor. if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. at the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins.
7540 group user? manual application 2-13 2.2 timer a 2.2 timer a this paragraph explains the registers setting method and the notes relevant to the timer a. 2.2.1 memory map 0001 16 0016 16 001d 16 001e 16 001f 16 port p0 direction register (p0d) pull-up control register (pull) timer a mode register (tam) timer a (low-order) (tal) timer a (high-order) (tah) 003c 16 003e 16 interrupt request register 1 (ireq1) interrupt control register 1 (icon1) 003a 16 interrupt edge selection register (intedge) interrupt request register 2 (ireq2) interrupt control register 2 (icon2) 003d 16 003f 16 fig. 2.2.1 memory map of registers relevant to timer a
7540 group user s manual 2-14 application 2.2 timer a 2.2.2 relevant registers fig. 2.2.2 structure of port p0 direction register port p0 direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p0 direction register 0 0 0 0 0 0 0 0 port p0 direction register (p0d) [address : 01 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode ? ? ? ? ? ? ? ? fig. 2.2.3 structure of pull-up control register pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name p0 0 pull-up control bit 0 0 0 0 0 0 0 0 pull-up control register (pull) [address : 16 16 ] 0 : pull-up off 1 : pull-up on notes 1: pins set to output are disconnected from the pull-up control. 2: keep setting the p3 5 , p3 6 pull-up control bit to 1 (initial value: 0) for the 3 2-pin package versions. p0 1 pull-up control bit 0 : pull-up off 1 : pull-up on p0 2 , p0 3 pull-up control bit 0 : pull-up off 1 : pull-up on p0 4 p0 7 pull-up control bit 0 : pull-up off 1 : pull-up on p3 0 p3 3 pull-up control bit 0 : pull-up off 1 : pull-up on p3 4 pull-up control bit 0 : pull-up off 1 : pull-up on p3 5 , p3 6 pull-up control bit 0 : pull-up off 1 : pull-up on p3 7 pull-up control bit 0 : pull-up off 1 : pull-up on
7540 group user? manual application 2-15 2.2 timer a fig. 2.2.4 structure of timer a mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw name timer a mode register (tam) [address : 1d 16 ] timer a mode register 4 6 7 0 0 0 0 0 : timer mode 0 1 : period measurement mode 1 0 : event counter mode 1 1 : pulse width hl continuously measurement mode b5 b4 5 0 timer a operating mode bits cntr 1 active edge switch bit the function depends on the operating mode. (refer to table 2.2.1) timer a count stop bit 0 : count start 1 : count stop 0 1 2 3 0 0 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? ? ? 0 0 ? timer a operating modes timer mode period measurement mode event counter mode pulse width hl continuously measurement mode cntr 1 active edge switch bit (bit 6 of address 1d 16 ) contents 0 cntr 1 interrupt request occurrence: falling edge ; no influence to timer count 1 cntr 1 interrupt request occurrence: rising edge ; no influence to timer count 0 period measurement: falling period measurement cntr 1 interrupt request occurrence: falling edge 1 period measurement: rising period measurement cntr 1 interrupt request occurrence: rising edge 0 timer a: rising edge count cntr 1 interrupt request occurrence: falling edge 1 timer a: falling edge count cntr 1 interrupt request occurrence: rising edge 0 cntr 1 interrupt request occurrence: rising edge and falling edge 1 cntr 1 interrupt request occurrence: rising edge and falling edge table 2.2.1 cntr 1 active edge switch bit function
7540 group user s manual 2-16 application 2.2 timer a fig. 2.2.5 structure of timer a register fig. 2.2.6 structure of interrupt edge selection register timer a register (low-order, high-order) b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 timer a register (low-order, high-order) (tal, tah) [address : 1e 16 , 1f 16 ] set a count value of timer a. the value set in this register is written to both timer a and timer a latch at the same time. when this register is read out, the timer a s count value is read out. notes 1: be sure to write to/read out both the low-order of timer a (tal) and the high- order of timer a (tah). 2: read the high-order of timer a (tah) first, and the high-order of timer a (tal) next. 3: write to the low-order of timer a (tal) first, and the high-order of timer a (tah) next. 4: do not write to them during read, and do not read out them during write. interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt edge selection register (intedge) [address : 3a 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? ? int 0 interrupt edge selection bit int 1 interrupt edge selection bit 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active p0 0 key-on wakeup enable bit ? ? ? 0 : key-on wakeup enabled 1 : key-on wakeup disabled
7540 group user s manual application 2-17 2.2 timer a fig. 2.2.7 structure of interrupt request register 1 fig. 2.2.8 structure of interrupt request register 2 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 1 (ireq1) [address : 3c 16 ] serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued cntr 0 interrupt request bit cntr 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued int 0 interrupt request bit int 1 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued key-on wake up interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? timer x interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ? interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 2 (ireq2) [address : 3d 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . timer y interrupt request bit timer z interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued timer a interrupt request bit serial i/o2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ad converter interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? ?
7540 group user s manual 2-18 application 2.2 timer a fig. 2.2.9 structure of interrupt control register 1 fig. 2.2.10 structure of interrupt control register 2 interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 1 (icon1) [address : 3e 16 ] serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled cntr 0 interrupt enable bit cntr 1 interrupt enable bit int 0 interrupt enable bit int 1 interrupt enable bit key-on wake up interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer x interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 2 (icon2) [address : 3f 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? timer y interrupt enable bit timer z interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled timer 1 interrupt enable bit timer a interrupt enable bit serial i/o2 interrupt enable bit ad conversion interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled ?
7540 group user s manual application 2-19 2.2 timer a 2.2.3 timer mode (1) operation description timer a counts the oscillation frequency divided by 16. each time the count clock is input, the contents of timer a is decremented by 1. when the contents of timer a reach 0000 16 , an underflow occurs at the next count clock, and the timer a latch is reloaded into timer a. the division ratio of timer a is 1/(n+1) provided that the value of timer a is n. timer a can stop counting by setting 1 to the timer a count stop bit. also, when timer a underflows, the timer a interrupt request bit is set to 1 . (2) timer mode setting method figure 2.2.11 shows the setting method for timer mode of timer a.
7540 group user s manual 2-20 application 2.2 timer a fig. 2.2.11 setting method for timer mode p r o c e s s 1 : d i s a b l e t i m e r a i n t e r r u p t . p r o c e s s 2 : s e t t i m e r a m o d e r e g i s t e r . b 7b 0 0 0 1 t i m e r a m o d e r e g i s t e r ( t a m ) [ a d d r e s s 1 d 1 6 ] p r o c e s s 3 : s e t t h e c o u n t v a l u e t o t i m e r a ( n o t e ) . s e t t h e c o u n t v a l u e t o t i m e r a ( l o w - o r d e r ) s e t t h e c o u n t v a l u e t o t i m e r a ( h i g h - o r d e r ) t i m e r a ( l o w - o r d e r ) ( t a l ) ( a d d r e s s 1 e 1 6 ) c o u n t v a l u e t i m e r a ( h i g h - o r d e r ) ( t a h ) ( a d d r e s s 1 f 1 6 ) n o t e : w r i t e b o t h r e g i s t e r s i n o r d e r o f t i m e r x ( l o w - o r d e r ) a n d t i m e r x ( h i g h - o r d e r ) f o l l o w i n g , c e r t a i n l y . p r o c e s s 4 : i n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t 0 ( n o r e q u e s t e d ) t o t h e t i m e r a i n t e r r u p t r e q u e s t b i t . b 7b 0 0 0 0 t i m e r m o d e t i m e r a c o u n t s t o p c o u n t v a l u e b 7b 0 0 i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 3 f 1 6 ] t i m e r a i n t e r r u p t d i s a b l e d b 7b 0 0 i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 3 d 1 6 ] b 7b 0 1 p r o c e s s 5 : w h e n t i m e r a i n t e r r u p t i s u s e d , s e t 1 ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r a i n t e r r u p t e n a b l e b i t . n o t i m e r a i n t e r r u p t r e q u e s t i s s u e d i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 3 f 1 6 ] t i m e r a i n t e r r u p t e n a b l e d t i m e r a m o d e r e g i s t e r ( t a m ) [ a d d r e s s 1 d 1 6 ] t i m e r a c o u n t s t a r t p r o c e s s 6 : s t a r t c o u n t i n g o f t i m e r a .
7540 group user s manual application 2-21 2.2 timer a (3) application example of timer mode outline : the input clock is divided by the timer so that the period processing is executed every 25 ms intervals. specifications : the f(x in ) = 8 mhz is divided by timer a to detect 25 ms. the timer a interrupt request is confirmed in the main routine. when 25 ms has elapsed, the period processing is executed in the timer a interrupt processing routine. operation clock: f(x in ) = 8 mhz, high-speed mode figure 2.2.12 shows an example of control procedure. fig. 2.2.12 example of control procedure s e t 0 t o t h e t i m e r a i n t e r r u p t e n a b l e b i t . ( t i m e r a i n t e r r u p t d i s a b l e d ) d 3 1 6 3 0 1 6 t i m e r a ( l o w - o r d e r ) ( a d d r e s s 1 e 1 6 ) s e t v a l u e t o t i m e r a ( n o t e s 2 , 3 ) 0 0 s e t 0 t o t h e t i m e r a i n t e r r u p t r e q u e s t b i t . c l i 0 t a m ( a d d r e s s 1 d 1 6 ) t i m e r m o d e t i m e r a c o u n t s t o p 0 s e t t i m e r a m o d e r e g i s t e r 0 1 i n i t i a l i z a t i o n r e s e t s e i c l d c l t c p u m ( a d d r e s s 3 b 1 6 ) 1 0 0 0 0 x 0 0 2 w a i t u n t i l f ( x i n ) o s c i l l a t i o n i s s t a b i l i z e d ( n o t e 1 ) c p u m ( a d d r e s s 3 b 1 6 ) 0 0 0 0 0 x 0 0 2 p r o c e s s i n g timer a interrupt processing routine p e r i o d i c p r o c e s s i n g rti t i m e r a ( h i g h - o r d e r ) ( a d d r e s s 1 f 1 6 ) s e t 1 t o t h e t i m e r a i n t e r r u p t e n a b l e b i t . ( t i m e r a i n t e r r u p t e n a b l e d ) t a m ( a d d r e s s 1 d 1 6 ) t i m e r a c o u n t s t a r t s e t t i m e r a m o d e r e g i s t e r x: this bit is not used here. set it to 0 or 1 arbitrary. n o t e s 1 : f o r t h e c o n c r e t e t i m e , a s k t h e o s c i l l a t o r m a n u f a c t u r e . 2 : w h e n s e t t i n g t h e v a l u e t o t i m e r a , s e t i n o r d e r o f l o w - o r d e r b y t e a n d h i g h - o r d e r b y t e f o l l o w i n g . 3 : 2 5 m s = 1 / 8 m h z ? 1 6 ? ( 3 0 d 3 1 6 + 1 ) timer a division ratio (fixed) t i m e r a s e t t i n g v a l u e
7540 group user s manual 2-22 application 2.2 timer a fig. 2.2.13 setting method for period measurement mode (1) 2.2.4 period measurement mode (1) operation description in the period measurement mode, the pulse period input from the p0 0 /cntr 1 pin is measured. cntr 1 interrupt request is generated at rising/falling edge of cntr 1 pin input signal. simultaneously, the value in the timer a latch is reloaded in timer a and count continues. the active edge of cntr 1 pin input signal can be selected from rising or falling by the cntr 1 active edge switch bit. the count value when trigger input from cntr 1 pin is accepted is retained until timer a is read once. timer a can stop counting by setting 1 to the timer a count stop bit. also, when timer a underflows, the timer a interrupt request bit is set to 1 . (2) period measurement mode setting method figure 2.2.13 and figure 2.2.14 show the setting method for period measurement mode of timer a. b 7b 0 0 b 7b 0 1 0 1 b7 b0 b 7b 0 0 b 7b 0 0 p r o c e s s 1 : d i s a b l e t i m e r a i n t e r r u p t a n d c n t r 1 i n t e r r u p t . i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] c n t r 1 i n t e r r u p t d i s a b l e d p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) [ a d d r e s s 0 1 1 6 ] s e t t h e p 0 0 / c n t r 1 p i n t o t h e i n p u t m o d e p r o c e s s 2 : s e t t h e c n t r 1 p i n t o t h e i n p u t m o d e . i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 3 f 1 6 ] t i m e r a i n t e r r u p t d i s a b l e d process 3: set pull-up control register. p u l l - u p c o n t r o l r e g i s t e r ( p u l l ) [ a d d r e s s 1 6 1 6 ] p 0 0 / c n t r 1 p u l l - u p c o n t r o l b i t 0 : p u l l - u p o f f 1 : p u l l - u p o n p r o c e s s 4 : s e t t i m e r a m o d e r e g i s t e r . t i m e r a m o d e r e g i s t e r ( t a m ) [ a d d r e s s 1 d 1 6 ] p e r i o d m e a s u r e m e n t m o d e c n t r 1 a c t i v e e d g e s e l e c t e d 0 : f a l l i n g p e r i o d m e a s u r e d f a l l i n g e d g e a c t i v e f o r c n t r 1 i n t e r r u p t 1 : r i s i n g p e r i o d m e a s u r e d r i s i n g e d g e a c t i v e f o r c n t r 1 i n t e r r u p t t i m e r a c o u n t s t o p
7540 group user s manual application 2-23 2.2 timer a fig. 2.2.14 setting method for period measurement mode (2) b 7b 0 1 b 7b 0 0 b 7b 0 1 b7 b0 0 b 7b 0 1 0 0 b 7b 0 1 p r o c e s s 5 : s e t t h e c o u n t v a l u e t o t i m e r a ( n o t e ) . s e t t h e i n i t i a l v a l u e t o t i m e r a ( l o w - o r d e r ) timer a (low-order) (tal) (address 1e 16 ) i n i t i a l v a l u e timer a (high-order) (tah) (address 1f 16 ) n o t e : w r i t e b o t h r e g i s t e r s i n o r d e r o f t i m e r x ( l o w - o r d e r ) a n d t i m e r x ( h i g h - o r d e r ) f o l l o w i n g , c e r t a i n l y . p r o c e s s 7 : i n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t 0 ( n o r e q u e s t e d ) t o t h e t i m e r a i n t e r r u p t r e q u e s t b i t a n d c n t r 1 i n t e r r u p t r e q u e s t b i t . interrupt request register 1 (ireq1) [address 3c 16 ] p r o c e s s 8 : w h e n t h e i n t e r r u p t i s u s e d , s e t 1 ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r a i n t e r r u p t e n a b l e b i t o r c n t r 1 i n t e r r u p t e n a b l e b i t . n o c n t r 1 i n t e r r u p t r e q u e s t i s s u e d interrupt control register 2 (icon2) [address 3f 16 ] ti mer a i nterrupt ena bl e d t i m e r a m o d e r e g i s t e r ( t a m ) [ a d d r e s s 1 d 1 6 ] t i m e r a c o u n t s t a r t p r o c e s s 9 : s t a r t c o u n t i n g o f t i m e r a . i n i t i a l v a l u e set the initial value to timer a (high-order) interrupt request register 2 (ireq2) [address 3d 16 ] n o t i m e r a i n t e r r u p t r e q u e s t i s s u e d interrupt control register 1 (icon1) [address 3e 16 ] cntr 1 i nterrupt ena bl e d interrupt edge selection register (intedge) [address 3a 16 ] k ey-on wa k eup di sa bl e d p r o c e s s 6 : i n o r d e r t o u s e t h e c n t r 1 p i n f u n c t i o n o f t h e p 0 0 / c n t r 1 p i n , d i s a b l e t h e p 0 0 k e y - o n w a k e u p f u n c t i o n .
7540 group user s manual 2-24 application 2.2 timer a (3) application example of period measurement mode outline : the phase control signal is adjusted by using the period measurement mode. specifications : the phase control signal is output to a load, and that controls the phase of a load. the period of the pulse input to the p0 0 /cntr 1 pin from the load as a feedback signal is measured. the correct of the phase control signal to the load is executed using this result. the input pulse period is set to be less than the period of timer a. when timer a underflows, the period is recognized as not corrected, and error processing is executed in the timer a interrupt processing routine. operation clock: f(x in ) = 8 mhz, high-speed mode figure 2.2.15 shows an example of a peripheral circuit, and figure 2.2.16 shows an example of control procedure. fig. 2.2.15 example of peripheral circuit load 7540 group p0 0 /cntr 1 port v ac
7540 group user s manual application 2-25 2.2 timer a fig. 2.2.16 example of control procedure ff 16 f f 1 6 set timer a mode register 0 tam(address 1d 16 ) t i m e r a c o u n t s t a r t 1 c l i 0 reset s e i c l d c l t c p u m ( a d d r e s s 3 b 1 6 ) 1 0 0 0 0 x 0 0 2 w a i t u n t i l f ( x i n ) o s c i l l a t i o n i s s t a b i l i z e d ( n o t e 1 ) c p u m ( a d d r e s s 3 b 1 6 ) 0 0 0 0 0 x 0 0 2 processing timer a interrupt processing routine error processing rti 0 t a m ( a d d r e s s 1 d 1 6 ) p e r i o d m e a s u r e m e n t m o d e r i s i n g p e r i o d m e a s u r e d r i s i n g e d g e a c t i v e f o r c n t r 1 i n t e r r u p t t i m e r a c o u n t s t o p 1 set timer a mode register 1 1 s e t p o r t p 0 0 t o t h e i n p u t m o d e . p u l l ( a d d r e s s 1 6 1 6 ) p0 0 pull-up control bit 0: pull-up off 1: pull-up on s e t p u l l - u p c o n t r o l r e g i s t e r 1 c n t r 1 i n t e r r u p t p r o c e s s i n g r o u t i n e r e a d t i m e r a ( n o t e 3 ) rti error processing at incorrect period input i n t e d g e ( a d d r e s s 3 a 1 6 ) k e y - o n w a k e u p d i s a b l e d 1 cntr 1 interrupt processing timer a interrupt processing s e t 0 t o t h e c n t r 1 i n t e r r u p t e n a b l e b i t . ( c n t r 1 i n t e r r u p t d i s a b l e d ) s e t 0 t o t h e t i m e r a i n t e r r u p t e n a b l e b i t . ( t i m e r a i n t e r r u p t d i s a b l e d ) i n i t i a l i z a t i o n x : t h i s b i t i s n o t u s e d h e r e . s e t i t t o 0 o r 1 a r b i t r a r y . n o t e s 1 : f o r t h e c o n c r e t e t i m e , a s k t h e o s c i l l a t o r m a n u f a c t u r e . 2 : w h e n s e t t i n g t h e v a l u e t o t i m e r a , s e t i n o r d e r o f l o w - o r d e r b y t e a n d h i g h - o r d e r b y t e f o l l o w i n g . 3 : w h e n r e a d i n g a v a l u e o f t i m e r a , r e a d i n o r d e r o f h i g h - o r d e r b y t e a n d l o w - o r d e r b y t e f o l l o w i n g . ti mer a (l ow-or d er ) (add ress 1 e 16 ) s e t v a l u e t o t i m e r a ( n o t e 2 ) ti mer a (hi g h -or d er ) (add ress 1 f 16 ) set interrupt edge selection register set 1 to the cntr 1 interrupt enable bit. (cntr 1 interrupt enabled) set 1 to the timer a interrupt enable bit. (timer a interrupt enabled) set 0 to the cntr 1 interrupt request bit. set 0 to the timer a interrupt request bit.
7540 group user s manual 2-26 application 2.2 timer a fig. 2.2.17 setting method for event counter mode (1) 2.2.5 event counter mode (1) operation description timer a counts signals input from the p0 0 /cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. the active edge of cntr 1 pin input signal can be selected from rising or falling by the cntr 1 active edge switch bit. timer a can stop counting by setting 1 to the timer a count stop bit. also, when timer a underflows, the timer a interrupt request bit is set to 1 . (2) event counter mode setting method figure 2.2.17 and figure 2.2.18 show the setting method for event counter mode of timer a. b 7b0 0 b 7b0 0 11 b 7b 0 b 7b0 0 b 7b0 0 p r o c e s s 1 : d i s a b l e t i m e r a i n t e r r u p t a n d c n t r 1 i n t e r r u p t . interrupt control register 1 (icon1) [address 3e 16 ] c n t r 1 i n t e r r u p t d i s a b l e d p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) [ a d d r e s s 0 1 1 6 ] s e t t h e p 0 0 / c n t r 1 p i n t o t h e i n p u t m o d e p r o c e s s 2 : s e t t h e c n t r 1 p i n t o t h e i n p u t m o d e . interrupt control register 2 (icon2) [address 3f 16 ] t i m e r a i n t e r r u p t d i s a b l e d p r o c e s s 3 : s e t p u l l - u p c o n t r o l r e g i s t e r . p u l l - u p c o n t r o l r e g i s t e r ( p u l l ) [ a d d r e s s 1 6 1 6 ] p 0 0 / c n t r 1 p u l l - u p c o n t r o l b i t 0 : p u l l - u p o f f 1 : p u l l - u p o n p r o c e s s 4 : s e t t i m e r a m o d e r e g i s t e r . t i m e r a m o d e r e g i s t e r ( t a m ) [ a d d r e s s 1 d 1 6 ] e v e n t c o u n t e r m o d e c n t r 1 a c t i v e e d g e s e l e c t e d 0 : r i s i n g p e r i o d m e a s u r e d f a l l i n g e d g e a c t i v e f o r c n t r 1 i n t e r r u p t 1 : f a l l i n g p e r i o d m e a s u r e d r i s i n g e d g e a c t i v e f o r c n t r 1 i n t e r r u p t t i m e r a c o u n t s t o p p r o c e s s 5 : s e t t h e c o u n t v a l u e t o t i m e r a ( n o t e ) . s e t t h e c o u n t v a l u e t o t i m e r a ( l o w - o r d e r ) t i m e r a ( l o w - o r d e r ) ( t a l ) ( a d d r e s s 1 e 1 6 ) c o u n t v a l u e t i m e r a ( h i g h - o r d e r ) ( t a h ) ( a d d r e s s 1 f 1 6 ) n o t e : w r i t e b o t h r e g i s t e r s i n o r d e r o f t i m e r x ( l o w - o r d e r ) a n d t h e t i m e r x ( h i g h - o r d e r ) f o l l o w i n g , c e r t a i n l y . c o u n t v a l u e s e t t h e c o u n t v a l u e t o t i m e r a ( h i g h - o r d e r )
7540 group user s manual application 2-27 2.2 timer a fig. 2.2.18 setting method for event counter mode (2) b 7b 0 1 b 7b 0 0 1 0 b 7b 0 1 b 7b 0 0 b 7b 0 0 b7 b0 1 p r o c e s s 7 : i n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t 0 ( n o r e q u e s t e d ) t o t h e t i m e r a i n t e r r u p t r e q u e s t b i t a n d c n t r 1 i n t e r r u p t r e q u e s t b i t . i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 3 c 1 6 ] process 8: when the interrupt is used, set 1 (interrupt enabled) to the timer a interrupt enable bit or cntr 1 interrupt enable bit. n o c n t r 1 i n t e r r u p t r e q u e s t i s s u e d i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 3 f 1 6 ] ti mer a i nterrupt ena bl e d t i m e r a m o d e r e g i s t e r ( t a m ) [ a d d r e s s 1 d 1 6 ] t i m e r a c o u n t s t a r t process 9: start counting of timer a. i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 3 d 1 6 ] n o t i m e r a i n t e r r u p t r e q u e s t i s s u e d interrupt control register 1 (icon1) [address 3e 16 ] cntr 1 i nterrupt ena bl e d i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) [ a d d r e s s 3 a 1 6 ] k ey-on wa k eup di sa bl e d process 6: in order to use the cntr 1 pin function of the p0 0 /cntr 1 pin, disable the p0 0 key-on wakeup function.
7540 group user s manual 2-28 application 2.2 timer a (3) application example of event counter mode outline : the frequency of the pulse which is input to the p0 0 /cntr 1 pin ( h active) is measured by the number of events in a certain period. specifications : the count source of timer a is input from the p0 0 /cntr 1 pin, and the timer a starts counting the count source. clock (f(x in ) = 8 mhz) is divided by timer x to detect 1 ms. the frequency of the pulse input to the p0 0 /cntr 1 pin is calculated by the number of events counted within 1 ms. operation clock: f(x in ) = 8 mhz, high-speed mode figure 2.2.19 shows an example of measurement method of frequency, and figure 2.2.20 shows an example of control procedure. fig. 2.2.19 example of measurement method of frequency n o t e s 1 : c o u n t e d a t f a l l i n g e d g e . 2 : f r e q u e n c y o f p u l s e i n p u t f r o m p 0 0 / c n t r 1 p i n : timer x interrupt processing routine timer a, timer x count stop timer a read timer a, timer x set again timer a, timer x count restart p0 0 /cntr 1 pin input t i m e r x i n t e r r u p t r e q u e s t b i t 1ms counted by timer a ( note 1 ) x times ( note 2 ) timer a, timer x count start khz x t i m e s 1 m s
7540 group user? manual application 2-29 2.2 timer a fig. 2.2.20 example of control procedure ( t i m e r a s e t t i n g v a l u e f f f f 1 6 ) ( t i m e r a c o u n t v a l u e ) e v e n t i n 1 m s timer x interrupt processing routine (1ms interrupt) ff 16 f f 1 6 1 0 c l i 0 reset s e i c l d c l t c p u m ( a d d r e s s 3 b 1 6 ) 1 0 0 0 0 x 0 0 2 f ( x i n ) u n t i l f ( x i n ) o s c i l l a t i o n i s s t a b i l i z e d ( n o t e 1 ) c p u m ( a d d r e s s 3 b 1 6 ) 0 0 0 0 0 x 0 0 2 processing ff 16 ff 16 1 0 1 1 1 s e t t i m e r x m o d e r e g i s t e r t x m ( a d d r e s s 2 b 1 6 ) t i m e r m o d e t i m e r x c o u n t s t o p 100 0 1 1 6 f 9 1 6 set timer count source set register tcss(address 2e 16 ) t i m e r x c o u n t s o u r c e : f ( x i n ) / 1 6 s e l e c t e d 000 txm(address 2b 16 ) 000 t x m ( a d d r e s s 2 b 1 6 ) 100 tam(address 1d 16 ) txm(address 2b 16 ) 0 1 1 0 0 00 r t i t a m ( a d d r e s s 1 d 1 6 ) 0 1 1 1 1 0 1 1 6 18 16 s e t t i m e r a m o d e r e g i s t e r t a m ( a d d r e s s 1 d 1 6 ) timer a count start t a m ( a d d r e s s 1 d 1 6 ) e v e n t c o u n t m o d e c o u n t a t f a l l i n g e d g e t i m e r a c o u n t s t o p s e t t i m e r a m o d e r e g i s t e r s e t p o r t p 0 0 t o t h e i n p u t m o d e . p u l l ( a d d r e s s 1 6 1 6 ) p 0 0 p u l l - u p c o n t r o l b i t 0 : p u l l - u p o f f 1 : p u l l - u p o n s e t p u l l - u p c o n t r o l r e g i s t e r i n t e d g e ( a d d r e s s 3 a 1 6 ) key-on wakeup disabled s e t 0 t o t h e c n t r 1 i n t e r r u p t e n a b l e b i t . ( c n t r 1 i n t e r r u p t d i s a b l e d ) s e t 0 t o t h e t i m e r a i n t e r r u p t e n a b l e b i t . ( t i m e r a i n t e r r u p t d i s a b l e d ) s e t 0 t o t h e t i m e r x i n t e r r u p t e n a b l e b i t ( t i m e r x i n t e r r u p t d i s a b l e d ) i n i t i a l i z a t i o n x : t h i s b i t i s n o t u s e d h e r e . s e t i t t o 0 o r 1 a r b i t r a r y . n o t e s 1 : f o r t h e c o n c r e t e t i m e , a s k t h e o s c i l l a t o r m a n u f a c t u r e . 2 : w h e n s e t t i n g t h e v a l u e t o t i m e r , s e t i n o r d e r o f l o w - o r d e r b y t e a n d h i g h - o r d e r b y t e f o l l o w i n g . 3 : 1 m s d e t e c t i o n = 1 / 8 m h z 1 6 ( 0 1 1 6 + 1 ) ( f 9 1 6 + 1 ) t i m e r a ( l o w - o r d e r ) ( a d d r e s s 1 e 1 6 ) set value to timer a ( note 2 ) t i m e r a ( h i g h - o r d e r ) ( a d d r e s s 1 f 1 6 ) s e t i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r set 1 to the timer x interrupt enable bit. (timer x interrupt enabled) s e t 0 t o t h e t i m e r x i n t e r r u p t r e q u e s t b i t . p resca l er x (add ress 2 c 16 ) set value to timer x ( note 3 ) t i m e r x ( a d d r e s s 2 d 1 6 ) s e t t i m e r x m o d e r e g i s t e r t i m e r x c o u n t s t a r t set timer a mode register timer a count start set timer x mode register t i m e r x c o u n t s t a r t set timer a mode register t i m e r a c o u n t s t o p set timer x mode register t i m e r x c o u n t s t o p t i m e r a ( l o w - o r d e r ) ( a d d r e s s 1 e 1 6 ) set value to timer a ( note 2 ) t i m e r a ( h i g h - o r d e r ) ( a d d r e s s 1 f 1 6 ) p r e s c a l e r x ( a d d r e s s 2 c 1 6 ) set value to timer x ( note 3 ) t i m e r x ( a d d r e s s 2 d 1 6 ) t i m e r x d i v i s i o n r a t i o t i m e r x s e t t i n g v a l u e p r e s c a l e r x s e t t i n g v a l u e
7540 group user s manual 2-30 application 2.2 timer a fig. 2.2.21 setting method for pulse width hl continuously measurement mode (1) 2.2.6 pulse width hl continuously measurement mode (1) operation description in the pulse width hl continuously measurement mode, the pulse width ( h and l levels) input to the p0 0 /cntr 1 pin is measured. cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. the count value when trigger input from the cntr 1 pin is accepted is retained until timer a is read once. timer a can stop counting by setting 1 to the timer a count stop bit. also, when timer a underflows, the timer a interrupt request bit is set to 1 . (2) pulse width hl continuously measurement mode setting method figure 2.2.21 and figure 2.2.22 show the setting method for pulse width hl continuously measurement mode of timer a. b 7b 0 0 b7 b 0 111 b7 b 0 b7 b 0 0 b 7b 0 0 p r o c e s s 1 : d i s a b l e t i m e r a i n t e r r u p t a n d c n t r 1 i n t e r r u p t . i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] cntr 1 i nterrupt di sa bl e d p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) [ a d d r e s s 0 1 1 6 ] s e t t h e p 0 0 / c n t r 1 p i n t o t h e i n p u t m o d e p r o c e s s 2 : s e t t h e c n t r 1 p i n t o t h e i n p u t m o d e . i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 3 f 1 6 ] ti mer a i nterrupt di sa bl e d p r o c e s s 3 : s e t t h e p u l l - u p c o n t r o l r e g i s t e r . p u l l - u p c o n t r o l r e g i s t e r ( p u l l ) [ a d d r e s s 1 6 1 6 ] p 0 0 / c n t r 1 p u l l - u p c o n t r o l b i t 0 : p u l l - u p o f f 1 : p u l l - u p o n p r o c e s s 4 : s e t t i m e r a m o d e r e g i s t e r . t i m e r a m o d e r e g i s t e r ( t a m ) [ a d d r e s s 1 d 1 6 ] p u l s e w i d t h h l c o n t i n u o u s l y m e a s u r e m e n t m o d e t i m e r a c o u n t s t o p p r o c e s s 5 : s e t t h e c o u n t v a l u e t o t i m e r a ( n o t e ) . s e t t h e i n i t i a l v a l u e t o t i m e r a ( l o w - o r d e r ) t i m e r a ( l o w - o r d e r ) ( t a l ) ( a d d r e s s 1 e 1 6 ) i n i t i a l v a l u e t i m e r a ( h i g h - o r d e r ) ( t a h ) ( a d d r e s s 1 f 1 6 ) n o t e : w r i t e b o t h r e g i s t e r s i n o r d e r o f t i m e r x ( l o w - o r d e r ) a n d t h e t i m e r x ( h i g h - o r d e r ) f o l l o w i n g , c e r t a i n l y . i n i t i a l v a l u e s e t t h e i n i t i a l v a l u e t o t i m e r a ( h i g h - o r d e r )
7540 group user s manual application 2-31 2.2 timer a fig. 2.2.22 setting method for pulse width hl continuously measurement mode (2) b7 b0 1 b 7b 0 1 b 7b 0 0 b 7b 0 0 b7 b0 0 11 b7 b0 1 p r o c e s s 7 : i n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t 0 ( n o r e q u e s t e d ) t o t h e t i m e r a i n t e r r u p t r e q u e s t b i t a n d c n t r 1 i n t e r r u p t r e q u e s t b i t ( n o t e ) . i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 3 c 1 6 ] process 8: when the interrupt is used, set 1 (interrupt enabled) to the timer a interrupt enable bit or cntr 1 interrupt enable bit. n o cntr 1 i nterrupt request i ssue d i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 3 f 1 6 ] t i m e r a i n t e r r u p t e n a b l e d t i m e r a m o d e r e g i s t e r ( t a m ) [ a d d r e s s 1 d 1 6 ] ti mer a count start process 9: start counting of timer a. i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 3 d 1 6 ] n o t i mer a i nterrupt request i ssue d i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] cntr 1 i nterrupt ena bl e d i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) [ a d d r e s s 3 a 1 6 ] k e y - o n w a k e u p d i s a b l e d p r o c e s s 6 : i n o r d e r t o u s e t h e c n t r 1 p i n f u n c t i o n o f t h e p 0 0 / c n t r 1 p i n , d i s a b l e t h e p 0 0 k e y - o n w a k e u p f u n c t i o n . n o t e : i n t h e p u l s e w i d t h h l c o n t i n u o u s l y m e a s u r e m e n t m o d e , t h e c n t r 1 i n t e r r u p t r e q u e s t o c c u r s a t t h e r i s i n g e d g e a n d f a l l i n g e d g e o f t h e p 0 0 / c n t r 1 p i n r e g a r d l e s s o f t h e v a l u e o f t h e p 0 0 / c n t r 1 a c t i v e e d g e s w i t c h b i t o f t h e t i m e r a m o d e r e g i s t e r .
7540 group user s manual 2-32 application 2.2 timer a (3) application example of pulse width hl continuously measurement mode outline : a telephone ringing (calling) pulse* is detected by using the pulse width hl continuously measurement mode. * signal which is sent by turning on/off (make/break) the telephone line. each country has a different standard. in this case, japanese domestic standard is adopted as an example. specifications : whether a telephone call exists or not is judged by measuring a pulse width output from the ringing signal detection circuit. f(x in )/16 (f(x in ) = 6.4 mhz) is used as the count source, and h and l pulse width of the ringing pulse are measured by using the pulse width hl continuously measurement mode. when the following conditions are satisfied, it is recognized as a normal value. when the following conditions are not satisfied, it is recognized as an unusual value. 200 ms h pulse width of ringing pulse < 1.2 s 600 ms l pulse width of ringing pulse < 2.2 s 1.0 s one period ( h pulse width + l pulse width) < 3.0 s operation clock: f(x in ) = 6.4 mhz, high-speed mode figure 2.2.23 shows an example of a peripheral circuit, and figure 2.2.24 shows an operation timing when a ringing pulse is input. figures 2.2.25 and 2.2.26 show an example of control procedure. fig. 2.2.23 example of peripheral circuit 7 5 4 0 g r o u p p 0 0 / c n t r 1 ringing pulse detection circuit telephone line fig. 2.2.24 operation timing when ringing pulse is input i n p u t s i g n a l t o p 0 0 / c n t r 1 p i n t i m e r a v a l u e t i m e r a i n t e r r u p t r e q u e s t c n t r 1 i n t e r r u p t r e q u e s t h w i d t h m e a s u r e m e n t e n d 4 t o 2 3 i n t e r r u p t s o c c u r 12 to 43 interrupts occur 1 p e r i o d 2 0 t o 5 9 i n t e r r u p t s o c c u r (1.0 s to 3.0 s) ringing duration (200 ms to 1.2 s) no ringing duration (600 ms to 2.2 s) w h e n a n o r m a l - r a n g e r i n g i n g p u l s e i s i n p u t r e l o a d reload l width measurement end
7540 group user s manual application 2-33 2.2 timer a fig. 2.2.25 example of control procedure (1) 1 f 1 6 4 e 16 1 1 c l i 0 r e s e t ti mer a di v i s i on ratio (fixed) ti mer a setting value s e i c l d c l t c p u m ( a d d r e s s 3 b 1 6 ) 1 0 0 0 0 x 0 0 2 w a i t u n t i l f ( x i n ) o s c i l l a t i o n i s s t a b i l i z e d ( n o t e 1 ) c p u m ( a d d r e s s 3 b 1 6 ) 0 0 0 0 0 x 0 0 2 1 1 1 1 n y cntr 1 interrupt occurs at rising edge and falling edge of waveform which is input to p0 0 /cntr 1 pin timer a interrupt occurs at timer a underflow (at every 50 ms) a ringing pulse exists ? (ringer flag = 1 ?) processing when a ringing pulse exists main processing m a i n p r o c e s s i n g s e t t i m e r a m o d e r e g i s t e r t a m ( a d d r e s s 1 d 1 6 ) t i m e r a c o u n t s t a r t t a m ( a d d r e s s 1 d 1 6 ) p u l s e w i d t h h l c o n t i n u o u s l y m e a s u r e m e n t m o d e t i m e r a c o u n t s t o p s e t t i m e r a m o d e r e g i s t e r s e t p o r t p 0 0 t o t h e i n p u t m o d e . p u l l ( a d d r e s s 1 6 1 6 ) p 0 0 p u l l - u p c o n t r o l b i t 0 : p u l l - u p o f f 1 : p u l l - u p o n s e t p u l l - u p c o n t r o l r e g i s t e r i n t e d g e ( a d d r e s s 3 a 1 6 ) k e y - o n w a k e u p d i s a b l e d cntr 1 interrupt processing timer a interrupt processing s e t 0 t o t h e t i m e r a i n t e r r u p t e n a b l e b i t . ( t i m e r a i n t e r r u p t d i s a b l e d ) s e t 0 t o t h e c n t r 1 i n t e r r u p t e n a b l e b i t . ( c n t r 1 i n t e r r u p t d i s a b l e d ) i n i t i a l i z a t i o n x: this bit is not used here. set it to 0 or 1 arbitrary. n o t e s 1 : f o r t h e c o n c r e t e t i m e , a s k t h e o s c i l l a t o r m a n u f a c t u r e . 2 : w h e n s e t t i n g t h e v a l u e t o t i m e r a , s e t i n o r d e r o f l o w - o r d e r b y t e a n d h i g h - o r d e r b y t e f o l l o w i n g . 3 : 5 0 m s = 1 / 6 . 4 m h z ? 1 6 ? ( 4 e 1 f 1 6 + 1 ) t i m e r a ( l o w - o r d e r ) ( a d d r e s s 1 e 1 6 ) set value to timer a ( notes 2, 3 ) t i m e r a ( h i g h - o r d e r ) ( a d d r e s s 1 f 1 6 ) s e t i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r s e t 1 t o t h e c n t r 1 i n t e r r u p t e n a b l e b i t . ( c n t r 1 i n t e r r u p t e n a b l e d ) s e t 1 t o t h e t i m e r a i n t e r r u p t e n a b l e b i t . ( t i m e r a i n t e r r u p t e n a b l e d ) set 0 to the cntr 1 interrupt request bit. set 0 to the timer a interrupt request bit.
7540 group user s manual 2-34 application 2.2 timer a fig. 2.2.26 example of control procedure (2) c n t r 1 i n t e r r u p t p r o c e s s i n g r o u t i n e t h e n u m b e r o f u n d e r f l o w i s w i t h i n t h e r a n g e ? ( 1 2 o r m o r e a n d l e s s t h a n 4 3 ) n n y y when judging that a ringing pulse exists as a result of several period measurement, set 1 to the ringing flag. n set 0 to the h width decision flag and the l width decision flag. * error processing w h e n p 0 0 / c n t r 1 = 0 , h d u r a t i o n m e a s u r i n g i s f i n i s h e d . y * error processing set 1 to the unusual value detection flag rti t h e n u m b e r o f a p e r i o d s u n d e r f l o w i s w i t h i n t h e r a n g e ? ( 2 0 o r m o r e a n d l e s s t h a n 5 9 ) timer a interrupt processing routine count the number of underflows rti set 1 to the l width decision flag. s e t 1 t o t h e h w i d t h d e c i s i o n f l a g . t h e n u m b e r o f u n d e r f l o w i s w i t h i n t h e r a n g e ? ( 4 o r m o r e a n d l e s s t h a n 2 3 ) l e v e l o f p 0 0 / c n t r 1 i s c h e c k e d , a n d w h i c h d u r a t i o n m e a s u r i n g i s f i n i s h e d i s j u d g e d . w h e n p 0 0 / c n t r 1 = 1 , l d u r a t i o n m e a s u r i n g i s f i n i s h e d .
7540 group user s manual application 2-35 2.2 timer a 2.2.7 notes on timer a notes on using timer a are described below. (1) common to all modes ? when reading timer a (high-order) (tah) and timer a (low-order) (tal), the contents of timer a is read out. read both registers in order of tah and tal following, certainly. tah and tal keep the values until they are read out. also, do not write to them during read. in this case, unexpected operation may occur. ? when writing data to tal and tah when timer a is operating or stopped, the data are set to timer a and timer a latch simultaneously. write both registers in order of tal and tah following, certainly. also, do not read them during write. in this case, unexpected operation may occur. (2) period measurement mode, event counter mode, and pulse width hl continuously measurement mode ? in order to use cntr 1 pin, set 0 to bit 0 of the port p0 direction register (input mode). ? in order to use cntr 1 pin, set 1 to bit 7 of the interrupt control register to disable the p0 0 key- on wakeup function. ? cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. when this bit is 0 , the cntr 1 interrupt request bit is set to 1 at the falling edge of the cntr 1 pin input signal. when this bit is 1 , the cntr 1 interrupt request bit is set to 1 at the rising edge of the cntr 1 pin input signal. however, in the pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit.
7540 group user? manual 2-36 application 2.3 timer 1 2.3 timer 1 this paragraph explains the registers setting method and the notes relevant to the timer 1. 2.3.1 memory map fig. 2.3.1 memory map of registers relevant to timer 1 0028 16 0029 16 prescaler 1 (pre1) timer 1 (t1) 003d 16 003f 16 interrupt request register 2 (ireq2) interrupt control register 2 (icon2) 0038 16 misrg 2.3.2 relevant registers fig. 2.3.2 structure of prescaler 1 prescaler 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 prescaler 1 (pre1) [address : 28 16 ] set a count value of prescaler 1. the value set in this register is written to both prescaler 1 and the prescaler 1 latch at the same time. when this register is read out, the count value of the prescaler 1 latch is read out.
7540 group user s manual application 2-37 2.3 timer 1 fig. 2.3.3 structure of timer 1 timer 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 timer 1 (t1) [address : 29 16 ] set a count value of timer 1. the value set in this register is written to both timer 1 and timer 1 latch at the same time. when this register is read out, the timer 1 s count value is read out. fig. 2.3.4 structure of misrg b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 misrg [address : 38 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? m i s r g o s c i l l a t i o n s t a b i l i z a t i o n t i m e s e t b i t a f t e r r e l e a s e o f t h e s t p i n s t r u c t i o n 0 0 : set 01 16 in timer 1, and ff 16 in prescaler 1 automatically 1 : not set automatically these are reserved bits. do not write 1 to these bits. 0 0 ( n o t e ) ? ? ? ? ? 0 : oscillation stop not detected 1 : oscillation stop detected ceramic or rc oscillation stop detection function active bit 0 : detection function inactive 1 : detection function active o s c i l l a t i o n s t o p d e t e c t i o n s t a t u s b i t note: 0 at normal reset 1 at reset by detecting the oscillation stop
7540 group user s manual 2-38 application 2.3 timer 1 fig. 2.3.5 structure of interrupt request register 2 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 2 (ireq2) [address : 3d 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . timer y interrupt request bit timer z interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued timer a interrupt request bit serial i/o2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ad converter interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? ? fig. 2.3.6 structure of interrupt control register 2 interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 2 (icon2) [address : 3f 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? timer y interrupt enable bit timer z interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled timer 1 interrupt enable bit timer a interrupt enable bit serial i/o2 interrupt enable bit ad conversion interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled ?
7540 group user s manual application 2-39 2.3 timer 1 2.3.3 timer 1 operation description timer 1 always operates in the timer mode. prescaler 1 counts the selected count source. each time the count clock is input, the contents of prescaler 1 is decremented by 1. when the contents of prescaler 1 reach 00 16 , an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into prescaler 1 and count continues. the division ratio of prescaler 1 is 1/ (n+1) provided that the value of prescaler 1 is n. the contents of timer 1 is decremented by 1 each time the underflow signal of prescaler 1 is input. when the contents of timer 1 reach 00 16 , an underflow occurs at the next count clock, and the timer 1 latch is reloaded into timer 1 and count continues. the division ratio of timer 1 is 1/(m+1) provided that the value of timer 1 is m. accordingly, the division ratio of prescaler 1 and timer 1 is provided as follows that the value of prescaler 1 is n and the value of timer 1 is m. timer 1 cannot stop counting by software. also, when timer 1 underflows, the timer 1 interrupt request bit is set to 1 . 2.3.4 notes on timer 1 note on using timer 1 is described below. (1) notes on set of the oscillation stabilizing time timer 1 can be used to set the oscillation stabilizing time after release of the stp instruction. the oscillation stabilizing time after release of stp instruction can be selected from set automatically / not set automatically by the oscillation stabilizing time set bit after release of the stp instruction of misrg. when 0 is set to this bit, 01 16 is set to timer 1 and ff 16 is set to prescaler 1 automatically. when 1 is set to this bit, nothing is set to timer 1 and prescaler 1. therefore, set the wait time according to the oscillation stabilizing time of the oscillation. also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. division ratio = 1 (n+1) ? (m+1)
7540 group user? manual 2-40 application 2.4 timer x 2.4 timer x this paragraph explains the registers setting method and the notes relevant to the timer x. 2.4.1 memory map fig. 2.4.1 memory map of registers relevant to timer x 0001 16 0003 16 002b 16 002c 16 002d 16 002e 16 port p0 direction register (p0d) port p1 direction register (p1d) timer x mode register (txm) prescaler x (prex) timer x (tx) timer count source set register (tcss) 003c 16 003e 16 interrupt request register 1 (ireq1) interrupt control register 1 (icon1)
7540 group user s manual application 2-41 2.4 timer x 2.4.2 relevant registers fig. 2.4.2 structure of port p0 direction register fig. 2.4.3 structure of port p1 direction register port p0 direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p0 direction register 0 0 0 0 0 0 0 0 port p0 direction register (p0d) [address : 01 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode ? ? ? ? ? ? ? ? port p1 direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p1 direction register 0 0 0 0 0 ? ? ? port p1 direction register (p1d) [address : 03 16 ] 0 : port p1 0 input mode 1 : port p1 0 output mode 0 : port p1 1 input mode 1 : port p1 1 output mode 0 : port p1 2 input mode 1 : port p1 2 output mode 0 : port p1 3 input mode 1 : port p1 3 output mode 0 : port p1 4 input mode 1 : port p1 4 output mode ? ? ? ? ? ? ? ? nothing is allocated for these bits. when these bits are read out, the values are undefined. ? ? ?
7540 group user s manual 2-42 application 2.4 timer x fig. 2.4.4 structure of timer x mode register timer x operating modes timer mode pulse output mode event counter mode pulse width measurement mode cntr 0 active edge switch bit (bit 2 of address 2b 16 ) contents 0 cntr 0 interrupt request occurrence: falling edge ; no influence to timer count 1 cntr 0 interrupt request occurrence: rising edge ; no influence to timer count 0 pulse output start: beginning at h level cntr 0 interrupt request occurrence: falling edge 1 pulse output start: beginning at l level cntr 0 interrupt request occurrence: rising edge 0 timer x: rising edge count cntr 0 interrupt request occurrence: falling edge 1 timer x: falling edge count cntr 0 interrupt request occurrence: rising edge 0 timer x: h level width measurement cntr 0 interrupt request occurrence: falling edge 1 timer x: l level width measurement cntr 0 interrupt request occurrence: rising edge table 2.4.1 cntr 0 active edge switch bit function b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 2 3 4 5 6 7 name 0 0 0 0 timer x mode register (txm) [address : 2b 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? ? ? timer x mode register 0 0 0 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode b1 b0 1 0 timer x operating mode bits cntr 0 active edge switch bit the function depends on the operating mode. (refer to table 2.4.1) timer x count stop bit 0 : count start 1 : count stop 0 : output invalid (i/o port) 1 : output valid (inverted cntr 0 output) p0 3 /tx out output valid bit
7540 group user s manual application 2-43 2.4 timer x fig. 2.4.5 structure of prescaler x fig. 2.4.6 structure of timer x prescaler x b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 prescaler x (prex) [address : 2c 16 ] set a count value of prescaler x. the value set in this register is written to both prescaler x and the prescaler x latch at the same time. when this register is read out, the count value of the prescaler x is read out. timer x b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 timer x (tx) [address : 2d 16 ] set a count value of timer x. the value set in this register is written to both timer x and timer x latch at the same time. when this register is read out, the timer x s count value is read out.
7540 group user s manual 2-44 application 2.4 timer x fig. 2.4.7 structure of timer count source set register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 timer count source set register (tcss) [address : 2e 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . timer count source set register timer x count source selection bits 0 0 0 b1 b0 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : f(x in ) ( note 1 ) 1 1 : not available 0 timer y count source selection bits timer z count source selection bits notes 1: f(x in ) can be used as timer x count source only when using a ceramic oscillator or ring oscillator. do not use it at rc oscillation. 2: system operates using a ring oscillator as a count source by setting the ring oscillator to oscillation enabled by bit 3 of cpum. fix this bit to 0 . b5 b4 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : timer y underflow 1 1 : not available b3 b2 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : ring oscillator output ( note 2 ) 1 1 : not available ?
7540 group user s manual application 2-45 2.4 timer x fig. 2.4.8 structure of interrupt request register 1 fig. 2.4.9 structure of interrupt control register 1 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 1 (ireq1) [address : 3c 16 ] serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued cntr 0 interrupt request bit cntr 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued int 0 interrupt request bit int 1 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued key-on wake up interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? timer x interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ? interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 1 (icon1) [address : 3e 16 ] serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled cntr 0 interrupt enable bit cntr 1 interrupt enable bit int 0 interrupt enable bit int 1 interrupt enable bit key-on wake up interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer x interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled
7540 group user s manual 2-46 application 2.4 timer x 2.4.3 timer mode (1) operation description prescaler x counts the selected count source by the timer x count source selection bits. each time the count clock is input, the contents of prescaler x is decremented by 1. when the contents of prescaler x reach 00 16 , an underflow occurs at the next count clock, and the prescaler x latch is reloaded into prescaler x and count continues. the division ratio of prescaler x is 1/(n+1) provided that the value of prescaler x is n. the contents of timer x is decremented by 1 each time the underflow signal of prescaler x is input. when the contents of timer x reach 00 16 , an underflow occurs at the next count clock, and the timer x latch is reloaded into timer x and count continues. the division ratio of timer x is 1/(m+1) provided that the value of timer x is m. accordingly, the division ratio of prescaler x and timer x is provided as follows that the value of prescaler x is n and the value of timer x is m. timer x can stop counting by setting 1 to the timer x count stop bit. also, when timer x underflows, the timer x interrupt request bit is set to 1 . (2) timer mode setting method figure 2.4.10 shows the setting method for timer mode of timer x. division ratio = 1 (n+1) ? (m+1)
7540 group user s manual application 2-47 2.4 timer x fig. 2.4.10 setting method for timer mode b 7b 0 0 1 0 b 7b 0 b 7b 0 0 0 b 7b 0 0 0 b 7b 0 0 b 7b 0 1 0 p r o c e s s 1 : d i s a b l e t i m e r x i n t e r r u p t . p r o c e s s 2 : s e t t i m e r x m o d e r e g i s t e r . timer x mode register (txm) [address 2b 16 ] p r o c e s s 4 : s e t t h e c o u n t v a l u e t o t i m e r x . s e t t h e c o u n t v a l u e t o p r e s c a l e r x a n d t i m e r x prescaler x (prex) (address 2c 16 ) c ount va l ue timer x (tx) (address 2d 16 ) note: f(x in ) can be used only when a ceramic resonator or a ring oscillator is used. do not use f(x in ) at rc oscillation. p r o c e s s 5 : i n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t 0 ( n o r e q u e s t e d ) t o t h e t i m e r x i n t e r r u p t r e q u e s t b i t . t i m e r m o d e t i m e r x c o u n t s t o p c ount va l ue interrupt control register 1 (icon1) [address 3e 16 ] ti mer x i nterrupt di sa bl e d i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 3 c 1 6 ] p r o c e s s 6 : w h e n t i m e r x i n t e r r u p t i s u s e d , s e t 1 ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r x i n t e r r u p t e n a b l e b i t . n o t i mer x i nterrupt request i ssue d i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] ti mer x i nterrupt ena bl e d timer x mode register (txm) [address 2b 16 ] t i m e r x c o u n t s t a r t p r o c e s s 7 : s t a r t c o u n t i n g o f t i m e r x . p r o c e s s 3 : s e t t i m e r c o u n t s o u r c e s e t r e g i s t e r . timer count source set register (tcss) [address 2e 16 ] ti mer x count source se l ect i on bi ts b1 b0 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : f(x in ) ( note ) 1 1 : not available
7540 group user s manual 2-48 application 2.4 timer x (3) application example of timer mode outline : the input clock is divided by the timer so that the clock is counted up every 250 ms intervals. specifications : the f(x in ) = 4.19 mhz (2 22 hz) is divided by timer x. the clock is counted up in the timer x interrupt processing routine (timer x interrupt occurs every 250 ms). operation clock: f(x in ) = 4.19 mhz, high-speed mode figure 2.4.11 shows the connection of timer and setting of division ratio and figure 2.4.12 shows an example of control procedure. fig. 2.4.11 connection of timer and setting of division ratio f(x in ) = 4.19 mhz p r e s c a l e r xtimer x timer x interrupt request bit 250 ms 1/16 1/256 1/256 0 or 1 1/4 1s d i v i d e d b y 4 b y s o f t w a r e 0: no interrupt request 1: interrupt request t i m e r x c o u n t s o u r c e s e l e c t i o n b i t s
7540 group user? manual application 2-49 2.4 timer x fig. 2.4.12 example of control procedure ff 16 cli 0 1 1 reset timer x interrupt processing routine rti 00 0 tcss(address 2e 16 ) timer x count source: f(x in )/16 selected set timer count source set register 1 00 0 txm(address 2b 16 ) 0 1 00 setting clock is required? processing processing of setting clock y n clock is stopped? y n processing of clock setting clock setting rts 0 1 00 0 0 1 00 set 0 to the timer x interrupt enable bit. (timer x interrupt disabled) prescaler x (address 2c 16 ) set value to timer x ( note 2 ) set 0 to the timer x interrupt request bit. txm(address 2b 16 ) timer mode timer x count stop set timer x mode register initialization sei cld clt cpum(address 3b 16 ) 10000x00 2 wait until f(x in ) oscillation is stabilized ( note 1 ) cpum(address 3b 16 ) 00000x00 2 timer x (address 2d 16 ) set 1 to the timer x interrupt enable bit. (timer x interrupt enabled) timer x count start set timer x mode register x: this bit is not used here. set it to 0 or 1 arbitrary. notes 1: for the concrete time, ask the oscillator manufacture. 2: about 250 ms = 1/4.19 mhz 16 (ff 16 + 1) (ff 16 + 1) timer x setting value ff 16 clock count up (1/4 s to year) set 0 to the timer x interrupt enable bit. (timer x interrupt disabled) txm(address 2b 16 ) timer x count start set timer x mode register txm(address 2b 16 ) timer x count stop set timer x mode register ff 16 prescaler x (address 2c 16 ) set value to timer x ( note 2 ) set 0 to the timer x interrupt request bit. timer x (address 2d 16 ) set 1 to the timer x interrupt enable bit. (timer x interrupt enabled) ff 16 timer x division ratio prescaler x setting value
7540 group user? manual 2-50 application 2.4 timer x fig. 2.4.13 setting method for pulse output mode (1) 2.4.4 pulse output mode (1) operation description in the pulse output mode, the waveform whose polarity is inverted each time timer x underflows is output from the p1 4/ cntr 0 pin. the output level of cntr 0 pin can be selected by the cntr 0 active edge switch bit. when the cntr 0 active edge switch bit is ?? the output of cntr 0 pin is started at ??level. when this bit is ?? the output is started at ??level. also, the inverted waveform of pulse output from cntr 0 pin can be output from tx out pin by setting ??to the p0 3 /tx out output valid bit. when using a timer in this mode, set the port p1 4 and p0 3 direction registers to output mode. timer x can stop counting by setting ??to the timer x count stop bit. also, when timer x underflows, the timer x interrupt request bit is set to ?? (2) pulse output mode setting method figure 2.4.13 and figure 2.4.14 show the setting method for pulse output mode of timer x. b 7b0 0 1 1 b 7b 0 1 b 7b 0 1 b 7b 0 0 p r o c e s s 1 : d i s a b l e t i m e r x i n t e r r u p t . interrupt control register 1 (icon1) [address 3e 16 ] t i m e r x i n t e r r u p t d i s a b l e d p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) [ a d d r e s s 0 3 1 6 ] s e t t h e p 1 4 / c n t r 0 p i n t o t h e o u t p u t m o d e p r o c e s s 3 : s e t t h e c n t r 0 p i n t o t h e o u t p u t m o d e . p r o c e s s 2 : s e t t i m e r x m o d e r e g i s t e r . timer x mode register (txm) [address 2b 16 ] p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) [ a d d r e s s 0 1 1 6 ] s e t t h e p 0 3 / t x o u t p i n t o t h e o u t p u t m o d e p r o c e s s 4 : s e t t h e t x o u t p i n a s t h e o u t p u t m o d e w h e n t x o u t o u t p u t i s v a l i d . p u l se output mo d e cntr 0 active edge switch 0: output is started at h level 1: output is started at l level timer x count stop p0 3 /tx out output 0: output invalid (i/o port) 1: output valid (inverted cntr 0 output)
7540 group user s manual application 2-51 2.4 timer x fig. 2.4.14 setting method for pulse output mode (2) b 7b 0 b 7b0 0 0 1 0 b 7b 0 0 b7 b0 1 p r o c e s s 6 : s e t t h e c o u n t v a l u e t o t i m e r x . set the count value to prescaler x and timer x p r e s c a l e r x ( p r e x ) ( a d d r e s s 2 c 1 6 ) c o u n t v a l u e timer x (tx) (address 2d 16 ) p r o c e s s 7 : i n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t 0 ( n o r e q u e s t e d ) t o t h e t i m e r x i n t e r r u p t r e q u e s t b i t . i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 3 c 1 6 ] p r o c e s s 8 : w h e n t h e i n t e r r u p t i s u s e d , s e t 1 ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r x i n t e r r u p t e n a b l e b i t . n o t i mer x i nterrupt request i ssue d timer x mode register (txm) [address 2b 16 ] ti mer x count start process 9: start counting of timer x. c o u n t v a l u e interrupt control register 1 (icon1) [address 3e 16 ] ti mer x i nterrupt ena bl e d n o t e : f ( x i n ) c a n b e u s e d o n l y w h e n a c e r a m i c r e s o n a t o r o r a r i n g o s c i l l a t o r i s u s e d . d o n o t u s e f ( x i n ) a t r c o s c i l l a t i o n . p r o c e s s 5 : s e t t i m e r c o u n t s o u r c e s e t r e g i s t e r . t i m e r c o u n t s o u r c e s e t r e g i s t e r ( t c s s ) [ a d d r e s s 2 e 1 6 ] t i m e r x c o u n t s o u r c e s e l e c t i o n b i t s b 1 b 0 0 0 : f ( x i n ) / 1 6 0 1 : f ( x i n ) / 2 1 0 : f ( x i n ) ( n o t e ) 1 1 : n o t a v a i l a b l e
7540 group user s manual 2-52 application 2.4 timer x (3) application example of pulse output mode outline : the pulse output mode of timer x is used for a piezoelectric buzzer output. specifications : the rectangular waveform which is clock f(x in ) = 4 mhz divided up to 4 khz is output from the p1 4 /cntr 0 pin. the level of the p1 4 /cntr 0 pin is fixed to h while a piezoelectric buzzer output is stopped. operation clock: f(x in ) = 4 mhz, double-speed mode figure 2.4.15 shows an example of a peripheral circuit, figure 2.4.16 shows the connection of timer and setting of the division ratio, and figure 2.4.17 shows an example of control procedure. fig. 2.4.15 example of peripheral circuit 7 5 4 0 g r o u p p 1 4 / c n t r 0 pipipi..... 125 s 125 s s e t d i v i s i o n r a t i o s o t h a t t h e u n d e r f l o w o u t p u t p e r i o d o f t i m e r x w i l l b e c o m e 1 2 5 s . t h e h l e v e l i s o u t p u t w h i l e a p i e z o e l e c t r i c b u z z e r o u t p u t i s s t o p p e d . c n t r 0 o u t p u t f(x in ) = 4mhz prescaler x timer x 1/2 timer x count source selection bit 1/2 1/125 1/2 fixed cntr 0 pin output 4 khz fig. 2.4.16 connection of timer and setting of division ratio
7540 group user? manual application 2-53 2.4 timer x fig. 2.4.17 example of control procedure 01 16 7c 16 0 txm(address 2b 16 ) 1 1 reset 01 0 tcss(address 2e 16 ) timer x count source: f(x in )/2 selected 1 01 0 0 1 0 0 buzzer output is requested? processing y n 0 7c 16 timer x (address 2d 16 ) cli timer x count is stopped? y processing timer x count is operating? 1 0 1 1 0 01 n y n buzzer output processing timer x division ratio timer x setting value sei cld clt cpum(address 3b 16 ) 10000x00 2 wait until f(x in ) oscillation is stabilized ( note 1 ) cpum(address 3b 16 ) 11000x00 2 set timer x mode register txm(address 2b 16 ) timer x count start pulse output mode output is started at h level timer x count stop set timer x mode register set port p1 4 to the output mode. set 0 to the cntr 0 interrupt enable bit. (cntr 0 interrupt disabled) set 0 to the timer x interrupt enable bit. (timer x interrupt disabled) initialization x: this bit is not used here. set it to 0 or 1 arbitrary. notes 1: for the concrete time, ask the oscillator manufacture. 2: 125 s = 1/4 mhz 2 (01 16 + 1) (7c 16 + 1) prescaler x (address 2c 16 ) set value to timer x ( notes 2, 3 ) timer x (address 2d 16 ) set 1 to port p1 4 . ( h output) set timer count source set register set timer x mode register txm(address 2b 16 ) timer x count stop set value to timer x ( note 3 ) 3: the output level of p1 4 /cntr 0 pin is initialized by writing to timer x. prescaler x setting value
7540 group user s manual 2-54 application 2.4 timer x fig. 2.4.18 setting method for event counter mode (1) 2.4.5 event counter mode (1) operation description the timer x counts signals input from the p1 4 /cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. the active edge of cntr 0 pin input signal can be selected from rising or falling by the cntr 0 active edge switch bit. timer x can stop counting by setting 1 to the timer x count stop bit. also, when timer x underflows, the timer x interrupt request bit is set to 1 . (2) event counter mode setting method figure 2.4.18 and figure 2.4.19 show the setting method for event counter mode of timer x. b7 b 0 1 1 0 b7 b0 0 b 7b 0 0 b7 b 0 00 process 1: disable timer x interrupt and cntr 0 interrupt. i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] c n t r 0 i n t e r r u p t d i s a b l e d t i m e r x i n t e r r u p t d i s a b l e d p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) [ a d d r e s s 0 3 1 6 ] s et t h e p 1 4 / cntr 0 p i n to t h e i nput mo d e p r o c e s s 2 : s e t t h e c n t r 0 p i n t o t h e i n p u t m o d e . process 3: set timer x mode register. t i m e r x m o d e r e g i s t e r ( t x m ) [ a d d r e s s 2 b 1 6 ] e vent counter mo d e cntr 0 active edge switch 0: count at rising edge cntr 0 interrupt request occurs at falling edge 1: count at falling edge cntr 0 interrupt request occurs at rising edge timer x count stop n o t e : f ( x i n ) c a n b e u s e d o n l y w h e n a c e r a m i c o s c i l l a t o r o r a r i n g o s c i l l a t o r i s u s e d . d o n o t u s e f ( x i n ) a t r c o s c i l l a t i o n . p r o c e s s 4 : s e t t i m e r c o u n t s o u r c e s e t r e g i s t e r . timer count source set register (tcss) [address 2e 16 ] ti mer x count source se l ect i on bi ts b1 b0 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : f(x in ) ( note ) 1 1 : not available
7540 group user s manual application 2-55 2.4 timer x fig. 2.4.19 setting method for event counter mode (2) b7 b0 0 b7 b 0 00 b7 b 0 11 10 p r o c e s s 5 : s e t t h e c o u n t v a l u e t o t i m e r x . s e t t h e c o u n t v a l u e t o p r e s c a l e r x a n d t i m e r x p r e s c a l e r x ( p r e x ) ( a d d r e s s 2 c 1 6 ) c o u n t v a l u e t i m e r x ( t x ) ( a d d r e s s 2 d 1 6 ) c o u n t v a l u e process 6: in order not to execute the no requested interrupt processing, set 0 (no requested) to the timer x interrupt request bit and cntr 1 interrupt request bit. interrupt request register 1 (ireq1) [address 3c 16 ] p r o c e s s 7 : w h e n t h e i n t e r r u p t i s u s e d , s e t 1 ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r x i n t e r r u p t e n a b l e b i t . n o c n t r 0 i n t e r r u p t r e q u e s t i s i s s u e d n o t i m e r x i n t e r r u p t r e q u e s t i s s u e d timer x mode register (txm) [address 2b 16 ] ti mer x count start process 8: start counting of timer x. interrupt control register 1 (icon1) [address 3e 16 ] c n t r 0 i n t e r r u p t e n a b l e d t i m e r x i n t e r r u p t e n a b l e d
7540 group user s manual 2-56 application 2.4 timer x (3) application example of event counter mode outline : pulses generated corresponding to the water flow rate are counted for a fixed period (100 ms), and the water flow rate during this period is calculated. specifications : pulses generated corresponding to the water flow rate are input to the p1 4 /cntr 0 pin and counted using timer x. the contents of timer x are read in the timer y interrupt processing routine generated after 100 ms from the start of counting pulses, and the water flow rate during 100 ms is calculated. operation clock: f(x in ) = 8 mhz, high-speed mode figure 2.4.20 shows an example of peripheral circuit, figure 2.4.21 shows the method of measuring water flow rate, and figure 2.4.21 shows an example of control procedure. fig. 2.4.20 example of peripheral circuit 7 5 4 0 g r o u p p1 4 /cntr 0 w a t e r f l o w r a t e s e n s o r water flow b l a d e s r o t a t e i n p r o p o r t i o n t o w a t e r f l o w a n d g e n e r a t e p u l s e s . t h e f a s t e r t h e w a t e r f l o w , t h e s h o r t e r t h e p u l s e p e r i o d . fig. 2.4.21 method of measuring water flow rate c n t r 0 p i n i n p u t t i m e r y i n t e r r u p t r e q u e s t b i t 1 0 0 m s timer x counting ( note ) note: counting rising edges. flow rate during 100 ms = (ff 16 read value of timer x) ? flow rate per pulse t i m e r y i n t e r r u p t p r o c e s s i n g r o u t i n e t i m e r x , t i m e r y s t o p c o u n t i n g . t i m e r x i s r e a d o u t . timer x, timer y start counting.
7540 group user s manual application 2-57 2.4 timer x fig. 2.4.22 example of control procedure f f 1 6 ff 16 0 1 1 10 0 1 00 0 0 1 10 f l o w r a t e m e a s u r i n g r o u t i n e 1 0 0 c 7 1 6 f 9 16 0 0 0 e n d timer y interrupt processing routine 0 1 1 10 1 0 0 (prescaler x setting value ff 16 timer x setting value ff 16 ) (prescaler x count value, timer x count value) the numbeer of event within 100 ms rti 1 1 1 t x m ( a d d r e s s 2 b 1 6 ) tcss(address 2e 16 ) timer y count source: f(x in )/16 selected t i m e r y d i v i s i o n r a t i o ti mer y primary setting value e v e n t c o u n t e r m o d e c o u n t a t f a l l i n g e d g e t i m e r x c o u n t s t o p s e t t i m e r x m o d e r e g i s t e r set port p1 4 to the input mode. s e t 0 t o t h e c n t r 0 i n t e r r u p t e n a b l e b i t . ( c n t r 0 i n t e r r u p t d i s a b l e d ) s e t 0 t o t h e t i m e r x i n t e r r u p t e n a b l e b i t . ( t i m e r x i n t e r r u p t d i s a b l e d ) s e t 0 t o t h e t i m e r y i n t e r r u p t e n a b l e b i t . ( t i m e r y i n t e r r u p t d i s a b l e d ) note : 100 ms = 1/8 mhz ? 16 ? (c7 16 + 1) ? (f9 16 + 1) p resca l er x (add ress 2 c 16 ) s e t v a l u e t o t i m e r x t i m e r x ( a d d r e s s 2 d 1 6 ) set timer count source set register p resca l er y setting value t y z m ( a d d r e s s 2 0 1 6 ) s e t t i m e r y , z m o d e r e g i s t e r t i m e r m o d e w r i t i n g t o l a t c h a n d t i m e r s i m u l t a n e o u s l y t i m e r y c o u n t s t o p s e t v a l u e t o t i m e r y ( n o t e ) p r e s c a l e r y ( a d d r e s s 2 1 1 6 ) t i m e r y p r i m a r y ( a d d r e s s 2 3 1 6 ) set 1 to the timer y interrupt enable bit. (timer y interrupt enabled) s e t 0 t o t h e t i m e r y i n t e r r u p t r e q u e s t b i t . t x m ( a d d r e s s 2 b 1 6 ) timer x count start s e t t i m e r x m o d e r e g i s t e r t y z m ( a d d r e s s 2 0 1 6 ) s e t t i m e r y , z m o d e r e g i s t e r t i m e r y c o u n t s t a r t txm(address 2b 16 ) t i m e r x c o u n t s t o p set timer x mode register tyzm(address 20 16 ) set timer y, z mode register t i m e r y c o u n t s t o p
7540 group user s manual 2-58 application 2.4 timer x 2.4.6 pulse width measurement mode (1) operation description in the pulse width measurement mode, the pulse width of the signal input to p1 4 /cntr 0 pin is measured. the operation of timer x can be controlled by the level of the signal input from the cntr 0 pin. when the cntr 0 active edge switch bit is 0 , the signal selected by the timer x count source selection bit is counted while the input signal level of cntr 0 pin is h . the count is stopped while the pin is l . also, when the cntr 0 active edge switch bit is 1 , the signal selected by the timer x count source selection bit is counted while the input signal level of cntr 0 pin is l . the count is stopped while the pin is h . timer x can stop counting by setting 1 to the timer x count stop bit. also, when timer x underflows, the timer x interrupt request bit is set to 1 . (2) pulse width hl continuously measurement mode setting method figure 2.4.23 and figure 2.4.24 show the setting method for pulse width measurement mode of timer x. fig. 2.4.23 setting method for pulse width measurement mode (1) b 7b0 b 7b0 1 1 1 b 7b0 0 0 b 7b 0 00 p r o c e s s 1 : d i s a b l e t i m e r x i n t e r r u p t a n d c n t r 0 i n t e r r u p t . i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] c n t r 0 i n t e r r u p t d i s a b l e d t i m e r x i n t e r r u p t d i s a b l e d port p1 direction register (p1d) [address 03 16 ] s et t h e p 1 4 / cntr 0 p i n to t h e i nput mo d e process 2: set the cntr 0 pin to the input mode. p r o c e s s 3 : s e t t i m e r x m o d e r e g i s t e r . timer x mode register (txm) [address 2b 16 ] p u l s e w i d t h m e a s u r e m e n t m o d e c n t r 0 a c t i v e e d g e s w i t c h 0 : h l e v e l w i d t h m e a s u r e m e n t 1 : l l e v e l w i d t h m e a s u r e m e n t t i m e r x c o u n t s t o p n o t e : f ( x i n ) c a n b e u s e d o n l y w h e n a c e r a m i c r e s o n a t o r o r a r i n g o s c i l l a t o r i s u s e d . d o n o t u s e f ( x i n ) a t r c o s c i l l a t i o n . process 4: set timer x count source. t i m e r c o u n t s o u r c e s e t r e g i s t e r ( t c s s ) [ a d d r e s s 2 e 1 6 ] t i m e r x c o u n t s o u r c e s e l e c t i o n b i t s b 1 b 0 0 0 : f ( x i n ) / 1 6 0 1 : f ( x i n ) / 2 1 0 : f ( x i n ) ( n o t e ) 1 1 : n o t a v a i l a b l e
7540 group user s manual application 2-59 2.4 timer x fig. 2.4.24 setting method for pulse width measurement mode (2) b7 b0 0 b7 b0 00 b7 b0 11 11 p r o c e s s 5 : s e t t h e c o u n t v a l u e t o t i m e r x . s e t t h e i n i t i a l v a l u e t o p r e s c a l e r x a n d t i m e r x prescaler x (prex) (address 2c 16 ) i n i t i a l v a l u e timer x (tx) (address 2d 16 ) i n i t i a l v a l u e p r o c e s s 6 : i n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t 0 ( n o r e q u e s t e d ) t o t h e t i m e r x i n t e r r u p t r e q u e s t b i t a n d c n t r 0 i n t e r r u p t r e q u e s t b i t . interrupt request register 1 (ireq1) [address 3c 16 ] process 7: when the interrupt is used, set 1 (interrupt enabled) to the timer x interrupt enable bit. n o c n t r 0 i n t e r r u p t r e q u e s t i s i s s u e d n o t i m e r x i n t e r r u p t r e q u e s t i s s u e d t i m e r x m o d e r e g i s t e r ( t x m ) [ a d d r e s s 2 b 1 6 ] t i m e r x c o u n t s t a r t process 8: start counting of timer x. interrupt control register 1 (icon1) [address 3e 16 ] cntr 0 i nterrupt ena bl e d timer x interrupt enabled
7540 group user s manual 2-60 application 2.4 timer x (3) application example of pulse width measurement mode outline : h level width of pulse input to p1 4 /cntr 0 pin is counted. specifications : the h level width of a fg pulse input to the p1 4 /cntr 0 pin is counted. an underflow is detected by the timer x interrupt. the completion of h level of input pulse is detected by the cntr 0 interrupt. operation clock: f(x in ) = 4.19 mhz, high-speed mode example: when f(x in ) = 4.19 mhz, the count source becomes 3.8 s divided by 16. measurement can be made up to 250 ms in the range of ffff 16 to 0000 16 . figure 2.4.25 shows a connection of the timer and setting of the division ratio. figure 2.4.26 shows an example of control procedure. fig. 2.4.25 connection of timer and setting of division ratio f(x in ) = 4.19mhz p r e s c a l e r xtimer x t i m e r x i n t e r r u p t r e q u e s t b i t 2 5 0 m s 1 / 1 61 / 2 5 6 1/256 0 o r 1 0: no interrupt request 1: interrupt request t i m e r x c o u n t s o u r c e s e l e c t i o n b i t
7540 group user s manual application 2-61 2.4 timer x fig. 2.4.26 example of control procedure ff 16 ff 16 0 1 1 11 0 1 00 0 0 1 11 end reset 0 cli processing timer x interrupt processing cntr 0 interrupt processing timer x interrupt processing routine error processing rti cntr 0 interrupt processing routine timer x is read out. rti txm(address 2b 16 ) tcss(address 2e 16 ) timer y count source: f(x in )/16 selected timer x division ratio timer x setting value sei cld clt cpum(address 3b 16 ) 10000x00 2 wait until f(x in ) oscillation is stabilized ( note 1 ) cpum(address 3b 16 ) 00000x00 2 pulse width measurement mode falling edge timer x count stop set timer x mode register set port p1 4 to the input mode. set 0 to the cntr 0 interrupt enable bit. (cntr 0 interrupt disabled) set 0 to the timer x interrupt enable bit. (timer x interrupt disabled) initialization x: this bit is not used here. set it to 0 or 1 arbitrary. notes 1: for the concrete time, ask the oscillator manufacture. 2: about 250 ms = 1/4.19 mhz 16 (ff 16 + 1) (ff 16 + 1) prescaler x (address 2c 16 ) set value to timer x ( note 2 ) timer x (address 2d 16 ) set timer count source set register prescaler x setting value set 1 to the cntr 0 interrupt enable bit. (cntr 0 interrupt enabled) set 1 to the timer x interrupt enable bit. (timer x interrupt enabled) set 0 to the cntr 0 interrupt request bit. set 0 to the timer x interrupt request bit. txm(address 2b 16 ) timer x count start set timer x mode register error processing at incorrect period input
7540 group user s manual 2-62 application 2.4 timer x 2.4.7 notes on timer x notes on using each mode of timer x are described below. (1) count source ? f(x in ) can be used only when a ceramic oscillator or a ring oscillator is used. do not use f(x in ) at rc oscillation. (2) pulse output mode ? in order to use cntr 0 pin, set 1 to bit 4 of the port p1 direction register (output mode). ? in order to use tx out pin, set 1 to bit 3 of the port p0 direction register (output mode). ? cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. when this bit is 0 , the cntr 0 interrupt request bit is set to 1 at the falling edge of cntr 0 pin input signal. when this bit is 1 , the cntr 0 interrupt request bit is set to 1 at the rising edge of cntr 0 pin input signal. (3) pulse width measurement mode ? in order to use cntr 0 pin, set 1 to bit 4 of the port p1 direction register (output mode). ? cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. when this bit is 0 , the cntr 0 interrupt request bit is set to 1 at the falling edge of cntr 0 pin input signal. when this bit is 1 , the cntr 0 interrupt request bit is set to 1 at the rising edge of cntr 0 pin input signal.
7540 group user? manual application 2-63 2.5 timer y and timer z 2.5 timer y and timer z this paragraph explains the registers setting method and the notes relevant to the timer y and timer z. 2.5.1 memory map fig. 2.5.1 memory map of registers relevant to timer y and timer z 0025 16 0026 16 0027 16 002a 16 002e 16 prescaler z (prez) timer z secondary (tzs) timer z primary (tzp) one-shot start register (ons) timer count source set register (tcss) 003c 16 003e 16 interrupt request register 1 (ireq1) interrupt control register 1 (icon1) 003a 16 interrupt edge selection register (intedge) 003d 16 003f 16 interrupt request register 2 (ireq2) interrupt control register 2 (icon2) 003b 16 cpu mode register (cpum) 0022 16 0023 16 0024 16 timer y secondary (tys) timer y primary (typ) timer y, z waveform output control register (pum) 0020 16 0021 16 timer y, z mode register (tyzm) prescaler y (prey) 0016 16 0017 16 pull-up control register (pull) port p1p3 control register (p1p3c) 0007 16 port p3 direction register (p3d) 0001 16 port p0 direction register (p0d)
7540 group user s manual 2-64 application 2.5 timer y and timer z 2.5.2 relevant registers fig. 2.5.2 structure of port p0 direction register fig. 2.5.3 structure of port p3 direction register port p0 direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p0 direction register 0 0 0 0 0 0 0 0 port p0 direction register (p0d) [address : 01 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode ? ? ? ? ? ? ? ? port p3 direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p3 direction register 0 0 0 0 0 0 0 0 port p3 direction register (p3d) [address : 07 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode ? ? ? ? ? ? ? ? note: the 32-pin package versions have nothing to be allocated for the following: bits 5 and 6 of p3d.
7540 group user s manual application 2-65 2.5 timer y and timer z fig. 2.5.4 structure of pull-up control register pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name p0 0 pull-up control bit 0 0 0 0 0 0 0 0 pull-up control register (pull) [address : 16 16 ] 0 : pull-up off 1 : pull-up on notes 1: pins set to output are disconnected from the pull-up control. 2: keep setting the p3 5 , p3 6 pull-up control bit to 1 (initial value: 0) for the 32-pin package versions. p0 1 pull-up control bit 0 : pull-up off 1 : pull-up on p0 2 , p0 3 pull-up control bit 0 : pull-up off 1 : pull-up on p0 4 p0 7 pull-up control bit 0 : pull-up off 1 : pull-up on p3 0 p3 3 pull-up control bit 0 : pull-up off 1 : pull-up on p3 4 pull-up control bit 0 : pull-up off 1 : pull-up on p3 5 , p3 6 pull-up control bit 0 : pull-up off 1 : pull-up on p3 7 pull-up control bit 0 : pull-up off 1 : pull-up on fig. 2.5.5 structure of port p1p3 control register port p1p3 control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name p3 7 /int 0 input level selection bit 0 0 0 0 0 0 0 0 port p1p3 control register (p1p3c) [address : 17 16 ] 0 : cmos level 1 : ttl level p3 6 /int 1 input level selection bit ( note ) 0 : cmos level 1 : ttl level p1 0 , p1 2 ,p1 3 input level selection bit 0 : cmos level 1 : ttl level nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? ? ? ? ? note: keep setting the p3 6 /int 1 input level selection bit to 0 (initial value) for the 32-pin package version.
7540 group user s manual 2-66 application 2.5 timer y and timer z fig. 2.5.6 structure of timer y, z mode register fig. 2.5.7 structure of prescaler y, prescaler z prescaler y, prescaler z b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 prescaler y (prey) [address : 21 16 ] prescaler z (prez) [address : 25 16 ] set a count value of each prescaler. the value set in this register is written to both each prescaler and the corresponding prescaler latch at the same time. when this register is read out, the count value of the corres- ponding prescaler is read out. timer y, z mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 0 . timer y, z mode register (tyzm) [address : 20 16 ) timer y operating mode bit 0 : timer mode 1 : programmable waveform generation mode timer y write control bit ( note ) 0 : write to latch and timer simultaneously 1 : write to only latch timer y count stop bit 0 : count start 1 : count stop timer z operating mode bits b5 b4 0 0 : timer mode 0 1 : programmable waveform generation mode 1 0 : programmable one-shot generation mode 1 1 : programmable wait one-shot generation mode timer z write control bit ( note ) 0 : write to latch and timer simultaneously 1 : write to only latch timer z count stop bit 0 : count start 1 : count stop ? note : when modes other than the timer mode, set these bits to 1 .
7540 group user s manual application 2-67 2.5 timer y and timer z fig. 2.5.8 structure of timer y secondary, timer z secondary timer y secondary, timer z secondary b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 timer y secondary, timer z secondary (tys, tzs) [address : 22 16 , 26 16 ] set a count value of the corresponding timer. the value set in this register is written to the corresponding secondary latch at the same time. these are read disabled bits. when these bits are read out, the values are undefined. ? ? ? ? ? ? ? ? fig. 2.5.9 structure of timer y primary, timer z primary b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 timer y primary, timer z primary timer y primary, timer z primary (typ, tzp) [address : 23 16 , 27 16 ] set a count value of the corresponding timer. when the corresponding timer is stopped, the value set in this register is written to both the corresponding primary latch and the corresponding timer at the same time. when the corresponding timer is operating, the value set in this register is written as follows; timer write control bit = 0: the value is written to both the corresponding primary latch and the corresponding timer at the same time. timer write control bit = 1: the value is written to the corresponding primary latch. when these bits are read out, the count value of the corres- ponding timer is read out (note). note: the primary count value is read out at the primary interval, the secondary count value is read out at the secondary interval.
7540 group user s manual 2-68 application 2.5 timer y and timer z fig. 2.5.10 structure of timer y, z waveform output control register fig. 2.5.11 structure of one-shot start register timer y, z waveform output control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 timer y primary waveform extension control bit timer y secondary waveform extension control bit timer z output level latch timer z primary waveform extension control bit timer z secondary waveform extension control bit timer y output level latch 0 : falling edge trigger 1 : rising edge trigger timer y, z waveform output control register (pum) [address : 24 16 ] int 0 pin one-shot trigger control bit ( note ) int 0 pin one-shot trigger active edge selection bit ( note ) 0 : waveform not extended 1 : waveform extended 0 : waveform not extended 1 : waveform extended 0 : waveform not extended 1 : waveform extended 0 : waveform not extended 1 : waveform extended 0 : l output 1 : h output 0 : l output 1 : h output 0 : int 0 pin one-shot trigger invalid 1 : int 0 pin one-shot trigger valid note: stop timer z to change the values of these bits. one-shot start register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 one-shot start register (ons) [address : 2a 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? ? timer z one-shot start bit ? ? ? ? ? 0 : one-shot stop 1 : one-shot start
7540 group user s manual application 2-69 2.5 timer y and timer z fig. 2.5.12 structure of timer count source set register fig. 2.5.13 structure of interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 timer count source set register (tcss) [address : 2e 16 ] nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 0 . timer count source set register timer x count source selection bits 0 0 0 b1 b0 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : f(x in ) ( note 1 ) 1 1 : not available 0 timer y count source selection bits timer z count source selection bits notes 1: f(x in ) can be used as timer x count source only when using a ceramic oscillator or ring oscillator. do not use it at rc oscillation. 2: system operates using a ring oscillator as a count source by setting the ring oscillator to oscillation enabled by bit 3 of cpum. fix this bit to 0 . b5 b4 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : timer y underflow 1 1 : not available b3 b2 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : ring oscillator output ( note 2 ) 1 1 : not available ? interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt edge selection register (intedge) [address : 3a 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? ? int 0 interrupt edge selection bit int 1 interrupt edge selection bit 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active p0 0 key-on wakeup enable bit ? ? ? 0 : key-on wakeup enabled 1 : key-on wakeup disabled
7540 group user s manual 2-70 application 2.5 timer y and timer z fig. 2.5.14 structure of cpu mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 2 3 4 5 6 7 name 0 0 0 1 cpu mode register (cpum) [address : 3b 16 ] cpu mode register 0 0 0 0 0 : single-chip mode 0 1 : not available 1 0 : not available 1 1 : not available b1 b0 1 0 processor mode bits ( note 1 ) 0 : ceramic oscillation 1 : rc oscillation 0 : 0 page 1 : 1 page stack page selection bit oscillation mode selection bit ( note 1 ) clock division ratio selection bits 0 0 : = f(x in )/2 (high-speed mode) 0 1 : = f(x in )/8 (middle-speed mode) 1 0 : applied from ring oscillator 1 1 : = f(x in ) (double-speed mode) ( note 2 ) b7 b6 0 : ceramic or rc oscillation enabled 1 : ceramic or rc oscillation stop notes 1: the bit can be rewritten only once after releasing reset. after rewriting it is disable to write any data to the bit. however, by reset the bit is initialized and can be rewritten, again. (it is not disable to write any data to the bit for emulator mcu m37540rss .) 2: these bits are used only when a ceramic oscillation is selected. do not use these when an rc oscillation is selected. ring oscillator oscillation control bit 0 : ring oscillator oscillation enabled 1 : ring oscillator oscillation stop x in oscillation control bit
7540 group user s manual application 2-71 2.5 timer y and timer z fig. 2.5.15 structure of interrupt request register 1 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 1 (ireq1) [address : 3c 16 ] serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued cntr 0 interrupt request bit cntr 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued int 0 interrupt request bit int 1 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued key-on wake up interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? timer x interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ? fig. 2.5.16 structure of interrupt request register 2 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 2 (ireq2) [address : 3d 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . timer y interrupt request bit timer z interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued timer a interrupt request bit serial i/o2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ad converter interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? ?
7540 group user s manual 2-72 application 2.5 timer y and timer z fig. 2.5.17 structure of interrupt control register 1 fig. 2.5.18 structure of interrupt control register 2 interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 1 (icon1) [address : 3e 16 ] serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled cntr 0 interrupt enable bit cntr 1 interrupt enable bit int 0 interrupt enable bit int 1 interrupt enable bit key-on wake up interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer x interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 2 (icon2) [address : 3f 16 ] ? timer y interrupt enable bit timer z interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled timer 1 interrupt enable bit timer a interrupt enable bit serial i/o2 interrupt enable bit ad conversion interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled ? nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 .
7540 group user? manual application 2-73 2.5 timer y and timer z 2.5.3 timer mode (timer y and timer z) the basic operation of timer y and timer z are the same. in this section, timer y is explained. (1) operation description prescaler y counts the count source selected by the timer y count source selection bits. each time the count clock is input, the contents of prescaler y is decremented by 1. when the contents of prescaler y reach ?0 16 ? an underflow occurs at the next count clock, and the prescaler y latch is reloaded into prescaler y and count continues. the division ratio of prescaler y is 1/(n+1) provided that the value of prescaler y is n. the contents of timer y is decremented by 1 each time the underflow signal of prescaler y is input. when the contents of timer y reach ?0 16 ? an underflow occurs at the next count clock, and the timer y primary latch is reloaded into timer y and count continues. (in the timer mode, the contents of timer y primary latch is counted. timer y secondary latch is not used in this mode.) the division ratio of timer y is 1/(m+1) provided that the value of timer y is m. accordingly, the division ratio of prescaler y and timer y is provided as follows that the value of prescaler y is n and the value of timer y is m. in the timer mode, writing to ?atch only?or ?atches and prescaler y and timer y primary?can be selected by the setting value of the timer y write control bit. timer y can stop counting by setting ??to the timer y count stop bit. also, when timer y underflows, the timer y interrupt request bit is set to ?? timer y reloads the value of latch when counting is stopped by the timer count stop bit. (when timer is read out while timer is stopped, the value of latch is read. the value of timer can be read out only while timer is operating.) (2) timer mode setting method figure 2.5.19 shows the setting method for timer mode of timer y. when timer z is used, registers are set by the same method. division ratio = 1 (n+1) ? (m+1)
7540 group user s manual 2-74 application 2.5 timer y and timer z fig. 2.5.19 setting method for timer mode b 7b 0 1 0 b 7b 0 b 7 b 0 00 notes 1: for timer z, f(x in ), f(x in )/2, or timer y underflow can be selected. 2: set the ring oscillator oscillation to be enabled by bit 3 (ring oscillator oscillation control bit) of cpu mode register. b 7b 0 0 0 n o t e : i n t h e t i m e r m o d e , t h e t i m e r y s e c o n d a r y i s n o t u s e d . b7 b0 1 b 7b 0 0 p r o c e s s 1 : d i s a b l e t i m e r y i n t e r r u p t . p r o c e s s 2 : s e t t i m e r y , z m o d e r e g i s t e r . t i m e r y , z m o d e r e g i s t e r ( t y z m ) [ a d d r e s s 2 0 1 6 ] process 4: set the count value to timer y. set the count value to prescaler y and timer y primary c o u n t v a l u e timer y primary (typ) (address 23 16 ) process 5: in order not to execute the no requested interrupt processing, set 0 (no requested) to the timer y interrupt request bit. t i m e r m o d e t i m e r y w r i t e c o n t r o l b i t 0 : w r i t e t o l a t c h a n d t i m e r s i m u l t a n e o u s l y 1 : w r i t e t o o n l y l a t c h t i m e r y c o u n t s t o p c o u n t v a l u e i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 3 f 1 6 ] t i m e r y i n t e r r u p t d i s a b l e d interrupt request register 2 (ireq2) [address 3d 16 ] p r o c e s s 6 : w h e n t i m e r y i n t e r r u p t i s u s e d , s e t 1 ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r y i n t e r r u p t e n a b l e b i t . n o t i m e r y i n t e r r u p t r e q u e s t i s s u e d interrupt control register 2 (icon2) [address 3f 16 ] t i m e r y i n t e r r u p t e n a b l e d t i m e r y , z m o d e r e g i s t e r ( t y z m ) [ a d d r e s s 2 0 1 6 ] t i m e r y c o u n t s t a r t p r o c e s s 7 : s t a r t c o u n t i n g o f t i m e r y . p r o c e s s 3 : s e t t i m e r y c o u n t s o u r c e ( n o t e 1 ) t i m e r c o u n t s o u r c e s e t r e g i s t e r ( t c s s ) [ a d d r e s s 2 e 1 6 ] t i m e r y c o u n t s o u r c e s e l e c t i o n b i t s b 3 b 2 0 0 : f ( x i n ) / 1 6 0 1 : f ( x i n ) / 2 1 0 : r i n g o s c i l l a t o r o u t p u t ( n o t e 2 ) 1 1 : n o t a v a i l a b l e p r e s c a l e r y ( p r e y ) ( a d d r e s s 2 1 1 6 )
7540 group user s manual application 2-75 2.5 timer y and timer z (3) application example of timer mode outline : pulses generated corresponding to the water flow rate are counted for a fixed period (100 ms), and the water flow rate during this period is calculated. specifications : pulses generated corresponding to the water flow rate are input to the p1 4 /cntr 1 pin and counted using timer x. the contents of timer x are read in the timer y interrupt processing routine generated after 100 ms from the start of counting pulses, and the water flow rate during 100 ms is calculated. operation clock: f(x in ) = 8 mhz, high-speed mode figure 2.5.20 shows an example of peripheral circuit, figure 2.5.21 shows the method of measuring water flow rate, and figure 2.5.21 shows an example of control procedure. fig. 2.5.20 example of peripheral circuit fig. 2.5.21 method of measuring water flow rate 7 5 4 0 g r o u p p 1 4 / c n t r 0 w a t e r f l o w r a t e s e n s o r water flow b l a d e s r o t a t e i n p r o p o r t i o n t o w a t e r f l o w a n d g e n e r a t e p u l s e s . t h e f a s t e r t h e w a t e r f l o w , t h e s h o r t e r t h e p u l s e p e r i o d . cntr 0 pin input t i m e r y i n t e r r u p t r e q u e s t b i t 1 0 0 m s timer x counting ( note ) n o t e : c o u n t i n g r i s i n g e d g e s . flow rate during 100 ms = (ff 16 read value of timer y) ? flow rate per pulse timer y interrupt processing routine timer x, timer y stop counting. timer x is read out. timer x, timer y start counting.
7540 group user s manual 2-76 application 2.5 timer y and timer z fig. 2.5.22 example of control procedure ff 16 ff 16 0 1 1 10 0 1 00 0 0 1 10 1 0 0 c 7 1 6 f 9 1 6 0 0 0 e n d 0 1 1 10 1 0 0 rti 1 1 1 f l o w r a t e m e a s u r i n g r o u t i n e t i m e r y i n t e r r u p t p r o c e s s i n g r o u t i n e (prescaler x setting value ff 16 timer x setting value ff 16 ) (prescaler x count value, timer x count value) the numbeer of event within 100 ms t x m ( a d d r e s s 2 b 1 6 ) t c s s ( a d d r e s s 2 e 1 6 ) t i m e r y c o u n t s o u r c e : f ( x i n ) / 1 6 s e l e c t e d ti mer y division ratio t i m e r y p r i m a r y s e t t i n g v a l u e e v e n t c o u n t e r m o d e c o u n t a t f a l l i n g e d g e t i m e r x c o u n t s t o p s e t t i m e r x m o d e r e g i s t e r s e t 0 t o t h e c n t r 0 i n t e r r u p t e n a b l e b i t . ( c n t r 0 i n t e r r u p t d i s a b l e d ) s e t 0 t o t h e t i m e r x i n t e r r u p t e n a b l e b i t . ( t i m e r x i n t e r r u p t d i s a b l e d ) s e t 0 t o t h e t i m e r y i n t e r r u p t e n a b l e b i t . ( t i m e r y i n t e r r u p t d i s a b l e d ) n o t e : 1 0 0 m s = 1 / 8 m h z ? 1 6 ? ( c 7 1 6 + 1 ) ? ( f 9 1 6 + 1 ) p resca l er x (add ress 2 c 16 ) s e t v a l u e t o t i m e r x t i m e r x ( a d d r e s s 2 d 1 6 ) set timer count source set register p r e s c a l e r y s e t t i n g v a l u e t y z m ( a d d r e s s 2 0 1 6 ) set timer y, z mode register t i m e r m o d e w r i t i n g t o l a t c h a n d t i m e r s i m u l t a n e o u s l y t i m e r y c o u n t s t o p s e t v a l u e t o t i m e r y ( n o t e ) p r e s c a l e r y ( a d d r e s s 2 1 1 6 ) ti mer y pr i mary (add ress 23 16 ) s e t 1 t o t h e t i m e r y i n t e r r u p t e n a b l e b i t . ( t i m e r y i n t e r r u p t e n a b l e d ) s e t 0 t o t h e t i m e r y i n t e r r u p t r e q u e s t b i t . t x m ( a d d r e s s 2 b 1 6 ) t i m e r x c o u n t s t a r t set timer x mode register t y z m ( a d d r e s s 2 0 1 6 ) set timer y, z mode register t i m e r y c o u n t s t a r t t x m ( a d d r e s s 2 b 1 6 ) timer x count stop s e t t i m e r x m o d e r e g i s t e r t y z m ( a d d r e s s 2 0 1 6 ) s e t t i m e r y , z m o d e r e g i s t e r timer y count stop s e t p o r t p 1 4 t o t h e i n p u t m o d e .
7540 group user s manual application 2-77 2.5 timer y and timer z 2.5.4 programmable waveform generation mode (timer y and timer z) the basic operation of timer y and timer z are the same. in this section, timer y is explained. (1) operation description in the programmable waveform generation mode, timer counts the setting value of timer y primary (typ) and the setting value of timer y secondary (tys) alternately, the waveform whose polarity is inverted each time timer y underflows is output from p0 1 /ty out pin. when using this mode, be sure to set 1 to the timer y write control bit to select write to latch only . also, set the port p0 1 direction registers to output mode. the active edge of output waveform is set by the timer y output level latch. when 0 is set to the timer y output level latch, h interval by the setting value of typ or l interval by the setting value of tys is output alternately. when 1 is set to the timer y output level latch, l interval by the setting value of typ or h interval by the setting value of tys is output alternately. also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer y primary waveform extension control bit (b2) and the timer y secondary waveform extension control bit (b3) of pum to 1 . as a result, the waveforms of more accurate resolution can be output. when b2 and b3 of pum are used, the frequency and duty of the output waveform are as follows; waveform frequency: fyout= duty: dyout= tmycl: timer y count source (frequency) typ: timer y primary tys: timer y secondary expyp (1 bit): timer y primary waveform extension control bit expys (1 bit): timer y secondary waveform extension control bit in the programmable waveform generation mode, when values of the typ, tys, expyp and expys are changed, the output waveform is changed at the beginning (timer y primary waveform interval) of waveform period. when the count values are changed, set values to the tys, expyp and expys first. after then, set the value to typ. the values are set all at once at the beginning of the next waveform period when the value is set to typ. (when writing at timer stop is executed, writing to typ at last is required.) timer y can stop counting by setting 1 to the timer y count stop bit. also, when timer y underflows, the timer y interrupt request bit is set to 1 . timer y reloads the value of latch when counting is stopped by the timer y count stop bit. (when timer is read out while timer is stopped, the value of latch is read. the value of timer can be read out only while timer is operating.) 2 ? (tmycl) (2 ? (typ+1)+expyp)+(2 ? (tys+1)+expys)) 2 ? (typ+1)+expyp (2 ? (typ+1)+expyp)+(2 ? (tys+1)+expys))
7540 group user s manual 2-78 application 2.5 timer y and timer z notes 1: in the programmable waveform generation mode, values of tys, expyp, and expys are valid by writing to typ because the setting to them is executed all at once by writing to typ. even when changing typ is not required, write the same value again. 2: in the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to typ and the timing of timer underflow during the secondary interval simultaneously. an example of a measurement is shown below. ex.) the underflow by the primary and the underflow by secondary are stored by polling etc. using timer y interrupt. writing is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (depending on a primary and a secondary setting values, and primary write timing, it may be impossible.) 3: the waveform extension function by the timer y waveform extension control bits can be used only when 00 16 is set to prescaler y. when the value other than 00 16 is set to prescaler y, be sure to set 0 to expyp and expys. the waveform extension function by the timer z waveform extension control bits can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp and expzs. also, when the timer y underflow is selected as the timer z count source, the waveform extension function cannot be used. 4: when using this mode, be sure to set 1 to the timer y write control bit to select write to latch only . 5: when tys is read out, the undefined value is read out. however, while timer y counts the setting value of tys, the count value during the secondary interval can be obtained by reading the timer y primary. 6: in order to use ty out pin, set 1 to bit 1 of the port p0 direction register (output mode). figure 2.5.23 shows the timing diagram of the programmable waveform generation mode.
7540 group user s manual application 2-79 2.5 timer y and timer z fig. 2.5.23 timing diagram of programmable waveform generation mode t i m e r y p r i m a r y r e l o a d c o n t e n t s o f t i m e r y ty out pin output t i m e r y c o u n t c l o c k t i m e r y c o u n t s t o p b i t t i m e r y i n t e r r u p t r e q u e s t b i t t i m e r y o u t p u t l e v e l l a t c h 0 i s w r i t t e n c o u n t s t a r t 02 16 0 3 1 6 01 16 0 0 1 6 0 2 1 6 0 1 1 6 00 16 0 3 1 6 0 2 1 6 01 16 0 0 1 6 0 2 1 6 01 16 w h e n 0 3 1 6 i s s e t t o t y p a n d 0 2 1 6 i s s e t t o t y s . underflow underflow underflow t i m e r y s e c o n d a r y r e l o a d secondary waveform extension ( n o t e 2 ) ( n o t e 2 )( n o t e 2 ) initialized to l waveform output start notes 1: in this case, timer y primary waveform is not extended, timer y secondary waveform is extended. 2: in this time, 0 is written to the timer y interrupt request bit or the timer y interrupt request bit is cleared to 0 by accepting the timer y interrupt request. t i m e r y s e c o n d a r y r e l o a d ( note 1 ) 0 i s w r i t t e n waveform output inverted waveform output inverted waveform output inverted
7540 group user s manual 2-80 application 2.5 timer y and timer z (2) programmable waveform generation mode setting method figure 2.5.24 and figure 2.5.25 show the setting method for programmable waveform generation mode of timer y. when timer z is used, registers are set by the same method. fig. 2.5.24 setting method for programmable waveform generation mode (1) b 7b0 1 1 1 b 7b0 ti mer y pr i mary wave f orm extens i on contro l bi t ( n ote ) 0: waveform not extended 1: waveform extended timer y secondary waveform extension control bit ( note ) 0: waveform not extended 1: waveform extended timer y output level latch 0: initial state at stop: l , h interval by typ setting value, l interval by tys setting value 1: initial state at stop: h , l interval by typ setting value, h interval by tys setting value p r o c e s s 4 : s e t t y o u t p i n t o t h e o u t p u t ( n o t e ) . port p0 direction register (p0d) [address 01 16 ] s e t p 0 1 / t y o u t p i n a s t h e o u t p u t m o d e b 7b 0 1 note: for timer z, set tz out pin as the output by bit 2 of p0d. b7 b0 0 n o t e : w h e n u s i n g t h i s m o d e , b e s u r e t o s e t 1 t o t h e t i m e r y w r i t e c o n t r o l b i t t o s e l e c t w r i t e t o l a t c h o n l y . p r o c e s s 1 : d i s a b l e t i m e r y i n t e r r u p t . p r o c e s s 2 : s e t t i m e r y , z m o d e r e g i s t e r . t i m e r y , z m o d e r e g i s t e r ( t y z m ) [ a d d r e s s 2 0 1 6 ] p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e w r i t e t o o n l y l a t c h ( n o t e ) t i m e r y c o u n t s t o p i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 3 f 1 6 ] ti mer y i nterrupt di sa bl e d p r o c e s s 3 : s e t t i m e r y , z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r . timer y, z waveform output control register (pum) [address 24 16 ] n o t e : t h e w a v e f o r m e x t e n s i o n f u n c t i o n b y t h e t i m e r y w a v e f o r m e x t e n s i o n c o n t r o l b i t s c a n b e u s e d o n l y w h e n 0 0 1 6 i s s e t t o p r e s c a l e r y . w h e n t h e v a l u e o t h e r t h a n 0 0 1 6 i s s e t t o p r e s c a l e r y , b e s u r e t o s e t 0 t o e x p y p a n d e x p y s . t h e w a v e f o r m e x t e n s i o n f u n c t i o n b y t h e t i m e r z w a v e f o r m e x t e n s i o n c o n t r o l b i t s c a n b e u s e d o n l y w h e n 0 0 1 6 i s s e t t o p r e s c a l e r z . w h e n t h e v a l u e o t h e r t h a n 0 0 1 6 i s s e t t o p r e s c a l e r z , b e s u r e t o s e t 0 t o e x p z p a n d e x p z s . a l s o , w h e n t h e t i m e r y u n d e r f l o w i s s e l e c t e d a s t h e t i m e r z c o u n t s o u r c e , t h e w a v e f o r m e x t e n s i o n f u n c t i o n c a n n o t b e u s e d .
7540 group user s manual application 2-81 2.5 timer y and timer z fig. 2.5.25 setting method for programmable waveform generation mode (2) b 7b 0 0 1 1 b 7b0 1 b 7b 0 0 p r o c e s s 7 : i n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t 0 ( n o r e q u e s t e d ) t o t h e t i m e r y i n t e r r u p t r e q u e s t b i t . i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 3 d 1 6 ] p r o c e s s 8 : w h e n t i m e r y i n t e r r u p t i s u s e d , s e t 1 ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r y i n t e r r u p t e n a b l e b i t . n o t i mer y i nterrupt request i ssue d interrupt control register 2 (icon2) [address 3f 16 ] ti mer y i nterrupt ena bl e d t i m e r y , z m o d e r e g i s t e r ( t y z m ) [ a d d r e s s 2 0 1 6 ] t i m e r y c o u n t s t a r t p r o c e s s 9 : s t a r t c o u n t i n g o f t i m e r y . b 7b 0 0 notes 1: for timer z, f(x in )/16, f(x in )/2, or timer y underflow can be selected. however, when the timer z waveform expansion function is used, do not select the timer y underflow for the timer z count source. 2: set the ring oscillator oscillation to be enabled by bit 3 (ring oscillator oscillation control bit) of cpu mode register. p r o c e s s 6 : s e t t h e c o u n t v a l u e t o t i m e r y ( n o t e 1 ) . s e t t h e c o u n t v a l u e t o p r e s c a l e r y , t i m e r y s e c o n d a r y a n d t i m e r y p r i m a r y c ount va l ue timer y secondary (tys) (address 22 16 ) c ount va l ue p r o c e s s 5 : s e t t i m e r y c o u n t s o u r c e ( n o t e 1 ) . t i m e r c o u n t s o u r c e s e t r e g i s t e r ( t c s s ) [ a d d r e s s 2 e 1 6 ] ti mer y count source se l ect i on bi ts b3 b2 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : ring oscillator output ( note 2 ) 1 1 : not available p r e s c a l e r y ( p r e y ) ( a d d r e s s 2 1 1 6 ) ( n o t e 2 ) t i m e r y p r i m a r y ( t y p ) ( a d d r e s s 2 3 1 6 ) ( n o t e s 3 , 4 ) c o u n t v a l u e notes 1: in the programmable waveform generation mode, values of tys, expyp, and expys are valid by writing to typ. even when changing typ is not required, write the same value again. 2: when the timer y waveform extension function is used, be sure to set 00 16 to prescaler y. 3: in the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to typ and the timing of timer y underflow during the secondary interval simultanesously. 4: count values of the primary interval and secondary interval can be checked by reading the typ (tys is undefined at read).
7540 group user s manual 2-82 application 2.5 timer y and timer z (3) application example of programmable waveform generation mode outline : the waveform extension function is used and the waveform output is executed. specifications : the h width generated by typ and the l width generated by tys are output. set each waveform extension function to be valid, and set the duty ratio to be 2:1. the frequency is 40 khz. operation clock: f(x in ) = 8 mhz, high-speed mode figure 2.5.26 shows an example of waveform output and figure 2.5.27 shows an example of control procedure. fig. 2.5.26 example of waveform output 4 0 k h z p u l s e i s o u t p u t t y o u t p i n o u t p u t 16.7 s8.3 s duty ratio w a v e f o r m e x t e n d e d 21 : waveform extended
7540 group user s manual application 2-83 2.5 timer y and timer z fig. 2.5.27 example of control procedure 0 0 1 6 2 0 1 6 r e s e t 0 1 01 p r o c e s s i n g 1 1 1 c l i 0 1 1 ti mer y pr i mary wave f orm generation extended ( note 3 ) timer y secondary waveform generation extended ( note 3 ) initial state: l , typ: h interval, tys: l interval pum(address 24 16 ) 41 16 0 1 1 tcss(address 2e 16 ) timer y count source: f(x in )/2 selected set port p0 1 to the output mode. s e t 0 t o t h e t i m e r y i n t e r r u p t e n a b l e b i t . ( t i m e r y i n t e r r u p t d i s a b l e d ) p resca l er y (add ress 21 16 ) s e t v a l u e t o t i m e r y ( n o t e s 3 , 4 , 5 , 6 ) s e t t i m e r c o u n t s o u r c e s e t r e g i s t e r tyzm(address 20 16 ) s e t t i m e r y , z m o d e r e g i s t e r p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e w r i t i n g t o o n l y l a t c h ( n o t e 2 ) t i m e r y c o u n t s t o p t i m e r y p r i m a r y ( a d d r e s s 2 3 1 6 ) s e t 1 t o t h e t i m e r y i n t e r r u p t e n a b l e b i t . ( t i m e r y i n t e r r u p t e n a b l e d ) s e t 0 t o t h e t i m e r y i n t e r r u p t r e q u e s t b i t . tyzm(address 20 16 ) set timer y, z mode register t i m e r y c o u n t s t a r t i n i t i a l i z a t i o n sei cld clt cpum(address 3b 16 ) 10000x00 2 wait until f(x in ) oscillation is stabilized ( note 1 ) cpum(address 3b 16 ) 00000x00 2 x : t h i s b i t i s n o t u s e d h e r e . s e t i t t o 0 o r 1 a r b i t r a r y . ti mer y secon d ary (add ress 22 16 ) set timer y, z waveform output control register n o t e s 1 : f o r t h e c o n c r e t e t i m e , a s k t h e o s c i l l a t o r m a n u f a c t u r e . 2 : w h e n u s i n g t h i s m o d e , b e s u r e t o s e l e c t w r i t e t o l a t c h o n l y . 3 : t h e w a v e f o r m e x t e n s i o n f u n c t i o n b y t h e t i m e r y w a v e f o r m e x t e n s i o n c o n t r o l b i t s c a n b e u s e d o n l y w h e n 0 0 1 6 i s s e t t o p r e s c a l e r y . w h e n t h e v a l u e o t h e r t h a n 0 0 1 6 i s s e t t o p r e s c a l e r y , b e s u r e t o s e t 0 t o e x p y p a n d e x p y s . 4 : i n t h e p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e , v a l u e s o f t y s , e x p y p , a n d e x p y s a r e v a l i d b y w r i t i n g t o t y p . e v e n w h e n c h a n g i n g t y p i s n o t r e q u i r e d , w r i t e t h e s a m e v a l u e a g a i n . 5 : i n t h e p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e , w h e n t h e s e t t i n g v a l u e i s c h a n g e d w h i l e t h e w a v e f o r m i s o u t p u t , s e t b y s o f t w a r e i n o r d e r n o t t o e x e c u t e t h e w r i t i n g t o t y p a n d t h e t i m i n g o f t i m e r y u n d e r f l o w d u r i n g t h e s e c o n d a r y i n t e r v a l s i m u l t a n e s o u s l y . 6 : c o u n t v a l u e s o f t h e p r i m a r y i n t e r v a l a n d s e c o n d a r y i n t e r v a l c a n b e c h e c k e d b y r e a d i n g t y p ( t y s i s u n d e f i n e d a t r e a d ) .
7540 group user s manual 2-84 application 2.5 timer y and timer z 2.5.5 programmable one-shot generation mode (timer z) (1) operation description in the programmable one-shot generation mode, the one-shot pulse by the setting value of timer z primary can be output from p0 2 /tz out pin by software or external trigger to the p3 7 /int 0 pin. when using this mode, be sure to set 1 to the timer z write control bit to select write to latch only . also, set the port p0 2 direction registers to output mode. in this mode, the timer z secondary (tzs) is not used. the active edge of output waveform is set by the timer z output level latch. when 0 is set to the timer z output level latch, h pulse during the interval of the timer z primary (tzp) setting value is output. when 1 is set to the timer z output level latch, l pulse during the interval of the tzp setting value is output. also, in this mode, the interval of the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting the timer z primary waveform extension control bit (expzp) to 1 . as a result, the waveforms of more accurate resolution can be output. during the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing 0 to the timer z one-shot start bit. in the programmable one-shot generation mode, when the count values are changed, set value to the expzp first. after then, set the value to tzp. the values are set all at once at the beginning of the next one-shot pulse when the value is set to tzp. (even when writing at timer stop is executed, writing to tzp at last is required.) timer z can stop counting by setting 1 to the timer z count stop bit. also, when timer z underflows, the timer z interrupt request bit is set to 1 . timer z reloads the value of latch when counting is stopped by the timer z count stop bit. (when timer is read out while timer is stopped, the value of latch is read. the value of timer can be read out only while timer is operating.) notes 1: in the programmable one-shot generation mode, the value of expzp becomes valid by writing to tzp. even when changing tzp is not required, write the same value again. 2: in the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer underflow simultaneously. an example of a measurement is shown below. ex.) the underflow of timer is stored by polling etc. using timer z interrupt. writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (depending on a primary setting value, primary write timing, software and timing of external trigger to int 0 pin, it may be impossible.) 3: the waveform extension function by the timer z waveform extension control bits can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp. also, when the timer y underflow is selected as the timer z count source, the waveform extension function cannot be used. 4: when using this mode, be sure to set 1 to the timer z write control bit to select write to latch only . 5: in order to use tz out pin, set 1 to bit 2 of the port p0 direction register (output mode). 6: stop timer z to change the int 0 pin one-shot trigger control bit and int 0 pin one-shot trigger active edge selection bit. figure 2.5.28 shows the timing diagram of the programmable one-shot generation mode.
7540 group user s manual application 2-85 2.5 timer y and timer z fig. 2.5.28 timing diagram of programmable one-shot generation mode 0 2 1 6 0 3 1 6 01 16 00 16 0 3 1 6 03 16 0 2 1 6 0 1 1 6 0 0 1 6 ( note 3 ) o n e - s h o t s t a r t b i t i n t 0 p i n i n p u t ( n o t e 1 ) s e t t o 1 b y i n t 0 p i n i n p u t t r i g g e r c o n t e n t s o f t i m e r z t z o u t p i n o u t p u t t i m e r z c o u n t c l o c k t i m e r z c o u n t s t o p b i t t i m e r z i n t e r r u p t r e q u e s t b i t timer z output level latch 0 i s w r i t t e n count start w h e n 0 3 1 6 i s s e t t o t z p underflow timer z primary reload waveform extension i n i t i a l i z e d t o l waveform output start notes 1: in this case, int 0 pin one-shot trigger valid. 2: in this case, timer z primary waveform is extended. 3: in this time, 0 is written to the timer z interrupt request bit or the timer z interrupt request bit is cleared to 0 by accepting the timer z interrupt request. ( note 2 ) 0 is written 1 i s w r i t t e n u n d e r f l o w timer z primary reload c o u n t s t a r t w a v e f o r m e x t e n s i o n w a v e f o r m o u t p u t s t a r t w a v e f o r m o u t p u t e n d waveform output end
7540 group user s manual 2-86 application 2.5 timer y and timer z fig. 2.5.29 setting method for programmable one-shot generation mode (1) (2) event counter mode setting method figure 2.5.29 to figure 2.5.31 show the setting method for programmable one-shot generation mode of timer z. b 7b 0 1 b7 b0 1 0 11 b7 b0 b 7b 0 0 b 7b 0 0 t i m e r z p r i m a r y w a v e f o r m e x t e n s i o n c o n t r o l b i t ( n o t e 1 ) 0 : w a v e f o r m n o t e x t e n d e d 1 : w a v e f o r m e x t e n d e d t i m e r z o u t p u t l e v e l l a t c h 0 : i n i t i a l s t a t e a t s t o p : l , h i n t e r v a l b y t z p s e t t i n g v a l u e , l i n t e r v a l b y t z s s e t t i n g v a l u e 1 : i n i t i a l s t a t e a t s t o p : h , l i n t e r v a l b y t z p s e t t i n g v a l u e , h i n t e r v a l b y t z s s e t t i n g v a l u e i n t 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t ( n o t e 2 ) 0 : i n t 0 p i n o n e - s h o t t r i g g e r i n v a l i d 1 : i n t 0 p i n o n e - s h o t t r i g g e r v a l i d i n t 0 p i n o n e - s h o t t r i g g e r a c t i v e e d g e s e l e c t i o n b i t ( n o t e 2 ) 0 : f a l l i n g e d g e t r i g g e r 1 : r i s i n g e d g e t r i g g e r p r o c e s s 4 : s e t t z o u t p i n t o t h e o u t p u t ( n o t e ) . port p0 direction register (p0d) [address 01 16 ] s e t p 0 2 / t z o u t p i n a s t h e o u t p u t m o d e note: when using this mode, be sure to select write to latch only . p r o c e s s 1 : d i s a b l e t h e i n t e r r u p t . process 2: set timer y, z mode register. t i m e r y , z m o d e r e g i s t e r ( t y z m ) [ a d d r e s s 2 0 1 6 ] p r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e w r i t e t o o n l y l a t c h ( n o t e ) t i m e r y c o u n t s t o p i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] int 0 i nterrupt di sa bl e d process 3: set timer y, z waveform output control register. timer y, z waveform output control register (pum) [address 24 16 ] n o t e s 1 : t h e w a v e f o r m e x t e n s i o n f u n c t i o n b y t h e t i m e r z w a v e f o r m e x t e n s i o n c o n t r o l b i t s c a n b e u s e d o n l y w h e n 0 0 1 6 i s s e t t o p r e s c a l e r z . w h e n t h e v a l u e o t h e r t h a n 0 0 1 6 i s s e t t o p r e s c a l e r z , b e s u r e t o s e t 0 t o e x p z p . a l s o , w h e n t h e t i m e r y u n d e r f l o w i s s e l e c t e d a s t h e t i m e r z c o u n t s o u r c e , t h e w a v e f o r m e x t e n s i o n f u n c t i o n c a n n o t b e u s e d . 2 : s t o p t i m e r z t o c h a n g e t h e s e b i t s . i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 3 f 1 6 ] t i m e r z i n t e r r u p t d i s a b l e d
7540 group user s manual application 2-87 2.5 timer y and timer z fig. 2.5.30 setting method for programmable one-shot generation mode (2) prescaler z (prez) [address 25 16 ] ( note 2 ) p r o c e s s 8 : s e t t h e s t a n d b y s t a t e t o a c c e p t t h e o n e - s h o t s t a r t t r i g g e r ( n o t e ) . b 7b 0 0 timer y, z mode register (tyzm) [address 20 16 ] t i m e r z c o u n t s t a r t 0 11 process 7: set the one-shot pulse width ( note 1 ). s e t t h e c o u n t v a l u e t o p r e s c a l e r z a n d t i m e r z p r i m a r y c o u n t v a l u e c o u n t v a l u e timer z primary (tzp) [address 27 16 ] ( note 3 ) n o t e : w h e n t h e i n t 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t o f p u m i s s e t t o v a l i d , t i m e r z c o u n t i n g i s s t a r t e d b y t h e i n p u t o f t r i g g e r t o i n t 0 p i n a f t e r t h i s s e t t i n g . notes 1: in the programmable one-shot generation mode, tzs is not used. when the count setting value is changed, value of expzp is valid by writing to tzp. even when changing tzp is not required, write the same value again. 2: when the timer z waveform extension function is used, be sure to set 00 16 to prescaler z. 3: in the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer z underflow simultanesously. p r o c e s s 6 : s e t t h e t i m e r z c o u n t s o u r c e . b7 b0 t i m e r c o u n t s o u r c e s e t r e g i s t e r ( t c s s ) [ a d d r e s s 2 e 1 6 ] t i m e r z c o u n t s o u r c e s e l e c t i o n b i t s b 5 b 4 0 0 : f ( x i n ) / 1 6 0 1 : f ( x i n ) / 2 1 0 : t i m e r y u n d e r f l o w ( n o t e ) 1 1 : n o t a v a i l a b l e process 5: when the trigger by int 0 pin input is selected: set port p3 direction register, pull-up control register and port p1p3 control register p u l l - u p c o n t r o l r e g i s t e r ( p u l l ) [ a d d r e s s 1 6 1 6 ] p 3 7 p u l l - u p c o n t r o l b i t 0 : p u l l - u p o f f 1 : p u l l - u p o n b 7b 0 p o r t p 1 p 3 c o n t r o l r e g i s t e r ( p 1 p 3 c ) [ a d d r e s s 1 7 1 6 ] p 3 7 / i n t 0 i n p u t l e v e l s e l e c t i o n b i t 0 : c m o s l e v e l 1 : t t l l e v e l b 7b 0 0 p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) [ a d d r e s s 0 7 1 6 ] s e t p 3 7 / i n t 0 p i n a s t h e i n p u t m o d e b 7b 0 0 note: when the timer z waveform extension function is used, do not select the timer y underflow as the timer z count source.
7540 group user s manual 2-88 application 2.5 timer y and timer z fig. 2.5.31 setting method for programmable one-shot generation mode (3) b 7b 0 1 n o t e : p u l s e i s o u t p u t f r o m t z o u t p i n . a f t e r o u t p u t , t h i s b i t i s i n i t i a l i z e d t o 0 . b 7b 0 b 7b 0 0 b 7b 0 0 n o t e : w h e n t h e i n t 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t i s s e t t o v a l i d , t h e i n t 0 i n t e r r u p t c a n b e a c c e p t e d a f t e r t h i s s e t t i n g . b 7b 0 1 b 7b 0 1 w h e n t h e i n t 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t o f p u m i s s e t t o v a l i d , t h e t i m e r z c o u n t i s s t a r t e d b y i n p u t o f t r i g g e r t o t h e i n t 0 p i n . p r o c e s s 9 : i n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t 0 ( n o r e q u e s t e d ) t o t h e t i m e r z i n t e r r u p t r e q u e s t b i t . interrupt request register 2 (ireq2) [address 3d 16 ] p r o c e s s 1 0 : w h e n t h e i n t e r r u p t i s u s e d , s e t 1 ( i n t e r r u p t e n a b l e d ) t o t h e c o r r e s p o n d i n g i n t e r r u p t e n a b l e b i t . n o t i m e r z i n t e r r u p t r e q u e s t i s s u e d i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] i n t 0 i n t e r r u p t e n a b l e d ( n o t e ) o n e - s h o t s t a r t r e g i s t e r ( o n s ) [ a d d r e s s 2 a 1 6 ] t i m e r z o n e - s h o t s t a r t ( n o t e ) p r o c e s s 1 1 : s t a r t c o u n t i n g o f t i m e r z . interrupt edge selection register (intedge) [address 3a 16 ] i n t 0 i n t e r r u p t e d g e s e l e c t i o n b i t 0 : f a l l i n g e d g e a c t i v e 1 : r i s i n g e d g e a c t i v e interrupt request register 1 (ireq1) [address 3c 16 ] n o i n t 0 i n t e r r u p t r e q u e s t i s s u e d i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 3 f 1 6 ] t i m e r y i n t e r r u p t e n a b l e d w h e n t h e i n t 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t o f p u m i s s e t t o v a l i d a n d t h e i n t 0 i n t e r r u p t i s u s e d , s e t t h e f o l l o w i n g ;
7540 group user s manual application 2-89 2.5 timer y and timer z (3) application example of programmable one-shot generation mode outline: the phase control signal to the load is output by using the programmable one-shot generation mode of timer z. specifications: the phase control signal to the load is output from the p0 2 /tz out pin using the programmable one-shot generation mode of timer z. count source: f(x in )/16 rising edges of the signal input to the p3 7 /int 0 pin from the trigger detection circuit are detected. a triac is turned on at the h level. the period of the feedback signal input from the load is measured, analyzed, and used to adjust the phase control signal. operation clock: f(x in ) = 8 mhz, high-speed mode for the measurement of the period of the feedback signal, refer to the period measurement mode of the using timer. figure 2.5.32 shows an example of peripheral circuit, figure 2.5.33 shows an example of an operation timing, and figure 2.5.34 shows an example of a control procedure. fig. 2.5.32 example of peripheral circuit fig. 2.5.33 example of operation timing 7 5 4 0 g r o u p p 3 7 / int 0 p 0 2 / tz out v a c t r i gger d etect i on c i rcu i t p ort f e e d b a c k s i g n a l ph ase contro l s i gna l load int 0 pin input v ac power source c o n t e n t s o f t i m e r z tz out pin output rl r l r l rl r l u f uf uf u f u f uf w r i t i ng to l atc h i n int 0 interrupt processing routine 0 0 0 0 1 6 rl
7540 group user s manual 2-90 application 2.5 timer y and timer z fig. 2.5.34 example of control procedure timer z primary (address 27 16 ) prescaler z (address 25 16 ) 0 1 00 cli r e s e t 1 1 1 0 1 1 0 1 s e t p u l l - u p c o n t r o l r e g i s t e r s e t p o r t p 1 p 3 c o n t r o l r e g i s t e r 1 t y z m ( a d d r e s s 2 0 1 6 ) timer z count start ( note 7 ) s e t t h e s t a n d b y s t a t e t o a c c e p t o n e - s h o t s t a r t t r i g g e r 0 10 i n t e d g e ( a d d r e s s 3 a 1 6 ) i n t 0 r i s i n g e d g e a c t i v e s e t t h e i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r 1 p h a s e c o n t r o l p r o c e s s i n g p e r i o d m e a s u r e m e n t o f f e e d b a c k s i g n a l a n a l y z e o f m e a s u r e d v a l u e ( d e t e r m i n a t i o n o f t i m e r z s e t t i n g v a l u e ) int 0 interrupt processing routine c h a n g e o f t i m e r z r t i t i m e r z p r i m a r y w a v e f o r m g e n e r a t i o n e x t e n d e d ( n o t e 3 ) i n i t i a l s t a t e : l , t z p : h i n t e r v a l , t z s : l i n t e r v a l , s t o p a t l a f t e r u n d e r f l o w i n t 0 p i n o n e - s h o t t r i g g e r v a l i d ( n o t e 4 ) i n t 0 p i n r i s i n g e d g e t r i g g e r ( n o t e 4 ) p u m ( a d d r e s s 2 4 1 6 ) tcss(address 2e 16 ) t i m e r z c o u n t s o u r c e : f ( x i n ) / 1 6 s e l e c t e d s e t p o r t p 0 2 t o t h e o u t p u t m o d e . set 0 to the timer z interrupt enable bit. (timer z interrupt disabled) set value to timer z ( notes 3, 5, 6 ) set timer count source set register ( note 3 ) t y z m ( a d d r e s s 2 0 1 6 ) s e t t i m e r y , z m o d e r e g i s t e r p r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e w r i t i n g t o o n l y l a t c h ( n o t e 2 ) t i m e r z c o u n t s t o p s e t 1 t o t h e i n t 0 i n t e r r u p t e n a b l e b i t . ( i n t 0 i n t e r r u p t e n a b l e d ) s e t 0 t o t h e i n t 0 i n t e r r u p t r e q u e s t b i t . i n i t i a l i z a t i o n s e i c l d c l t c p u m ( a d d r e s s 3 b 1 6 ) 1 0 0 0 0 x 0 0 2 w a i t u n t i l f ( x i n ) o s c i l l a t i o n i s s t a b i l i z e d ( n o t e 1 ) c p u m ( a d d r e s s 3 b 1 6 ) 0 0 0 0 0 x 0 0 2 s e t t i m e r y , z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r x : t h i s b i t i s n o t u s e d h e r e . s e t i t t o 0 o r 1 a r b i t r a r y . set port p3 7 to the input mode. n o t e s 1 : f o r t h e c o n c r e t e t i m e , a s k t h e o s c i l l a t o r m a n u f a c t u r e . 2 : w h e n u s i n g t h i s m o d e , b e s u r e t o s e l e c t w r i t e t o l a t c h o n l y . 3 : t h e w a v e f o r m e x t e n s i o n f u n c t i o n b y t h e t i m e r z w a v e f o r m e x t e n s i o n c o n t r o l b i t s c a n b e u s e d o n l y w h e n 0 0 1 6 i s s e t t o p r e s c a l e r z . w h e n t h e v a l u e o t h e r t h a n 0 0 1 6 i s s e t t o p r e s c a l e r z , b e s u r e t o s e t 0 t o e x p z p . a l s o , w h e n t h e t i m e r y u n d e r f l o w i s s e l e c t e d a s t h e t i m e r z c o u n t s o u r c e , t h e w a v e f o r m e x t e n s i o n f u n c t i o n c a n n o t b e u s e d . 4 : s t o p t i m e r z t o c h a n g e t h e i n t 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t a n d i n t 0 o n e - s h o t t r i g g e r a c t i v e e d g e s e l e c t i o n b i t . 5 : i n t h e p r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e , t h e v a l u e o f e x p z p i s v a l i d b y w r i t i n g t o t z p . e v e n w h e n c h a n g i n g t z p i s n o t r e q u i r e d , w r i t e t h e s a m e v a l u e a g a i n . 6 : i n t h e p r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e , w h e n t h e s e t t i n g v a l u e i s c h a n g e d w h i l e t h e w a v e f o r m i s o u t p u t , s e t b y s o f t w a r e i n o r d e r n o t t o e x e c u t e t h e w r i t i n g t o t z p a n d t h e t i m i n g o f t i m e r z u n d e r f l o w s i m u l t a n e s o u s l y . 7 : i n t h i s s t a t e , t i m e r c o u n t i s n o t s t a r t e d .
7540 group user s manual application 2-91 2.5 timer y and timer z 2.5.6 programmable wait one-shot generation mode (timer z) (1) operation description in the programmable wait one-shot generation mode, the one-shot pulse by the setting value of timer z secondary (tzs) can be output from p0 2 /tz out pin by software or external trigger to p3 7 /int 0 pin after the wait by the setting value of the timer z primary (tzp). when using this mode, be sure to set 1 to the timer z write control bit to select write to latch only . also, set the port p0 2 direction registers to output mode. the active edge of output waveform is set by the timer z output level latch. when 0 is set to the timer z output level latch, after the wait during the interval of the tzp setting value, h pulse during the interval of the tzs setting value is output. when 1 is set to the timer z output level latch, after the wait during the interval of the tzp setting value, l pulse during the interval of the tzs setting value is output. also, in this mode, the intervals of the wait and the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting the timer z primary waveform extension control bit (expzp) and the timer z secondary waveform extension control bit (expzs) to 1 . as a result, the waveforms of more accurate resolution can be output. in the programmable wait one-shot generation mode, the trigger by software or the external int 0 pin can be accepted by writing 0 to the timer z count stop bit after the count value is set. (at the time when 0 is written to the timer z count stop bit, timer z stops.) by writing 1 to the timer z one-shot start bit, or by inputting the valid trigger to the int 0 pin after the trigger to the int 0 pin becomes valid by writing 1 to the int 0 pin one-shot trigger control bit, timer z starts counting. while timer z counts the tzp, the initial value of the tz out pin output is retained. when timer z underflows, the value of tzs is reloaded, at the same time, the output of tz out pin is inverted. when timer z underflows, the output of tz out pin is inverted again and timer z stops. when also the trigger of int 0 pin is accepted, the contents of the one-shot start bit is changed to 1 by hardware. the falling or rising can be selected as the edge of the valid trigger of int 0 pin by the int 0 pin one- shot trigger edge selection bit. during the wait interval and the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing 0 to the timer z one-shot start bit. in the programmable wait one-shot generation mode, when the count values are changed, set values to the tzs, expzp and expzs first. after then, set the value to tzp. the values are set all at once at the beginning of the next wait interval when the value is set to tzp. (when writing at timer stop is executed, writing to tzp at last is required.) timer z can stop counting by setting 1 to the timer z count stop bit. also, when timer z underflows, the timer z interrupt request bit is set to 1 . timer z reloads the value of latch when counting is stopped by the timer z count stop bit. (when timer is read out while timer is stopped, the value of latch is read. the value of timer can be read out only while timer is operating.)
7540 group user s manual 2-92 application 2.5 timer y and timer z notes 1: in the programmable wait one-shot generation mode, values of tzs, expzp and expzs are valid by writing to tzp. even when changing tzp is not required, write the same value again. 2: in the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer underflow during the secondary interval simultaneously. an example of a measurement is shown below. ex.) the underflow by the primary and the underflow by secondary are stored by polling etc. using timer z interrupt. writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (depending on a primary setting value, primary write timing, software and timing of external trigger to int 0 pin, it may be impossible.) 3: the waveform extension function by the timer z waveform extension control bits can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp and expzs. also, when the timer y underflow is selected as the timer z count source, the waveform extension function cannot be used. 4: when using this mode, be sure to set 1 to the timer z write control bit to select write to latch only . 5: when tzs is read out, the undefined value is read out. however, while timer z counts the setting value of tzs (during one-shot output), the count value during the secondary interval can be obtained by reading tzp. 6: in order to use tz out pin, set 1 to bit 2 of the port p0 direction register (output mode). 7: stop timer z to change the int 0 pin one-shot trigger control bit and int 0 pin one-shot trigger active edge selection bit. figure 2.5.35 shows the timing diagram of the programmable wait one-shot generation mode.
7540 group user s manual application 2-93 2.5 timer y and timer z fig. 2.5.35 timing diagram of programmable wait one-shot generation mode 0 2 1 6 0 3 1 6 01 16 0 0 1 6 0 3 1 6 0 2 1 6 01 16 0 0 1 6 w a i t s t a r t 03 16 0 4 1 6 ( note 3 ) ( note 3 ) o n e - s h o t s t a r t b i t i n t 0 p i n i n p u t ( n o t e 1 ) s e t t o 1 b y i n t 0 p i n i n p u t t r i g g e r c o n t e n t s o f t i m e r z t z o u t p i n o u t p u t timer z count clock t i m e r z c o u n t s t o p b i t t i m e r z i n t e r r u p t r e q u e s t b i t t i m e r z o u t p u t l e v e l l a t c h 0 i s w r i t t e n c o u n t s t a r t w h e n 0 3 1 6 i s s e t t o t z p a n d 0 4 1 6 i s s e t t o t z s . underflow timer z secondary reload initialized to l n o t e s 1 : i n t h i s c a s e , i n t 0 p i n o n e - s h o t t r i g g e r v a l i d ( r i s i n g e d g e t r i g g e r s e l e c t e d ) . 2 : i n t h i s c a s e , t i m e r z p r i m a r y w a v e f o r m i s e x t e n d e d , t i m e r z s e c o n d a r y w a v e f o r m i s n o t e x t e n d e d . 3 : i n t h i s t i m e , 0 i s w r i t t e n t o t h e t i m e r z i n t e r r u p t r e q u e s t b i t o r t h e t i m e r z i n t e r r u p t r e q u e s t b i t i s c l e a r e d t o 0 b y a c c e p t i n g t h e t i m e r z i n t e r r u p t r e q u e s t . ( n o t e 2 ) 0 is written 1 i s w r i t t e n u n d e r f l o w timer z primary reload c o u n t s t a r t w a v e f o r m e x t e n s i o n w a v e f o r m o u t p u t e n d waveform output start
7540 group user s manual 2-94 application 2.5 timer y and timer z fig. 2.5.36 setting method for programmable wait one-shot generation mode (1) b7 b0 1 b 7b 0 1 1 1 1 b7 b0 b 7b 0 0 b 7b 0 0 ti mer z pr i mary wave f orm extens i on contro l bi t ( n ote 1 ) 0: waveform not extended 1: waveform extended timer z secondary waveform extension control bit ( note 1 ) 0: waveform not extended 1: waveform extended timer z output level latch 0: l level is output at timer stop. when count is started, l level is output during the tzp interval (wait), and them, h level is output during the tzs interval (one-shot) and timer z output is stopped at l level by underflow. 1: h level is output at timer stop. when count is started, h level is output during the tzp interval (wait), and them, l level is output during the tzs interval (one-shot) and timer z output is stopped at h level by underflow. int 0 pin one-shot trigger control bit ( note 2 ) 0: int 0 pin one-shot trigger invalid 1: int 0 pin one-shot trigger valid int 0 pin one-shot trigger active edge selection bit ( note 2 ) 0: falling edge trigger 1: rising edge trigger p r o c e s s 4 : s e t t z o u t p i n t o t h e o u t p u t . port p0 direction register (p0d) [address 01 16 ] s e t p 0 2 / t z o u t p i n a s t h e o u t p u t m o d e note: when using this mode, be sure to select write to latch only . p r o c e s s 1 : d i s a b l e i n t e r r u p t . p r o c e s s 2 : s e t t i m e r y , z m o d e r e g i s t e r . t i m e r y , z m o d e r e g i s t e r ( t y z m ) [ a d d r e s s 2 0 1 6 ] p r o g r a m m a b l e w a i t o n e - s h o t g e n e r a t i o n m o d e w r i t e t o o n l y l a t c h ( n o t e ) t i m e r y c o u n t s t o p i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] i n t 0 i n t e r r u p t d i s a b l e d process 3: set timer y, z waveform output control register. t i m e r y , z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r ( p u m ) [ a d d r e s s 2 4 1 6 ] n o t e s 1 : t h e w a v e f o r m e x t e n s i o n f u n c t i o n b y t h e t i m e r z w a v e f o r m e x t e n s i o n c o n t r o l b i t s c a n b e u s e d o n l y w h e n 0 0 1 6 i s s e t t o p r e s c a l e r z . w h e n t h e v a l u e o t h e r t h a n 0 0 1 6 i s s e t t o p r e s c a l e r z , b e s u r e t o s e t 0 t o e x p z p a n d e x p z s . a l s o , w h e n t h e t i m e r y u n d e r f l o w i s s e l e c t e d a s t h e t i m e r z c o u n t s o u r c e , t h e w a v e f o r m e x t e n s i o n f u n c t i o n c a n n o t b e u s e d . 2 : s t o p t i m e r z t o c h a n g e t h e s e b i t s . interrupt control register 2 (icon2) [address 3f 16 ] t i m e r z i n t e r r u p t d i s a b l e d (2) programmable wait one-shot generation mode setting method figure 2.5.36 to figure 2.5.38 show the setting method for programmable wait one-shot generation mode of timer z.
7540 group user s manual application 2-95 2.5 timer y and timer z fig. 2.5.37 setting method for programmable wait one-shot generation mode (2) b7 b 0 b7 b 0 b7 b 0 0 b7 b 0 0 prescaler z (prez) [address 25 16 ] ( note 2 ) process 7: set the wait interval, one-shot pulse width ( note 1 ). set the wait interval to the timer z primary, and one-shot pulse width to the timer z secondary. c ount va l ue c o u n t v a l u e t i m e r z s e c o n d a r y ( t z s ) [ a d d r e s s 2 6 1 6 ] notes 1: in the programmable wait one-shot generation mode, values of tzs, expzp, and expzs are valid by writing to tzp. even when changing tzp is not required, write the same value again. 2: when the timer z waveform extension function is used, be sure to set 00 16 to prescaler z. 3: in the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer z underflow during the secondary interval simultanesously. 4: count values of the primary interval (during wait) and secondary interval (during one-shot output) can be checked by reading tzp (tzs is undefined at read). p r o c e s s 6 : s e t t h e t i m e r z c o u n t s o u r c e . t i m e r c o u n t s o u r c e s e t r e g i s t e r ( t c s s ) [ a d d r e s s 2 e 1 6 ] t i m e r z c o u n t s o u r c e s e l e c t i o n b i t s b 5 b 4 0 0 : f ( x i n ) / 1 6 0 1 : f ( x i n ) / 2 1 0 : t i m e r y u n d e r f l o w ( n o t e ) 1 1 : n o t a v a i l a b l e p r o c e s s 5 : w h e n t h e t r i g g e r b y i n t 0 p i n i n p u t i s s e l e c t e d : s e t p o r t p 3 d i r e c t i o n r e g i s t e r , p u l l - u p c o n t r o l r e g i s t e r a n d p o r t p 1 p 3 c o n t r o l r e g i s t e r pull-up control register (pull) [address 16 16 ] p 3 7 / i n t 0 p u l l - u p c o n t r o l b i t 0 : p u l l - u p o f f 1 : p u l l - u p o n port p1p3 control register (p1p3c) [address 17 16 ] p 3 7 / i n t 0 i n p u t l e v e l s e l e c t i o n b i t 0 : c m o s l e v e l 1 : t t l l e v e l p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) [ a d d r e s s 0 7 1 6 ] s e t p 3 7 / i n t 0 p i n t o t h e i n p u t m o d e note: when the timer z waveform extension function is used, do not select the timer y underflow for the timer z count source. c o u n t v a l u e t i m e r z p r i m a r y ( t z p ) [ a d d r e s s 2 7 1 6 ]
7540 group user s manual 2-96 application 2.5 timer y and timer z fig. 2.5.38 setting method for programmable wait one-shot generation mode (3) b 7b0 01 11 b 7b0 b7 b 0 0 b 7b0 0 b 7b 0 1 b7 b0 1 b 7b 0 1 p r o c e s s 8 : s e t t h e s t a n d b y s t a t e t o a c c e p t t h e o n e - s h o t s t a r t t r i g g e r ( n o t e ) . t i m e r y , z m o d e r e g i s t e r ( t y z m ) [ a d d r e s s 2 0 1 6 ] t i m e r z c o u n t s t a r t n o t e : w h e n t h e i n t 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t o f p u m i s s e t t o v a l i d , t i m e r z c o u n t i n g i s s t a r t e d b y t h e i n p u t o f t r i g g e r t o i n t 0 p i n a f t e r t h i s s e t t i n g . n o t e : p u l s e i s o u t p u t f r o m t z o u t p i n . a f t e r o u t p u t , t h i s b i t i s i n i t i a l i z e d t o 0 . note: when the int 0 pin one-shot trigger control bit is set to valid , the int 0 interrupt can be accepted after this setting. w h e n t h e i n t 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t o f p u m i s s e t t o v a l i d , t h e t i m e r z c o u n t i s s t a r t e d b y i n p u t o f t r i g g e r t o t h e i n t 0 p i n . p r o c e s s 9 : i n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t 0 ( n o r e q u e s t e d ) t o t h e t i m e r z i n t e r r u p t r e q u e s t b i t . i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 3 d 1 6 ] process 10: when the interrupt is used, set 1 (interrupt enabled) to the corresponding interrupt enable bit. n o t i m e r z i n t e r r u p t r e q u e s t i s s u e d i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] int 0 i nterrupt ena bl e d ( n ote ) o n e - s h o t s t a r t r e g i s t e r ( o n s ) [ a d d r e s s 2 a 1 6 ] ti mer z one-s h ot start ( n ote ) p r o c e s s 1 1 : s t a r t c o u n t i n g o f t i m e r z . interrupt edge selection register (intedge) [address 3a 16 ] i n t 0 i n t e r r u p t e d g e s e l e c t i o n b i t 0 : f a l l i n g e d g e a c t i v e 1 : r i s i n g e d g e a c t i v e i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 3 c 1 6 ] n o i n t 0 i n t e r r u p t r e q u e s t i s s u e d interrupt control register 2 (icon2) [address 3f 16 ] t i m e r z i n t e r r u p t e n a b l e d when the int 0 pin one-shot trigger control bit is set to valid and the int 0 interrupt is used, set the following;
7540 group user s manual application 2-97 2.5 timer y and timer z (3) application example of programmable wait one-shot generation mode outline : the wait one-shot pulse synchronized with the pwm waveform output from the p0 1 /ty out pin is generated from timer z by using the programmable waveform generation mode of timer y. specifications :ty out pin is connected to the p3 7 /int 0 pin. the wait one-shot pulse is output by the int 0 pin input as trigger. operation clock: f(x in ) = 8 mhz, high-speed mode as for the usage of timer y, refer to the above mentioned programmable waveform generation mode. figure 2.5.39 shows an example of waveform generation and peripheral circuit. figure 2.5.40 shows an example of control procedure. fig. 2.5.39 example of waveform generation and peripheral circuit 7540 group p 3 7 / i n t 0 p 0 2 / tz out p 0 1 / ty out timer z active timer z active timer z active
7540 group user s manual 2-98 application 2.5 timer y and timer z fig. 2.5.40 example of control procedure 0 1 w a i t o n e - s h o t g e n e r a t i o n r o u t i n e 1 1 1 1 1 1 1 0 1 0 11 int 0 rising edge active 1 t i m e r z i n t e r r u p t p r o c e s s i n g r o u t i n e rti 0 rts t i m e r z p r i m a r y ( a d d r e s s 2 7 1 6 ) prescaler z (address 25 16 ) set pull-up control register set port p1p3 control register tyzm(address 20 16 ) t i m e r z c o u n t s t a r t ( n o t e 7 ) s e t t h e s t a n d b y s t a t e t o a c c e p t o n e - s h o t s t a r t t r i g g e r i n t e d g e ( a d d r e s s 3 a 1 6 ) s e t i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r change of timer z ti mer z pr i mary wave f orm generation not extended ( note 2 ) timer z secondary waveform generation not extended ( note 2 ) initial state: tzp: h interval, tzs: l interval after underflow stop at h after underflow int 0 pin one-shot trigger valid ( note 3 ) int 0 pin rising edge trigger ( note 3 ) pum(address 24 16 ) t c s s ( a d d r e s s 2 e 1 6 ) t i m e r z c o u n t s o u r c e s e l e c t e d s e t p o r t p 0 2 t o t h e o u t p u t m o d e . s e t 0 t o t h e t i m e r z i n t e r r u p t e n a b l e b i t . ( t i m e r z i n t e r r u p t d i s a b l e d ) s e t v a l u e t o t i m e r z ( n o t e s 2 , 4 , 5 , 6 ) s e t t i m e r c o u n t s o u r c e s e t r e g i s t e r ( n o t e 3 ) t y z m ( a d d r e s s 2 0 1 6 ) s e t t i m e r y , z m o d e r e g i s t e r programmable wait one-shot generation mode writing to only latch ( note 2 ) timer z count stop s e t 1 t o t h e t i m e r z i n t e r r u p t e n a b l e b i t . ( t i m e r z i n t e r r u p t e n a b l e d ) s e t 0 t o t h e i m e r z i n t e r r u p t r e q u e s t b i t . s e t t i m e r y , z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r set port p3 7 to the input mode. notes 1: when using this mode, be sure to select write to latch only . 2: the waveform extension function by the timer z waveform extension control bits can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp and expzs. also, when the timer y underflow is selected as the timer z count source, the waveform extension function cannot be used. 3: stop timer z to change the int 0 pin one-shot trigger control bit and int 0 one-shot trigger active edge selection bit. 4: in the programmable wait one-shot generation mode, values of tzs, expzp, and expzs are valid by writing to tzp. even when changing tzp is not required, write the same value again. 5: in the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer z underflow simultanesously. 6: count values of the primary interval (during wait) and secondary interval (during one-shot output) can be checked by reading tzp (tzs is undefined at read). 7: in this state, timer count is not started. t i m e r z s e c o n d a r y ( a d d r e s s 2 6 1 6 )
7540 group user s manual application 2-99 2.5 timer y and timer z 2.5.7 notes on timer y and timer z notes on using each mode of timer y and timer z are described below. (1) timer mode (timer y and timer z) ? in the timer mode, typ and tys is not used. (2) programmable waveform generation mode (timer y and timer z) ? in the programmable waveform generation mode, values of tys, expyp, and expys are valid by writing to typ because the setting to them is executed all at once by writing to typ. even when changing typ is not required, write the same value again. ? in the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to typ and the timing of timer underflow during the secondary interval simultaneously. an example of a measurement is shown below. ex.) the underflow by the primary and the underflow by secondary are stored by polling etc. using timer y interrupt. writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (depending on a primary and a secondary setting values, and primary write timing, it may be impossible.) ? the waveform extension function by the timer y waveform extension control bits can be used only when 00 16 is set to prescaler y. when the value other than 00 16 is set to prescaler y, be sure to set 0 to expyp and expys. the waveform extension function by the timer z waveform extension control bits can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp and expzs. also, when the timer y underflow is selected as the timer z count source, the waveform extension function cannot be used. ? when using this mode, be sure to set 1 to the timer y write control bit to select write to latch only . ? when tys is read out, the undefined value is read out. however, while timer y counts the setting value of tys, the count value during the secondary interval can be obtained by reading the timer y primary. ? in order to use ty out pin, set 1 to bit 1 of the port p0 direction register (output mode). (3) programmable one-shot generation mode (timer z) ? in the programmable one-shot generation mode, the value of expzp becomes valid by writing to tzp. even when changing tzp is not required, write the same value again. ? in the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer underflow simultaneously.
7540 group user s manual 2-100 application 2.5 timer y and timer z ? the waveform extension function by the timer z waveform extension control bits can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp. also, when the timer y underflow is selected as the timer z count source, the waveform extension function cannot be used. an example of a measurement is shown below. ex.) the underflow of timer is stored by polling etc. using timer z interrupt. writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (depending on a primary setting value, primary write timing, software and timing of external trigger to int 0 pin, it may be impossible.) ? when using this mode, be sure to set 1 to the timer z write control bit to select write to latch only . ? in order to use tz out pin, set 1 to bit 2 of the port p0 direction register (output mode). ? stop timer z to change the int 0 pin one-shot trigger control bit and int 0 pin one-shot trigger active edge selection bit. (4) programmable wait one-shot generation mode (timer z) ? in the programmable wait one-shot generation mode, values of tzs, expzp and expzs are valid by writing to tzp. even when changing tzp is not required, write the same value again. an example of a measurement is shown below. ex.) the underflow by the primary and the underflow by secondary are stored by polling etc. using timer z interrupt. writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (depending on a primary setting value, primary write timing, software and timing of external trigger to int 0 pin, it may be impossible.) ? in the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer underflow during the secondary interval simultaneously. ? the waveform extension function by the timer z waveform extension control bit can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp and expzs. also, when the timer y underflow is selected as the timer z count source, the waveform extension function cannot be used. ? when using this mode, be sure to set 1 to the timer z write control bits to select write to latch only . ? when tzs is read out, the undefined value is read out. however, while timer z counts the setting value of tzs (during one-shot output), the count value during the secondary interval can be obtained by reading tzp. ? in order to use tz out pin, set 1 to bit 2 of the port p0 direction register (output mode). ? stop timer z to change the int 0 pin one-shot trigger control bit and int 0 pin one-shot trigger active edge selection bit.
7540 group user? manual application 2-101 2.6 serial i/o1 2.6 serial i/o1 this paragraph explains the registers setting method and the notes relevant to the serial i/o. 2.6.1 memory map fig. 2.6.1 memory map of registers relevant to serial i/o 2.6.2 relevant registers fig. 2.6.2 structure of transmit/receive buffer register 0018 16 0019 16 001a 16 001b 16 001c 16 003c 16 transmit/receive buffer register (tb/rb) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart control register (uartcon) baud rate generator (brg) interrupt request register 1 (ireq1) 003e 16 interrupt control register 1 (icon1) transmit/receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? transmit/receive buffer register (tb/rb) [address : 18 16 ] the transmission data is written to or the receive data is read out from this buffer register. at writing: a data is written to the transmit buffer register. at reading: the contents of the receive buffer register are read out. note: the contents of transmit buffer register cannot be read out. the data cannot be written to the receive buffer register.
7540 group user s manual 2-102 application 2.6 serial i/o1 fig. 2.6.3 structure of serial i/o1 status register fig. 2.6.4 structure of serial i/o1 control register serial i/o1 status register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 1 serial i/o1 status register (sio1sts) [address : 19 16 ] nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 1 . ? ? ? ? ? ? ? ? transmit buffer empty flag (tbe) 0 : (oe) (pe) (fe) = 0 1 : (oe) (pe) (fe) = 1 overrun error flag (oe) 0 : buffer full 1 : buffer empty receive buffer full flag (rbf) transmit shift register shift completion flag (tsc) parity error flag (pe) framing error flag (fe) summing error flag (se) 0 : buffer empty 1 : buffer full 0 : transmit shift in progress 1 : transmit shift completed 0 : no error 1 : overrun error 0 : no error 1 : parity error 0 : no error 1 : framing error serial i/o1 control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 serial i/o1 control register (sio1con) [address : 1a 16 ] 0 : f(x in ) 1 : f(x in )/4 brg count source selection bit (css) 0 0 : transmit disabled 1 : transmit enabled 0 : receive disabled 1 : receive enabled transmit interrupt source selection bit (tic) transmit enable bit (te) receive enable bit (re) serial i/o1 enable bit (sioe) 0 : interrupt when transmit buffer has emptied 1 : interrupt when transmit shift operation is completed 0: serial i/o1 disabled 1: serial i/o1 enabled serial i/o1 synchronous clock selection bit (scs) when clock synchronous serial i/o is selected; 0: brg output divided by 4 1: external clock input when uart is selected; 0: brg output divided by 16 1: external clock input divided by 16 0 s rdy1 output enable bit (srdy) 0: p1 3 pin 1: s rdy1 output pin serial i/o1 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o
7540 group user s manual application 2-103 2.6 serial i/o1 fig. 2.6.5 structure of uart control register fig. 2.6.6 structure of baud rate generator b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 1 u a r t c o n t r o l r e g i s t e r ( u a r t c o n ) [ a d d r e s s : 1 b 1 6 ] n o t h i n g i s a l l o c a t e d f o r t h e s e b i t s . t h e s e a r e w r i t e d i s a b l e d b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 1 . ? ? ? u a r t c o n t r o l r e g i s t e r c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) p a r i t y e n a b l e b i t ( p a r e ) s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) p a r i t y s e l e c t i o n b i t ( p a r s ) i n o u t p u t m o d e 0 : c m o s o u t p u t 1 : n - c h a n n e l o p e n - d r a i n o u t p u t 0 : 8 bits 1 : 7 bits 0 : parity checking disabled 1 : parity checking enabled 0 : 1 stop bit 1 : 2 stop bits 0 : even parity 1 : odd parity p 1 1 / t x d p - c h a n n e l o u t p u t d i s a b l e b i t ( p o f f ) 1 1 0 baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? baud rate generator (brg) [address : 1c 16 ] set a count value of baud rate generator.
7540 group user s manual 2-104 application 2.6 serial i/o1 fig. 2.6.7 structure of interrupt request register 1 fig. 2.6.8 structure of interrupt control register 1 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 1 (ireq1) [address : 3c 16 ] serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued cntr 0 interrupt request bit cntr 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued int 0 interrupt request bit int 1 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued key-on wake up interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? timer x interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ? interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 1 (icon1) [address : 3e 16 ] serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled cntr 0 interrupt enable bit cntr 1 interrupt enable bit int 0 interrupt enable bit int 1 interrupt enable bit key-on wake up interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer x interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled
7540 group user s manual application 2-105 2.6 serial i/o1 2.6.3 serial i/o1 transfer data format figure 2.6.9 shows the serial i/o1 transfer data format. fig. 2.6.9 serial i/o1 transfer data format 1st-8data-1sp s t l s b s e r i a l i / o 1 uart clock synchronous serial i/o 1 s t - 7 d a t a - 1 s p s t l s b 1st-8data-1par-1sp st lsb 1 s t - 7 d a t a - 1 p a r - 1 s p s t l s b 1 s t - 8 d a t a - 2 s p st lsb 1st-7data-2sp st lsb 1 s t - 8 d a t a - 1 p a r - 2 s p s t l s b 1 s t - 7 d a t a - 1 p a r - 2 s p st lsb m s b sp m s b sp msb p a r sp m s b par sp msb 2 sp msb 2 sp m s b p a r 2 sp msb par 2 sp l s b f i r s t s t : s t a r t b i t s p : s t o p b i t p a r : p a r i t y b i t
7540 group user s manual 2-106 application 2.6 serial i/o1 2.6.4 application example of clock synchronous serial i/o1 for clock synchronous serial i/o1, the transmitter and the receiver use the same clock. synchronizing with this clock, the transmit operation of the transmitter and the receive operation of the receiver are executed at the same time. if an internal clock is used as the operation clock, transfer is started by a write signal to the tb/rb. (1) data transfer rate the synchronous clock frequency is calculated by the following formula; when the internal clock is selected (when baud rate generator is used) synchronous clock frequency [hz] = division ratio* 1 : 1 or 4 is selected (set by bit 0 of serial i/o1 control register) brg setting value* 2 : 0 to 255 (00 16 to ff 16 ) is set when the external clock is selected synchronous clock frequency [hz] = clock input to s clk1 pin f(x in ) division ratio * 1 ? (brg setting value * 2 + 1) ? 4
7540 group user s manual application 2-107 2.6 serial i/o1 fig. 2.6.10 setting method for clock synchronous serial i/o1 (1) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] b 7b 0 s e r i a l i / o 1 r e c e i v e i n t e r r u p t d i s a b l e d s e r i a l i / o 1 t r a n s m i t i n t e r r u p t d i s a b l e d 0 b a u d r a t e g e n e r a t o r ( b r g ) [ a d d r e s s 1 c 1 6 ] s et b au d rate va l ue b 7b 0 0 0 p r o c e s s 1 : s t o p a n d i n i t i a l i z e s e r i a l i / o . s e r i a l i / o 1 c o n t r o l r e g i s t e r ( s i o 1 c o n ) [ a d d r e s s 1 a 1 6 ] t r a n s m i t o p e r a t i o n s t o p a n d i n i t i a l i z e d r e c e i v e o p e r a t i o n s t o p a n d i n i t i a l i z e d 0 brg count source se l ecte d ( set i n i nterna l c l oc k se l ecte d) 0: f(x in ) 1: f(x in )/4 serial i/o1 synchronous clock selected 0: brg output/4 ( note 1 ) 1: external clock input s rdy1 output enable selected 0: p1 3 pin operates as normal i/o pin 1: p1 3 pin operates as s rdy1 output pin ( note 2 ) transmit interrupt source selected 0: when transmit buffer has emptied 1: when transmit shift operation is completed transmit enable selected 0: transmit disabled (at half-duplex communication receive) 1: transmit enabled (at full-duplex communication) ( note 3 ) receive enable selected 0: receive disabled (at half-duplex communication transmit) 1: receive enabled (at full-duplex communication) ( note 3 ) clock synchronous serial i/o serial i/o1 enabled (p1 0 p1 3 pins operate as serial i/o1 pins) s e r i a l i / o 1 c o n t r o l r e g i s t e r ( s i o 1 c o n ) [ a d d r e s s 1 a 1 6 ] p r o c e s s 3 : s e t s e r i a l i / o 1 c o n t r o l r e g i s t e r . b 7b 0 1 1 notes 1: setting of serial i/o1 synchronous selection bit is as follows: 0 : p1 2 pin is set to be an output pin of the synchronous clock. 1 : p1 2 pin is set to be an input pin of the synchronous clock. 2: when an external clock input is selected as the synchronous clock, and the receiver performs the s rdy1 output, set 1 to the transmit enable bit in addition to the receive enable bit and s rdy1 output enable bit. 3: when data transmission is executed at the state that an external clock input is selected as the synchronous clock, set 1 to the transmit enable bit while the s clk1 is h state. p r o c e s s 2 : d i s a b l e s e r i a l i / o 1 t r a n s m i t / r e c e i v e i n t e r r u p t . process 4: when brg output/4 is selected as synchronous clock, set value to baud rate generator. (2) clock synchronous serial i/o setting method figure 2.6.10 and figure 2.6.11 show the setting method for the clock synchronous serial i/o1.
7540 group user s manual 2-108 application 2.6 serial i/o1 fig. 2.6.11 setting method for clock synchronous serial i/o1 (2) p r o c e s s 7 : t r a n s m i t / r e c e i v e o f s e r i a l d a t a ( n o t e s 1 , 2 ) . transmit/receive buffer register (tb/rb) [address 18 16 ] b 7b 0 00 b 7b 0 1 1 s et transm i t d ata (i n f u ll - d up l ex commun i cat i on ) set dummy data (in half-duplex communication) p r o c e s s 5 : i n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t 0 ( n o r e q u e s t e d ) t o t h e s e r i a l i / o 1 t r a n s m i t / r e c e i v e i n t e r r u p t r e q u e s t b i t . i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 3 c 1 6 ] n o s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t i s s u e d n o s e r i a l i / o 1 t r a n s m i t i n t e r r u p t r e q u e s t i s s u e d s e r i a l i / o 1 r e c e i v e i n t e r r u p t e n a b l e d s e r i a l i / o 1 t r a n s m i t i n t e r r u p t e n a b l e d i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] p r o c e s s 6 : w h e n t h e i n t e r r u p t i s u s e d , s e t 1 ( i n t e r r u p t e n a b l e d ) t o t h e s e r i a l i / o t r a n s m i t / r e c e i v e i n t e r r u p t e n a b l e b i t . notes 1: when data transmission is executed at the state that an external clock input is selected as the synchronous clock, set the transmit data while the s clk is h state. 2: when inputting the s rdy1 signal, set used pins to to the input mode before transmitting data.
7540 group user s manual application 2-109 2.6 serial i/o1 (3) communication using clock synchronous serial i/o1 (transmit/receive) outline : 2-byte data is transmitted and received, using the clock synchronous serial i/o1. s rdy1 signal is used for communication control. specifications : the serial i/o1 (clock synchronous serial i/o selected ) is used. synchronous clock frequency : 125 khz; f(x in ) = 4 mhz divided by 32 the receiver outputs the s rdy1 signal at 2 ms intervals which the timer generates, and 2-byte data is transferred from the transmitter to the receiver. figure 2.6.12 shows a connection diagram, figure 2.6.13 shows a timing chart, figure 2.6.14 shows the control procedure of transmitter, and figure 2.6.15 shows an example of control procedure of receiver. fig. 2.6.12 connection diagram fig. 2.6.13 timing chart s r d y 1 s c l k 1 t x d d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 2ms . . . . . . . . . . . . . . . t r a n s m i t t e r p3 7 /int 0 s clk1 t x d 1 7 5 4 0 g r o u p s rdy1 s clk1 r x d 1 receiver 7540 group
7540 group user s manual 2-110 application 2.6 serial i/o1 fig. 2.6.14 control procedure of transmitter s i o 1 c o n ( a d d r e s s 1 a 1 6 ) b r g c o u n t s o u r c e : f ( x i n ) s y n c h r o n o u s c l o c k : b r g o u t p u t / 4 p 1 3 p i n ( n o r m a l i / o p i n ) t r a n s m i t i n t e r r u p t s o u r c e : w h e n t r a n s m i t b u f f e r h a s e m p t i e d t r a n s m i t e n a b l e d r e c e i v e d i s a b l e d c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o 1 e n a b l e d s e t s e r i a l i / o 1 c o n t r o l r e g i s t e r 0 00 b r g ( a d d r e s s 1 c 1 6 ) set baud rate generator 1 i n t 0 f a l l i n g e d g e i n p u t ? y n i n i t i a l i z a t i o n reset s e i c l d c l t 11 00 07 16 intedge(address 3a 16 ) i n t 0 f a l l i n g e d g e a c t i v e set int 0 interrupt active edge 0 t b / r b ( a d d r e s s 1 8 1 6 ) write the first-byte transmission data to the transmit/receive buffer register transmit buffer has emptied ? (checked by b0 of sio1sts (address 19 16 )) y n tb/rb(address 18 16 ) y n n y write the second-byte transmission data to the transmit/receive buffer register transmit buffer has emptied ? (checked by b0 of sio1sts (address 19 16 )) transmit shift has completed ? (checked by b2 of sio1sts (address 19 16 ))
7540 group user s manual application 2-111 2.6 serial i/o1 fig. 2.6.15 control procedure of receiver 1 1 1 2 ms elapsed ? (generated by timer) y n r e s e t s e i c l d c l t 11 1 set dummy data to the transmit/receive buffer y n y n sio1con(address 1a 16 ) synchronous clock: external clock input s rdy1 output pin transmit enabled receive enabled clock synchronous serial i/o serial i/o enabled set serial i/o1 control register i n i t i a l i z a t i o n tb/rb(address 18 16 ) read the first-byte reception data from the transmit/receive buffer register r e c e i v e b u f f e r i s f u l l ? ( c h e c k e d b y b 1 o f s i o 1 s t s ( a d d r e s s 1 9 1 6 ) ) t b / r b ( a d d r e s s 1 8 1 6 ) r e a d t h e s e c o n d - b y t e r e c e p t i o n d a t a f r o m t h e t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r r e c e i v e b u f f e r i s f u l l ? ( c h e c k e d b y b 1 o f s i o 1 s t s ( a d d r e s s 1 9 1 6 ) ) tb/rb(address 18 16 )
7540 group user s manual 2-112 application 2.6 serial i/o1 brg count source f(x in ) / 4 f(x in ) / 4 f(x in ) / 4 f(x in ) / 4 f(x in ) / 4 f(x in ) / 4 f(x in ) / 4 f(x in ) / 4 f(x in ) f(x in ) f(x in ) brg set value 255 (ff 16 ) 127 (7f 16 ) 63 (3f 16 ) 31 (1f 16 ) 15 (0f 16 ) 7 (07 16 ) 3 (03 16 ) 1 (01 16 ) 3 (03 16 ) 1 (01 16 ) 0 (00 16 ) transfer bit rate (bps) at f(x in ) = 4.9152 mhz 300 600 1200 2400 4800 9600 19200 38400 76800 153600 307200 at f(x in ) = 8 mhz 488.28125 976.5625 1953.125 3906.25 7812.5 15625 31250 62500 125000 250000 500000 2.6.5 application example of clock asynchronous serial i/o1 for clock asynchronous serial i/o1 (uart), the transfer formats used by a transmitter and receiver must be identical. in the 7540 group, eight serial data transfer formats can be selected. (1) data transfer rate the transfer bit rate is calculated by the following formula; when the internal clock is selected (when baud rate generator is used) transfer bit rate [bps] = division ratio* 1 : 1 or 4 is selected (set by bit 0 of serial i/o1 control register) brg setting value* 2 : 0 to 255 (00 16 to ff 16 ) is set when the external clock is selected transfer bit rate [bps] = clock input to s clk1 pin/16 table 2.6.1 shows the setting example of baud rate generator and transfer bit rate values. table 2.6.1 setting example of baud rate generator (brg) and transfer bit rate values f(x in ) division ratio *1 ? (brg setting value *2 + 1) ? 16
7540 group user s manual application 2-113 2.6 serial i/o1 fig. 2.6.16 setting method for uart of serial i/o1 (1) (2) uart setting method figure 2.6.16 and figure 2.6.17 show the setting method for uart of serial i/o1. b 7b0 0 b 7b 0 1 0 b 7b0 0 0 0 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] s e r i a l i / o 1 r e c e i v e i n t e r r u p t d i s a b l e d s e r i a l i / o 1 t r a n s m i t i n t e r r u p t d i s a b l e d p r o c e s s 1 : s t o p a n d i n i t i a l i z e s e r i a l i / o . s e r i a l i / o 1 c o n t r o l r e g i s t e r ( s i o 1 c o n ) [ a d d r e s s 1 a 1 6 ] t ransm i t operat i on stop an d i n i t i a li zat i on receive operation stop and initialization brg count source se l ecte d ( set i n i nterna l c l oc k se l ecte d) 0: f(x in ) 1: f(x in )/4 serial i/o1 synchronous clock selected ( note 1 ) 0: brg output/16 1: external clock input/16 transmit interrupt source selected 0: when transmit buffer has emptied 1: when transmit shift operation is completed transmit enable selected 0: transmit disabled (at half-duplex communication receive) 1: transmit enabled (at full-duplex communication) ( note 2 ) receive enable selected 0: receive disabled (at half-duplex communication transmit) 1: receive enabled (at full-duplex communication) ( note 2 ) clock asynchronous serial i/o serial i/o1 enabled (p1 0 p1 2 pins operate as serial i/o1 pins)( note 3 ) serial i/o1 control register (sio1con) [address 1a 16 ] p r o c e s s 3 : s e t s e r i a l i / o 1 c o n t r o l r e g i s t e r . n o t e 1 : s e t t i n g o f s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t i s a s f o l l o w s ; 0 : p 1 2 p i n c a n b e u s e d a s a n o r m a l i / o p i n 1 : p 1 2 p i n i s u s e d a s a n i n p u t p i n f o r a n e x t e r n a l c l o c k . 2: w h e n d a t a t r a n s m i s s i o n i s e x e c u t e d a t t h e s t a t e t h a t a n e x t e r n a l c l o c k i n p u t i s s e l e c t e d a s t h e s y n c h r o n o u s c l o c k , s e t 1 t o t h e t r a n s m i t e n a b l e b i t w h i l e t h e s c l k 1 i s h s t a t e . 3: w h e n c l o c k a s y n c h r o n o u s ( u a r t ) s e r i a l i / o i s s e l e c t e d , p 1 3 p i n c a n b e u s e d a s a n o r m a l i / o p i n . p r o c e s s 2 : d i s a b l e s e r i a l i / o 1 t r a n s m i t / r e c e i v e i n t e r r u p t .
7540 group user s manual 2-114 application 2.6 serial i/o1 fig. 2.6.17 setting method for uart of serial i/o1 (2) b 7b 0 00 b7 b0 1 1 p r o c e s s 5 : w h e n b r g o u t p u t / 1 6 i s s e l e c t e d a s s y n c h r o n o u s c l o c k , s e t v a l u e t o b a u d r a t e g e n e r a t o r . baud rate generator (brg) [address 1c 16 ] s e t b a u d r a t e v a l u e p r o c e s s 4 : s e t u a r t c o n t r o l r e g i s t e r . s e l e c t c h a r a c t e r l e n g t h 0 : 8 b i t s 1 : 7 b i t s s e l e c t p a r i t y e n a b l e 0 : p a r i t y d i s a b l e d 1 : p a r i t y e n a b l e d s e l e c t p a r i t y ( v a l i d o n l y w h e n p a r i t y i s e n a b l e d ) 0 : e v e n p a r i t y 1 : o d d p a r i t y s e l e c t s t o p b i t l e n g t h 0 : 1 s t o p b i t 1 : 2 s t o p b i t s s e l e c t p 1 1 / t x d p - c h a n n e l o u t p u t d i s a b l e ( i n o u t p u t m o d e ) 0 : c m o s o u t p u t 1 : n - c h a n n e l o p e n - d r a i n o u t p u t u a r t c o n t r o l r e g i s t e r ( u a r t c o n ) [ a d d r e s s 1 b 1 6 ] b 7b 0 p r o c e s s 8 : w h e n t r a n s m i t t i n g , s t a r t s e r i a l d a t a t r a n s m i s s i o n ( n o t e ) . t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r ( t b / r b ) [ a d d r e s s 1 8 1 6 ] s et transm i t d ata p r o c e s s 6 : i n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t 0 ( n o r e q u e s t e d ) t o t h e s e r i a l i / o 1 t r a n s m i t / r e c e i v e i n t e r r u p t r e q u e s t b i t . interrupt request register 1 (ireq1) [address 3c 16 ] n o s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t i s s u e d n o s e r i a l i / o 1 t r a n s m i t i n t e r r u p t r e q u e s t i s s u e d s e r i a l i / o 1 r e c e i v e i n t e r r u p t e n a b l e d s e r i a l i / o 1 t r a n s m i t i n t e r r u p t e n a b l e d i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 3 e 1 6 ] p r o c e s s 7 : w h e n t h e i n t e r r u p t i s u s e d , s e t 1 ( i n t e r r u p t e n a b l e d ) t o t h e s e r i a l i / o 1 t r a n s m i t / r e c e i v e i n t e r r u p t e n a b l e b i t . note: when data transmission is executed at the state that an external clock input is selected as the synchronous clock, set the transmit data while the s clk1 is h state.
7540 group user s manual application 2-115 2.6 serial i/o1 (3) communication using uart of serial i/o (transmit/receive) outline : 2-byte data is transmitted and received, using uart. port p0 0 is used for communication control. specifications : the serial i/o1 (uart selected ) is used. transfer bit rate : 9600 bps (f(x in ) = 4.9152 mhz divided by 512) communication control using port p0 0 (output level of port p0 0 is controlled by software) 2-byte data is transferred from the transmitter to the receiver at 10 ms intervals which the timer generates. figure 2.6.18 shows a connection diagram, figure 2.6.19 shows a timing chart, figure 2.6.20 shows the control procedure of transmitter, and figure 2.6.21 shows an example of control procedure of receiver. fig. 2.6.18 connection diagram fig. 2.6.19 timing chart p0 0 t x d 1 0 m s d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st s p ( 2 ) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st s p ( 2 ) d 0 st ..... ..... t r a n s m i t t e r p 0 0 t x d 7 5 4 0 g r o u p p0 0 r x d 7540 group receiver
7540 group user s manual 2-116 application 2.6 serial i/o1 fig. 2.6.20 control procedure of transmitter 0 1 1 0 m s e l a p s e d ? ( g e n e r a t e d b y t i m e r ) y n r e s e t s e i c l d c l t 10 0 y n 1 0 uartcon(address 1b 16 ) character length: 8 bits parity disabled stop bit length: 2 bits t x d: cmos output s e t u a r t c o n t r o l r e g i s t e r 0 0 1 0 07 16 y n n s e t 0 t o t h e c o m m u n i c a t i o n c o n t r o l p o r t p 0 0 . y sio1con(address 1a 16 ) brg count source: f(x in )/4 synchronous clock: brg output/16 transmit interrupt source: w h e n t r a n s m i t b u f f e r h a s e m p t i e d transmit enabled receive disabled uart serial i/o1 enabled s e t s e r i a l i / o 1 c o n t r o l r e g i s t e r b r g ( a d d r e s s 1 c 1 6 ) s e t b a u d r a t e g e n e r a t o r i n i t i a l i z a t i o n t b / r b ( a d d r e s s 1 8 1 6 ) w r i t e t h e f i r s t - b y t e t r a n s m i s s i o n d a t a t o t h e t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r t b / r b ( a d d r e s s 1 8 1 6 ) w r i t e t h e s e c o n d - b y t e t r a n s m i s s i o n d a t a t o t h e t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r transmit buffer has emptied ? (checked by b0 of sio1sts (address 19 16 )) t r a n s m i t s h i f t h a s c o m p l e t e d ? ( c h e c k e d b y b 2 o f s i o 1 s t s ( a d d r e s s 1 9 1 6 ) ) transmit buffer has emptied ? (checked by b0 of sio1sts (address 19 16 )) set 1 to the communication control port p0 0 . set the communication control port p0 0 to the output mode.
7540 group user s manual application 2-117 2.6 serial i/o1 fig. 2.6.21 control procedure of receiver 0 0 y 101 1 u a r t c o n ( a d d r e s s 1 b 1 6 ) 0 1 0 b r g ( a d d r e s s 1 c 1 6 ) 0 7 1 6 n n y n n y y n y error processing s e i c l d c l t s i o 1 c o n ( a d d r e s s 1 a 1 6 ) brg count source: f(x in )/4 synchronous clock: brg output/16 transmit disabled receive enabled uart serial i/o1 enabled s e t s e r i a l i / o 1 c o n t r o l r e g i s t e r i n i t i a l i z a t i o n c h a r a c t e r l e n g t h : 8 b i t s p a r i t y d i s a b l e d s t o p b i t l e n g t h : 2 b i t s s e t u a r t c o n t r o l r e g i s t e r b r g ( a d d r e s s 1 c 1 6 ) s e t b a u d r a t e g e n e r a t o r tb/rb(address 18 16 ) read the first-byte transmission data from the transmit/receive buffer register r e c e i v e b u f f e r i s f u l l ? ( c h e c k e d b y b 1 o f s i o 1 s t s ( a d d r e s s 1 9 1 6 ) ) c o m m u n i c a t i o n c o n t r o l p o r t p 0 0 = 0 ? s e t t h e c o m m u n i c a t i o n c o n t r o l p o r t p 0 0 t o t h e i n p u t m o d e . tb/rb(address 18 16 ) r e a d t h e s e c o n d - b y t e t r a n s m i s s i o n d a t a f r o m t h e t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r e r r o r o c c u r s ? ( c h e c k e d b y b 6 o f s i o 1 s t s ( a d d r e s s 1 9 1 6 ) ) e r r o r o c c u r s ? ( c h e c k e d b y b 6 o f s i o 1 s t s ( a d d r e s s 1 9 1 6 ) ) r e c e i v e b u f f e r i s f u l l ? ( c h e c k e d b y b 1 o f s i o 1 s t s ( a d d r e s s 1 9 1 6 ) )
7540 group user s manual 2-118 application 2.6 serial i/o1 2.6.6 notes on serial i/o1 notes on using serial i/o1 are described below. (1) notes when selecting clock synchronous serial i/o ? when the clock synchronous serial i/o1 is used, serial i/o2 cannot be used. ? when the transmit operation is stopped, clear the serial i/o1 enable bit and the transmit enable bit to 0 (serial i/o1 and transmit disabled). reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to 0 (serial i/o1 disabled), the internal transmission is running (in this case, since pins txd 1 , rxd 1 , s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to 1 at this time, the data during internally shifting is output to the txd 1 pin and an operation failure occurs. ? when the receive operation is stopped, clear the receive enable bit to 0 (receive disabled), or clear the serial i/o1 enable bit to 0 (serial i/o1 disabled). ? when the transmit/receive operation is stopped, clear both the transmit enable bit and receive enable bit to 0 (transmit and receive disabled) simultaneously. (any one of data transmission and reception cannot be stopped.) reason in the clock synchronous serial i/o mode, the same clock is used for transmission and reception. if any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. in this mode, the clock circuit of the transmission circuit also operates for data reception. accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to 0 (transmit disabled). also, the transmission circuit cannot be initialized even if the serial i/o1 enable bit is cleared to 0 (serial i/o1 disabled) (same as ? ). ? when signals are output from the s rdy1 pin on the reception side by using an external clock, set all of the receive enable bit, the s rdy1 output enable bit, and the transmit enable bit to 1 . ? when the s rdy1 signal input is used, set the using pin to the input mode before data is written to the transmit/receive buffer register. ? setup of a serial i/o1 synchronous clock selection bit when a clock synchronous serial i/o is selected; 0 : p1 2 pin turns into an output pin of a synchronous clock. 1 : p1 2 pin turns into an input pin of a synchronous clock. setup of a s rdy1 output enable bit (s rdy1 ) when a clock synchronous serial i/o1 is selected; 0 : p1 3 pin can be used as a normal i/o pin. 1 : p1 3 pin turns into a s rdy1 output pin.
7540 group user s manual application 2-119 2.6 serial i/o1 (2) notes when selecting uart ? when the clock asynchronous serial i/o1 (uart) is used, serial i/o2 can be used only when brg output divided by 16 is selected as the synchronous clock. ? when the transmit operation is stopped, clear the transmit enable bit to 0 (transmit disabled). reason same as (1) ? . ? when the receive operation is stopped, clear the receive enable bit to 0 (receive disabled). ? when the transmit/receive operation is stopped, clear the transmit enable bit to 0 (transmit disabled) and receive enable bit to 0 (receive disabled). ? setup of a serial i/o1 synchronous clock selection bit when a clock asynchronous (uart) serial i/o is selected; 0 : p1 2 pin can be used as a normal i/o pin. 1 : p1 2 pin turns into an input pin of an external clock. when clock asynchronous (uart) type serial i/o is selected, it is p1 3 pin. it can be used as a normal i/o pin. (3) notes common to clock synchronous serial i/o and uart ? when data transmission is executed at the state that an external clock input is selected as the synchronous clock, set 1 to the transmit enable bit while the s clk1 is h state. also, write to the transmit buffer register while the s clk1 is h state. ? when the transmit interrupt is used, set as the following sequence. ? serial i/o1 transmit interrupt enable bit is set to 0 (disabled). ? serial i/o1 transmit enable bit is set to 1 . ? serial i/o1 transmit interrupt request bit is set to 0 . ? serial i/o1 transmit interrupt enable bit is set to 1 (enabled). reason when the transmit enable bit is set to 1 , the transmit buffer empty flag and transmit shift completion flag are set to 1 . accordingly, even if the timing when any of the above flags is set to 1 is selected for the transmit interrupt source, interrupt request occurs and the transmit interrupt request bit is set. ? write to the baud rate generator (brg) while the transmit/receive operation is stopped. fig. 2.6.22 sequence of setting serial i/o1 control register again ? set the serial i/o control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to 0. ? the transmit shift completion flag changes from 1 to 0 with a delay of 0.5 to 1.5 shift clocks. when data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. can be set with the ldm instruction at the same time clear both the transmit enable bit (te) and the receive enable bit (re) to 0 set the bits 0 to 3 and bit 6 of the serial i/o1 control register set both the transmit enable bit (te) and the receive enable bit (re), or one of them to 1
7540 group user? manual 2-120 application 2.7 serial i/o2 2.7 serial i/o2 this paragraph explains the registers setting method and the notes relevant to the serial i/o. 2.7.1 memory map fig. 2.7.1 memory map of registers relevant to serial i/o2 2.7.2 relevant registers fig. 2.7.2 structure of port p1 direction register 0003 16 003d 16 port p1 direction register (p1d) interrupt request register 2 (ireq2) 003f 16 interrupt control register 2 (icon2) 0030 16 serial i/o2 control register (sio2con) 0031 16 serial i/o2 register (sio2) port p1 direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p1 direction register 0 0 0 0 0 ? ? ? port p1 direction register (p1d) [address : 03 16 ] 0 : port p1 0 input mode 1 : port p1 0 output mode 0 : port p1 1 input mode 1 : port p1 1 output mode 0 : port p1 2 input mode 1 : port p1 2 output mode 0 : port p1 3 input mode 1 : port p1 3 output mode 0 : port p1 4 input mode 1 : port p1 4 output mode ? ? ? ? ? ? ? ? nothing is allocated for these bits. when these bits are read out, the values are undefined. ? ? ?
7540 group user s manual application 2-121 2.7 serial i/o2 fig. 2.7.3 structure of serial i/o2 control register fig. 2.7.4 structure of serial i/o2 register b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 c o n ) [ a d d r e s s : 3 0 1 6 ] n o t h i n g i s a l l o c a t e d f o r t h i s b i t . t h i s i s a w r i t e d i s a b l e d b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . ? ? s e r i a l i / o 2 c o n t r o l r e g i s t e r 0 0 n o t e : w h e n u s i n g i t a s a s d a t a i n p u t , s e t t h e p o r t p 1 3 d i r e c t i o n r e g i s t e r b i t t o 0 . 0 : l s b f i r s t 1 : m s b f i r s t 0 0 0 : f(x in )/8 0 0 1 : f(x in )/16 0 1 0 : f(x in )/32 0 1 1 : f(x in )/64 1 1 0 : f(x in )/128 1 1 1 : f(x in )/256 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s t r a n s f e r d i r e c t i o n s e l e c t i o n b i t b 2 b 1 b 0 s d a t a 2 p i n s e l e c t i o n b i t ( n o t e ) 0 : i / o p o r t / s d a t a 2 i n p u t 1 : s d a t a 2 o u t p u t s c l k 2 p i n s e l e c t i o n b i t 0 : e x t e r n a l c l o c k ( s c l k 2 i s i n p u t ) 1 : i n t e r n a l c l o c k ( s c l k 2 i s o u t p u t ) transmit / receive shift completion flag 0 : shift in progress 1 : shift completed 0 0 serial i/o2 register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? serial i/o2 register (sio2) [address : 31 16 ] a shift register for serial transmission and reception. at transmitting : set a transmission data. at receiving : a reception data is stored.
7540 group user s manual 2-122 application 2.7 serial i/o2 fig. 2.7.5 structure of interrupt request register 2 fig. 2.7.6 structure of interrupt control register 2 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 2 (ireq2) [address : 3d 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . timer y interrupt request bit timer z interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued timer a interrupt request bit serial i/o2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ad converter interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? ? interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 2 (icon2) [address : 3f 16 ] ? timer y interrupt enable bit timer z interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled timer 1 interrupt enable bit timer a interrupt enable bit serial i/o2 interrupt enable bit ad conversion interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled ? nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 .
7540 group user s manual application 2-123 2.7 serial i/o2 fig. 2.7.7 setting method for serial i/o2 2.7.3 application example of serial i/o2 (1) serial i/o2 setting method figure 2.7.7 and figure 2.7.8 show the setting method for the serial i/o2. b7 b 0 b7 b0 0 b 7b 0 0 p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) [ a d d r e s s 0 3 1 6 ] b7 b 0 p 1 2 / s c l k 2 p i n ( n o t e 1 ) p 1 3 / s d a t a 2 p i n ( n o t e s 2 , 3 ) interrupt control register 2 (icon2) [address 3f 16 ] s e r i a l i / o 2 i n t e r r u p t d i s a b l e d i nterna l sync h ronous c l oc k se l ecte d ( set i n i nterna l c l oc k se l ecte d) b2b1b0 0 0 0: f(x in )/8 0 0 1: f(x in )/16 0 1 0: f(x in )/32 0 1 1: f(x in )/64 1 1 0: f(x in )/128 1 1 1: f(x in )/256 s data2 pin selected 0: i/o port/s data2 input (at receive) 1: s data2 output (at transmit) transfer direction selected 0: lsb first 1: msb first s clk2 pin selected 0: external clock (s clk2 is input) 1: internal clock (s clk2 is outpu) serial i/o2 control register (sio2con) [address 30 16 ] process 3: set serial i/o2 control register. p r o c e s s 1 : d i s a b l e s e r i a l i / o 2 t r a n s m i t / r e c e i v e i n t e r r u p t . process 4: in order not to execute the no requested interrupt processing, set 0 (no requested) to the serial i/o2 interrupt request bit. i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 3 d 1 6 ] n o s e r i a l i / o 2 i n t e r r u p t r e q u e s t i s s u e d n o t e s 1 : w h e n a n e x t e r n a l c l o c k i n p u t i s s e l e c t e d , s e t p 1 2 / s c l k 2 p i n t o t h e i n p u t m o d e . 2 : w h e n p 1 3 / s d a t a 2 p i n i s u s e d a s t h e p 1 3 p i n , s e t t h i s b i t t o 0 . 3 : w h e n t h i s b i t i s s e t t o 0 a t t r a n s m i t a n d t h e i n t e r n a l c l o c k i s s e l e c t e d f o r s c l k 2 , t h e s d a t a 2 p i n i s i n a h i g h i m p e d a n c e s t a t e a f t e r t h e d a t a t r a n s f e r i s c o m p l e t e d . p r o c e s s 2 : s e t p o r t p 1 a c c o r d i n g t o t h e u s a g e c o n d i t i o n .
7540 group user s manual 2-124 application 2.7 serial i/o2 fig. 2.7.8 setting method for serial i/o2 b7 b0 1 serial i/o2 register (sio2) [address 31 16 ] s e t t r a n s m i t d a t a s er i a l i / o 2 i nterrupt ena bl e d interrupt control register 2 (icon2) [address 3f 16 ] process 5: when the interrupt is used, set 1 (interrupt enabled) to the serial i/o2 interrupt. enable bit. process 6: when transmitting, start serial data transmission.
7540 group user s manual application 2-125 2.7 serial i/o2 (2) communication using serial i/o2 (transmit/receive) outline: 2-byte data is transmitted and received, using the serial i/o2. port p0 0 is used for communication control and outputs the quasi-s rdy signal. specifications: the serial i/o2, clock synchronous serial i/o, is used. synchronous clock frequency : 125 khz; f(x in ) = 8 mhz divided by 64 transfer direction : lsb first the receiver outputs the quasi-s rdy signal at 2 ms intervals which the timer generates, and 2-byte data is transferred from the transmitter to the receiver. figure 2.7.9 shows a connection diagram, figure 2.7.10 shows a timing chart, figure 2.7.11 shows the control procedure of transmitter, and figure 2.7.12 shows an example of control procedure of receiver. fig. 2.7.9 connection diagram fig. 2.7.10 timing chart t r a n s m i t t e r p3 7 /int 0 s clk s data 7 5 4 0 g r o u p p 0 0 s c l k s d a t a 7540 group r e c e i v e r q u a s i -s r d y s c l k s d a t a d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 2 ms . . . . . ..... . . . . .
7540 group user s manual 2-126 application 2.7 serial i/o2 fig. 2.7.11 control procedure of transmission side 0 11 y n r e s e t 10 1 i n t 0 f a l l i n g e d g e a c t i v e 0 s i o 2 ( a d d r e s s 3 1 1 6 ) y n y n s e t p o r t p 1 2 t o t h e o u t p u t m o d e . s e t 0 t o t h e s e r i a l i / o 2 i n t e r r u p t r e q u e s t b i t . sio2con(address 30 16 ) s y n c h r o n o u s c l o c k : f ( x i n ) / 6 4 s d a t a 2 p i n : s d a t a 2 o u t p u t l s b f i r s t s c l k 2 p i n : i n t e r n a l c l o c k s e t s e r i a l i / o 2 c o n t r o l r e g i s t e r i n t 0 f a l l i n g e d g e i n p u t ? i n i t i a l i z a t i o n sei cld clt i n t e d g e ( a d d r e s s 3 a 1 6 ) set int 0 interrupt active edge w r i t e t h e f i r s t - b y t e t r a n s m i s s i o n d a t a t o t h e s e r i a l i / o 2 r e g i s t e r transmit shift has completed ? (checked by serial i/o2 interrupt request bit) s e t p o r t p 1 3 t o t h e o u t p u t m o d e . ( n o t e ) s i o 2 ( a d d r e s s 3 1 1 6 ) s e t 0 t o t h e s e r i a l i / o 2 i n t e r r u p t r e q u e s t b i t . w r i t e t h e s e c o n d - b y t e t r a n s m i s s i o n d a t a t o t h e s e r i a l i / o 2 r e g i s t e r transmit shift has completed ? (checked by serial i/o2 interrupt request bit) n o t e : w h e n d i r e c t i o n r e g i s t e r o f p 1 3 / s d a t a 2 p i n i s s e t t o t h e i n p u t m o d e a n d t h e i n t e r n a l c l o c k i s s e l e c t e d , t h e s d a t a 2 p i n i s i n a h i g h i m p e d a n c e s t a t e a f t e r t h e d a t a t r a n s f e r i s c o m p l e t e d .
7540 group user s manual application 2-127 2.7 serial i/o2 fig. 2.7.12 control procedure of reception side 0 11 y n reset 0 00 y n sio2(address 31 16 ) sio2(address 31 16 ) s e t d u m m y d a t a t o s e r i a l i / o 2 r e g i s t e r ( n o t e 1 ) y n wait for half cycle of clock ( note 2 ) sio2(address 31 16 ) r e a d r e c e i v e d a t a f r o m s e r i a l i / o 2 r e g i s t e r s i o 2 ( a d d r e s s 3 1 1 6 ) s e t q u a s i - s r d y s i g n a l p o r t p 0 0 t o t h e o u t p u t m o d e . s i o 2 c o n ( a d d r e s s 3 0 1 6 ) synchronous clock: f(x in )/64 s data2 pin: s data2 input lsb first s clk2 pin: external clock set serial i/o2 control register 2 ms elapsed ? (generated by timer) i n i t i a l i z a t i o n s e i c l d c l t s e t d u m m y d a t a t o t h e s e r i a l i / o 2 r e g i s t e r ( n o t e 1 ) receive has completed ? (checked by b7 of sio2con (address 30 16 )) s e t p o r t p 1 2 t o t h e i n p u t m o d e . n o t e s 1 : t h e t r a n s m i t / r e c e i v e s h i f t c o m p l e t i o n f l a g o f t h e s e r i a l i / o 2 c o n t r o l r e g i s t e r i s 1 a f t e r t r a n s m i t / r e c e i v e s h i f t i s c o m p l e t e d . i n o r d e r t o s e t 0 t o t h i s f l a g , s e t d a t a ( d u m m y d a t a a t r e c e i v e ) t o t h e s e r i a l i / o 2 r e g i s t e r b y p r o g r a m . 2 : b i t 7 ( t r a n s m i t / r e c e i v e s h i f t c o m p l e t i o n f l a g ) o f t h e s e r i a l i / o 2 c o n t r o l r e g i s t e r i s s e t e a r l i e r t h a n t h e c o m p l e t i o n o f t h e a c t u a l s h i f t o p e r a t i o n f o r a h a l f c y c l e o f s h i f t c l o c k . a c c o r d i n g l y , w h e n t h e s h i f t c o m p l e t i o n i s c h e c k e d b y u s i n g t h i s b i t , r e a d / w r i t e t h e s e r i a l i / o 2 r e g i s t e r a f t e r a h a l f o r m o r e c y c l e o f c l o c k f r o m t h e s e t t i n g 1 t o t h i s b i t i s c h e c k e d . output 1 from quasi-s rdy signal port p0 0 . s e t p o r t p 1 3 t o t h e i n p u t m o d e . r e c e i v e h a s c o m p l e t e d ? ( c h e c k e d b y b 7 o f s i o 2 c o n ( a d d r e s s 3 0 1 6 ) ) wait for half cycle of clock ( note 2 ) read receive data from serial i/o2 register o u t p u t 0 f r o m q u a s i - s r d y s i g n a l p o r t p 0 0 . output 1 from quasi-s rdy signal port p0 0 .
7540 group user s manual 2-128 application 2.7 serial i/o2 2.7.4 notes on serial i/o2 notes on using serial i/o2 are described below. (1) note on serial i/o1 serial i/o2 can be used only when serial i/o1 is not used or serial i/o1 is used as uart and the brg output divided by 16 is selected as the synchronous clock. (2) note on s clk2 pin when an external clock is selected, set 0 to bit 2 of the port p1 direction register (input mode). (3) note on s data2 pin when p1 3 /s rdy1 /s data2 pin is used as the s data input, set 0 to bit 3 of the port p1 direction register (input mode). when the internal clock is selected as the transfer and p1 3 /s data2 pin is set to the input mode, the s data2 pin is in a high-impedance state after the data transfer is completed. (4) notes on serial i/o2 transmit/receive shift completion flag ? the transmit/receive shift completion flag of the serial i/o2 control register is 1 after transmit/ receive shift is completed. in order to set 0 to this flag, set data (dummy data at receive) to the serial i/o2 register by program. ? bit 7 (transmit/receive shift completion flag) of the serial i/o2 control register is set earlier than the completion of the actual shift operation for a half cycle of shift clock. accordingly, when the shift completion is checked by using this bit, read/write the serial i/o2 register after a half or more cycle of clock from the setting 1 to this bit is checked.
7540 group user? manual application 2-129 2.8 a-d converter 2.8 a-d converter this paragraph explains the registers setting method and the notes relevant to the a-d converter. 2.8.1 memory map fig. 2.8.1 memory map of registers relevant to a-d converter 2.8.2 relevant registers fig. 2.8.2 structure of a-d control register 0034 16 0035 16 0036 16 003d 16 a-d control register (adcon) a-d conversion register (low-order) (adl) a-d conversion register (high-order) (adh) interrupt request register 2 (ireq2) 003f 16 interrupt control register 2 (icon2) b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 1 0 0 a-d control register (adcon) [address : 34 16 ] nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 0 . ? a-d control register 0 note: these can be used only for the 36-pin package versions. 0 0 0 : p2 0 /an 0 0 0 1 : p2 1 /an 1 0 1 0 : p2 2 /an 2 0 1 1 : p2 3 /an 3 1 0 0 : p2 4 /an 4 1 0 1 : p2 5 /an 5 1 1 0 : p2 6 /an 6 ( note ) 1 1 1 : p2 7 /an 7 ( note ) analog input pin selection bits b2 b1 b0 0 0 ad conversion completion bit 0 : conversion in progress 1 : conversion completed nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . 0 ? ? ? ? : this bit can be cleared to 0 by program, but cannot be set to 1 . ?
7540 group user s manual 2-130 application 2.8 a-d converter fig. 2.8.3 structure of a-d conversion register (low-order) fig. 2.8.4 structure of a-d conversion register (high-order) a-d conversion register (low-order) b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? a-d conversion register (low-order) (adl) [address : 35 16 ] the read-only register in which the a-d conversion s results are stored. ? ? ? ? ? ? ? ? < 8-bit read> b7 b8 b7 b6 b5 b4 b3 b0 b2 b9 < 10-bit read> b7 b6 b5 b4 b3 b2 b1 b0 b0 b7 a-d conversion register (high-order) b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? a-d conversion register (high-order) (adh) [address : 36 16 ] the read-only register in which the a-d conversion s results are stored. ? ? ? ? ? ? ? ? < 10-bit read> b7 b9 b0 b8 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 .
7540 group user s manual application 2-131 2.8 a-d converter fig. 2.8.5 structure of interrupt request register 2 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 2 (ireq2) [address : 3d 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . timer y interrupt request bit timer z interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued timer a interrupt request bit serial i/o2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ad converter interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? ? interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 2 (icon2) [address : 3f 16 ] ? timer y interrupt enable bit timer z interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled timer 1 interrupt enable bit timer a interrupt enable bit serial i/o2 interrupt enable bit ad conversion interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled ? nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . fig. 2.8.6 structure of interrupt control register 2
7540 group user s manual 2-132 application 2.8 a-d converter 2.8.3 a-d converter application examples (1) setting of a-d converter figure 2.8.7 shows the relevant registers setting. fig. 2.8.7 relevant registers setting p r o c e s s 2 : s e t a - d c o n t r o l r e g i s t e r . b7 b 0 a - d c o n t r o l r e g i s t e r ( a d c o n ) [ a d d r e s s 3 4 1 6 ] a na l og i nput p i ns se l ecte d b2b1b0 0 0 0: p2 0 /an 0 0 0 1: p2 1 /an 1 0 1 0: p2 2 /an 2 0 1 1: p2 3 /an 3 1 0 0: p2 4 /an 4 1 0 1: p2 5 /an 5 1 1 0: p2 6 /an 6 ( note ) 1 1 1: p2 7 /an 7 ( note ) b 7b 0 0 b 7b 0 i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 3 f 1 6 ] 0 note: these can be used only for 36-pin version. b 7b 0 1 b7 b 0 0 a - d c o n v e r s i o n i n t e r r u p t d i s a b l e d p r o c e s s 1 : d i s a b l e a - d c o n v e r s i o n i n t e r r u p t . process 3: in order not to execute the no requested interrupt processing, set 0 (no requested) to the a-d conversion interrupt request bit. i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 3 d 1 6 ] n o a - d convers i on i nterrupt request i ssue d a - d c o n t r o l r e g i s t e r ( a d c o n ) [ a d d r e s s 3 4 1 6 ] s tart a - d convers i on a - d convers i on i nterrupt ena bl e d i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 3 f 1 6 ] process 4: when the interrupt is used, set 1 (interrupt enabled) to the a-d conversion interrupt enable bit. p r o c e s s 5 : s t a r t a - d c o n v e r s i o n .
7540 group user s manual application 2-133 2.8 a-d converter fig. 2.8.8 connection diagram (2) control procedure outline : the analog input voltage input from a sensor is converted to digital values. specifications : the analog input voltage input from a sensor is converted to digital values. p2 0 /an 0 pin is used as an analog input pin. figure 2.8.8 shows a connection diagram, and figure 2.8.9 shows an example of control procedure. fig. 2.8.9 control procedure p2 0 /an 0 7 5 4 0 g r o u p s e n s o r a-d conversion processing adcon(address 34 16 ) analog input pins: p2 0 /an 0 set analog input pins 0 00 adcon(address 34 16 ) s t a r t a - d c o n v e r s i o n 0 00 0 1 a-d conversion completed ? ( note 2 ) read adh (address 36 16 ) ( note 3 ) r t s n o t e s 1 : i n t h i s c a s e , t h e a - d c o n v e r s i o n i n t e r r u p t i s u s e d . 2 : t h e c o m p l e t i o n o f t h e a - d c o n v e r s i o n i s c h e c k e d b y t h e f o l l o w i n g ; t h e a - d c o n v e r s i o n c o m p l e t i o n b i t o f t h e a - d c o n t r o l r e g i s t e r i s 1 . t h e a - d c o n v e r s i o n i n t e r r u p t r e q u e s t b i t o f t h e i n t e r r u p t r e q u e s t r e g i s t e r 2 i s 1 . b r a n c h t o t h e a - d c o n v e r s i o n i n t e r r u p t p r o c e s s i n g r o u t i n e i s e x e c u t e d . ( i n t h i s t i m e , t h e a - d c o n v e r s i o n i n t e r r u p t i s e n a b l e d . ) 3 : a t 1 0 - b i t r e a d : t h e c o n v e r s i o n r e s u l t o f t h e h i g h - o r d e r 2 b i t s ( b 9 , b 8 ) c a n b e r e a d . a t 8 - b i t r e a d : n o t u s e d . 4 : a t 1 0 - b i t r e a d : t h e c o n v e r s i o n r e s u l t o f t h e l o w - o r d e r 8 b i t s ( b 7 t o b 0 ) c a n b e r e a d . a t 8 - b i t r e a d : t h e c o n v e r s i o n r e s u l t o f b 7 t o b 0 c a n b e r e a d . y n set 0 to the a-d conversion interrupt request bit. set 1 to the a-d conversion interrupt enable bit. (a-d conversion interrupt enabled) ( note 1 ) start a-d conversion s e t 0 t o t h e a - d c o n v e r s i o n i n t e r r u p t e n a b l e b i t . ( a - d c o n v e r s i o n i n t e r r u p t d i s a b l e d ) read adl (address 35 16 ) ( note 4 )
7540 group user s manual 2-134 application 2.8 a-d converter 2.8.4 notes on a-d converter notes on a-d converter are described below. (1) analog input pin figure 2.8.10 shows the internal equivalent circuit of an analog input. in order to execute the a-d conversion correctly, to complete the charge to an internal capacitor within the specified time is required. the maximum output impedance of the analog input source required to complete the charge to a capacitor within the specified time is as follows; about 35 k ? (at f(x in ) = 8 mhz) when the maximum output impedance exceeds the above value, equip an analog input pin with an external capacitor of 0.01 f to 1 f between an analog input pin and v ss . further, be sure to verify the operation of application products on the user side. reason an analog input pin includes the capacitor for analog voltage comparison. accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. this may cause the a-d conversion/comparison precision to be worse. (2) clock frequency during a-d conversion the comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. thus, make sure the following during an a-d conversion. f(x in ) is 500 khz or more do not execute the stp instruction fig. 2.8.10 connection diagram ani (i=0 to 7: 36-pin version i=0 to 5: 32-pin version) c1 12 pf(typical) notes 1: this is a parasitic diode. 2: only the selected analog input pin is turned on. c2 1.5 pf(typical) chopper amp. a-d control circuit typical voltage generation circuit switch tree, ladder resistor 1.5 k ? (typical) v ss v ss v cc v ss v ref r ( note 1 ) sw1 ( note 2 ) ( note 1 )
7540 group user? manual application 2-135 2.9 oscillation control 2.9 oscillation control this paragraph explains the registers setting method and the notes relevant to the oscillation control. 2.9.1 memory map fig. 2.9.1 memory map of registers relevant to oscillation control 2.9.2 relevant registers 0038 16 0039 16 003b 16 misrg watchdog timer control register (wdtcon) cpu mode register (cpum) fig. 2.9.2 structure of misrg b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 misrg [address : 38 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? m i s r g o s c i l l a t i o n s t a b i l i z a t i o n t i m e s e t b i t a f t e r r e l e a s e o f t h e s t p i n s t r u c t i o n 0 0 : set 01 16 in timer 1, and ff 16 in prescaler 1 automatically 1 : not set automatically these are reserved bits. do not write 1 to these bits. 0 0 ( n o t e ) ? ? ? ? ? 0 : oscillation stop not detected 1 : oscillation stop detected ceramic or rc oscillation stop detection function active bit 0 : detection function inactive 1 : detection function active o s c i l l a t i o n s t o p d e t e c t i o n s t a t u s b i t n o t e : 0 a t n o r m a l r e s e t 1 a t r e s e t b y d e t e c t i n g t h e o s c i l l a t i o n s t o p
7540 group user s manual 2-136 application 2.9 oscillation control fig. 2.9.3 structure of watchdog timer control register watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 1 1 1 1 1 0 0 watchdog timer control register (wdtcon) [address : 39 16 ] watchdog timer h (the high-order 6 bits are read-only bits.) stp instruction disable bit 0 : stp instruction enabled 1 : stp instruction disabled watchdog timer h count source selection bit 0 : watchdog timer l underflow 1 : f(x in )/16 ? ? ? ? ? ? fig. 2.9.4 structure of cpu mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 2 3 4 5 6 7 name 0 0 0 1 cpu mode register (cpum) [address : 3b 16 ] cpu mode register 0 0 0 0 0 : single-chip mode 0 1 : not available 1 0 : not available 1 1 : not available b1 b0 1 0 processor mode bits ( note 1 ) 0 : ceramic oscillation 1 : rc oscillation 0 : 0 page 1 : 1 page stack page selection bit oscillation mode selection bit ( note 1 ) clock division ratio selection bits 0 0 : f(x in )/2 (high-speed mode) 0 1 : f(x in )/8 (middle-speed mode) 1 0 : applied from ring oscillator 1 1 : f(x in ) (double-speed mode) ( note 2 ) b7 b6 0 : ceramic or rc oscillation enabled 1 : ceramic or rc oscillation stop notes 1: the bit can be rewritten only once after releasing reset. after rewriting it is disable to write any data to the bit. however, by reset the bit is initialized and can be rewritten, again. (it is not disable to write any data to the bit for emulator mcu m37540rss .) 2: these bits are used only when a ceramic oscillation is selected. do not use these when an rc oscillation is selected. ring oscillator oscillation control bit 0 : ring oscillator oscillation enabled 1 : ring oscillator oscillation stop x in oscillation control bit
7540 group user s manual application 2-137 2.9 oscillation control 2.9.3 application example of ring oscillator the ring oscillator is the oscillation circuit which is equipped with the 7540 group. external circuits can be eliminated by using this oscillator as the operation clock or by using this oscillator with a ceramic or rc oscillation circuit. when this oscillator is used as the operation clock, all peripheral functions can be used. in this section, the setting method and application example are explained. note: the 7540 group starts operation by the ring oscillator. (1) setting method figure 2.9.5 shows the setting method when the ring oscillator is used as the operation clock. fig. 2.9.5 setting method when the ring oscillator is used as the operation clock p r o c e s s 1 : e n a b l e r i n g o s c i l l a t o r o s c i l l a t i o n . b 7b0 c p u m o d e r e g i s t e r ( c p u m ) [ a d d r e s s 3 b 1 6 ] r i n g o s c i l l a t i o r o s c i l l a t i o n e n a b l e d 0 0 0 p r o c e s s 2 : s e t t h e o p e r a t i o n c l o c k t o r i n g o s c i l l a t o r . b 7b0 a p p l i e d f r o m r i n g o s c i l l a t o r 0 0 0 0 1 p r o c e s s 3 : w h e n f ( x i n ) i s n o t u s e d , s t o p f ( x i n ) . b 7b 0 c e r a m i c o r r c o s c i l l a t i o n s t o p 0 0 0 0 1 1 cpu mode register (cpum) [address 3b 16 ] cpu mode register (cpum) [address 3b 16 ] (2) example of control procedure outline: the frequency of the ring oscillator is measured, and an error by the power source voltage or temperature is confirmed. specifications : the f(x in ) = 4 mhz is divided by timer z and 10 ms is detected. the ring oscillator is divided by timer y. the count value of timer y is read out in the timer z interrupt processing routine which occurs every 10 ms, and an error from f(x in ) is confirmed. figure 2.9.6 shows an example of control procedure.
7540 group user s manual 2-138 application 2.9 oscillation control fig. 2.9.6 control procedure f 9 16 4 f 1 6 1 i n i t i a l i z a t i o n r e s e t s e i c l d c l t s e t c p u m o d e r e g i s t e r c p u m ( a d d r e s s 3 b 1 6 ) 100 s i n g l e - c h i p m o d e r i n g o s c i l l a t o r o s c i l l a t i o n e n a b l e d f ( x i n ) o s c i l l a t i o n ( c e r a m i c / r c ) e n a b l e d c e r a m i c o s c i l l a t i o n a p p l i e d f r o m r i n g o s c i l l a t o r 00 0 0 00 0 0 0 0 0 : = f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) 0 1 : = f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) 1 0 : a p p l i e d f r o m r i n g o s c i l l a t o r ( n o t e 2 ) 1 1 : = f ( x i n ) ( d o u b l e - s p e e d m o d e ) 0 0 00 1 f f 1 6 ff 16 1 00 1 0 p r o c e s s i n g 0 0 00 0 0 0 c l i read prescaler y and timer y and compare their complement with the setting values of prescaler z and timer z t i m e r z i n t e r r u p t p r o c e s s i n g r o u t i n e p r o c e s s i n g rti s e t c p u m o d e r e g i s t e r c p u m ( a d d r e s s 3 b 1 6 ) t y z m ( a d d r e s s 2 0 1 6 ) t c s s ( a d d r e s s 2 e 1 6 ) t i m e r y c o u n t s o u r c e : r i n g o s c i l l a t o r s e l e c t e d t i m e r z : f ( x i n ) / 2 s e l e c t e d timer y: timer mode selected timer y count stop timer z: timer mode selected timer z count stop set timer y, z mode register s e t 0 t o t h e t i m e r y i n t e r r u p t e n a b l e b i t . ( t i m e r y i n t e r r u p t d i s a b l e d ) s e t 0 t o t h e t i m e r z i n t e r r u p t e n a b l e b i t . ( t i m e r z i n t e r r u p t d i s a b l e d ) p resca l er y (add ress 21 16 ) s e t v a l u e t o p r e s c a l e r y , t i m e r y ti mer y (add ress 23 16 ) s e t t i m e r c o u n t s o u r c e s e t r e g i s t e r set value to prescaler z, timer z ( note 3 ) p resca l er z (add ress 25 16 ) t i m e r z p r i m a r y ( a d d r e s s 2 7 1 6 ) s e t 1 t o t h e t i m e r z i n t e r r u p t e n a b l e b i t . ( t i m e r z i n t e r r u p t e n a b l e d ) set 0 to the timer y interrupt request bit. set 0 to the timer z interrupt request bit. t y z m ( a d d r e s s 2 0 1 6 ) timer y count start timer z count start set timer y, z mode register ti mer z division ratio ti mer z primary notes 1: for the concrete time, ask the oscillator manufacture. 2: in this example, this setting cannot be selected. 3: 10 ms = 1/4 mhz ? 2 ? (f9 16 + 1) ? (4f 16 + 1) p r e s c a l e r z w a i t u n t i l f ( x i n ) o s c i l l a t i o n i s s t a b i l i z e d ( n o t e 1 )
7540 group user s manual application 2-139 2.9 oscillation control 2.9.4 oscillation stop detection circuit the oscillation stop detection circuit can be used to detect the stop by some failure or disconnection of an external ceramic oscillation circuit. in this section, the setting method and application example. (1) operation description when the stop of an external oscillation circuit is detected by the oscillation stop detection circuit, the oscillation stop detection status bit of misrg is set to 1 and the internal reset occurs. the 7540 group starts operation by the built-in ring oscillator after system is released from reset. accordingly, error of the external oscillation circuit can be detected by checking the oscillation stop detection status bit after system starts operation. notes 1: when the stop mode is used, set the oscillation stop detection function to invalid . 2: when f(x in ) oscillation is stopped, set the oscillation stop detection function to invalid .
7540 group user s manual 2-140 application 2.9 oscillation control (2) setting method figure 2.9.7 shows the initial setting method oscillation stop detection circuit. figure 2.9.8 shows the setting method for the oscillation stop detection circuit in the main processing. fig. 2.9.7 initial setting method for the oscillation stop detection circuit p r o c e s s 1 : c h e c k t h a t r e s e t b y o s c i l l a t i o n s t o p d e t e c t i o n i s e x e c u t e d b y r e f e r r i n g t h e o s c i l l a t i o n s t o p d e t e c t i o n s t a t u s b i t . process 2: select oscillation mode. b7 b 0 misrg (misrg) [address 38 16 ] o s c i l l a t i o n s t o p d e t e c t i o n s t a t u s b i t 0 : o s c i l l a t i o n s t o p n o t d e t e c t e d 1 : o s c i l l a t i o n s t o p d e t e c t e d * e x e c u t e t h e f o l l o w i n g s e t a t t h e b e g i n n i n g o f p r o g r a m a f t e r s y s t e m i s r e l e a s e d f r o m r e s e t . 0 0 oscillation stop is detected some error occus in the oscillation circuit. do not switch the operation clock and execute the processing when some error occurs. oscillation stop is not detected execute the process 2. b 7b 0 cpu mode register (cpum) [address 3b 16 ] o s c i l l a t i o n m o d e s e l e c t i o n b i t ( n o t e ) 0 : c e r a m i c o s c i l l a t i o n 1 : r c o s c i l l a t i o n p r o c e s s 3 : w a i t o s c i l l a t i o n s t a b i l i z i n g ( n o t e ) . n o t e : t h i s p r o c e s s c a n b e e l i m i n a t e d w h e n t h e r c o s c i l l a t i o n i s s e l e c t e d . f o r t h e o s c i l l a t i o n s t a b i l i z i n g t i m e , a s k t h e o s c i l l a t o r m a n u f a c t u r e . process 4: set the ceramic or rc oscillation stop detection function active bit. b 7b 0 d e t e c t i o n f u n c t i o n a c t i v e ( n o t e ) 0 01 misrg (misrg) [address 38 16 ] n o t e : t h e b i t c a n b e r e w r i t t e n o n l y o n c e a f t e r r e l e a s i n g r e s e t . a f t e r r e w r i t i n g i t i s d i s a b l e t o w r i t e a n y d a t a t o t h e b i t . h o w e v e r , b y r e s e t t h e b i t i s i n i t i a l i z e d a n d c a n b e r e w r i t t e n , a g a i n . ( i t i s n o t d i s a b l e t o w r i t e a n y d a t a t o t h e b i t f o r e m u l a t o r m c u m 3 7 5 4 0 r s s ) . 0 00 0 0 0 0 0 1 0 00 n o t e : w h e n s o m e e r r o r o c c u r s i n t h e o s c i l l a t i o n c i r c u i t , s y s t e m i s r e l e a s e d f r o m r e s e t a f t e r s e t t i n g o f p r o c e s s 4 i s e x e c u t e d . process 5: select clock division ratio. b 7b 0 cpu mode register (cpum) [address 3b 16 ] cl oc k di v i s i on rat i o se l ect i on bi ts b7b6 0 0: f( ) = f(x in )/2 (high-speed mode) 0 1: f( )= f(x in )/8 (middle-speed mode) 1 0: applied from ring oscillator 1 1: f( )=f(x in ) (double-speed mode) ( note ) note: these bits are used only when a ceramic oscillation is selected. do not use these when an rc oscillation is selected. 0 0
7540 group user s manual application 2-141 2.9 oscillation control fig. 2.9.8 setting method for the oscillation stop detection circuit in main processing p r o c e s s : s t a r t r i n g o s c i l l a t i o n w h e n i t i s s t o p p e d . b 7b0 cpu mode register (cpum) [address 3b 16 ] r i n g o s c i l l a t i o r o s c i l l a t i o n e n a b l e d 0 0 p r o c e s s 2 : s e t c e r a m i c o r r c o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n a c t i v e b i t . b 7b 0 d e t e c t i o n f u n c t i o n a c t i v e ( n o t e ) 0 01 m i s r g ( m i s r g ) [ a d d r e s s 3 8 1 6 ] 0 00 0 0 n o t e : w h e n s o m e e r r o r o c c u r s i n t h e o s c i l l a t i o n c i r c u i t , s y s t e m i s r e l e a s e d f r o m r e s e t a f t e r s e t t i n g o f p r o c e s s 2 i s e x e c u t e d .
7540 group user s manual 2-142 application 2.9 oscillation control 2.9.5 state transition in the 7540 group, the operation clock is selected from the following 4 types. f(x in )/2 (high-speed mode) f(x in )/8 (middle-speed mode) ring oscillator f(x in ) (double-speed mode) ( note 1 ) note 1: f(x in ) can be used only at the ceramic oscillation. do not use f(x in ) at rc oscillation. also, in the 7540 group, the function to stop cpu operation by software and to keep cpu wait in the following 2-type low power dissipation. stop mode with the stp instruction ( notes 2, 3, 4, 5, 6, 7 ) wait mode with the wit instruction ( note 8 ) notes 2: when the stop mode is used, set the oscillation stop detection function to invalid . 3: when the stop mode is used, set 0 ( stp instruction enabled) the stp instruction disable bit of the watchdog timer control register. 4: timer 1 can be used to set the oscillation stabilizing time after release of the stp instruction. the oscillation stabilizing time after release of stp instruction can be selected from set automatically / not set automatically by the oscillation stabilizing time set bit after release of the stp instruction of misrg. when 0 is set to this bit, 01 16 is set to timer 1 and ff 16 is set to prescaler 1 automatically. when 1 is set to this bit, nothing is set to timer 1 and prescaler 1. therefore, set the wait time according to the oscillation stabilizing time of the oscillation. also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. 5: the stp instruction cannot be used during cpu is operating by the ring oscillator. 6: when the stop mode is used, stop the ring oscillator oscillation. 7: do not execute the stp instruction during the a-d conversion. 8: when the wait mode is used, stop the clock except the operation clock source. figure 2.9.9 shows the state transition. fig. 2.9.9 state transition s t o p m o d e wait mode wit instruction o s c i l l a t i o n s t o p d e t e c t i o n c i r c u i t v a l i d cpum 4 1 2 misrg 1 1 2 i n t e r r u p t i n t e r r u p t s t p i n s t r u c t i o n wit instruction interrupt m i s r g 1 0 2 cpum 3 1 2 cpum 3 0 2 c p u m 7 6 1 0 2 c p u m 7 6 0 0 2 0 1 2 1 1 2 ( n o t e 2 ) cpum 4 0 2 misrg 1 1 2 m i s r g 1 0 2 r e s e t r e l e a s e d s t a t e 1 o p e r a t i o n c l o c k s o u r c e : f (x i n ) ( n o t e 1 ) f (x i n ) o s c i l l a t i o n e n a b l e d r i n g o s c i l l a t o r s t o p s t a t e 2 o p e r a t i o n c l o c k s o u r c e : f (x i n ) ( n o t e 1 ) f (x i n ) o s c i l l a t i o n e n a b l e d r i n g o s c i l l a t o r e n a b l e d s t a t e 3 o p e r a t i o n c l o c k s o u r c e : r i n g o s c i l l a t o r ( n o t e 3 ) f ( x i n ) o s c i l l a t i o n e n a b l e d r i n g o s c i l l a t o r e n a l b e d s t a t e 4 o p e r a t i o n c l o c k s o u r c e : r i n g o s c i l l a t o r ( n o t e 3 ) f (x i n ) o s c i l l a t i o n s t o p r i n g o s c i l l a t o r e n a l b e d n o t e s o n s w i t c h o f c l o c k ( 1 ) i n o p e r a t i o n c l o c k s o u r c e = f (x i n ) , t h e f o l l o w i n g c a n b e s e l e c t e d f o r t h e c p u c l o c k d i v i s i o n r a t i o . f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) f ( x i n ) ( d o u b l e - s p e e d m o d e , o n l y a t a c e r a m i c o s c i l l a t i o n ) ( 2 ) e x e c u t e t h e s t a t e t r a n s i t i o n s t a t e 3 t o s t a t e 2 o r s t a t e 3 t o s t a t e 2 a f t e r s t a b i l i z i n g x i n o s c i l l a t i o n . ( 3 ) i n o p e r a t i o n c l o c k s o u r c e = r i n g o s c i l l a t o r , t h e m i d d l e - s p e e d m o d e i s s e l e c t e d f o r t h e c p u c l o c k d i v i s i o n r a t i o . ( 4 ) w h e n t h e s t a t e t r a n s i t i o n s t a t e 2 s t a t e 3 s t a t e 4 i s p e r f o r m e d , e x e c u t e t h e n o p i n s t r u c t i o n a s s h o w n b e l o w a c c o r d i n g t o t h e d i v i s i o n r a t i o o f c p u c l o c k . c p u m 7 6 1 0 2 ( s t a t e 2 s t a t e 3 ) n o p i n s t r u c t i o n c p u m 4 1 2 ( s t a t e 3 s t a t e 4 ) d o u b l e - s p e e d m o d e a t r i n g o s c i l l a t o r : n o p ? 3 h i g h - s p e e d m o d e a t r i n g o s c i l l a t o r : n o p ? 1 m i d d l e - s p e e d m o d e a t r i n g o s c i l l a t o r : n o p ? 0 reset state cpum 76 10 2 c p u m 7 6 0 0 2 0 1 2 1 1 2 ( n o t e 2 ) s t a t e 2 o p e r a t i o n c l o c k s o u r c e : f (x i n ) ( n o t e 1 ) f (x i n ) o s c i l l a t i o n e n a b l e d r i n g o s c i l l a t o r e n a b l e d state 3? operation clock source: ring oscillator (note 3) f(x in ) oscillation enabled ring oscillator enalbed
7540 group user s manual application 2-143 2.9 oscillation control fig. 2.9.10 example of mode transition (1) example of control procedure outline : the ring oscillator is used, and the intermittent operation for the low-power dissipation can be realized. specifications: a mode is selected from the following modes 1 to 4 according to the usage condition. the return from mode 1 is executed by the timer a interrupt request which occurs every 0.5 s. mode 1: wait mode by the ring oscillator oscillation operation clock source: ring oscillator cpu stop, ceramic oscillation stop, ring oscillator oscillation mode 2: middle-speed mode by the ring oscillator oscillation operation clock source: ring oscillator cpu operation, ceramic oscillation stop, ring oscillator oscillation mode 3: middle-speed mode by the ceramic oscillation operation clock source: ceramic oscillation cpu operation, ceramic oscillation, ring oscillator oscillation mode 4: double-speed mode by the ceramic oscillation operation clock source: ceramic oscillation cpu operation, ceramic oscillation, ring oscillator oscillation figure 2.9.10 shows an example of mode transition and figure 2.9.11 shows an example of control procedure. p o w e r d i s s i p a t i o n time m o d e 1 m o d e 2 m o d e 1 mode 2 mode 1 mode 2 mode 3 m o d e 1 m o d e 2 cpu operation is started by interrupt of timer underflow c e r a m i c o s c i l l a t i o n s t a r t m i d d l e - s p e e d m o d e ( 1 / 8 ) mode 4 ceramic oscillation double-speed mode (1/1) w a i t m o d e b y r i n g o s c i l l a t i o n c p u s t o p t i m e r o p e r a t i n g
7540 group user s manual 2-144 application 2.9 oscillation control fig. 2.9.11 control procedure n o t e s 1 : a t v c c = 5 v , t h e t i m e r a c o u n t s o u r c e w h e n a r i n g o s c i l l a t o r i s s e l e c t e d a s t h e o p e r a t i o n c l o c k i s a s f o l l o w s ; a b o u t 2 m h z / 1 6 = a b o u t 1 2 5 k h z 2 : w h e n s e t t i n g t h e v a l u e t o t i m e r , s e t i n o r d e r o f l o w - o r d e r b y t e a n d h i g h - o r d e r b y t e f o l l o w i n g . 3 : 0 . 5 s = 1 / 1 2 5 k h z ? ( f 4 2 3 1 6 + 1 ) 4 : f o r t h e c o n c r e t e t i m e , a s k t h e o s c i l l a t o r m a n u f a c t u r e . modes 3, 4 (common) n s w i t c h t o c e r a m i c o s c i l l a t i o n i s r e q u i r e d ? r e s e t s e i c l d c l t 100 00 1 0 cli wit instruction executed w a i t m o d e p r o c e s s i n g timer a interrupt processing routine p r o c e s s i n g p r o c e s s i n g 100 00 0 0 000 10 0 0 p r o c e s s i n g 100 10 0 0 00 0 t a m ( a d d r e s s 1 d 1 6 ) count stop set timer a mode register 00 1 r t i t a m ( a d d r e s s 1 d 1 6 ) t i m e r m o d e s e l e c t e d c o u n t s t o p s e t t i m e r a m o d e r e g i s t e r 00 1 2 3 1 6 f 4 1 6 t i m e r a ( h i g h - o r d e r ) [ a d d r e s s 1 f 1 6 ] set values to timer a ( notes 2, 3 ) set 0 to the timer a interrupt request bit t i m e r a ( l o w - o r d e r ) [ a d d r e s s 1 e 1 6 ] m o d e s 3 , 4 o p e r a t i o n m o d e b y c e r a m i c o s c i l l a t i o n n y switch to double-speed mode is required? rts 1 00 ri ng osc ill ator osc ill at i on ena bl e d x in oscillation (ceramic) stop applied from ring oscillator 00 1 0 o p e r a t i o n m o d e b y c e r a m i c o s c i l l a t i o n m o d e 2 m o d e 1 mode 2 y m o d e 2 mode 3 mode 4 i n i t i a l i z a t i o n s e t c p u m o d e r e g i s t e r c p u m ( a d d r e s s 3 b 1 6 ) s i n g l e - c h i p m o d e r i n g o s c i l l a t o r o s c i l l a t i o n e n a b l e d f ( x i n ) o s c i l l a t i o n ( c e r a m i c ) s t o p c e r a m i c o s c i l l a t i o n a p p l i e d f r o m r i n g o s c i l l a t o r ( n o t e 1 ) s e t c p u m o d e r e g i s t e r c p u m ( a d d r e s s 3 b 1 6 ) s e t 0 t o t h e t i m e r a i n t e r r u p t e n a b l e b i t . ( t i m e r a i n t e r r u p t d i s a b l e d ) ti mer a di v i s i on rat i o (fi xe d) t i m e r a s e t t i n g v a l u e wait until f(x in ) oscillation is stabilized ( note 4 ) s e t c p u m o d e r e g i s t e r c p u m ( a d d r e s s 3 b 1 6 ) d o u b l e - s p e e d m o d e set cpu mode register c p u m ( a d d r e s s 3 b 1 6 ) set cpu mode register c p u m ( a d d r e s s 3 b 1 6 ) s e t 0 t o t h e t i m e r a i n t e r r u p t e n a b l e b i t . ( t i m e r a i n t e r r u p t d i s a b l e d ) s e t 0 t o o t h e r i n t e r r u p t e n a b l e b i t s . ( o t h e r i n t e r r u p s d i s a b l e d ) tam(address 1d 16 ) count start set timer a mode register f(x in ) osc ill at i on ( ceram i c ) ena bl e d m i d d l e - s p e e d m o d e
7540 group user s manual application 2-145 2.9 oscillation control 2.9.6 notes on oscillation stop detection circuit notes on using oscillation stop detection circuit are described below. (1) note on ring oscillator ? the 7540 group starts operation by the ring oscillator. (2) notes on oscillation circuit stop detection circuit ? when the stop mode is used, set the oscillation stop detection function to invalid . ? when f(x in ) oscillation is stopped, set the oscillation stop detection function to invalid . ? the oscillation stop detection circuit is not included in the emulator mcu m37540rss . (3) notes on stop mode ? when the stop mode is used, set the oscillation stop detection function to invalid . ? when the stop mode is used, set 0 ( stp instruction enabled) to the stp instruction disable bit of the watchdog timer control register. ? timer 1 can be used to set the oscillation stabilizing time after release of the stp instruction. the oscillation stabilizing time after release of stp instruction can be selected from set automatically / not set automatically by the oscillation stabilizing time set bit after release of the stp instruction of misrg. when 0 is set to this bit, 01 16 is set to timer 1 and ff 16 is set to prescaler 1 automatically. when 1 is set to this bit, nothing is set to timer 1 and prescaler 1. therefore, set the wait time according to the oscillation stabilizing time of the oscillation. also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. ? the stp instruction cannot be used during cpu is operating by the ring oscillator. ? when the stop mode is used, stop the ring oscillator oscillation. ? do not execute the stp instruction during the a-d conversion. (4) note on wait mode ? when the wait mode is used, stop the clock except the operation clock source. (5) notes on state transition ? when the operation clock source is f(x in ), the cpu clock division ratio can be selected from the following; f(x in )/2 (high-speed mode) f(x in )/8 (middle-speed mode) f(x in ) (double-speed mode) the double-speed mode can be used only at ceramic oscillation. do not use the mode at rc oscillation. ? stabilize the f(x in ) oscillation to change the operation clock source from the ring oscillator to f(x in ).
7540 group user s manual 2-146 application 2.9 oscillation control ? when the ring oscillation is used as the operation clock, the cpu clock division ratio is the middle- speed mode. ? when the state transition state 2 state 3 state 4 is performed, execute the nop instruction as shown below according to the division ratio of cpu clock. cpum 76 10 2 (state 2 state 3) nop instruction cpum 4 1 2 (state 3 state 4) double-speed mode at ring oscillator: nop ? 3 high-speed mode at ring oscillator: nop ? 1 middle-speed mode at ring oscillator: nop ? 0
chapter 3 appendix 3.1 electrical characteristics 3.2 typical characteristics 3.3 notes on use 3.4 countermeasures against noise 3.5 list of registers 3.6 package outline 3.7 list of instruction code 3.8 machine instructions 3.9 sfr memory map 3.10 pin configurations 3.11 differences between 7540 group and 7531 group
appendix 7540 group user? manual 3.1 electrical characteristics 3-2 ?.3 to 6.5 ( note 1 ) ?.3 to v cc + 0.3 ?.3 to v cc + 0.3 ?.3 to 13 ?.3 to v cc + 0.3 300 ( note 3 ) ?0 to 85 ?0 to 125 power source voltage input voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 , v ref input voltage reset, x in input voltage cnv ss ( note 2 ) output voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 , x out power dissipation operating temperature storage temperature v v v v v mw ? ? v cc v i v i v i v o p d t opr t stg conditions symbol ratings unit parameter all voltages are based on v ss . output transistors are cut off. ta = 25? notes 1: this is the rating value for the mask rom version. the rating value for the one time prom version is ?.3 to 7.0 v. 2: it is a rating only for the one time prom version. connect to v ss for the mask rom version. 3: 200 mw for the 32p6u package product. 3.1 electrical characteristics 3.1.1 7540 group (general purpose) applied to: m37540m2-xxxfp/sp/gp, m37540m4-xxxfp/sp/gp, m37540e2fp/sp/gp, m37540e8fp/sp/gp (1) absolute maximum ratings (general purpose) table 3.1.1 absolute maximum ratings
appendix 7540 group user? manual 3-3 3.1 electrical characteristics (2) recommended operating conditions (general purpose) table 3.1.2 recommended operating conditions (1) (v cc = 2.2 to 5.5 v, ta = ?0 to 85 ?, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 v cc v cc 4.0 2.4 2.2 4.5 4.0 2.4 2.2 4.0 2.4 2.2 2.0 0.8v cc 2.0 0.8v cc 0 0 0 0 min. typ. max. symbol parameter unit power source voltage (ceramic) f(x in ) = 8 mhz (high-, middle-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 2 mhz (high-, middle-speed mode) f(x in ) = 6 mhz (double-speed mode) f(x in ) = 4 mhz (double-speed mode) f(x in ) = 2 mhz (double-speed mode) f(x in ) = 1 mhz (double-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 2 mhz (high-, middle-speed mode) f(x in ) = 1 mhz (high-, middle-speed mode) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 limits v cc v v v v v v v v v v v v v v v v v v v ma ma ma ma ma ma power source voltage analog reference voltage ??input voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) ??input voltage reset, x in ??input voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) ??input voltage reset, cnv ss ??input voltage x in ??total peak output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??total peak output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 7 ??total peak output current (note 2) p3 0 ?3 6 ??total average output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??total average output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 7 ??total average output current (note 2) p3 0 ?3 6 note 1: vcc = 4.0 to 5.5v 2: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. v cc v cc 0.3v cc 0.8 0.2v cc 0.16v cc ?0 80 60 ?0 40 30 v ss v ref v ih v ih v ih v il v il v il v il i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) power source voltage (rc)
appendix 7540 group user? manual 3.1 electrical characteristics 3-4 table 3.1.3 recommended operating conditions (2) (v cc = 2.2 to 5.5 v, ta = ?0 to 85 ?, unless otherwise noted) ??peak output current (note 1) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??peak output current (note 1) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 7 ??peak output current (note 1) p3 0 ?3 6 ??average output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??average output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 7 ??average output current (note 2) p3 0 ?3 6 internal clock oscillation frequency (note 3) v cc = 4.5 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 2.2 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.2 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at rc oscillation high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at rc oscillation high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.2 to 5.5 v at rc oscillation high-, middle-speed mode symbol parameter limits max. typ. min. ?0 10 30 ? 5 15 6 4 2 1 8 4 2 4 2 1 notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) in an average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50 %. i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) ma ma ma ma ma ma mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz unit
appendix 7540 group user? manual 3-5 3.1 electrical characteristics (3) electrical characteristics (general purpose) table 3.1.4 electrical characteristics (1) v cc = 2.2 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit i oh = ? ma v cc = 4.0 to 5.5 v i oh = ?.0 ma v cc = 2.2 to 5.5 v i ol = 5 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma v cc = 2.2 to 5.5 v i ol = 15 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 10 ma v cc = 2.2 to 5.5 v v i = v cc (pin floating. pull up transistors ?ff? v i = v cc v i = v cc v i = v ss (pin floating. pull up transistors ?ff? v i = v ss v i = v ss v i = v ss (pull up transistors ?n? when clock stopped v cc = 5.0 v, ta = 25 ? v cc = 5.0 v, ta = 25 ? test conditions v cc ?.5 v cc ?.0 2.0 1000 62.5 ??output voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 (note 1) ??output voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 7 ??output voltage p3 0 ?3 6 hysteresis cntr 0 , cntr 1 , int 0 , int 1 (note 2) p0 0 ?0 7 (note 3) hysteresis r x d, s clk1 , s clk2 , s data2 (note 2) hysteresis reset ??input current p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??input current reset ??input current x in ??input current p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??input current reset, cnv ss ??input current x in ??input current p0 0 ?0 7 , p3 0 ?3 7 ram hold voltage ring oscillator oscillation frequency oscillation stop detection circuit detection frequency 1.5 0.3 1.0 2.0 0.3 1.0 5.0 5.0 ?.0 ?.0 ?.5 5.5 3000 187.5 v v v v v v v v v v v a a a a a a ma v khz khz v oh v ol v ol v t+ ? t v t+ ? t v t+ ? t i ih i ih i ih i il i il i il i il v ram r osc d osc 0.4 0.5 0.5 4.0 ?.0 ?.2 2000 125 notes 1: p1 1 is measured when the p1 1 /t x d 1 p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is ?? 2: r x d 1 , s clk1 , s clk2 , s data2 , int 0 , and int 1 have hysteresises only when bits 0 to 2 of the port p1p3 control register are set to ??(cmos level). 3: it is available only when operating key-on wake up.
appendix 7540 group user? manual 3.1 electrical characteristics 3-6 table 3.1.5 electrical characteristics (2) (v cc = 2.2 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit test conditions power source current 8.0 1.5 10.0 5.0 1000 3.2 450 1.0 10 6.5 1.2 8.0 5.0 900 3.2 450 1.0 10 ma ma ma ma a ma ma a ma a a ma ma ma ma a ma ma a ma a a i cc 5.0 0.5 6.0 2.0 350 1.6 0.2 150 0.5 0.1 3.5 0.4 4.5 2.0 300 1.6 0.2 150 0.5 0.1 high-speed mode, f(x in ) = 8 mhz output transistors ?ff high-speed mode, f(x in ) = 2 mhz, v cc = 2.2 v output transistors ?ff double-speed mode, f(x in ) = 6 mhz output transistors ?ff middle-speed mode, f(x in ) = 8 mhz output transistors ?ff ring oscillator operation mode, v cc = 5 v output transistors ?ff f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors ?ff f(x in ) = 2 mhz, v cc = 2.2 v (in wit state), functions except timer 1 disabled, output transistors ?ff ring oscillator operation mode, v cc = 5v output transistors ?ff increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors ?ff high-speed mode, f(x in ) = 8 mhz output transistors ?ff high-speed mode, f(x in ) = 2 mhz, v cc = 2.2 v output transistors ?ff double-speed mode, f(x in ) = 6 mhz output transistors ?ff middle-speed mode, f(x in ) = 8 mhz output transistors ?ff ring oscillator operation mode, v cc = 5 v output transistors ?ff f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors ?ff f(x in ) = 2 mhz, v cc = 2.2 v (in wit state), functions except timer 1 disabled, output transistors ?ff ring oscillator operation mode, v cc = 5v output transistors ?ff increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors ?ff one time prom version mask rom version ta = 25 ? ta = 85 ? ta = 25 ? ta = 85 ?
appendix 7540 group user? manual 3-7 3.1 electrical characteristics (4) a-d converter characteristics (general purpose) table 3.1.6 a-d converter characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current min. typ. max. symbol parameter limits unit test conditions v cc = 2.7 to 5.5 v ta = 25 ? v cc = 2.7 to 5.5 v ta = 25 ? v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v v ref = 3.0 v v cc = 2.7 to 5.5 v ta = 25 ? v cc = 2.7 to 5.5 v ta = 25 ? v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v v ref = 3.0 v bits lsb lsb mv mv mv mv tc(x in ) k ? a a bits lsb lsb mv mv mv mv tc(x in ) k ? a a 10 ? ?.9 20 15 5125 3075 122 200 120 5.0 10 ? ?.5 35 21 5150 3090 122 200 120 5.0 v ot v fst t conv r ladder i vref i i(ad) v ot v fst t conv r ladder i vref i i(ad) 5 3 5115 3069 55 150 70 15 9 5125 3075 55 150 70 0 0 5105 3060 50 50 0 0 5105 3060 50 50 one time prom version mask rom version
appendix 7540 group user? manual 3.1 electrical characteristics 3-8 (5) timing requirements (general purpose) table 3.1.7 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input ??pulse width external clock input cycle time external clock input ??pulse width external clock input ??pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input ??pulse width cntr 0 , int 0 , int 1 , input ??pulse width cntr 1 input cycle time cntr 1 input ??pulse width cntr 1 input ??pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input ??pulse width (note) serial i/o1 clock input ??pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input ??pulse width serial i/o2 clock input ??pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 ? clk1 ) t h (s clk1 ?xd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 ? clk2 ) t h (s clk2 ? data2 ) 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 1000 400 400 200 200 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to ??(clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is ??(clock asynchronous serial i/o1 is selected), the rating values are divid ed by 4. table 3.1.8 timing requirements (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input ??pulse width external clock input cycle time external clock input ??pulse width external clock input ??pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input ??pulse width cntr 0 , int 0 , int 1 , input ??pulse width cntr 1 input cycle time cntr 1 input ??pulse width cntr 1 input ??pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input ??pulse width (note) serial i/o1 clock input ??pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input ??pulse width serial i/o2 clock input ??pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 ? clk1 ) t h (s clk1 ?xd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 ? clk2 ) t h (s clk2 ? data2 ) 2 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to ??(clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is ??(clock asynchronous serial i/o1 is selected), the rating values are divid ed by 4.
appendix 7540 group user? manual 3-9 3.1 electrical characteristics table 3.1.9 timing requirements (3) (v cc = 2.2 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input ??pulse width external clock input cycle time external clock input ??pulse width external clock input ??pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input ??pulse width cntr 0 , int 0 , int 1 , input ??pulse width cntr 1 input cycle time cntr 1 input ??pulse width cntr 1 input ??pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input ??pulse width (note) serial i/o1 clock input ??pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input ??pulse width serial i/o2 clock input ??pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 ? clk1 ) t h (s clk1 ?xd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 ? clk2 ) t h (s clk2 ? data2 ) 2 500 200 200 1000 460 460 8000 3200 3200 4000 1900 1900 800 400 4000 1900 1900 800 800 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to ??(clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is ??(clock asynchronous serial i/o1 is selected), the rating values are divid ed by 4.
appendix 7540 group user? manual 3.1 electrical characteristics 3-10 (6) switching characteristics (general purpose) table 3.1.10 switching characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 t c (s clk2 )/2?0 t c (s clk2 )/2?0 0 min. typ. max. symbol parameter limits unit t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 ?xd 1 ) t v (s clk1 ?xd 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 ? data2 ) t v (s clk2 ? data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output ??pulse width serial i/o1 clock output ??pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ??pulse width serial i/o2 clock output ??pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) note 1: pin x out is excluded. table 3.1.11 switching characteristics (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit 350 50 50 350 50 50 50 50 note 1: pin x out is excluded. t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 ? x d 1 ) t v (s clk1 ? x d 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 ? data2 ) t v (s clk2 ? data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output ??pulse width serial i/o1 clock output ??pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ??pulse width serial i/o2 clock output ??pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 t c (s clk2 )/2?0 t c (s clk2 )/2?0 0 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 140 30 30 140 30 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
appendix 7540 group user? manual 3-11 3.1 electrical characteristics table 3.1.12 switching characteristics (3) (v cc = 2.2 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit 450 70 70 450 70 70 70 70 note 1: pin x out is excluded. fig. 3.1.1 switching characteristics measurement circuit diagram (general purpose) / / / measured output pin cmos output 100 pf t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 ? x d 1 ) t v (s clk1 ? x d 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 ? data2 ) t v (s clk2 ? data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output ??pulse width serial i/o1 clock output ??pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ??pulse width serial i/o2 clock output ??pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 t c (s clk2 )/2?0 t c (s clk2 )/2?0 0 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
appendix 7540 group user? manual 3.1 electrical characteristics 3-12 fig. 3.1.2 timing chart (general purpose) 0.2v cc t d (s clk1 -txd 1 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (rxd 1 -s clk1 )t h (s clk1 -rxd 1 ) t v (s clk1 -txd 1 ) t c (s clk1 ) t wl (s clk1 ) t wh (s clk1 ) r x d 1 (at receive) s clk1 0.2v cc t wl (x in ) 0.8v cc t wh (x in ) t c (x in ) x in 0.2v cc 0.8v cc t w (reset) reset 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) t c (cntr 0 ) t x d 1 (at transmit) cntr 0 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) int 0 , int 1 0.2v cc t wl (cntr 1 ) 0.8v cc t wh (cntr 1 ) t c (cntr 1 ) cntr 1 0.2v cc t d (s clk2 -s data2 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (s data2 -s clk2 )t h (s clk2 -s data2 ) t v (s clk2 -s data2 ) t c (s clk2 ) t wl (s clk2 ) t wh (s clk2 ) s data2 (at receive) s clk2 s data2 (at transmit)
appendix 7540 group user s manual 3-13 3.1 electrical characteristics 3.1.2 7540group (extended operating temperature version) applied to: m37540m2t-xxxfp/gp, m37540m4t-xxxfp/gp, m37540e8t-xxxfp/gp (2) absolute maximum ratings (extended operating temperature version) table 3.1.13 absolute maximum ratings 0.3 to 6.5 ( note 1 ) 0.3 to v cc + 0.3 0.3 to v cc + 0.3 0.3 to v cc + 0.3 300 ( note 2 ) 40 to 85 65 to 150 power source voltage input voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 , v ref input voltage reset, x in , cnv ss output voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 , x out power dissipation operating temperature storage temperature v v v v mw c c v cc v i v i v o p d t opr t stg conditions symbol ratings unit parameter all voltages are based on v ss . output transistors are cut off. ta = 25 c notes 1: this is the rating value for the mask rom version. the rating value for the one time prom version is 0.3 to 7.0 v. 2: 200 mw for the 32p6u package product.
appendix 7540 group user s manual 3.1 electrical characteristics 3-14 (2) recommended operating conditions (extended operating temperature version) table 3.1.14 recommended operating conditions (1) (v cc = 2.4 to 5.5 v, ta = ?0 to 85 ?, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 v cc v cc v cc v cc 4.0 2.4 4.5 4.0 2.4 4.0 2.4 2.0 0.8v cc 2.0 0.8v cc 0 0 0 0 min. typ. max. symbol parameter unit power source voltage (ceramic) f(x in ) = 8 mhz (high-, middle-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 6 mhz (double-speed mode) f(x in ) = 4 mhz (double-speed mode) f(x in ) = 2 mhz (double-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 2 mhz (high-, middle-speed mode) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 limits v cc v v v v v v v v v v v v v v v v ma ma ma ma ma ma power source voltage analog reference voltage h input voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 h input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) h input voltage reset, x in l input voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) l input voltage reset, cnv ss l input voltage x in h total peak output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l total peak output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l total peak output current (note 2) p3 0 p3 6 h total average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l total average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l total average output current (note 2) p3 0 p3 6 note 1: vcc = 4.0 to 5.5v 2: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 0.3v cc 0.8 0.2v cc 0.16v cc 80 80 60 40 40 30 v ss v ref v ih v ih v ih v il v il v il v il i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) power source voltage (rc)
appendix 7540 group user s manual 3-15 3.1 electrical characteristics table 3.1.15 recommended operating conditions (2) (v cc = 2.4 to 5.5 v, ta = ?0 to 85 ?, unless otherwise noted) h peak output current (note 1) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l peak output current (note 1) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l peak output current (note 1) p3 0 p3 6 h average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l average output current (note 2) p3 0 p3 6 internal clock oscillation frequency (note 3) v cc = 4.5 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at rc oscillation high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at rc oscillation high-, middle-speed mode ma ma ma ma ma ma mhz mhz mhz mhz mhz mhz mhz symbol parameter limits unit max. typ. min. 10 10 30 5 5 15 6 4 2 8 4 4 2 notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) in an average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50 %. i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in )
appendix 7540 group user s manual 3.1 electrical characteristics 3-16 (3) electrical characteristics (extended operating temperature version) table 3.1.16 electrical characteristics (1) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit i oh = 5 ma v cc = 4.0 to 5.5 v i oh = 1.0 ma v cc = 2.4 to 5.5 v i ol = 5 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma v cc = 2.4 to 5.5 v i ol = 15 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 10 ma v cc = 2.4 to 5.5 v v i = v cc (pin floating. pull up transistors off ) v i = v cc v i = v cc v i = v ss (pin floating. pull up transistors off ) v i = v ss v i = v ss v i = v ss (pull up transistors on ) when clock stopped v cc = 5.0 v, ta = 25 c v cc = 5.0 v, ta = 25 c test conditions v cc 1.5 v cc 1.0 2.0 1000 62.5 h output voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 (note 1) l output voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l output voltage p3 0 p3 6 hysteresis cntr 0 , cntr 1 , int 0 , int 1 (note 2) p0 0 p0 7 (note 3) hysteresis r x d, s clk1 , s clk2 , s data2 (note 2) hysteresis reset h input current p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 h input current reset h input current x in l input current p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l input current reset, cnv ss l input current x in l input current p0 0 p0 7 , p3 0 p3 7 ram hold voltage ring oscillator oscillation frequency oscillation stop detection circuit detection frequency 1.5 0.3 1.0 2.0 0.3 1.0 5.0 5.0 5.0 5.0 0.5 5.5 3000 187.5 v v v v v v v v v v v a a a a a a ma v khz khz v oh v ol v ol v t+ v t v t+ v t v t+ v t i ih i ih i ih i il i il i il i il v ram r osc d osc 0.4 0.5 0.5 4.0 4.0 0.2 2000 125 notes 1: p1 1 is measured when the p1 1 /t x d 1 p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2: r x d1, s clk1 , s clk2 , s data2 , int 0 , and int 1 have hysteresises only when bits 0 to 2 of the port p1p3 control register are set to 0 (cmos level). 3: it is available only when operating key-on wake up.
appendix 7540 group user s manual 3-17 3.1 electrical characteristics table 3.1.17 electrical characteristics (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol limits unit 8.0 1.5 10.0 5.0 1000 3.2 450 1.0 10 6.5 1.2 8.0 5.0 900 3.2 450 1.0 10 ma ma ma ma a ma ma a ma a a ma ma ma ma a ma ma a ma a a i cc 5.0 0.5 6.0 2.0 350 1.6 0.2 150 0.5 0.1 3.5 0.4 4.5 2.0 300 1.6 0.2 150 0.5 0.1 high-speed mode, f(x in ) = 8 mhz output transistors off high-speed mode, f(x in ) = 2 mhz, v cc = 2.4 v output transistors off double-speed mode, f(x in ) = 6 mhz, output transistors off middle-speed mode, f(x in ) = 8 mhz, output transistors off ring oscillator operation mode, v cc = 5 v output transistors off f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors off f(x in ) = 2 mhz, v cc = 2.4 v (in wit state), functions except timer 1 disabled, output transistors off ring oscillator operation mode, v cc = 5v (in wit state), functions except timer 1 disabled, output transistors off increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors off high-speed mode, f(x in ) = 8 mhz output transistors off high-speed mode, f(x in ) = 2 mhz, v cc = 2.4 v output transistors off double-speed mode, f(x in ) = 6 mhz output transistors off middle-speed mode, f(x in ) = 8 mhz output transistors off ring oscillator operation mode, v cc = 5 v output transistors off f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors off f(x in ) = 2 mhz, v cc = 2.4 v (in wit state), functions except timer 1 disabled, output transistors off ring oscillator operation mode, v cc = 5v (in wit state), functions except timer 1 disabled, output transistors off increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors off ta = 25 c ta = 85 c test conditions one time prom version mask rom version ta = 25 c ta = 85 c
appendix 7540 group user? manual 3.1 electrical characteristics 3-18 (4) a-d converter characteristics (extended operating temperature version) table 3.1.18 a-d converter characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current min. typ. max. symbol parameter limits unit test conditions v cc = 2.7 to 5.5 v ta = 25 ? v cc = 2.7 to 5.5 v ta = 25 ? v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v v ref = 3.0 v v cc = 2.7 to 5.5 v ta = 25 ? v cc = 2.7 to 5.5 v ta = 25 ? v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v v ref = 3.0 v bits lsb lsb mv mv mv mv tc(x in ) k ? a a bits lsb lsb mv mv mv mv tc(x in ) k ? a a 10 ? ?.9 20 15 5125 3075 122 200 120 5.0 10 ? ?.5 35 21 5150 3090 122 200 120 5.0 v ot v fst t conv r ladder i vref i i(ad) v ot v fst t conv r ladder i vref i i(ad) 5 3 5115 3069 55 150 70 15 9 5125 3075 55 150 70 0 0 5105 3060 50 50 0 0 5105 3060 50 30 one time prom version mask rom version
appendix 7540 group user s manual 3-19 3.1 electrical characteristics (5) timing requirements (extended operating temperature version) table 3.1.19 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input h pulse width cntr 0 , int 0 , int 1 , input l pulse width cntr 1 input cycle time cntr 1 input h pulse width cntr 1 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 s clk1 ) t h (s clk1 rxd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 s clk2 ) t h (s clk2 s data2 ) 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 1000 400 400 200 200 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to 1 (clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is 0 (clock asynchronous serial i/o1 is selected), the rating values are divided by 4. table 3.1.20 timing requirements (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input h pulse width cntr 0 , int 0 , int 1 , input l pulse width cntr 1 input cycle time cntr 1 input h pulse width cntr 1 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 s clk1 ) t h (s clk1 rxd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 s clk2 ) t h (s clk2 s data2 ) 2 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to 1 (clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is 0 (clock asynchronous serial i/o1 is selected), the rating values are divided by 4.
appendix 7540 group user s manual 3.1 electrical characteristics 3-20 fig. 3.1.3 switching characteristics measurement circuit diagram (extended operating temperature) / / / measured output pin cmos output 100 pf (6) switching characteristics (extended operating temperature version) table 3.1.21 switching characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) t c (s clk1 )/2 30 t c (s clk1 )/2 30 30 t c (s clk2 )/2 30 t c (s clk2 )/2 30 0 min. typ. max. symbol parameter limits unit t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 txd 1 ) t v (s clk1 txd 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 s data2 ) t v (s clk2 s data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) note 1: pin x out is excluded. table 3.1.22 switching characteristics (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit 350 50 50 350 50 50 50 50 note 1: pin x out is excluded. t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 t x d 1 ) t v (s clk1 t x d 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 s data2 ) t v (s clk2 s data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) t c (s clk1 )/2 50 t c (s clk1 )/2 50 30 t c (s clk2 )/2 50 t c (s clk2 )/2 50 0 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 140 30 30 140 30 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
appendix 7540 group user s manual 3-21 3.1 electrical characteristics fig. 3.1.4 timing chart (extended operating temperature version) 0.2v cc t d (s clk1 -txd 1 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (rxd 1 -s clk1 )t h (s clk1 -rxd 1 ) t v (s clk1 -txd 1 ) t c (s clk1 ) t wl (s clk1 ) t wh (s clk1 ) r x d 1 (at receive) s clk1 0.2v cc t wl (x in ) 0.8v cc t wh (x in ) t c (x in ) x in 0.2v cc 0.8v cc t w (reset) reset 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) t c (cntr 0 ) t x d 1 (at transmit) cntr 0 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) int 0 , int 1 0.2v cc t wl (cntr 1 ) 0.8v cc t wh (cntr 1 ) t c (cntr 1 ) cntr 1 0.2v cc t d (s clk2 -s data2 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (s data2 -s clk2 )t h (s clk2 -s data2 ) t v (s clk2 -s data2 ) t c (s clk2 ) t wl (s clk2 ) t wh (s clk2 ) s data2 (at receive) s clk2 s data2 (at transmit)
appendix 7540 group user s manual 3.1 electrical characteristics 3-22 3.1.3 7540group (extended operating temperature 125 ? version) applied to: m37540m2v-xxxfp/gp, m37540m4v-xxxfp/gp, m37540e8v-xxxfp/gp (1) absolute maximum ratings (extended operating temperature 125 ? version) table 3.1.23 absolute maximum ratings 0.3 to 6.5 ( note 1 ) 0.3 to v cc + 0.3 0.3 to v cc + 0.3 0.3 to v cc + 0.3 300 ( note 2 ) 40 to 125 ( note 3 ) 65 to 150 power source voltage input voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 , v ref input voltage reset, x in , cnv ss output voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 , x out power dissipation operating temperature storage temperature v v v v mw c c v cc v i v i v o p d t opr t stg conditions symbol ratings unit parameter all voltages are based on v ss . output transistors are cut off. ta = 25 c notes 1: this is the rating value for the mask rom version. the rating value for the one time prom version is 0.3 to 7.0 v. 2: 200 mw for the 32p6u package product. 3: in this version, the operating temperature range and total time are limited as follows; 55 c to 85 c: within total 6000 hours, 85 c to 125 c: within total 1000 hours.
appendix 7540 group user s manual 3-23 3.1 electrical characteristics (2) recommended operating conditions (extended operating temperature 125 ? version) table 3.1.24 recommended operating conditions (1) (v cc = 2.4 to 5.5 v, ta = ?0 to 125 ?, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 v cc v cc v cc v cc 4.0 2.4 4.0 2.4 4.0 2.4 2.0 0.8v cc 2.0 0.8v cc 0 0 0 0 min. typ. max. symbol parameter unit power source voltage (ceramic) f(x in ) = 8 mhz (high-, middle-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 4 mhz (double-speed mode) f(x in ) = 2 mhz (double-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 2 mhz (high-, middle-speed mode) 5.0 5.0 5.0 5.0 5.0 5.0 0 limits v cc v v v v v v v v v v v v v v v ma ma ma ma ma ma power source voltage analog reference voltage h input voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 h input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) h input voltage reset, x in l input voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) l input voltage reset, cnv ss l input voltage x in h total peak output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l total peak output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l total peak output current (note 2) p3 0 p3 6 h total average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l total average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l total average output current (note 2) p3 0 p3 6 note 1: vcc = 4.0 to 5.5v 2: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 0.3v cc 0.8 0.2v cc 0.16v cc 80 80 60 40 40 30 v ss v ref v ih v ih v ih v il v il v il v il i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) power source voltage (rc)
appendix 7540 group user s manual 3.1 electrical characteristics 3-24 table 3.1.25 recommended operating conditions (2) (v cc = 2.4 to 5.5 v, ta = ?0 to 125 ?, unless otherwise noted) h peak output current (note 1) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l peak output current (note 1) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l peak output current (note 1) p3 0 p3 6 h average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l average output current (note 2) p3 0 p3 6 internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at rc oscillation high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at rc oscillation high-, middle-speed mode ma ma ma ma ma ma mhz mhz mhz mhz mhz mhz symbol parameter limits unit max. typ. min. 10 10 30 5 5 15 4 2 8 4 4 2 notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) in an average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50 %. i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in )
appendix 7540 group user s manual 3-25 3.1 electrical characteristics (3) electrical characteristics (extended operating temperature 125 ? version) table 3.1.26 electrical characteristics (1) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit i oh = 5 ma v cc = 4.0 to 5.5 v i oh = 1.0 ma v cc = 2.4 to 5.5 v i ol = 5 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma v cc = 2.4 to 5.5 v i ol = 15 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 10 ma v cc = 2.4 to 5.5 v v i = v cc (pin floating. pull up transistors off ) v i = v cc v i = v cc v i = v ss (pin floating. pull up transistors off ) v i = v ss v i = v ss v i = v ss (pull up transistors on ) when clock stopped v cc = 5.0 v, ta = 25 c v cc = 5.0 v, ta = 25 c test conditions v cc 1.5 v cc 1.0 2.0 1000 62.5 h output voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 (note 1) l output voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l output voltage p3 0 p3 6 hysteresis cntr 0 , cntr 1 , int 0 , int 1 (note 2) p0 0 p0 7 (note 3) hysteresis r x d, s clk1 , s clk2 , s data2 (note 2) hysteresis reset h input current p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 h input current reset h input current x in l input current p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l input current reset, cnv ss l input current x in l input current p0 0 p0 7 , p3 0 p3 7 ram hold voltage ring oscillator oscillation frequency oscillation stop detection circuit detection frequency 1.5 0.3 1.0 2.0 0.3 1.0 5.0 5.0 5.0 5.0 0.5 5.5 3000 187.5 v v v v v v v v v v v a a a a a a ma v khz khz v oh v ol v ol v t+ v t v t+ v t v t+ v t i ih i ih i ih i il i il i il i il v ram r osc d osc 0.4 0.5 0.5 4.0 4.0 0.2 2000 125 notes 1: p1 1 is measured when the p1 1 /t x d 1 p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2: r x d1, s clk1 , s clk2 , s data2 , int 0 , and int 1 have hysteresises only when bits 0 to 2 of the port p1p3 control register are set to 0 (cmos level). 3: it is available only when operating key-on wake up.
appendix 7540 group user s manual 3.1 electrical characteristics 3-26 table 3.1.27 electrical characteristics (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) min. typ. max. symbol limits unit 8.0 1.5 5.0 1000 3.2 450 1.0 50 6.5 1.2 5.0 900 3.2 450 1.0 50 ma ma ma a ma ma a ma a a ma ma ma a ma ma a ma a a i cc 5.0 0.5 2.0 350 1.6 0.2 150 0.5 0.1 3.5 0.4 2.0 300 1.6 0.2 150 0.5 0.1 high-speed mode, f(x in ) = 8 mhz output transistors off high-speed mode, f(x in ) = 2 mhz, v cc = 2.4 v output transistors off middle-speed mode, f(x in ) = 8 mhz, output transistors off ring oscillator operation mode, v cc = 5 v output transistors off f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors off f(x in ) = 2 mhz, v cc = 2.4 v (in wit state), functions except timer 1 disabled, output transistors off ring oscillator operation mode, v cc = 5v (in wit state), functions except timer 1 disabled, output transistors off increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors off high-speed mode, f(x in ) = 8 mhz output transistors off high-speed mode, f(x in ) = 2 mhz, v cc = 2.4 v output transistors off middle-speed mode, f(x in ) = 8 mhz, output transistors off ring oscillator operation mode, v cc = 5 v output transistors off f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors off f(x in ) = 2 mhz, v cc = 2.4 v (in wit state), functions except timer 1 disabled, output transistors off ring oscillator operation mode, v cc = 5v (in wit state), functions except timer 1 disabled, output transistors off increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors off ta = 25 c ta = 125 c test conditions one time prom version mask rom version ta = 25 c ta = 125 c
appendix 7540 group user? manual 3-27 3.1 electrical characteristics (4) a-d converter characteristics (extended operating temperature 125 ? version) table 3.1.28 a-d converter characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current min. typ. max. symbol parameter limits unit test conditions v cc = 2.7 to 5.5 v ta = 25 ? v cc = 2.7 to 5.5 v ta = 25 ? v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v v ref = 3.0 v v cc = 2.7 to 5.5 v ta = 25 ? v cc = 2.7 to 5.5 v ta = 25 ? v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v v ref = 3.0 v bits lsb lsb mv mv mv mv tc(x in ) k ? a a bits lsb lsb mv mv mv mv tc(x in ) k ? a a 10 ? ?.9 20 15 5125 3075 122 200 120 7.0 10 ? ?.5 35 21 5150 3090 122 200 120 7.0 v ot v fst t conv r ladder i vref i i(ad) v ot v fst t conv r ladder i vref i i(ad) 5 3 5115 3069 55 150 70 15 9 5125 3075 55 150 70 0 0 5105 3060 50 30 0 0 5105 3060 50 30 one time prom version mask rom version
appendix 7540 group user s manual 3.1 electrical characteristics 3-28 (5) timing requirements (extended operating temperature 125 ? version) table 3.1.29 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input h pulse width cntr 0 , int 0 , int 1 , input l pulse width cntr 1 input cycle time cntr 1 input h pulse width cntr 1 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 s clk1 ) t h (s clk1 rxd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 s clk2 ) t h (s clk2 s data2 ) 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 1000 400 400 200 200 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to 1 (clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is 0 (clock asynchronous serial i/o1 is selected), the rating values are divided by 4. table 3.1.30 timing requirements (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input h pulse width cntr 0 , int 0 , int 1 , input l pulse width cntr 1 input cycle time cntr 1 input h pulse width cntr 1 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 s clk1 ) t h (s clk1 rxd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 s clk2 ) t h (s clk2 s data2 ) 2 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to 1 (clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is 0 (clock asynchronous serial i/o1 is selected), the rating values are divided by 4.
appendix 7540 group user? manual 3-29 3.1 electrical characteristics fig. 3.1.5 switching characteristics measurement circuit diagram (extended operating temperature 125 ? version) / / / measured output pin cmos output 100 pf (6) switching characteristics (extended operating temperature 125 ? version) table 3.1.30 switching characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 t c (s clk2 )/2?0 t c (s clk2 )/2?0 0 min. typ. max. symbol parameter limits unit t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 ?xd 1 ) t v (s clk1 ?xd 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 ? data2 ) t v (s clk2 ? data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output ??pulse width serial i/o1 clock output ??pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ??pulse width serial i/o2 clock output ??pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) note 1: pin x out is excluded. table 3.1.31 switching characteristics (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit 350 50 50 350 50 50 50 50 note 1: pin x out is excluded. t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 ? x d 1 ) t v (s clk1 ? x d 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 ? data2 ) t v (s clk2 ? data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output ??pulse width serial i/o1 clock output ??pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ??pulse width serial i/o2 clock output ??pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 t c (s clk2 )/2?0 t c (s clk2 )/2?0 0 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 140 30 30 140 30 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
appendix 7540 group user s manual 3.1 electrical characteristics 3-30 fig. 3.1.6 timing chart (extended operating temperature 125 ? version) 0.2v cc t d (s clk1 -txd 1 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (rxd 1 -s clk1 )t h (s clk1 -rxd 1 ) t v (s clk1 -txd 1 ) t c (s clk1 ) t wl (s clk1 ) t wh (s clk1 ) r x d 1 (at receive) s clk1 0.2v cc t wl (x in ) 0.8v cc t wh (x in ) t c (x in ) x in 0.2v cc 0.8v cc t w (reset) reset 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) t c (cntr 0 ) t x d 1 (at transmit) cntr 0 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) int 0 , int 1 0.2v cc t wl (cntr 1 ) 0.8v cc t wh (cntr 1 ) t c (cntr 1 ) cntr 1 0.2v cc t d (s clk2 -s data2 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (s data2 -s clk2 )t h (s clk2 -s data2 ) t v (s clk2 -s data2 ) t c (s clk2 ) t wl (s clk2 ) t wh (s clk2 ) s data2 (at receive) s clk2 s data2 (at transmit)
7540 group user? manual 3-31 appendix 3.2 typical characteristics 0 1 2 3 23456 0 2 4 6 23456 3.2 typical characteristics standard characteristics described below are just examples of the 7540 group s characteristics and are not guaranteed. for rated values, refer to 3.1 electrical characteristics . 3.2.1 mask rom version (1) power source current characteristic example (v cc -i cc characteristics) fig. 3.2.1 v cc -i cc characteristics (in double-speed mode: mask rom version) measuring condition: when system is operating in double-speed mode (a-d conversion not executed), ta = 25 c, ceramic oscillation power source current icc [ma] power source voltage vcc [v] f(x in ) = 6 mhz f(x in ) = 4 mhz f(x in ) = 2 mhz f(x in ) = 1 mhz 0 1 2 3 4 5 23456 fig. 3.2.2 v cc -i cc characteristics (in high-speed mode: mask rom version) measuring condition: when system is operating in high-speed mode (a-d conversion not executed), ta = 25 c, ceramic oscillation power source current icc [ma] power source voltage vcc [v] f(x in ) = 8 mhz f(x in ) = 4 mhz f(x in ) = 2 mhz fig. 3.2.3 v cc -i cc characteristics (in middle-speed mode: mask rom version) measuring condition: when system is operating in middle-speed mode (a-d conversion not executed), ta = 25 c, ceramic oscillation power source current icc [ma] power source voltage vcc [v] f(x in ) = 8 mhz f(x in ) = 4 mhz f(x in ) = 2 mhz
3-32 appendix 7540 group user s manual 3.2 typical characteristics 0.0 0.5 1.0 1.5 23456 0 1 2 3 23 45 6 fig. 3.2.4 v cc -i cc characteristics (at wit instruction execution: mask rom version) measuring condition: at wit instruction execution (at wait), ta = 25 c, ceramic oscillation power source current icc [ma] power source voltage vcc [v] f(x in ) = 6 mhz f(x in ) = 4 mhz f(x in ) = 8 mhz fig. 3.2.5 v cc -i cc characteristics (at stp instruction execution: mask rom version) measuring condition: at stp instruction execution (at stop), ta = 25 c, ring oscillator stop power source current icc [na] power source voltage vcc [v]
7540 group user s manual 3-33 appendix 3.2 typical characteristics 0 2 4 6 8 3456 0 2 4 6 8 3456 fig. 3.2.6 v cc -i cc characteristics (addition when operating a-d conversion, f(x in ) = 8 mhz in high- speed mode: mask rom version) measuring condition: a-d conversion executed/not executed (f(x in ) = 8 mhz in high-speed mode), ta = 25 c, ceramic oscillation power source current icc [ma] power source voltage vcc [v] during a-d conversion power source current icc [ma] power source voltage vcc [v] during not a-d conversion fig. 3.2.7 v cc -i cc characteristics (addition when operating a-d conversion, f(x in ) = 6 mhz in double- speed mode: mask rom version) measuring condition: a-d conversion executed/not executed (f(x in ) = 6 mhz in double-speed mode), ta = 25 c, ceramic oscillation during a-d conversion during not a-d conversion
3-34 appendix 7540 group user? manual 3.2 typical characteristics 0 100 200 300 23456 0 200 400 600 23456 fig. 3.2.8 v cc -i cc characteristics (when system is operating by ring oscillator, ceramic oscillation stop: mask rom version) measuring condition: when system is operating by ring oscillator (a-d conversion not executed), ceramic oscillation stop power source current icc [ a] power source voltage vcc [v] ta = 25 c ta = 25 c ta = 45 c fig. 3.2.9 v cc -i cc characteristics (when system is operating by ring oscillator, at wit instruction execution, ceramic oscillation stop: mask rom version) measuring condition: when system is operating by ring oscillator, at wit instruction execution ceramic oscillation stop power source current icc [ a] power source voltage vcc [v] ta = 90 c ta = 130 c ta = 25 c ta = 25 c ta = 45 c ta = 90 c ta = 130 c
7540 group user s manual 3-35 appendix 3.2 typical characteristics 0.0 0.5 1.0 1.5 2.0 2.5 2345678 0 1 2 3 4 234 5678 0 1 2 3 4 5 123456 fig. 3.2.10 f(x in )-i cc characteristics (in double-speed mode: mask rom version) measuring condition: when system is operating in double-speed mode (a-d conversion not executed), ta = 25 c, ceramic oscillation power source current icc [ma] oscillation frequency f(x in ) [mhz] v cc = 5.0 v v cc = 3.0 v fig. 3.2.11 f(x in )-i cc characteristics (in high-speed mode: mask rom version) measuring condition: when system is operating in high-speed mode (a-d conversion not executed), ta = 25 c, ceramic oscillation power source current icc [ma] oscillation frequency f(x in ) [mhz] fig. 3.2.12 f(x in )-i cc characteristics (in middle-speed mode: mask rom version) measuring condition: when system is operating in middle-speed mode (a-d conversion not executed), ta = 25 c, ceramic oscillation power source current icc [ma] oscillation frequency f(x in ) [mhz] v cc = 5.0 v v cc = 3.0 v v cc = 5.0 v v cc = 3.0 v (2) power source current characteristic example (f(x in )-i cc characteristics)
3-36 appendix 7540 group user s manual 3.2 typical characteristics 0 50 100 150 200 -50 -25 0 25 50 75 100 125 150 0 100 200 300 400 -50 -25 0 25 50 75 100 125 150 0.0 0.5 1.0 1.5 2.0 12345678 fig. 3.2.13 f(x in )-i cc characteristics (at wit instruction execution: mask rom version) measuring condition: at wit instruction execution, ta = 25 c, ceramic oscillation power source current icc [ma] oscillation frequency f(x in ) [mhz] fig. 3.2.14 ta-i cc characteristics (when system is operating by ring oscillator, ceramic oscillation stop: mask rom version) measuring condition: when system is operating by ring oscillator (a-d conversion not executed), ceramic oscillation stop power source current icc [ a] operating temperature range [ c] fig. 3.2.15 ta-i cc characteristics (when system is operating by ring oscillator, at wit instruction execution, ceramic oscillation stop: mask rom version) measuring condition: when system is operating by ring oscillator, at wit instruction execution, ceramic oscillation stop power source current icc [ a] operating temperature range ta [ c] (3) power source current characteristic example (ta-i cc characteristics) v cc = 5.0 v v cc = 3.0 v v cc = 5.0 v v cc = 3.0 v v cc = 5.0 v v cc = 3.0 v
7540 group user s manual 3-37 appendix 3.2 typical characteristics 0 1 2 3 4 5 34 56 0 1 2 3 4 5 23456 fig. 3.2.16 v cc -v ihl characteristics (i/o port (cmos): mask rom version) measuring condition: v cc v ihl characteristics of i/o port (cmos), v cc = 5.0 v, ta = 25 c (same characteristics pins: p0 1 p0 7 , p1 1 , p2 0 p2 7 , p3 0 p3 5 ) input voltage v ihl [v] power source voltage vcc [v] fig. 3.2.17 v cc -v ihl characteristics (i/o port (ttl): mask rom version) measuring condition: v cc v ihl characteristics of i/o port (ttl), v cc = 5.0 v, ta = 25 c (same characteristics pins: p1 0 , p1 2 , p1 3 , p3 6 , p3 7 ) input voltage v ihl [v] power source voltage vcc [v] (4) port typical characteristic example (v cc -v ihl characteristics)
3-38 appendix 7540 group user s manual 3.2 typical characteristics 0 1 2 3 4 5 23456 0 1 2 3 4 5 23 456 fig. 3.2.19 v cc -v ihl characteristics (x in pin: mask rom version) power source voltage vcc [v] fig. 3.2.20 v cc -v il characteristics (cnv ss pin: mask rom version) measuring condition: v cc v il characteristics of cnv ss pin, v cc = 5.0 v, ta = 25 c input voltage v il [v] power source voltage vcc [v] measuring condition: v cc v ihl characteristics of x in pin, v cc = 5.0 v, ta = 25 c input voltage v ihl [v] 0 1 2 3 4 5 23456 fig. 3.2.18 v cc -v ihl characteristics (reset pin: mask rom version) measuring condition: v cc v ihl characteristics of reset pin, v cc = 5.0 v, ta = 25 c input voltage v ihl [v] power source voltage vcc [v] h input voltage (v ih ) l input voltage (v il )
7540 group user s manual 3-39 appendix 3.2 typical characteristics 0.0 0.2 0.4 0.6 0.8 1.0 23456 0.0 0.2 0.4 0.6 0.8 1.0 23456 0.0 0.2 0.4 0.6 0.8 1.0 23456 fig. 3.2.21 v cc -hys characteristics (reset pin: mask rom version) measuring condition: v cc hys characteristics of reset pin, v cc = 5.0 v, ta = 25 c hysteresis hys [v] power source voltage vcc [v] fig. 3.2.22 v cc -hys characteristics (sio pin: mask rom version) measuring condition: v cc hys characteristics of sio pin, v cc = 5.0 v, ta = 25 c (same characteristics pins: rxd 1 , s clk1 , s clk2 , s data2 ) hysteresis hys [v] power source voltage vcc [v] fig. 3.2.23 v cc -hys characteristics (int pin: mask rom version) measuring condition: v cc hys characteristics of int pin, v cc = 5.0 v, ta = 25 c (same characteristics pins: cntr 0 , cntr 1 , int 0 , int 1 , p0 0 p0 7 ) hysteresis hys [v] power source voltage vcc [v]
3-40 appendix 7540 group user s manual 3.2 typical characteristics -40 -30 -20 -10 0 012345 -15 -10 -5 0 0123 fig. 3.2.24 v oh -i oh characteristics of p-channel (v cc = 3.0 v, normal port: mask rom version) measuring condition: v oh i oh characteristics of p-channel (normal port), v cc = 3.0 v (same characteristics pins: p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 ) h output current i oh [ma] h output voltage v oh [v] ta = 25 c ta = 125 c ta = 40 c fig. 3.2.25 v oh -i oh characteristics of p-channel (v cc = 5.0 v, normal port: mask rom version) measuring condition: v oh i oh characteristics of p-channel (normal port), v cc = 5.0 v (same characteristics pins: p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 ) h output current i oh [ma] h output voltage v oh [v] ta = 25 c ta = 125 c ta = 40 c (5) port typical characteristic example (v oh -i oh characteristics)
7540 group user s manual 3-41 appendix 3.2 typical characteristics 0 15 30 45 60 012 345 0 5 10 15 20 25 0123 fig. 3.2.26 v ol -i ol characteristics of n-channel (v cc = 3.0 v, normal port: mask rom version) measuring condition: v ol i ol characteristics of n-channel (normal port), v cc = 3.0 v (same characteristics pins: p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 ) l output current i ol [ma] l output voltage v ol [v] ta = 25 c ta = 125 c ta = 40 c fig. 3.2.27 v ol -i ol characteristics of n-channel (v cc = 5.0 v, normal port: mask rom version) measuring condition: v ol i ol characteristics of n-channel (normal port), v cc = 5.0 v (same characteristics pins: p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 ) l output current i ol [ma] l output voltage v ol [v] ta = 25 c ta = 125 c ta = 40 c (6) port typical characteristic example (v ol -i ol characteristics)
3-42 appendix 7540 group user s manual 3.2 typical characteristics 0 20 40 60 80 100 012345 0 10 20 30 40 50 0123 fig. 3.2.28 v ol -i ol characteristics of n-channel (v cc = 3.0 v, led drive port: mask rom version) measuring condition: v ol i ol characteristics of n-channel (led drive port), v cc = 3.0 v (same characteristics pins: p3 0 p3 6 ) l output current i ol [ma] l output voltage v ol [v] ta = 25 c ta = 125 c ta = 40 c fig. 3.2.29 v ol -i ol characteristics of n-channel (v cc = 5.0 v, led drive port: mask rom version) measuring condition: v ol i ol characteristics of n-channel (led drive port), v cc = 5.0 v (same characteristics pins: p3 0 p3 6 ) l output current i ol [ma] l output voltage v ol [v] ta = 25 c ta = 125 c ta = 40 c
7540 group user s manual 3-43 appendix 3.2 typical characteristics -0.4 -0.3 -0.2 -0.1 0 23456 (7) port typical characteristic example (v cc -iil characteristics) fig. 3.2.30 v cc -iil characteristics (port ??input current when connecting pull-up transistor: mask rom version) measuring condition: port l input current when connecting pull-up transistor (same characteristics pins: p0 0 p0 7 , p3 0 p3 7 ) l output current iil [ma] power source voltage v cc [v] ta = 25 c ta = 130 c ta = 45 c ta = 90 c ta = 25 c
3-44 appendix 7540 group user s manual 3.2 typical characteristics -0.3 -0.2 -0.1 0 0.1 0.2 0.3 012345 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 012345 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 012345 fig. 3.2.31 v in -ii(ad) characteristics (a-d port input current during a-d conversion, f(x in ) = 8 mhz in high-speed mode: mask rom version) measuring condition: f(x in ) = 8 mhz in high-speed mode, v cc = 5.0 v, ta = 25 c (same characteristics pins: p2 0 p2 7 ) input current ii(ad) [ a] input voltage v in [v] fig. 3.2.32 v in -ii(ad) characteristics (a-d port input current during a-d conversion, f(x in ) = 6 mhz in double-speed mode: mask rom version) measuring condition: f(x in ) = 6 mhz in double-speed mode, v cc = 5.0 v, ta = 25 c (same characteristics pins: p2 0 p2 7 ) input current ii(ad) [ a] input voltage v in [v] fig. 3.2.33 v in -ii(ad) characteristics (a-d port input current during a-d conversion, f(x in ) = 4 mhz in double-speed mode: mask rom version) measuring condition: f(x in ) = 4 mhz in double-speed mode, v cc = 5.0 v, ta = 25 c (same characteristics pins: p2 0 p2 7 ) input current ii(ad) [ a] (8) port typical characteristic example (v in -ii(ad) characteristics) input voltage v in [v]
7540 group user s manual 3-45 appendix 3.2 typical characteristics 0 1 2 3 -60 -40 -20 0 20 40 60 80 100 120 140 0 1 2 3 4 23 456 fig. 3.2.34 v cc -r osc characteristics (ring oscillator frequency: mask rom version) measuring parameter: ring oscillator frequency ring oscillator frequency r osc [mhz] power source voltage vcc [v] fig. 3.2.35 ta-r osc characteristics (ring oscillator frequency: mask rom version) measuring parameter: ring oscillator frequency ring oscillator frequency r osc [mhz] operating temperature range ta [ c] (9) ring oscillator frequency typical characteristic example ta = 25 c ta = 130 c ta = 45 c ta = 90 c ta = 25 c v cc = 5.0 v v cc = 3.0 v
3-46 appendix 7540 group user s manual 3.2 typical characteristics 0 1 2 3 4 5 0 10 203040 5060 0 1 2 3 4 5 6 0 1020304050 fig. 3.2.36 r-f(x in ) characteristics (rc oscillation frequency: mask rom version) measuring parameter: rc oscillation frequency measuring condition: v cc = 5.0 v, ta = 25 c, c = 33 pf rc oscillation frequency f(x in ) [mhz] external resistor r [k ? ] fig. 3.2.37 c-f(x in ) characteristics (rc oscillation frequency: mask rom version) measuring parameter: rc oscillation frequency measuring condition: v cc = 5.0 v, ta = 25 c, r = 6.8 k ? (fixed) rc oscillation frequency f(x in ) [mhz] external capacitor c [pf] (10) rc oscillation frequency typical characteristic example
7540 group user s manual 3-47 appendix 3.2 typical characteristics 3.0 3.5 4.0 4.5 5.0 -60 -40 -20 0 20 40 60 80 100 120 140 0 1 2 3 4 5 23 456 fig. 3.2.38 v cc -f(x in ) characteristics (rc oscillation frequency: mask rom version) measuring parameter: rc oscillation frequency measuring condition: ta = 25 c, f(x in ) ? 4 mhz (r = 5.1 k ? , c = 20 pf) rc oscillation frequency f(x in ) [mhz] power source voltage v cc [v] fig. 3.2.39 ta-f(x in ) characteristics (rc oscillation frequency: mask rom version) measuring parameter: rc oscillation frequency measuring condition: f(x in ) ? 4 mhz (r = 5.1 k ? , c = 20 pf) rc oscillation frequency f(x in ) [mhz] operating temperature range ta [ c] v cc = 5.0 v v cc = 3.0 v
3-48 appendix 7540 group user s manual 3.2 typical characteristics (11) a-d conversion typical characteristics example ? definition of a-d conversion accuracy the a-d conversion accuracy is defined below (refer to fig. 3.2.40). relative accuracy zero transition voltage (v ot ) this means an analog input voltage when the actual a-d conversion output data changes from 0 to 1. full-scale transition voltage (v fst ) this means an analog input voltage when the actual a-d conversion output data changes from 1023 to 1022. non-linearity error this means a deviation from the line between v ot and v fst of a converted value between v ot and v fst . differential non-linearity error this means a deviation from the input potential difference required to change a converted value between v ot and v fst by 1 lsb of the 1 lsb at the relative accuracy. absolute accuracy this means a deviation from the ideal characteristics between 0 to v ref of actual a-d conversion characteristics. v ref 1024 fig. 3.2.40 definition of a-d conversion accuracy vn: analog input voltage when the output data changes from n to n + 1 (n = 0 to 1022) 1 lsb at relative accuracy (v) 1 lsb at absolute accuracy (v) v fst v ot 1022 analog voltage v ref v 1022 v n v 1 v 0 zero transition voltage (v 0t ) full-scale transition voltage (v fst ) non-linearity error= actual a-d conversion characteristics v n+1 n+1 n 1022 1023 1 0 ideal line of a-d conversion between v 0 to v 1022 output data b a a: 1lsb at relative accuracy b: v n+1 -v n c: difference between the ideal vn and actual vn differential non-linearity error= b-a a [lsb] c c a [lsb]
7540 group user s manual 3-49 appendix 3.2 typical characteristics -15 -10 -5 0 5 10 15 0 32 64 96 128 160 192 224 256 -15 -10 -5 0 5 10 15 256 288 320 352 384 416 448 480 512 -15 -10 -5 0 5 10 15 512 544 576 608 640 672 704 736 768 -15 -10 -5 0 5 10 15 768 800 832 864 896 928 960 992 1024 fig. 3.2.41 a-d conversion accuracy typical characteristic example-1 (mask rom version) v cc = 5.12 [v] v ref = 5.12 [v] x in = 4 [mhz] temp. = 25 [ c] cpu mode = double-speed mode zero transition voltage: 13.75 mv full-scale transition voltage: 5120.94 mv differential non-linearity error: 1.72 mv ( 0.34 lsb) non-linearity error: 5.09 mv ( 1.02 lsb) m37540m4-xxxfp a-d converter step width measurement reference(error(absolute)) error/1lsb width [mv] error (linearity) 1lsb width error/1lsb width [mv] error/1lsb width [mv] error/1lsb width [mv] ? a-d conversion accuracy typical characteristics-1
3-50 appendix 7540 group user s manual 3.2 typical characteristics -15 -10 -5 0 5 10 15 0 32 64 96 128 160 192 224 256 -15 -10 -5 0 5 10 15 256 288 320 352 384 416 448 480 512 -15 -10 -5 0 5 10 15 512 544 576 608 640 672 704 736 768 -15 -10 -5 0 5 10 15 768 800 832 864 896 928 960 992 1024 fig. 3.2.42 a-d conversion accuracy typical characteristic example-2 (mask rom version) v cc = 5.12 [v] v ref = 5.12 [v] x in = 6 [mhz] temp. = 25 [ c] cpu mode = double-speed mode zero transition voltage: 14.38 mv full-scale transition voltage: 5121.88 mv differential non-linearity error: 1.41 mv (0.28 lsb) non-linearity error: 4.23 mv ( 0.85 lsb) m37540m4-xxxfp a-d converter step width measurement reference(error(absolute)) error/1lsb width [mv] error (linearity) 1lsb width error/1lsb width [mv] error/1lsb width [mv] error/1lsb width [mv] ? a-d conversion accuracy typical characteristics-2
7540 group user s manual 3-51 appendix 3.2 typical characteristics -10 -5 0 5 10 15 20 25 30 0 32 64 96 128 160 192 224 256 -10 -5 0 5 10 15 20 25 30 256 288 320 352 384 416 448 480 512 -10 -5 0 5 10 15 20 25 30 512 544 576 608 640 672 704 736 768 -10 -5 0 5 10 15 20 25 30 768 800 832 864 896 928 960 992 1024 fig. 3.2.43 a-d conversion accuracy typical characteristic example-3 (mask rom version) v cc = 5.12 [v] v ref = 5.12 [v] x in = 8 [mhz] temp. = 25 [ c] cpu mode = high-speed mode zero transition voltage: 30.31 mv full-scale transition voltage: 5143.33 mv differential non-linearity error: 1.72 mv (0.34 lsb) non-linearity error: 7.64 mv ( 1.53 lsb) m37540m4-xxxfp a-d converter step width measurement reference(error(absolute)) error/1lsb width [mv] error (linearity) 1lsb width error/1lsb width [mv] error/1lsb width [mv] error/1lsb width [mv] ? a-d conversion accuracy typical characteristics-3
3-52 appendix 7540 group user? manual 3.2 typical characteristics 0 1 2 3 4 23456 0 2 4 6 8 23456 0 2 4 6 8 10 23 45 6 3.2.2 one time prom version (1) power source current characteristic example (v cc -i cc characteristics) fig. 3.2.44 v cc -i cc characteristics (in double-speed mode: one time prom version) measuring condition: when system is operating in double-speed mode (a-d conversion not executed), ta = 25 c, ceramic oscillation power source current icc [ma] power source voltage vcc [v] f(x in ) = 6 mhz f(x in ) = 4 mhz f(x in ) = 2 mhz f(x in ) = 1 mhz fig. 3.2.45 v cc -i cc characteristics (in high-speed mode: one time prom version) measuring condition: when system is operating in high-speed mode (a-d conversion not executed), ta = 25 c, ceramic oscillation power source current icc [ma] power source voltage vcc [v] f(x in ) = 8 mhz f(x in ) = 4 mhz f(x in ) = 2 mhz fig. 3.2.46 v cc -i cc characteristics (in middle-speed mode: one time prom version) measuring condition: when system is operating in middle-speed mode (a-d conversion not executed), ta = 25 c, ceramic oscillation power source current icc [ma] power source voltage vcc [v] f(x in ) = 8 mhz f(x in ) = 4 mhz f(x in ) = 2 mhz
7540 group user s manual 3-53 appendix 3.2 typical characteristics 0 1 2 3 23456 0 1 2 3 23456 fig. 3.2.47 v cc -i cc characteristics (at wit instruction execution: one time prom version) measuring condition: at wit instruction execution (at wait), ta = 25 c, ceramic oscillation power source current icc [ma] power source voltage vcc [v] f(x in ) = 6 mhz f(x in ) = 4 mhz f(x in ) = 8 mhz fig. 3.2.48 v cc -i cc characteristics (at stp instruction execution: one time prom version) measuring condition: at stp instruction execution (at stop), ta = 25 c, ring oscillator stop power source current icc [na] power source voltage vcc [v]
3-54 appendix 7540 group user s manual 3.2 typical characteristics 0 2 4 6 8 10 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0 2 4 6 8 3.5 4.0 4.5 5.0 5.5 6.0 6.5 fig. 3.2.49 v cc -i cc characteristics (addition when operating a-d conversion, f(x in ) = 8 mhz in high- speed mode: one time prom version) measuring condition: a-d conversion executed/not executed (f(x in ) = 8 mhz in high-speed mode), ta = 25 c, ceramic oscillation power source current icc [ma] power source voltage vcc [v] during a-d conversion power source current icc [ma] power source voltage vcc [v] during not a-d conversion fig. 3.2.50 v cc -i cc characteristics (addition when operating a-d conversion, f(x in ) = 6 mhz in double- speed mode: one time prom version) measuring condition: a-d conversion executed/not executed (f(x in ) = 6 mhz in double-speed mode), ta = 25 c, ceramic oscillation during a-d conversion during not a-d conversion
7540 group user? manual 3-55 appendix 3.2 typical characteristics 0 100 200 300 23456 0 200 400 600 800 23456 fig. 3.2.51 v cc -i cc characteristics (when system is operating by ring oscillator, ceramic oscillation stop: one time prom version) measuring condition: when system is operating by ring oscillator (a-d conversion not executed), ceramic oscillation stop power source current icc [ a] power source voltage vcc [v] ta = 25 c ta = 25 c ta = 45 c fig. 3.2.52 v cc -i cc characteristics (when system is operating by ring oscillator, at wit instruction execution, ceramic oscillation stop: one time prom version) measuring condition: when system is operating by ring oscillator, at wit instruction execution ceramic oscillation stop power source current icc [ a] power source voltage vcc [v] ta = 90 c ta = 130 c ta = 25 c ta = 25 c ta = 45 c ta = 90 c ta = 130 c
3-56 appendix 7540 group user s manual 3.2 typical characteristics 0 1 2 3 234 5678 0 2 4 6 23 456 78 0 2 4 6 8 123456 fig. 3.2.53 f(x in )-i cc characteristics (in double-speed mode: one time prom version) measuring condition: when system is operating in double-speed mode (a-d conversion not executed), ta = 25 c, ceramic oscillation power source current icc [ma] oscillation frequency f(x in ) [mhz] v cc = 5.0 v v cc = 3.0 v fig. 3.2.54 f(x in )-i cc characteristics (in high-speed mode: one time prom version) measuring condition: when system is operating in high-speed mode (a-d conversion not executed), ta = 25 c, ceramic oscillation power source current icc [ma] oscillation frequency f(x in ) [mhz] fig. 3.2.55 f(x in )-i cc characteristics (in middle-speed mode: one time prom version) measuring condition: when system is operating in middle-speed mode (a-d conversion not executed), ta = 25 c, ceramic oscillation power source current icc [ma] oscillation frequency f(x in ) [mhz] v cc = 5.0 v v cc = 3.0 v v cc = 5.0 v v cc = 3.0 v (2) power source current characteristic example (f(x in )-i cc characteristics)
7540 group user s manual 3-57 appendix 3.2 typical characteristics 0 50 100 150 200 -50 -25 0 25 50 75 100 125 150 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 150 0.0 0.5 1.0 1.5 2.0 12345678 fig. 3.2.56 f(x in )-i cc characteristics (at wit instruction execution: one time prom version) measuring condition: at wit instruction execution, ta = 25 c, ceramic oscillation power source current icc [ma] oscillation frequency f(x in ) [mhz] fig. 3.2.57 ta-i cc characteristics (when system is operating by ring oscillator, ceramic oscillation stop: one time prom version) measuring condition: when system is operating by ring oscillator (a-d conversion not executed), ceramic oscillation stop power source current icc [ a] operating temperature range [ c] fig. 3.2.58 ta-i cc characteristics (when system is operating by ring oscillator, at wit instruction execution, ceramic oscillation stop: one time prom version) measuring condition: when system is operating by ring oscillator, at wit instruction execution, ceramic oscillation stop power source current icc [ a] operating temperature range ta [ c] (3) power source current characteristic example (ta-i cc characteristics) v cc = 5.0 v v cc = 3.0 v v cc = 5.0 v v cc = 3.0 v v cc = 5.0 v v cc = 3.0 v
3-58 appendix 7540 group user s manual 3.2 typical characteristics 0 1 2 3 4 5 34 56 0 1 2 3 4 5 23456 fig. 3.2.59 v cc -v ihl characteristics (i/o port (cmos): one time prom version) measuring condition: v cc v ihl characteristics of i/o port (cmos), v cc = 5.0 v, ta = 25 c (same characteristics pins: p0 1 p0 7 , p1 1 , p2 0 p2 7 , p3 0 p3 5 ) input voltage v ihl [v] power source voltage vcc [v] fig. 3.2.60 v cc -v ihl characteristics (i/o port (ttl): one time prom version) measuring condition: v cc v ihl characteristics of i/o port (ttl), v cc = 5.0 v, ta = 25 c (same characteristics pins: p1 0 , p1 2 , p1 3 , p3 6 , p3 7 ) input voltage v ihl [v] power source voltage vcc [v] (4) port typical characteristic example (v cc -v ihl characteristics)
7540 group user s manual 3-59 appendix 3.2 typical characteristics 0 1 2 3 4 5 23456 0 1 2 3 4 5 23456 0 1 2 3 4 5 23456 fig. 3.2.62 v cc -v ihl characteristics (x in pin: one time prom version) power source voltage vcc [v] fig. 3.2.63 v cc -v il characteristics (cnv ss pin: one time prom version) measuring condition: v cc v il characteristics of cnv ss pin, v cc = 5.0 v, ta = 25 c input voltage v il [v] power source voltage vcc [v] measuring condition: v cc v ihl characteristics of x in pin, v cc = 5.0 v, ta = 25 c input voltage v ihl [v] fig. 3.2.61 v cc -v ihl characteristics (reset pin: one time prom version) measuring condition: v cc v ihl characteristics of reset pin, v cc = 5.0 v, ta = 25 c input voltage v ihl [v] power source voltage vcc [v] h input voltage (v ih ) l input voltage (v il )
3-60 appendix 7540 group user s manual 3.2 typical characteristics 0.0 0.2 0.4 0.6 0.8 1.0 23456 0.0 0.2 0.4 0.6 0.8 1.0 23456 0.0 0.2 0.4 0.6 0.8 1.0 23456 fig. 3.2.64 v cc -hys characteristics (reset pin: one time prom version) measuring condition: v cc hys characteristics of reset pin, v cc = 5.0 v, ta = 25 c hysteresis hys [v] power source voltage vcc [v] fig. 3.2.65 v cc -hys characteristics (sio pin: one time prom version) measuring condition: v cc hys characteristics of sio pin, v cc = 5.0 v, ta = 25 c (same characteristics pins: rxd 1 , s clk1 , s clk2 , s data2 ) hysteresis hys [v] power source voltage vcc [v] fig. 3.2.66 v cc -hys characteristics (int pin: one time prom version) measuring condition: v cc hys characteristics of int pin, v cc = 5.0 v, ta = 25 c (same characteristics pins: cntr 0 , cntr 1 , int 0 , int 1 , p0 0 p0 7 ) hysteresis hys [v] power source voltage vcc [v]
7540 group user s manual 3-61 appendix 3.2 typical characteristics -50 -40 -30 -20 -10 0 012345 -15 -10 -5 0 0123 fig. 3.2.67 v oh -i oh characteristics of p-channel (v cc = 3.0 v, normal port: one time prom version) measuring condition: v oh i oh characteristics of p-channel (normal port), v cc = 3.0 v (same characteristics pins: p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 ) h output current i oh [ma] h output voltage v oh [v] ta = 25 c ta = 125 c fig. 3.2.68 v oh -i oh characteristics of p-channel (v cc = 5.0 v, normal port: one time prom version) measuring condition: v oh i oh characteristics of p-channel (normal port), v cc = 5.0 v (same characteristics pins: p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 ) h output current i oh [ma] h output voltage v oh [v] ta = 25 c ta = 125 c ta = 40 c (5) port typical characteristic example (v oh -i oh characteristics)
3-62 appendix 7540 group user s manual 3.2 typical characteristics 0 15 30 45 60 012 345 0 5 10 15 20 25 0123 fig. 3.2.69 v ol -i ol characteristics of n-channel (v cc = 3.0 v, normal port: one time prom version) measuring condition: v ol i ol characteristics of n-channel (normal port), v cc = 3.0 v (same characteristics pins: p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 ) l output current i ol [ma] l output voltage v ol [v] ta = 25 c ta = 125 c fig. 3.2.70 v ol -i ol characteristics of n-channel (v cc = 5.0 v, normal port: one time prom version) measuring condition: v ol i ol characteristics of n-channel (normal port), v cc = 5.0 v (same characteristics pins: p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 ) l output current i ol [ma] l output voltage v ol [v] ta = 25 c ta = 125 c ta = 40 c (6) port typical characteristic example (v ol -i ol characteristics)
7540 group user s manual 3-63 appendix 3.2 typical characteristics 0 20 40 60 80 100 012345 0 10 20 30 40 0123 fig. 3.2.71 v ol -i ol characteristics of n-channel (v cc = 3.0 v, led drive port: one time prom version) measuring condition: v ol i ol characteristics of n-channel (led drive port), v cc = 3.0 v (same characteristics pins: p3 0 p3 6 ) l output current i ol [ma] l output voltage v ol [v] ta = 25 c ta = 125 c fig. 3.2.72 v ol -i ol characteristics of n-channel (v cc = 5.0 v, led drive port: one time prom version) measuring condition: v ol i ol characteristics of n-channel (led drive port), v cc = 5.0 v (same characteristics pins: p3 0 p3 6 ) l output current i ol [ma] l output voltage v ol [v] ta = 25 c ta = 125 c ta = 40 c
3-64 appendix 7540 group user s manual 3.2 typical characteristics -0.5 -0.4 -0.3 -0.2 -0.1 0 23456 (7) port typical characteristic example (v cc -iil characteristics) fig. 3.2.73 v cc -iil characteristics (port ??input current when connecting pull-up transistor: one time prom version) measuring condition: port l input current when connecting pull-up transistor (same characteristics pins: p0 0 p0 7 , p3 0 p3 7 ) l output current iil [ma] power source voltage v cc [v] ta = 25 c ta = 130 c ta = 45 c ta = 90 c ta = 25 c
7540 group user s manual 3-65 appendix 3.2 typical characteristics -0.3 -0.2 -0.1 0 0.1 0.2 0.3 012345 fig. 3.2.74 v in -ii(ad) characteristics (a-d port input current during a-d conversion, f(x in ) = 8 mhz in high-speed mode: one time prom version) measuring condition: f(x in ) = 8 mhz in high-speed mode, v cc = 5.0 v, ta = 25 c (same characteristics pins: p2 0 p2 7 ) input current ii(ad) [ a] input voltage v in [v] fig. 3.2.75 v in -ii(ad) characteristics (a-d port input current during a-d conversion, f(x in ) = 6 mhz in double-speed mode: one time prom version) measuring condition: f(x in ) = 6 mhz in double-speed mode, v cc = 5.0 v, ta = 25 c (same characteristics pins: p2 0 p2 7 ) input current ii(ad) [ a] input voltage v in [v] fig. 3.2.76 v in -ii(ad) characteristics (a-d port input current during a-d conversion, f(x in ) = 4 mhz in double-speed mode: one time prom version) measuring condition: f(x in ) = 4 mhz in double-speed mode, v cc = 5.0 v, ta = 25 c (same characteristics pins: p2 0 p2 7 ) input current ii(ad) [ a] (8) port typical characteristic example (v in -ii(ad) characteristics) input voltage v in [v] -0.3 -0.2 -0.1 0 0.1 0.2 0.3 012345 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 012345
3-66 appendix 7540 group user s manual 3.2 typical characteristics 0 1 2 3 4 -60 -40 -20 0 20 40 60 80 100 120 140 0 1 2 3 4 23 456 fig. 3.2.77 v cc -r osc characteristics (ring oscillator frequency: one time prom version) measuring parameter: ring oscillator frequency ring oscillator frequency r osc [mhz] power source voltage vcc [v] fig. 3.2.78 ta-r osc characteristics (ring oscillator frequency: one time prom version) measuring parameter: ring oscillator frequency ring oscillator frequency r osc [mhz] operating temperature range ta [ c] (9) ring oscillator frequency typical characteristic example ta = 25 c ta = 130 c ta = 45 c ta = 90 c ta = 25 c v cc = 5.0 v v cc = 3.0 v
7540 group user s manual 3-67 appendix 3.2 typical characteristics 0 2 4 6 8 0 102030405060 fig. 3.2.79 r-f(x in ) characteristics (rc oscillation frequency: one time prom version) measuring parameter: rc oscillation frequency measuring condition: v cc = 5.0 v, ta = 25 c rc oscillation frequency f(x in ) [mhz] external resistor r [k ? ] fig. 3.2.80 c-f(x in ) characteristics (rc oscillation frequency: one time prom version) measuring parameter: rc oscillation frequency measuring condition: v cc = 5.0 v, ta = 25 c rc oscillation frequency f(x in ) [mhz] external capacitor c [pf] (10) rc oscillation frequency typical characteristic example 0 2 4 6 0 1020304050 c = 33 pf c = 20 pf c = 47 pf r = 5.1 k ? r = 10 k ? r = 15 k ?
3-68 appendix 7540 group user s manual 3.2 typical characteristics 4.0 4.2 4.4 4.6 4.8 5.0 -60 -30 0 30 60 90 120 150 0.0 1.0 2.0 3.0 4.0 5.0 23456 fig. 3.2.81 v cc -f(x in ) characteristics (rc oscillation frequency: one time prom version) measuring parameter: rc oscillation frequency measuring condition: ta = 25 c, r = 5.1 k ? /c = 33 pf rc oscillation frequency f(x in ) [mhz] power source voltage v cc [v] fig. 3.2.82 ta-f(x in ) characteristics (rc oscillation frequency: one time prom version) measuring parameter: rc oscillation frequency measuring condition: r = 5.1 k ? , c = 33 pf rc oscillation frequency f(x in ) [mhz] operating temperature range ta [ c] v cc = 5.0 v v cc = 3.0 v
7540 group user s manual 3-69 appendix 3.2 typical characteristics (11) a-d conversion typical characteristics example ? definition of a-d conversion accuracy the a-d conversion accuracy is defined below (refer to fig. 3.2.83). relative accuracy zero transition voltage (v ot ) this means an analog input voltage when the actual a-d conversion output data changes from 0 to 1. full-scale transition voltage (v fst ) this means an analog input voltage when the actual a-d conversion output data changes from 1023 to 1022. non-linearity error this means a deviation from the line between v ot and v fst of a converted value between v ot and v fst . differential non-linearity error this means a deviation from the input potential difference required to change a converted value between v ot and v fst by 1 lsb of the 1 lsb at the relative accuracy. absolute accuracy this means a deviation from the ideal characteristics between 0 to v ref of actual a-d conversion characteristics. v ref 1024 fig. 3.2.83 definition of a-d conversion accuracy vn: analog input voltage when the output data changes from n to n + 1 (n = 0 to 1022) 1 lsb at relative accuracy (v) 1 lsb at absolute accuracy (v) v fst v ot 1022 analog voltage v ref v 1022 v n v 1 v 0 zero transition voltage (v 0t ) full-scale transition voltage (v fst ) non-linearity error= actual a-d conversion characteristics v n+1 n+1 n 1022 1023 1 0 ideal line of a-d conversion between v 0 to v 1022 output data b a a: 1lsb at relative accuracy b: v n+1 -v n c: difference between the ideal vn and actual vn differential non-linearity error= b-a a [lsb] c c a [lsb]
3-70 appendix 7540 group user s manual 3.2 typical characteristics -10 -5 0 5 10 0 32 64 96 128 160 192 224 256 -10 -5 0 5 10 256 288 320 352 384 416 448 480 512 -10 -5 0 5 10 512 544 576 608 640 672 704 736 768 -10 -5 0 5 10 768 800 832 864 896 928 960 992 1024 fig. 3.2.84 a-d conversion accuracy typical characteristic example-1 (one time prom version) v cc = 5.12 [v] v ref = 5.12 [v] x in = 4 [mhz] temp. = 25 [ c] cpu mode = double-speed mode zero transition voltage: 6.88 mv full-scale transition voltage: 5115.63 mv differential non-linearity error: 2.34 mv ( 0.47 lsb) non-linearity error: 5.66 mv ( 1.13 lsb) m37540e8fp a-d converter step width measurement reference(error(absolute)) error/1lsb width [mv] error (linearity) 1lsb width error/1lsb width [mv] error/1lsb width [mv] error/1lsb width [mv] ? a-d conversion accuracy typical characteristics-1
7540 group user s manual 3-71 appendix 3.2 typical characteristics -10 -5 0 5 10 0 32 64 96 128 160 192 224 256 -10 -5 0 5 10 256 288 320 352 384 416 448 480 512 -10 -5 0 5 10 512 544 576 608 640 672 704 736 768 -10 -5 0 5 10 768 800 832 864 896 928 960 992 1024 fig. 3.2.85 a-d conversion accuracy typical characteristic example-2 (one time prom version) v cc = 5.12 [v] v ref = 5.12 [v] x in = 6 [mhz] temp. = 25 [ c] cpu mode = double-speed mode zero transition voltage: 5.94 mv full-scale transition voltage: 5113.44 mv differential non-linearity error: 3.28 mv (0.66 lsb) non-linearity error: 4.91 mv ( 0.98 lsb) m37540e8fp a-d converter step width measurement reference(error(absolute)) error/1lsb width [mv] error (linearity) 1lsb width error/1lsb width [mv] error/1lsb width [mv] error/1lsb width [mv] ? a-d conversion accuracy typical characteristics-2
3-72 appendix 7540 group user s manual 3.2 typical characteristics -10 -5 0 5 10 0 32 64 96 128 160 192 224 256 -10 -5 0 5 10 256 288 320 352 384 416 448 480 512 -10 -5 0 5 10 512 544 576 608 640 672 704 736 768 -10 -5 0 5 10 768 800 832 864 896 928 960 992 1024 fig. 3.2.86 a-d conversion accuracy typical characteristic example-3 (one time prom version) v cc = 5.12 [v] v ref = 5.12 [v] x in = 8 [mhz] temp. = 25 [ c] cpu mode = high-speed mode zero transition voltage: 5.63 mv full-scale transition voltage: 5115.31 mv differential non-linearity error: 2.66 mv ( 0.53 lsb) non-linearity error: 5.99 mv ( 1.20 lsb) m37540e8fp a-d converter step width measurement reference(error(absolute)) error/1lsb width [mv] error (linearity) 1lsb width error/1lsb width [mv] error/1lsb width [mv] error/1lsb width [mv] ? a-d conversion accuracy typical characteristics-3
7540 group user? manual 3-73 appendix 3.3 notes on use 3.3.1 notes on input and output ports notes on using input and output ports are described below. (1) notes in stand-by state in stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an i/o port ?ndefined? pull-up (connect the port to v cc ) or pull-down (connect the port to v ss ) these ports through a resistor. when determining a resistance value, note the following points: ?external circuit ?variation of output levels during the ordinary operation when using a built-in pull-up resistor, note on varied current values: ?when setting as an input port : fix its input level when setting as an output port : prevent current from flowing out to external. reason the output transistor becomes the off state, which causes the ports to be the high-impedance state. note that the level becomes ?ndefined?depending on external circuits. accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an i/o port are ?ndefined? this may cause power source current. * 1 stand-by state : the stop mode by executing the stp instruction the wait mode by executing the wit instruction (2) modifying output data with bit managing instruction when the port latch of an i/o port is modified with the bit managing instruction* 2 , the value of the unspecified bit may be changed. reason the bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. accordingly, when these instructions are executed on a bit of the port latch of an i/o port, the following is executed to all bits of the port latch. ?as for a bit which is set for an input port : the pin state is read in the cpu, and is written to this bit after bit managing. ?as for a bit which is set for an output port : the bit value of the port latch is read in the cpu, and is written to this bit after bit managing. note the following : ?even when a port which is set as an output port is changed for an input port, its port latch holds the output data. ?as for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. * 2 bit managing instructions : seb , and clb instructions (3) usage for the 32-pin version ? fix the p3 5 , p3 6 pull-up control bit of the pull-up control register to ?? ? keep the p3 6 /int 1 input level selection bit of the port p1p3 control register ??(initial state). 3.3 notes on use
3-74 appendix 7540 group user? manual 3.3.2 termination of unused pins (1) terminate unused pins ? i/o ports : ?set the i/o ports for the input mode and connect them to v cc or v ss through each resistor of 1 k ? to 10 k ? . ports that permit the selecting of a built-in pull-up resistor can also use this resistor. set the i/ o ports for the output mode and open them at ??or ?? ?when opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. thus, the potential at these pins is undefined and the power source current may increase in the input mode. with regard to an effects on the system, thoroughly perform system evaluation on the user side. ?since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) termination remarks ? input ports and i/o ports : do not open in the input mode. reason ?the power source current may increase depending on the first-stage circuit. ?an effect due to noise may be easily produced as compared with proper termination ? and ? shown on the above. ? i/o ports : when setting for the input mode, do not connect to v cc or v ss directly. reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and v cc (or v ss ). ? i/o ports : when setting for the input mode, do not connect multiple ports in a lump to v cc or v ss through a resistor. reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. ?at the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. 3.3 notes on use
7540 group user? manual 3-75 appendix 3.3.3 notes on timer ?when n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). ?when a count source of timer x, timer y or timer z is switched, stop a count of timer x. 3.3.4 notes on timer a notes on using timer a are described below. (1) common to all modes ? when reading timer a (high-order) (tah) and timer a (low-order) (tal), the contents of timer a is read out. read both registers in order of tah and tal following, certainly. tah and tal keep the values until they are read out. also, do not write to them during read. in this case, unexpected operation may occur. ? when writing data to tal and tah even when timer a is operating or stopped, the data are set to timer a and timer a latch simultaneously. write both registers in order of tal and tah following, certainly. also, do not read them during write. in this case, unexpected operation may occur. (2) period measurement mode, event counter mode, and pulse width hl continuously measurement mode ? in order to use cntr 1 pin, set ??to bit 0 of the port p0 direction register (input mode). ? in order to use cntr 1 pin, set ??to bit 7 of the interrupt control register to disable the p0 0 key- on wakeup function. ? cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. when this bit is ?? the cntr 1 interrupt request bit is set to ??at the falling edge of the cntr 1 pin input signal. when this bit is ?? the cntr 1 interrupt request bit is set to ??at the rising edge of the cntr 1 pin input signal. however, in the pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. 3.3.5 notes on timer 1 note on timer 1 is described below. (1) notes on set of the oscillation stabilizing time timer 1 can be used to set the oscillation stabilizing time after release of the stp instruction. the oscillation stabilizing time after release of stp instruction can be selected from ?et automatically? ?ot set automatically?by the oscillation stabilizing time set bit after release of the stp instruction of misrg. when ??is set to this bit, ?1 16 ?is set to timer 1 and ?f 16 ?is set to prescaler 1 automatically. when ??is set to this bit, nothing is set to timer 1 and prescaler 1. therefore, set the wait time according to the oscillation stabilizing time of the oscillation. also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. 3.3 notes on use
3-76 appendix 7540 group user? manual 3.3.6 notes on timer x notes on using each mode of timer x are described below. (1) count source ? f(x in ) can be used only when a ceramic oscillator or a ring oscillator is used. do not use f(x in ) at rc oscillation. (2) pulse output mode ? in order to use cntr 0 pin, set ??to bit 4 of the port p1 direction register (output mode). ? in order to use tx out pin, set ??to bit 3 of the port p0 direction register (output mode). ? cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the falling edge of cntr 0 pin input signal. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the rising edge of cntr 0 pin input signal. (3) pulse width measurement mode ? in order to use cntr 0 pin, set ??to bit 4 of the port p1 direction register (output mode). ? cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the falling edge of cntr 0 pin input signal. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the rising edge of cntr 0 pin input signal. 3.3 notes on use
7540 group user? manual 3-77 appendix 3.3 notes on use 3.3.7 notes on timer y and timer z notes on using each mode of timer y and timer z are described below. (1) timer mode (timer y and timer z) ? in the timer mode, typ and tys is not used. (2) programmable waveform generation mode (timer y and timer z) ? in the programmable waveform generation mode, values of tys, expyp, and expys are valid by writing to typ because the setting to them is executed all at once by writing to typ. even when changing typ is not required, write the same value again. ? in the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to typ and the timing of timer underflow during the secondary interval simultaneously. an example of a measurement is shown below. ex.) the underflow by the primary and the underflow by secondary are stored by polling etc. using timer y interrupt. writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (depending on a primary and a secondary setting values, and primary write timing, it may be impossible.) ? the waveform extension function by the timer y waveform extension control bits can be used only when ?0 16 ?is set to prescaler y. when the value other than ?0 16 ?is set to prescaler y, be sure to set ??to expyp and expys. the waveform extension function by the timer z waveform extension control bits can be used only when ?0 16 ?is set to prescaler z. when the value other than ?0 16 ?is set to prescaler z, be sure to set ??to expzp and expzs. also, when the timer y underflow is selected as the timer z count source, the waveform extension function cannot be used. ? when using this mode, be sure to set ??to the timer y write control bit to select ?rite to latch only? ? when tys is read out, the undefined value is read out. however, while timer y counts the setting value of tys, the count value during the secondary interval can be obtained by reading the timer y primary. ? in order to use ty out pin, set ??to bit 1 of the port p0 direction register (output mode). (3) programmable one-shot generation mode (timer z) ? in the programmable one-shot generation mode, the value of expzp becomes valid by writing to tzp. even when changing tzp is not required, write the same value again. ? in the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer underflow simultaneously.
3-78 appendix 7540 group user? manual 3.3 notes on use ? the waveform extension function by the timer z waveform extension control bits can be used only when ?0 16 ?is set to prescaler z. when the value other than ?0 16 ?is set to prescaler z, be sure to set ??to expzp. also, when the timer y underflow is selected as the timer z count source, the waveform extension function cannot be used. an example of a measurement is shown below. ex.) the underflow of timer is stored by polling etc. using timer z interrupt. writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (depending on a primary setting value, primary write timing, software and timing of external trigger to int 0 pin, it may be impossible.) ? when using this mode, be sure to set ??to the timer z write control bit to select ?rite to latch only? ? in order to use tz out pin, set ??to bit 2 of the port p0 direction register (output mode). ? stop timer z to change the int 0 pin one-shot trigger control bit and int 0 pin one-shot trigger active edge selection bit. (4) programmable wait one-shot generation mode (timer z) ? in the programmable wait one-shot generation mode, values of tzs, expzp and expzs are valid by writing to tzp. even when changing tzp is not required, write the same value again. an example of a measurement is shown below. ex.) the underflow by the primary and the underflow by secondary are stored by polling etc. using timer z interrupt. writing is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (depending on a primary setting value, primary write timing, software and timing of external trigger to int 0 pin, it may be impossible.) ? in the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer underflow during the secondary interval simultaneously. ? the waveform extension function by the timer z waveform extension control bit can be used only when ?0 16 ?is set to prescaler z. when the value other than ?0 16 ?is set to prescaler z, be sure to set ??to expzp and expzs. also, when the timer y underflow is selected as the timer z count source, the waveform extension function cannot be used. ? when using this mode, be sure to set ??to the timer z write control bits to select ?rite to latch only? ? when tzs is read out, the undefined value is read out. however, while timer z counts the setting value of tzs (during one-shot output), the count value during the secondary interval can be obtained by reading tzp. ? in order to use tz out pin, set ??to bit 2 of the port p0 direction register (output mode). ? stop timer z to change the int 0 pin one-shot trigger control bit and int 0 pin one-shot trigger active edge selection bit.
7540 group user? manual 3-79 appendix 3.3 notes on use (5) common to all modes (timer y and timer z) timer y can stop counting by setting ??to the timer y count stop bit in any mode. also, when timer y underflows, the timer y interrupt request bit is set to ?? timer y reloads the value of latch when counting is stopped by the timer y count stop bit. (when timer is read out while timer is stopped, the value of latch is read. the value of timer can be read out only while timer is operating.) 3.3.8 notes on serial i/o1 notes on using serial i/o1 are described below. (1) notes when selecting clock synchronous serial i/o ? when the clock synchronous serial i/o1 is used, serial i/o2 cannot be used. ? when the transmit operation is stopped, clear the serial i/o1 enable bit and the transmit enable bit to ??(serial i/o1 and transmit disabled). reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to ??(serial i/o1 disabled), the internal transmission is running (in this case, since pins txd 1 , rxd 1 , s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to ??at this time, the data during internally shifting is output to the txd 1 pin and an operation failure occurs. ? when the receive operation is stopped, clear the receive enable bit to ??(receive disabled), or clear the serial i/o1 enable bit to ??(serial i/o1 disabled). ? when the transmit/receive operation is stopped, clear both the transmit enable bit and receive enable bit to ??(transmit and receive disabled) simultaneously. (any one of data transmission and reception cannot be stopped.) reason in the clock synchronous serial i/o mode, the same clock is used for transmission and reception. if any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. in this mode, the clock circuit of the transmission circuit also operates for data reception. accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to ??(transmit disabled). also, the transmission circuit cannot be initialized even if the serial i/o1 enable bit is cleared to ??(serial i/o1 disabled) (same as ? ). ? when signals are output from the s rdy1 pin on the reception side by using an external clock, set all of the receive enable bit, the s rdy1 output enable bit, and the transmit enable bit to ?? ? when the s rdy1 signal input is used, set the using pin to the input mode before data is written to the transmit/receive buffer register. ? setup of a serial i/o1 synchronous clock selection bit when a clock synchronous serial i/o is selected; ??: p1 2 pin turns into an output pin of a synchronous clock. ??: p1 2 pin turns into an input pin of a synchronous clock. setup of a s rdy1 output enable bit (s rdy1 ) when a clock synchronous serial i/o1 is selected; ??: p1 3 pin can be used as a normal i/o pin. ??: p1 3 pin turns into a s rdy1 output pin.
3-80 appendix 7540 group user? manual (2) notes when selecting uart ? when the clock asynchronous serial i/o1 (uart) is used, serial i/o2 can be used only when brg output divided by 16 is selected as the synchronous clock. ? when the transmit operation is stopped, clear the transmit enable bit to ??(transmit disabled). reason same as (1) ? . ? when the receive operation is stopped, clear the receive enable bit to ??(receive disabled). ? when the transmit/receive operation is stopped, clear the transmit enable bit to ??(transmit disabled) and receive enable bit to ??(receive disabled). ? setup of a serial i/o1 synchronous clock selection bit when a clock asynchronous (uart) serial i/o is selected; ?? p1 2 pin can be used as a normal i/o pin. ?? p1 2 pin turns into an input pin of an external clock. when clock asynchronous (uart) type serial i/o is selected, it is p1 3 pin. it can be used as a normal i/o pin. (3) notes common to clock synchronous serial i/o and uart ? when data transmission is executed at the state that an external clock input is selected as the synchronous clock, set ??to the transmit enable bit while the s clk1 is ??state. also, write to the transmit buffer register while the s clk1 is ??state. ? when the transmit interrupt is used, set as the following sequence. ? serial i/o1 transmit interrupt enable bit is set to ??(disabled). ? serial i/o1 transmit enable bit is set to ?? ? serial i/o1 transmit interrupt request bit is set to ?? ? serial i/o1 transmit interrupt enable bit is set to ??(enabled). reason when the transmit enable bit is set to ?? the transmit buffer empty flag and transmit shift completion flag are set to ?? accordingly, even if the timing when any of the above flags is set to ??is selected for the transmit interrupt source, interrupt request occurs and the transmit interrupt request bit is set. ? write to the baud rate generator (brg) while the transmit/receive operation is stopped. fig. 3.3.1 sequence of setting serial i/o1 control register again ? set the serial i/o control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to ?. ? the transmit shift completion flag changes from ??to ??with a delay of 0.5 to 1.5 shift clocks. when data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. can be set with the ldm instruction at the same time clear both the transmit enable bit (te) and the receive enable bit (re) to ? set the bits 0 to 3 and bit 6 of the serial i/o1 control register set both the transmit enable bit (te) and the receive enable bit (re), or one of them to ? 3.3 notes on use
7540 group user? manual 3-81 appendix 3.3 notes on use 3.3.9 notes on serial i/o2 notes on using serial i/o2 are described below. (1) note on serial i/o1 serial i/o2 can be used only when serial i/o1 is not used or serial i/o1 is used as uart and the brg output divided by 16 is selected as the synchronous clock. (2) note on s clk2 pin when an external clock is selected, set ??to bit 2 of the port p1 direction register (input mode). (3) note on s data2 pin when p1 3 /s rdy1 /s data2 pin is used as the s data input, set ??to bit 3 of the port p1 direction register (input mode). when the internal clock is selected as the transfer and p1 3 /s data2 pin is set to the input mode, the s data2 pin is in a high-impedance state after the data transfer is completed. (4) notes on serial i/o2 transmit/receive shift completion flag ? the transmit/receive shift completion flag of the serial i/o2 control register is ??after transmit/ receive shift is completed. in order to set ??to this flag, set data (dummy data at receive) to the serial i/o2 register by program. ? bit 7 (transmit/receive shift completion flag) of the serial i/o2 control register is set earlier than the completion of the actual shift operation for a half cycle of shift clock. accordingly, when the shift completion is checked by using this bit, read/write the serial i/o2 register after a half or more cycle of clock from the setting ??to this bit is checked.
3-82 appendix 7540 group user? manual 3.3.10 notes on a-d converter notes on a-d converter are described below. (1) analog input pin figure 3.3.2 shows the internal equivalent circuit of an analog input. in order to execute the a-d conversion correctly, to complete the charge to an internal capacitor within the specified time is required. the maximum output impedance of the analog input source required to complete the charge to a capacitor within the specified time is as follows; about 35 k ? (at f(x in ) = 8 mhz) when the maximum output impedance exceeds the above value, equip an analog input pin with an external capacitor of 0.01 f to 1 f between an analog input pin and v ss . further, be sure to verify the operation of application products on the user side. reason an analog input pin includes the capacitor for analog voltage comparison. accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. this may cause the a-d conversion/comparison precision to be worse. (2) clock frequency during a-d conversion the comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. thus, make sure the following during an a-d conversion. ?f(x in ) is 500 khz or more ?do not execute the stp instruction fig. 3.3.2 connection diagram 3.3 notes on use ani (i=0 to 7: 36-pin version i=0 to 5: 32-pin version) c1 12 pf(typical) notes 1: this is a parasitic diode. 2: only the selected analog input pin is turned on. c2 1.5 pf(typical) chopper amp. a-d control circuit typical voltage generation circuit switch tree, ladder resistor 1.5 k ? (typical) v ss v ss v cc v ss v ref r ( note 1 ) sw1 ( note 2 ) ( note 1 )
7540 group user? manual 3-83 appendix 3.3 notes on use 3.3.11 notes on oscillation stop detection circuit notes on using oscillation stop detection circuit are described below. (1) note on ring oscillator ? the 7540 group starts operation by the ring oscillator. (2) notes on oscillation circuit stop detection circuit ? when the stop mode is used, set the oscillation stop detection function to ?nvalid? ? when f(x in ) oscillation is stopped, set the oscillation stop detection function to ?nvalid? ? the oscillation stop detection circuit is not included in the emulator mcu ?37540rss? (3) notes on stop mode ? when the stop mode is used, set the oscillation stop detection function to ?nvalid? ? when the stop mode is used, set ??( stp instruction enabled) to the stp instruction disable bit of the watchdog timer control register. ? timer 1 can be used to set the oscillation stabilizing time after release of the stp instruction. the oscillation stabilizing time after release of stp instruction can be selected from ?et automatically? ?ot set automatically?by the oscillation stabilizing time set bit after release of the stp instruction of misrg. when ??is set to this bit, ?1 16 ?is set to timer 1 and ?f 16 ?is set to prescaler 1 automatically. when ??is set to this bit, nothing is set to timer 1 and prescaler 1. therefore, set the wait time according to the oscillation stabilizing time of the oscillation. also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. ? the stp instruction cannot be used during cpu is operating by the ring oscillator. ? when the stop mode is used, stop the ring oscillator oscillation. ? do not execute the stp instruction during the a-d conversion. (4) note on wait mode ? when the wait mode is used, stop the clock except the operation clock source. (5) notes on state transition ? when the operation clock source is f(x in ), the cpu clock division ratio can be selected from the following; ?f(x in )/2 (high-speed mode) ?f(x in )/8 (middle-speed mode) ?f(x in ) (double-speed mode) the double-speed mode can be used only at ceramic oscillation. do not use the mode at rc oscillation. ? stabilize the f(x in ) oscillation to change the operation clock source from the ring oscillator to f(x in ).
3-84 appendix 7540 group user? manual 3.3 notes on use ? when the ring oscillation is used as the operation clock, the cpu clock division ratio is the middle- speed mode. ? when the state transition state 2 state 3 state 4 is performed, execute the nop instruction as shown below according to the division ratio of cpu clock. ?cpum 76 10 2 (state 2 state 3) ?nop instruction ?cpum 4 1 2 (state 3 state 4) double-speed mode at ring oscillator: nop ? 3 high-speed mode at ring oscillator: nop ? 1 middle-speed mode at ring oscillator: nop ? 0 (6) switch of ceramic and rc oscillations after releasing reset the operation starts by starting a built-in ring oscillator. then, a ceramic oscillation or an rc oscillation is selected by setting bit 5 of the cpu mode register. (7) double-speed mode when a ceramic oscillation is selected, a double-speed mode can be used. do not use it when an rc oscillation is selected. (8) clock division ratio, x in oscillation control, ring oscillator control the state transition shown in figure 3.3.3 can be performed by setting the clock division ratio selection bits (bits 7 and 6), x in oscillation control bit (bit 4), ring oscillator oscillation control bit (bit 3) of cpu mode register. be careful of notes on use in figure 3.3.3. fig. 3.3.3 state transition s t o p m o d ew a i t m o d e wit instruction o s c i l l a t i o n s t o p d e t e c t i o n c i r c u i t v a l i d cpum 4 1 2 m i s r g 1 1 2 i n t e r r u p t i n t e r r u p t s t p i n s t r u c t i o n wit instruction i n t e r r u p t m i s r g 1 0 2 cpum 3 1 2 cpum 3 0 2 c p u m 7 6 1 0 2 c p u m 7 6 0 0 2 0 1 2 1 1 2 ( n o t e 2 ) cpum 4 0 2 m i s r g 1 1 2 m i s r g 1 0 2 r e s e t r e l e a s e d s t a t e 1 o p e r a t i o n c l o c k s o u r c e : f (x i n ) ( n o t e 1 ) f (x i n ) o s c i l l a t i o n e n a b l e d r i n g o s c i l l a t o r s t o p state 2 operation clock source: f(x in ) (note 1) f(x in ) oscillation enabled ring oscillator enabled s t a t e 3 o p e r a t i o n c l o c k s o u r c e : r i n g o s c i l l a t o r ( n o t e 3 ) f ( x i n ) o s c i l l a t i o n e n a b l e d r i n g o s c i l l a t o r e n a l b e d s t a t e 4 o p e r a t i o n c l o c k s o u r c e : r i n g o s c i l l a t o r ( n o t e 3 ) f (x i n ) o s c i l l a t i o n s t o p r i n g o s c i l l a t o r e n a l b e d notes on switch of clock (1) in operation clock source = f(x in ), the following can be selected for the cpu clock division ratio. f(x in )/2 (high-speed mode) f(x in )/8 (middle-speed mode) f(x in ) (double-speed mode, only at a ceramic oscillation) (2) execute the state transition state 3 to state 2 or state 3?to state 2?after stabilizing x in oscillation. (3) in operation clock source = ring oscillator, the middle- speed mode is selected for the cpu clock division ratio. (4) when the state transition state 2 state 3 state 4 is performed, execute the nop instruction as shown below according to the division ratio of cpu clock. cpum76 10 2 (state 2 state 3) nop instruction cpum4 1 2 (state 3 state 4) double-speed mode at ring oscillator: nop ? 3 high-speed mode at ring oscillator: nop ? 1 middle-speed mode at ring oscillator: nop ? 0 reset state c p u m 7 6 1 0 2 cpum 76 00 2 01 2 11 2 (note 2) s t a t e 2 o p e r a t i o n c l o c k s o u r c e : f (x i n ) ( n o t e 1 ) f (x i n ) o s c i l l a t i o n e n a b l e d r i n g o s c i l l a t o r e n a b l e d s t a t e 3 o p e r a t i o n c l o c k s o u r c e : r i n g o s c i l l a t o r ( n o t e 3 ) f ( x i n ) o s c i l l a t i o n e n a b l e d r i n g o s c i l l a t o r e n a l b e d
7540 group user? manual 3-85 appendix 3.3.12 notes on cpu mode register (1) switching method of cpu mode register after releasing reset switch the cpu mode register (cpum) at the head of program after releasing reset in the following method. fig. 3.3.4 switching method of cpu mode register (2) cpu mode register bits 5, 1 and 0 of cpu mode register are used to select oscillation mode and to control operation modes of the microcomputer. in order to prevent the dead-lock by error-writing (ex. program run- away), these bits can be rewritten only once after releasing reset. after rewriting it is disable to write any data to the bit. (the emulator mcu ?37540rss?is excluded.) also, when the read-modify-write instructions (seb, clb) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. after releasing reset switch the oscillation mode selection bit (bit 5 of cpum) switch the clock division ratio selection bits (bits 6 and 7 of cpum) main routine start with a built-in ring oscillator ( note ) an initial value is set as a ceramic oscillation mode. when it is switched to an rc oscillation, its oscillation starts. select 1/1, 1/2, 1/8 or ring oscillator. wait by ring oscillator operation until establishment of oscillator clock when using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. when using an rc oscillation, wait time is not required basically (time to execute the instruction to switch from a ring oscillator meets the requirement). note . after releasing reset the operation starts by starting a ring oscillator automatically. do not use a ring oscillator at ordinary operation. 3.3 notes on use
3-86 appendix 7540 group user? manual 3.3.13 notes on interrupts (1) switching external interrupt detection edge for the products able to switch the external interrupt detection edge, switch it as the following sequence. clear an interrupt enable bit to ??(interrupt disabled) switch the detection edge nop (one or more instructions) clear an interrupt request bit to ? (no interrupt request issued) set the interrupt enable bit to ??(interrupt enabled) 3.3 notes on use (2) check of interrupt request bit when executing the bbc or bbs instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to ??by using a data transfer instruction, execute one or more instructions before executing the bbc or bbs instruction. reason if the bbc or bbs instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to ?? the value of the interrupt request bit before being cleared to ? is read. clear the interrupt request bit to ??(no interrupt issued) nop (one or more instructions) execute the bbc or bbs instruction data transfer instruction: ldm, lda, sta, stx, and sty instructions fig. 3.3.6 sequence of check of interrupt request bit fig. 3.3.5 sequence of switch the detection edge reason the interrupt circuit recognizes the switching of the detection edge as the change of external input signals. this may cause an unnecessary interrupt.
7540 group user? manual 3-87 appendix (3) structure of interrupt control register 2 fix the bit 7 of the interrupt control register 1 to ?? figure 3.3.7 shows the structure of the interrupt control register 2. fig. 3.3.7 structure of interrupt control register 2 0 b7 b0 interrupt control register 2 (address: 003f 16 ) interrupt enable bit not used (fix this bit to ?? (4) interrupt when setting the followings, the interrupt request bit may be set to ?? ?hen switching external interrupt active edge related register: interrupt edge selection register (address 003a 16 ) timer x mode register (address 002b 16 ) timer a mode register (address 001d 16 ) when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ??(disabled). ? set the interrupt edge select bit (active edge switch bit). ? set the corresponding interrupt request bit to ??after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ??(enabled). 3.3.14 notes on reset pin (1) connecting capacitor in case where the reset signal rise time is long, connect a ceramic capacitor or others across the reset pin and the v ss pin. and use a 1000 pf or more capacitor for high frequency use. when connecting the capacitor, note the following : ?make the length of the wiring which is connected to a capacitor as short as possible. ?be sure to verify the operation of application products on the user side. reason if the several nanosecond or several ten nanosecond impulse noise enters the reset pin, it may cause a microcomputer failure. 3.3 notes on use
3-88 appendix 7540 group user? manual 3.3.15 notes on programming (1) processor status register ? flags which affect program execution must be initialized after a reset. in particular, it is essential to initialize the t and d flags because they have an important effect on calculations. after a reset, the contents of the processor status register (ps) are undefined except for the i flag which is ?? 3.3 notes on use reset initializing of flags main program fig. 3.3.10 stack memory contents after php instruction execution plp instruction execution ? to reference the contents of the processor status register (ps), execute the php instruction once then read the contents of (s+1). if necessary, execute the plp instruction to return the ps to its original status. a nop instruction should be executed after every plp instruction. fig. 3.3.8 initialization of processor status register fig. 3.3.9 sequence of plp instruction execution (s) (s)+1 stored ps
7540 group user? manual 3-89 appendix (2) decimal calculations ? the adc and sbc are the only instructions which will yield proper decimal notation, set the decimal mode flag (d) to ??with the sed instruction. after executing the adc or sbc instruction, execute another instruction before executing the sec , clc , or cld instruction. ? when decimal mode is selected, the values of three of the flags in the status register (the n, v, and z flags) are invalid after a adc or sbc instruction is executed. the carry flag (c) is set to ??if a carry is generated as a result of the calculation, or is cleared to ??if a borrow is generated. to determine whether a calculation has generated a carry, the c flag must be initialized to ??before each calculation. to check for a borrow, the c flag must be initialized to ??before each calculation. (3) jmp instruction when using the jmp instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. (4) interrupts the contents of the interrupt request bit do not change even if the bbc or bbs instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. for executing the instruction for the changed contents, execute one instruction before executing the bbc or bbs instruction. (5) ports ?the values of the port direction registers cannot be read. that is, it is impossible to use the lda instruction, memory operation instruction when the t flag is ?? addressing mode using direction register values as qualifiers, and bit test instructions such as bbc and bbs. it is also impossible to use bit operation instructions such as clb and seb and read/modify/write instructions of direction registers for calculations such as ror. for setting direction registers, use the ldm instruction, sta instruction, etc. (6) a-d conversion do not execute the stp instruction during a-d conversion. set d flag to ? or sbc instruction instruction , clc , or cld instruction fig. 3.3.11 status flag at decimal calculations 3.3 notes on use
3-90 appendix 7540 group user? manual (7) instruction execution timing the instruction execution time can be obtained by multiplying the frequency of the internal clock f by the number of cycles mentioned in the machine-language instruction table. the frequency of the internal clock f is the same as that of the x in in double-speed mode, twice the x in cycle in high-speed mode and 8 times the x in cycle in middle-speed mode. (8) cpu mode register the oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. however, after rewriting it is disable to write any value to the bit. (emulator mcu is excluded.) when a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. do not use it when an rc oscillation is selected. fig. 3.3.12 programming and testing of one time prom version (1) one time prom version the cnvss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, connect a track between cnvss pin and vss pin with 1 to 10 k ? resistance. the mask rom version track of cnvss pin has no operational interference even if it is connected via a resistor. 3.3.17 handling of power source pin in order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (vcc pin) and gnd pin (vss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 f to 0.1 f is recommended. 3.3.16 programming and test of built-in prom version as for in the one time prom version (shipped in blank), its built-in prom can be read or programmed with a general-purpose prom programmer using a special programming adapter. the programming test and screening for prom of the one time prom version (shipped in blank) are not performed in the assembly process and the following processes. to ensure reliability after programming, performing programming and test according to the figure 3.3.12 before actual use are recommended. programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. caution: 3.3 notes on use
7540 group user? manual 3-91 appendix 3.3.18 notes on built-in prom version (1) programming adapter use a special programming adapter shown in table 3.3.1 and a general-purpose prom programmer when reading from or programming to the built-in prom in the built-in prom version. table 3.3.1 programming adapters m37540e8gp (one time prom version shipped in blank) m37540e8sp (one time prom version shipped in blank) m37540e8fp (one time prom version shipped in blank) pca7435gpg03 pca7435spg02 pca7435fpg02 programming adapter part number 3.3 notes on use (2) programming/reading in prom mode, operation is the same as that of the m5m27c101ak, but programming conditions of prom programmer are not set automatically because there are no internal device id codes. accurately set the following conditions for data programming /reading. take care not to apply 21 v to v pp pin (is also used as the cnv ss pin), or the product may be permanently damaged. ?programming voltage: 12.5 v ?setting of prom programmer switch: refer to table 3.3.2. part number prom programmer start address prom programmer end address m37540e8gp m37540e8sp m37540e8fp table 3.3.2 prom programmer address setting note: addersses 8080 16 to fffd 16 in the built-in prom corresponds to addresses 08080 16 to 0fffd 16 in the prom programmer. address 08080 16 ( note ) address 0fffd 16 ( note )
3-92 appendix 7540 group user? manual fig. 3.4.2 wiring for the reset pin 3.4 countermeasures against noise 3.4 countermeasures against noise 3.4.1 shortest wiring length (1) package select the smallest possible package to make the total wiring length short. the wiring length depends on a microcomputer package. use of a small package, for example qfp and not dip, makes the total wiring length short to reduce influence of noise. fig. 3.4.1 selection of packages (2) wiring for reset pin make the length of wiring which is connected to the reset pin as short as possible. especially, connect a capacitor across the reset pin and the v ss pin with the shortest possible wiring (within 20mm). the width of a pulse input into the reset pin is determined by the timing necessary conditions. if noise having a shorter pulse width than the standard is input to the reset pin, the reset is released before the internal state of the microcomputer is completely initialized. this may cause a program runaway. dip sdip sop qfp reset reset circuit noise v ss v ss reset circuit v ss reset v ss n.g. o.k.
7540 group user? manual 3-93 appendix (3) wiring for clock input/output pins ?make the length of wiring which is connected to clock i/o pins as short as possible. ?make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillator and the v ss pin of a microcomputer as short as possible. ?separate the v ss pattern only for oscillation from other v ss patterns. if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a program failure or program runaway. also, if a potential difference is caused by the noise between the v ss level of a microcomputer and the v ss level of an oscillator, the correct clock will not be input in the microcomputer. fig. 3.4.3 wiring for clock i/o pins (4) wiring to cnv ss pin connect the cnv ss pin to the v ss pin with the shortest possible wiring. the processor mode of a microcomputer is influenced by a potential at the cnv ss pin. if a potential difference is caused by the noise between pins cnv ss and v ss , the processor mode may become unstable. this may cause a microcomputer malfunction or a program runaway. fig. 3.4.4 wiring for cnv ss pin 3.4 countermeasures against noise noise x in x out v ss x in x out v ss n.g. o.k. noise cnv ss v ss cnv ss v ss n.g. o.k.
3-94 appendix 7540 group user? manual (5) wiring to v pp pin of one time prom version connect an approximately 5 k ? resistor to the v pp pin the shortest possible in series and also to the v ss pin. when not connecting the resistor, make the length of wiring between the v pp pin and the v ss pin the shortest possible. note: even when a circuit which included an approximately 5 k ? resistor is used in the mask rom version, the microcomputer operates correctly. the v pp pin of the one time prom is the power source input pin for the built-in prom. when programming in the built-in prom, the impedance of the v pp pin is low to allow the electric current for writing flow into the prom. because of this, noise can enter easily. if noise enters the v pp pin, abnormal instruction codes or data are read from the built-in prom, which may cause a program runaway. fig. 3.4.5 wiring for the v pp pin of the one time prom 3.4.2 connection of bypass capacitor across v ss line and v cc line connect an approximately 0.1 f bypass capacitor across the v ss line and the v cc line as follows: ?connect a bypass capacitor across the v ss pin and the v cc pin at equal length. ?connect a bypass capacitor across the v ss pin and the v cc pin with the shortest possible wiring. ?use lines with a larger diameter than other signal lines for v ss line and v cc line. ?connect the power source wiring via a bypass capacitor to the v ss pin and the v cc pin. fig. 3.4.6 bypass capacitor across the v ss line and the v cc line 3.4 countermeasures against noise cnv ss /v pp v ss in the shortest distance approximately 5k ? v ss v cc aa aa aa aa aa aa v ss v cc aa aa aa aa aa aa aa aa aa aa n.g. o.k.
7540 group user? manual 3-95 appendix 3.4.3 wiring to analog input pins ?connect an approximately 100 ? to 1 k ? resistor to an analog signal line which is connected to an analog input pin in series. besides, connect the resistor to the microcomputer as close as possible. ?connect an approximately 1000 pf capacitor across the v ss pin and the analog input pin. besides, connect the capacitor to the v ss pin as close as possible. also, connect the capacitor across the analog input pin and the v ss pin at equal length. signals which is input in an analog input pin (such as an a-d converter/comparator input pin) are usually output signals from sensor. the sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. this long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. fig. 3.4.7 analog signal line and a resistor and a capacitor 3.4.4 oscillator concerns take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) keeping oscillator away from large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. in the system using a microcomputer, there are signal lines for controlling motors, leds, and thermal heads or others. when a large current flows through those signal lines, strong noise occurs because of mutual inductance. fig. 3.4.8 wiring for a large current signal line 3.4 countermeasures against noise analog input pin v ss noise thermistor microcomputer n.g. o.k. (note) note : the resistor is used for dividing resistance with a thermistor. x in x out v ss m microcomputer mutual inductance large current gnd
3-96 appendix 7540 group user? manual (2) installing oscillator away from signal lines where potential levels change frequently install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. reason signal lines where potential levels change frequently (such as the cntr pin signal line) may affect other lines at signal rising edge or falling edge. if such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. 3) oscillator protection using v ss pattern as for a two-sided printed circuit board, print a v ss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. connect the v ss pattern to the microcomputer v ss pin with the shortest possible wiring. besides, separate this v ss pattern from other v ss patterns. 3.4 countermeasures against noise x in x out v ss cntr do not cross n.g. aaa aaa aaa aaa a a a aaa a a a a a aa aa x in x out v ss an example of v ss patterns on the underside of a printed circuit board oscillator wiring pattern example separate the v ss line for oscillation from other v ss lines 3.4.5 setup for i/o ports setup i/o ports using hardware and software as follows: connect a resistor of 100 ? or more to an i/o port in series. as for an input port, read data several times by a program for checking whether input levels are equal or not. as for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. rewrite data to direction registers and pull- up control registers at fixed periods. note: when a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. if this is undesirable, connect a capacitor to this port to remove the noise pulse. fig. 3.4.10 v ss pattern on the underside of an oscillator fig. 3.4.9 wiring of signal lines where potential levels change frequently fig. 3.4.11 setup for i/o ports direction register port latch data bus i/o port pins noise noise n.g. o.k.
7540 group user s manual 3-97 appendix 3.4.6 providing of watchdog timer function by software if a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. this is equal to or more effective than program runaway detection by a hardware watchdog timer. the following shows an example of a watchdog timer provided by software. in the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. this example assumes that interrupt processing is repeated multiple times in a single main routine processing. assigns a single byte of ram to a software watchdog timer (swdt) and writes the initial value n in the swdt once at each execution of the main routine. the initial value n should satisfy the following condition: n+1 ( counts of interrupt processing executed in each main routine) as the main routine execution cycle may change because of an interrupt processing or others, the initial value n should have a margin. watches the operation of the interrupt processing routine by comparing the swdt contents with counts of interrupt processing after the initial value n has been set. detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: if the swdt contents do not change after interrupt processing. decrements the swdt contents by 1 at each interrupt processing. determines that the main routine operates normally when the swdt contents are reset to the initial value n at almost fixed cycles (at the fixed interrupt processing count). detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: if the swdt contents are not initialized to the initial value n but continued to decrement and if they reach 0 or less. fig. 3.4.12 watchdog timer by software 3.4 countermeasures against noise main routine (swdt) n cli main processing (swdt) interrupt processing routine errors n interrupt processing routine (swdt) (swdt) 1 interrupt processing (swdt) main routine errors > 0 0 rti return =n? 0? n
7540 group user? manual 3-98 appendix 3.5 list of registers 3.5 list of registers fig. 3.5.1 structure of port pi (i = 0, 2, 3) fig. 3.5.2 structure of port p1 port pi b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi 0 port pi 1 port pi 2 port pi 3 port pi 4 port pi 5 port pi 6 port pi 7 in output mode write read port latch in input mode write : port latch read : value of pins port pi (pi) (i = 0, 2, 3) [address : 00 16 , 04 16 , 06 16 ] ? ? ? ? ? ? ? ? note: the 32-pin package versions have nothing to be allocated for the following: bits 6 and 7 of port p2 bits 5 and 6 of port p3. port p1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p1 0 port p1 1 port p1 2 port p1 3 port p1 4 in output mode write read port latch in input mode write : port latch read : value of pins port p1 (p1) [address : 02 16 ] ? ? ? ? ? ? ? ? ?? ?? ?? nothing is allocated for these bits. when these bits are read out, the values are undefined.
7540 group user s manual 3-99 appendix 3.5 list of registers fig. 3.5.3 structure of port pi direction register (i = 0, 2, 3) port pi direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi direction register 0 0 0 0 0 0 0 0 port pi direction register (pid) (i = 0, 2, 3) [address : 01 16 , 05 16 , 07 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode ? ? ? ? ? ? ? ? note: the 32-pin package versions have nothing to be allocated for the following: bits 6 and 7 of p2d bits 5 and 6 of p3d. fig. 3.5.4 structure of port p1 direction register port p1 direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port p1 direction register 0 0 0 0 0 ? ? ? port p1 direction register (p1d) [address : 03 16 ] 0 : port p1 0 input mode 1 : port p1 0 output mode 0 : port p1 1 input mode 1 : port p1 1 output mode 0 : port p1 2 input mode 1 : port p1 2 output mode 0 : port p1 3 input mode 1 : port p1 3 output mode 0 : port p1 4 input mode 1 : port p1 4 output mode ? ? ? ? ? ? ? ? nothing is allocated for these bits. when these bits are read out, the values are undefined. ? ? ?
7540 group user s manual 3-100 appendix 3.5 list of registers fig. 3.5.5 structure of pull-up control register fig. 3.5.6 structure of port p1p3 control register pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name p0 0 pull-up control bit 0 0 0 0 0 0 0 0 pull-up control register (pull) [address : 16 16 ] 0 : pull-up off 1 : pull-up on notes 1: pins set to output are disconnected from the pull-up control. 2: keep setting the p3 5 , p3 6 pull-up control bit to 1 (initial value: 0) for the 32-pin package versions. p0 1 pull-up control bit 0 : pull-up off 1 : pull-up on p0 2 , p0 3 pull-up control bit 0 : pull-up off 1 : pull-up on p0 4 p0 7 pull-up control bit 0 : pull-up off 1 : pull-up on p3 0 p3 3 pull-up control bit 0 : pull-up off 1 : pull-up on p3 4 pull-up control bit 0 : pull-up off 1 : pull-up on p3 5 , p3 6 pull-up control bit 0 : pull-up off 1 : pull-up on p3 7 pull-up control bit 0 : pull-up off 1 : pull-up on port p1p3 control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name p3 7 /int 0 input level selection bit 0 0 0 0 0 0 0 0 port p1p3 control register (p1p3c) [address : 17 16 ] 0 : cmos level 1 : ttl level p3 6 /int 1 input level selection bit ( note ) 0 : cmos level 1 : ttl level p1 0 , p1 2 ,p1 3 input level selection bit 0 : cmos level 1 : ttl level nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? ? ? ? ? note: keep setting the p3 6 /int 1 input level selection bit to 0 (initial value) for the 32-pin package version.
7540 group user s manual 3-101 appendix 3.5 list of registers fig. 3.5.7 structure of transmit/receive buffer register fig. 3.5.8 structure of serial i/o1 status register transmit/receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? transmit/receive buffer register (tb/rb) [address : 18 16 ] the transmission data is written to or the receive data is read out from this buffer register. at writing: a data is written to the transmit buffer register. at reading: the contents of the receive buffer register are read out. note: the contents of transmit buffer register cannot be read out. the data cannot be written to the receive buffer register. serial i/o1 status register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 1 serial i/o1 status register (sio1sts) [address : 19 16 ] nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 1 . ? ? ? ? ? ? ? ? transmit buffer empty flag (tbe) 0 : (oe) (pe) (fe) = 0 1 : (oe) (pe) (fe) = 1 overrun error flag (oe) 0 : buffer full 1 : buffer empty receive buffer full flag (rbf) transmit shift register shift completion flag (tsc) parity error flag (pe) framing error flag (fe) summing error flag (se) 0 : buffer empty 1 : buffer full 0 : transmit shift in progress 1 : transmit shift completed 0 : no error 1 : overrun error 0 : no error 1 : parity error 0 : no error 1 : framing error
7540 group user s manual 3-102 appendix 3.5 list of registers fig. 3.5.9 structure of serial i/o1 control register serial i/o1 control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 serial i/o1 control register (sio1con) [address : 1a 16 ] 0 : f(x in ) 1 : f(x in )/4 brg count source selection bit (css) 0 0 : transmit disabled 1 : transmit enabled 0 : receive disabled 1 : receive enabled transmit interrupt source selection bit (tic) transmit enable bit (te) receive enable bit (re) serial i/o1 enable bit (sioe) 0 : interrupt when transmit buffer has emptied 1 : interrupt when transmit shift operation is completed 0: serial i/o1 disabled 1: serial i/o1 enabled serial i/o1 synchronous clock selection bit (scs) when clock synchronous serial i/o is selected; 0: brg output divided by 4 1: external clock input when uart is selected; 0: brg output divided by 16 1: external clock input divided by 16 0 s rdy1 output enable bit (srdy) 0: p1 3 pin 1: s rdy1 output pin serial i/o1 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o fig. 3.5.10 structure of uart control register b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 1 u a r t c o n t r o l r e g i s t e r ( u a r t c o n ) [ a d d r e s s : 1 b 1 6 ] n o t h i n g i s a l l o c a t e d f o r t h e s e b i t s . t h e s e a r e w r i t e d i s a b l e d b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 1 . ? ? ? u a r t c o n t r o l r e g i s t e r c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) p a r i t y e n a b l e b i t ( p a r e ) s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) p a r i t y s e l e c t i o n b i t ( p a r s ) i n o u t p u t m o d e 0 : c m o s o u t p u t 1 : n - c h a n n e l o p e n - d r a i n o u t p u t 0 : 8 bits 1 : 7 bits 0 : parity checking disabled 1 : parity checking enabled 0 : 1 stop bit 1 : 2 stop bits 0 : even parity 1 : odd parity p 1 1 / t x d p - c h a n n e l o u t p u t d i s a b l e b i t ( p o f f ) 1 1 0
7540 group user s manual 3-103 appendix 3.5 list of registers fig. 3.5.11 structure of baud rate generator baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? baud rate generator (brg) [address : 1c 16 ] set a count value of baud rate generator.
7540 group user s manual 3-104 appendix 3.5 list of registers fig. 3.5.12 structure of timer a mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw name timer a mode register (tam) [address : 1d 16 ] timer a mode register 4 6 7 0 0 0 0 0 : timer mode 0 1 : period measurement mode 1 0 : event counter mode 1 1 : pulse width hl continuously measurement mode b5 b4 5 0 timer a operating mode bits cntr 1 active edge switch bit the function depends on the operating mode. (refer to table 3.5.1) timer a count stop bit 0 : count start 1 : count stop 0 1 2 3 0 0 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? ? ? 0 0 ? timer a operating modes timer mode period measurement mode event counter mode pulse width hl continuously measurement mode cntr 1 active edge switch bit 0 cntr 1 interrupt request occurrence: falling edge ; no influence to timer a count 1 cntr 1 interrupt request occurrence: rising edge ; no influence to timer a count 0 pulse output start: falling edge period measurement cntr 1 interrupt request occurrence: falling edge 1 pulse output start: rising edge period measurement cntr 1 interrupt request occurrence: rising edge 0 timer a: rising edge count cntr 1 interrupt request occurrence: falling edge 1 timer a: falling edge count cntr 1 interrupt request occurrence: rising edge 0 cntr 1 interrupt request occurrence: falling edge and rising edge ; no influence to timer a count 1 cntr 1 interrupt request occurrence: rising edge and falling edge ; no influence to timer a count table 3.5.1 cntr 1 active edge switch bit function
7540 group user s manual 3-105 appendix 3.5 list of registers fig. 3.5.13 structure of timer a register fig. 3.5.14 structure of timer y, z mode register timer a register (low-order, high-order) b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 timer a register (low-order, high-order) (tal, tah) [address : 1e 16 , 1f 16 ] set a count value of timer a. the value set in this register is written to both timer a and timer a latch at the same time. when this register is read out, the timer a s count value is read out. notes 1: be sure to write to/read out both the low-order of timer a (tal) and the high- order of timer a (tah). 2: read the high-order of timer a (tah) first, and the high-order of timer a (tal) next. 3: write to the low-order of timer a (tal) first, and the high-order of timer a (tah) next. 4: do not write to them during read, and do not read out them during write. timer y, z mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 0 . timer y, z mode register (tyzm) [address : 20 16 ) timer y operating mode bit 0 : timer mode 1 : programmable waveform generation mode timer y write control bit ( note ) 0 : write to latch and timer simultaneously 1 : write to only latch timer y count stop bit 0 : count start 1 : count stop timer z operating mode bits b5 b4 0 0 : timer mode 0 1 : programmable waveform generation mode 1 0 : programmable one-shot generation mode 1 1 : programmable wait one-shot generation mode timer z write control bit ( note ) 0 : write to latch and timer simultaneously 1 : write to only latch timer z count stop bit 0 : count start 1 : count stop ? note : when modes other than the timer mode, set these bits to 1 .
7540 group user s manual 3-106 appendix 3.5 list of registers fig. 3.5.15 structure of prescaler y, prescaler z fig. 3.5.16 structure of timer y secondary, timer z secondary prescaler y, prescaler z b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 prescaler y (prey) [address : 21 16 ] prescaler z (prez) [address : 25 16 ] set a count value of each prescaler. the value set in this register is written to both each prescaler and the corresponding prescaler latch at the same time. when this register is read out, the count value of the corres- ponding prescaler is read out. timer y secondary, timer z secondary b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 timer y secondary, timer z secondary (tys, tzs) [address : 22 16 , 26 16 ] set a count value of the corresponding timer. the value set in this register is written to the corresponding secondary latch at the same time. these are read disabled bits. when these bits are read out, the values are undefined. ? ? ? ? ? ? ? ?
7540 group user s manual 3-107 appendix 3.5 list of registers fig. 3.5.18 structure of timer y, z waveform output control register fig. 3.5.17 structure of timer y primary, timer z primary b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 timer y primary, timer z primary timer y primary, timer z primary (typ, tzp) [address : 23 16 , 27 16 ] set a count value of the corresponding timer. when the corresponding timer is stopped, the value set in this register is written to both the corresponding primary latch and the corresponding timer at the same time. when the corresponding timer is operating, the value set in this register is written as follows; timer write control bit = 0: the value is written to both the corresponding primary latch and the corresponding timer at the same time. timer write control bit = 1: the value is written to the corresponding primary latch. when these bits are read out, the count value of the corres- ponding timer is read out (note). note: the primary count value is read out at the primary interval, the secondary count value is read out at the secondary interval. timer y, z waveform output control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 timer y primary waveform extension control bit timer y secondary waveform extension control bit timer z output level latch timer z primary waveform extension control bit timer z secondary waveform extension control bit timer y output level latch 0 : falling edge trigger 1 : rising edge trigger timer y, z waveform output control register (pum) [address : 24 16 ] int 0 pin one-shot trigger control bit ( note ) int 0 pin one-shot trigger active edge selection bit ( note ) 0 : waveform not extended 1 : waveform extended 0 : waveform not extended 1 : waveform extended 0 : waveform not extended 1 : waveform extended 0 : waveform not extended 1 : waveform extended 0 : l output 1 : h output 0 : l output 1 : h output 0 : int 0 pin one-shot trigger invalid 1 : int 0 pin one-shot trigger valid note: stop timer z to change the values of these bits.
7540 group user s manual 3-108 appendix 3.5 list of registers fig. 3.5.19 structure of prescaler 1 prescaler 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 prescaler 1 (pre1) [address : 28 16 ] set a count value of prescaler 1. the value set in this register is written to both prescaler 1 and the prescaler 1 latch at the same time. when this register is read out, the count value of the prescaler 1 latch is read out. fig. 3.5.20 structure of timer 1 timer 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 timer 1 (t1) [address : 29 16 ] set a count value of timer 1. the value set in this register is written to both timer 1 and timer 1 latch at the same time. when this register is read out, the timer 1 s count value is read out.
7540 group user s manual 3-109 appendix 3.5 list of registers fig. 3.5.21 structure of one-shot start register one-shot start register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 one-shot start register (ons) [address : 2a 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? ? timer z one-shot start bit ? ? ? ? ? 0 : one-shot stop 1 : one-shot start
7540 group user s manual 3-110 appendix 3.5 list of registers fig. 3.5.22 structure of timer x mode register timer x operating modes timer mode pulse output mode event counter mode pulse width measurement mode cntr 0 active edge switch bit (bit 2 of address 2b 16 ) contents 0 cntr 0 interrupt request occurrence: falling edge ; no influence to timer count 1 cntr 0 interrupt request occurrence: rising edge ; no influence to timer count 0 pulse output start: beginning at h level cntr 0 interrupt request occurrence: falling edge 1 pulse output start: beginning at l level cntr 0 interrupt request occurrence: rising edge 0 timer x: rising edge count cntr 0 interrupt request occurrence: falling edge 1 timer x: falling edge count cntr 0 interrupt request occurrence: rising edge 0 timer x: h level width measurement cntr 0 interrupt request occurrence: falling edge 1 timer x: l level width measurement cntr 0 interrupt request occurrence: rising edge table 3.5.2 cntr 0 active edge switch bit function b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 2 3 4 5 6 7 name 0 0 0 0 timer x mode register (txm) [address : 2b 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? ? ? timer x mode register 0 0 0 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode b1 b0 1 0 timer x operating mode bits cntr 0 active edge switch bit the function depends on the operating mode. (refer to table 3.5.2) timer x count stop bit 0 : count start 1 : count stop 0 : output invalid (i/o port) 1 : output valid (inverted cntr 0 output) p0 3 /tx out output valid bit
7540 group user s manual 3-111 appendix 3.5 list of registers fig. 3.5.23 structure of prescaler x fig. 3.5.24 structure of timer x prescaler x b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 prescaler x (prex) [address : 2c 16 ] set a count value of prescaler x. the value set in this register is written to both prescaler x and the prescaler x latch at the same time. when this register is read out, the count value of the prescaler x is read out. timer x b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 timer x (tx) [address : 2d 16 ] set a count value of timer x. the value set in this register is written to both timer x and timer x latch at the same time. when this register is read out, the timer x s count value is read out.
7540 group user s manual 3-112 appendix 3.5 list of registers fig. 3.5.25 structure of timer count source set register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 timer count source set register (tcss) [address : 2e 16 ] nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 0 . timer count source set register timer x count source selection bits 0 0 0 b1 b0 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : f(x in ) ( note 1 ) 1 1 : not available 0 timer y count source selection bits timer z count source selection bits notes 1: f(x in ) can be used as timer x count source only when using a ceramic oscillator or ring oscillator. do not use it at rc oscillation. 2: system operates using a ring oscillator as a count source by setting the ring oscillator to oscillation enabled by bit 3 of cpum. fix this bit to 0 . b5 b4 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : timer y underflow 1 1 : not available b3 b2 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : ring oscillator output ( note 2 ) 1 1 : not available ?
7540 group user s manual 3-113 appendix 3.5 list of registers fig. 3.5.27 structure of serial i/o2 register fig. 3.5.26 structure of serial i/o2 control register b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 c o n ) [ a d d r e s s : 3 0 1 6 ] n o t h i n g i s a l l o c a t e d f o r t h i s b i t . t h i s i s a w r i t e d i s a b l e d b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . ? ? s e r i a l i / o 2 c o n t r o l r e g i s t e r 0 0 n o t e : w h e n u s i n g i t a s a s d a t a i n p u t , s e t t h e p o r t p 1 3 d i r e c t i o n r e g i s t e r b i t t o 0 . 0 : l s b f i r s t 1 : m s b f i r s t 0 0 0 : f(x in )/8 0 0 1 : f(x in )/16 0 1 0 : f(x in )/32 0 1 1 : f(x in )/64 1 1 0 : f(x in )/128 1 1 1 : f(x in )/256 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s transfer direction selection bit b 2 b 1 b 0 s d a t a 2 p i n s e l e c t i o n b i t ( n o t e ) 0 : i / o p o r t / s d a t a 2 i n p u t 1 : s d a t a 2 o u t p u t s clk2 pin selection bit 0 : external clock (s clk2 is input) 1 : internal clock (s clk2 is output) t r a n s m i t / r e c e i v e s h i f t c o m p l e t i o n f l a g 0 : shift in progress 1 : shift completed 0 0 serial i/o2 register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? serial i/o2 register (sio2) [address : 31 16 ] a shift register for serial transmission and reception. at transmitting : set a transmission data. at receiving : a reception data is stored.
7540 group user s manual 3-114 appendix 3.5 list of registers fig. 3.5.29 structure of a-d conversion register (low-order) fig. 3.5.28 structure of a-d control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 1 0 0 a-d control register (adcon) [address : 34 16 ] nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 0 . ? a-d control register 0 note: these can be used only for the 36-pin package versions. 0 0 0 : p2 0 /an 0 0 0 1 : p2 1 /an 1 0 1 0 : p2 2 /an 2 0 1 1 : p2 3 /an 3 1 0 0 : p2 4 /an 4 1 0 1 : p2 5 /an 5 1 1 0 : p2 6 /an 6 ( note ) 1 1 1 : p2 7 /an 7 ( note ) analog input pin selection bits b2 b1 b0 0 0 ad conversion completion bit 0 : conversion in progress 1 : conversion completed nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . 0 ? ? ? ? : this bit can be cleared to 0 by program, but cannot be set to 1 . ? a-d conversion register (low-order) b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? a-d conversion register (low-order) (adl) [address : 35 16 ] the read-only register in which the a-d conversion s results are stored. ? ? ? ? ? ? ? ? < 8-bit read> b7 b8 b7 b6 b5 b4 b3 b0 b2 b9 < 10-bit read> b7 b6 b5 b4 b3 b2 b1 b0 b0 b7
7540 group user s manual 3-115 appendix 3.5 list of registers fig. 3.5.31 structure of misrg fig. 3.5.30 structure of a-d conversion register (high-order) a-d conversion register (high-order) b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? a-d conversion register (high-order) (adh) [address : 36 16 ] the read-only register in which the a-d conversion s results are stored. ? ? ? ? ? ? ? ? < 10-bit read> b7 b9 b0 b8 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 misrg [address : 38 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? m i s r g o s c i l l a t i o n s t a b i l i z a t i o n t i m e s e t b i t a f t e r r e l e a s e o f t h e s t p i n s t r u c t i o n 0 0 : set 01 16 in timer 1, and ff 16 in prescaler 1 automatically 1 : not set automatically these are reserved bits. do not write 1 to these bits. 0 0 ( n o t e ) ? ? ? ? ? 0 : oscillation stop not detected 1 : oscillation stop detected ceramic or rc oscillation stop detection function active bit 0 : detection function inactive 1 : detection function active o s c i l l a t i o n s t o p d e t e c t i o n s t a t u s b i t note: 0 at normal reset 1 at reset by detecting the oscillation stop
7540 group user s manual 3-116 appendix 3.5 list of registers fig. 3.5.33 structure of interrupt edge selection register fig. 3.5.32 structure of watchdog timer control register watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 1 1 1 1 1 0 0 watchdog timer control register (wdtcon) [address : 39 16 ] watchdog timer h (the high-order 6 bits are read-only bits.) stp instruction disable bit 0 : stp instruction enabled 1 : stp instruction disabled watchdog timer h count source selection bit 0 : watchdog timer l underflow 1 : f(x in )/16 ? ? ? ? ? ? interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt edge selection register (intedge) [address : 3a 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? ? int 0 interrupt edge selection bit int 1 interrupt edge selection bit 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active p0 0 key-on wakeup enable bit ? ? ? 0 : key-on wakeup enabled 1 : key-on wakeup disabled
7540 group user s manual 3-117 appendix 3.5 list of registers fig. 3.5.34 structure of cpu mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 2 3 4 5 6 7 name 0 0 0 1 cpu mode register (cpum) [address : 3b 16 ] cpu mode register 0 0 0 0 0 : single-chip mode 0 1 : not available 1 0 : not available 1 1 : not available b1 b0 1 0 processor mode bits ( note 1 ) 0 : ceramic oscillation 1 : rc oscillation 0 : 0 page 1 : 1 page stack page selection bit oscillation mode selection bit ( note 1 ) clock division ratio selection bits 0 0 : f(x in )/2 (high-speed mode) 0 1 : f(x in )/8 (middle-speed mode) 1 0 : applied from ring oscillator 1 1 : f(x in ) (double-speed mode) ( note 2 ) b7 b6 0 : ceramic or rc oscillation enabled 1 : ceramic or rc oscillation stop notes 1: the bit can be rewritten only once after releasing reset. after rewriting it is disable to write any data to the bit. however, by reset the bit is initialized and can be rewritten, again. (it is not disable to write any data to the bit for emulator mcu m37540rss .) 2: these bits are used only when a ceramic oscillation is selected. do not use these when an rc oscillation is selected. ring oscillator oscillation control bit 0 : ring oscillator oscillation enabled 1 : ring oscillator oscillation stop x in oscillation control bit
7540 group user s manual 3-118 appendix 3.5 list of registers fig. 3.5.36 structure of interrupt request register 2 fig. 3.5.35 structure of interrupt request register 1 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 1 (ireq1) [address : 3c 16 ] serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued cntr 0 interrupt request bit cntr 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued int 0 interrupt request bit int 1 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued key-on wake up interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? timer x interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ? interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 2 (ireq2) [address : 3d 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . timer y interrupt request bit timer z interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued timer a interrupt request bit serial i/o2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ad converter interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? ?
7540 group user s manual 3-119 appendix 3.5 list of registers fig. 3.5.38 structure of interrupt control register 2 fig. 3.5.37 structure of interrupt control register 1 interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 2 (icon2) [address : 3f 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . ? timer y interrupt enable bit timer z interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled timer 1 interrupt enable bit timer a interrupt enable bit serial i/o2 interrupt enable bit ad conversion interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled ? interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 1 (icon1) [address : 3e 16 ] serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled cntr 0 interrupt enable bit cntr 1 interrupt enable bit int 0 interrupt enable bit int 1 interrupt enable bit key-on wake up interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer x interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled
3-120 appendix 7540 group user? manual 3.6 package outline 3.6 package outline sdip32-p-400-1.78 weight(g) 2.2 jedec code eiaj package code lead material alloy 42/cu alloy 32p4b plastic 32pin 400mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 ?.8 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 1.778 10.16 3.0 0 ?5 5.08 e e 1 32 17 16 1 e c e 1 a 2 a 1 b 2 b b 1 e la seating plane d mmp
7540 group user? manual 3-121 appendix 3.6 package outline ssop36-p-450-0.80 weight(g) jedec code 0.53 eiaj package code lead material alloy 42 36p2r-a plastic 36pin 450mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 .35 0 .05 0 .13 0 .8 14 .2 8 .63 11 .3 0 .27 1 .0 2 .4 0 .15 0 .0 15 .4 8 .8 0 .93 11 .5 0 .765 1 .43 11 .4 2 .5 0 .2 0 .2 15 .6 8 .23 12 .7 0 .15 0 b 2 .5 0 0 10 e e 1 36 19 18 1 h e e d e y f a a 2 a 1 l 1 l c e b 2 e 1 i 2 recommended mount pad detail f z z 1 detail g z 1 0.7 0.85 z b g mmp
addressing mode symbol function details imp imm a bit, a zp bit, zp opn#opn#opn#opn#opn# op n # 3-122 appendix 7540 group user? manual 3.7 machine instructions when t = 0, this instruction adds the contents m, c, and a; and stores the results in a and c. when t = 1, this instruction adds the contents of m(x), m and c; and stores the results in m(x) and c. when t=1, the contents of a re- main unchanged, but the contents of status flags are changed. m(x) represents the contents of memory where is indicated by x. when t = 0, this instruction transfers the con- tents of a and m to the alu which performs a bit-wise and operation and stores the result back in a. when t = 1, this instruction transfers the con- tents m(x) and m to the alu which performs a bit-wise and operation and stores the results back in m(x). when t = 1, the contents of a remain unchanged, but status flags are changed. m(x) represents the contents of memory where is indicated by x. this instruction shifts the content of a or m by one bit to the left, with bit 0 always being set to 0 and bit 7 of a or m always being contained in c. this instruction tests the designated bit i of m or a and takes a branch if the bit is 0. the branch address is specified by a relative ad- dress. if the bit is 1, next instruction is executed. this instruction tests the designated bit i of the m or a and takes a branch if the bit is 1. the branch address is specified by a relative ad- dress. if the bit is 0, next instruction is executed. this instruction takes a branch to the ap- pointed address if c is 0. the branch address is specified by a relative address. if c is 1, the next instruction is executed. this instruction takes a branch to the ap- pointed address if c is 1. the branch address is specified by a relative address. if c is 0, the next instruction is executed. this instruction takes a branch to the ap- pointed address when z is 1. the branch address is specified by a relative address. if z is 0, the next instruction is executed. this instruction takes a bit-wise logical and of a and m contents; however, the contents of a and m are not modified. the contents of n, v, z are changed, but the contents of a, m remain unchanged. this instruction takes a branch to the ap- pointed address when n is 1. the branch address is specified by a relative address. if n is 0, the next instruction is executed. this instruction takes a branch to the ap- pointed address if z is 0. the branch address is specified by a relative address. if z is 1, the next instruction is executed. adc (note 1) (note 5) and (note 1) asl bbc (note 4) bbs (note 4) bcc (note 4) bcs (note 4) beq (note 4) bit bmi (note 4) bne (note 4) 7 0 c 0 29 2 2 0a 2 1 03 + 20i 17 + 20i 07 + 20i 06 5 2 25 3 2 3 65 3 2 69 2 2 4 4 2 2 13 + 20i 5 5 3 3 24 when t = 0 a a + m + c when t = 1 m(x) m(x) + m + c when t = 0 a a m when t = 1 m(x) m(x) m ai or mi = 0? ai or mi = 1? c = 0? c = 1? z = 1? a m n = 1? z = 0? v v v 2 3.7 machine instructions bit, a, r bit, zp, r
addressing mode zp, x zp, y abs abs, x abs, y ind zp, ind ind, x ind, y rel sp 7 6 5 4 3 2 1 0 proc essor st atus register nvtbd i zc op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 7540 group user? manual 3-123 appendix 3.7 machine instructions 75 35 16 4 4 6 2 2 2 6d 2d 0e 2c 4 4 6 4 3 3 3 3 7d 3d 1e 5 5 7 3 3 3 79 39 5 5 3 3 61 21 6 6 2 2 90 b0 f0 2 2 2 2 2 2 71 31 6 6 2 2 n n n m 7 v m 6 z z z z c c 30 d0 2 2 2 2
addressing mode symbol function details imp imm a bit, a zp bit, zp opn#opn#opn#opn#opn# op n # 3-124 appendix 7540 group user? manual 3.7 machine instructions this instruction takes a branch to the ap- pointed address if n is 0. the branch address is specified by a relative address. if n is 1, the next instruction is executed. this instruction branches to the appointed ad- dress. the branch address is specified by a relative address. when the brk instruction is executed, the cpu pushes the current pc contents onto the stack. the badrs designated in the interrupt vector table is stored into the pc. this instruction takes a branch to the ap- pointed address if v is 0. the branch address is specified by a relative address. if v is 1, the next instruction is executed. this instruction takes a branch to the ap- pointed address when v is 1. the branch address is specified by a relative address. when v is 0, the next instruction is executed. this instruction clears the designated bit i of a or m. this instruction clears c. this instruction clears d. this instruction clears i. this instruction clears t. this instruction clears v. when t = 0, this instruction subtracts the con- tents of m from the contents of a. the result is not stored and the contents of a or m are not modified. when t = 1, the cmp subtracts the contents of m from the contents of m(x). the result is not stored and the contents of x, m, and a are not modified. m(x) represents the contents of memory where is indicated by x. this instruction takes the one? complement of the contents of m and stores the result in m. this instruction subtracts the contents of m from the contents of x. the result is not stored and the contents of x and m are not modified. this instruction subtracts the contents of m from the contents of y. the result is not stored and the contents of y and m are not modified. this instruction subtracts 1 from the contents of a or m. bpl (note 4) bra brk bvc (note 4) bvs (note 4) clb clc cld cli clt clv cmp (note 3) com cpx cpy dec n = 0? pc pc ?offset b 1 (pc) (pc) + 2 m(s) pc h s s ?1 m(s) pc l s s ?1 m(s) ps s s ?1 i 1 pc l ad l pc h ad h v = 0? v = 1? ai or mi 0 c 0 d 0 i 0 t 0 v 0 when t = 0 a ?m when t = 1 m(x) ?m __ m m x ?m y ?m a a ?1 or m m ?1 18 d8 58 12 b8 2 2 2 2 2 1 1 1 1 1 c9 e0 c0 2 2 2 2 2 2 1a 2 1 1b + 20i c5 44 e4 c4 c6 3 5 3 3 5 2 2 2 2 2 1f + 20i 21 52 00 7 1
addressing mode zp, x zp, y abs abs, x abs, y ind zp, ind ind, x ind, y rel sp 7 6 5 4 3 2 1 0 proc essor st atus register nvtbd i zc op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 7540 group user? manual 3-125 appendix 3.7 machine instructions d5 d6 cd ec cc ce 50 70 2 2 2 2 n n n n n 0 4 6 4 4 4 6 3 3 3 3 dd de 5 7 3 3 d9 5 3 c1 6 2 d1 6 2 0 1 0 1 0 z z z z z 0 c c c 2 2 10 80 2 4 2 2
addressing mode symbol function details imp imm a bit, a zp bit, zp opn#opn#opn#opn#opn# op n # 3-126 appendix 7540 group user? manual 3.7 machine instructions this instruction subtracts one from the current contents of x. this instruction subtracts one from the current contents of y. this instruction divides the 16-bit data in m(zz+(x)) (low-order byte) and m(zz+(x)+1) (high-order byte) by the contents of a. the quotient is stored in a and the one's comple- ment of the remainder is pushed onto the stack. when t = 0, this instruction transfers the con- tents of the m and a to the alu which performs a bit-wise exclusive or, and stores the result in a. when t = 1, the contents of m(x) and m are transferred to the alu, which performs a bit- wise exclusive or and stores the results in m(x). the contents of a remain unchanged, but status flags are changed. m(x) represents the contents of memory where is indicated by x. this instruction adds one to the contents of a or m. this instruction adds one to the contents of x. this instruction adds one to the contents of y. this instruction jumps to the address desig- nated by the following three addressing modes: absolute indirect absolute zero page indirect absolute this instruction stores the contents of the pc in the stack, then jumps to the address desig- nated by the following addressing modes: absolute special page zero page indirect absolute when t = 0, this instruction transfers the con- tents of m to a. when t = 1, this instruction transfers the con- tents of m to (m(x)). the contents of a remain unchanged, but status flags are changed. m(x) represents the contents of memory where is indicated by x. this instruction loads the immediate value in m. this instruction loads the contents of m in x. this instruction loads the contents of m in y. dex dey div eor (note 1) inc inx iny jmp jsr lda (note 2) ldm ldx ldy x x ?1 y y ?1 a (m(zz + x + 1), m(zz + x )) / a m(s) one's comple- ment of remainder s s ?1 when t = 0 a a v m when t = 1 m(x) m(x) v m a a + 1 or m m + 1 x x + 1 y y + 1 if addressing mode is abs pc l ad l pc h ad h if addressing mode is ind pc l m (ad h , ad l ) pc h m (ad h , ad l + 1) if addressing mode is zp, ind pc l m(00, ad l ) pc h m(00, ad l + 1) m(s) pc h s s ?1 m(s) pc l s s ?1 after executing the above, if addressing mode is abs, pc l ad l pc h ad h if addressing mode is sp, pc l ad l pc h ff if addressing mode is zp, ind, pc l m(00, ad l ) pc h m(00, ad l + 1) when t = 0 a m when t = 1 m(x) m m nn x m y m 3a 21 1 1 1 1 2 2 2 2 ca 88 e8 c8 45 e6 3 5 2 2 49 22 a9 a2 a0 a5 3c a6 a4 3 4 3 3 2 3 2 2 2 2 2 2 2 2
addressing mode zp, x zp, y abs abs, x abs, y ind zp, ind ind, x ind, y rel sp 7 6 5 4 3 2 1 0 proc essor st atus register nvtbd i zc op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 7540 group user? manual 3-127 appendix 3.7 machine instructions e2 16 2 4d ee 4 6 3 3 5d fe 5 7 3 3 59 5 3 n n n n n n n n n z z z z z z z z z 41 6 2 51 6 2 b5 b4 4c 20 ad ae ac 6c a1 4 4 2 2 b6 4 2 3 6 4 4 4 3 3 3 3 3 bd bc 5 5 b9 be 5 5 3 3 3 3 53b2 02 4 7 2 2 62b162 22 5 2 55 f6 4 6 2 2
addressing mode symbol function details imp imm a bit, a zp bit, zp opn#opn#opn#opn#opn# op n # 3-128 appendix 7540 group user? manual 3.7 machine instructions this instruction shifts either a or m one bit to the right such that bit 7 of the result always is set to 0, and the bit 0 is stored in c. this instruction multiply accumulator with the memory specified by the zero page x address mode and stores the high-order byte of the re- sult on the stack and the low-order byte in a. this instruction adds one to the pc but does no otheroperation. when t = 0, this instruction transfers the con- tents of a and m to the alu which performs a bit-wise ?r? and stores the result in a. when t = 1, this instruction transfers the con- tents of m(x) and the m to the alu which performs a bit-wise or, and stores the result in m(x). the contents of a remain unchanged, but status flags are changed. m(x) represents the contents of memory where is indicated by x. this instruction pushes the contents of a to the memory location designated by s, and decrements the contents of s by one. this instruction pushes the contents of ps to the memory location designated by s and dec- rements the contents of s by one. this instruction increments s by one and stores the contents of the memory designated by s in a. this instruction increments s by one and stores the contents of the memory location designated by s in ps. this instruction shifts either a or m one bit left through c. c is stored in bit 0 and bit 7 is stored in c. this instruction shifts either a or m one bit right through c. c is stored in bit 7 and bit 0 is stored in c. this instruction rotates 4 bits of the m content to the right. this instruction increments s by one, and stores the contents of the memory location designated by s in ps. s is again incremented by one and stores the contents of the memory location designated by s in pc l . s is again incremented by one and stores the contents of memory location designated by s in pc h . this instruction increments s by one and stores the contents of the memory location designated by s in pc l . s is again incremented by one and the contents of the memory location is stored in pc h . pc is incremented by 1. lsr mul nop ora (note 1) pha php pla plp rol ror rrf rti rts m(s) a a ? m(zz + x) s s ?1 pc pc + 1 when t = 0 a a v m when t = 1 m(x) m(x) v m m(s) a s s ?1 m(s) ps s s ?1 s s + 1 a m(s) s s + 1 ps m(s) s s + 1 ps m(s) s s + 1 pc l m(s) s s + 1 pc h m(s) s s + 1 pc l m(s) s s + 1 pc h m(s) (pc) (pc) + 1 7 0 c 7 0 7 0 c 7 0 0 c 4a 2 1 ea 2 1 09 2 2 46 05 5 3 2 2 2a 6a 26 66 82 48 08 68 28 40 60 3 3 4 4 6 6 1 1 1 1 1 1 2 2 1 1 5 5 8 2 2 2
addressing mode zp, x zp, y abs abs, x abs, y ind zp, ind ind, x ind, y rel sp 7 6 5 4 3 2 1 0 proc essor st atus register nvtbd i zc op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 7540 group user? manual 3-129 appendix 3.7 machine instructions 0 n n n n z z z z z c c c 56 62 15 6 15 4 2 2 2 4e 0d 6 4 3 3 5e 1d 7 5 3 3 19 53 01 6 2 11 6 2 36 76 2e 6e 6 6 2 2 6 6 3 3 3e 7e 7 7 3 3 (value saved in stack) (value saved in stack)
addressing mode symbol function details imp imm a bit, a zp bit, zp opn#opn#opn#opn#opn# op n # 3-130 appendix 7540 group user? manual 3.7 machine instructions when t = 0, this instruction subtracts the value of m and the complement of c from a, and stores the results in a and c. when t = 1, the instruction subtracts the con- tents of m and the complement of c from the contents of m(x), and stores the results in m(x) and c. a remain unchanged, but status flag are changed. m(x) represents the contents of memory where is indicated by x. this instruction sets the designated bit i of a or m. this instruction sets c. this instruction set d. this instruction set i. this instruction set t. this instruction stores the contents of a in m. the contents of a does not change. this instruction resets the oscillation control f/ f and the oscillation stops. reset or interrupt input is needed to wake up from this mode. this instruction stores the contents of x in m. the contents of x does not change. this instruction stores the contents of y in m. the contents of y does not change. this instruction stores the contents of a in x. the contents of a does not change. this instruction stores the contents of a in y. the contents of a does not change. this instruction tests whether the contents of m are ??or not and modifies the n and z. this instruction transfers the contents of s in x. this instruction stores the contents of x in a. this instruction stores the contents of x in s. this instruction stores the contents of y in a. the wit instruction stops the internal clock but not the oscillation of the oscillation circuit is not stopped. cpu starts its function after the timer x over flows (comes to the terminal count). all regis- ters or internal memory contents except timer x will not change during this mode. (of course needs vdd). sbc (note 1) (note 5) seb sec sed sei set sta stp stx sty tax tay tst tsx txa txs tya wit when t = 0 _ a a ?m ?c when t = 1 _ m(x) m(x) ?m ?c ai or mi 1 c 1 d 1 i 1 t 1 m a m x m y x a y a m = 0? x s a x s x a y 85 86 84 64 4 4 4 3 2 2 2 2 notes 1 : the number of cycles ??is increased by 3 when t is 1. 2 : the number of cycles ??is increased by 2 when t is 1. 3 : the number of cycles ??is increased by 1 when t is 1. 4 : the number of cycles ??is increased by 2 when branching has occurred. 5 : n, v, and z flags are invalid in decimal operation mode. e9 2 2 0b + 20i 0f + 20i 21 52 e5 3 2 38 f8 78 32 2 2 2 2 1 1 1 1 42 aa a8 ba 8a 9a 98 c2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1
addressing mode zp, x zp, y abs abs, x abs, y ind zp, ind ind, x ind, y rel sp 7 6 5 4 3 2 1 0 proc essor st atus register nvtbd i zc op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 7540 group user? manual 3-131 appendix 3.7 machine instructions n n n n n n z z z z z z 3 35 fd 4 ed 2 4 f5 f9 5 3 e1 6 2 f1 6 2 95 94 5 5 2 2 96 52 8d 8e 8c 5 5 5 3 3 3 9d 6 3 99 6 3 81 7 2 91 7 2 n v 1 1 1 z c 1
addition subtraction multiplication division logical or logical and logical exclusive or negation shows direction of data flow index register x index register y stack pointer program counter processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address ff in hexadecimal notation immediate value zero page address memory specified by address designation of any ad- dressing mode memory of address indicated by contents of index register x memory of address indicated by contents of stack pointer contents of memory at address indicated by ad h and ad l , in ad h is 8 high-order bits and ad l is 8 low-or- der bits. contents of address indicated by zero page ad l bit i (i = 0 to 7) of accumulator bit i (i = 0 to 7) of memory opcode number of cycles number of bytes implied addressing mode immediate addressing mode accumulator or accumulator addressing mode accumulator bit addressing mode accumulator bit relative addressing mode zero page addressing mode zero page bit addressing mode zero page bit relative addressing mode zero page x addressing mode zero page y addressing mode absolute addressing mode absolute x addressing mode absolute y addressing mode indirect absolute addressing mode zero page indirect absolute addressing mode indirect x addressing mode indirect y addressing mode relative addressing mode special page addressing mode carry flag zero flag interrupt disable flag decimal mode flag break flag x-modified arithmetic mode flag overflow flag negative flag imp imm a bit, a bit, a, r zp bit, zp bit, zp, r zp, x zp, y abs abs, x abs, y ind zp, ind ind, x ind, y rel sp c z i d b t v n symbol contents symbol contents + ? / v v x y s pc ps pc h pc l ad h ad l ff nn zz m m(x) m(s) m(ad h , ad l ) m(00, ad l ) ai mi op n # v 3-132 appendix 38b5 group user's manual 3.7 machine instructions
7540 group user? manual 3-133 appendix 3.8 list of instruction code 3.8 list of instruction code d 7 ?d 4 d 3 ?d 0 hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f 0000 0 brk bpl jsr abs bmi rti bvc rts bvs bra bcc ldy imm bcs cpy imm bne cpx imm beq 0001 1 ora ind, x ora ind, y and ind, x and ind, y eor ind, x eor ind, y adc ind, x adc ind, y sta ind, x sta ind, y lda ind, x lda ind, y cmp ind, x cmp ind, y sbc ind, x sbc ind, y 0010 2 jsr zp, ind clt jsr sp set stp mul zp, x rrf zp ldx imm jmp zp, ind wit div zp, x 0011 3 bbs 0, a bbc 0, a bbs 1, a bbc 1, a bbs 2, a bbc 2, a bbs 3, a bbc 3, a bbs 4, a bbc 4, a bbs 5, a bbc 5, a bbs 6, a bbc 6, a bbs 7, a bbc 7, a 0100 4 bit zp com zp tst zp sty zp sty zp, x ldy zp ldy zp, x cpy zp cpx zp 0101 5 ora zp ora zp, x and zp and zp, x eor zp eor zp, x adc zp adc zp, x sta zp sta zp, x lda zp lda zp, x cmp zp cmp zp, x sbc zp sbc zp, x 0110 6 asl zp asl zp, x rol zp rol zp, x lsr zp lsr zp, x ror zp ror zp, x stx zp stx zp, y ldx zp ldx zp, y dec zp dec zp, x inc zp inc zp, x 0111 7 bbs 0, zp bbc 0, zp bbs 1, zp bbc 1, zp bbs 2, zp bbc 2, zp bbs 3, zp bbc 3, zp bbs 4, zp bbc 4, zp bbs 5, zp bbc 5, zp bbs 6, zp bbc 6, zp bbs 7, zp bbc 7, zp 1000 8 php clc plp sec pha cli pla sei dey tya tay clv iny cld inx sed 1001 9 ora imm ora abs, y and imm and abs, y eor imm eor abs, y adc imm adc abs, y sta abs, y lda imm lda abs, y cmp imm cmp abs, y sbc imm sbc abs, y 1010 a asl a dec a rol a inc a lsr a ror a txa txs tax tsx dex nop 1011 b seb 0, a clb 0, a seb 1, a clb 1, a seb 2, a clb 2, a seb 3, a clb 3, a seb 4, a clb 4, a seb 5, a clb 5, a seb 6, a clb 6, a seb 7, a clb 7, a 1100 c bit abs ldm zp jmp abs jmp ind sty abs ldy abs ldy abs, x cpy abs cpx abs 1101 d ora abs ora abs, x and abs and abs, x eor abs eor abs, x adc abs adc abs, x sta abs sta abs, x lda abs lda abs, x cmp abs cmp abs, x sbc abs sbc abs, x 1 110 e asl abs asl abs, x rol abs rol abs, x lsr abs lsr abs, x ror abs ror abs, x stx abs ldx abs ldx abs, y dec abs dec abs, x inc abs inc abs, x 1111 f seb 0, zp clb 0, zp seb 1, zp clb 1, zp seb 2, zp clb 2, zp seb 3, zp clb 3, zp seb 4, zp clb 4, zp seb 5, zp clb 5, zp seb 6, zp clb 6, zp seb 7, zp clb 7, zp : 3-byte instruction : 2-byte instruction : 1-byte instruction
3-134 appendix 7540 group user? manual 3.9 sfr memory map 3.9 sfr memory map 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) pull-up control register (pull) transmit/receive buffer register (tb/rb) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart control register (uartcon) baud rate generator (brg) port p1p3 control register (p1p3c) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 timer count source set register (tcss) a-d conversion register (low-order) (adl) prescaler 1 (pre1) timer 1 (t1) one-shot start register (ons) timer x mode register (txm) prescaler x (prex) timer x (tx) serial i/o2 control register (sio2con) serial i/o2 register (sio2) a-d control register (adcon) a-d conversion register (high-order) (adh) misrg watchdog timer control register (wdtcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt control register 1 (icon1) timer a mode register (tam) timer a (low-order) (tal) timer a (high-order) (tah) timer y, z mode register (tyzm) prescaler y (prey) timer y secondary (tys) timer y primary (typ) timer y, z waveform output control register (pum) prescaler z (prez) timer z secondary (tzs) timer z primary (tzp) interrupt request register 2 (ireq2) interrupt control register 2 (icon2)
7540 group user s manual 3-135 appendix 3.10 pin configurations 3.10 pin configurations fig. 3.10.1 32p6u-a package pin configuration (top view) package type: 32p6u-a p0 7 p1 0 /r x d 1 p1 1 /t x d 1 p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 / an 0 p2 1 / an 1 32 31 30 29 28 27 26 25 p3 4 (led 4 ) p3 3 (led 3 ) p3 2 (led 2 ) p3 1 (led 1 ) p3 0 (led 0 ) v ss x out x in 9 10 11 12 13 14 15 16 2 8 7 6 5 3 1 4 v cc cnv ss reset p2 2 /an 2 p0 5 20 17 18 19 21 24 p0 2 /tz out p0 4 p0 3 /tx out p0 6 23 22 p0 1 /ty out p0 0 /cntr 1 p3 7 /int 0 m37540mx-xxxgp m37540mxt-xxxgp m37540mxv-xxxgp m37540exgp m37540e8t-xxxgp m37540e8v-xxxgp p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 v ref
3-136 appendix 7540 group user s manual 3.10 pin configurations fig. 3.10.2 36p2r-a package pin configuration (top view) packa g e t yp e: 36p2r-a 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 21 20 19 32 27 29 28 p0 0 /cntr 1 cnv ss x out x in v ss p0 1 /ty out p0 2 /tz out p0 3 /tx out p0 4 p3 0 (led 0 ) vcc v ref p0 5 p1 0 /r x d 1 p2 6 /an 6 p2 7 /an 7 p1 1 /t x d 1 p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p2 3 /an 3 p2 2 /an 2 p2 1 /an 1 p2 0 /an 0 p3 1 (led 1 ) p3 6 (led 6 )/int 1 p2 4 /an 4 p2 5 /an 5 p0 6 p0 7 p3 7 /int 0 reset m37540mx-xxxfp m37540mxt-xxxfp m37540mxv-xxxfp m37540e8fp m37540e8t-xxxfp m37540e8v-xxxfp p1 4 /cntr 0 p3 5 (led 5 ) p3 4 (led 4 ) p3 3 (led 3 ) p3 2 (led 2 )
7540 group user s manual 3-137 appendix 3.10 pin configurations fig. 3.10.3 32p4b package pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cnv ss p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 v cc x in x out v ss p1 1 /t x d 1 p1 0 /r x d 1 p0 7 p0 6 p0 5 p0 4 p3 0 (led 0 ) p2 5 /an 5 v ref reset p0 0 /cntr 1 p3 3 (led 3 ) p3 2 (led 2 ) p3 1 (led 1 ) m37540mx-xxxsp m37540exsp 32 p0 1 /ty out p0 2 /tz out p0 3 /tx out 14 15 16 p3 7 /int 0 p3 4 (led 4 ) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 package type: 32p4b
3-138 appendix 7540 group user s manual 3.10 pin configurations fig. 3.10.4 42s1m package pin configuration (top view) outline 42s1m 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 32 27 29 28 19 20 21 42 41 40 39 37 38 p0 0 /cntr 1 cnv ss x out x in v ss p0 1 /ty out p0 2 /tz out p0 3 /tx out p0 4 p3 0 (led 0 ) vcc v ref p0 5 p1 2 /s clk1 /s clk2 p2 5 /an 5 p2 6 /an 6 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 nc p2 2 /an 2 nc p2 1 /an 1 p2 0 /an 0 p3 1 (led 1 ) p3 6 (led 6 )/int 1 p2 3 /an 3 p2 4 /an 4 p0 6 p0 7 p3 7 /int 0 reset m37540rss nc p3 5 (led 5 ) p3 4 (led 4 ) p3 3 (led 3 ) p3 2 (led 2 ) nc p1 0 /r x d 1 p1 1 /t x d 1 nc nc p2 7 /an 7
7540 group user? manual 3-139 appendix 3.11 differences between 7540 group and 7531 group 3.11 differences between 7540 group and 7531 group table 3.11.1 shows the differences between 7540 group and 7531 group. table 3.11.1 differences between 7540 group and 7531 group (performance overview) 7531 group 69 8 to 16 k bytes 256 to 384 bytes initial value: ff 16 (ports p0 and p3 pull-up on) 11 sources, 8 vector (3 for external) 12 sources, 8 vector (4 for external) 3 (timer 1, 2, x) uart only cecamic oscillator/ quartz-crystal oscillator/ rc oscillation parameter number of basic instructions memory sizes input/output ports interrupt sources 16-bit timer 8-bit timer serial i/o1 clock generation circuit oscillation stop detection circuit rom ram 32-pin version 36-pin version 7540 group 71 (div, mul instruction added) 16 to 32 k bytes 512 to 768 bytes initial value: 00 16 (ports p0 and p3 pull-up off) 14 sources, 14 vector (4 for external) 15 sources, 15 vector (5 for external) 1 (timer a) 3 (timer 1, x, y, z) clock synchronous/uart cecamic oscillator/ quartz-crystal oscillator/ rc oscillation/ ring oscillator oscillation 1
3-140 appendix 7540 group user? manual 3.11 differences between 7540 group and 7531 group figure 3.11.1 shows the memory map of 7540 group and 7531 group. fig. 3.11.1 memory map of 7540 group and 7531 group 0000 16 0 0 4 0 1 6 0 0 f f 1 6 pppp 16 ff00 16 f f f e 1 6 ffff 16 0100 16 rom ram (512/768 bytes) z e r o p a g e special page 7 5 4 0 g r o u p 0440 16 qqqq 16 rrrr 16 f f d c 1 6 address pppp 16 5 1 2 023f 16 7 6 8 033f 16 address qqqq 16 address rrrr 16 16384 c 0 0 0 1 6 c080 16 32768 8000 16 8 0 8 0 1 6 7 5 3 1 g r o u p 0 0 0 0 1 6 0 0 4 0 1 6 0 0 f f 1 6 x x x x 1 6 ff00 16 f f f e 1 6 ffff 16 0 1 0 0 1 6 s f r a r e a r a m ( 2 5 6 / 3 8 4 b y t e s ) n o t u s e d r e s e r v e d a r e a 0440 16 reserved rom area (common rom area 128 bytes) y y y y 1 6 zzzz 16 r e s e r v e d r o m a r e a f f d c 1 6 i n t e r r u p t v e c t o r a r e a rom r a m a r e a ram capacity ( b y t e s ) a d d r e s s x x x x 1 6 256 013f 16 3 8 40 1 b f 1 6 rom area r o m c a p a c i t y ( b y t e s ) a d d r e s s y y y y 1 6 address zzzz 16 8 1 9 2e 0 0 0 1 6 e 0 8 0 1 6 1 6 3 8 4c 0 0 0 1 6 c 0 8 0 1 6 ram area ram capacity (bytes) rom area r o m c a p a c i t y (bytes) sfr area not used reserved area r e s e r v e d r o m a r e a interrupt vector area reserved rom area (common rom area 128 bytes)
7540 group user s manual 3-141 appendix 3.11 differences between 7540 group and 7531 group figure 3.11.2 shows the memory map of interrupt vector area of 7540 group and 7531 group. fig. 3.11.2 memory map of interrupt vector area of 7540 group and 7531 group ffeb 16 ffec 16 ffed 16 ffee 16 ffea 16 ffef 16 fff0 16 fff1 16 fff2 16 fff3 16 fff4 16 fff5 16 fff6 16 fff7 16 fff8 16 fff9 16 fffa 16 fffb 16 fffc 16 fffd 16 ffe9 16 ffe8 16 f f e c 1 6 f f e d 1 6 f f e e 1 6 f f e f 1 6 fff0 16 fff1 16 fff2 16 fff3 16 fff4 16 fff5 16 fff6 16 f f f 7 1 6 f f f 8 1 6 f f f 9 1 6 f f f a 1 6 f f f b 1 6 f f f c 1 6 f f f d 1 6 c n t r 0 / a - d c o n v e r s i o n i n t e r r u p t timer x/key-on wakeup interrupt t i m e r 2 / s e r i a l i / o 2 i n t e r r u p t timer 1 interrupt i n t 0 i n t e r r u p t b r k i n s t r u c t i o n i n t e r r u p t r e s e t 7531 group 7540 group serial i/o1 receive interrupt s e r i a l i / o 1 t r a n s m i t / i n t 1 ( n o t e ) i n t e r r u p t note: the interrupt can be used only for the 36-pin version. ffdc 16 ffdd 16 ffde 16 ffdf 16 ffe0 16 ffe1 16 ffe2 16 ffe3 16 ffe4 16 ffe5 16 ffe6 16 ffe7 16 : interrupts added in 7540 group b r k i n s t r u c t i o n i n t e r r u p t timer 1 interrupt a-d conversion interrupt serial i/o2 interrupt r e s e t serial i/o1 receive interrupt serial i/o1 transmit interrupt int 0 interrupt int 1 interrupt (note) key-on wakeup interrupt c n t r 0 i n t e r r u p t c n t r 1 i n t e r r u p t timer x interrupt timer y interrupt timer z interrupt timer a interrupt reserved area
3-142 appendix 7540 group user s manual 3.11 differences between 7540 group and 7531 group figure 3.11.3 shows the timer function of 7540 group and 7531 group. fig. 3.11.3 timer function of 7540 group and 7531 group t i m e r y c a n b e u s e d f o r t h e t i m e r z c o u n t s o u r c e . 7540 group 7 5 3 1 g r o u p t i m e r 1 ( 8 - b i t t i m e r ) t i m e r m o d e the number of timer increased function expanded t i m e r 2 ( 8 - b i t t i m e r ) t i m e r m o d e t i m e r x ( 8 - b i t t i m e r ) t i m e r m o d e p u l s e o u t p u t m o d e e v e n t c o u n t e r m o d e p u l s e w i d t h m e a s u r e m e n t m o d e t i m e r 1 ( 8 - b i t t i m e r ) t i m e r m o d e t i m e r x ( 8 - b i t t i m e r ) t i m e r m o d e p u l s e o u t p u t m o d e ( i n v e r t e d o u t p u t p o r t a d d e d ) e v e n t c o u n t e r m o d e p u l s e w i d t h m e a s u r e m e n t m o d e t i m e r y ( 8 - b i t t i m e r ) t i m e r m o d e p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e t i m e r z ( 8 - b i t t i m e r ) t i m e r m o d e p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e p r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e p r o g r a m m a b l e w a i t o n e - s h o t g e n e r a t i o n m o d e timer a (16-bit timer) timer mode period measurement mode event counter mode pulse width hl continuously measurement mode
renesas 8-bit cisc single-chip microcomputer user? manual 7540 group rev.1.00 editioned by committee of editing of renesas semiconductor user? manual this book, or parts thereof, may not be reproduced in any form without permission of renesas technology corporation. copyright 2003. renesas technology corporation, all rights reserved.
7540 group user s manual 2-6-2, ote-machi, chiyoda-ku, tokyo, 100-0004, japan

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