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www.fairchildsemi.com rev. 1.1.5 7/24/02 features high ef?iency over wide load range non dissipative current-sense; uses mosfet r ds(on) or can use optional current-sense resistor for greater precision overcurrent protection powerful drivers for n-channel mosfets with adaptive dead time precision core voltage control remote ?elvin?sensing summing current-mode control with programmable active droop for optimum transient response and lower processor power dissipation 5-bit digital output voltage selection wide range output voltage: 0.6 vdc to 1.0 vdc in 25mv steps, and from 1.0 vdc to 1.75 vdc in 50mv steps ?n-the-fly?vid code change with programmable slew rate alternative input to set output voltage during start-up or power saving modes forced continuous conduction mode of operation output voltage (power-good) monitor no negative core voltage on turn-off over-voltage, under-voltage and over-current fault monitors selectable 300/600khz switching frequency applications mobile pcs web tablets internet appliances description the FAN5250 is a single output power controller to power transmetas crusoe mobile cpu core. the FAN5250 includes a 5-bit digital-to-analog converter (dac) that adjusts the core pwm output voltage from 0.6vdc to 1.75vdc, and may be changed during operation. special measures are taken to allow the output to transition with controlled slew rate to comply with transmetas longrun technology. the FAN5250 includes a precision reference, and a proprietary architecture with integrated compensation providing excellent static and dynamic core voltage regula- tion. with nominal currents, the controller operates at a selectable frequency of 300khz or 600khz. at light loads, when the ?ter inductor current becomes discontinuous, the controller operates in a hysteretic mode dramatically improving system ef?iency. the hysteretic mode of operation can be inhibited by the fpwm control pin. the FAN5250 monitors the output voltage and issues a pgood (power-good) when soft start is completed and the output is in regulation. a built-in over-voltage protection (ovp) forces the lower mosfet on to prevent output volt- ages from exceeding 1.9v. undervoltage protection latches the chip off when the output drops below 75% of the set value. the pwm controller's overcurrent circuitry monitors the converter load by sensing the voltage drop across the lower mosfet. the overcurrent threshold is set by an external resistor. if precision overcurrent protection is required, an optional external current-sense resistor may be used. FAN5250 crusoe processor core-voltage regulator longrun is a trademark of transmeta corporation.
FAN5250 2 rev. 1.1.5 7/24/02 typical application figure 1. pin assignments qsop-24 ja = 90? FAN5250 vin (battery) = 5 to 24v hdrv boot sw ldrv 22 23 20 19 vin 13 start pgnd c boot q1 c out 18 16 vcore+ 4 en 14 ss 11 vcc 10 9 8 12 vid0 vid1 vid2 vid3 vid4 2 15 r5 dsx r7 altv 24 pvcc +5 +5 +5 1 agnd 3 v core pgood 6 17 7 freq isns 21 5 c ss r8 ilim n/c fpwm l out q2 pvcc ldrv pgnd isns sw hdrv boot nc vcore+ ilim ss vin agnd vcc pgood en fpwm altv freq vid4 vid3 vid2 vid1 vid0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
FAN5250 rev. 1.1.5 7/24/02 3 pin description pin number pin name pin function description 1 agnd analog ground . this is the signal ground reference for the ic. all voltage levels are measured with respect to this pin. 2 vcc vcc. this pin powers the chip. the ic starts to operate when voltage on this pin exceeds 4.6v (uvlo rising) and shuts down when it drops below 4.3v (uvlo falling). 3 pgood power good flag. an open-drain output that will pull low when the core output is outside of a +25% 10% range of the vid reference voltage the pgood pin is kept high during transitions between vid settings, deep sleep, and reserved mode transitions. 4en enable. this pin enables ic operation when either left open, or pulled up to vcc. toggling en will also reset the chip after a latched fault condition. 5 fpwm forced pwm mode. when logic low, inhibits the chip from entering hysteretic operating mode. 6altv alternative to vid. the ic will regulate to the voltage on this pin if it is below the highest vid voltage (1.75v). such a requirement may occur during cpu initialization or during some power saving modes. this pin has a 10 a current source, so that its voltage can be programmed with a resistor to gnd. see alternative voltage programming on page 8 for details. 7 freq frequency set. logic low sets the operating frequency to 300khz. high sets the frequency to 600khz. 8 12 vid0 4 voltage identification code . input to vid dac. sets the output voltage according to the codes set as defined in table 1. 13 vin input voltage from battery. this voltage is used by the oscillator for feed-forward compensation of input voltage variation. 14 ss soft start. a capacitor from this pin to gnd programs the slew rate of the converter during initialization as well as in operation. this pin is used as the reference against which the output is compared. during initialization, this pin is charged with a 25 a current source. once this pin reaches 0.5v, its function changes, and it assumes the value of the voltage as set by the vid programming. the current driving this pin is then limited to + 500 a, that together with c ss sets a controlled slew rate for vid code changes. 15 ilim current limit. a resistor from this pin to gnd sets the current limit. 16 v core + vcore output sense. this pin is the feedback from the vcore output. used for regulation as well as pgood, under-voltage and over-voltage protection and monitoring. 17 nc no internal connection. while no connection is necessary, tying this pin to gnd is recommended to reduce coupled noise into pin 16 from pin 18. 18 boot boot. the positive supply for the upper mosfet driver. connect as shown in figure 1. 19 hdrv high-side drive. the high-side (upper) mosfet driver output. 20 sw switching node. the return for the high-side mosfet driver. 21 isns current sense input. monitors the voltage drop across the lower mosfet or external sense resistor for current feedback. 22 pgnd power ground. the return for the low-side mosfet driver. 23 ldrv low-side drive. the low-side (lower) mosfet driver output. 24 pvcc power vcc. the positive supply for the lower mosfet driver.
FAN5250 4 rev. 1.1.5 7/24/02 absolute maximum ratings absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. functional operation under these conditions is not implied recommended operating conditions parameter min. typ. max. units vcc supply voltage 6.5 v vin 27 v boot, sw, hdrv pins 33 v boot to sw 6.5 v all other pins -0.3 vcc + 0.3 v junction temperature (t j ) -10 150 c storage temperature -65 150 c lead soldering temperature, 10 seconds 300 c parameter conditions min. typ. max. units supply voltage vcc 4.75 5 5.25 v supply voltage vin 5 24 v ambient temperature (t a ) 10 85 c
FAN5250 rev. 1.1.5 7/24/02 5 electrical speci?ations (vcc = 5v, vin = 5v 24v, and t a = recommended operating ambient temperature range using circuit of figure 1, unless otherwise noted) parameter conditions min. typ. max. units power supplies vcc current operating, c l = 10pf 2.7 3.2 ma shut-down (en = 0) 6 30 a vin current operating 12 20 a shut-down (en = 0) 1 a uvlo threshold rising vcc 4.3 4.65 4.75 v falling 4.1 4.35 4.45 v regulator / control functions output voltage per table 1. output voltage vid 0.6 1.75 v initial accuracy -1 1 % vid static load regulation -2 2 % vid error amplifier gain 86 db error amplifier gbw 2.7 mhz error amplifier slew rate 1 v/s ilim voltage r ilim = 30k ? 0.89 0.91 v over-voltage threshold 1.9 1.95 2.0 v over-voltage protection delay 1.6 3.2 s under-voltage shutdown disabled during vid code change 72 75 78 % vid under-voltage delay 1.2 1.6 s en, input threshold logic low 1.2 v logic high 2 v output drivers hdrv output resistance sourcing 3.8 5 ? sinking 1.6 3 ? ldrv output resistance sourcing 3.8 5 ? sinking 0.8 1.5 ? oscillator frequency freq = high 255 300 345 khz freq = low 510 600 690 khz ramp amplitude, pk-pk vin = 16v 2 v ramp offset 0.5 v ramp gain ramp amplitude vin 125 mv/v reference, dac and soft-start vid input threshold logic low 1.21 v logic high 1.62 v vid pull-up current to internal 2.5v reference 12 a dac output accuracy -1 1 %
FAN5250 6 rev. 1.1.5 7/24/02 figure 2. ic block diagram soft start current (i ss ) at start-up, v ss < 0.5 20 26 32 a at start-up, 1.75 > v ss > 0.5 350 500 650 a altv current source 9.5 10 10.5 a altv to vid mode threshold 1.71 1.75 1.78 v pgood vcore upper threshold 123 127 % vid vcore lower threshold falling edge 77 81 % vid rising edge 87 94 % vid pgood output low ipgood = 4ma 0.5 v leakage current v pullup = 5v 1 a electrical speci?ations (continued) (vcc = 5v, vin = 5v 24v, and t a = recommended operating ambient temperature range using circuit of figure 1, unless otherwise noted) parameter conditions min. typ. max. units pgood fpwm en c boot q1 q2 5v vdd adaptive gate control logic current processing 5 4 20 19 7 18 hdrv sw ldrv pgnd boot vdd hyst isns 21 vin c out v core pwm/hyst pwm s/h 15 ilim r5 r sense ilim det. 16 ea hyst 14 ss vcore+ ss dty cyc clamp pwm sr q ramp mode 13 vin osc i out ramp clk ovp por/uvlo freq 7 4 5 dac and soft start 3 fpwm l out
FAN5250 rev. 1.1.5 7/24/02 7 circuit description overview the FAN5250 is a single output power management ic supplies the low-voltage, high-current power to modern processors for notebook and sub-notebook pcs. using very few external components, the ic controls a precision pro- grammable synchronous buck converter driving external n-channel power mosfets. the output voltage is adjust- able from 0.6v to 1.75v by changing the dac code settings (see table 1). alternatively, the output voltage can be set by an analog input. this feature is important in systems where vid code may not be established during start-up or cpu core power saving modes. the output voltage of the core converter can be changed on-the-? with programmable slew rate, which meets a key requirement of transmetas crusoe processors. the converter can operate in two modes: ?ed frequency pwm, and variable frequency hysteretic depending on the load. at loads lower than the point where ?ter inductor current becomes discontinuous, hysteretic mode of operation is activated. switchover from pwm to hysteretic operation at light loads improves the converter's ef?iency and prolongs battery run time. as the ?ter inductor resumes continuous current, the pwm mode of operation is restored. the chip can be prevented from entering hysteretic mode by driving the fpwm pin low. the core converter incorporates a proprietary output voltage droop method for optimum handling of fast load transients found in modern processors. initialization and soft start assuming en is high, FAN5250 is initialized when power is applied on vcc. should vcc drop below the uvlo threshold, an internal power-on reset function disables the chip. the ic attempts to regulate the vcore output according to the voltage that appears on the ss pin (v ss ). during start-up of the converter, this voltage is initially 0, and rises linearly to 0.5v via the current supplied to c ss through the 25? internal current source. the time it takes to reach 0.5v is: where t 0.5 is in seconds if c ss is in ?. at that point, the current source changes to 500?, which then sets the slew rate of voltage changes at the output in response to changes in vid. this dual slope approach helps to provide safe rise of voltages and currents in the converters during initial start-up and at the same time sets a controlled speed of the core voltage change when the processor commands to do so. figure 3. soft-start function c ss typically is chosen based on the slew rate desired in response to a vid change. for example, if the spec requires a 50mv step to occur in 32?: with this value of c ss , the time for the output voltage to rise to 0.5v if found using equation 1: t 0.5 = 6.6ms we de?ed a slew rate of 50mv/32? to choose the capacitor, therefore it takes an additional 450? to rise from 0.5v to 1.2v. converter operation at nominal current the converter operates in ?ed frequency pwm mode. the output voltage is compared with a reference voltage set by the dac, which appears on the ss pin. the derived error signal is ampli?d by an internally compensated error ampli?r and applied to the inverting input of the pwm comparator. to provide output voltage droop for enhanced dynamic load regulation, a signal proportional to the output current is added to the voltage feedback signal. this feedback scheme in conjunction with a pwm ramp proportional to the input voltage allows for fast and stable loop response over a wide range of input voltage and output current variations. for the sake of ef?iency and maximum simplicity, the current sense signal is derived from the voltage drop across the lower mosfet during its conduction time. t 0.5 0.5 c ss 25 ------------------------- = 1v 0 en ss vcore pgood 1v 0 c ss ? i ss ? v dac ------------------ = ? t 500 a 50mv ----------------- - ?? ?? 32 s = 0.33 f ? (2) t 1.2 t 0.5 t 0.5to1.2 () 6.6 = 0.45 ++ 7ms == (3) (1)
FAN5250 8 rev. 1.1.5 7/24/02 output voltage programming the output voltage of the converter is programmed by an internal dac in discrete steps between 0.6v and 1.75v: table 1. output voltage vid 1 = logic high or open, 0 = logic low vid0? pins will assume a logic 1 level if left open as each has a 12? internal current source pull-up to 2.5v. the output of the dac voltage also establishes the thresholds for pgood, uvp and ovp thresholds. alternative voltage programming input the output voltage can alternatively be set by the altv pin. this override of the vid dac becomes necessary during power-up and some power saving modes of operation, when the voltage on the processor is insuf?ient to provide correct vid codes to the controller. therefore, the required core voltage should be set by some means external to the processor. a common approach to this problem is to provide hard-wired vid codes via a multiplexer controlled by the cpu. that approach lacks simplicity and takes many external components and valuable motherboard area. the FAN5250 uses a simpler way to set the core voltages when the cpu is incapable of providing valid vid codes. a resistor-mosfet network (shown in figure 4) works with the calibrated 10? current from the altv pin to set the altv voltage when the mosfet's gate is driven high. the controller regulates the output voltage to the level established on the altv pin when this voltage is lower than the highest vid programmed voltage (1.75v). when both mosfet gates are low, the altv pin goes to 2.5v and the output is controlled by the vid code. if a more accurate deep-sleep (dsx) and start voltages are required than the internal current source can provide, it may be overridden with the external resistor shown (grey-shading). figure 4. altv programming when relying on the internal current source to set altv: when using rx for greater accuracy, on the internal current source to set altv, choose a value for rx where vid4 vid3 vid2 vid1 vid0 v out to cpu 11111 0.600 11110 0.625 11101 0.650 11100 0.675 11011 0.700 11010 0.725 11001 0.750 11000 0.775 10111 0.800 10110 0.825 10101 0.850 10100 0.875 10011 0.900 10010 0.925 10001 0.950 10000 0.975 01111 1.000 01110 1.050 01101 1.100 01100 1.150 01011 1.200 01010 1.250 01001 1.300 01000 1.350 00111 1.400 00110 1.450 00101 1.500 00100 1.550 00011 1.600 00010 1.650 00001 1.700 00000 1.750 start dsx altv 6 r8 r7 ref rx 2.5v 10?a r7 v start 10 a -------------------- ?? ?? = and r8 ? v dsx 10 a -------------- ?? ?? = (4) r7 vv start v ref v start r x 10 a () + -------------------------------------------------------------------------------- - ?? ?? = r8 rv start v ref v dsx r x 10 a () + -------------------------------------------------------------------------- ?? ?? = v ref v start r x ---------------------------------------- - ?? ?? 10 a (5) , then
FAN5250 rev. 1.1.5 7/24/02 9 operation mode control the mode-control circuit changes the converters mode of operation based on the voltage polarity of the sw node when the lower mosfet is conducting and just before the upper mosfet turns on. for continuous inductor current, the sw node is negative when the lower mosfet is conducting and the converters operate in ?ed-frequency pwm mode as shown in figure 5. this mode of operation achieves high ef?iency at nominal load. when the load current decreases to the point where the inductor current ?ws through the lower mosfet in the ?everse direction, the sw node becomes positive, and the mode is changed to hysteretic, which achieves higher ef?iency at low currents by decreas- ing the effective switching frequency. a comparator handles the timing of the sw node voltage sensing. a low level on the sw comparator output indicates a negative sw voltage during the conduction time of the lower mosfet. a high level on the comparator output indi- cates a positive sw voltage. to prevent accidental mode change and ?ode chatter? the circuit must detect eight con- secutive matching sign signals in a row before it changes mode. if during the monitoring process the mismatch of volt- age signs occurs, no decision to mode change will occur. this same decision algorithm is used both for changing from pwm to hysteretic mode as well as from hysteretic to pwm mode. pwm mode is sustained during all upward and downward transitions commanded by either vid code change, or during transitions from altv programmed voltage to vid code set voltage, or vice versa, as well as in soft-start. the boundary value of inductor current, where current becomes discontinuous, can be estimated by the following expression. hysteretic mode the mode change from hysteretic to pwm can be caused by one of two events. one event is the same mechanism that causes a pwm to hysteretic transition. but instead of look- ing for eight consecutive positive occurrences on the sw node it is looking for eight consecutive negative occurrences on the sw node. the operation mode will be changed from hysteretic to pwm when these eight consecutive pulses occur. this transition technique prevents jitter of the operation mode at load levels close to boundary. the other mechanism for changing from hysteretic to pwm is due to a sudden increase in the output current. this step load causes an instantaneous decrease in the output voltage due to the voltage drop on the output capacitor esr. if the decrease causes the output voltage to drop below the hyster- etic regulation level (20mv below v ss ), the mode is changed to pwm on the next clock cycle. this insures the full power required by the increase in output current. in hysteretic mode, the pwm comparator and the error ampli?r that provided control in pwm mode are inhibited and the hysteretic comparator is activated. in this mode the synchronous recti?r mosfet is controlled in diode emulation mode, where the voltage across it is monitored, and it is switched off when its voltage goes positive (current ?wing back from the load) allowing the schottky diode to block reverse conduction. the hysteretic comparator initiates a pfm signal to turn on udrv when the output voltage falls below the lower threshold (10mv below v ss ) and terminates the pfm signal when the output voltage rises over the higher threshold (5mv above v ss ). i load dis () v in v out () v out 2 f sw l out v vin ------------------------------------------------- - = (6) figure 5. transitioning between pwm and hysteresis pwm mode hysteretic mode hysteretic mode pwm mode 12345678 v core i l 0 v core i l 0 1 23 4 56 7 8
FAN5250 10 rev. 1.1.5 7/24/02 the switching frequency is primarily a function of: 1. spread between the two hysteretic thresholds 2. i load 3. output inductor and capacitor esr a transition back to pwm (continuous conduction mode or ccm) mode occurs when the inductor current has risen suf?ient as to be positive for 8 consecutive cycles. this occurs when: where ? v hysteresis = 15mv and esr is the equivalent series resistance of c out . because of the different control mechanisms, the value of the load current where transition into ccm operation takes place is typically higher compared to the load level at which transi- tion into hysteretic mode had occurred. hysteretic mode can be disabled by setting the fpwm pin low. the presence of this pin enhances applicability of the controller. figure 6 shows an application circuit where hysteretic mode is only allowed in a deep sleep extension (dsx) mode. in this mode the cpu has stopped and its current is signi?antly lower compared to other modes of operation. using the fpwm pin simpli?s control over converter modes of opera- tion and increases ef?iency. current processing section the following discussion refers to figure 7. active droop active droop?or voltage positioning is now widely used in the computer power applications. the technique is based on raising the converter voltage at light load in anticipation of a step increase in load current, and conversely, lowering v core in anticipation of a step decrease in load current. with active droop, the output voltage varies with the load as if a resistor were connected in series with the converters out- put, in other words, it's effect is to raise the output resistance of the converter. to get the most from the active droop, its magnitude should be scaled to match the output capacitors esr voltage drop. active droop allows the size and cost of the output capaci- tors required to handle cpu current transients to be reduced. the reduction may be almost a factor of 2 when compared to a system without active droop. figure 6. allowing hysteretic mode in deep sleep i load ccm () ? v hysteresis 2 esr ---------------------------------------- - = (7) v droop i max esr = (8) start dsx altv 6 r8 r7 5 fpwm figure 7. current limit and active droop circuits ldrv 22 pgnd q2 isns 21 in + in 2.5v ilim det. r sense i1a = 200k 16 ss 1.5m 14 c ss vcore+ r droop v to i ea out dac and soft start 17pf 100k 300k isns 48 i1b = isns 8 i2 = 4 * ilim 3 15 ilim 1.2v r ilim ilim mirror s/h
FAN5250 rev. 1.1.5 7/24/02 11 figure 8. active droop additionally, the cpu power dissipation is also slightly reduced as it is proportional to the applied voltage squared and even slight voltage decrease translates to a measurable reduction in power dissipated. figure 9. effect of active droop on esr the crusoe ? processor regulation window including transients is speci?d as +5%2%. to accommodate the droop, the output voltage of the converter is raised by about 3.25% at no load as shown below (r24 = 1k and r25 = 30.1k): figure 10. setting the no-load output voltage rise the converter response to the load step is shown in figure 11. at zero load current, the output voltage is raised ~50mv above nominal value of 1.35v. when the load current increases, the output voltage droops down approximately 55mv. due to use of active droop, the converters output voltage adaptively changes with the load current allowing better utilization of the regulation window. figure 11. converter response to 5a load step the current through r sense resistor (isns) is sampled shortly after q2 is turned on. that current is held, and then injected (with a 1/48 gain) into the inverting path of the error amp to produce an offset to the sensed output voltage at v core + proportional to the load current. setting the current limit a ratio of isns is also compared to the current established when a 1.2 v internal reference drives the ilim pin. the threshold is determined at the point when the since therefore, since the tolerance on the current limit is largely dependent on the ratio of the external resistors it is fairly accurate if the voltage drop on the switching node side of r sense is an accurate representation of the load current. when using the mosfet as the sensing element, the variation of r ds(on) causes proportional variation in the isns. this value not only varies from device to device, but also has a typical junction temperature coef?ient of about 0.4%/? (consult the mosfet datasheet for actual values), so the actual current limit set point will decrease proportional to increasing mosfet die temperature. the same discussion applies to the v droop calculation, which has an additional initial error of ?0% due to its value being determined by a ratio between r sense and the internal 100k resistor. 1.2 v core i load v droop i max v esr upper lim lower lim iload vout (no droop) vout droop esr upper lim lower lim v esr 16 vcore+ v core r24 r25 c out 1 2 i cpu = 0a...5.0a lower limit v cpu = 1.35v upper limit ch2 2.0a m50 s ch1 50mv v droop 100k i load r ds on () 48 r sense -------------------------------------------- = v droop 2083 i load r ds on () r sense -------------------------------------------- = (9a) (9b) isns 8 -------------- - ilim 4 3 --------------------- - > isns i load r ds on () r sense -------------------------------------------- = i limit 1.2v r lim ------------ - 4 3 -- - 8 100 r sense + () r ds on () ---------------------------------------------------- = (10)
FAN5250 12 rev. 1.1.5 7/24/02 figure 12. improving current sensing accuracy more accurate sensing can be achieved by using a resistor (r1) instead of the rdson of the fet as shown in figure 12. this approach causes higher losses, but yields greater accuracy in both v droop and i limit . r1 is a low value (e.g. 10m ? ) resistor. current limit (i limit ) should be set suf?iently high as to allow the output slew rate required by the design, since the output capacitors will have to be charged during this slew. the dv/dt term we used earlier in the discussion (set up by the c ss ) was 50mv/32 s or 1.56v/ms. in addition, since i limit is a peak current cut-off value, we will need to multi- ply the result by the inductor ripple current (we'll use 30%). assuming c out of 1000 f, and a maximum load current of 6a the target for i limit would be: gate driver section the gate control logic translates the internal pwm control signal into the mosfet gate drive signals providing necessary ampli?ation, level shifting and shoot-through protection. also, it has functions that help optimize the ic performance over a wide range of operating conditions. since mosfet switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower mosfets. the lower mosfet drive is not turned on until the gate-to-source voltage of the upper mosfet has decreased to less than approximately 1 volt. similarly, the upper mosfet is not turned on until the gate-to-source voltage of the lower mosfet has decreased to less than approximately 1 volt. this allows a wide variety of upper and lower mosfets to be used without a concern for simultaneous conduction, or shoot-through. there must be a low ?resistance, low ?inductance path between the driver pin and the mosfet gate for the adap- tive dead-time circuit to work properly. any delay along that path will subtract from the delay generated by the adaptive dead-time circuit and a shoot-through condition may occur. frequency loop compensation due to the implemented current mode control, the modulator has a single pole response with -1 slope at frequency determined by load where r o is load resistance, c o is load capacitance. for this type of modulator type 2 compensation circuit is usually suf?ient. to reduce the number of external components and simplify the design task, the pwm controller has an inter- nally compensated error ampli?r. figure 13 shows a type 2 ampli?r and its response along with the responses of a cur- rent mode modulator and of the converter. the type 2 ampli- ?r, in addition to the pole at the origin, has a zero-pole pair that causes a ?t gain region at frequencies between the zero and the pole. figure 13. compensation this region is also associated with phase ?ump or reduced phase shift. the amount of phase shift reduction depends on how wide the region of ?t gain is and has a maximum value of 90? to further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feed-forward of vin to the oscillator ramp. the zero frequency, the ampli?r high frequency gain and the modulator gain are chosen to satisfy most typical appli- cations. the crossover frequency will appear at the point where the modulator attenuation equals the ampli?r high ldrv 22 pgnd isns 21 r sense r1 q2 i limit i load > c out dv dt ------ - + (11a) i limit 1.3 6a 1mf 1.56v ms ? () + () 13a > (11b) f p0 1 2 r o c o ----------------------- - = (12) r1 r2 ea out c1 c2 ref v in converter 0 14 18 modulator f p0 f z f p error amp f z 1 2 r 2 c 1 --------------------- - 6 khz == f p 1 2 r 2 c 1 --------------------- - 600 khz == (13a) (13b)
FAN5250 rev. 1.1.5 7/24/02 13 frequency gain. the only task that the system designer has to complete is to specify the output ?ter capacitors to position the load main pole somewhere within one decade lower than the ampli?r zero frequency. with this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase ?oost? conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output ?ter capacitance. in this case, the esr zero placed within the 10khz...50khz range gives some additional phase ?oost? fortunately, there is an oppo- site trend in mobile applications to keep the output capacitor as small as possible. protection the converter output is monitored and protected against extreme overload, short circuit, over-voltage and under-voltage conditions. a sustained overload on the output sets the pgood pin low and latches-off the whole chip. operation can be restored by cycling the vcc voltage or enabling (en) pin. over-current sensing when the circuit's current limit signal (?lim det?as shown in figure 7) goes high, a pulse-skipping circuit is activated. hdrv will be inhibited as long as the sensed current is higher than the ilim value. this limits the current supplied by the dc input. this condition continues for 8 clock cycles after the over-current comparator was tripped for the ?st time. if after these ?st 8 clock cycles the current exceeds the over-current threshold again at any time within the subse- quent 8 clock cycles, the overcurrent protection circuit is latched and the chip is disabled. if "ilim det" goes away during the ?st 8 clock cycles, normal operation is restored and the over-current circuit resets itself 16 clock cycles after the over-current threshold was exceeded for the ?st time. if the load step is strong enough to pull the v core + lower than the under-voltage threshold, the chip shuts down immediately. over-voltage protection should the output voltage exceed 1.9v due to an upper mosfet failure, or for other reasons, the overvoltage protection comparator will force the ldrv high. this action actively pulls down the output voltage and, in the event of the upper mosfet failure, will eventually blow the battery fuse. as soon as the output voltage drops below the threshold, the ovp comparator is disengaged. this ovp scheme provides a ?oft crowbar function which helps to tackle severe load transients and does not invert the output voltage when activated ?a common problem for ovp schemes with a latch. over-temperature protection the chip incorporates an over temperature protection circuit that shuts the chip down when a die temperature of 150?c is reached. normal operation is restored at die temperature below 125? with internal power on reset asserted, resulting in a full soft-start cycle. design and component selection guidelines as an initial step, de?e operating voltage range and mini- mum and maximum load currents for the controller. output inductor selection the minimum practical output inductor value is the one that keeps inductor current just on the boundary of continuous conduction at some minimum load. the industry standard practice is to choose the minimum current somewhere from 15% to 35% of the nominal current. at light load, the con- troller can automatically switch to hysteretic mode of opera- tion to sustain high ef?iency. the following equations help to choose the proper value of the output ?ter inductor. where ? i is the inductor ripple current and ? v out is the maximum ripple allowed. for this example we'll use: therefore, ch1 5.0v ch3 2.0a ? ch2 100mv m 10.0 s shutdown 1 2 3 vout 8 clk il pgood ? i2 = i min ? v out esr ------------------ = l v in v out f sw ? i ----------------------------- - v out v in -------------- = v in 20v v out 1v = , = ? i30% = 5a 1.25a = f sw 300khz = l 1.8 h
FAN5250 14 rev. 1.1.5 7/24/02 output capacitor selection the output capacitor serves two major functions in a switch- ing power supply. along with the inductor it ?ters the sequence of pulses produced by the switcher, and it supplies the load transient currents. the ?tering requirements are a function of the switching frequency and the ripple current allowed, and are usually easy to satisfy in high frequency converters. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. modern microprocessors produce transient load rates in excess of 10a/ s. high frequency ceramic capacitors placed beneath the processor socket initially supply the transient and reduce the slew rate seen by the bulk capacitors. the bulk capacitor values are generally determined by the total allowable esr rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the processor power pins as physically possible. consult with the processor manufacturer for speci? decou- pling requirements. use only specialized low-esr electro- lytic capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitors esr will deter- mine the output ripple voltage and the initial voltage drop after a transient. in most cases, multiple electrolytic capaci- tors of small case size perform better than a single large case capacitor. power mosfet selection for the example in the following discussion, we will be selecting components for: v in from 5v to 20v v out = 1.2v @ i load(max) = 7a the FAN5250 converter's output voltage is very low with respect to the input voltage, therefore the lower mosfet (q2) is conducting the full load current for most of the cycle. therefore, q2 should be selected to be a mosfet with low r ds(on) to minimize conduction losses. in contrast, q1 is on for a maximum of 20% (when v in = 5v) of the cycle, and its conduction loss will have less of an impact. q1, however, sees most of the switching losses, so q1s primary selection criteria should be gate charge (q g(sw) ). high-side losses: figure 14. switching losses and q g figure 15. drive equivalent circuit assuming switching losses are about the same for both the rising edge and falling edge, q1s switching losses, as can be seen by figure 14, are given by: where r ds(on) is @t j(max) and t s is the switching period (rise or fall time) and is predominantly the sum of t2, t3 (figure 14), a function of the impedance of the driver and the q g(sw) of the mosfet. since most of t s occurs when v gs = v sp we can use a constant current assumption for the driver to simplify the calculation of t s : v sp t1 t2 t3 4.5v t4 t5 q g(sw) v ds i d q gs q gd v th v gs c iss c rss c iss c iss = c gs || c gd c gd r d g r gate c gs 19 hdrv 5v 20 sw vin p upper p sw = p cond + p sw v ds i l 2 --------------------- 2t s ?? ?? f sw = p cond v out v in -------------- i out 2 r ds on () = (14a) (14b) (14c) t s q gsw () i driver -------------------- - q gsw () vdd v sp r driver r gate + ------------------------------------------------ ?? ?? ----------------------------------------------------- - = (15)
FAN5250 rev. 1.1.5 7/24/02 15 for the high-side mosfet, v ds = vin, which can be as high as 20v in a typical portable application. q2, however, switches on or off with its parallel shottky diode conducting, therefore v ds 0.5v. since p sw is proportional to v ds , q2's switching losses are negligible and we can select q2 based on r ds(on) only. care should also be taken to include the delivery of the mosfet's gate power (p gate ) in calculating the power dissipation required for the FAN5250: low-side losses conduction losses for q2 are given by: where r ds(on) is the r ds(on) of the mosfet at the highest operating junction temperature and is the minimum duty cycle for the converter. since d min is 5% for portable computers, (1-d) 1, further simplifying the calcu- lation. the maximum power dissipation (p d(max) ) is a function of the maximum allowable die temperature of the low-side mosfet, the j-a , and the maximum allowable ambient temperature rise: j-a , depends primarily on the amount of pcb area that can be devoted to heat sinking (see fsc app note an-1029 for so-8 mosfet thermal information). table 2. suggested component values layout considerations switching converters, even during normal operation, pro- duce short pulses of current which could cause substantial ringing and be a source of emi if layout constrains are not observed. there are two sets of critical components in a dc-dc converter. the switching power components process large amounts of energy at high rate and are noise generators. the low power components responsible for bias and feedback functions are sensitive to noise. a multi-layer printed circuit board is recommended. dedicate one solid layer for a ground plane. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. notice all the nodes that are subjected to high dv/dt voltage swing such as sw, hdrv and ldrv, for example. all surrounding circuitry will tend to couple the signals from these nodes through stray capacitance. do not oversize copper traces connected to these nodes. do not place traces connected to the feedback components adjacent to these traces. it is not recommended to use high density interconnect systems, or micro-vias on these signals. the use of blind or buried vias should be limited to the low current signals only. the use of normal thermal vias is left to the discretion of the designer. keep the wiring traces from the ic to the mosfet gate and source as short as possible and capable of handling peak cur- rents of 2a. minimize the area within the gate-source path to reduce stray inductance and eliminate parasitic ringing at the gate. locate small critical components like the soft-start capacitor and current sense resistors as close as possible to the respec- tive pins of the ic. the FAN5250 utilizes advanced packaging technology that will have lead pitch of 0.6mm. high performance analog semiconductors utilizing narrow lead spacing may require special considerations in pwb design and manufacturing. it is critical to maintain proper cleanliness of the area sur- rounding these devices. it is not recommended to use any type of rosin or acid core solder, or the use of ?x in either the manufacturing or touch up process as these may contrib- ute to corrosion or enable electromigration and/or eddy cur- rents near the sensitive low current signals. when chemicals such as these are used on or near the pwb, it is suggested that the entire pwb be cleaned and dried completely before applying power. design 1 design 2 design 3 i cpu(max) 6 a 12 a 18 a inductor 1.8h sumida cep1231r8mh 1.0h panasonic etqp6f1r0bfa 0.8h panasonic etqp6f0r8bfa output caps 4 x 220f sanyo poscap 2r5tpc220m or 3 x 270f panasonic eefue271r 6 x 220f sanyo poscap 2r5tpc220m or 5 x 270f panasonic eefue271r 6 x 270f panasonic eefue271r high-side mosfets fds6612a fds6694 fds6694 low-side mosfets fds6690s 2 x fds6672a 2 x fds7764a r sns for 3% droop 3.57k 2.8k 3k p gate q g vdd f sw = (16) (17) p cond 1d () i out 2 r ds on () = d v out v in -------------- = p d max () t j max () t a max () ja ------------------------------------------------ - =
FAN5250 16 rev. 1.1.5 7/24/02 mechanical dimensions mqa24 24-lead quarter size outline package (qsop), jedec mo-137, 0.150" wide package number mqa24
FAN5250 7/24/02 0.0m 003 stock#ds30005250 ? 2001 fairchild semiconductor corporation life support policy fairchild s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. ordering information part number temperature range package FAN5250qsc -10 c to 85 c qsop-24

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