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toshiba toshiba corporation 1 tlcs-900 series TMP96C031N/f the information contained here is subject to change without notice. the information contained herein is presented only as guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. these toshiba products are intended for usage in general electronic equipments (of?e equipment, communication equipment, measuring equipment, domestic electri?ation, etc.) please make sure that you consult with us before you use these toshiba products in equip- ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traf? signal, combustion control, all types of safety devices, etc.). toshiba cannot accept liability to any damage which may occur in case these toshiba products were used in the mentioned equipments without prior consultation with toshiba. (3) external memory expansion can be expanded up to 16m-bytes (for both programs and data). external data bus width selection pin (am8/16 ) can mix 8- and 16-bit external data buses. ? dynamic data bus sizing (4) 8-bit timer: 2 channels (5) 16-bit timer: 2 channels (6) pattern generator: 4 bits, 2 channels (7) serial interface: 2 channels (8) 8-bit a/d converter: 4 channels (9) dram controller (10) watchdog timer (11) chip select/wait controller: 4 blocks (12) interrupt functions 3 cpu interrupts ? ? swi instruction, privileged violation, and illegal instruction 12 internal interrupts 9 external interrupts (13) i/o ports: 37 pins (14) standby function : 3 halt modes (run, idle, stop) 7-level priority can be set. cmos 16-bit microcontrollers TMP96C031N/tmp96c031f 1. outline and device characteristics the tmp96c031 are high-speed advanced 16-bit microcon- trollers developed for controlling medium to large-scale equip- ment. TMP96C031N comes in a 64-pin shrink dip; the tmp96c031f, in a 64-pin ?t package. (1) original 16-bit cpu tlcs-90 instruction mnemonic upward compatible. 16m-byte linear address space general-purpose registers and register bank system 16-bit multiplication/division and bit transfer/arithmetic instructions high-speed micro dma - 4 channels (1.6 m s/2 bytes @ 20mhz) (2) minimum instruction execution time - 200ns @ 20mhz
2 toshiba corporation TMP96C031N/f figure 1. tmp96c031f block diagram
toshiba corporation 3 TMP96C031N/f 2. pin assignment and functions 2.1 pin assignment figure 2.1 shows pin assignment of TMP96C031N. figure 2.1 (1). pin assignment (64-sdip) figure 2.1 (2) shows pin assignment of tmp96c031f. figure 2.1 (2). pin assignment (64qfp)
4 toshiba corporation TMP96C031N/f 2.2 pin names and functions the names of input/output pins and their functions are described below. note: the internal i/o of this device cannot be accessed using the external dma controller. table 2.2. pin names and functions pin name number of pins i/o functions ad0 ~ ad7 8 tri-state address/data (lower): 0 - 7 for address/data bus ad8 ~ ad15 a8 ~ a15 8 tri-state output address data (upper): 8 - 15 for address/data bus address: 8 to 15 for address bus p20 ~ p27 a0 ~ a7 a16 ~ a23 8 i/o output output port 2: i/o port that allows selection of i/o on a bit basis (with pull-down resistor) address: 0 - 7 for address bus address: 16 - 23 for address bus p30 to5 hwr 1 i/o output output port 30: output port (with pull-up register) timer output 5: timer 4 output pin high write: strobe signal for writing data on pins ad8 - 15 p31 ti0 w ait 1 i/o output output port 31: output port (with pull-up register) timer output 0: timer 0 input write: pin used to request cpu bus wait p32 busrq 1 i/o input port 32: i/o port (with pull-up register) bus request: signal used to request high impedance for ad0 - 15, a0 - 23, rd , wr , hwr , r/w , ras , cs0 , cs1 , and cs2 pins. (for external dmac) p33 busak 1 i/o input port 33: i/o port (with pull-up register) bus acknowledge: strobe indicating that ad0 - 15, a0 - 23, rd , wr , hwr , r/w , ras , cs0 , cs1 , and cs2 pins are at high impedance after receiving busrq. p34 r/w nmi 1 i/o output input port 34: i/o (with pull-up register) read/write: 1 represents read or dummy cycle 0, write cycle. non-maskable interrupt request pin; interrupt request pin with falling edge. can also be operated at rising edge by program. p35 ras int7 1 i/o output input port 35: i/o (with pull-up register) row address strobe: outputs ras strobe for dram. interrupt request pin 7: interrupt request pin with rising edge. p40 cs0 1 output output port 40: i/o port chip select 0: outputs 0 when address is within speci?d address area. p41 cs1 1 output output port 41: output port chip select 1: outputs 0 if address is within speci?d address area. p42 cs2 1 output output port 42: output port chip select 2: outputs 0 if address is within speci?d address area. p43 cs3 cas 1 output output output port 43: output port chip select 3: outputs 0 if address is within speci?d address area. column address strobe 2: outputs cas strobe for dram if address is within speci?d address area. p50 ~ p53 an0 ~ an3 int1 ~ int3 4 input input input port 50 ~ 53: input port analog input: input to a/d converter interrupt request pin 0: interrupt request pin with programmable level/rising edge. interrupt request pin 1: interrupt request pin with programmable rising/falling edge. interrupt request pin 2 ~ 3: interrupt request pin with rising edge. p60 txd0 pg00 1 i/o output output port 60: i/o port serial send data 0 pattern generator port 00 p61 rxd0 pg01 1 i/o output output port 61: i/o port serial receive data 0 pattern generator port 01
toshiba corporation 5 TMP96C031N/f note: pull-up/pull-down resistor can be released from the pin by software. pin name number of pins i/o functions p62 cts0 pg02 1 i/o output output port 62: i/o port serial data send enable 0 (clear to send) pattern generator port 02 p63 rfsh pg03 1 i/o output output port 63: i/o port refresh out: this is a state signal output pin which indicates that the dram controller is in refresh cycle. pattern generator port 03 p64 pg10 1 i/o output port 64: i/o port pattern generator port 10 p65 pg11 1 i/o output port 65: i/o port pattern generator port 11 p66 int6 pg12 1 i/o input output port 66: i/o port interrupt request pin 6: interrupt request pin with rising edge. pattern generator port 12 p67 wdtout pg13 1 i/o output output port 71: i/o port watchdog timer output pin pattern generator port 13 p70 to1 to4 1 i/o output output port 70: i/o port timer output 1: timer 0 or 1 output pin timer output 4: timer 4 output pin p71 t03 dmux 1 i/o output output port 71: i/o port timer output 3: timer 2 or timer 3 output pin dram address multiplexor: this pin outputs row address, column address, and selector select signal. p72 int4 ti4 1 i/o input input port 72: i/o port interrupt request pin 4: interrupt request pin with programmable rising/falling edge. timer input 4: timer 4 count/capture trigger signal input p73 int5 ti5 1 i/o input input port 73: i/o port interrupt request pin 5: interrupt request pin with programmable rising edge. timer input 5: timer 4 count/capture trigger signal input p74 txd1 1 i/o output port 74: i/o port serial send data 1 p75 rxd1 1 i/o input port 75: i/o port serial receive data 1 p76 sclk1 1 i/o i/o port 76: i/o port serial clock i/o 1 clk 1 output clock output: outputs x1 ? 4 clock. pulled-up during reset. rd 1 output read: strobe signal for reading external memory. wr 1 output write: strobe signal for writing data on pins ad0 - 7. am8/16 1 input address mode: external data bus width selection pin. set to ??for ?ed external 16-bit bus or for mixed external 8/16 bit bus and to ??for ?ed external 8-bit bus. reset 1 input reset: initializes lsi. (with pull-up resistor) ale 1 output address latch enable x1/x2 1 i/o oscillator connecting pin vcc 1 power supply pin (-5v) vss 1 gnd pin (0v)
6 toshiba corporation TMP96C031N/f 3. operation this section describes in blocks the functions and basic opera- tions of the tmp96c031f device. check the chapter guidelines and restrictions for proper care of the device. 3.1 cpu the tmp96c031f device has a built-in high-performance 16- bit cpu. (for cpu operation, see tlcs-900 cpu in the book core manual architecture user manual.) this section describes cpu functions unique to tmp96c031f that are not described in the previous section. 3.1.1 reset to reset the tmp96c031f, the reset input must be kept at 0 for at least 10 system clocks (10 states: 1 m s with a 20mhz system clock) within an operating voltage range and with a sta- ble oscillation. when reset is accepted, the cpu sets as follows: program counter (pc) to 8000h. stack pointer (xsp) for system mode to 100h. sysm bit of status register (sr) to 1. (sets to system mode.) iff2 to 0 bits of status register to 111. (sets mask register to interrupt level 7.) max bit of status register to 0. (sets to minimum mode.) bits rfp2 to 0 of status register to 000. (sets register banks to 0.) when reset is released, instruction execution starts from address 8000h. cpu internal registers other than the above are not changed. when reset is accepted, processing for built-in i/os, ports, and other pins is as follows: initializes built-in i/o registers as per specifications. sets port pins (including pins also used as built-in i/os) to general-purpose input/output port mode (sets i/o ports to input ports). sets the wdtout pin to 0. (watchdog timer is set to enable after reset.) pulls up the clk pin to 1. sets the ale pin to 0. 3.1.2 external data bus width selection pin (am8/16 ) the tmp96c031f automatically operates in 8-bit bus/16-bit bus mode after reset depending on how the am8/16 pin is set. the tmp96c031f have altogether the following 23 inter- rupt sources: for mixed external 8/16-bit data bus or fixed 16-bit data bus set this pin to ?? then the ad8 to 15/a8 to 15 pins are fixed to functions ad8 to 15. the external data bus width is set by the chip select/wait control register described in section 3.6.1. for fixed external 8-bit data bus set this pin to ?? then the ad8 to 15/a8 to 15 pins are fixed to functions a8 to 15. the value of chip select/wait control register bit 4 (, , , ) described in section 3.6.1 is ignored and the bus is fixed external 8-bit data bus.
toshiba corporation 7 TMP96C031N/f 3.2 memory map figure 3.2 is a memory map of the tmp96c031f. note: the start address after reset is 8000h. resetting sets the stack pointer (xsp) on the system mode side to 100h. figure 3.2. memory map
8 toshiba corporation TMP96C031N/f 3.3 interrupts tlcs-900 interrupts are controlled by the cpu interrupt mask ?p-?p (iff2 to 0) and the built-in interrupt controller. tmp96c031f have altogether the following 24 interrupt sources: interrupts from the cpu 3 (software interrupts, privileged violations, and illegal (unde?ed) instruction execution) interrupts from external pins (nmi, int0, and int0 to 7) 9 interrupts from built-in i/os 12
toshiba corporation 9 TMP96C031N/f a ?ed individual interrupt vector number is assigned to each interrupt source; six levels of priority (variable) can also be assigned to each maskable interrupt. non-maskable interrupts have a ?ed priority of 7. when an interrupt is generated, the interrupt controller sends the value of the priority of the interrupt source to the cpu. when more than one interrupt is generated simulta- neously, the interrupt controller sends the value of the highest priority (7 for non-maskable interrupts is the highest) to the cpu. the cpu compares the value of the priority sent with the value in the cpu interrupt mask register (iff2 to 0). if the value is greater than that of the cpu interrupt mask register, the interrupt is accepted. the value in the cpu interrupt mask reg- ister (iff2 to 0) can be changed using the ei instruction (con- tents of the ei num/iff <2:0> = num). for example, programming ei 3 enables acceptance of maskable interrupts with a priority of 3 or greater, and non-maskable interrupts which are set in the interrupt controller. the di instruction (iff <2:0> = 7) operates in the same way as the ei 7 instruction. since the priority values for maskable interrupts are 0 to 6, the di instruction is used to disable maskable interrupts to be accepted. the ei instruction becomes effective immediately after execution. (with the tlcs-90, the ei instruction becomes effective after execution of the subsequent instruction.) in addition to the general-purpose interrupt processing mode described above, there is also a high-speed m dma pro- cessing mode. high-speed m dma is a mode used by the cpu to automatically transfer byte or word data. it enables the cpu to process interrupts such as data saves to built-in i/os at high speed. figure 3.3 (1) is a ?wchart showing overall interrupt processing.
10 toshiba corporation TMP96C031N/f figure 3.3 (1). interrupt processing flowchart
toshiba corporation 11 TMP96C031N/f 3.3.1 general-purpose interrupt processing when accepting an interrupt, the cpu operates as follows: (1) the cpu reads the interrupt vector from the interrupt controller. when more than one interrupt with the same level is generated simultaneously, the interrupt controller generates interrupt vectors in accordance with the default priority (which is ?ed as follows: the smaller the vector value, the higher the priority), then clears the inter- rupt request. (2) the cpu pushes the program counter and the status register to the system stack area (area indicated by the system mode stack pointer). (3) the cpu sets a value in the cpu interrupt mask register that is higher by 1 than the value of the accepted interrupt level. however, if the value is 7, 7 is set without an increment. (4) the cpu sets the ?g of the status register to 1 and enters the system mode. (5) the cpu jumps to address 8000h + interrupt vector, then starts the interrupt processing routine. the table below shows the number of execution states for the above processing times. to return to the main routine after completion of the inter- rupt processing, the reti instruction is usually used. executing this instruction restores the contents of the program counter and the status registers. though acceptance of non-maskable interrupts cannot be disabled by program, acceptance of maskable interrupts can. a priority can be set for each source of maskable inter- rupts. the cpu accepts an interrupt request with a priority higher than the value in the cpu mask register . the cpu mask register is set to a value higher by 1 than the priority of the accepted interrupt. thus, if an inter- rupt with a level higher than the interrupt being processed is generated, the cpu accepts the interrupt with the higher level, causing interrupt processing to nest. the cpu does not accept an interrupt request of the same level as that of the interrupt being processed. resetting initializes the cpu mask registers to 7; therefore, maskable interrupts are disabled. the addresses 008000h to 0081ffh (512 bytes) of the tlcs-900 are assigned for interrupt processing entry area. bus width of stack area interrupt processing state number max mode min mode 8-bit 23 19 16-bit 17 15
12 toshiba corporation TMP96C031N/f table 3.3 (1) tmp96c031f interrupt table default priority type interrupt source vector value ? start address high-speed micro dma start to vector 1 non- maskable reset , or swi0 instruction 0000h 8000h 2 intprev: privileged violation, or swi1 0010h 8010h 3 intundef: illegal instruction, or swi2 0020h 8020h 4 swi 3 instruction 0030h 8030h 5 swi 4 instruction 0040h 8040h 6 swi 5 instruction 0050h 8050h 7 swi 6 instruction 0060h 8060h 8 swi 7 instruction 0070h 8070h 9 nmi pin 0080h 8080h 08h 10 intwd: watchdog timer 0090h 8090h 09h 11 maskable into pin 00a0h 80a0h 0ah 12 int4 pin 00b0h 80b0h 0bh 13 int5 pin 00c0h 80c0h 0ch 14 int6 pin 00d0h 80d0h 0dh 15 int7 pin 00e0h 80e0h 0eh - (reserved) 00f0h 80f0h 0fh 16 intt0: 8-bit timer 0 0100h 8100h 10h 17 intt1: 8-bit timer 1 0110h 8110h 11h 18 intt2: 8-bit timer 2/pwm0 0120h 8120h 12h 19 intt3: 8-bit timer 3/pwm1 0130h 8130h 13h 20 inttr4: 16-bit timer 4 (treg4) 0140h 8140h 14h 21 inttr5: 16-bit timer 4 (treg5) 0150h 8150h 15h 22 (reserved) 0160h 8160h 16h 23 (reserved) 0170h 8170h 17h 24 intrx0: serial receive (channel.0) 0180h 8180h 18h 25 inttx0: serial send (channel.0) 0190h 8190h 19h 26 intrx1: serial receive (channel.1) 01a0h 81a0h 1ah 27 inttx1: serial send (channel.1) 01b0h 81b0h 1bh 28 intad: a/d conversion completion 0 1 c 0 h 81c0h 1ch 29 int1 pin 01d0h 81d0h 1dh 30 int2 pin 01e0h 81e0h 1eh 31 int3 pin 01f0h 81f0h 1fh 3.3.2 high-speed m dma in addition to the conventional interrupt processing, the tlcs- 900 also has a high-speed m dma function. when an interrupt is accepted, in addition to an interrupt vector, the cpu receives data indicating whether processing is high-speed m dma mode or general-purpose interrupt. if high-speed m dma mode is requested, the cpu performs high-speed m dma processing. the tlcs-900 can process at very high speed com- pared with the tlcs-90 m dma because it has transfer param- eters in dedicated registers in the cpu. since those dedicated registers are assigned as cpu control registers, they can only be accessed by the ldc (privileged) instruction.
toshiba corporation 13 TMP96C031N/f (1) high-speed m dma operation high-speed m dma operation starts when the accepted inter- rupt vector value matches the m dma start vector value set in the interrupt controller. the high-speed m dma has four chan- nels so that it can be set for up to four types of interrupt source. when a high-speed m dma interrupt is accepted, data is automatically transferred from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented. if the value in the counter after decrementing is other than 0, high-speed m dma process- ing is completed. if the value in the counter after decrementing is 0, general-purpose interrupt processing is performed. in read-only mode, which is provided for dram refresh, the value in the counter is ignored and dummy read is repeated. the 32-bit control registers are used for setting transfer source/destination addresses. however, the tlcs-900 has only 24 address pins for output. a 16m-byte space is available for the high-speed m dma. also in normal mode operation, the all address space (in other words, the space for system mode which is set by the cs/wait controller) can be accessed by high-speed m dma processing. there are two data transfer modes: one-byte mode and one-word mode. incrementing, decrementing, and ?ing the transfer source/destination address after transfer can be done in both modes. therefore data can easily be transferred between i/o and memory and between i/os. for details of transfer modes, see the description of transfer mode registers. the transfer counter has 16-bit, so up to 65536 transfers (the maximum when the initial value of the transfer counter is 0000h) can be performed for one interrupt source by high- speed m dma processing. after transferring data using the high-speed m dma and the transfer counter has been decremented to 0, the program goes to a general-purpose interrupt processing. note that after interrupt processing, when an interrupt for the same channel is generated, if the system requires resetting the transfer counter starts from 65536. the following section illustrates the high-speed m dma cycle when the transfer destination address is in inc mode. (min mode, 16-bit bus for all address areas, 0 wait). interrupt sources processed by high-speed m dma pro- cessing are those with the high-speed m dma start vectors listed in table 3.3 (1).
14 toshiba corporation TMP96C031N/f (2) register con?uration (cpu control register)
toshiba corporation 15 TMP96C031N/f (3) transfer mode register details execution time: when 16-bit bus width and 0 wait are set for the transfer destination/source address. note: n: corresponds to high-speed m dma channels 0 - 3. dmadn +/dmasn + : post-increment (increments register value after transfer.) dmadn -/dmasn - : post-decrement (decrement register value after transfer.) all address space (the space for system mode) can be accessed by high-speed m dma. do not use unde?ed codes for transfer mode control.
16 toshiba corporation TMP96C031N/f 3.3.3 interrupt controller figure 3.3.3 (1) is a block diagram of the interrupt circuits. the left half of the diagram shows the interrupt controller; the right half includes the cpu interrupt request signal circuit and the halt release signal circuit. each interrupt channel (total of 20 channels) in the inter- rupt controller has an interrupt request ?p-?p, interrupt prior- ity setting register, and a register for storing the high-speed micro dma start vector. the interrupt request ?p-?p is used to latch interrupt requests from peripheral devices. the ?p-?p is cleared to 0 at reset, when the cpu reads the interrupt channel vector after the acceptance of interrupt, or when the cpu executes an instruction that clears the interrupt of that channel (writes 0 in the clear bit of the interrupt priority setting register). for example, to clear the int0 interrupt request, set the register after the di instruction as follows. inte0ad ? ---- 0 --- zero-clears the int0 flip flop. the status of the interrupt request ?p-?p is detected by reading the clear bit. detects whether there is an interrupt request for an interrupt channel. the interrupt priority can be set by writing the priority in the interrupt priority setting register (e.g., inte0ad, inte45, etc.) provided for each interrupt source. interrupt levels to be set are from 1 to 6. writing 0 or 7 as the interrupt priority dis- ables the corresponding interrupt request. the priority of the non-maskable interrupt (nmi pin, watchdog timer, etc.) is ?ed to 7. if interrupt requests with the same interrupt level are gen- erated simultaneously, interrupts are accepted in accordance with the default priority (the smaller the vector value, the higher the priority). the interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the cpu. the cpu compares the priority value set in the status register by the interrupt request signal with the priority value sent; if the latter is higher, the interrupt is accepted. then the cpu sets a value higher than the priority value by 1 in the cpu sr . inter- rupt requests where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine. when interrupt processing is completed (after execution of the reti instruction), the cpu restores the priority value saved in the stack before the interrupt was generated to the cpu sr . the interrupt controller also has four registers used to store the high-speed other m dma start vector. these are i/o registers; unlike other dma registers (dmas, dmad, dmam, and dmac), they can be accessed in either normal or system mode. writing the start vector of the interrupt source for the m dma processing (see table 3.3 (1)), enables the correspond- ing interrupt to be processed by m dma processing. the values must be set in the m dma parameter registers (e.g., dmas and dmad) prior to the m dma processing.
toshiba corporation 17 TMP96C031N/f figure 3.3.3 (1). block diagram of interrupt controller
18 toshiba corporation TMP96C031N/f (1) interrupt priority setting register
toshiba corporation 19 TMP96C031N/f (2) external interrupt control setting of external interrupt pin functions interrupt pin name mode setting method nmi p34 falling edge iimc = 0 rising and falling edge iimc = 1 int0 p50 rising edge iimc = 0, = 1 level iimc = 1, = 1 int1 p51 rising edge iimc = 0 falling edge iimc = 1 int2 p52 rising edge iimc = 1 int3 p53 rising edge iimc = 1 int4 p72 rising edge t4mod = 0, 0 or 0, 1 or 1, 1 falling edge t4mod = 1, 0 int5 p73 rising edge int6 p66 rising edge iimc = 1 int7 p35 rising edge iimc = 1
20 toshiba corporation TMP96C031N/f (3) high-speed m dma start vector when the cpu reads the interrupt vector after accepting an interrupt, it simultaneously compares the interrupt vector with each channels m dma start vector (bits 4 to 8 of the interrupt vector). when both match, the interrupt is processed in m dma mode for the channel whose value matched. if the interrupt vector matches more than one channel, the channel with the lower channel number has a higher prior- ity. (4) notes the instruction execution unit and the bus interface unit of this cpu operate independently of each other. therefore, if the instruc- tion used to clear an interrupt request ?g of an interrupt is fetched before the interrupt is generated, it is possible that the cpu might execute the fetched instruction to clear the interrupt request ?g while reading the interrupt vector after accepting the inter- rupt. if so, the cpu would read the default vector 00a0h and start the interrupt processing from the address 80a0h. to avoid this, make sure that the instruction used to clear the interrupt request ?g comes after the di instruction.
toshiba corporation 21 TMP96C031N/f note 1: when releasing standby setting int0 to high level input mode, keep it high until interrupt processing starts. if the level drops to low, interrupt process- ing cannot be started correctly. 76543210 bit symbol wdte wdtp1 wdtp0 warm haltm1 haltm0 rescr drve read/write r/w after reset 10000000 function 1 : wdt enable 00 : 2 16 / fc 01 : 2 18 / fc 10 : 2 20 / fc 11 : 2 22 / fc detection time warming up time 0 : 2 16 /fc 1 : 2 18 /fc standby mode 00 : run mode 01 : stop mode 10 : idle mode 11 : don? care 1: connects watchdog timer output to reset pin internally. 1: drive pin even in stop mode. standby release by interrupt interrupt level standby mode interrupt mask (iff2 to 0) interrupt request level interrupt mask (iff2 to 0) > interrupt request level run can be released by any interrupt. after standby mode is released, interrupt processing starts. can only be released by int0 pin. processing resumes from address next to halt instruction. idle can only be released by nmi or int0 pin. after standby mode is released, interrupt processing starts. - stop -- wdmod (005ch) 3.4 standby function when the halt instruction is executed, the tmp96c031 enters run, idle, or stop mode depending on the contents of the halt mode setting register. (1) run: only the cpu halts; power consumption remains unchanged. (2) idle: only the built-in oscillator operates, while all other built-in circuits halt. power consumption is reduced to 1/10 or less than that during normal operation. (3) stop: all internal circuits including the built-in oscillator halt. this greatly reduces power consumption. the states of the port pins in stop mode can be set as listed in table 3.4 (1) using the i/o register wdmod bit. when stop mode is released by other than a reset, the system clock output starts after allowing some time for warm- ing up set by the warming-up counter fro stabilizing the built-in oscillator. to release stop mode by reset, it is necessary to allow the oscillator to stabilize. to release standby mode, a reset or an interrupt is used. to release idle or stop mode, only an interrupt by the nmi or int0 pin, or a reset can be used. the details are described below:
22 toshiba corporation TMP96C031N/f ? input for input mode/input pin is invalid; output mode/output pin is at high impedance. input: input enable state input: input gate in operation. fix input voltage to 0 or 1 so that input pin stays constant. output: output state pu: programmable pull-up pin. fix the pin to avoid through current since the input gate operates when a pull-up resistor is not set. pd: programmable pull-down pin. fix the pin like a pull-up pin when a pull-down resistor is not set. *: input gate disable state. no through current even if the pin is set to high impedance. note: port registers are used for controlling programmable pull-up/pull-down. if a pin is also used for an output function (e.g., to1) and the output function is speci?d, whether pull-up or pull-down is selected depends on the output function data. if a pin is also used for an input function, whether pull-up or pull-down is selected depends on the port register setting value only. table 3.4 (1) pin states in stop mode pin name i/o drve = 0 drve = 1 ad0 ~ ad7 ad0 ~ 7 ad8 ~ ad15 ad8 ~ 15 a8 ~ 15 p20 ~ p27 input mode output mode/a16 ~ 23 pd* pd* pd output p30 ~ p33 input mode output mode pd* pd* pd output p34 (r/w /nmi ) input mode output mode pu* pu* pu output nmi input input p35 (ras /int7) input mode output mode ras pu* pu* output pu output output p40 ~ p42 (cs0 ~ cs2 ) output pu* output p43 (cs3 /cas ) output cas pu* output output output p50 (an0/int0) input int0 input input input p51 ~ p53 input input p60 ~ p66 input mode output mode input output p67 (p13/wdtout ) input mode output mode wdtout output input output output p70 ~ p76 input mode output mode input output ale output ? ? clk output ? reset input input input wr output ??output rd output ??output am8/16 input input input x1 input x2 output ? ?
toshiba corporation 23 TMP96C031N/f table 3.5 (1) port function port name pin name number of pins direction r direction setting unit pin name for built-in function port2 p20 to p27 8 input/output bit a0 to a7/ a16 to a23 port3 p30 p31 p32 p33 p34 p35 1 1 1 1 1 1 input/output input/output input/output input/output input/output input/output - - - - - - bit bit bit bit bit bit to5/hwr ti0/w ait busrq busak r/w /ras ras /int7 port4 p40 p41 p42 p43 1 1 1 1 output output output output - - - - (fixed) (fixed) (fixed) (fixed) cs0 cs1 cs2 cs3 /cas port5 p50 to p53 4 input (fixed) an0 ~ an3 port6 p60 p61 p62 p63 p64 p65 p66 p67 1 1 1 1 1 1 1 1 input/output input/output input/output input/output input/output input/output input/output input/output bit bit bit bit bit bit bit bit pg00/txd0 pg01/rxd0 pg02/cts0 pg03/rsfh pg10 pg11 pg12/int6 pg13/wdtout port7 p70 p71 p72 p73 p74 p75 p76 1 1 1 1 1 1 1 input/output input/output input/output input/output input/output input/output input/output bit bit bit bit bit bit bit to1/to4 to2/dmux int4/ti4 int5/ti5 txd1 rxd1 sclk1 3.5.1 programmable pull-up/pull-down port2 has a built-in pull-down resistor and port3 and port4 have a built-in pull-up resistor. normally, their load can be turned on or off from software by setting the value of the output latch (registers p2, p3, and p4) during input mode. they can also be set in stand-by (stop) mode and the load can be turned on or off when the immediately preceding set- ting is the value of output latch in input mode or is the value of output data in output mode. table 3.5 (2) pull-up/down function setting pull-up/down programmable setting output latch output data on/off normal standby (stop) mode port2 (i/o) pull-down 0on setting enabled only in input mode setting enabled in input/ output mode 1 off port3 (i/o) pull-up 0on -- 1 off port4 (output) pull-up 0on setting disabled setting enabled only in output mode 1 off (r: - = with programmable pull-up resistor = with programmable pull-down resistor) 3.5 port functions the input/output ports of the tmp96c031f consist of a total of 37 bits. in addition to general purpose input/output port func- tions, these port pins also function as input/outputs for internal cpu and built-in i/o. table 3.5 (1) shows the function of each port pin.
24 toshiba corporation TMP96C031N/f figure 3.5 (2) shows the external bus interface when the bus release function is in use. the internal i/o of this device cannot be accessed when the bus is released. 3.5.2 bus release function the pull-up/down function explained in section 3.5.1 is also used to stabilize bus control signal at bus release. table 3.5 (2) shows pin states at bus release (busak = 0). pin name pin state at bus release port mode function mode ad0 - ad15 ad0 - ad7 (a8 ~ a15) becomes high impedance. p20 - p27 (a16 ~ 23) no status change. (does not become high impedance.) first sets all bits to low, then sets output buffer to off. internal pull-down is added regardless to output latch value. rd wr first sets all bits to high, then sets them to high impedance. p30 (hwr ) p34 (r/w ) no status change. (does not become high impedance.) first sets all bits to high, then sets output buffer to off. internal pull-down is added regardless to output latch value. p40 (cs0 ) p41 (cs1 ) p42 (cs2 ) p43 (cs3 ) no status change. (does not become high impedance.) first sets all bits to high, then sets output buffer to off. internal pull-down is added regardless to output latch value. p71 (dmux ) p63 (rfsh ) no status change. (does not become high impedance.) first sets all bits to high, then sets them to high impedance. p35 (ras ) p43 (cas ) no status change. (does not become high impedance.) no status change. (does not become high impedance.) figure 3.5 (1). external bus interface example when bus release function is in use
toshiba corporation 25 TMP96C031N/f 3.5.3 port 2 (p20 - p27) port 2 is an 8-bit general-purpose i/o port. i/o can be set on bit basis using the control register p2cr and function register p2fc. resetting resets all bits of output latch p2, control regis- ter p2cr and function register p2fc to 0. it also sets port 2 to input mode and connects a pull-down resistor. in addition to functioning as a general-purpose i/o port, port 2 also functions as an address bus (a16 to 23). figure 3.5 (2). port 2
26 toshiba corporation TMP96C031N/f figure 3.5 (3). registers for port 2
toshiba corporation 27 TMP96C031N/f 3.5.4 port 3 (p30 - p35) port 3 is a 6-bit general-purpose i/o port. i/o can be set bit by bit using control registers p3crl and p3crh. resetting sets all bits of p3 to 0; p30 to p35 to input mode and connects a pull-up resistor. in addition to functioning as a general-pur- pose i/o port, port 3 is also used for cpu control/status signal interrupt input, and timer i/o. figure 3.5 (4). port 3 (p30)
28 toshiba corporation TMP96C031N/f figure 3.5 (5). port 3 (p31, p32)
toshiba corporation 29 TMP96C031N/f figure 3.5 (6). port 3 (p33, p35)
30 toshiba corporation TMP96C031N/f (1) p34/nmi /r/w port 34 is a general-purpose i/o port, shared with non- maskable interrupt input pin (nmi ). the nmi pin is selected by the control register p3crh . by setting = <0,0>, it turns to the nmi input pin. since the nmi pin is speci?d only once, the nmi pin cannot be switched to the general-purpose port. the should be initialized to ??by resetting in order to switch to the general-purpose i/o port mode. port3 register (p34) is set to be ??when the pull-up resistor is attached. figure 3.5 (6). port 3 (p33, p34)
toshiba corporation 31 TMP96C031N/f figure 3.5 (8). port 3 registers note: there is no port/function switch register for pin p31 (tio/w ait ). for example, if pin p31 is used as an input port, data are input to 8-bit timer 0. if pin p31 is used as the w ait pin, set p3crl to 00, and bits 3 and 2 in the chip select/wait control register to 10. if pin p35 (ras /int7) is used as the int7 pin, set p3crh to 1.
32 toshiba corporation TMP96C031N/f 3.5.5 port 4 (p40 - p43) port 4 is a 4-bit output dedicated port. port 4 is also used for chip select cs0 - cs3 outputs and column address strobe cas (cs3 only) output. to select the function to be used, use function register p4fc. resetting sets the output register for p40, p41, and p42 to 1; the output register for p42 to 0; all bits in the function register to 0. p40, p41, and p43 are set to out- put ports for outputting 1; p42 to output port for outputting 0. figure 3.5 (9). port 4 (p40, p41, p43)
toshiba corporation 33 TMP96C031N/f figure 3.5 (10). port 4 (p42) figure 3.5 (11). registers for port 4 p4fc is disabled for read-modify-write. note: to select the function to be used for p43, use the b3cs register for the chip select/wait controller.
34 toshiba corporation TMP96C031N/f 3.5.6 port 5 (p50 - p53) port 5 is a 4-bit input dedicated port which is also used for analog inputs or external interrupts. figure 3.5 (11). port 5 (p50, p51, p52, p53) port 5 register figure 3.5 (12). register for port 5
toshiba corporation 35 TMP96C031N/f 3.5.7 port 6 (p60 - p67) port 6 is an 8-bit port. i/o can be set bit by bit. in addition to functioning as an i/o port, pins p60 to p67 function as follows: p60 - p63/p64 - p67: pattern generate pg0/pg1 output p60: serial channel txd0 output pin and programmable open drain function. p61: serial channel rxd0 output pin p62: serial channel cts0 output pin p63: dram controller refresh signal pin p66: external interrupt request input int6 pin p67: watchdog timer wdt output pin. set using port 6 con- trol registers. p6crl and p6crh. resetting sets control registers p6crl and p6crh to 0; all bits to input mode. figure 3.5 (13) port 6 (p60, p67)
36 toshiba corporation TMP96C031N/f figure 3.5 (14). registers for port 6 (p61, p62, p66) figure 3.5 (15). port 6 (p63, p64, p65)
toshiba corporation 37 TMP96C031N/f figure 3.5 (16). registers for port 6
38 toshiba corporation TMP96C031N/f 3.5.8 port 7 (p70 - p76) port 7 is a 7-bit general-purpose i/o port. i/o can be set bit by bit using control registers p7crl and p7crh. resetting sets all bits in p7 to 1; control registers p7crl and p7crh to 0; p70 - p76 to input mode. in addition to functioning as a gen- eral-purpose i/o port, port 7 as follows: interrupt input, timer i/o, dram address multiplex, serial channel send/receive (txd1 and rxd1), and transfer clock input (sclk1) pin. figure 3.5 (17). port 7 (p70, p71)
toshiba corporation 39 TMP96C031N/f figure 3.5 (18). port 7 (p72, p73, p75) figure 3.5 (19). port 7 (p74)
40 toshiba corporation TMP96C031N/f figure 3.5 (20). port 7 (p76)
toshiba corporation 41 TMP96C031N/f figure 3.5 (21). registers for port 7
42 toshiba corporation TMP96C031N/f 3.6 chip select/wait control the tmp96c031f has a built-in chip select/wait controller used to control chip select (cs0 - cs3 pins), wait (w ait pin), and data bus size (8 or 16 bits) for any of the three block address areas. the select pin (am8/16 ) is used to select the width of the external data bus. (see section 3.1.2, external data width select pin.) 3.6.1 control registers table 3.6 (1) shows control registers the block address areas is controlled by corresponding cs/wait control register (b0cs, b1cs, b2cs, b3cs) and start address register/address mask register (explained in section 3.6.2, address area). registers can be written to only when the cpu is in sys- tem mode. (there are two cpu modes: system and normal.) the reason is that the settings of these registers have an important effect on the system. table 3.6 (1) chip select/wait control register
toshiba corporation 43 TMP96C031N/f (1) enable control register bit 7 (b0e, b1e, b2e, and b3e) is a master bit used to specify enable ??/disable ??of the setting. resetting sets b0e, b1e, and b3e to disable ??and b2e to enable ?? (2) system only speci?ation control register bit 6 (b0sys, b1sys, b2sys, and b3sys) is used to specify enable/disable of the setting depending on the cpu operating mode (system or nor- mal). setting this bit to 0 enables setting (address space for cs , wait state, bus size, etc.) regardless of the cpu operating mode; setting it to 1 enables setting in system mode but disables setting in normal mode. resetting clears bit 6 to 0. bit 6 is mainly used when external memory data should not be accessed in normal mode (i.e., for sys- tem mode only memory data for the operating system). (3) address area speci?ation control register bit 5 (b0are, b1are, b2are, and b3are) is used to specify the target address space. when this bit is set to ??after reset, cs0 is set to addresses 7f00h to 7ffff, cs1 is set to address 80h to 7fffh, and cs2 is set to addresses 8000h to 3fffff. cs3 is unde?ed. (see 3.6.3 default address space speci?ation.) when this bit is set to ?? the target address is the address space is the address space speci?d by the memory start address register msar and memory start address mask register mamr. (see 3.6.2 address space speci?ation.) (4) data bus width select control register bit 4 (b0bus, b1bus, b2bus, b3bus) is used to specify the data bus width. when this bit is set to ?? memory is accessed in 16-bit data bus mode. when this bit is set to ?? memory is accessed in 16-bit data bus mode. however, this bit is valid only in 16-bit bus mode (am8/16 pin = ??. in 8- bit bus mode (am8/16 pin = ??, all address space is accessed in 8-bit data bus mode regardless of the value of this bit. (see 3.1.2 external data bus width selection pin.) the changing data bus width according to the address to be address to be accessed is referred to dynamic bus sizing. table 3.6 (2) shows the details of the bus operation.
44 toshiba corporation TMP96C031N/f table 3.6 (2) dynamic bus sizing xxxxx: during a read, data input to the bus is ignored. at write, the bus is at high impedance and the write strobe signal remains non-active. operand data size operand start address memory data size cpu address cpu data d15 - d8 d7 - d0 8-bit 2n + 0 (even number) 8-bit 2n + 0 xxxxx b7 - b0 16-bit 2n + 0 xxxxx b7 - b0 2n + 1 (odd number) 8-bit 2n + 1 xxxxx b7 - b0 16-bit 2n + 1 b7 - b0 xxxxx 16-bit 2n + 0 (even number) 8-bit 2n + 0 2n + 1 xxxxx xxxxx b7 - b0 b15 - b8 16-bit 2n + 0 b15 - b8 b7 - b0 2n + 1 (odd number) 8-bit 2n + 1 2n + 2 xxxxx xxxxx b7 - b0 b15 - b8 16-bit 2n + 1 2n + 2 b7 - b0 xxxxx xxxxx b15 - b8 32-bit 2n + 0 (even number) 8-bit 2n + 0 2n + 1 2n + 2 2n + 3 xxxxx xxxxx xxxxx xxxxx b7 - b0 b15 - b8 b23 - b16 b31 - b24 16-bit 2n + 0 2n + 2 b15 - b8 b31 - b24 b7 - b0 b23 - b16 2n + 1 (odd number) 8-bit 2n + 1 2n + 2 2n + 3 2n + 4 xxxxx xxxxx xxxxx xxxxx b7 - b0 b15 - b8 b23 - b16 b31 - b24 16-bit 2n + 1 2n + 2 2n + 4 b7 - b0 b23 - b16 xxxxx xxxxx b15 - b8 b31 - b24
toshiba corporation 45 TMP96C031N/f (5) wait control control register bits 3 and 2 (b0w1, 0; b1w1, 0; b2w1, 0; b3w1, 0) are used to specify the number of waits. setting these bits to 00 inserts a 2-state wait regard- less of the w ait pin status. setting them to 01 inserts a 1-state wait regardless of the w ait status. setting them to 10 inserts a 1-state wait and samples the w ait pin status. if the pin is low, inserting the wait maintains the bus cycle until the pin goes high. setting them to 11 completes the bus cycle without a wait regardless of the w ait pin status. resetting sets these bits to 00 (2-state wait mode). note: if there ia a contention between dram access and refresh when using dram, the refresh cycle is added to the speci?d wait. (6) cs/cas waveform select the b3cs register bit 1 is used to specify the mode of the waveform output from the chip select pin (cs3 /cas ) pin. when this bit is set to ?? cs3 waveform is output. when it is set to ?? cas wave- form is output. this bit is cleared to zero after reset. (7) self refresh control (described in section 3.13.1 refresh controller.) (8) wait control outside space cs0 to cs3 this bit is used to specify the number of waits when b0cs register bits 1 and 0 or space out- side cs0 to cs3 is accessed.
46 toshiba corporation TMP96C031N/f 3.6.2 address space speci?ation (b0cs to b3cs < b0are to b3are> = ?? the address space is speci?d with the start address register (msar0, msar1, msar2, and msar3) and address mask register (mamr0, mamr1, mamr2, and mamr3). for each bus cycle, the chip select controller compares the address on the bus and value of this start address register. the value of the address mask register is used to ignore result of this address comparison. when there is a match, the speci?d space is assumed to be accessed and a low strobe signal is output from the corresponding chip select pin (cs0 to cs3 ) if it is enabled (b0e to b3e = ??. figure 3.6 (1). chip select (cs0 to cs3 ) operation timing
toshiba corporation 47 TMP96C031N/f figure 3.6 (2). cs0 address decode block diagram figure 3.6 (3). cs1 address decode block diagram
48 toshiba corporation TMP96C031N/f figure 3.6 (4). cs2 , cs3 address decode block diagram (1) memory start address register memory start address register table 3.6 (3) memory start address register
toshiba corporation 49 TMP96C031N/f table 3.6 (4) memory start address mask registers
50 toshiba corporation TMP96C031N/f msar0 to 3 < s23> to correspond to addresses a23 to a16 and s15, s14 to 9, and s8 corresponding to addresses a15, a14, to 9, and a8 are ??by default. mamr0 to enable/disable comparison of value set with msar0 and address and to correspond to to , s15, s14 to 9, and s8. in addition, v21, v22, and v23 corresponding to , , and are ??by default and comparison is always enabled. example of enabling/disabling comparison (cs0 registers msar0 and msamr0) when comparison is disabled by setting = 1, the comparison of the value of and address a16 is dis- abled and the value of becomes invalid. when comparison is enabled by setting = 0, the comparison of the value of and address a16 is enabled and cs0 is enabled only when they match. cs1 , cs2 , and cs3 can be used in the same manner. (2) how to the start address the address decoder is output by specifying the start address for cs output and the space size. the start address is set every 64k-byte because it is decoded by a16 to a23 as shown in the block diagram. in other words, the dram start address is set to one of the 64k-byte intervals after ?00000h? however, note that the start address may be changed due to the value of the mamr. figure 3.6 (5). where to set start address
toshiba corporation 51 TMP96C031N/f (3) how to set the address space the address space is speci?d by setting the memory start address mask register (mamr0 to 3). as shown in the address decoder block diagram (figures 3.6 (2) to (4)), cs0 , cs1 , or cs2 /cs3 can specify the address area for which the chip select signal can be output depending on whether to compare the address a8 to a20, a8 to a21, or a15 to a22 respectively. figure 3.6 (6). chip select and space size (4) start address/address space setting procedure set memory start address mask register (mamr) (set address space) set memory start address register (msar) (set area start address) a check the identical address bit of mamr and msar example: check the value of (cs0 ) mamr0 and msar0 ? if the bits at identical address are 1 and 1, msar bit is treated as 0. <-the start address changes. example: if (cs0 ) mamr = 1 and msar = 1, comparison of address a16 and is disabled and address a16 is selected regardless of whether the value is 1 or 0 and the start address is replaced by the value in msar. ? if it is ok for the start address to change, end the set- ting procedure. if not, change the value to msar. ? reset msar and re-verify (return to step 3). (setting example) when address space is 128k-byte and start address is 30000h (area 30000h to4ffffh). set mamr = 0fh address space 128k-byte msar = 03h start address 30000h mamr and msar are 1 and 1 and the start address changes to 2000h. (space 20000h to 3ffffh). if this is not desired, change the start address. change the start address to 4000h. (space 40000h to 5ffffh). mamr = 0fh msar = 04h the bits at identical address of mamr and msar are not 1 and 1 and the start address remains unchanged. therefore, a 128k-byte space starting at address 40000h can be decoded.
52 toshiba corporation TMP96C031N/f (setting example 1) (cs0 ) when msar is set to 02h and mamr is set to 0fh, the chip select output is as shown in the following memory map. s23 to s17 are valid because v23 to v17 = ??and s16 are invalid because v16 to v8 = ??
toshiba corporation 53 TMP96C031N/f (setting example 2) (cs0 ) when msar is set to 01h and msar is set to 04h, the chip select output is as shown in the following memory map. the values of s23 - s16, and s14-s8 become valid because v23 to v16 = 0 and v14 - v8 = 0.the value of s15 becomes invalid because v15 = 1.
54 toshiba corporation TMP96C031N/f (setting example 3) (cs0 ) space where chip select is output by values set in msar and mamr (excerpt).
toshiba corporation 55 TMP96C031N/f 3.6.3 default address space speci?ation (b0cs to b2cs < b0are to b2are> = ?? the following ?ures show the actual chip select image. cs0 can specify 7f00h to 7fffh, cs1 can specify 80h to 7fffh, and cs2 can specify 8000h to 3fffffh. this is because external connection of devices (such as ram or i/o) other than rom is considered. the area 7f00 to 7fffh (256-byte space) for cs0 is mapped in this space mainly due to external i/o expansion consideration. the area 80h to 7fffh (approximately 32k-byte space) for cs1 is mapped in this space mainly due to external ram expansion consideration. the area 8000h to 3fffffh (approximately 4m-byte space) for cs2 is mapped in this space mainly due to external rom expansion consideration. supplement 1: the access priority is in the order of built-in i/o and chip select/wait controller. supplement 2: wait for spaces other than cs0 to cs3 is set with b0cs register and the data bus width is ?ed to 16-bit if the am8/16 pin is ?? and to 8 bits if it is ?? note: when using the chip select/wait controller, do not assign multiple de?itions to the same address area. (however, if cs0 is set to 7f000h to 7fffh and cs1 is set to 80h to 7fffh, only the cs0 setting/pin is active in the overlapped address space 7f00h to 7fffh.) when the bus is opened (busak = ??, cs0 to cs3 pins are also opened (output buffer off). refer to the note on bus open in section ?.5 port functions?for the pin status at this point. cs0 cs1 cs2 7f00h 80h 8000h 8000h 8000h 3fffffh ffffffh ffffffh ffffffh (mainly for i/o) (mainly for ram) (mainly for rom)
56 toshiba corporation TMP96C031N/f 3.6.4 example of usage (1) connection example 1 figure 3.6 (6) is an example (1) in which an external memory is connected to the tmp96c031f. in this example, a rom is connected using 16-bit bus; a ram is connected using 8-bit bus. figure 3.6 (7). example of external memory connection (rom = 16-bit, ram and i/o = 8-bit) after a reset, the cs0 - cs3 pins are set to output port mode; 1 is output from cs0 , cs1 , and cs3 ; 0 from cs2 . the program used to set these pins is as follows:
toshiba corporation 57 TMP96C031N/f p4fc equ 10h b0cs equ 68h b1cs equ 69h b2cs equ 6ah b3cs equ 6bh msar3 equ 46h mamr3 equ 47h ld (bocs), 10010000b ; cs0 = 8-bit, 2wait, 7f00h ~ 7fffh, 2wait other than in cs0 ~ cs3 areas ld (b1cs), 100111xxb ; cs1 = 8-bit, 0wait, 80h ~ 7fffh ld (b2cs), 100001xxb ; cs2 = 16-bit, 1wait, 8000h ~ 3fffffh ld (b3cs), 10111100b ; cs3 = 8-bit, 0wait, address area speci?ation (400000h ~ 407fffh) ld (msar3), 01000000b ; cs3 start address: 400000h ld (mamr3), 00000000b ; cs3 area = 32k-byte ld (p4fc), xxxx1111b ; cs0 ~ cs3 output mode note: x: don? care (2) connection example 2 figure 3.6 (7) is an example (2) in which an external memory is connected to the tmp96c031. in this example, the rom, ram, and i/o are connected with 8-bit width. figure 3.6 (8). example of external memory connection (rom = 16-bit, ram and i/o = 8-bit)
58 toshiba corporation TMP96C031N/f after a reset, the cs0 - cs3 pins are set to output port mode; 1 is output from cs0 , cs1 , and cs3 ; 0 from cs2 . the program used to set these pins is as follows: p4fc equ 10h b0cs equ 68h b1cs equ 69h b2cs equ 6ah b3cs equ 6bh msar3 equ 46h mamr3 equ 47h ld (bocs), 10010000b ; cs0 = 8-bit, 2wait, 7f00h ~ 7fffh, 2wait other than in cs0 ~ cs3 areas ld (b1cs), 100111xxb ; cs1 = 8-bit, 0wait, 80h ~ 7fffh ld (b2cs), 100001xxb ; cs2 = 16-bit, 1wait, 8000h ~ 3fffffh ld (b3cs), 10111100b ; cs3 = 8-bit, 0wait, address area speci?ation (400000h ~ 407fffh) ld (msar3), 01000000b ; cs3 start address: 400000h ld (mamr3), 00000000b ; cs3 area = 32k-byte ld (p4fc), xxxx1111b ; cs0 ~ cs3 output mode note: x: don? care
toshiba corporation 59 TMP96C031N/f 3.6.5 how to start with an 8-bit data bus (with am8/16 = ?? resetting sets the cs2 pin low due to an internal pull-down resistor; memory access starts in 16-bit data bus (2-wait) mode. to start in 8-bit data bus mode, a special operation is required. operation is as described in the example below: b2cs equ 6ah ; cs2 register address org 8000h ; reset address ldx (b2cs), 9ch ; cs2 8-bit, 0wait, 8000h ~ after reset, the program reads the ldx (b2cs), 9ch instruction in 16-bit data bus mode. ldx is a 6-byte instruc- tion: the 2nd, 4th and 6th bytes are handled as dummies (i.e., only codes in the 1st, 3rd and 5th bytes are actually used). even if starting in 8-bit data bus mode, it is possible to pro- gram so that the ldx instruction is executed and the block 2 area (8000h - 3fffffh) is accessed in 8-bit data bus mode without any problem. the above program does not include setting the p42/ cs2 pin to output; add a program to set the p4cr and p4fc registers as required.
60 toshiba corporation TMP96C031N/f 3.7 8-bit timers tmp96c031f contains four 8-bit timers (timers 0, 1 2, and 3), each of which can be operated independently. the cascade connection allows these timers to be used as two 16-bit tim- ers. the following four operating modes are provided for the 8- bit timers. 8-bit interval timer mode (4 timers) 16-bit interval timer mode (2 timers) 8-bit programmable square wave pulse generation (ppg: variable duty with variable cycle) output mode (2 timers) 8-bit pulse width modulation (pwm: variable duty with con- stant cycle) output mode (1 timer) figure 3.7 (1) shows the block diagram of 8-bit timer (timer 0 and timer 1). timers 2 and 3 have the same circuit con?uration as timers 0 and 1. however, timer 0 has an external clock, pin ti0, whereas timer 2 does not. each interval timer consists of an 8-bit up counter, 8-bit comparator, and 8-bit timer register. timer ?p-?p (tfe1) is provided for timers 0 and 1; tfe3 timer 2 and 3. among the input clock sources for the interval timers, the internal clocks of f t1, f t4, f t16, and f t256 are obtained from the 9-bit prescaler shown in figure 3.7 (2). the operation modes and timer ?ip-?ops of the 8-bit timer are controlled by three control registers t01mod, t23mod, tffcr, trun, and trdc. either two 8-bit buses or one 16-bit bus can be used .
toshiba corporation 61 TMP96C031N/f figure 3.7 (1). block diagram of 8-bit timers (timers 0 and 1)
62 toshiba corporation TMP96C031N/f prescaler this 9-bit prescaler generates the clock input to the 8-bit timers, 16-bit timer/event counters, and baud rate generators by further dividing the fundamental clock (fc) after it has been divided by 4 (fc/4). among them, 8-bit timer uses 4 types of clock: f t1, f t4, f t16, and f t256. this prescaler can be run or stopped by the timer operation control register trun . counting starts when is set to 1, while the prescaler is cleared to zero, and stops operation when is set to 0. resetting clears to 0, which clears and stops the prescaler. figure 3.7 (2). prescaler
toshiba corporation 63 TMP96C031N/f up-counter this is an 8-bit binary counter counted by an input clock specited by mode register t01mod for timers 0 and 1, or mode register t23mod for timers 2 and 3. input clocks for timer 0 or 2 can be selected from internal clocks f t1, f t4, and f t16 depending to the value set in the ti0 pin can also be selected. the input clock of timer 1 or 3 depends on the oper- ation mode; in 16-bit timer mode, timer 0/2 over?ow out- put is used as the output clock. when set to any other mode than 16-bit timer mode, the input clock is selected from the internal clocks f t1, f t16, and f t256 as well as the comparator output (match detection signal) of timer 0 according to the set value of t01mod register or t23mod. example: when t01mod = 01, the over ?ow output of timer 0 becomes the input clock of timer 1 (16-bit timer). when t01mod7, 6 = 00, t01mod3, 2 = 01, f t1 (8/fc) becomes the input of timer 1 (8-bit timer). operation mode is also set by t01mod register and t23mod register. when reset, it is initialized to t01mod = 00, t23mod = 00 whereby the up-counter is placed in the 8-bit timer mode. the counting and stop and clear of up-counter can be controlled for each interval timer by the timer opera- tion control register trun. when reset, all up-counters will be cleared to stop the timers. a timer register this is an 8-bit register for setting an interval time. when the set value of timer registers treg0, treg1, treg2, treg3 matches the value of up-counter, the comparator match detect signal becomes active. if the set value is 00h, this signal becomes active when the up- counter over?ows. timer register treg0/treg2 is of double buffer structure, each of which makes a pair with register buffer. treg0/treg2 is used to control enable/disable of the double buffers according to the timer register double buffer control register, trdc . it is dis- abled when / = 0 and enabled when they are set to 1. in the condition of double buffer enable state, the data is transferred from the register buffer to the timer register when the 2 n - 1 over?ow occurs in pwm mode, or at the ppg cycle in ppg mode. when reset, it will be initialized to / = 0 to disable the double buffer. to use the double buffer, write data in the timer register, set / to 1, and write the following data in the register buffer.
64 toshiba corporation TMP96C031N/f figure 3.7 (3). con?uration of timer register 0/2 note: timer register and the register buffer are allocated to the same memory address. when / = 0, the same value is written in the reg- ister buffer as well as the timer register, while when / = 1 only the register buffer is written. the memory address of each timer register is as fol- lows. treg0: 000022h treg1: 000023h treg2: 000026h treg3: 000027h all registers are write-only and cannot be read.
toshiba corporation 65 TMP96C031N/f figure 3.7 (4). timer 0, 1 mode register (t01mod)
66 toshiba corporation TMP96C031N/f figure 3.7 (5). timer 2,3 mode register (t23mod)
toshiba corporation 67 TMP96C031N/f figure 3.7 (6). 8-bit timer flip-flop control register (tffcr)
68 toshiba corporation TMP96C031N/f figure 3.7 (7). timer operation control register (trun)
toshiba corporation 69 TMP96C031N/f figure 3.7 (8). timer register double buffer control register (trdc)
70 toshiba corporation TMP96C031N/f ? comparator a comparator compares the value in the up-counter with the values to which the timer register is set. when they match, the up-counter is cleared to zero and an interrupt signal (intt0, intt1, intt2, intt3) is gener- ated. if the timer ?ip-?op inversion is enabled, the timer ?ip-?op is inverted at the same time. ? timer flip-flops (timer f/f) the timer ?ip-?ops are inverted according to the interval timer match detect signal (comparator output). the signal can output a value to the timer output pins to1 (also used as p70) and to3 (also used as p71). there are two timer ?ip-?ops: tff1 for timers 0 and 1; tff3 for timers 2 and 3. tff1 is output to the to1 pin; tff3 to the to3 pin. to3 (also used as p71) is multiplexed using the dmux pin; setting must be done using the port 7 control registers (p7crl and p7crh). the operation of 8-bit timers will be described below: (1) 8-bit timer mode four interval timers 0, 1, 2, 3, can be used indepen- dently as 8-bit interval timer. all interval timers operate in the same manner, and thus only the operation of timer 1 will be explained below. generating interrupts in a fixed cycle to generate timer 1 interrupt at constant intervals using timer 1 (intt1), trst stop timer 1 then set the operation mode, input clock, and a cycle to t01mod and treg1 register, respectively. then, enable interrupt intt1 and start the counting of timer 1. example: to generate timer 1 interrupt every 40 microseconds at fc = 16mhz, set each register in the following manner. note: x; don?t care e; no change msb lsb 76543210 trun ? 0 stop timer 1, and clear it to ?? t01mod ? 0 0 x x 0 1 set the 8-bit timer mode, and select f t1 (0.5 m s @ fc = 16mhz) as the input clock. treg1 ? 01101000 set the timer register at 40 m s f t1 = 50h. intet10 ? 1101 enable intt1, and set it to ?evel 5? trun ? x x 1? start timer 1 counting. use the following table for selecting the input clock. table 3.7 (1) 8-bit timer interrupt cycle and input clock input clock interrupt cycle (at fc = 20mhz) resolution f t1 (8/fc) 0.4 m s ~ 102.4 m s 0.4 m s f t4 (32/fc) 1.6 m s ~ 409.6 m s 1.6 m s f t16 (128/fc) 6.4 m s ~ 1.638ms 6.4 m s f t256 (2048/fc) 102.4 m s ~ 2.621ms 102.4 m s
toshiba corporation 71 TMP96C031N/f generating a 50% duty square wave pulse the timer ?ip-?op is inverted at constant intervals, and its status is output to timer output pin (to1). example: to output a 2.4 m s square wave pulse from to1 pin at fc = 20mhz, set each register in the following procedures. either timer 0 or timer 1 may be used, but this example uses timer 1. note: x; don?t care e; no change figure 3.7 (9). square wave (50% duty) output timing chart msb lsb 76543210 trun ? 0 stop timer 1, and clear it to ?? t01mod ? 0 0 x x 0 1 set the 8-bit timer mode, and select f t1 as the input clock. treg1 ? 00000011 set the timer register at 2.4 m s ? f t1 ? 2 = 3. tffcr ? 1011 clear tff1 to ?? and set to invert by the match detect signal from timer 1. p7crl ? 10 select p71 as to1 pin. trun ? x x 1? start timer 1 counting.
72 toshiba corporation TMP96C031N/f a making timer 1 count up by match signal from timer 0 comparator set the 8-bit timer mode, and set the comparator out- put of timer 0 as the input clock to timer 1. figure 3.7 (10). timer 1 count up by timer 0 ? output inversion with software the value of timer ?ip-?op (timer f/f) can be inverted, independent of timer operation. writing 00 into tffcr inverts the value of tff1, writing 00 into tffcr inverts the value of tff3. ? initial setting of timer flip-flop (timer f/f) the value of tff1 can be initialized to 0 or 1, inde- pendent of timer operation. for example, write 10 in tffcr to clear tff1 to 0, while write 01 in tffcr to set tff1 to 1. note: the value of timer register and timer ?ip-?op cannot be read. (2) 16-bit timer mode a 16-bit interval timer is contgured by combining tim- ers 0 and 1, or timers 2 and 3. timers 0 and 1 combined function the same as timers 2 and 3. a combination of timers 0 and 1 is used for explanation here. to contgure a 16-bit timer by cascade-connecting tim- ers 0 and 1, set the mode register, t01mod , to 00. setting 16-bit timer mode the input clock for timer 1 to timer 0 over?ow output regardless of the value set in the clock control register, tclk.
toshiba corporation 73 TMP96C031N/f table 3.7 (2) 16-bit timer (interrupt) and input clock input clock interrupt cycle (at fc = 20mhz) resolution f t1 (8/fc) 0.4 m s ~ 26.214ms 0.4 m s f t4 (32/fc) 1.6 m s ~ 104.857ms 1.6 m s f t16 (128/fc) 6.4 m s ~ 419.430ms 6.4 m s the lower 8-bit of the timer (interrupt) cycle are set by the timer register treg0, and the upper 8 bits are set by treg1. note that treg0 always must be set ?st. (writing data into treg0 disables the comparator temporarily, and the compar- ator is restarted by writing data into treg1.) setting example: to generate an interrupt intt1 every 0.4 seconds at fc = 20mhz, set the following values for timer registers treg0 and treg1: when counting with input clock of f t16 (8 m s @ 16mhz) 0.4 sec ? 4 m s = 62500 = f424h therefore, set treg1 = f4h and treg0 = 24h, respectively. the comparator match signal is output from timer 0 each time the up-counter uc0 matches treg0, where the up-counter uc0 is not to be cleared. int0 is not to be generated at this time, either. with the timer 1 comparator, the match detect signal is output at each comparator timing when up-counter uc1 and treg1 values match. when the match detect signal is output simultaneously from both comparators of timer 0 and timer 1, the up-counters uc0 and uc1 are cleared to 0, and the interrupt intt1 is generated. if inversion is enabled, the value of the timer ?ip-?op tff1 is inverted. figure 3.7 (11). output timer by 16-bit timer mode
74 toshiba corporation TMP96C031N/f (3) 8-bit ppg (programmable pulse generation) output mode square wave pulse can be generated at any frequency and duty by timer 0 or timer 1 and timer 0. the output pulse may be either low-active or high-active. in this figure 3.7 (12). block diagram of 8-bit ppg output mode mode, timer 1 cannot be used. with timer 0, data are output to the to1 pin (also used as p70); with timer 2, to the to3 pin (also used as p71).
toshiba corporation 75 TMP96C031N/f when the double buffer of treg0 is enabled in this mode, the value of register buffer will be shifted in treg0 each time treg1 matches uc0. use of the double buffer makes easy handling of low duty waves (when duty is varied). example: generating 1/4 duty 62.5khz pulse @ fc = 20mhz) calculate the value to be set for timer register. to obtain the frequency 62.5khz, the pulse cycle t should be: t = 1/62.5khz = 16 m s. given f t1 = 0.4 m s @ 20mhz), 16 m s ? 0.4 m s = 40 consequently, to set the timer register 1 (treg1) to treg1 = 40 = 28h and then duty to 1/4, t x 1/4 = 16 m s x 1/4 = 4 m s 4 m s ? 0.4 m s = 10 therefore, set timer register 0 (treg0) to treg0 = 10 = 0ah.
76 toshiba corporation TMP96C031N/f msb lsb note: x; dont care ? no change 76543210 trun ? x x 00 stop timer 0, and clear it to ?? t01mod ? 10xxxx01 set the 8-bit ppg mode, and select f t1 as input clock. tffcr ? 011x sets tff1 and enables the inversion and double buffer enable. writing ?0?provides negative logic pulse. treg0 ? 00001010 write ?ah? treg1 ? 00101000 write ?8h? p7crl ? 10 set p70 as the to1 pin. trun ? x x 1?1 start timer 0 and timer 1 counting. (4) 8-bit pwm output mode (pulse width modulation) mode used for timers 1 and 3. up to 2 pwms with a resolution of 8-bit (pwm1 and pwm3) pulse can be output. with timer 1, pwm is output to the to1 pin (also used as p70); with timer 3, to the to3 pin (also used as p71). timer 0 or 2 is used as an 8-bit timer. timer 1 (pwm1) is explained here because the opera- tion is the same as timer 3. timer output is inverted when up-counter (uc1) matches the set value of timer register treg or when 2n - 1 (n = 6, 7, or 8; speci?d by t01mod) counter over?w occurs. up-counter uc1 is cleared when 2n - 1 counter over?w occurs. for example, when n = 6, 6-bit pwm will be output, while when n = 7, 7-bit pwm will be output. to use this pwm mode, the following conditions must be satis?d. (set value of timer register) < (set value of 2 n - 1 counter over?w) (set value of timer register 1 0)
toshiba corporation 77 TMP96C031N/f figure 3.7 (13). block diagram of 8-bit pwm waveforms in this mode, the value of register buffer will be shifted in treg0 if 2 n - 1 over?w is detected when the double buffer of treg0 is enabled. use of the double buffer makes the handling of small duty waves easy.
78 toshiba corporation TMP96C031N/f example: to output the following pwm waves to to1 pin at fc = 20mhz. to realize 50.8 m s of pwm cycle by f t1 = 0.4 m s (@ fc = 20mhz), 50.8 m s ? 0.4 m s = 127 = 2 n - 1 consequently, n should be set to 7. as the period of low level is 36 m s, for f t1 = 0.4 m s, set the following value for treg0: 36 m s ? 0.4 m s = 90 = 5ah note : x; don?t care e; no change msb lsb 76543210 trun ? x x ? stop timer 0, and clear it to ?? t01mod ? 111001 set 8-bit pwm mode (cycle : 2 7 - 1) and select f t1 as the input clock. tffcr ? 101x clears tff1, enables the inversion and double buffer. treg0 ? 01011010 write ?ah? p7crl ? 10 set p70 as the to1 pin. trun ? x x 11 start timer 0 counting. table 3.7 (3) pwm cycle and the setting of 2 n - 1 counter pwm cycle (@ fc = 20 mhz) f t1 f t4 f t16 2 6 - 1 25.2 m sec (39.0khz) 100 m sec (10.0khz) 4.03msec (2.4khz) 2 7 - 1 50.8 m sec (19.7khz) 203 m sec (4.9khz) 812msec (1.2khz) 2 8 - 1 102 m sec (9.80khz) 408 m sec (2.4khz) 1.63msec (0.61khz)
toshiba corporation 79 TMP96C031N/f (5) table 3.7 (4) shows the list of 8-bit timer modes. note: ? dont care table 3.7 (4) timer mode setting registers timer mode (8-bit timer x 2channel) mode t01m (t23m) pwm0 (pwm2) upper input t1clk (t3clk) lower input t0clk (t2clk) invert select ff1is (ff3is) 16-bit timer (full 16-bit) x 1channel 01 (external clock, f t1, 4, 16) 8-bit timer (8-bit x 8-bit mode x 1channel) (comparator output from the lower timer is input to the upper timer.) 00 00 (external clock, f t1, 4, 16) 0 : lower timer 1 : upper timer 8-bit timer x 2channel 00 ( f t1, t16, t256) (external clock, f t1, 4, 16) 0 : lower timer 1 : upper timer 8-bit ppg x 1channel 10 (external clock, f t1, 4, 16) 8-bit pwm x 1channel (lower) 8-bit timer x 1channel (upper) 11 pwm cycle ( f t1, t16, t256) (external clock, f t1, 4, 16)
80 toshiba corporation TMP96C031N/f 3.8 16-bit pwm timer the tmp96c031f contains one (timer 4) multifunctional 16-bit timer/event counter with the following operation modes. 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation mode frequency measurement mode pulse width measurement mode time differential measurement mode timer/event counter consists of 16-bit up-counter, two 16-bit timer registers, two 16-bit capture registers (one of them applies double-buffer), two comparators, capture input controller, and timer ?p-?p and the control circuit. timer/event counter is controlled by 4 control registers: t4mod, t4ffcr, trun and t45cr. figure 3.8 (1) shows the block diagram of 16-bit timer/ event counter (timer 4).
toshiba corporation 81 TMP96C031N/f figure 3.8 (1). block diagram of 16-bit timer (timer 4)
82 toshiba corporation TMP96C031N/f figure 3.8 (2). 16-bit timer mode controller register (t4mod) (1/2)
toshiba corporation 83 TMP96C031N/f figure 3.8 (3). 16-bit timer mode controller register (t4mod) (2/2)
84 toshiba corporation TMP96C031N/f figure 3.8 (4). 16-bit timer 4 f/f control (t4ffcr)
toshiba corporation 85 TMP96C031N/f figure 3.8 (5). 16-bit timer (timer 4) control register (t45cr) figure 3.8 (6). timer operation control register (trun)
86 toshiba corporation TMP96C031N/f up-counter uc4 is a 16-bit binary counter which counts up according to the input clock specited by t4mod register. as the input clock, one of the internal clocks f t1(8/ fc), f t4 (32/fc), and f t16 (128/fc) from 9-bit prescaler (also used for 8-bit timer), and external clock from ti4 pin (also used as p72/int4 pin) can be selected. when reset, it will be initialized to = 00 to select ti4 input pin mode. counting or stop and clear of the counter is controlled by timer operation control register trun . when clearing is enabled, up-counter uc4 will be cleared to zero each time it coincides matches the timer register treg5. the clear enable/disable is set by t4mod . if clearing is disabled, the counter operates as a free- running counter. timer registers these two 16-bit registers are used to set the interval time. when the value of up-counter uc4 matches the set value of this timer register, the comparator match detect signal will be active. setting data for timer register (treg4 and treg5) is executed using 2-byte data transfer instruction or using 1-byte data transfer instruction twice for lower 8-bit and upper 1-bit in order. treg4 timer register is of double buffer structure, which is paired with register buffer. the timer control register t45cr controls whether the dou- ble buffer should be enabled or disabled. : disabled when = 0, while enabled when = 1. when the double buffer is enabled, the timing to transfer data from the register buffer to the timer regis- ter is at the match between the up-counter (uc4) and timer register treg5. when reset, it will be initialized to = 0, whereby the double buffer is disabled. to use the double buffer, write data in the timer register, set = 1, and then write the following data in the register buffer. treg4 and register buffer are allocated to the same memory addresses 000030h/000031h. when = 0, same value will be written into only the register buffer. a capture register these 16-bit registers are used to hold the values of the up-counter. data in the capture registers should be read by a 2- byte data load instruction or two 1-byte data load instruction, from the lower 8-bit followed by the upper 8-bit.
toshiba corporation 87 TMP96C031N/f ? capture input control this circuit controls the timing to latch the value of up- counter uc4 into (cap1, cap2). the latch timing of capture register is controlled by register t4mod /t5mod . when t4mod = 00 capture function is disabled. disable is the default on reset. when t4mod = 01 data is loaded to cap1 at the rise edge of ti4 pin (also used p80/int4) input, while data is loaded to cap2 at the rise edge of ti5 pin (also used as p81/ int5) and input. (time difference measurement) when t4mod = 10 data is loaded to cap1 at the rise edge of ti4 pin input, while to cap2 at the fall edge. only in this set- ting, interrupt int4 occurs at fall edge. (pulse width measurement) when t4mod = 11 data is loaded to cap1 at the rise edge of timer ?ip- ?op tff1, while to cap2 at the fall edge. besides, the value of up-counter can be loaded to capture registers by software. whenever 0 is written in t4mod the current value of up-counter will be loaded to capture register cap1. it is neces- sary to keep the prescaler in run mode (trun to be 1). ? comparator these are 16-bit comparators which compare the up- counter uc4 value with the set value of (treg4, treg5) to detect the match. when a match is detected, the comparators generate and interrupt (intt4, intt5) respectively. the up-counter uc4 is cleared only when uc4 matches treg5. (the clear- ing of up-counter uc4 can be disabled by setting t4mod = 0.) ? timer flip-flop (tff4) this ?ip-?op is inverted by the match detect signal from the comparators and the latch signals to the capture registers. disable/enable of inversion can be set for each element by t4ffcr . tff4 will be inverted when 00 is written in t4ffcr . also it is set to 1 when 10 is written, and cleared to 0 when 10 is written. the value of tff4 can be output to the timer output pin to4 (also used as p70). ? timer flip-flop (tff5) this ?ip-?op is inverted by the match detect signal from the comparator and the latch signal to the cap- ture register cap2. tff5 will be inverted when 00 is written in t4ffcr /t6ffcr . also it is set to 1 when 10 is written, and cleared to 0 when 10 is written. the value of tff5 can be output to the timer output pin to5 (also used as p82). to5 (also used as p30) is multiplexed using the hwr pin; setting must be done using the port 3 control reg- ister, p3crl. note: to5 (also used as p30) is multiplexed with hwr; setting must be done using the p3sr.
88 toshiba corporation TMP96C031N/f (1) 16-bit timer mode generating interrupts at ?ed intervals in this example, the interval time is set in the timer reg- ister treg5 to generate the interrupt inttr5. note : x; dont care ? no change 76543210 trun ? x x 0 stop timer 4. intet54 ? 11001000 enable inttr5 and sets interrupt level 4. disable inttr4. t4ffcr ? 11000011 disable trigger. t4mod ? 001001** select internal clock for input and disable the capture function. (** = 01, 10, 11) treg5 ? 00101000 set the interval time (16-bit). ******** trun ? 1x 11 start timer 4. (2) 16-bit event counter mode in 16-bit timer mode as described in above, the timer can be used as an event counter be selecting the external clock (ti4 pin input) as the input clock. to read the value of the counter, ?st perform the ?oftware capture?once and read the captured value. the counter counts at the rise edge of ti4 pin input. ti4 can also be used as p72/int4. note: when used as an event counter, set the prescaler in run mode. 76543210 trun ? x x 0 stop timer 4. p7cr ? 00 set p72 to input mode. intet54 ? 11001000 enable inttr5 and sets interrupt level 4, while disable inttr4. t4ffcr ? 11000011 disable trigger. t4mod ? 00100100 select ti4 as the input clock. treg5 ? ******** set the number of counts (16-bit). trun ? x x 11 start timer 4.
toshiba corporation 89 TMP96C031N/f (3) 16-bit programmable pulse generation (ppg) mode the ppg mode is obtained by inversion of the timer ?p-?p tff4 that is to be enabled by the match of the up-counter uc4 with the timer register treg4 or 5 and to be output to to4 (also used as p70). in this mode, the following conditions must be satis?d. (set value of treg4) < (set value of treg5) note : x; dont care ? no change 76543210 trun ? x x 0 stop timer 4. treg4 ? ******** set the duty. (16-bit). treg5 ? ******** set the cycle. (16-bit). t45cr ? ******** double buffer of treg4 enable (change the duty and cycle at the interrupt inttr5). t4ffcr ? 11000011 set the mode to invert tff4 at the match with treg4/treg5, and also set the tff4 to ?? t4mod ? 00100100 select the internal clock for the input, and disable the (** = 01, 10, 11) capture function. p7cr ? 11 assign p70 as to4. trun ? x x 11 start timer 4. figure 3.8 (7). programmable pulse generation (ppg) output waveforms
90 toshiba corporation TMP96C031N/f when the double buffer of treg4 is enabled in this mode, the value of register buffer 4 will be shifted in treg4 at match with treg5. this feature makes easy the handling of low duty waves. figure 3.8 (8). operation of register buffer shows the block diagram of this mode. figure 3.8 (9). block diagram of 16-bit ppg mode
toshiba corporation 91 TMP96C031N/f (4) application examples of capture function the loading of up-counter (uc4) values into the cap- ture registers cap1 and cap2, the timer ?p-?p tff4 inversion due to the match detection by comparators cp4 and cp5, and the output of the tff4 status to to4 pin can be enabled or disabled. combined with interrupt function, they can be applied in many ways, for example; one-shot pulse output from the external trigger pulse frequency measurement a pulse width measurement ? time difference measurement one-shot pulse output from the external trigger pulse set the up-counter uc4 in free-running mode with the internal input clock, input the external trigger pulse from ti4 pin, and load the value of up-counter into capture register cap1 at the rise edge of the ti4 pin. then set t4mod = 01. when the interrupt int4 is generated at the rise edge of the ti4 pin, set the cap1 value (c) plus a delay time (d) to treg5 (= c + d), and set the above set value (c + d) plus a one-shot pulse width (p) to treg5 (= c + d + p). when interrupt int4 occurs the t4ffcr register sgould be set that the tff4 inversion is enabled only when the up-counter value matches treg4 or treg5. when interrupt inttr5 occurs, this inversion will be disabled. figure 3.8 (10). one-shot pulse output (with delay)
92 toshiba corporation TMP96C031N/f setting example: to output 2ms one-shot with 3ms delay to the external trigger pulse to ti4 pin.
toshiba corporation 93 TMP96C031N/f when delay is unnecessary, invert timer ?p-?p tff4 when the up-counter value is loaded into capture register 1 (cap1), and set the cap1 value (c) plus the one-shot pulse width (p) to treg5 when the interrupt int4 occurs. the tff4 inversion should be enabled when the up-counter (uc4) value matches treg5, and disabled when generating the interrupt inttr5. figure 3.8 (11). one-shot pulse output (without delay) frequency measurement the frequency of the external clock can be measured in this mode. the clock is input through the ti4 pin, and its frequency is measured by the 8-bit timers (timer 0 and timer 1) and the 16-bit timer/event counter (timer 4). the ti4 pin input should be selected for the input clock of timer 4. the value of the up-counter is loaded into the capture register cap1 at the rise edge of the timer ?ip-?op tff1 of 8-bit timers (timer 0 and timer 1), and into cap2 at its fall edge. the frequency is calculated by the difference between the loaded values in cap1 and cap2 when the interrupt (intt0 or intt1) is generated by either 8-bit timer.
94 toshiba corporation TMP96C031N/f figure 3.8 (12). frequency measurement for example, if the value for the level ??width of tff1 of the 8-bit timer is set to 0.5 s. and the difference between cap1 and cap2 is 100, the frequency will be 100/0.5[s] = 200[hz].
toshiba corporation 95 TMP96C031N/f a pulse width measurement this mode allows measuring the ??level width of an external pulse. while keeping the 16-bit timer/event counter counting (free-running) with the internal clock input, the external pulse is input through the ti4 pin. then the capture function is used to load the uc4 values into cap1 and cap2 at the rising edge and falling edge of the external trigger pulse respectively. the interrupt int4 occurs at the falling edge of ti4. the pulse width is obtained from the difference between the values of cap1 and cap2 and the internal clock cycle. for example, if the internal clock is 0.8 microseconds and the difference between cap1 and cap2 is 100, the pulse width will be 100 x 0.8 = 80 microseconds. figure 3.8 (13). pulse width measurement note: only in this pulse width measuring mode (t4mod = 10), external interrupt int4 occurs at the falling edge of ti4 pin input. in other modes, it occurs at the rising edge. the width of ??level can be measured from the dif- ference between the ?st c2 and the second c1 at the second int4 interrupt. ? time difference measurement this mode is used to measure the difference in time between the rising edges of external pulses input through ti4 and ti5. keep the 16-bit timer/event counter (timer 4) count- ing (free-running) with the internal clock, and load the uc4 value into cap1 at the rising edge of the input pulse to ti4. then the interrupt int4 is generated. similarly, the uc4 value is loaded into cap2 at the rising edge of the input pulse to ti5, generating the inter- rupt int5. the time difference between these pulses can be obtained from the difference between the time counts at which loading the up-counter value into cap1 and cap2 has been done.
96 toshiba corporation TMP96C031N/f figure 3.8 (14). time difference measurement (5) different phased pulses output mode in this output mode, signals with any different phase can be outputted by free-running up-counter uc4. when the value in up-counter uc4 and the value in treg4 (treg5) match, the value in tff4 (tff5) is inverted and output to to4 (to5). this mode can only be used by 16-bit timer 4. figure 3.8 (15). phase output cycles (counter over?w time) of the above output waves are listed below. 16mhz 20mhz f t1 32.768ms 26.214ms f t4 131.072ms 104.856ms f t16 524.288ms 419.424ms
toshiba corporation 97 TMP96C031N/f 3.9 stepping motor control/pattern generation port the tmp96c031f contains 2 channels (pg0 and pg1) of 4-bit hardware stepping motor control/pattern generation (herein after called pg) which actuate in synchronization with the (8-bit/16-bit) timers. the pg (pg0 and pg1) are shared in 8-bit i/o ports p6. channel 0 (pg0) is synchronous with 8-bit timer 0 or timer 1, 16-bit timer 4, channel 1 (pg1) is synchronous with 8- difference between pg0 and pg1 figure 3.9 (1). pattern generator/stepping motor control block diagram bit timer2 or timer3, 16-bit timer4, to update the output. the pg ports are controlled by control registers (pg01cr) and can select either stepping motor control mode or pattern generation mode. each bit of the p6 can be used as the pg port. channel 0 (pg0) and channel 1 (pg1) operate indepen- dently. except in the following case, both channels operate the same. thus, channel 0 (pg0) is explained here.
98 toshiba corporation TMP96C031N/f figure 3.9 (2a). pattern generation control register (pg01cr)
toshiba corporation 99 TMP96C031N/f figure 3.9 (2b). pattern generation control register (pg01cr)
100 toshiba corporation TMP96C031N/f figure 3.9 (3). pattern generation 0 register (pg0reg) figure 3.9 (4). pattern generation 1 register (pg1reg) 76543210 bit symbol pg03 pg02 pg01 pg00 sa03 sa02 sa01 sa00 read/write w r/w after reset 0000 unde?ed function pattern generation 0 (pg0) output latch register (reading the p6 that is set to the pg port allows to read-out.) shift alternate register 0 for the pg mode (4-bit write) register 76543210 bit symbol pg13 pg12 pg11 pg10 sa13 sa12 sa11 sa10 read/write w r/w after reset 0000 unde?ed function pattern generation 1 (pg1) output latch register (reading the p6 that is set to the pg port allows to read-out.) shift alternate register 1 for the pg mode (4-bit write) register pg0reg (004ch) prohibit read modify write pg1reg (004dh) prohibit read modify write
toshiba corporation 101 TMP96C031N/f figure 3.9 (5). 16-bit timer trigger control register (t45cr)
102 toshiba corporation TMP96C031N/f figure 3.9 (6). connection of timer and pattern generator (1) pattern generation mode pg functions as a pattern generation according to the setting of pg01cr /. in this mode, writing from cpu is executed only on the shifter alter- nate register. writing a new data should be done during the interrupt operation of the timer for shift trigger, and a pattern can be output synchronous with the timer. in this mode, set pg01cr and to 1, and pg01cr and to 0. the output of this pattern generator is output to port 6; since port and functions can be switched on a bit basis using port function control register p6crl/p6crh, any port pin can be assigned to pattern generator output. figure 3.9 (7) shows the block diagram of this mode. figure 3.9 (7). pattern generation mode timing example
toshiba corporation 103 TMP96C031N/f figure 3.9 (7). pattern generation mode block diagram (pg0) in this pattern generation mode, only writing the output latch is disabled by hardware, but other functions do the same operation as 1-2 excitation in stepping motor control port mode. accordingly, the data shifted by trigger signal from a timer must be written before the next trigger signal is output.
104 toshiba corporation TMP96C031N/f (2) stepping motor control mode 4-phase 1-step/2-step excitation figure 3.9 (8) and figure 3.9 (9) show the output wave- forms of 4-phase 1 excitation and 4-phase 2 excita- tion, respectively when channel 0 (pg0) is selected. figure 3.9 (8). output waveforms of 4-phase 1-step excitation (normal rotation and reverse rotation)
toshiba corporation 105 TMP96C031N/f figure 3.9 (9). output waveforms of 4-phase 2-step excitation (normal rotation) the operation when channel 0 is selected is explained below. the output latch of pg0 (also used as p6) is shifted at the rising edge of the trigger signal from the timer to be output to the port. the direction of shift is speci?d by pg01cr : normal rotation (pg00 ? pg01 ? pg02 ? pg03) when is set to ?? reverse rotation (pg00 ? pg01 ? pg02 ? pg03) when ?? four-phase 1-step excitation will be selected when only one bit is set to ??during the initialization of pg, while 4-phase 2-step excitation will be selected when two consecutive bits are set to ?? the value in the shift alternate registers are ignored when the 4-phase 1-step/2-step excitation mode is selected. figure 3.9 (10) shows the block diagram. figure 3.9 (10). block diagram of 4-phase 1-step excitation/2-step excitation (normal rotation)
106 toshiba corporation TMP96C031N/f 4-phase 1-2 step excitation figure 3.9 (11) shows the output waveforms of 4- phase 1 -2 step excitation when channel 0 is selected. figure 3.9 (11). output waveforms of 4-phase 1-2 step excitation (normal rotation and reverse rotation)
toshiba corporation 107 TMP96C031N/f the initialization for 4-phase 1-2 step excitation is as follows: by rearranging the initial value ?7 b6 b5 b4 b3 b2 b1 b0?to ?7 b3 b6 b2 b5 b1 b4 b0? the consecutive 3 bits are set to ??and other bits are set to ??(positive logic). for example, if b7, b3, and b6 are set to ?", the ini- tial value becomes ?1001000? obtaining the output waveforms as shown in figure 3.10 (11). to get an output waveform of negative logic, set val- ues 1s and 0s of the initial value should be inverted. for example, to change the output waveform shown in fig- ure 3.10 (11) into negative logic, change the initial value to ?0110111? the operation will be explained below for channel 0. the output latch of pg0 (shared by p6) and the shifter alternate register (sa0) for pattern generation are shifted at the rising edge of trigger signal from the timer to be output to the port. the direction of shift is set by pg01cr . figure 3.9 (12) shows the block diagram. figure 3.9 (12). block diagram of 4-phase 1-2 step excitation (normal rotation)
108 toshiba corporation TMP96C031N/f note: to shift pg, tffcr must be set to ??to enable tff1 inversion. table 3.9 (1) select of trigger signal tff1 inversion pg shift 8-bit timer mode selected by tffcr when the up-counter value matches treg0 or treg1 value. 16-bit timer mode when the up-counter value matches with both treg0 and treg1 values. (the value of up-counter = treg1*2 8 + treg0) ppg output mode when the up-counter value matches with both treg0 and treg1. when the up-counter value matches treg1 value (ppg cycle). pwm output mode when the up-counter value matches treg0 value and pwm cycle. trigger signal for pg is not generated. setting example: to drive channel 0 (pg0) by 4-phase 1-2 step excitation (normal rotation) when timer 0 is selected, set each register as follows: note: x; dont care ? no change 76543210 trun ? ? ? stop timer 0, and clears it to zero. tmod ? 0 0 x x 0 1 set 8-bit timer mode and selects f t1 as the input clock of timer 0. tffcr ? xxx01010 clear tff1 to zero and enables the inversion trigger by timer 0. treg0 ? ******** set the cycle in timer register. p6crl ? 10101010 set p60 ~ p63 bits to pg output. pg01cr ? 0011 select pg0 4-phase 1 - 2 step excitation mode and normal rotation. pg0reg ? 11001000 set an initial value. trun ? 1x ? start timer 0. (3) trigger signal from timer the trigger signal from the timer which is used by pg is channel 1 of pg can be synchronized with the 16-bit timer timer 4. in this case, the pg shift trigger signal from the 16-bit timer is output only when the up- counter uc4 value matches treg5. when using a trigger signal from timer 4, set either t4ffcr or t4mod to ??and a trigger is generated when the value in uc4 and the value in treg5 match. not equal to the trigger signal of timer ?p-?p (tff1, tff4, tff5, and tff6) and differs as shown in table 3.9 (1) depending on the operation mode of the timer.
toshiba corporation 109 TMP96C031N/f figure 3.9 (13). output waveforms of 4-phase 1-step excitation setting example: note: x; dont care ? no change 76543210 trun ? ? 00 stop timer 0, and clears it to zero. tmod ? 10xxxx01 set timer 0 and timer 1 in ppg output mode and selects f t1 as the input clock. tffcr ? xxx0011x enable tff1 inversion and sets tff1 to ?? treg0 ? ******** set the duty of to1 to treg0. treg1 ? ******** set the cycle of to1 to treg1. p7cr ? 10 assign p70 as to1. p6crl ? 10101011 assign p60 ~ 63 as pg0. pg01cr ? 0001 set pg0 in 4-phase 1-step excitation mode. pg0reg ? ******** set an initial value. trun ? 1x 11 start timer 0 and timer 1. (4) application of pg and timer output as explained in ?rigger signal from timer? the timing to shift pg and invert tff differs depending on the mode of timer. an application to operate pg while operating an 8-bit timer in ppg mode will be explained below. to drive a stepping motor, in addition to the value of each phase (pg output), synchronizing signal is often required at the timing when excitation is changed over. in this application, port 6 is used as a stepping motor control port to output a synchronizing signal to the to1 pin (shared by p70).
110 toshiba corporation TMP96C031N/f 3.10 serial channel the tmp96c031f contains 2 serial i/o channels for full duplex asynchronous transmission (uart) as well as for i/o exten- sion. the serial channel has the following operation modes. l i/o interface mode mode 0: to transmit and receive i/o data as well as (channel 1 only) the synchronizing signal sclk for extending i/o. mode 1: 7-bit data l asynchronous transmission mode 2: 8-bit data (uart) mode (channel 0 and 1) mode 3: 9-bit data in mode 1 and mode 2, a parity bit can be added. mode 3 has wake-up function for making the master controller start slave controllers in serial link (multi-controller system). figure 3.10 (1) shows the data format (for one frame) in each mode. figure 3.10 (1). data formats
toshiba corporation 111 TMP96C031N/f the serial channel has a buffer register for transmitting and receiving operations, in order to temporarily store trans- mitted or received data, so that transmitting and receiving operations can be done independently (full duplex). however, in i/o interface mode, sclk (serial clock) pin is used for both transmission and receiving, the channel becomes half-duplex. the receiving data register is of a double buffer structure to prevent the occurrence of overrun error and provides one frame of margin before cpu reads the received data. the receiving data register stores the already received data while the buffer register receives the next frame data. by using cts and r ts (there is no r ts pin, so any one port must be controlled by software), it is possible to halt data send until cpu ?ishes reading receive data every time a frame is received (handshake function). in the uart mode, a check function is added not to start the receiving operation by error start bits due to noise. the channel starts receiving data only when the start bit is detected to be normal at least twice in three samplings. when the transmission buffer becomes empty and requests the cpu to send the next transmission data, or when data is stored in the receiving data register and the cpu is requested to read the data, inttx or intrx interrupt occurs. besides, if an overrun error, parity error, or framing error occurs during receiving operation, ?g sc0cr/sc1cr will be set. the serial channel 0/1 includes a special baud rate gen- erator, which can set any baud rate by dividing the frequency of four clocks ( f t0, f t2, f t8, and f t32) from the internal pres- caler (shared by 8-bit/16-bit timer) by the value 2 to 16. in i/o interface mode, it is possible to input synchronous signals as well as to transmit or receive data by external clock. 3.10.1 control registers the serial channel is controlled by three control registers sc0cr, sc0mod, and br0cr. transmitted and received data is stored in register sc0buf.
112 toshiba corporation TMP96C031N/f figure 3.10 (2). serial mode control register (channel 0, sc0mod)
toshiba corporation 113 TMP96C031N/f figure 3.10 (3). serial control register (channel, sc0cr)
114 toshiba corporation TMP96C031N/f figure 3.10 (4). serial channel control (channel 0, br0cr) figure 3.10 (5). serial transmission/receiving buffer registers (channel 0, sc0buf) 76543210 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 76543210 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 note: (transmission) (receiving) sc0buf (50h)
toshiba corporation 115 TMP96C031N/f figure 3.10 (6). serial mode control register (channel 1, sc1mod)
116 toshiba corporation TMP96C031N/f figure 3.10 (7). serial control register (channel 1, sc1cr)
toshiba corporation 117 TMP96C031N/f figure 3.10 (8). baud rate generator control register (channel 0, br0cr) figure 3.10 (9). serial transmission/receiving buffer registers (channel 1, sc1buf) 76543210 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 76543210 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 (transmission) (receiving) sc1buf (0054h)
118 toshiba corporation TMP96C031N/f figure 3.10 (10). port 6, 7 control registers
toshiba corporation 119 TMP96C031N/f port 3.10 (11). serial open drain enable register (ode)
120 toshiba corporation TMP96C031N/f 3.10.2 con?uration figure 3.10 (12) shows the block diagram of the serial channel 0. figure 3.10 (12). block diagram of the serial channel 0
toshiba corporation 121 TMP96C031N/f figure 3.10 (13). block diagram of the serial channel 1 figure 3.10 (13) shows the block diagram of the serial channel 1. ? 16
122 toshiba corporation TMP96C031N/f baud rate generator baud rate generator comprises a circuit that generates transmission and receiving clocks to determine the transfer rate of the serial channel. the input clock to the baud rate generator, f t0 (fc/4), f t2 (fc/16), f t8 (fc/64), or f t32 (fc/256) is generated by the 9-bit prescaler which is shared by the timers. one of these input clocks is selected by the baud rate generator control register br0cr/br1cr . the baud rate generator includes a 4-bit frequency divider, which divides frequency by 2 to 16 values to determine the transfer rate. how to calculate a transfer rate when the baud rate generator is used is explained below. l uart mode transfer rate = input clock of baud rate generator fr equency divisor of baud rate generator l i/o interface mode transfer rate = input clock of baud rate generator fr equency divisor of baud rate generator the relation between the input clock and the source clock (fc) is as follows: f t0 = fc/4 f t2 = fc/16 f t8 = fc/64 f t32 = fc/256 accordingly, when source clock fc is 12.288mhz, input clock is f t2 (fc/16), and frequency divisor is 5, the transfer rate in uart mode becomes as follows: transfer rate = fc/16 5 = 12.288 x 10 6 /16/5/16 = 9600 (bps) table 3.10 (1) shows an example of the transfer rate in uart mode. also with 8-bit timer 0, the serial channel can get a transfer rate. table 3.10 (2) shows an example of baud rate using timer 0. note: transfer rate in i/o interface mode is 8 times as fast as the values given in the above table. table 3.10 (1) selection of transfer rate (1) (when baud rate generator is used) unit (kbps) fc [mhz] input clock frequency divisor f t0 (fc/4) f t2 (fc/16) f t8 (fc/64) f t32 (fc/256) 9.830400 2 76.800 19.200 4.800 1.200 - 4 38.400 9.600 2.400 0.600 - 8 19.200 4.800 1.200 0.300 - 0 9.600 2.400 0.600 0.150 12.288000 5 38.400 9.600 2.400 0.600 - a 19.200 4.800 1.200 0.300 14.745600 3 76.800 19.200 4.800 1.200 - 6 38.400 9.600 2.400 0.600 - c 19.200 4.800 1.200 0.300
toshiba corporation 123 TMP96C031N/f how to calculate the transfer rate (when timer 0 is used): transfer rate = fc treg0 x 8 x 16 (when timer 0 (input clock f t1) is used) input clock of timer 0 f t1 = fc /8 f t4 = fc /32 f t16 = fc /128 note: timer 0 match detect signal cannot be used as the transfer clock in i/o interface mode. table 3.10 (2) selection of transfer rate (1) (when timer 0 (input clock f t1) is used) unit (kbps) fc treg0 12.288mhz 12mhz 9.8304mhz 8mhz 6.144mhz 1h 96 76.8 62.5 48 2h 48 38.4 31.25 24 3h 32 31.25 16 4h 24 19.2 12 5h 19.2 9.6 8h 12 9.6 6 ah 9.6 4.8 10h 6 4.8 3 14h 4.8 2.4 serial clock generation circuit this circuit generates the basic clock for transmitting and receiving data. i/o interface mode (channel 1 only) when in sclk output mode with the setting of sc1cr = ?", the basic clock will be generated by dividing by 2 the output of the baud rate generator as described before. when in sclk input mode with the setting of sc1cr = ?", the rising edge or falling edge will be detected according to the setting of sc1cr register to generate the basic clock. asynchronous communication (uart) mode according to the setting of sc0cr and sc1cr , the above baud rate generator clock, internal clock f 1 (500kbps @ fc = 16 mhz), or the match detect signal from timer 0 will be selected to generate the basic clock sioclk. a receiving counter the receiving counter is a 4-bit binary counter used in asynchronous communication (uart) mode and counts up by sioclk clock. 16 pulses of sioclk are used for receiving one bit of data, and the data bit is sampled three times at 7th, 8th and 9th clock. with the three samples, the received data is evalu- ated by the rule of majority. for example, if the sampled data bit is ?", ??and ??at 7th, 8th and 9th clock respectively, the received -
124 toshiba corporation TMP96C031N/f data is evaluated as ?? the sampled data ?", ??and ??is evaluated that the received data is ?? ? receiving control i/o interface mode (channel 1 only) when in sclk1 output mode with the setting of sc1cr = ?", rxd1 signal will be sampled at the rising edge of shift clock which is output to sclk pin. when in sclk input mode with the setting sc1cr = ?", rxd1 signal will be sampled at the rising edge or falling edge of sclk input according to the set- ting of sc1cr register. asynchronous communication (uart) mode the receiving control has a circuit for detecting the start bit by the rule of majority. when two or more ??are detected during 3 samples, it is recognized as start bit and the receiving operation is started. data being received is also evaluated by the rule of majority. ? receiving buffer to prevent overrun error, the receiving buffer has a double buffer structure. received data is stored one bit by one bit in the receiving buffer 1 (shift register type). when 7 bits or 8 bits of data are stored in the receiving buffer 1, the stored data is transferred to another receiving buffer 2 (sc0buf/sc1buf), generating an interrupt intrx0/ intrx1. the cpu reads only receiving buffer 2 (sc0buf/sc1buf). even before the cpu reads the receiving buffer 2 (sc0buf/sc1buf), the received data can be stored in the receiving buffer 1. however, unless the receiving buffer 2 (sc0buf/sc1buf) is read before all bits of the next data are received by the receiving buffer 1, an overrun error occurs. if an overrun error occurs, the contents of the receiving buffer 1 will be lost, although the contents of the receiving buffer 2 and sc0cr sc1cr are still preserved. the parity bit added in 8-bit uart mode and the most signi?ant bit (msb) in 9-bit uart mode are stored in sc0cr /sc1cr . when in 9-bit uart mode, the wake-up function of the slave controllers is enabled by setting sc0mod /sc1mod to ?", and interrupt intrx0/ intrx1 occurs only when sc0cr /sc1cr is set to ?? ? transmission counter transmission counter is a 4-bit binary counter which is used in asynchronous communication (uart) mode and, like a receiving counter, counts by sioclk clock, generating txdclk every 16 clock pulses. figure 3.10 (14). generation of transmission clock
toshiba corporation 125 TMP96C031N/f figure 3.10 (15). handshake function ? transmission controller i/o interface mode (channel 1 only) in sclk output mode with the setting of sc1cr = ?", the data in the transmission buffer are out- put bit by bit to txd1 pin at the rising edge of shift clock which is output from sclk1 pin. in sclk input mode with the setting sc1cr = ?", the data in the transmission buffer are output bit by bit to txd1 pin at the rising edge or falling edge of sclk input according to the setting of sc1cr regis- ter. asynchronous communication (uart) mode when transmission data is written in the transmission buffer sent from the cpu, transmission starts at the rising edge of the next txdclk, generating a transmission shift clock txdsft. handshake function serial channel 0 has a cts0 pin. using this pin, data can be sent in units of one frame; thus, overrun errors can be avoided. the handshake function is enabled/dis- abled by sc0mod . when the cts0 pin goes high, after completion of the current data send, data send is halted until the cts0 pin goes low again. the inttx0 interrupts are generated, requests the next send data to the cpu. though there is no r ts pin, a handshake function can be easily con?ured by setting any port assigned to the r ts function. the r ts should be output ?igh?to request data send halt after data receive is completed by a software in the rxd interrupt routine.
126 toshiba corporation TMP96C031N/f figure 3.10 (16). timing of cts (clear to send) ? transmission buffer transmission buffer (sc0buf/sc1buf) shifts to and sends the transmission data written from the cpu from the least signi?ant bit (lsb) in order, using transmission shift clock txdsft which is generated by the transmis- sion control. when all bits are shifted out, the transmis- sion buffer becomes empty and generates inttx0/ inttx1 interrupt. parity control circuit when serial channel control register sc0cr / sc1cr is set to ?", it is possible to transmit and receive data with parity. however, parity can be added only in 7-bit uart or 8-bit uart mode. with sc0cr /sc1cr register, even (odd) parity can be selected. for transmission, parity is automatically generated according to the data written in the transmission buffer scbuf, and data are transmitted after being stored in sc0buf /sc1buf when in 7-bit uart mode while in scmod /scmod when in 8-bit uart mode. and must be set before transmission data are written in the transmission buffer. for receiving, data is shifted in the receiving buffer 1, and parity is added after the data is transferred in the receiving buffer 2 (sc0buf/sc1buf), and then com- pared with sc0buf /sc1buf when in 7- bit uart mode and with sc0mod /sc1mod when in 8-bit uart mode. if they are not equal, a parity error occurs, and sc0cr /sc1cr ?g is set error flag three error ?gs are provided to increase the reliabil- ity of receiving data. 1. overrun error if all bits of the next data are received in receiving buffer 1 while valid data is stored in receiving buffer 2 (scbuf), an overrun error will occur. 2. parity error the parity generated for the data shifted in receiving buffer 2 (scbuf) is compared with the parity bit received from rxd pin. if they are not equal, a parity error occurs. 3. framing error the stop bit of received data is sampled three times around the center. if the majority is ?", a framing error occurs.
toshiba corporation 127 TMP96C031N/f generating timing 1) uart mode 2) i/o interface mode receiving mode 9-bit 8-bit + parity 8-bit, 7-bit + parity, 7-bit interrupt timing center of last bit (bit 8) center of last bit (parity bit) center of stop bit framing error timing center of stop bit center of stop bit center of stop bit parity error timing center of last bit (bit 8) center of last bit (parity bit) center of stop bit overrun error timing center of last bit (bit 8) center of last bit (parity bit) center of stop bit transmitting mode 9-bit 8-bit + parity 8-bit, 7-bit + parity, 7-bit interrupt timing just before last bit is transmitted. ?? transmission interrupt tim- ing sclk output mode immediately after rise of last sclk signal. (see ?ure 3.10 (19) .) sclk input mode immediately after rise of last sclk signal (rising mode), or immediately after fall in falling mode. (see ?ure 3.10 (20)) receiving interrupt timing sclk output mode timing used to transfer received data to data receive buffer 2 (sc1buf); that is, immediately after last sclk. (see ?ure 3.10 (21)) sclk input mode timing used to transfer received data to data receive buffer 2 (sc1buf); that is, immediately after sclk. (see ?ure 3.10 (22)) 11
128 toshiba corporation TMP96C031N/f 3.10.3 operational description (1) mode 0 (i/o interface mode) this mode is used to increase the number of i/o pins for transmitting or receiving data to or from the external shifter register. this mode includes sclk output mode to output syn- chronous clock sclk and sclk input mode to input external synchronous clock sclk. figure 3.10 (17). example of sclk output mode connection figure 3.10 (18). example of sclk input mode connection
toshiba corporation 129 TMP96C031N/f transmission in sclk output mode, 8-bit data and synchronous clock are output from txd pin and sclk pin, respectively, each time the cpu writes data in the transmission buffer. when all data is output, intes1 will be set to generate inttx1 interrupt. figure 3.10 (20). transmitting operation in i/o interface mode (sclk input mode) figure 3.10 (19). transmitting operation in i/o interface mode (sclk output mode) when all data are output, intes1 will be set to generate inttx1 interrupt. in sclk output mode, 8-bit data are output from txd1 pin when sclk input becomes active while data are written in the transmission buffer by cpu.
130 toshiba corporation TMP96C031N/f receiving in sclk output mode, synchronous clock is output from sclk pin and the data is shifted in the receiving buffer 1 whenever the receive interrupt ?ag intes1 is cleared by reading the received data. when 8-bit data are received, the data will be trans- ferred in the receiving buffer 2 (sc1buf) at the timing shown below, and intes1 will be set again to generate intrx1 interrupt. figure 3.10 (21). receiving operation in i/o interface mode (sclk output mode) in sclk input mode, the data is shifted in the receiving buffer 1 when sclk input becomes active, while the receive interrupt ?g intes1 is cleared by read- ing the received data. when 8-bit data is received, the data will be shifted in the receiving buffer 2 (sc1buf) at the timing shown below, and intes1 will be set again to generate intrx interrupt. figure 3.10 (22). receiving operation in i/o interface mode (sclk input mode) note: for data receiving, the system must be placed in the receive enable state (scmod = ??
toshiba corporation 131 TMP96C031N/f note: x; dont care ? no change 76543210 p9crl 11 select p60 as the txd pin. sc0mod x0x0101 set 7-bit uart mode. sc0cr x11xxx00 add an even parity. br0cr 0x100101 set transfer rate at 2400 bps. trun x x 1 start the prescaler for the baud rate generator. intes0 1100 enable inttx0 interrupt and sets interrupt level 4. sc0buf ******** set data for transmission. (2) mode 1 (7-bit uart mode) the 7-bit mode can be set by setting serial channel mode register sc0mod /sc1mod to ?1? in this mode, a parity bit can be added, and the addi- tion of a parity bit can be enabled or disabled by serial channel control register sc0cr /sc1cr , (3) mode 2 (8-bit uart mode) the 8-bit uart mode can be speci?d by setting sc0mod / sc1mod to ?0? in this mode, parity bit can be added, the addition of a parity bit is enabled or disabled by sc0cr / sc1cr , and even parity or odd parity is selected by sc0cr /sc1cr when is set to ??(enable). setting example: when receiving data with the follow- ing format, the control register should be set as described below. and even parity or odd parity is selected by sc0cr /sc1cr when is set to ?? (enable). setting example: when transmitting data with the fol- lowing format, the control registers should be set as described below. channel 0 is explained here.
132 toshiba corporation TMP96C031N/f note: x; dont care ? no change main setting 76543210 p9crl 00 select p61 (rxd) as the input pin. sc0mod 01x1001 enable receiving in 8-bit uart mode. sc0cr x01xxx00 add an odd parity. br0cr 0x010101 set transfer rate at 9600 bps. trun x x 1 start the prescaler for the baud rate generator. intes0 1100 enable inttx0 interrupt and sets interrupt level 4. interrupt processing acc sc0cr and 00011100 if acc 0 then error acc sc0buf read the received data. ) check for error. (4) mode 3 (9-bit uart mode) 9-bit uart mode can be speci?d by setting sc0mod /sc1mod to ?1? in this mode, parity bit cannot be added for transmission, the msb (9th bit) is written in scm0d , while in receiving it is stored in sccr . for writing and reading the buffer, the msb is read or written ?st, then sc0buf/sc1buf. w ake-up function in 9-bit uart mode, the wake-up function of slave controllers is enabled by setting sc0mod / sc1mod to ?? the interrupt intrx1/intrx0 occurs only when = 1 . figure 3.10 (23). serial link using wake-up function
toshiba corporation 133 TMP96C031N/f protocol select the 9-bit uart mode for master and slave controllers. set sc0mod /sc1mod bit of each slave controller to 1 to enable data receiving. a the master controller transmits one-frame data including the 8-bit select code for the slave control- lers. the msb (bit 8) is set to 1. ? each slave controller receives the above frame, and clears wu bit to 0 if the above select code matches its own select code. ? the master controller transmits data to the specified slave controller whose sc0mod / sc1mod bit is cleared to 0. the msb (bit 8) is cleared to 0. ? the other slave controllers (with the bit remain- ing at 1) ignore the receiving data because their msbs (bit 8 or ) are set to 0 to disable the interrupt intrx0/intrx1. the slave controllers (wu = 0) can transmit data to the master controller, and it is possible to indicate the end of data receiving to the master controller by this transmission.
134 toshiba corporation TMP96C031N/f setting example: to link two slave controllers serially with the master controller, and use the internal clock f 1 (fc/2) as the transfer clock. since serial channels 0 and 1 operate in exactly the same way, channel 0 is used for the purposes of explanation. setting the master controller setting the slave controller 2 main setting p6crl 0011 select p60 as txd pin and p61 as rxd pin. intes0 11001101 enable inttx0 and sets the interrupt level 4. enable intrx0 and sets the interrupt level 5. sc0mod 10101110 set f 1 (fc/2) as the transmission clock in 9-bit uart mode. sc0buf 00000001 set the select code for slave controller 1. inttx0 interrupt sc0mod ? set tb8 to ?? sc0buf ******** set data for transmission. main setting p6crl x x 01 select p61 as rxd pin and p60 as txd pin. ode xxxxxx1 intes0 11011110 enable intrx0 and inttx0. sc0mod 00111110 set to ??in the 9-bit uart transmission mode with transfer clock f 1 (fc/2). intrx0 interrupt acc sc0buf if acc = select code then sc0mod4 ? clear to ??
toshiba corporation 135 TMP96C031N/f 3.11 analog/digital converter the tmp96c031f contains a high-speed analog/digital con- verter (a/d converter) with 4- channel analog input that features 10-bit successive approximation. figure 3.11 (1). block diagram of a/d converter note1: this a/d converter does not have a built-in sample and hold circuit. therefore, when a/d converting high-frequency signals, connect a sample and hold circuit externally. note2: the lower the power supply current in idle or stop mode, depending on the timing, standby mode can be entered with the internal comparator in enable state. thus, stop a/d conversion before executing the halt instruction. the ladder resistor between vref- gnd cannot be disconnected internally. therefore, iref will ?w regardless of the mode. figure 3.11 (1) shows the block diagram of the a/d con- verter. the 4-channel analog input pins (an3 to an0) are shared by input-only p5 and so can be used as input port.
136 toshiba corporation TMP96C031N/f 3.11.1 control register figure 3.11 (2). a/d converter mode register (admod)
toshiba corporation 137 TMP96C031N/f figure 3.11 (3). register for saving an a/d switch value (adreg0 ~ 3)
138 toshiba corporation TMP96C031N/f 3.11.1 operation (1) analog reference voltage high analog reference voltage is applied to the vref pin. the reference voltage between vreg and agnd is divided by 256 using ladder resistance, and compared with the analog input voltage for a/d conversion. (2) analog input channels analog input channel is selected by admod . however, in ?ed analog input mode, one channel is selected by admod among four pins: an0 to an3. in analog input channel scan mode, the number of channels to be scanned from an0 is speci?d by admod , such as an0 ? an1, an0 ? an1 ? an2, and an0 ? an1 ? an2 ? an3. when reset, a/d conversion channel register will be ini- tialized to admod = 00, so that an0 pin will be selected. the pins which are not used as analog input channel can be used as ordinary input port p5. (3) starting a/d conversion a/d conversion starts when a/d conversion register admod is written ?". when a/d conversion starts, a/d conversion busy ?g admod which indicates ?/d conversion is in progress?will be set to ?". (4) a/d conversion mode both ?ed a/d conversion channel mode and a/d con- version channel scan mode have two conversion modes, i.e., single and repeat conversion modes. in ?ed channel repeat mode, conversion of speci?d one channel is executed repeatedly. in scan repeat mode, scanning from an0, ? an3 is executed repeatedly. a/d conversion mode is selected by admod . (5) a/d conversion speed selection there are two a/d conversion speed modes: high speed mode and low speed mode. the selection is executed by admod register. when reset, admod will be initialized to ?,? so that high speed conversion mode will be selected. (6) a/d conversion end and interrupt a/d conversion single mode admod for a/d conversion end will be set to ?,?admod ?g will be reset to ?,?and intad interrupt will be enabled when a/d conversion of speci?d channel ends in ?ed conversion channel mode or when a/d conversion of the last channel ends in channel scan mode. (7) storing the a/d conversion result the results of a/d conversion are stored in adreg0 to adreg3 registers for each channel. in repeat mode, the registers are updated whenever conversion ends. adreg0 to adreg3 are read-only registers. (8) reading the a/d conversion result the results of a/d conversion are stored in adreg0 to adreg3 registers. when the contents of one of adreg0 to adreg3 registers are read, admod will be cleared to ?". setting example: when the analog input volt- age of the an3 pin is a/d converted and the result is stored in the memory address ff10h by a/d interrupt intad routine.
toshiba corporation 139 TMP96C031N/f main setting inte0ad ? 1100 xxxx enable intad and sets interrupt level 4. admod ? xx000111 specify an3 pin as an analog input channel and starts a/d conversion in high speed mode. intad routine a ? adreg3 the value of adreg3 is read into the accumulator. then the accumulator value is stored into memory at ff10h. (ff10h) ? a setting example: ? when the analog pin voltage of an0 ~ an2 pin is a/d converted in high speed conversion channel scan repeat mode. note: x; dont care ? no change inte0ad ? 100xxxxx disable intad. admod ? xx110110 start the a/d conversion of analog input channels an0 ~ an2 in the high-speed scan repeat mode. 3.12 watchdog timer (runaway detecting timer) the tmp96c031f is containing watchdog timer of runaway detecting. the watchdog timer (wdt) is used to return the cpu to the normal state when it detects that the cpu has started to malfunction (runaway) due to causes such as noise. when the watchdog timer detects a malfunction, it generates a non- maskable interrupt to notify the cpu of the malfunction, and outputs 0 externally from watchdog timer out pin wdtout to notify the peripheral devices of the malfunction. connecting the watchdog timer output to the reset pin internally forces a reset. a built-in function is used to stop the wdt count at bus release request (busrq).
140 toshiba corporation TMP96C031N/f 3.12.1 con?uration figure 3.12 (1) shows the block diagram of the watchdog timer (wdt). figure 3.12 (1). block diagram of watchdog timer
toshiba corporation 141 TMP96C031N/f the watchdog timer is a 22-stage binary counter which uses f (fc/2) as the input clock. there are four outputs from the binary counter: 2 16 /fc, 2 18 /fc, 2 20 /fc, and 2 22 /fc. selecting one of the outputs with the wdmod register generates a watch- dog interrupt, and outputs watchdog timer out when an over- ?w occurs. since the watchdog timer out pin (wdtout ) outputs ?? due to a watchdog timer over?w, the peripheral devices can be reset. clearing the watchdog timer (by writing the clear code (4eh) to the wdcr) after disabling it sets 0 to output to 1 (pro- gram example). ldw (wdmod), 0b100h ; disables watchdog timer ld (wdcr), 4eh ; writes clear code set 7, (wdmod) ; enables watchdog timer again. in other words, the wdtout keeps outputting ??until the clear code is written. the watchdog timer out pin can also be connected to the reset pin internally. in this case, the watchdog timer out pin (wdtout ) outputs 0 at 8 to 20 states (800ns to 2.0 m s @ 20mhz) and resets itself. the wdtout (also used as p67) is multiplexed with pin pg13; setting must be done using the port 6 control register, p6crh (wdtout pin is set after reset). figure 3.12 (2). normal mode figure 3.12 (3). reset mode
142 toshiba corporation TMP96C031N/f 3.12.2 control registers watchdog timer wdt is controlled by two control registers wdmod and wdcr. (1) watchdog timer mode register (wdmod) setting the detecting time of watchdog timer this 2-bit register is used to set the watchdog timer interrupt time for detecting the runaway. this register is initialized to wdmod = 00 when reset, and therefore 2 16 /fc is set. (the number of states is approximately 32,768.) watchdog timer enable/disable control register when reset, wdmod is initialized to ?? enable the watchdog timer. disable control wdmod ? 0? x clear wdmod to ?". wdcr ? 10110001 write the disable code (b1h). enable control set wdmod to ?". watchdog timer clear control the binary counter can be cleared and resume count- ing by writing clear code (4eh) into the wdcr register. wdcr ? 01001110 write the clear code (4eh). to disable, it is necessary to clear this bit to ??and write the disable code (b1h) in the watchdog timer control register wdcr. this makes it dif?ult for the watchdog timer to be disabled by runaway. however, it is possible to return from the disable state to enable state by merely setting to ?". watchdog timer out reset connection this register is used to connect the output of the watchdog timer with reset terminal, internally. since wdmod is initialized to 0 at reset, a reset by the watchdog timer will not be performed. (2) watchdog timer control register (wdcr) this register is used to disable and clear the binary counter of the watchdog timer function.
toshiba corporation 143 TMP96C031N/f figure 3.12 (4). watchdog timer mode register
144 toshiba corporation TMP96C031N/f figure 3.12 (5). watchdog timer control register figure 3.12 (6)
toshiba corporation 145 TMP96C031N/f 3.12.3 operation the watchdog timer generates interrupt intwd after the detecting time set in the wdmod register and outputs a low level signal. the watchdog timer must be zero- cleared by software before an intwd interrupt is generated. if the cpu malfunctions (runaway) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter over?ws and an intwd interrupt is generated. the cpu detects malfunction (runaway) due to the intwd interrupt and it is possible to return to normal oper- ation by an anti-malfunction program. by connecting the watchdog timer out pin to peripheral devices?resets, a cpu malfunction can also be acknowledged to other devices. the watchdog timer restarts operation immediately after resetting is released. the watchdog timer stops its operation in the idle and stop modes. in the run mode, the watchdog timer is enabled. however, the function can be disabled when entering the run mode. example: clear the binary counter set the watchdog timer detecting time to 2 18 /fc disable the watchdog timer set idle mode set the stop mode (warming up time: 2 16 /fc) wdcr ? 01001110 write clear code (4eh). wdmod ? 101? x wdmod ? 0? x clear wdte to ?". wdcr ? 10110001 write disable code (b1h). wdmod ? 0 1 0 x x disables wdt and sets idle mode. wdcr ? 10110001 executes halt command set the standby mode wdmod ? 101xx set the stop mode. executes halt command execute halt instruction. set the standby mode. 2) writing 1 to the p4fc register halts count by the wdt binary counter at bus release due to the bus request signal, busrq.
146 toshiba corporation TMP96C031N/f 3.13 dynamic ram (dram controller the tmp96c031f consists of a control circuit to refresh dram, an access circuit to perform read/write, and an address decoder. figure 3.13 (1) shows a block diagram of the dram controller. figure 3.13 (1). dram controller 3.13.1 control register figure 3.13 (2). chip select wait control register (b3cs)
toshiba corporation 147 TMP96C031N/f figure 3.13 (3). port 4 function register
148 toshiba corporation TMP96C031N/f figure 3.13 (4). refresh control register
toshiba corporation 149 TMP96C031N/f 3.13.2 operation description (1) read/write control the read/write controller outputs valid signals ras and cas to dram when address space speci?d by the internal address decoder (chip select 2 cs3 /cas ) is accessed. in addition, a dmux signal is output for row address/ column address switching. figure 3.13 (6) shows the ras , cas , and dmux out- put timing diagram during memory access cycle. figure 3.13 (5). memory access cycle timing
150 toshiba corporation TMP96C031N/f how to set the registers is described next. ? setting the ras , cas , dmux , and rfsh output figure 3.13 (2) shoes the structure of the chip select wait control register b3cs. b3cs can be used to control the output of cs3 /cas and b3cs can be used to control cas selection. figure 3.13 (6). relationship between address decoder and dram controller the ras , cas , dmux , and rfsh signals must be set with the corresponding port control register because they are multiplexed with p35, p43, p71, and p63 respectively. ? inserting wait wait insertion during read/write control can be set with the register b3cs .
toshiba corporation 151 TMP96C031N/f (2) refresh controller the tmp96c031f can output ras /cas used to refresh in dram. at the same time the state signal rfsh which indicates a refresh cycle is output. dram can be refreshed easily because ras /cas out- put frequency and pulse width are programmable. the refresh controller has the following features. refresh mode: cas before ras interval refresh mode cas before ras self refresh mode refresh interval: 15 to 154 states (programmable) refresh cycle width: 2 to 9 states (programmable) dummy cycle can be generated refresh cycle is asynchronous with cpu operation cycle. i) cas before ras interval refresh mode the refresh interval and refresh width for cas before ras interval refresh mode depends on the dram being used. therefore, tmp96c031f enables the cas before ras output to be set with the refresh controller register value according to the system clock and dram that are being used. figure 3.13 (2) shows a timing example for cas before ras refresh cycle. figure 3.13 (7). refresh cycle timing example how to set the register is described next. figure 3.13 (4) shows the bit structure of the refresh con- trol register drefcr. refresh cycle insertion interval the insertion interval is set with the three bits drefcr according to the system clock being used. example: when the system clock is 20mhz and the dram refresh cycle is to be 16 m s, set these bits to ?11?
152 toshiba corporation TMP96C031N/f table 3.13 refresh cycle insertion interva l ? the three bits drefcr can used to change the refresh cycle width (ras , cas output). (2 to 9 states) ? refresh cycle control the refresh cycle can be disabled/enable with the bit drefcr . ii) cas before ras self refresh mode this mode is used when cpu or dram control is halted with a halt (idel, stop) instruction while refreshing with cas before ras interval refresh mode (hereafter referred to as interval mode). however, rfsh is not output. (??is output.). figure 3.13 (8) shows the self refresh mode timing dia- gram. figure 3.13 (8). self refresh cycle timing this mode is executed as follows. first, the settings are made for normal interval mode then, b3cs is set to ??just before a halt instruction to perform one normal refresh. then, the cas pin and ras pin are kept at low level and self refresh mode is entered. set b3cs to ??to cancel this mode and return to normal cas before ras refresh mode. (the ?st cas before ras refresh is performed immediately after cancellation because the refresh counter is cleared.)
toshiba corporation 153 TMP96C031N/f (3) dram initialize the dram controller can generate consecutive cas before ras dummy cycles necessary when using dram. this is executed by setting drefcr bit to ??and cancelled by setting it to ?? (the bit need not be changed.) the dummy cycle width is ?ed to 4 states. figure 3.13 (9) shows the cas before ras dummy cycle timing. figure 3.13 (9). cas before ras dummy cycle timing (fixed to 4 states) 3.13.4 priority the dram refresh cycle may overlap with the dram read/ write cycle because it is not synchronized with the cpu oper- ating cycle. in this case, the dram controller gives priority to the cycle that starts operation ?st. if the priority is given to the refresh cycle, a wait is automatically inserted in the memory access cycle. figure 3.13 (8) shows the timing in this case.
154 toshiba corporation TMP96C031N/f figure 3.13 (101). timing diagram when refresh cycle is inserted in memory access cycle
toshiba corporation 155 TMP96C031N/f 3.13.4 connection example
156 toshiba corporation TMP96C031N/f 4. electrical characteristics 4.1 absolute maximum (tmp96c031f) symbol parameter rating unit v cc power supply voltage -0.5 ~ 6.5 v v in input voltage -0.5 ~ v cc + 0.5 v s iol output current (total) 100 ma s ioh output current (total) -100 ma pd power dissipation (ta = 70 c) 600 mw t solder soldering temperature (10s) 260 c t stg storage temperature -65 ~ 150 c t opr operating temperature -20 ~ 70 c
toshiba corporation 157 TMP96C031N/f note: i-dar is guaranteed for a total of up to 8 ports. 4.2 dc characteristics (tmp96c031f) v cc = 5v 10%, ta = -20 ~ 70 c (typical values are for ta = 25 c and v cc = 5v) symbol parameter min max unit test condition v il input low voltage (ad0-15) -0.3 0.8 v v il1 p2, p3, p4, p5, p6, p7, p8, p9 -0.3 0.3v cc v v il2 reset , nmi , into (p87) -0.3 0.25v cc v v il3 am8/ea -0.3 0.3 v v il4 x1 -0.3 0.2v cc v v ih input high voltage (ad0-15) 2.2 v cc + 0.3 v v ih1 p2, p3, p4, p5, p6, p7, p8, p9 0.7v cc v cc + 0.3 v v ih2 reset , nmi , into (p87) 0.75v cc v cc + 0.3 v v ih3 ea v cc - 0.3 v cc + 0.3 v v ih4 x1 0.8v cc v cc + 0.3 v v ol output low voltage 0.45 v i ol = 1.6ma v oh output high voltage 2.4 v i oh = -400 m a v oh1 0.75v cc v i oh = -100 m a v oh2 0.9v cc v i oh = - 20 m a i dar darlington drive current (8 output pins max.) -1.0 -3.5 ma v ext - 1.5v r ext = 1.1k w i li input leakage current 0.02 (typ) 5 m a 0.0 v in v cc i lo output leakage current 0.05 (typ) 10 m a 0.2 v in v cc - 0.2 i cc operating current (run) idle stop (ta = -20 ~ 70 c) stop (ta = 0 ~ 50 c) 30 (typ) 2.0 (typ) 0.2 (typ) 60 10 50 10 ma ma m a m a tosc = 20mhz 0.2 v in v cc - 0.2 0.2 v in v cc - 0.2 v stop power down voltage (@stop, ram back up) 2.0 6.0 v v il2 = 0.2v cc , v ih2 = 0.8v cc r rst reset pull up register 50 150 k w c io pin capacitance 10 pf tosc = 1mhz v th schmitt width reset , nmi , into (p50) 0.4 1.0 (typ) v r k pull down/up register 50 150 k w
158 toshiba corporation TMP96C031N/f ac measuring conditions output level: high 2.2v /low 0.8v, cl50pf (however cl = 100pf for ad0 ~ ad15, ad0 ~ ad23, ale, rd , wr , hwr , clk, cs0 ~ cs3 ) input level: high 2.4v /low 0.45v (ad0 ~ ad15) high 0.8vcc /low 0.2vcc (except for ad0 ~ ad15) 4.3 ac electrical characteristics (tmp96c031f) v cc = 5v 10%, ta = -20 ~ 70 c (4mhz ~ 20mhz) no. symbol parameter variable 16mhz 20mhz unit min max min max min max 1t osc osc. period (= x) 50 250 62.5 50 ns 2t clk clk width 2x - 40 85 60 .0 ns 3t ak a0 - 23 valid ? clk hold 0.5x - 20 11 .0 5 0 ns 4t ka clk valid ? a0 - 23 hold 1.5x - 70 24 0 5 0 ns 5t al a0-15 valid ? ale fall 0.5x - 15 16 0 10 0 ns 6t la ale fall ? a0 - 15 hold 0.5x - 15 16 0 10 0 ns 7t ll ale high width x - 40 23 .0 10 0 ns 8t lc ale fall ? rd /wr fall 0.5x - 30 1 .0 -5 ns 9t cl rd /wr rise ? ale rise 0.5x - 20 11 .0 5 0 ns 10 t acl a0 - 15 valid ? rd /wr fall x - 25 38 .0 25 0 ns 11 t ach a0 - 23 valid ? rd /wr fall 1.5x - 50 44 .0 25 .0 ns 12 t ca rd /wr rise ? a0 - 23 hold 0.5x - 20 11 .0 5ns 13 t adl a0 - 15 valid ? d0 - 15 input 3.0x - 45 143 105 ns 14 t adh a0 - 23 valid ? d0 - 15 input 3.5x - 65 154 110 ns 15 t rd rd fall ? d0 - 15 input 2.0x - 50 75 50 ns 16 t rr rd low width 2.0x - 40 85 .0 60 .0 ns 17 t hr rd rise ? d0 - 15 hold 0 0 .0 0 .0 ns 18 t rae rd rise ? a0 - 15 output x - 15 48 .0 35 .0 ns 19 t ww wr low width 2.0x - 40 85 .0 60 .0 ns 20 t dw d0 - 15 valid ? wr rise 2.0x - 50 75 .0 50 .0 ns 21 t wd wr rise ? d0 - 15 hold 0.5x - 10 21 .0 15 .0 ns 22 t aeh a0 - 23 valid ? w ait input (1wait + n mode) 3.5x - 90 129 85 ns 23 t awl a0 - 15 valid ? w ait input (1wait + n mode) 3.0x - 80 108 70 ns 24 t cw rd /wr fall ? w ait hold (1wait + n mode) 2.0x + 0 125 .0 100 .0 ns 25 t aph a0 - 23 valid ? port input 2.5x - 120 36 5 ns 26 t aph2 a0 - 23 valid ? port hold 2.5x + 50 206 .0 175 .0 ns 27 t cp wr rise ? port valid 200 200 200 ns
toshiba corporation 159 TMP96C031N/f (1) read cycle
160 toshiba corporation TMP96C031N/f (2) write cycle
toshiba corporation 161 TMP96C031N/f 4.4 dram control ac characteristics (tmp96c031f) v cc = 5v 10% ta = -20 ~ 70 c (4mhz ~ 20mhz) *1 cas before ras interval refresh mode *2 cas before ras self-refresh mode * both refresh modes ac measuring conditions output level: high 2.2v /low 0.8v, cl50pf (however cl = 100pf for ad0 ~ ad15, ad0 ~ ad23, rd , wr , hwr , r/w ras ) input level: high 2.4v /low 0.45v (ad0 ~ ad15) high 0.8vcc/low 0.2vcc (except for ad0 ~ ad15) no. symbol parameter variable 16mhz 20mhz unit min max min max min max 1t rc ras cycle time 4x - 10 240 190 ns 2t rac ras fall ? data input 2x - 20 105 80 ns 3t cac cas fall ? data input 1x - 25 38 25 ns 4t rp ras high pulse width 2x - 30 95 70 ns 5t ras ras low pulse width 2x - 10 115 90 ns 6t rsh cas fall ? ras rise 1x - 25 38 25 ns 7t csh ras fall ? cas rise 2x - 20 105 80 ns 8t cas cas low pulse width 1.5x - 10 84 65 ns 9t rcd ras fall ? cas fall 1x - 15 48 35 ns 10 t crp cas rise ? ras rise 1.5x - 50 44 25 ns 11 t rah ras fall ? a0 - 15 hold 0 0 0 ns 12 t asrl a 0 - 15 valid ? ras fall 1x - 10 53 40 ns 13 t asrh a 0 - 23 valid ? ras fall 1.5x - 10 84 65 ns 14 t rwl wr fall ? ras rise 2x - 50 75 50 ns 15 t cwl wr fall ? cas rise 2x - 50 75 50 ns 16 t ds data output ? cas fall setup 1x - 30 33 20 ns 17 t dh cas fall ? data output hold 1.5x - 50 44 25 ns 18 t dhr ras fall ? data output hold 2.5x - 50 106 75 ns 19 t wcs wr fall ? cas fall setup 1x - 30 33 20 ns 20 t wch cas fall ? wr hold 1x - 30 33 20 ns 21 t rdm ras fall ? dmux fall 0.5x - 10 21 15 ns 22 t cdm dmux fall ? cas fall 0.5x - 10 21 15 ns 23 t chr*1 ras fall ? cas rise 2x - 50 75 50 ns 24 t rpc* ras rise ? cas fall 1.5x + 0 64 45 ns 25 t cp* cas high pulse width 1.5x + 0 64 45 ns 26 t csr* cas fall ? ras fall 0.5x - 10 21 15 ns 27 t rass*2 ras low pulse width 2000x 125 100 ns 28 t rps*2 ras precharge time 4x - 20 230 180 ns 29 t chs*2 cas hold time 0 0 0 ns 30 t cfl* rfsh fall ? cas fall 1x - 10 53 40 ns 31 t cfh* cas rise ? rfsh rise 0.5x - 10 21 15 ns
162 toshiba corporation TMP96C031N/f (1) read/write access cycle (2) cas before ras interval refresh cycle (3) cas before ras self-refresh cycle
toshiba corporation 163 TMP96C031N/f 4.5 a/d conversion characteristics (tmp96c031f) v cc = 5v 10% ta = -20 ~ 70 c symbol parameter min typ max unit v ref analog reference voltage v cc - 1.5 v cc v a gnd analog reference voltage v ss v ss v ain analog input voltage range v ss v cc i ref analog current for analog reference voltage 0.5 1.5 ma error (quantize error of 0.5 lsb not included) total error (ta = 25 c, v cc = vref = 5.0v) 1.0 lsb total error 2.5 4.6 serial channel timing - i/o interface mode v cc = 5v 10% ta = -20 ~ 70 c (1) sclk input mode symbol parameter variable 16mhz 20mhz unit min max min max min max t scy sclk cycle 16x 1 0.8 m s t oss output data ? rising edge of sclk t scy /2 - 5x - 50 137 100 ns t ohs sclk rising edge ? output data hold 5x - 100 212 150 ns t hsr sclk rising edge ? input data hold 0 0 0 ns t srd sclk rising edge ? effective data input t scy - 5x - 100 587 450 ns (2) sclk output mode symbol parameter variable 16mhz 20mhz unit min max min max min max t scy sclk cycle (programmable) 16x 8192x 1 512 0.8 409.6 m s t oss output data ? rising edge of sclk t scy - 2x - 150 725 550 ns t ohs sclk rising edge ? output data hold 2x - 80 45 20 ns t hsr sclk rising edge ? input data hold 0 0 0 ns t srd sclk rising edge ? effective data input t scy - 2x - 150 725 550 ns 4.7 timer/counter input clock (ti0, ti4, ti5) v cc = 5v 10% ta = -20 ~ 70 c symbol parameter variable 16mhz 20mhz unit min max min max min max t vck clock cycle 8x + 100 600 500 ns t vckl low level clock pulse width 4x + 40 290 240 ns t vckh high level clock pulse width 4x + 40 290 240 ns
164 toshiba corporation TMP96C031N/f 4.8 interrupt operation v cc = 5v 10% ta = -20 ~ 70 c symbol parameter variable 16mhz 20mhz unit min max min max min max t intal nmi , int0 low level pulse width 4x 250 200 ns t intah nmi , int0 high level pulse width 4x 250 200 ns t intbl int1 ~ int7 low level pulse width 8x + 100 600 500 ns t intbh int1 ~ int7 high level pulse width 8x + 100 600 500 ns
toshiba corporation 165 TMP96C031N/f 4.9 timing chart for i/o interface mode
166 toshiba corporation TMP96C031N/f 4.10 timing chart for bus request/bus acknowledge note 1: the bus will be released after the w ait request is inactive, when the busrq is set to ??during ?ait?cycle. note 2: an internal programmable pull-down resistor must be connected. note 3: an internal programmable pull-up resistor must be connected. symbol parameter variable 16mhz 20mhz unit min max min max min max t brc busrq setup time for clk 120 120 120 ns t cbal clk ? busak falling edge 1.5x + 120 214 220 ns t cbah clk ? busak rising edge 0.5x + 40 71 65 ns t aba output buffer is off to busak 0 80 080080ns t baa busak output buffer is on. 0 80 0 80 0 80 ns
toshiba corporation 167 TMP96C031N/f 5. table of special function registers (sfr; special function register) the special function registers (sfrs) include the i/o ports and peripheral control registers allocated to the 128-byte addresses from 000000h to 00007fh. (1) i/o port (2) i/o port control (3) timer control (4) pattern generator control (5) watch dog timer control (6) serial channel control (7) a/d converter control (8) interrupt control (9) chip select/wait control (10) dram control con?uration of the table
168 toshiba corporation TMP96C031N/f table 5 i/o register address map address name address name address name address name 000000h 20h trun 40h msar0 60h adreg0 1h 21h 41h mamr0 61h adreg1 2h 22h treg0 42h msar1 62h adreg2 3h 23h treg1 43h mamr1 63h adreg3 4h 24h t01tmod 44h msar2 64h 5h 25h tffcr 45h mamr2 65h 6h p2 26h treg2 46h msar3 66h 7h p3 27h treg3 47h mamr3 67h 8h p2cr 28h t23mod 48h 68h 9h p2fc 29h trdc 49h 69h b0cs ah p3crl 2ah 4ah 6ah b1cs bh p3crh 2bh 4bh drefcr 6bh b2cs ch p4 2ch 4ch pg0reg 6ch b3cs dh p5 2dh 4dh pg1reg 6dh eh 2eh 4eh pg01cr 6eh fh 2fh 4fh 6fh 10h p4fc 30h treg4l 50h sc0buf 70h inte01 11h 31h treg4h 51h sc0cr 71h inte23 12h p6 32h treg5l 52h sc0mod 72h inte45 13h p7 33h treg5h 53h br0cr 73h inte67 14h p6crl 34h cap1l 54h sc1buf 74h intet10 15h p7crl 35h cap1h 55h sc1cr 75h intet32 16h p6crh 36h cap2l 56h sc1mod 76h intet54 17h p7crh 37h cap2h 57h br1cr 77h intes0 18h 38h t4mod 58h ode 78h intes1 19h 39h tff4cr 59h 79h intead 1ah 3ah t45cr 5ah 7ah iimc0 1bh 3bh 5bh 7bh iimc1 1ch 3ch 5ch wdmod 7ch dma0v 1dh 3dh 5dh wdcr 7dh dma1v 1eh 3eh 5eh admod 7eh dma2v 1fh 3fh 5fh 7fh dma3v
toshiba corporation 169 TMP96C031N/f (1) i/o port read/write r/w ; either read or write is possible r ; only read is possible w ; only write is possible prohibit rwm ; prohibit read modify write. (prohibit res/set/tset/chg/stcf/andcf/orcf/xorcf instruction) symbol name address 76543210 p2 port2 06h p27 p26 p25 p24 p23 p22 p21 p20 r/w input mode 00000000 p3 port3 07h p35 p34 p33 p32 p31 p30 r/w 111111 input mode (pulled-up) p4 port4 0ch p43 p42 p41 p40 r/w 1011 output mode p5 port5 0dh p53 p52 p51 p50 r input mode p6 port6 12h p67 p66 p65 p64 p63 p62 p61 p60 r/w 11111111 input mode p7 port7 13h p76 p75 p74 p73 p72 p71 p70 r/w 1111111 input mode
170 toshiba corporation TMP96C031N/f (2) i/o port control (1/2) symbol name address 7 6 5 4 3 2 1 0 p2cr port2 control 08h (prohibit rmw) p27c p26c p25c p24c p23c p22c p21c p20c w 00000 000 < p2fc port2 function 09h (prohibit rmw) p27f p26f p25f p24f p23f p22f p21f p20f w 00000 000 p2fc/ p2cr = 00 : in, 01 : out, 10 : ? 11 : a23 - 16 p3crl port3 control low 0ah (prohibit rmw) p33c1 p33c0 p32c1 p32c0 p31c1 p31c0 p30c1 p30c0 w 00000 000 00 : port input 01 : port output 10 : busak 11 : 00 : port input 01 : port output 10 : busrq 11 : 00 : port input 01 : port output 10 : 11 : 00 : port input 01 : port output 10 : to5 11 : hwr p3crh port3 control high 0bh (prohibit rmw) rden p35c1 p35c0 p34c1 p34c0 ww 0 0 000 1 : pseudo sram en 00 : port input 01 : port output 10 : ras 11 : 00 : port input 01 : port output 10 : nmi 11 : r/w p4fc port4 function 10h (prohibit rmw) buswdt budrm p43f p42f p41f p40f ww w 00 0 000 00 : bussrq dis 01 : busrq en 0 : on 1 : off 00 : port 01 : cs3 /cas 00 : port 01 : cs2 00 : port 01 : cs1 00 : port 01 : cs0
toshiba corporation 171 TMP96C031N/f i/o port control (2/2) symbol name address 76543210 p6crl port6 control low 14h (prohibit rmw) p63c1 p63c0 p62c1 p62c0 p61c1 p61c0 p60c1 p60c0 w 00000000 00 : port input 01 : port output 10 : pg03 11 : rfsh 00 : port input 01 : port output 10 : pg02 11 : 00 : port input 01 : port output 10 : pg01 11 : 00 : port input 01 : port output 10 : pg00 11 : txd0 p6crh port6 control high 15h (prohibit rmw) p67c1 p67c0 p66c1 p66c0 p65c1 p65c0 p64c1 p64c0 w 00000000 00 : port input 01 : port output 10 : pg13 11 : wdtout 00 : port input 01 : port output 10 : pg12 11 : 00 : port input 01 : port output 10 :pg11 11 : 00 : port input 01 : port output 10 : pg10 11 : p7crl port7 control low 16h (prohibit rmw) p73c1 p73c0 p72c1 p72c0 p71c1 p71c0 p70c1 p70c0 w 00000000 00 : port input 01 : port output 10 : 11 : 00 : port input 01 : port output 10 : 11 : 00 : port input 01 : port output 10 : to3 11 : dmux 00 : port input 01 : port output 10 : to1 11 : to4 p7crh port7 control high 17h (prohibit rmw) p76c1 p76c0 p75c1 p75c0 p74c1 p74c0 w 000000 00 : port input 01 : port output 10 : sclk1 11 : 00 : port input 01 : port output 10 : 11 : 00 : port input 01 : port output 10 : txd1 11 :
172 toshiba corporation TMP96C031N/f (3) timer control (1/3) symbol name address 76543210 trun timer run control reg. 20h t5run t4run p1run p0run t1run t0run r/w 000000 prescaler and timer run/stop control 0 : stop and clear 1 : run (count up) treg0 8bit timer register 0 22h (prohibit rmw) w unde?ed treg1 8bit timer register 1 23h (prohibit rmw) w unde?ed t01tmod 8bit timer source clk and mode 24h (prohibit rmw) t10m1 t10m0 pwmm1 pwmm0 t1clk1 t1clk0 t0clk1 t0clk0 w 00000000 00 : 8-bit timer 01 : 16-bit timer 10 : 8-bit ppg 11 : 8-bit pwm 00 : 01 : 2 6 - 1 pwm 10 : 2 7 - 1 cycle 11 : 2 8 - 1 00 : to0trg 01 : f t1 10 : f t16 11 : f t256 00 : ti0 input 01 : f t1 10 : f t4 11: f t16 tffcr 8bit timer flip-?p control 25h tff3c1 tff3c0 tff3ie tff3is tff1c1 tff1c0 tff1ie tff1is w r/w w r/w ?0?0 00 : invert tff3 01 : set tff3 10 : clear tff3 11 : don? care 1 : tff3 invert enable 0 : timer 2 1 : timer 3 00 : invert tff1 01 : set tff1 10 : clear tff1 11 : don? care 1 : tff1 invert enable 0 : timer 0 1 : timer 1 treg2 pwm timer register 2 26h w unde?ed treg3 pwm timer register 3 27h w unde?ed t23mod timer 2, 3 hode reg. 28h (prohibit rmw) t23m1 t23m0 pwm21 pwm20 t3clk1 t3clk0 t2clk0 t2clk0 r/w 00000000 00 : 8-bit timer 01 : 16-bit timer 10 : 8-bit ppg 11 : 8-bit pwm 00 : 01 : 2 6 - 1 pwm 10 : 2 7 - 1 cycle 11 : 2 8 - 1 00 : to2trg 01 : f t1 10 : f t16 11 : f t256 00 : ti0 input 01 : f t1 10 : f t4 11: f t16 trdc timer reg. double buffer control reg. 29h tr2de tr0de r/w 00 tmer reg. double buffer control 0 : double buffer disable 1 : double buffer enable
toshiba corporation 173 TMP96C031N/f (3) timer control (2/3) symbol name address 76543210 treg4l 16bit timer register 4l 30h (prohibit rmw) w unde?ed treg4h 16bit timer register 4h 31h (prohibit rmw) w unde?ed treg5l 16bit timer register 5l 32h (prohibit rmw) w unde?ed treg5h 16bit timer register 5h 33h (prohibit rmw) w unde?ed cap1l capture register 1l 34h r unde?ed cap1h capture register 1h 35h r unde?ed cap2l capture register 2l 36h r unde?ed cap2h capture register 2h 37h r unde?ed t4mod 16bit timer 4 source clk and mode 38h cap2t5 eq5t5 cap1in cap12m1 cap12m0 cle t4clk1 t4clk0 r/w w r/w 00000000 tff5 inv trg o : trg disable 1: trg enable 0 : soft- capture 1 : don? care capture timing 00 : disable 01 : t14 - ti5 - 10 : t14 - t14 - 11 : tff1 - tff1 1 : uc4 clear enable source clock 00 : ti4 01 : f t1 10 : f t4 11 : f t16
174 toshiba corporation TMP96C031N/f (3) timer control (3/3) (4) pattern generator (5) watch dog timer symbol name address 7654 3 210 t4ffcr 16bit timer 4 flip-?p control 39h tff5c1 tff5c0 cap2t4 cap1t4 eq5t4 eq4t4 tff4c1 tff4c0 w r/w w 0000 0 000 00 : invert tff5 01 : set tff5 10 : clear tff5 11 : don? care tff4 invert trigger 0 : trigger disable 1 : trigger enable source clock 00 : invert tff4 01 : set tff4 10 : clear tff4 11 : don? care t45cr t4, t5 control 3ah pg1t pg0t db4en r/w r/w 0000 fix at ? pg1 shift trigger 0 : timer 0, 1 1 : timer 4 pg0 shift trigger o : timer 2,3 1 : timer 4 1 : double buffer enable symbol name address 76543210 pg0reg pgo register 4ch (prohibit rmw) pg03 pg02 pg01 pg00 sa03 sa02 sa01 sa00 w r/w 0000 unde?ed pg1reg pg1 register 4dh (prohibit rmw) pg13 pg12 pg11 pg10 sa13 sa12 sa11 sa10 w r/w 0000 unde?ed pg01cr pg0, 1 control 4eh pat1 ccw1 pg1m pg1te pat0 ccw0 pg0m pg0te r/w 00000000 0 : 8-bit write 1 : 4-bit write 0 : normal rotation 1 : reverse rotation 0 : 4-bit step 1 : 8-bit step pg1 trigger input enable 1 : enable 0 : 8-bit write 1 : 4-bit write 0 : normal rotation 1 : reverse rotation 0 : 4-bit step 1 : 8-bit step pg0 trigger input enable 1 : enable symbol name address 76543210 wd- mod watch dog timer mode 5ch wdte wdtp1 wdtp0 warm haltm1 haltm0 rescr drve r/w 10000000 1 : wdt enable 00 : 2 16 /fc 01 : 2 18 /fc 10 : 2 20 /fc 11 : 2 22 /fc warming up time 0 : 2 14 /fc 1 : 2 16 /fc standby mode 00 : run mode 01 : stop mode 10 : idle mode 11 : don? care 1 : connect internally wdt out pin to reset pin 1 : drive the pin in stop mode wdcr watch dog timer control register 5dh w unde?ed b1h : wdt disable code 4eh : wdt clear code
toshiba corporation 175 TMP96C031N/f (6) serial channel (1/2) symbol name address 76543210 sc0buf serial channel 0 buffer 50h rb7 tb7 rb6 tb6 rb5 tb5 rb4 tb4 rb3 tb3 rb2 tb2 rb1 tb1 rb0 tb0 r (receiving)/w (transmission) unde?ed sc0cr serial channel 0 control 51h rb8 even pe oerr perr ferr r r/w r (cleared to 0 by reading) r/w 0000000 receiving data bit 8 parity 0 : odd 1 : even 1 : parity enable 1 : error fix at ? fix at ? overrun parity framing sc0- mod serial channel 0 mode 52h tb8 ctse rxe wu sm1 sm0 sc1 sc0 r/w 00000000 transmission data bit 8 1 : cts enable 1 : receive enable 1 : wake up enable 00 : unused 01 : uart 7-bit 10 : uart 8-bit 11 : uart 9-bit 00 : to0 trigger 01 : baud rate generator 10 : internal clock f 1 11 : don?t care br0cr baud rate control 53h e br0ck1 br0ck0 br053 br052 br051 br050 r/w r/w 0 000000 fix at 0 00 : f t0 (fc/4) 01 : f t2 (fc/16) 10 : f t8 (fc/64) 11 : f t32 (fc/256) set frequency divisor 0 ~ f (1 prohibited) sc1buf serial channel 1 buffer 54h rb7 tb7 rb6 tb6 rb5 tb5 rb4 tb4 rb3 tb3 rb2 tb2 rb1 tb1 rb0 tb0 r (receiving)/w (transmission) undetned sc1cr serial channel 1 control 55h rb8 even pe oerr perr ferr sclks ioc r r/w r (cleared to 0 by reading) r/w 0000000 receiving data bit 8 parity 0 : odd 1 : even 1 : parity enable 1 : error 1 : input sclk1 pin overrun parity framing sc1- mod serial channel 1 mode 56h tb8 e rxe wu sm1 sm0 sc1 sc0 r/w 00000000 transmission data bit 8 fix at 0 1 : receive enable 1 : wake up enable 00 : i/o interface 01 : uart 7-bit 10 : uart 8-bit 11 : uart 9-bit 00 : to0 trigger 01 : baud rate generator 10 : internal clock f 1 11 : don?t care
176 toshiba corporation TMP96C031N/f (7) a/d converter control br1cr baud rate control 57h br1ck1 br1ck0 br153 br152 br151 br150 r/w r/w 0 000000 fix at ? 00 : f t0 (fc/4) 01 : f t2 (fc/16) 10 : f t8 (fc/64) 11 : f t32 (fc/256) set frequency divisor 0 ~ f (1 prohibited) ode special open drain enable 58h ode1 ode0 r/w 00 1 : p74 open-drain 1 : p60 open-drain symbol name address 76543210 admod a/d converter mode reg. 5eh eocf adbf repet scan adcs ads adch1 adch0 r r/w r/w r/w r/w 00000000 1 : end 1 : busy 1 : repeat mode set 1 : scan mode 1 : slow mode 1 : start analog input channel select adreg0 ad result reg. 0 60h r unde?ed adreg1 ad result reg. 1 61h r unde?ed adreg2 ad result reg. 2 62h r unde?ed adreg3 ad result reg. 3 63h r unde?ed symbol name address 76543210 (6) serial channel (2/2)
toshiba corporation 177 TMP96C031N/f (8) interrupt control (1/2)
178 toshiba corporation TMP96C031N/f (8) interrupt control (2/2) symbol name address 76543210 dma0v dma 0 request vector 7ch (prohibit rmw) m dma0 start vector dma0v8 dma0v7 dma0v6 dam0v5 dma0v4 w 00000 dma1v dma 1 request vector 7dh (prohibit rmw) m dma1 start vector dma01v8 dma1v7 dma1v6 dam1v5 dma1v4 w 00000 dma2v dma 2 request vector 7eh (prohibit rmw) m dma2 start vector dma2v8 dma2v7 dma2v6 dam2v5 dma2v4 w 00000 dma3v dma 3 request vector 7fh (prohibit rmw) m dma3 start vector dma3v8 dma3v7 dma3v6 dam3v5 dma3v4 w 00000 iimc0 interrupt input mode control 0 7ah (prohibit rmw) i4ie i3ie i2ie i1ie i1em i0ie i0le nmiree w 00000000 1 : int4 input enable 1 : int3 input enable 1 : int2 input enable 1 : int1 input enable 0 : into rising edge 1 : int1 falling edge 1 : int0 input enable 0 : into edge mode 1 : into level mode 1 : operate even at nmi rise edge iimc1 interrupt input mode control 1 7bh (prohibit rmw) i7ie i6le i5ie w 000 1 : int7 input enable 1 : int6 input enable 1 : int5 input enable
toshiba corporation 179 TMP96C031N/f (9) chip select/wait controller (1/2) symbol name address 7 6 5 4 3210 b0cs block 0 cs/wait control register 68h (prohibit rmw) b0e b0sys b0are b0bus b0w1 b0w0 b0c1 b0c0 w 00000000 0 : cs0 dis 1 : cs0 en 1 : system only 0 : 7f00 ~ 7fff 1 : address area speci?ation 0 : 16-bit bus 1 : 8-bit bus 00 : 2wait 01 : 1wait 10 : 1wait + n 11 : 0wait 00 : 2wait 01 : 1wait 10 : 1wait + n 11 : 0wait b1cs block 1 cs/wait control register 69h (prohibit rmw) b1e b1sys b1are b1bus b1w1 b1w0 w 000000 0 : cs1 dis 1 : cs1 en - 0 : 80 ~ 7fff 1 : address area specitcation -- ee b2cs block 2 cs/wait control register 6ah (prohibit rmw) b2e b2sys b2are b2bus b2w1 b2w0 w 1 0 0 undetned 0 0 0 : cs0 dis 1 : cs0 en - 0 : 8000 ~ 3fffff 1 : address area specitcation -- ee b3cs block 3 cs/wait control register 68h (prohibit rmw) b3e b3sys b3are b3bus b3w1 b3w0 b3cas srfc w 00000000 0 : cs3 /cas dis 1 : cs3 /cas en - 0 : undetned 1 : address area specitcation -- 0 : cs3 /cas dis 1 : cs3 /cas en 0 : self refresh execution 1 : release msar0 memory start adrress reg. 0 40h s23 s22 s21 s20 s19 s18 s17 s16 r/w 11111111 a23 ~ a16 memory start address setting mamr0 memory start adrress mask reg. 0 41h v20 v19 v18 v17 v16 v15 v14 ~ 9 v8 r/w 11111111 0: address a8 ~ a20 comparison is valid. 1: address a8 ~ a20 comparison is invalid. (specitcation bit by bit). msar1 memory start adrress reg. 1 42h s23 s22 s21 s20 s19 s18 s17 s16 r/w 11111111 a23 ~ a16 memory start address setting
180 toshiba corporation TMP96C031N/f mamr1 memory start adrress mask reg. 1 43h v21 v20 v19 v18 v17 v16 v15 ~ 9 v8 r/w 11111111 0: address a8 ~ a21 comparison is valid. 1: address a8 ~ a21 comparison is invalid. (speci?ation bit by bit). msar2 memory start adrress reg. 2 44h s23 s22 s21 s20 s19 s18 s17 s16 r/w 11111111 a23 ~ a16 memory start address setting mamr2 memory start adrress mask reg. 2 45h v22 v21 v20 v19 v18 v17 v16 v15 r/w 11111111 0: address a15 ~ a22 comparison is valid 1: address a15 ~ a22 comparison is invalid. (speci?ation bit by bit). msar3 memory start adrress reg. 3 46h s23 s22 s21 s20 s19 s18 s17 s16 r/w 11111111 a23 ~ a16 memory start address setting mamr3 memory start mask adrress reg. 3 46h v22 v21 v20 v19 v18 v17 v16 v15 r/w 11111111 0: address a15 ~ a22 comparison is valid 1: address a15 ~ a22 comparison is invalid. (speci?ation bit by bit). symbol name address 7 6 5 4 3210 (9) chip select/wait controller (2/2)
toshiba corporation 181 TMP96C031N/f (10) dram control symbol name address 7 6 5 4 3 2 1 0 drefcr refresh control reg. 48h dmi rs2 rs1 rs0 rw2 rw1 rw0 rc r/w 0 0000000 dummy cycle 0 : prohibit 1 : execute refresh cycle insertion interval 000 : 15 states 001 : 31 states 010 : 62 states 011 : 78 states 100 : 97 states 101 : 109 states 110 : 124 states 111 : 154 states refresh cycle insertion interval 000 : 2 states 001 : 3 states 010 : 4 states 011 : 5 states 100 : 6 states 101 : 7 states 110 : 8 states 111 : 9 states refresh cycle 0 : prohibit 1 : execute
182 toshiba corporation TMP96C031N/f 6. port section equivalent circuit diagram reading the circuit diagram basically, the gate singles written are the same as those used for the standard cmos logic ic [74hcxx] series. the dedicated signal is described below. stop: this signal becomes active ??when the hold mode setting register is set to the stop mode and the cpu executes the halt instruction. when the drive enable bit [drive] is set to ?? however, stp remains at ?? the input protection resistans ranges from several tens of ohms to several hundreds of ohms. po (ad0 ~ ad7), p1 (ad8 ~ 15, a8 ~ 15), p2 (a16 ~ 23) ?d , wr p30 ~ 33, p35
toshiba corporation 183 TMP96C031N/f p61 ~ p67, p70 ~ p73, p75 ~ p76 p50 (an0/int0) p51 ~ p53 (an1 ~ 3/int1 ~ 3) vcc
184 toshiba corporation TMP96C031N/f p60 (txd0), p74 (txd1) p34 (nmi /r/w ) p40~ p43 (cs0 ~ cs3 /cas)
toshiba corporation 185 TMP96C031N/f clk am8/16 reset x1, x2 vref
186 toshiba corporation TMP96C031N/f 7. guidelines and restrictions (1) special expression explanation of a built-in i/o register: register symbol ex) trun . . . bit t0run of register trun read, modify and write instruction an instruction which cpu executes following by one instruction. 1. cpu reads data of the memory. 2. cpu modites the data. 3. cpu writes the data to the same memory. ex1) set 3, (trun) . . . set bit3 of trun ex2) inc1, (100h) increment the data of 100h the representative read, modify and write instruction in the tlcs-900 set imm, mem, res imm, mem chg imm, mem, tset imm, mem inc imm, mem, dec imm, mem rld a, mem, add imm, reg a 1 state one cycle clock divided by 2 oscillation frequency is called 1 state ex) oscillation frequency is 20mhz 2/20mhz = 100ns = 1 state (2) guidelines am8/16 pin fix these pins vcc or gnd unless changing voltage. warming-up counter the warming-up counter operates when the stop mode. is released even the system which is used an external oscillator. as a result, it takes warming up time from inputting the releasing request to outputting the system clock. a programmable pull up/down resistance the programmable pull up/down resistors can be selected on/off by program when they are used as the input ports. the case of they are used as the out- put ports, they cannot be selected on/off by pro- gram. ? bus releasing function refer to the note about the bus release in 3.5 func- tions of ports because the pin state when the bus is released is written. ? watch dog timer the watch dog timer starts operation immediately after the reset is released. when the watch dog timer is not used, set watch dog timer to disable. ? cpu (high speed m dma) only the ldc cr, r, ldc r, cr instruction can be used to access the control register like transfer source address register (dmasn) in the cpu.

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