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downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm copyright 2001 pmc-sierra, inc. all rights reserved pmc-sierra 8555 baxter place burnaby, bc canada v5a4v7 phone 604.415.6000, fax 604.415.6200 the information is proprietary and confidential to pmc-sierra, inc., and for its customers ? internal use. in any event, no part of this document may be reproduced in any form without the express consent of pmc-sierra, inc. document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet PM2329 classipi network classification processor datasheet proprietary and confidential issue 4, november 2001
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 5 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet legal information copyright copyright 2001 pmc-sierra, inc. the information is proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. in any event, you cannot reproduce any part of this document, in any form, without the express written consent of pmc-sierra, inc. pmc-2010146 (r4) disclaimer none of the information contained in this document constitutes an express or implied warranty by pmc- sierra, inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. patents relevant patent applications and other patents may also exist . contacting pmc-sierra pmc-sierra, inc. 8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com technical support: apps@pmc-sierra.com web site: http://www.pmc-sierra.com
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm PM2329 classipi network classification processor datasheet proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 6 document id: pmc-2010146, issue 4 contents 1 PM2329 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4.1 algorithmic support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4.2 architectural support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4.3 software model support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4.4 policy search engine pse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.5 field extraction engine fee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.6 operation control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.6.1 operation cycles, descriptors and e-ram . . . . . . . . . . . . . . . . 19 1.5 system diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 signals listed by function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3 signals listed by ball . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4.1 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4.1.1 clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4.1.2 processor bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.4.1.2.1syncburst bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.4.1.2.2zbt bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.4.1.3 packet source interface signals . . . . . . . . . . . . . . . . . . . . . . . . 45 2.4.1.4 64-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.4.1.5 32-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.4.1.6 byte ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.4.1.7 cascade mode addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.4.1.8 local and global register access . . . . . . . . . . . . . . . . . . . . . . 49 2.4.1.9 multiple context support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.4.1.10 reset and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.4.2 extended ram (e-ram) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.4.3 cascade interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.5 system configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.5.1 stand alone configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.5.2 cascaded configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.5.3 operation with extended ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1 internal organization and data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 7 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 3.1.1 basic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.1.2 data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.1.3 context support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.1.4 channel input, output and status mechanism . . . . . . . . . . . . . . . . . . . 62 3.2 field extraction engine (fee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.2.2 supported packet formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.3 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.4 policy search engine (pse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.4.1 rule memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.4.2 cell organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.4.3 priority of rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.4.4 rule partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.5 e-ram operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.5.1 organization of e-ram words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.6 cascade operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.1 PM2329 access modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.1.1 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.1.2 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.1.3 channel register blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.1.4 direct and indirect access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.2 register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.2.1 programmable register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.2.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.2.2.1 local configuration register (lcr; n000h) . . . . . . . . . . . . . . . . 80 4.2.2.2 rule indirect command register (ricr; n008h) . . . . . . . . . . . . 82 4.2.2.3 rule indirect address register (riar; n010h) . . . . . . . . . . . . . . 84 4.2.2.4 rule indirect data register set (ridr0; n018h) (ridr2; n020h) (ridr4; n028h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.2.2.5 oc descriptors (ocd; n400h, n408h...n7f0h, n7f8h) . . . . . . . . 88 4.2.2.6 e-ram indirect data register set (eidr0; 8200h) (eidr2; 8208h) (eidr2; 8208h) (eidr4; 8210h) (eidr6; 8218h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.2.2.7 e-ram indirect command register (eicr; 8220h) . . . . . . . . . . 94 4.2.2.8 e-ram indirect address register (eiar; 8228h) . . . . . . . . . . . . 96 4.2.2.9 e-ram configuration register (ecr; 8230h) . . . . . . . . . . . . . . 97 4.2.2.10 interrupt enable register (ier; 8238h) . . . . . . . . . . . . . . . . . . . 99
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 8 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.11 status register (stsr; 8240h) . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.2.12 operation control register (opcr; 8248h) . . . . . . . . . . . . . . 102 4.2.2.13 channel assignment register (car; 8250h) . . . . . . . . . . . . . . 104 4.2.2.14 oc conductor register (occr; 8258h) . . . . . . . . . . . . . . . . . 105 4.2.2.15 packet information register (pir; 8260h) . . . . . . . . . . . . . . . . 107 4.2.2.16 timer register (tmr; 8268h) . . . . . . . . . . . . . . . . . . . . . . . . 111 4.2.2.17 alternate occ register (aocc; 8270h) . . . . . . . . . . . . . . . . . 113 4.2.2.18 packet buffer input register (pbir; base 3 +00h, +08h,... +0e8h, +0f0h) (pbir, eopd0; base 3 +0f8h) (pbir, eopd1; base 0 +08h) . . . . . . . . . . . . . . . . . . . . . . . . 115 4.2.2.19 channel status register (csr; base 0 +00h) . . . . . . . . . . . . . 118 4.2.2.20 oc results fifo output reg (ocrf; base 1 +00h) . . . . . . . . 120 4.2.2.21 data results fifo output register . . . . . . . . . . . . . . . . . . . . 125 4.3 indirectly addressable locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.3.1 rule memory cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.3.2 e-ram words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.4 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5 rule formats and oc sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.1 rule formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.1.0.1 rule data field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.1.0.2 rule control field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.1.1 rule operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.1.2 masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.1.3 composite rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.1.4 rule attribute bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.1.5 rule negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.2 operation cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.3 oc sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.3.1 oc conductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.3.2 occ sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 5.3.2.1 trace feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.3.2.2 sequencing control modes . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.3.2.2.1automated sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.3.2.2.2processor controlled sequencing . . . . . . . . . . . . . . . . . . 145 5.3.2.3 occ sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.3.2.4 e-ram sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.3.3 e-word association with cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 6 electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 6.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 9 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 6.2 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.2.1 reset timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.2.1.1 vdd power on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.2.2 clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6.2.3 system interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6.2.4 e-ram interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.2.5 cascade interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.2.6 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 7 package details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.1 package type, characteristics and mechanical drawing . . . . . . . . . . . . . . . . 163 7.1.1 package type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.1.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.1.3 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm PM2329 classipi network classification processor datasheet proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 10 document id: pmc-2010146, issue 4 list of figures figure 1 system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 2 PM2329 external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 3 PM2329 ball number assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 4 on-chip pll bypass mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 5 system interface register timing diagram (syncburst) . . . . . . . . . . . . . . . . . 43 figure 6 system interface register timing diagram (zbt) . . . . . . . . . . . . . . . . . . . . . . 45 figure 7 system interface dma timing (syncburst mode) . . . . . . . . . . . . . . . . . . . . . . 47 figure 8 system interface dma timing (zbt mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 9 e-ram interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 10 e-ram connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 11 cascaded bus connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 12 single PM2329 with 32-bit/64-bit e-ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 13 two cascaded PM2329 devices with 64 or 96 bits of eram . . . . . . . . . . . . . 56 figure 14 maximum cascade configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 15 PM2329 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 16 simplified data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 17 simplified data flow--oc processing and results posting . . . . . . . . . . . . . . . 61 figure 18 packet input, result output, and associated status handshake . . . . . . . . . . . 63 figure 19 packet formats supported by PM2329 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 20 headers formats within packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 21 organization of rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 22 local vs. global register space; conceptual view a . . . . . . . . . . . . . . . . . . . 71 figure 23 PM2329 packet input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 24 channel register blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 25 PM2329 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 26 access to rule memory cells via ridr0-4 registers . . . . . . . . . . . . . . . . . . . 82 figure 27 timer logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 28 rule control and data field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 29 rule control fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 30 trace feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 31 processor controlled sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 32 general overview of occ sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 33 general overview of eram sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 34 recommended vdd power on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 35 sclk to eclkout skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 36 system interface timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 37 load equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 38 e-ram interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 39 cascade interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 40 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 11 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 41 jtag idcode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 42 device compact model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 43 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm PM2329 classipi network classification processor datasheet proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 12 document id: pmc-2010146, issue 4 list of tables table 1 timing and common control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 2 system interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 3 eram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 4 cascade interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5 test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 6 vdd and vss signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7 signals listed by ball assignment; rows a through c . . . . . . . . . . . . . . . . 33 table 8 signals listed by ball assignment; rows d through k . . . . . . . . . . . . . . . . . 34 table 9 signals listed by ball assignment; rows l through w . . . . . . . . . . . . . . . . . 35 table 10 signals listed by ball assignment; rows y through ad . . . . . . . . . . . . . . . . 36 table 11 signals listed by ball assignment; rows ae and af . . . . . . . . . . . . . . . . . . 37 table 12 signals listed by name (alphabetically) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 13 pspba deassertion delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 14 system bus 64-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 15 system bus 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 16 cascade size vs. maximum physical e-ram width . . . . . . . . . . . . . . . . . . 54 table 17 PM2329 register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 18 channel register block base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 19 channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 20 e-word depth chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 21 ema[18:17] usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 22 direction specifier bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 23 oc conductor register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 24 processor controlled oc sequencing & trace oc execution . . . . . . . . . . 109 table 25 timestamp increment interval example (sclk 66.67 mhz) . . . . . . . . . . . 111 table 26 data results fifo output register (64-bit mode) . . . . . . . . . . . . . . . . . . . 125 table 27 data results fifo ouput register (32-bit mode) . . . . . . . . . . . . . . . . . . . 126 table 28 common control rule - ccr bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 29 operations supported for rule data sub-fields . . . . . . . . . . . . . . . . . . . . . 138 table 30 masked sub-field and associated mask source . . . . . . . . . . . . . . . . . . . . . 139 table 31 occ sequencing control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 32 occ sequencing status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 33 registers applicable to occ sequencing . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 34 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 35 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 36 terminal capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 37 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 38 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 39 clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 40 system interface timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 13 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 41 e-ram interface timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 42 cascade interface timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 43 jtag interface timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 44 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 14 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 1 PM2329 overview 1.1 introduction the PM2329 is a member of the classipi family of sophisticated network classification processors capable of supporting gigabit/oc-48 interfaces. it is optimized for network environments--network equipment can use the PM2329 ? s classification and analysis capability to implement wire-speed routing, qos, firewall and other functionality such as nat and network monitoring that requires packet inspection and classification. the PM2329 can be used to implement a mixed l2, l3, l4 and payload data (l5 to l7) based search. with a peak throughput of up to oc-48 ipv4 packets per second, the PM2329 is an ideal choice for all classification requirements. the PM2329 ? s patented architecture has been designed to work efficiently in a wide range of system configurations such as per-port, customized hardware, gigabit environment, or a centralized search engine shared by a number of ports. the PM2329 architecture minimizes the bandwidth and latency incurred due to multiple packet data transfers within the equipment. it can be programmed to perform multiple pattern searches sequentially, and/or conditionally without host processor intervention, providing the high throughput required for complex classification applications. 1.2 features ? packet header, packet data based or user-defined data based classification at gigabit wire-speed. single PM2329 can store up to 16k policy rules. up to eight PM2329 devices can be cascaded to appear as a large PM2329 with support for up to 128k rules. supports external synchronous ram to extend capabilities such as programmed operation cycle sequencing, per rule statistical information, and aging. on-chip policy database or rule memory that can be partitioned to implement multiple classification partitions. mechanism to allow support for up to 32 independent tasks running on the external processor. supports multiple classification lookups per input request. each lookup extracts its unique key from input data stream and applies its dedicated classification rule table to produce match results. classification lookups can be invoked sequentially and/or conditionally using sophisticated sequencing mechanisms. register, external ram, or processor controlled lookup sequencing mechanism powerful assist for routing, qos, nat, firewall and load balancing applications. high-speed synchronous packet data input and result output interface.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 15 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 1.3 functional overview the PM2329 is designed for use in switches, routers, access concentrators and other telecommunications equipment such as traffic shapers, firewalls and network address translators. these equipment implement one or more of software modules in the PM2329, such as the routing, qos, nat, firewall, load balancing and network monitoring modules. these modules implement functions such as address lookup, flow classification, and connections cache identification. the PM2329 accelerates these functions, extending the performance of such equipment in gigabit/oc-48 wirespeed environments. the PM2329 is a high performance search and classification processor. during initialization the external packet processor and application code will configure the description of various searches that would be performed by the PM2329. these descriptions consist of key extraction procedures, rule table identities, search methodologies and termination criteria. the external packet processor will then load the PM2329 ? s on-chip rule memory with a set of initial rules for every search. these rules can also be updated at a later time. once the PM2329 has been configured, the external packet processor can submit packet data together with classification requests. classification requests can trigger multiple searches to be performed on the same packet. multiple searches are typically useful when multiple applications are supported on the network equipment - such as routing, qos, nat etc. for example, a route lookup table can be stored in one table, while another table can store a qos flow classification policy. the searches can be specified to be conditional upon the results of the previous searches. the ability to partition the rule memory combined with the ability to sequence multiple searches enable the system designer to offload complex packet processing tasks to the PM2329. the PM2329 returns a series of results for every packet it analyzes. these can be used by software either directly or to index into a user data structure. the PM2329 provides the capability of attaching an external sram, which can store user programmable data corresponding to the indexes returned upon a match. in addition to searches, the PM2329 can gather statistics--counts and time stamps--against every rule match. the PM2329 gathers these statistics in the external sram. before performing a search operation on a packet, the PM2329 performs key extraction. the PM2329 has an on-chip field extraction engine that can extract layer 3 and layer 4 header fields from ipv4 packets as the packet data is presented to the chip. using these fields, it constructs a header key that be used during searches. further, it can also extract keys (short and long) at arbitrary offsets into the input data stream. each extracted key is made up of a number of fields. every rule in the rule tables specifies values and conditions for all fields in a key. the PM2329 search engine can perform tasks such as: single or multiple match identification prioritized match selection on multiple match layer-n searches: patterns and signature composed of strings, numbers, etc. longest prefix (lp) search for ip routing
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 16 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 1.4 architectural overview the PM2329 architecture supports the requirements of networking protocols pertaining to high-speed search and classification. it supports the implementation of several protocols in the same equipment to achieve wire-speed performance at gigabit/oc-48 rates. this architecture permits sequential, parallel and conditional operations. the PM2329 device can also be cascaded to allow searches consisting of a large number of rules. the PM2329 architecture is tuned to high-speed yet sophisticated classification operation. networking protocol processing requires performing searches and lookups in data structures based on information contained in the header of a packet. in ipv4 packets, this is typically the source and destination ip address (layer 3), the ip protocol field, and the source and destination port numbers (layer 4). a lookup operation would consist of extracting the header of a packet and conducting a search in a data structure using this and some specific search criterion. as the sophistication of network protocols has increased, data lookups using information contained in the data payload of the packet (layer 5 to layer 7) has also become necessary. the PM2329 supports high-speed lookups using this (layer 5 to layer 7) data. to perform these lookups at wirespeed packet rates, the accelerator engine must have algorithmic support, architectural support and software model support. the PM2329 provides this support in an optimized manner as outlined below. 1.4.1 algorithmic support the PM2329 provides algorithmic support for searches and examination of packet contents. based on the information provided by the PM2329, the associated packet content manipulation is performed by an external packet processor. key capabilities of the PM2329 for algorithmic support are as listed below: flexible key extraction search prioritization single or multiple match identification range searches counters/statistics (packet and byte count) and timestamps longest prefix search aging support
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 17 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 1.4.2 architectural support the PM2329 architecture supports the following to improve system performance: scalable policy search engine can be scaled up to accommodate a wide variation in the number of rules as well as number of search partitions (to store multiple search rules). supports search sequencing to minimize packet processor or cpu intervention. supports complex field extraction from input packet for further classification. lookup/search model that is easy to integrate into software implementations of protocols. supports statistics collection. 1.4.3 software model support from the software programmers perspective, the PM2329 presents a flexible lookup/search model. it implements a generalized lookup/search operation, which is atomic in nature. this operation has two main inputs: the key data using which the lookup is to be performed and the set of policy rules, which have to be applied to the key data to perform this lookup. the former is selected from the packet and can be the packet header l3/l4 information, other fields from the packet header or fields from the packet data payload. the latter is a set of rules, which are to be applied to this data to obtain a result. the result is in the form of an occurrence of match, in other words, the identification of a rule, which the input data satisfies. since it is possible for more than one rule to match the input data, the rules are prioritized. in case of multiple matches, multiple results can be returned and the higher priority matching rule is presented first. multiple such lookup/search functions can be stored within a single PM2329. each such function is said to occupy a partition within the chip. for example, a route lookup table can be stored in one partition, while another partition can store a qos flow classification policy. the PM2329 also has the ability to perform a sequence of different lookups or classifications on the same packet data. the search/lookup operations programmed into the PM2329 can be automatically applied to every packet presented to the PM2329 ? s high-speed wide synchronous data transfer bus. thus, the sequence of operations is performed on every packet and the result is made available, on a per packet basis, to the packet processor. to assist in high-speed packet classification, the PM2329 is designed to be ethernet and ipv4-aware. it incorporates a field extraction engine (fee) that understands ethernet ii, 802.3 & 802.1p/q and determines where the layer 3 payload starts from in the packet. it can extract key ip, tcp and udp header fields as well as payload data at any offset. the fee is tolerant of the various idiosyncrasies of the ip and tcp headers. it is also possible to bypass the fee on a per-packet basis. operating at a high clock rate, the 64-bit wide synchronous bus provides adequate bandwidth to support gigabit/oc-48 rate transfer of data, commands and results. the PM2329 ? s flexible data interface architecture allows complete hardware controlled data transfer for high-speed applications, as well as a processor driven software controlled data transfer for systems where performance is less critical. the PM2329 can be configured to receive streaming commands and data through its data interface. data can consist of arbitrary bytes, partial ip packets (ip header, tcp header and partial data), or complete ip packets. in all cases the data could be optionally preceded by command words that identify the nature of data following immediately as well as the kinds of classification to be performed on the data. this method
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 18 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet of operation ensures high-speed command and data input. architecturally the PM2329 consists of three major functional blocks: policy search engine pse field extraction engine fee operation control logic: operation cycles, descriptors and e-ram each of these blocks is introduced in the following sections. 1.4.4 policy search engine pse operating at up to 232 mhz, the PM2329 policy search engine performs multiple search operations on input data against a set of pre-loaded rules. lookup criteria or search policies called rules are stored in the policy database or rule memory. a rule is made up of an operation code and corresponding operand data. these operation codes and operand data specify match criteria for multiple fields that make up the key data. rules related to a single search/lookup operation are stored in a partition within the rule memory. a single search/lookup operation is termed an operation cycle (oc). it consists of applying the rules within a specified partition to the key data extracted from the packet by the fee. the result of an oc is in the form of identification of the rule that caused a match with the data presented by the fee to the policy search engine. more complex rules can be created with the help of the composite rule facility using which up to four consecutive instructions can be combined to form a composite instruction. 1.4.5 field extraction engine fee the fee performs ip, tcp and udp header analysis of every packet presented to the PM2329. it extracts relevant layer 3 addresses and layer 4 port numbers together with protocol type from these headers to form a header key. the fee can also extract arbitrary data at any offset in the input data stream, thereby enabling classification based on the packet data other than layer 3 and layer 4 header fields. the fee can also maintain some amount of tcp state information in the e-ram if so desired. the fee is ethernet (ii, 802.3 & 802.1p/q) aware and hence it can automatically identify offsets for the layer 3 header. likewise it can correctly locate layer 4 header offsets by correct interpretation of the ip options fields. for applications where it is more efficient to carry out the ip/tcp/udp header extraction externally, ip/ tcp/udp header processing can be disabled in the fee. 1.4.6 operation control logic the operation control logic orchestrates the primary search and classification operations of the PM2329 device.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 19 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 1.4.6.1 operation cycles, descriptors and e-ram the operation control logic controls the execution of the operation cycles. an oc is the atomic action of looking up a packet against a class of rules and returning a match index. in order to run an operation cycle, the rules that will participate in the oc must be specified. this information is provided by using an operation cycle descriptor (ocd). each descriptor stores adequate information to describe the start and end of a rule partition. rule partitions can be uniquely described in each cascaded PM2329 device. the ocds are arranged in the form of a table within each device, and are specified by an index into this table. in the minimal mode, a standalone PM2329 device can execute a sequence of up to 4 fixed operation cycles. to support enhanced functionality including conditional sequencing and user data storage, the PM2329 supports an external synchronous sram (e-ram) that contains control and data information. the control information is stored in control words (c-words). the operation control logic can execute operation cycles based on a flow control mechanism driven by these c-words stored in the external sram. each control word contains an index into the oc descriptor table and identifies a single oc descriptor. control words also supply control information that drives the policy search engine. control words can also specify branch conditions that can start the execution of another oc based on the result of the current oc. besides c-words, the e-ram also contains data words (d-words). these d-words contain statistical and state information such as packet count, byte count, tcp state and time-stamp. d-words are typically accessed and updated by the device after a match or when an oc execution is complete. 1.5 system diagram figure 1 illustrates one possible application of the PM2329 in a line interface card of a high performance switch. figure 1 system block diagram packet data port interface control processor switch matrix or backplane classipi 1 - 8 chips sram user data + sequence control (e-ram) physical packet data in result out
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 20 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 2 signal description 2.1 introduction the PM2329 has three external interfaces to connect external devices: system interface extended ram (e-ram) interface cascade interface the system interface is a general purpose synchronous 64-bit interface over which the PM2329 can connect to a processor and optionally a packet source or dma device. this interface is designed to work like a synchronous sram interface so that it can be connected to an external search machine interface or memory interface on common network processors. on 32-bit platforms, this interface can be configured to work in 32-bit mode. the extended ram (e-ram) interface is used in the extended (single device or a cascaded set of devices) mode of operation. this interface drives all the signals required for an external sram memory array. the cascade interface is used when multiple PM2329 devices are used in the cascade mode. the cascade mode of operation allows up to eight PM2329 devices to work together as one large logical PM2329. extended and cascade modes are described in sections 2.4.2 and 2.4.3, respectively.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 21 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 2 PM2329 external signals notes: 1. pinout shown for 64-bit mode operation; refer to detailed table for 32-bit pin assignment. vdd and vss pins for i/o and core are not shown. sd [63:0] sa [15:3] channels packet source processor system interface timing & control eram interface cascade interface PM2329 ecd [31:0] edd [31:0] srw* soe* sce1* sce0* pspd pseop pscc pspba emoe* ecwe* edwe* testctl3 emce* cemrq cocdout cocm* swhe* swle* schstb test signals reset* sclk eclkout aclkin pllabyps aclkout sclkout tristate jtdi jtms jtck jtdo zbtmode sdwidth64 jtrst sint* pllsbyps sce2 spare3 spare4 pllavdd pllavss pllsvdd pllsvss test mode cocs schnum[4:0] ema[18:0] testctl[2:0] testout[7:0] cid[2:0] pllactl[1:0] cocdin[7:0]
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 22 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 3 PM2329 ball number assignments a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 c2 6 c2 5 c2 4 c2 3 c2 2 c2 1 c2 0 c19 c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 e26e25e24e23 e4 e3 e2 e1 f26f25f24f23 f4 f3 f2 f1 g2 6 g2 5 g2 4 g2 3 g4 g3 g2 g1 h26h25h24h23 h4 h3 h2 h1 j26 j25 j24 j23 j4 j3 j2 j1 k26k25k24k23 k4 k3 k2 k1 l26 l25 l24 l23 l4 l3 l2 l1 m26m25m24m23 m4 m3 m2 m1 n26 n25 n24 n23 n4 n3 n2 n1 p26p25p24p23 p4 p3 p2 p1 r26 r25 r24 r23 r4 r3 r2 r1 t26t25t24t23 t4 t3 t2 t1 u26 u25 u24 u23 u4 u3 u2 u1 v26 v25 v24 v23 v4 v3 v2 v1 w26w25w24w23 w4 w3 w2 w1 y26 y25 y24 y23 y4 y3 y2 y1 aa26 aa25 aa24 aa23 aa4 aa3 aa2 aa1 ab 26 ab 25 ab 24 ab 23 ab 4 ab 3 ab 2 ab 1 ac26 ac25 ac24 ac23 ac22 ac21 ac20 ac19 ac18 ac17 ac16 ac15 ac14 ac13 ac12 ac11 ac10 ac9 ac8 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ae26 ae25 ae24 ae23 ae22 ae21 ae20 ae19 ae18 ae17 ae16 ae15 ae14 ae13 ae12 ae11 ae10 ae9 ae8 ae7 ae6 ae5 ae4 ae3 ae2 ae1 af 26 af 25 af 24 af 23 af 22 af 21 af 20 af 19 af 18 af 17 af 16 af 15 af 14 af 13 af 12 af 11 af 10 af 9 af 8 af 7 af 6 af 5 af 4 af 3 af 2 af 1 bottom view
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 23 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 2.2 signals listed by function table 1 timing and common control signals signal name ball # size i/o description reset* y3 1 i reset input (active low) this is the asynchronous reset input, it must be active for a minimum of 100 sclk cycles. when this signal is asserted, PM2329 is forced into its reset state. cid [2:0] ab3 y4 ab2 3 i PM2329 id number these signals are sensed at reset to determine the 3-bit PM2329 id number. sdwidth64 aa3 1 i sd width select 64 this signal is sampled at reset to determine the width of the system interface data bus. 0: 32-bit (data transfers on sd[63:32] only) 1: 64-bit zbtmode ab1 1 i zbt mode select this signal is sampled at reset to indicate the system bus interface type 0: syncburst pipelined synchronous scd sram mode 1: zbt pipelined synchronous sram mode eclkout n23 1 o e-ram clock output regenerated sclk is output on this pin. when the device is operating in the single device configuration, this signal should be used to drive the external ssram clock input. when the device is operating in cascade mode, it is recommended that an external pll be used to generate the clock input for the extended ssram array. the external pll must guarantee a minimum skew to meet the ssram timing requirement. aclkin p4 1 i internal clock input during normal device operation, this input should be tied low. when plla is byspassed, this pin drives the internal aclk signal.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 24 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet aclkout r2 1 o internal aclk output during normal device operation (testmode is low), this signal is driven low. during test mode operation (testmode is high), this pin outputs a divided by 4 version of the qualified aclk. the source of aclkout can either be: internal aclk signal generated by the on-chip plla (when pllabyps is low) - o r- external aclkin input signal (when pllabyps is high) if the aclk frequency is 232mhz, the corresponding aclkout will be 50 mhz. sclkout m2 1 o sclk output during normal device operation (testmode is low), this signal is driven low. during test mode operation (testmode is high), this pin outputs the qualified sclk. the source of sclkout can either be: internal sclk signal generated by the on-chip plls (when pllsbyps is low) - or - external sclk input signal (when pllsbyps is high) sclk n4 1 i system clock input this is the main timing clock input to the PM2329. it must be active at all times. the maximum clock input frequency is dictated by the cvdd voltage input level. nominal cvdd max sclk input 1.5v 100mhz 1.6v 116mhz pllsbyps n3 1 i plls bypass during normal device operation, this signal must be grounded and its state must not be changed during operation of the PM2329. in order to bypass the internal plls, this signal must be forced high and the sclk clock signal supplied on the sclk pin is used to drive the clock internally. table 1 timing and common control signals signal name ball # size i/o description
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 25 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet pllactl[1:0] p2 p3 2 i plla control these pins select an internal aclk clock of 4xsclk, 3xsclk, 2xsclk or 1xsclk. these control signals must be tied high or low as required and must not change during the operation of the PM2329. if nominal cvdd = 1.5v 00: 4x for sclk < 50 mhz 01: 3x for sclk < 66 mhz 10: 2x for sclk < 100 mhz 11: 1x for sclk < 100 mhz (for reduced power application) if nominal cvdd = 1.6v 00: 4x for sclk < 58 mhz 01: 3x for sclk < 77 mhz 10: 2x for sclk < 116 mhz 11: 1x for sclk < 116 mhz (for reduced power application) these control signals must be tied appropriately, even when the plla is bypassed. pllabyps n2 1 i plla bypass during normal device operation, this signal must be grounded and its state must not be changed during operation of the PM2329. in order to bypass the internal plla, this signal must be forced high and the aclk clock signal supplied on the aclkin pin from an external source. table 1 timing and common control signals signal name ball # size i/o description
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 26 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 2 system interface signals signal name ball # size i/o description sce0* v1 1 i system chip enable 0 (active low) this is the chip enable signal for the PM2329. it should be driven active low for every read or write cycle to the device. sce1* u2 1 i system chip enable 1 (active low) this is the chip enable signal for the PM2329. it should be driven active low for every read or write cycle to the device. sce2 g2 1 i system chip enable 2 (active high) this is the chip enable signal for the PM2329. it should be driven active high for every read or write cycle to the device. sa[15:3] refer to section 2.3 tables 2.3-2.4 13 i system address bus address bus to address the internal locations in the PM2329. sa[11:3] : these signals are used to address the internal 64-bit registers of the PM2329 sa[14:12] : these 3 address lines must match the cid# of the PM2329 for its internal registers to be addressed as local registers. sa[15] : if this address bit is asserted high during a write cycle, the register addressed by sa[11:3] is accessed irrespective of the value on sa[14:12]. a global write is performed in this manner. note: when the PM2329 is configured in 32-bit mode, sa[2] is driven on the swhe* signal. sd[63:0] refer to section 2.3 tables 2.2-2.3 64 i/o system data bus all data transfers between the PM2329 and the external system components take place on this bus. when PM2329 is configured for 64-bit data bus width, sd[63:0] should be tied to the external packet processor. when PM2329 is configured for 32-bit data bus width, signals sd[63:32] are used, sd[31:0] should be left open. sint* u1 1 o system interrupt (active low) interrupt signal from PM2329 to the processor. in cascaded applications, sint* from PM2329 zero (cid=0) is connected to the processor, sint* signals from all other PM2329 devices are left open and unconnected.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 27 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet soe* u3 1 i system output enable (active low) this signal is driven active low by the packet processor to enable PM2329 data onto the external bus when a read operation is performed. this signal must be held high during write cycle. srw* v2 1 i system write enable (active low) if syncburst mode is selected, this signal can be tied permanently low. if zbt mode is selected, this signal should be driven low during a write cycle and held high during a read cycle. swhe* {sa[2]} u4 1 i system write high enable (active low) or system address bit 2 in 64-bit mode, this signal is swhe* and should be asserted during write cycles to indicate write data transfers on the upper 32 bits of the system data bus (sd[63:32]). in 32-bit mode, this signal is connected to the system address line #2 of the packet processor, and functions as the sa[2] signal. swle* {swe*} w1 1 i system write low enable (active low) in 64-bit mode, this signal should be asserted during write cycles to indicate write data transfers on the lower 32 bits of the system data bus (sd[31:0]). in 32-bit mode, this signal should be asserted during write cycle. pspd e24 1 i packet source packet direction this signal can be used by the ps to indicate the direction of packet movement (upstream/downstream) to the PM2329. this signal should indicate the packet direction during each cycle of packet data transfer after pspba has been asserted. this signal is used in dma mode only and should be tied low otherwise. pseop e26 1 i packet source end of packet ps asserts this signal to indicate that the current packet transfer to the PM2329 is complete. the PM2329 can now process the completed packet. this signal is typically connected to the terminal count pin of the dma device. this signal is used in dma mode only and should be tied low otherwise. table 2 system interface signals signal name ball # size i/o description
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 28 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet pscc g25 1 i packet source current cycle the ps asserts this signal to indicate to the PM2329 that the current bus cycle is packet data download. this signal is typically connected to the dma acknowledge pin of a dma controller. when this signal is asserted, the other system control lines sa[15:3] and sce* are ignored. this signal is used in dma mode only and should be tied low otherwise. pspba h24 1 o packet source packet buffer available this signal when asserted indicates to the ps that at least one packet buffer is currently available to receive packet data. this signal is typically connected to the dma request pin of the dma device. schnum[4:0] e25 f24 g24 f25 f26 5 o system channel number in multi-channel mode, when the schstb signal is active, these signals indicate the channel number for which the result is available. schstb g23 1 o system channel strobe this signal is asserted for one sclk cycle when a result for a packet becomes available. if multiple results are generated for a packet, then this signal is asserted every time a result becomes available. table 2 system interface signals signal name ball # size i/o description
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 29 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 3 eram interface signals signal name ball # size i/o description emce* p24 1 o extended memory chip enable (active low) this signal when active selects the entire bank of extended memory. only the primary PM2329 device drives this signal. the emce* signal from the primary device should be tied to the the chip enable inputs of all the e-rams (c-word and all d-words) in the e-ram array. the emce* signal of all secondary PM2329 devices should be left unconnected. emoe* r25 1 o extended memory output enable (active low) read enable to the entire bank of extended memory. only the primary PM2329 device drives this signal. the emoe* signal from the primary device should be tied to the the output enable inputs of all the e-rams (c-word and all d-words) in the e-ram array. the emoe* signal of all secondary PM2329 devices should be left unconnected. spare4 spare3 t24 m26 2 o spare signals for future use these signals are reserved for future use, in the current device they can be left unconnected. current proposed assignment on future devices, subject to change, is shown below. the current default output state of the signals is shown in parentheses. spare4: ectl (1) spare3: ema[19] (0) ema[18:0] refer to section 2.3 tables 2.4-2.5 19 o extended memory address bus address bus for the extended memory. any of the cascaded PM2329 devices can drive this bus. address lines ema[16:0] are driven from the e-ram address field whereas ema[18:17] are driven from the depth control field. for ema[16:0] signals, the number of address bits that need to be connected to the external e-ram device is a function of the total number of e-words required. ema[18:17] can be left unconnected if depth is 1. for depth of 2, only ema[17] needs to be connected. for depth of 4, ema[18:17] should be connected. edd[31:0] refer to section 2.3 tables 2.5-2.6 32 i/o extended data memory data bus data bus for the data memory assigned to each of the PM2329 devices.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 30 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet edwe* u24 1 o extended data memory write enable (active low) this is the write enable for the data memory assigned to the PM2329. in the cascade mode, each PM2329 device drives the write enable of the corresponding d-word eram. ecd[31:0] refer to section 2.3 tables 2.5-2.6 32 i/o extended c-word data bus shared data bus for the c-words in the extended memory. this bus transfers the c-words to all the PM2329 devices in the cascade. only the primary PM2329 writes c-word data over this bus. ecwe* v24 1 o extended c-word write enable (active low) this signal is driven by the primary PM2329 to write c- words to the e-ram. in the cascade mode, this signal from all secondary devices is left unconnected. table 4 cascade interface signals signal name ball # size i/o description cocs h26 1 i or o cascade oc start output for primary and input for all others. asserted by primary PM2329 to indicate start of a new oc to all others. de-asserted when all the PM2329 devices in the cascade complete their ocs. cocdin[7:0] k24 j26 k25 k26 l24 l25 l26 m25 8 i cascade oc done inputs connected to the corresponding cocdout pins of the other PM2329 devices in the cascade. unused cocdin pins should be tied high. cocdout j24 1 o cascade oc done output connected to the appropriate cocdin[n] pin on the other PM2329 devices in the cascade. cocm* k23 1 i/o cascade oc match (active low) this signal is asserted low by a PM2329 if and only if its own oc has resulted in a match and all the higher order PM2329 devices participating in that oc have asserted their cocdout signals. this signal is wire- or connected to all PM2329 devices and must be pulled high by an external pull up. cemrq g26 1 i/o extended memory bus request this signal is asserted by the primary PM2329 to indicate to the other PM2329 devices in the cascade that it has a pending extended memory data transfer operation. it is used for extended memory bus arbitration. table 3 eram interface signals signal name ball # size i/o description
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 31 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 5 test signals signal name ball # size i/o description jtrst v3 1 i jtag reset (tie low during normal operation) jtms w2 1 i jtag mode (tie high during normal operation) jtdi y1 1 i jtag data in (tie high during normal operation) jtdo w3 1 o jtag data out (no connect during normal operation) jtck y2 1 i jtag clock input (tie low during normal operation) tristate aa1 1 i tristate mode select during normal operation, this signal should be tied permanently low. if this signal is asserted high all outputs of the PM2329 are tristated. testctl[3:0] h25 t2 t3 j25 3 i test control signals these test signals are for test and debug purpose only. during normal device operation, these testctl[3] should be tied permanently low and testctl[2:0] should be tied permanently high. for debug purpose, a provision should be made on the board to drive these signals low or high. testout[7:0] ad5 ac7 ac20 ad22 c22 d20 d7 c5 8 o test output signals these test signals are for test and debug purpose only. during normal device operation, these signals can be left unconnected. for debug purpose, these signals should be routed to test points for observation. testmode aa2 1 i test signal this test signal is for internal use only. during normal device operation this signal should be tied low.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 32 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 6 vdd and vss signals signal name ball # size description avss1 avss2 m1 r1 2 pll analog ground each avss signal should be tied to its corresponding avdd signal using two low-inductance bypass capacitors (1-10 uf and 0.01-0.001uf). these signals should not be tied to the general ground plane. in order to ensure that the digital and analog sections of the on- chip plls have a common reference, they are tied to a ground reference internally on-chip. avdd1 avdd2 n1 p1 2 pll analog power 1.5v all signals must be connected to an appropriate power supply for correct device operation. cvss refer to section 2.3 tables 2.3-2.7 16 core ground all signals must be connected to an appropriate ground plane for correct device operation. cvdd refer to section 2.3 tables 2.3-2.7 16 core power 1.5v all signals must be connected to an appropriate power supply for correct device operation. vss refer to section 2.3 tables 2.3-2.7 64 i/o ground all signals must be connected to an appropriate ground plane for correct device operation. vdd refer to section 2.3 tables 2.3-2.7 16 i/o power 3.3v all signals must be connected to an appropriate power supply for correct device operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 33 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 2.3 signals listed by ball table 7 signals listed by ball assignment; rows a through c ball signal name ball signal name ball signal name a1 vss b1 vss c1 vss a2 vss b2 vss c2 vss a3 vss b3 vss c3 vss a4 vss b4 vss c4 vss a5 sd10 b5 sd8 c5 testout0 a6 sd13 b6 sd12 c6 sd9 a7 sd16 b7 sd14 c7 sd11 a8 sd19 b8 sd17 c8 sd15 a9 sd23 b9 sd21 c9 sd18 a10 sd25 b10 sd24 c10 sd22 a11 sd28 b11 sd27 c11 sd26 a12 sd31 b12 sd30 c12 sd29 a13 sd32 b13 sd35 c13 sd34 a14 sd39 b14 sd36 c14 sd37 a15 sd40 b15 sd41 c15 sd42 a16 sd43 b16 sd44 c16 sd45 a17 sd46 b17 sd47 c17 sd49 a18 sd48 b18 sd50 c18 sd53 a19 sd52 b19 sd54 c19 sd56 a20 sd55 b20 sd57 c20 sd60 a21 sd58 b21 sd59 c21 sd62 a22 sd61 b22 sd63 c22 testout3 a23 vss b23 vss c23 vss a24 vss b24 vss c24 vss a25 vss b25 vss c25 vss a26 vss b26 vss c26 vss
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 34 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 8 signals listed by ball assignment; rows d through k ball signal name ball signal name ball signal name d1 vss e1 sd3 h1 sa11 d2 vss e2 sd5 h2 sa13 d3 vss e3 sd7 h3 sa15 d4 vss e4 cvdd h4 cvss d5 cvdd e23 cvdd h23 cvss d6 cvdd e24 pspd h24 pspba d7 testout1 e25 schnum4 h25 testctl3 d8 cvss e26 pseop h26 cocs d9 cvss f1 sd0 j1 sa7 d10 sd20 f2 sd1 j2 sa9 d11 vdd f3 sd4 j3 sa12 d12 vdd f4 cvdd j4 cvss d13 sd33 f23 cvdd j23 cvss d14 sd38 f24 schnum3 j24 cocdout d15 vdd f25 schnum1 j25 testctl0 d16 vdd f26 schnum0 j26 cocdin6 d17 sd51 g1 sa14 k1 sa5 d18 cvss g2 sce2 k2 sa6 d19 cvss g3 sd2 k3 sa8 d20 testout2 g4 sd6 k4 sa10 d21 cvdd g23 schstb k23 cocm* d22 cvdd g24 schnum2 k24 cocdin7 d23 vss g25 pscc k25 cocdin5 d24 vss g26 cemrq k26 cocdin4 d25 vss d26 vss
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 35 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 9 signals listed by ball assignment; rows l through w ball signal name ball signal name ball signal name l1 n.c. p1 avdd2 u1 sint* l2 sa3 p2 pllactl1 u2 sce1* l3 sa4 p3 pllactl0 u3 soe* l4 vdd p4 aclkin u4 swhe* l23 vdd p23 ema14 u23 ema4 l24 cocdin3 p24 emce* u24 edwe* l25 cocdin2 p25 ema15 u25 ema7 l26 cocdin1 p26 ema13 u26 ema8 m1 avss1 r1 avss2 v1 sce0* m2 sclkout r2 aclkout v2 srw* m3 n.c. r3 n.c. v3 jtrst m4 vdd r4 vdd v4 cvss m23 vdd r23 vdd v23 cvss m24 n.c. r24 ema11 v24 ecwe* m25 cocdin0 r25 emoe* v25 ema5 m26 spare3 r26 ema12 v26 ema6 n1 avdd1 t1 n.c. w1 swle* n2 pllabyps t2 testctl2 w2 jtms n3 pllsbyps t3 testctl1 w3 jtdo n4 sclk t4 vdd w4 cvss n23 eclkout t23 vdd w23 cvss n24 ema17 t24 spare4 w24 ema0 n25 ema16 t25 ema9 w25 ema2 n26 ema18 t26 ema10 w26 ema3
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 36 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 10 signals listed by ball assignment; rows y through ad ball signal name ball signal name ball signal name y1 jtdi ac1 vss ad1 vss y2 jtck ac2 vss ad2 vss y3 reset* ac3 vss ad3 vss y4 cid1 ac4 vss ad4 vss y23 edd25 ac5 cvdd ad5 testout7 y24 edd28 ac6 cvdd ad6 ecd1 y25 edd31 ac7 testout6 ad7 ecd3 y26 ema1 ac8 cvss ad8 ecd7 aa1 tristate ac9 cvss ad9 ecd10 aa2 testmode ac10 ecd12 ad10 ecd14 aa3 sdwidth64 ac11 vdd ad11 ecd18 aa4 cvdd ac12 vdd ad12 ecd21 aa23 cvdd ac13 ecd25 ad13 ecd26 aa24 edd27 ac14 ecd30 ad14 ecd29 aa25 edd29 ac15 vdd ad15 edd2 aa26 edd30 ac16 vdd ad16 edd5 ab1 zbtmode ac17 edd11 ad17 edd9 ab2 cid0 ac18 cvss ad18 edd13 ab3 cid2 ac19 cvss ad19 edd16 ab4 cvdd ac20 testout5 ad20 edd20 ab23 cvdd ac21 cvdd ad21 edd22 ab24 edd24 ac22 cvdd ad22 testout4 ab25 edd26 ac23 vss ad23 vss ab26 n.c. ac24 vss ad24 vss ac25 vss ad25 vss ac26 vss ad26 vss
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 37 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 11 signals listed by ball assignment; rows ae and af ball signal name ball signal name ae1 vss af1 vss ae2 vss af2 vss ae3 vss af3 vss ae4 vss af4 vss ae5 ecd0 af5 ecd2 ae6 ecd4 af6 ecd5 ae7 ecd6 af7 ecd8 ae8 ecd9 af8 ecd11 ae9 ecd13 af9 ecd15 ae10 ecd16 af10 ecd17 ae11 ecd19 af11 ecd20 ae12 ecd22 af12 ecd23 ae13 ecd27 af13 ecd24 ae14 ecd28 af14 ecd31 ae15 edd1 af15 edd0 ae16 edd4 af16 edd3 ae17 edd7 af17 edd6 ae18 edd10 af18 edd8 ae19 edd14 af19 edd12 ae20 edd17 af20 edd15 ae21 edd19 af21 edd18 ae22 edd23 af22 edd21 ae23 vss af23 vss ae24 vss af24 vss ae25 vss af25 vss ae26 vss af26 vss
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 38 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 12 signals listed by name (alphabetically) signal name ball signal name ball signal name ball aclkin p4 cvss d18 ecd27 ae13 aclkout r2 cvss d19 ecd28 ae14 avdd1 n1 cvss v23 ecd29 ad14 avdd2 p1 cvss ac18 ecd30 ac14 avss1 m1 cvss ac19 ecd31 af14 avss2 r1 cvss ac8 eclkout n23 cemrq g26 cvss ac9 ecwe* v24 cid0 ab2 cvss h23 edd0 af15 cid1 y4 cvss h4 edd1 ae15 cid2 ab3 cvss j23 edd2 ad15 cocdin0 m25 cvss j4 edd3 af16 cocdin1 l26 cvss w23 edd4 ae16 cocdin2 l25 cvss w4 edd5 ad16 cocdin3 l24 ecd0 ae5 edd6 af17 cocdin4 k26 ecd1 ad6 edd7 ae17 cocdin5 k25 ecd2 af5 edd8 af18 cocdin6 j26 ecd3 ad7 edd9 ad17 cocdin7 k24 ecd4 ae6 edd10 ae18 cocdout j24 ecd5 af6 edd11 ac17 cocm* k23 ecd6 ae7 edd12 af19 cocs h26 ecd7 ad8 edd13 ad18 cvdd d5 ecd8 af7 edd14 ae19 cvdd d6 ecd9 ae8 edd15 af20 cvdd d21 ecd10 ad9 edd16 ad19 cvdd d22 ecd11 af8 edd17 ae20 cvdd aa23 ecd12 ac10 edd18 af21 cvdd aa4 ecd13 ae9 edd19 ae21 cvdd ab23 ecd14 ad10 edd20 ad20 cvdd ab4 ecd15 af9 edd21 af22 cvdd ac21 ecd16 ae10 edd22 ad21 cvdd ac22 ecd17 af10 edd23 ae22 cvdd ac5 ecd18 ad11 edd24 ab24 cvdd ac6 ecd19 ae11 edd25 y23 cvdd e23 ecd20 af11 edd26 ab25 cvdd e4 ecd21 ad12 edd27 aa24 cvdd f23 ecd22 ae12 edd28 y24 cvdd f4 ecd23 af12 edd29 aa25 cvss v4 ecd24 af13 edd30 aa26 cvss d8 ecd25 ac13 edd31 y25 cvss d9 ecd26 ad13 edwe* u24 ema0 w24 sa4 l3 sd19 a8
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 39 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet ema1 y26 sa5 k1 sd20 d10 ema2 w25 sa6 k2 sd21 b9 ema3 w26 sa7 j1 sd22 c10 ema4 u23 sa8 k3 sd23 a9 ema5 v25 sa9 j2 sd24 b10 ema6 v26 sa10 k4 sd25 a10 ema7 u25 sa11 h1 sd26 c11 ema8 u26 sa12 j3 sd27 b11 ema9 t25 sa13 h2 sd28 a11 ema10 t26 sa14 g1 sd29 c12 ema11 r24 sa15 h3 sd30 b12 ema12 r26 sce0* v1 sd31 a12 ema13 p26 sce1* u2 sd32 a13 ema14 p23 sce2 g2 sd33 d13 ema15 p25 schnum0 f26 sd34 c13 ema16 n25 schnum1 f25 sd35 b13 ema17 n24 schnum2 g24 sd36 b14 ema18 n26 schnum3 f24 sd37 c14 emce* p24 schnum4 e25 sd38 d14 emoe* r25 schstb g23 sd39 a14 jtck y2 sclk n4 sd40 a15 jtdi y1 sclkout m2 sd41 b15 jtdo w3 sd0 f1 sd42 c15 jtms w2 sd1 f2 sd43 a16 jtrst v3 sd2 g3 sd44 b16 n.c. ab26 sd3 e1 sd45 c16 n.c. l1 sd4 f3 sd46 a17 n.c. m24 sd5 e2 sd47 b17 n.c. m3 sd6 g4 sd48 a18 n.c. r3 sd7 e3 sd49 c17 n.c. t1 sd8 b5 sd50 b18 pllabyps n2 sd9 c6 sd51 d17 pllactl0 p3 sd10 a5 sd52 a19 pllactl1 p2 sd11 c7 sd53 c18 pllsbyps n3 sd12 b6 sd54 b19 pscc g25 sd13 a6 sd55 a20 pseop e26 sd14 b7 sd56 c19 pspba h24 sd15 c8 sd57 b20 pspd e24 sd16 a7 sd58 a21 reset* y3 sd17 b8 sd59 b21 sa3 l2 sd18 c9 sd60 c20 sd61 a22 vdd m4 vss ae4 table 12 signals listed by name (alphabetically) signal name ball signal name ball signal name ball
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 40 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet sd62 c21 vdd r23 vss af1 sd63 b22 vdd r4 vss af2 sdwidth64 aa3 vdd t23 vss af23 sint* u1 vdd t4 vss af24 soe* u3 vss a1 vss af25 spare3 m26 vss a2 vss af26 spare4 t24 vss a23 vss af3 srw* v2 vss a24 vss af4 swhe* u4 vss a25 vss b1 swle* w1 vss a26 vss b2 testctl0 j25 vss a3 vss b23 testctl1 t3 vss a4 vss b24 testctl2 t2 vss ac1 vss b25 testctl3 h25 vss ac2 vss b26 testmode aa2 vss ac23 vss b3 testout0 c5 vss ac24 vss b4 testout1 d7 vss ac25 vss c1 testout2 d20 vss ac26 vss c2 testout3 c22 vss ac3 vss c23 testout4 ad22 vss ac4 vss c24 testout5 ac20 vss ad1 vss c25 testout6 ac7 vss ad2 vss c26 testout7 ad5 vss ad23 vss c3 tristate aa1 vss ad24 vss c4 vdd ac11 vss ad25 vss d1 vdd ac12 vss ad26 vss d2 vdd ac15 vss ad3 vss d23 vdd ac16 vss ad4 vss d24 vdd d11 vss ae1 vss d25 vdd d12 vss ae2 vss d26 vdd d15 vss ae23 vss d3 vdd d16 vss ae24 vss d4 vdd l23 vss ae25 zbtmode ab1 vdd l4 vss ae26 vdd m23 vss ae3 table 12 signals listed by name (alphabetically) signal name ball signal name ball signal name ball
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 41 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 2.4 interface description 2.4.1 system interface the system interface is a general-purpose, 64-bit synchronous bus interface, which can optionally be configured as a 32-bit interface by holding the sdwidth64 pin low during reset. the PM2329 ? s ability to perform wire-speed operations at gigabit rates is dependent on the speed of data transfer over this interface. in general, data transfer speed will be halved when the system interface is configured for 32-bit wide data. the system interface is used by: 1. the processor to access the registers and rules memory of the PM2329 and the extended ram locations. 2. the packet source (or dma source) to load packets (or packet data) to the PM2329. the PM2329 is designed to interface to the processor as well as the packet source (configured as a dma device) for packet transfer without any additional logic. in case a packet source (dma) is not present, the processor can perform packet transfer. 2.4.1.1 clock frequency the system clock input signal (sclk) controls the timing of the synchronous system bus signals; address, data and control signal timings are all referenced to the system clock. the cascade and e-ram interfaces also run at the sclk frequency and are synchronous to sclk. however, in order to provide improved timing on the e-ram interface, the PM2329 generates the eclkout signal for the external e-ram devices. in a lightly loaded system bus with up to two cascaded PM2329 devices and associated e-rams, the sclk frequency may be up to 100mhz. when running at 116mhz sclk frequency, only a single PM2329 device operation is recommended. factors such as bus loading must be considered in determining the sclk frequency. when operating the device at 100 mhz or 116mhz, it is recommended that all high- speed signals should be source- and destination-terminated, to minimize problems due to ground bounce or ringing. low inductance terminating resistors in the range of 17 to 33 ohms are recommended. in applications with 3 or more cascaded PM2329 devices and associated e-rams, the sclk frequency should be less than the rated maximum clock input. the actual frequency used in these systems should be appropriately selected in order to achieve a balance of interface speed and the maximum throughput from the pse logic. the policy search engine pse of the PM2329 can run at a frequency of up to 232 mhz regardless of the number of devices in the cascade. it is clocked by an internally generated pse clock, which is derived from the externally supplied sclk using an on-chip pll. the internal pse clock is derived by multiplying the sclk by a multiplier of 1x, 2x, 3x or 4x. the multiplier value is sampled at reset by the PM2329 on the pllctl[1:0] pins.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 42 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet the diagram below shows the bypass mechanism for on-chip plls. when plla is bypassed, pllactl[1:0] signals must still be tied appropriately to specify the desired sclk vs. aclk clock ratio. figure 4 on-chip pll bypass mechanism 2.4.1.2 processor bus cycles the PM2329 interface to the processor has been designed to appear like a synchronous pipelined sram. two types of bus timings are supported: syncburst and zbt. the block read or block write throughput is the same for syncburst and zbt timings. however, zbt timings allow greater throughput for random read and write operations. the basic signals involved in a processor access are: sd[63:0], sa[15:3], swe*, soe*, swhe*, swle*, sce0*, sce1* and sce2. in addition to the sce0* signal, two additional chip enable signals--sce1* and sce2--are provided, for a total of two active low and one active high chip enable signals. this allows the PM2329 to interface with external processor at high speed, without the need of any external glue logic for address decode. for systems that do not require multiple chip enable signals, the (one or two) unused scen signals can be permanently tied to their active state. 2.4.1.2.1 syncburst bus cycles processor accesses may be either write cycles or read cycles. the write cycle is conducted in a single clock period, whereas the read takes 3 clock periods. the PM2329 supports contiguous or back-to-back transfers for both read and write operations. sys pll disable pllsbyps sclk 0 1 internal sclk eclk aclk pll disable pllabyps aclkin 0 1 internal aclk pllactl[1:0] testmode sclkout /4 aclkout 0 1 sfbck 0 1 afbck/4 pllsbyps pllabyps testmode 0 0 0 normal 0 0 1 bypass sclk 0 1 0 bypass aclk 0 1 1 bypass both 1 x x test use function
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 43 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 5 system interface register timing diagram (syncburst) a write cycle occurs as follows: 1. sa[15:3], and sd[63:32] and sd[31:0] (as required) are driven by the processor. sce0* and sce1* are asserted low and sce2 is asserted high by the processor. one or both of swhe* and swle* are asserted low to indicate the 32-bit lanes on which the write should occur. 2. on the next rising edge of sclk, the write cycle occurs. 3. in case of back-to-back writes, the next write occurs on the next clock edge. register read and write timing, syncburst mode sclk sa[15:3] sd[63:0] sce0*/ sce1* soe* srw* swhe* swle* sce2 wa1 wa2 ra1 ra2 wa3 wa4 wd1 wd2 undefined rd1 rd2 wd3 wd4 don ? t care don ? t care write cycles write cycles read cycles pscc pspd pseop don ? t care don ? t care don ? t care don ? t care don ? t care for reads (address and control cycle), either... 1) sr/w* should be high and swhe* and swle* are don ? t care (shown), or 2) sr/w* should be low and swhe* and swle* should be high (not shown).
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 44 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet a read cycle occurs as follows: 1. sa[15:3] is driven by the processor. sce0* and sce1* are asserted low and sce2 is asserted high by the processor. PM2329 latches this state on the first rising edge of clock and starts the read cycle internally. (note: if srw* is driven low and swhe* and swle* are high, then the PM2329 treats this as a read cycle in syncburst mode to be compatible with syncburst sram specification. in zbt mode, this case is treated as no operation.) 2. on the second rising edge, the PM2329 internally fetches the data to be read. the processor must drive soe* before the second rising edge. this causes the PM2329 output buffers to be enabled and drive the read data onto the system bus. keeping soe* low through the third rising edge will allow the processor to latch the data on this edge. 3. in case of back-to-back reads, the next cycle address and control signals can be asserted after the first rising edge and PM2329 will latch this state on the second rising edge in a pipelined fashion. thus, read data can be transferred on every cycle. note: srw* should be tied low for syncburst mode. 2.4.1.2.2 zbt bus cycles in the zbt mode, both the read and write cycles are pipelined. the read cycle is the same as the normal (syncburst) mode. (except for the case stated above: if srw* is driven low and swhe* and swle* are high in zbt mode, the PM2329 treats the case as a ? no operation ? .). the write cycle is conducted in 3 clock periods, just like the read. the zbt mode thus supports contiguous or back-to-back transfers on both read and write or interleaved read/write/read cycles. the zbt operation results in greater available bus bandwidth when random reads/writes are performed. in a write cycle in zbt mode, the processor drives the sa[15:3] on the first rising edge. it also drives srw* low to indicate a write cycle and asserts sce0*, sce1* and sce2 signals on the first rising edge. one or both of swhe* and swle* are asserted low on the first rising edge to indicate the 32-bit lanes on which the write should occur. finally, the processor asserts write data sd[63:32] and sd[31:0] (as required) on the third rising edge. there is an important consideration when the PM2329 is used in zbt mode: if a register is written in cycle 1, its value will only be available for read during bus cycle 4. that is, read cycles performed in bus cycles 2 and 3 will return the old register value . similarly, if a write to register q is expected to cause a change in the value of register r, then the new value of register r will only be visible when read at least 2 clock cycles after register q has been written.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 45 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 6 system interface register timing diagram (zbt) 2.4.1.3 packet source interface signals the PM2329 system interface has four control signals designed to support a dedicated packet processor configured as a dma controller. these signals are pspba, pseop, pspd and pscc. this dma interface is a write-only interface, and active in single channel mode only. when the PM2329 has space in the packet buffer to accept packet data, pspba signal is asserted. the signal is deasserted when: 1. the last available 256-byte segment is being written and either the pseop signal is asserted or the eop command terminates the current packet transfer, or 2. the packet buffer limit is reached. the pspba signal is deasserted low corresponding to the 27th (64-bit) word written into the last 32- locations by 64-bits segment (that is, the last 256-byte segment) of the packet input buffer. due to the pipelined nature of the device, there will be a certain delay between the external write cycle for the 27th word and deassertion of pspba signal, as noted in table 13 below. sclk sa[15:3] sd[63:0] sce0*/ sce1* soe* srw* swhe* swle* sce2 wa1 wa2 ra1 ra2 wa3 wa4 undefined undefined wd1 wd2 rd1 rd2 wd3 wd4 don ? t care don ? t care write cycles read cycles write cycles undefined cycles register read and write timing, zbt mode pscc pspd don ? t care don ? t care pseop don ? t care don ? t care don ? t care don ? t care don ? t care
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 46 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet depending on the write cycle timing, up to 4 additional 64-bit writes can be performed without causing packet input buffer overflow. if the dma source performs a burst write into the PM2329 with data transfers on every clock cycle, it can perform a number of additional data transfers without causing a data overrun, as shown in figure 7 . the number of additional transfers varies depending on transfer width and mode. in 64-bit syncburst mode, it can perform two additional data transfers after the cycle in which it detects pspba deasserted low (since the internal pipeline is 2 deep). in 64-bit zbt mode, it can perform data transfers until the cycle in which it detects pspba deasserted low (since the internal and external pipeline is 4 deep). the corresponding numbers in 32-bit mode are six for syncburst mode and four for zbt mode. when pspba is asserted, the packet source acquires the bus and asserts pscc to indicate to the PM2329 that the present transfer is from the packet source. assertion of the swe* in conjunction with swle* and/ or swhe* lines causes the current cycle to be treated as a packet data write cycle and data present on sd[63:0] is written to the PM2329 on the next sclk rising edge. a number of such packet data write cycles could occur in a back-to-back cycle burst. alternatively, pscc can be de-asserted while pspba is asserted and the processor can execute read or write cycles interleaved with dma cycles. pscc is generally tied to the dma acknowledge signal. the PM2329 provides an additional signal, pspd, to allow the dma controller to communicate to the PM2329 the direction of each packet. packets can be associated with a direction bit and the PM2329 rules can be programmed to inspect this direction bit in header lookups. this signal (if used) must be asserted during each cycle of packet transfer. if pspd is not used, packet direction can be signalled via the packet attribute field. in order to complete the packet transfer, the ps must assert the pseop signal or issue an eop command for the last word of the packet to be transferred. this indicates to the PM2329 that the current packet transfer is complete and the PM2329 can begin processing the packet data. pseop would generally be connected to the terminal count signal in a dma based system. systems that do not use this dma mechanism to perform packet transfers should leave the pspba output signal unconnected and tie the pseop, pspd and pscc input signals inactive. in such systems, a processor write to the packet buffer input register can be used to load the packet data into the device. the packet buffer availaibility status is readable in a PM2329 status register, and end of packet can be indicated to the PM2329 by a write to the alternate address of the packet buffer input register. table 13 pspba deassertion delay pspba deassertion delay access mode 64-bit mode 32-bit mode zbt 4 clocks 4 clocks syncburst 2 clocks 6 clocks
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 47 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 7 system interface dma timing (syncburst mode) sclk sa[15:3] sd[63:0] sce0*/ sce1* soe* srw* swhe* swle* sce2 wd1 wdn wdn wd eop dma write cycles pspba pscc pspd pseop don ? t care don ? t care dma write cycles non-dma or idle non-dma or idle non-dma or idle dma timing, syncburst mode (supported in single-channel mode only) don ? t care don ? t care don ? t care don ? t care don ? t care don ? t care don ? t care don ? t care don ? t care
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 48 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 8 system interface dma timing (zbt mode) 2.4.1.4 64-bit mode if sdwidth64 is pulled high during reset, the system bus works in 64-bit mode. in this mode, the bus supports 64-bit read and 64/32 bit write operations. all bus data is assumed to be aligned on an 8 byte boundary; thus sa2 is assumed to be 0 and is not connected to the processor address bus. packet data transfers over the system interface follow the network byte order for packet transfer. all other data transfers are assumed to be big endian (that is, the most significant byte transfers at the lowest address). the processor must take care when performing 32-bit read accesses when it is configured for a 64-bit bus width. it can perform 64-bit read accesses without any side effects; however, if a 32-bit read access is performed to an address that is part of a 64-bit register and which contains self clearing bits or which, if read, can trigger other actions, then undesirable side effects can occur. similarly, if the processor code performs a misaligned read, indeterminate side effects can occur. table 14 system bus 64-bit system data bus (sd) bit range 63:56 55:46 47:40 39:32 31:24 23:16 15:8 7:0 byte address01234567 dma timing, zbt mode (supported in single-channel mode only) sclk sce0*/ sce1* soe* srw* swhe* swle* wd1 wdn wdn wd eop dma write cycles pspba pscc pspd don ? t care don ? t care dma write cycles non-dma or idle non-dma or idle non-dma or idle pseop sa[15:3] sd[63:0] sce2 don ? t care don ? t care don ? t care don ? t care don ? t care don ? t care don ? t care don ? t care don ? t care
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 49 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 2.4.1.5 32-bit mode when the sdwidth64 pin is tied low during reset, the system interface is configured to work in 32-bit mode. in this case, all data transfer takes place over sd[63:32] only, and sa[2] must be connected to address bit 2 of the external processor (the PM2329 interprets it as sa[2]). 2.4.1.6 byte ordering PM2329 byte organization convention assumes that lower addresses contain the more significant bytes. for example, 32-bit mode, the msb lies at address 0 and is passed on sd [63:56], while the lsb lies at address 3 and is passed over sd [39:32]. 2.4.1.7 cascade mode addressing all the sa[15:3] address lines, and the sce0*, sce1*, and sce2 signals, are connected in parallel to the corresponding pins of all PM2329 devices in the cascade. when the processor accesses the PM2329 register space with sa[15] = 0, each device in the cascade will compare address lines sa[14:12] against the assigned cascade id (cid#) of the device. access to a particular device in the cascade will be enabled if sa[14:12] matches the cid# of that device. when the processor accesses the PM2329 register space with sa[15] equal to 1, sa[14:12] lines are ignored and cascade bus mechanism determines the device that responds to the access. 2.4.1.8 local and global register access the PM2329 register space supports two access mechanisms: local and global. some registers are accessed in local access mode while others are accessible via glocal access mode. this access mechanism permits all system interface signals of the devices in the cascade (except sint*) to be wired in parallel to the system bus, including the sce0*, sce1* and sce2 system chip enable signals. while all devices in the cascade are selected by the processor at the same time (since all system chip enables are simultaneously asserted active to all devices), arbitration logic inside the PM2329 devices ensure that only one of them will respond during processor read cycles. only the primary device ? s sint* is tied to the processor; all other sint* signals are left unconnected. for local access, the following conditions must be met: sa[15] should be driven to 0, sa[14:12] must match the assigned cid# of the device, and the lower sa signals must specify the address of the desired register. reads or writes to the individual registers accessible via local access mechanism can be performed this way in both non-cascaded or cascaded configurations. table 15 system bus 32-bit system data bus (sd) bit range 63:56 55:46 47:40 39:32 31:24 23:16 15:8 7:0 byte address0123nananana
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 50 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet for global access, the following conditions must be met: sa[15] should be driven to 1, sa[14:12] are ignored by the device, and the lower sa signals must specify the address of the desired register. writes to registers accessible via global access mode occur in the specified registers of all devices in the cascade simultaneously. reads from registers accessible via global access mode are either from the primary device (cid 0) or arbitrated via the cascade bus. note that the non-cascaded configuration is a simpified case of the cascade configuration. further details of local and global register access mechanism are provided in chapter 4, registers and programming. 2.4.1.9 multiple context support when the PM2329 is operating in multi-channel mode, it can can support multiple contexts running on the external packet processor (see operation control register, chapter 4). in this mode, the PM2329 supports up to 32 internal channels for processing packets from up to 32 different contexts. each context of the packet processor can access the assigned PM2329 channel, sending packets to it and obtaining the associated results, without conflict with other contexts. channels are numbered 0 to 31. the schnum[4:0] and schstb signals are provided on the PM2329 system interface. whenever a particular PM2329 channel has a result available, the channel number is output on the schnum[4:0] pins, and schstb is driven active for one sclk cycle. this provides a direct hardware mechanism to signal the particular context of the packet processor to access the PM2329 result fifo for its results. in cascade mode, the schnum[4:0] and schstb signals of the primary device are used. schnum[4:0] and schstb signals from secondary devices in the cascade should be left unconnected and ignored. for packet processors that do not support this type of interface, the PM2329 channels can be polled by individual contexts, or the PM2329 sint* pin can be set up to provide a common interrupt whenever a packet ? s processing is complete. in single-channel mode, schnum[4:0] signals may be left unconnected. schstb is asserted whenever the packet processing is complete. 2.4.1.10 reset and interrupts reset* is the asynchronous reset input to the PM2329. reset* must be asserted for a minimum of 100 sclk cycles after sclk has become active. when asserted, it forces the device into the power-on/reset state. the device enters the normal operating mode after this signal is deasserted. sint* is the interrupt from the PM2329 to the rest of the system. masking, and programming the conditions for assertion, are accomplished via the interrupt enable register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 51 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 2.4.2 extended ram (e-ram) interface the capabilities of the PM2329 can be enhanced significantly by the addition of the extended ram (e- ram). the PM2329 e-ram interface is designed to connect directly to a bank of synchronous pipelined srams. the e-ram stores control words (c-words) and data words (d-words) corresponding to each on-chip rule. with the e-ram connected, the PM2329 (or a cascade of PM2329 devices) works in the extended mode of operation. this mode allows powerful oc sequencing capabilities in addition to storage of statistics and aging information on a per-oc or per-connection basis. the e-ram data can be automatically updated by the PM2329 based upon the results of oc processing. the e-ram can also provide a fast user-defined lookup based on the results of an oc match. the e-ram interface memory address bus ema[16:0] is connected to the c-word and d-word e-ram memory devices ? address bus. the e-ram interface control word data bus (ecd[31:0]) is connected to the c-word memory device ? s data bus. in the cascade configuration, the ema bus from all PM2329 devices are connected in parallel to all the memory buses of the c-word and d-word memory devices. the ecd bus from all PM2329 devices are tied in parallel together and to the c-word memory data bus. the e-ram interface data word data bus (edd[31:0]) is connected to the d-word memory device ? s data bus. in the cascade configuration, the edd bus from each PM2329 device is connected to the data bus of the corresponding d-word memory device. the e-ram interface chip enable (emce*) and output enable (emoe*) signals are always driven by the primary device. regardless of the configuration (single or cascade), the emce* and emoe* signals of the primary PM2329 device are tied to the corresponding chip enable signals and output enable signals of the c-word and d-word e-ram devices. in the cascade configuration, the emce* and emoe* signals of the secondary PM2329 devices are left unconnected. the e-ram interface write enable for the c-word memory device (ecwe*) is connected from the primary PM2329 device only to the write enable of the c-word memory device. in the cascade configuration, the ecwe* signals of all secondary PM2329 devices are left unconnected. the e-ram interface write enable for the d-word memory device (edwe*) is connected to the write enable of the d-word memory device. in the cascade configuration, the edwe* signals of each PM2329 device is connected to the write enable signal of the corresponding d-word memory device. in the non-cascade configuration, the bus request (cemrq) signal can be left unconnected. in the cascade configuration, the cemrq signals of every PM2329 device in the array are tied together. the e-ram width, depth and organization are all highly flexible through programmable registers. the interface can handle a maximum e-ram size of 128k words by 256 bits/word. the access times of the e- ram devices depends on the sclk frequency as well as the number of PM2329 devices in cascade, since they load the memory data bus. moreover, the loading of the c-word sram is not the same as that of the d-word sram, as explained in section 2.5 . the table below gives typical access times expected, but these may change depending on board design and operating conditions.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 52 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 9 e-ram interface timing figure 10 e-ram connectivity ecwe*/ edwe* eclkout ema[16:0] emce* emoe* wa1 ra1 wa2 wa3 wd1 wd2 wd3 rd1 write read write nop sclk e-ram read/write timing syncburst mode only don ? t care adv* adsp* gw* mode adsc* zz bwe* bwd* bwc* bwb* bwa* ce* ce2 ce2* oe* ecwe*/ edwe* emce* emoe* vcc adv* adsp* gw* mode adsc* zz bwe* bwd* bwc* bwb* bwa* ce* ce2 ce2* oe* ecwe*/ edwe* emce* emoe*/ gnd (opt) vcc pipelined scd or dcd syncburst sram connectivity pipelined dcd syncburst sram connectivity (alternate)
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 53 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 2.4.3 cascade interface the cascade interface allows up to 8 PM2329 devices to be connected in a cascade configuration. the interface is designed so that the entire cascade appears to the processor as a single PM2329 having 128k rules. in the cascade configuration, the primary PM2329 should have its cid# set to 0. the remaining PM2329 devices should have their cid numbers set from 1 to n (n < 8) by strapping the cid[2:0] signals of each device appropriately. the primary PM2329 has the highest priority, with priority of each PM2329 decreasing with an increase in its cid number. cid numbers must be assigned serially starting from 0 with no gaps. for a non-cascaded configuration with a single PM2329 device, the cid[2:0] pins of the device should be tied low during reset; this assigns cid# 0 to this device. the primary PM2329 device asserts the cocs signal to start packet processing in itself and all the secondary PM2329 devices. (packet processing and sequencing is described in the next chapter.) after processing, each PM2329 drives its cocdout output pin, which, when active, indicates the completion of the current operation by a particular PM2329. since the cocdout pin of each PM2329 is connected to the appropriate cocdin[n] pins of all the remaining PM2329 devices, each one is informed of the completion status of all the others. the highest priority PM2329 chip with a match, asserts the cocm* signal. based on a proprietary arbitration mechanism, it gains mastership of the e-ram bus and accesses a word based on the result of the current operation. 2.5 system configurations 2.5.1 stand alone configuration stand alone is a minimal configuration, where a single PM2329 can store up to 16k rules and perform packet classification and other functions based on that set of rules. stand alone configuration affords the smallest system component count; there is no extended ram and no cascaded PM2329 devices in this configuration. 2.5.2 cascaded configuration a cascaded configuration is the most powerful configuration for packet processing using a set of PM2329 devices. cascading allows up to 8 PM2329 devices to be cascaded, thus increasing the rule space to a maximum of 128k rules. PM2329 interfaces are designed to allow cascading without any glue logic. a cascaded set of devices is designed to appear as a single device to the external processor and other system components. cid#s are configured to uniquely identify each PM2329 device. the cid#s also define the address space (as seen by an external processor) for each PM2329 devices ? local registers, and determine the participation of the PM2329 in the packet processing operations. the cid# also determines the priority of the PM2329 devices; PM2329 #0 has the highest priority, and PM2329 #7 has the lowest priority. figure 11 shows the cascade bus connectivity between cascaded PM2329 devices.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 54 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 11 cascaded bus connectivity 2.5.3 operation with extended ram in this configuration, an extended ram is connected to one or more PM2329 devices. each e-ram is controlled by one of the PM2329 devices, and all processor accesses to the e-ram are through one of the PM2329 devices. as compared to non-extended configurations, the addition of the e-ram enhances the basic oc processing capabilities by providing oc sequencing, connection data storage, and update capabilities to the PM2329. the PM2329 can be connected to an e-ram array up to 128k words deep. the maximum width of the e- ram depends on the number of PM2329 devices connected in cascade. table 16 cascade size vs. maximum physical e-ram width number of PM2329 devices in cascade maximum width of eram supported (c-word+d-word) 1 64 (32+32) 2 96 (32+64) 3 128 (32+96) 4 160 (32+128) 5 192 (32+160) 6 224 (32+192) 7 256 (32+224) 8 256 (32+224) classipi #6 classipi #0 classipi #1 classipi #7 c o c d o u t c o c d o u t c o c d o u t c o c d o u t c o c d i n [ 0 : 7 ] c o c d i n [ 0 : 7 ] c o c d i n [ 0 : 7 ] no connect no connect no connect c o c d o u t to processor c o c s c o c m * s i n t * c e m r q c o c s c o c m * s i n t * c e m r q c o c s c o c m * s i n t * c e m r q c o c s c o c m * s i n t * c e m r q 10k
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 55 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 12 single PM2329 with 32-bit/64-bit e-ram ema PM2329 #0 eram 0 ecd system bus PM2329 #0 eram 1 eram 0 edd ecd ema system bus single PM2329 with 32-bit eram single PM2329 with 64-bit eram edd
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 56 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 13 two cascaded PM2329 devices with 64 or 96 bits of eram figure 14 maximum cascade configuration cascade bus PM2329 #0 eram 1 eram 0 ema PM2329 #1 ecd edd ecd two PM2329 devices in cascade with 64-bit or 96-bit eram system bus eram 2 edd classipi #0 classipi #1 classipi #2 classipi #3 classipi #4 classipi #5 classipi #6 classipi #7 eram #0 c-word eram #1 d-w0 eram #2 d-w1 eram #3 d-w2 eram #4 d-w3 system interface bus cascade interface bus ema ecd edd eram #5 d-w4 eram #6 d-w5 eram #7 d-w6 edd edd edd edd edd edd ecd n.c. 8 cascaded PM2329 devices with a 256-bit wide e-ram
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 57 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 3 functional description 3.1 internal organization and data flow this section provides an overview of the major functional blocks of the PM2329 and illustrates the flow of data through the device. later sections explain the various blocks in greater detail. figure 15 PM2329 block diagram packet data policy search engine (for rule processing) results fifo fee cascade i/f PM2329 control eram i/f system interface fee registers control registers eram access local oc results results final oc results key rules packet input buffer
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 58 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 3.1.1 basic blocks as illustrated in figure 15 , the PM2329 consists of 7 major internal blocks: 1. system interface this block allows access to the PM2329 registers, and implements specific registers for programming the rule memory, transferring packet data to the PM2329, and reading results. additionally, indirect memory access registers in this block provide access to the e-ram memory. 2. field extraction engine (fee) this block includes the 8 kb packet input buffer which can store multiple packets in the single channel mode or one for each channel, in the multi channel mode. this block performs data extraction on the packet and transfers this data to the policy search engine for classification. the extracted data can be either from the header or pattern data from the user data field. 3. control logic this block controls the overall operation of the device. 4. policy search engine (pse) this is the core of the PM2329 classification engine and holds the policy database (also known as the rule memory). this block executes operation cycles (ocs) and returns results. 5. results fifo this block contains the results fifo logic. the results of packet processing are stored in the results fifo. in multi-channel mode, results are organized on a per channel basis in the fifo. 6. e-ram interface this block interfaces with the external ram (e-ram), both control ram and data ram. the e- ram is useful for conditional sequencing of ocs and for maintaining statistics and user data. 7. cascade logic this block provides the interface between multiple PM2329 devices in a cascade configuration. it resolves priorities between devices and enables processing across the cascade.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 59 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 3.1.2 data flow this section presents a brief overview of the data flow of a packet as it is processed. details of packet processing are discussed in later sections of this chapter. figure 15 illustrates the data flow for the PM2329 during normal operation. the data flow in the device can be split into three phases: packet transfer phase oc processing phase result phase packet transfer phase during the packet transfer phase, the packet data and associated control information is transferred to the device, over the PM2329 ? s system interface. it can be loaded into the PM2329 by a packet source (ps), or directly by the external processor. the packets are stored in the PM2329 packet input buffer--an input fifo which is the first element in the data path inboard from the system interface. figure 16 simplified data flow the packet input buffer ? s physical size is 256 bytes deep times the total number of channels supported by the PM2329 (256 x 32 bytes). a packet source can load the packet input buffer using either a single write port (the packet buffer input register, or pbir), or alternatively with sram-like addressing, wherein a block memory transfer mechanism is utilized in which the destination address increments. in single-channel mode, the packet input buffer acts like a fifo for multiple packets. in multi-channel mode, several packets may be transferred collectively into the packet input buffer. if a cascade PM2329 field extraction engine system interface ctl info policy search engine control unit packet input buffer e-ram interface
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 60 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet configuration is used, a transfer of packet data or packet control information to the packet input buffer loads all PM2329 devices in the cascade simultaneously. for further details regarding the packet input buffer size and functionality, refer to the channel assignment register and packet buffer input register descriptions in chapter 4. the packet transfer phase of processing is not complete until key data is extracted from the newly- acquired packet(s), including ip/tcp/udp fields (header fields), and data within the packet at given offsets which must undergo pattern searches. to extract such data for processing, the field extraction engine (fee) accesses the packets in the order in which packet transfers are completed. the fee transfers the extracted data fields to the policy search engine (pse) for classification with respect to a predetermined subset of the defined rules. in addition to the needs of the fee, the PM2329 control unit needs the control information associated with every packet, in order to start the packet processing operation. this control information defines the search space in the rule memory, the sequence of packet processing operations, the data upon which to act, and the action to be taken after each step in the packet processing. the control information may come from the packet source (ps) or from an external packet processor (pp), through the system interface. the control information can also come from the e-ram, if the oc execution is controlled by e-ram sequencing. oc processing phase once the packet data has been received, the relevant fields have been delivered to the policy search engine, and the control and sequencing information is in the hands of the control unit, the PM2329 starts the oc processing phase. the policy search engine applies select rules from a master rules memory in the order specified by the control unit, to packet header/data it received from the fee. application of a rule is essentially a pattern matching operation. (section 3.2 describes the field extraction engine in detail.) result phase during the result phase, the results of successful pattern searches are transferred from the pse into the oc results fifo. if an applied rule yields a match, the PM2329 uses the cascade interface signals and bus to assert an oc match signal and return the results of that comparison, with statistical data relating to that rule, in the results fifo. the system interface allows the external processor access to the results.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 61 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 17 simplified data flow--oc processing and results posting additionally, if the device is extended with external ram, the control unit can retrieve from this e-ram and deliver to the results fifo the d-words associated with the rule that produced a match. the control unit can also update the data portion of the e-ram word (e-word), based on update instructions in the control information for that packet. the cascade bus is in operation during the oc processing and results phases, in order to co-ordinate result processing activity between the cascade of devices. the system interface allows access to the results fifo by the external processor. 3.1.3 context support the PM2329 has been designed to work with high speed network processing applications where multiple processors or multiple tasks running on the same processor can send packets for processing and then retrieve only their own results. the PM2329 supports this through the use of channels. the concept of a channel is a path through the PM2329 from packet entry to result buffering. thirty two independent channels are supported, allowing for up to 32 independent contexts to utilize the PM2329. interleaved writing of packets by the contexts, as well as interleaved access to the context-based results, are possible; this can be accomplished without the use of any semaphore mechanism between the contexts. PM2329 field extraction engine system interface ctl info policy search engine control unit packet input buffer e-ram interface results fifo cascade interface ctl info
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 62 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet the multi-channel operation of the PM2329 is enabled by setting a bit in the operation control register to enable the multi-channel mode. note that packet data transfer when multi-channel mode is enabled must be done using processor cycles. packet source (dma) transfers are not supported in this case. in the multi-channel mode, the 8 kb input buffer is organized as 32 segments of 256 bytes each. packet input buffer registers for each segment are provided so that the external processor(s) may write to any segment (based on the context that is writing the packet). similarly, the 128 entry results fifo gets organized into 32 segments of 4 entries each. the combination of the input buffer and the associated results segment defines a channel. these channels are numbered 0 through 31. consequently, 32 simultaneous channels can co-exist and be used by 32 independent tasks/contexts. the registers used to load the packet, retrieve results, and check the packet processing status are organized in a per-channel fashion into channel- oriented register groups. this allows multiple contexts on the external processor to access their channel registers simply by using the appropriate base address for that channel group. the PM2329 processes the packets in the order in which packet transfers complete. results from packet processing are then sent to the appropriate segment in the results fifo. the results for a channel are made available through an oc results fifo read port for each channel. the schnum[4:0] and schstb pins on the PM2329 provide the required support to accomplish a hardware-based handshake between the PM2329 and the processor. for processors equipped to handle such handshake signals, this interface awakens a context whenever its packet processing results are ready. if the processor does not implement this interface, a channel status register can be read by any context to determine the status of the packet input buffers and result fifos for that channel. concatenation of segments is supported to allow any channel to transfer a packet larger than 256 bytes or to accumulate more than 4 results. this is accomplished using the channel assignment register. this allows any number of adjacent channels to be concatenated to work as a single larger channel. when 4 channels are concatenated, for example, the packet input buffer will appear to be 1 kb in length and the oc results will appear to be a 16 deep fifo. 3.1.4 channel input, output and status mechanism each channel (0 through 31) has its pre-assigned packet input buffer available for loading after reset and after the previously loaded packet has been processed. since the write ports associated with the packet input buffers share the processor bus, only one of them can be written to at a time; however, they can be loaded in an interleaved fashion. once a packet has been loaded by a context, the context must wait until the processing for this packet is complete as indicated by oc sequence terminated bit, before loading the next packet for its assigned channel. the diagram below shows the operation of status bits used for packet input and result output.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 63 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 18 packet input, result output, and associated status handshake 3.2 field extraction engine (fee) 3.2.1 introduction the field extraction engine (fee) represents the first stage of processing for all packet classification operations in the PM2329. packet input buffer the fee includes an 8 kb packet input buffer which can store up to 32 packets simultaneously. whenever the external device (processor or other packet source) sends packet data to the PM2329, the packet is first deposited in the packet input buffer. packets may transfer to the PM2329 while earlier packets are still being processed. packet bytes may begin to transfer to the PM2329 before other packets have completed transfer. multiple packets may be stored concurrently in the packet input buffer. csr read result fifo read oc processing packet fifo write pkt buffer available result available oc seq terminated interrupt or poll oc seq term or chnl strobe poll pba set write packet eop oc processing oc start oc done read result last result read (status handshake associated with result output involves pba, ra and ocst signals)
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 64 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet key extraction packet transfer for any packet completes when the PM2329 receives an eop indication for that packet. packets are then taken for further processing in the order in which the packet transfers complete. since the fee ? s task is to glean one or more "keys" from the packet which will be compared against a series of rules, it extracts the relevant header or data key from the packet, constructs the key(s), and transfers the key(s) to the pse for processing. a key can be one of three main types: pi field attribute key: the attribute segment of the packet ? s pi field (or the attribute segment of the pre-programmed pi register) becomes the key to be compared, according to the sequence of rules identified for the oc . header key: the ip, tcp and udp information from within the packet ? s header are concatenated to construct a 108-bit packet header key, which is compared (with appropriate masking if desired) in the rules processing of the oc. the fee parses and extracts header fields from ethernet at layer 2, ip at layer 3, and tcp/udp at layer 4. within ethernet, it can decode ethernet ii, ethernet 802.3 and ethernet 802.1p/q. packet data key: the fee also has the capability of extracting a given length of packet data starting at a given byte offset, and constructing short or long keys. this feature can be used for searching for a set of specific strings within a packet, whereby the fee repeatedly extracts data using an offset shifted by one additional byte for each iteration, in the forward or reverse direction, thereby allowing pattern searches in either direction. a packet data field can include payload bytes, header bytes, or both. the fee can extract multiple fields for any packet, and submit them all to the pse for processing. there can be one unique pi field attribute key, one unique 108-bit header key, and many unique packet data keys of varying lengths and beginning at varying offsets within the header/payload parts of the packet. 3.2.2 supported packet formats the fee performs extraction of fields and key construction as data is being received into its buffers. the fee uses the information in the pi field (or the pi register if no pi field exists in the packet) to direct its extract efforts. figure 19 and figure 20 show the packet formats recognized by the PM2329.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 65 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 19 packet formats supported by PM2329 l3 header extraction enable = 0 0781516 l3 header extraction enable = 1 ethernet framing enable = 0 0 l3 header offset ip header 24 l3ofs l3ofs+23 l4 header offset (ihl*4+l3 header offset) tcp/udp* 16 l4ofs l4ofs+15 * if l4 extraction enable = 1 & protocol = tcp/udp dmac 6 smac 6 type 2 0x0800 fcs 4 0 56 11121314 data 46-1500 dmac 6 smac 6 length 2 <=1500 fcs 4 056111213 data 38-1492 14 19 20 21 802.2 6 type 2 0x0800 22 dmac 6 smac 6 0x8100 2 fcs 4 056111213 data 34-1488 14 15 25 26 802.2 6 type 2 0x0800 vlan id 2 length 2 <=1500 16 17 18 23 24 dmac 6 smac 6 0x8100 2 fcs 4 056111213 data 42-1496 14 15 vlan id 2 type 2 0x0800 16 17 18 ethernet ii ethernet 802.3 ethernet 802.1p with ethernet ii ethernet 802.1p with ethernet 802.3 ethernet framing enable = 1 ip header 24 37 l4 header offset tcp/udp* 16 l4ofs l4ofs+15 ip header** 24 l4 header offset tcp/udp* 16 l4ofs l4ofs+15 45 ip header 24 l4 header offset tcp/udp* 16 l4ofs l4ofs+15 41 ip header** 24 l4 header offset tcp/udp* 16 l4ofs l4ofs+15 49 * if l4 extraction enable = 1 & protocol = tcp/udp l3 header extraction enable = 1
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 66 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 20 headers formats within packet 3.3 control unit the control unit (or control logic block) consists of registers required to control the operation of the PM2329 and its various internal blocks, and state machines to perform the control functions. the registers of the control logic block include various configuration and status registers for controlling the oc processing, as well as the 64-entry oc descriptor table. a brief description of some of these key registers follows: operation control register - this register controls the operation modes of the PM2329. interrupt enable register - this register specifies the mask bits for the various conditions that can cause the PM2329 to assert an external interrupt. status register - a register that provides common information regarding the state of the single or cascaded PM2329 devices. oc descriptors - registers that define the processing of the oc. details of register definitions, as well as oc descriptor format and usage, is available in 4. 3.4 policy search engine (pse) the PM2329 policy search engine (pse) is the work-horse of rules processing. it can perform powerful policy-based search operation sequences, applying rules from the 16k-deep rule memory and comparing a specified sequence of rules with the extracted key information from the fee. it generates detailed results of those searches, and returns those results (under control of the control unit) throuh the cascade interface to the results fifo. 01 23 4567 89 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ipv[7:4] ihl[3:0] length fragment offset lower 13 bits ttl ip header protocol sip dip 01 23 4567 dp tcp/ udp sp 89 10 11 12 13 14 15 flags fin syn rst ack tcp flags bytes bytes 01 23 4567 802.2 header dsap 1 bytes ssap 1 control 1 protocol id/ org code 3 type 2 0x0800 802.2 llc 802.2 snap*** *** 802.2 snap valid if dsap=0xaa, ssap=0xaa and control=0x03 ** ip header for 802.3 valid only if dsap=0xaa, ssap=0xaa, control=0x03 protocol id = 0x000000 and type=0x0800
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 67 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet operation cycle (oc) the pse performs operation cycles (referred to throughout this data book as ocs) on packets in the order that their field extraction is complete. the processing of any one search using one key constitutes a single oc. as there could be multiple keys extracted from a packet, and as each key can be subjected to multiple searches, a packet can utilize many ocs for full processing. an oc is complete when the key is compared against a specific rule, and the results are queued in the results fifo. the time duration of an oc depends therefore on the availability of space in the results fifo; if the oc must wait for space, it remains active until space is available. oc sequencing the order in which searches are performed for a particular key (that is, the order in which ocs execute) is called oc sequencing. there are 2 basic types of oc sequencing: occ sequencing and e-ram sequencing. within each type, sequencing can be automated or processor controlled. chapter 5 describes the sequencing modes in detail. 3.4.1 rule memory the rule memory can store up to 16,384 rules in on-chip memory. this rule memory is composed of cells arranged into rows and columns. each rule is stored in a location known as a cell. the PM2329 can perform multiple and simultaneous data operations on the extracted fields of the input packet and the specified set of rules (cells) in the rule memory. refer to chapter 5 for a description of the rules and oc sequencing. 3.4.2 cell organization the organization of the cells in the rule memory is shown in figure 21. the smallest element is a cell, which contains a single rule. rules are grouped into "rule packs" of 16 cells (that is, up to 16 rules) each. the rule pack represents the smallest number of cells that can participate in any oc. therefore, partitioning of rules among different ocs is done in "rule pack" units. rule packs themselves are further organized into a two dimensional array consisting of 64 rows and 16 columns. each row contains 16 rule packs, and each column contains 64 rule packs. figure 21 illustrates. each cell can be uniquely identified by the row number (0-63) and column number (0-15) of the rule pack, and finally by its position (0-15) within the rule pack to which it belongs. the cell address is a 14-bit number where the most significant 6 bits represent its row number, the middle 4 bits indicate its column number, and the least significant 4 bits describe its position within the rule pack. the unique cell number of each cell ranges from 0 to 16,383 for a single PM2329 device.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 68 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 21 organization of rules 3.4.3 priority of rules there is an inherent priority structure built into the rule memory, with each of the 16k rules having a distinct priority. the priority of a rule is a function of the cell number. rules at lower cell numbers have higher priority. thus, priority is first determined by its row number, then its column number, and lastly by its position within the rule pack. rule 0 has the highest priority and rule 16,383 has the lowest priority. the priority structure allows prioritization of match results when multiple rules match the packet key data. in the case of multiple matches in the pse, the matched rule (cell) numbers are returned in the order of their priority. 3.4.4 rule partitions a partition is defined as a collection of rule packs. the selection of rule packs that belong to a partition is decided by specifying row numbers and column numbers. the row numbers are specified as a range, while the column numbers are defined by an enable bit for each column. for example, rows 6 to 9 and columns 13 and 15 can be defined as a partition. separately, rows 3 to 4 and columns 0, 1, 2 ? 15 can be defined as rows 0 63 columns 5 15 cell 0 cell 255 cell 16383 cell 16128 rule pack rule 0 rule 15 62 1 2 3 4 6 7 8 9 10 61 oc3 oc1 oc1 oc2 0 1 13 14
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 69 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet a second partition. both these partitions are shown in figure 21 as "oc1" and "oc2" respectively. partitions are used when running operation cycles (ocs). an oc executes over a specific partition, and typically all rules in a partition participate in the same kind of operation. from a software point of view, a partition will consist of cells storing rules relating to a specific networking operation. for example, routing rules, firewall rules, qos rules, etc. in general, partitions can overlap; for example, two partitions can point to the same rule space. this is useful when multiple software contexts in a network processor access rule memory; partitions can then be associated with the appropriate context. another situation where rule space sharing is beneficial is in mac address tables where the source and destination mac addresses can be maintained in one table. 3.5 e-ram operation the basic functionality of a single PM2329 or a cascade of multiple PM2329 devices can be greatly enhanced by the addition of the extended ram. the e-ram may be used for storing statistical counts, aging, and per-connection state information. it can also be used to implement conditional sequencing of multiple ocs. oc sequencing is a powerful way of selectively running multiple classification operations on a single packet. the PM2329 ? s e-ram interface is designed to work with or without cascading. it allows external synchronous pipelined sram to be gluelessly interfaced to the PM2329. the PM2329 supports up to a maximum of 128k word deep e-ram, allowing up to a word per rule when using 8 cascaded PM2329 devices (128k rules). the width of the e-ram can be decided based upon the system requirements, with the maximum width specified by the number of cascaded PM2329 devices. a single PM2329 can interface to a 64-bit-wide e-ram, and each additional PM2329 in the cascade allows an additional 32 bits to be added to the e-ram word width, up to a maximum of 256 bits with 7 PM2329 devices in cascade. PM2329 chip #7 (the eighth chip of a cascade) does not support an additional 32 bits of e-ram width. figures in chapter 2 show some typical configurations using e-ram. 3.5.1 organization of e-ram words every e-ram word (e-word) is composed of the following fields: further details of e-word format and e-ram based oc sequencing is provided in chapter 5. 3.6 cascade operation the cascade bus allows up to 8 PM2329 devices to work in parallel, appearing to the external processor as a single large PM2329 chip. the 16k-rule memory size of a single PM2329 is thus expandable up to 128k rules on 8 PM2329 devices. the rule set of an operation cycle (oc) can be spread across several PM2329 devices allowing greater parallelism in operation across a larger rule memory space. extended memory word (e-word) control word (32 - bit) c-word data words (d-words) byte count (32-bit) packet count (32-bit) timestamp/state (24/8- bit) user defined (32-bit)
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 70 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet each PM2329 in the cascade has its cid pins uniquely wired to the supply rails. these cid pins are sampled on reset, thereby assigning a unique cid# (0 to 7) to each PM2329. rules participating in an oc running across multiple PM2329 devices are now prioritized by cid# of the PM2329 to which they belong. thus, for any oc, all the rules within PM2329 #0 will have a higher priority than rules for that oc within PM2329 #1. priority decreases with increasing cid#; the priority of a rule match is automatically determined among the PM2329 devices by communication over the cascade interface. ocs can be processed as "single hit" or "multiple hit" ocs, referring to the number of matches that should be processed before execution is terminated and a result is returned. in the case of a single-hit oc, a single result is generated--the result of the first match found. in case of a multi-hit oc, a result is generated for each match found. a single-hit oc execution is terminated as soon as the first (highest priority) match is found. in case of a multi-hit oc, all the rules in the oc are executed and all matches are returned (in order of priority) the external processor need not determine in which PM2329 a match has occurred, since the appropriate information is returned when it reads the globally accessible results fifo.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 71 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4 registers 4.1 PM2329 access modes the mechanism to access the internal status and programmable locations within the PM2329 device permits simple and flexible access in a variety of configurations. the access mechanism provides a consistent interface to the external processor in both single-chip or cascade (multi-chip) configurations. the PM2329 can be connected to either a 64-bit or a 32-bit interface on the packet processor. the access mechanism allows multiple contexts on the packet processor to communicate easily with an assigned channel within the PM2329. 4.1.1 address space the PM2329 address space is divided into local and global spaces. the concept of local vs. global addressing is relevant to the cascade (multi-chip) configuration. local space in general represents registers involved with processing functions that are specific to a particular PM2329 device. global space in general represents registers involved with processing functions that span all PM2329 devices in the cascade. a conceptual view of global and local register space is considered in figure 22. figure 22 local vs. global register space; conceptual view a each register within the PM2329 is mapped either to local or global address space. the access mode is determined by the state of the sa[15] address line in any given access cycle. if sa[15] is low, the access is to the local space. if sa[15] is high, the access is to the global space. the other address lines dictate which specific PM2329 device, and which specific register within the prescribed space of that device, is accessed. the PM2329 has three pins (cid[2:0]) which are sampled at reset to assign a unique PM2329 id number (cid #n) to each chip in the cascade. the value on these pins during reset must be set up to assign a serial number from 0 to n to each PM2329 device, where n varies from 0 to 7. in single chip configuration, the PM2329 is assigned cascade id #0 (or cid #0). when the local address space is accessed (sa[15] is low), each PM2329 compares the address lines sa[14:12] with its cid #n. if they match, then the particular PM2329 device is accessed. network processor PM2329 cid #0 local address space PM2329 cid #1 local address space PM2329 cid #2 local address space PM2329 cid #n local address space global address space
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 72 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet when the global address space is accessed (sa[15] is high), all PM2329 devices participate in the operation. when a global write is performed, all PM2329 devices are written. when a global read is performed, all devices in the cascade respond in turn, while an internal address resolution mechanism within the PM2329 devices avoids contention. once initialization is complete and local PM2329 registers are configured, the network processor thereafter treats the bank of cascaded PM2329 devices as a single PM2329 device; whether a single device or a cascade of devices is implemented, there is no difference in the interface protocol. (thus, in discussion throughout this data book, references to ? the PM2329 device ? can mean a single device or multiple cascaded devices.) 4.1.2 channels the PM2329 implements a set of thirty two channels to support independent contexts of the external network processor (a network processor divides packets among its various processing cores; each stream of packets from any given core represents a context to the PM2329 device[s]). PM2329 channels can be assigned to these contexts; each context can send a packet to PM2329 in an independent manner and then fetch its own classification results. packet input activities, as well as access to results, can be interleaved between the various contexts. to facilitate packet transfers, on board each PM2329 device is a packet input buffer--an input fifo which is the first element in the data path inboard from the network processor (system) interface. the packet input buffer ? s physical size is 256 bytes times the maximum number of channels supported in hardware, or 256 x 32 bytes. the packet input buffer can be accessed using either a single write port (called the packet buffer input register, or pbir), or with sram-like addressing. the packet input buffer resides in global address space. thus, when packets are written to a packet input buffer, they are written simultaneously to all packet input buffers of all cascaded PM2329 devices. at any given time, then, all packet input buffers are identical, and all PM2329 devices in the cascade have the opportunity to utilize or classify each packet. figure 23 PM2329 packet input buffer to facilitate the return of processing information back to the network processor ? s context, each PM2329 device has a results fifo that can hold 8 entries per channel, or (32 x 8) = 256 entries total. like the packet input buffer, the results fifo can be accessed using either a single write port, or with sram-like addressing. the results fifo also resides in global address space. 256 bytes 32 segments (one per channel) 8 k b y t e s t o t a l
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 73 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet the PM2329 channels are implemented through segmentation of the packet buffer and the results fifo. channel segments may be concatenated to allow larger packet or result storage for a given channel (with correspontingly fewer channels supported). 4.1.3 channel register blocks PM2329 registers involved in packet transfer, packet processing status and packet results are organized into channel register blocks. there is one block of channel registers for each of the 32 possible channels. these registers reside in global address space. thus, every PM2329 in a cascade has them, and a write to them by the network processor affects all devices in the cascade. figure 24 channel register blocks as illustrated in figure 24, each channel ? s register block is spread over four address regions identified by base addresses 0 to 3. however, the specific registers of each channel have a unique offset relative to base addresses. that is, for any given channel, the offset distinguishes the channel ? s registers from corresponding registers of other channels. thus, each context on the packet processor can access a particular channel easily, and perform its own packet processing independently. (the four base address spaces differ in size, so a channel ? s offset from base 0 will differ from its offset from base 1, or 2, or 3.) figure 25 and table 18 show the complete register block address space. 4.1.4 direct and indirect access the registers of the PM2329 are accessed using direct addressing by directly reading or writing to these registers. memory locations controlled by the PM2329 (the e-ram and PM2329 rule memory), however, are accessed using indirect addressing. this is done by writing and reading a set of address, data and command registers. the following registers provide indirect access to the rule memory: rule indirect address register, rule indirect data register, and rule indirect command register. the following registers provide indirect access to the e-ram: e-ram indirect address register, e-ram indirect data register, and e-ram indirect command register. base 3 addresses base 2 addresses base 1 addresses base 0 addresses register block for channel 0 register block for channel 1 register block for channel 2 register block for channel 3 register block for channel 31 no offset from base addresses ch1 ? s offsets from bases ch2 ? s offsets from bases ch3 ? s offsets from bases ch31 ? s offsets from bases
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 74 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet both sets of indirect access registers support an auto-increment mode which is optimized for writing or reading a block of data. enabling auto-increment avoids repeated writes to the address and command registers. also, if initializing a block of locations with the same data, multiple writes to the data register can be avoided. 4.2 register interface 4.2.1 programmable register overview the table below lists the registers of the PM2329 and their addresses. these are all addressable using direct addressing. the table shows the register address for a 64-bit packet processor. the source and table 17 PM2329 register memory map #register name mode local or global source (processor read) destination (processor write) address 1 local configuration register r/w local cid n cid n n000h 2 rule indirect command register r/w local cid n cid n n008h 3 rule indirect address register r/w local cid n cid n n010h 4 rule indirect data register set reg 0 reg 2 reg 4 r/w local cid n cid n n018h n020h n028h 5 oc descriptors upper ocd 0 lower ocd 0 upper ocd 1 lower ocd 1 ... upper ocd 63 lower ocd 63 r/w local cid n cid n n400h n408h n410h n418h .. n7f0h n7f8h 6 e-ram indirect data register set c-word : d-word 0 d-word 1: d-word 2 d-word 3 : d-word 4 d-word 5 : d-word 6 r/w global cid 0 cid 1: cid 2 cid 3 : cid 4 cid 5 : cid 6 cid 0 cid 1 : cid 2 cid 3 : cid 4 cid 5 : cid 6 8200h 8208h 8210h 8218h 7 e-ram indirect command register r/w global cid 0 cid 0~7 8220h 8 e-ram indirect address register r/w global cid 0 cid 0~7 8228h 9 e-ram configuration register r/w global cid 0 cid 0~7 8230h 10 interrupt enable register r/w global cid 0 cid 0~7 8238h 11 status register ro global cid 0 na 8240h 12 operation control register r/w global cid 0 cid 0~7 8248h 13 channel assignment register r/w global cid 0 cid 0~7 8250h 14 oc conductor register r/w global cid 0 cid 0~7 8258h 15 packet information register r/w global cid 0 cid 0~7 8260h 16 timer register r/w global cid 0 cid 0~7 8268h
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 75 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet destination columns show the PM2329 devices participating in the read or write operations, respectively. cid n indicates the address device n responds to the access, cid # or #~# indicates the device with the specified id responds to the access. in the address column, the addresses for local registers are shown as ? nnnn ? (for example, ? n000 ? ). to access the register of a specific PM2329 device in the cascade, substitute a number from 0 to 7 for ? n ? , depending on the device to be accessed. for example, in a single PM2329 system or to access the primary PM2329 in a cascade, ? n ? would equal ? 0 ? . PM2329 registers generally fall into one of three categories: setup and control, packet input, and result output. they must be written to or read from in specified sequences and at appropriate times to ensure proper device operation. for example, improperly sequenced or ill-timed modification of setup and control registers when a packet is being processed by the device can result in operation failure, the new value being ignored, or some other unpredictable behavior. all PM2329 registers are 64-bit locations; however, they can be accessed either in 64-bit or 32-bit mode. if the processor executes a 64-bit access using a register address specified in table 17, it will accesses the entire register. if the processor executes a 32-bit access using the same address, it will access the upper half of the register (bits 63:32). to access the lower half (bits 31:0) of the register using 32-bit access, the value ? 04h ? should be added to the address specified in table 17. bits in every register are aligned toward bit 0 (that is, right-aligned), so for all registers with bits in the lower half only, 32-bit accesses should be at the address+04h location. figure 25 provides a graphical representation of the address space. 17 alternate oc conductor register r/w global cid 0 cid 0~7 8270h 18 channel register block base addresses see table 4.2 for further details see table 19 global see table 19 see table 19 8400h - 8600h, c000h - cfffh, d000h - d7ffh, e000h - ffffh table 17 PM2329 register memory map #register name mode local or global source (processor read) destination (processor write) address
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 76 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 25 PM2329 address space base 3 addr. 0000 1000 2000 3000 4000 5000 6000 7000 8000 9000 a000 b000 c000 d000 e000 f000 0000 0400 0800 0200 0600 ridr4 ridr2 ridr0 riar ricr lcr ier ecr eiar eicr eidr 6 eidr 4 eidr 2 eidr 0 8200 8208 8210 8218 8220 8228 8230 8238 tmr pir occ car ocr sr 8240 8248 8250 8258 8260 8268 locd 1 uocd 1 locd 0 uocd 0 locd 63 uocd 63 locd 62 uocd 62 ... g l o b a l l o c a l csr-ch0 8400 8408 8000 8400 8200 8600 eop-d1-ch0 uocd 62 ch 18-1f ch 10-17 ch 8-f c000 c800 d000 d200 c400 cc00 d100 d300 ch 18-1f ch 10-17 ch 8-f ch 0-7 ch 1c-1f ch 18-1b ch 14-17 ch 10-13 ch c-f ch 8-b ch 4-7 ch 0-3 result memory space 0 +0000 +0008 +0010 +0018 +00f0 +00f8 ch 1f ... ... ... ch 0 data-ch1f data-ch1f data-ch1f data-ch1f data-ch1f data/eop-d0-ch1f +0000 +0008 +0010 +0000 +0008 +0010 +0018 +0000 +0008 +0010 +00f0 +00f8 data-ch0 data-ch0 data-ch0 data/eop-d0-ch0 data-ch0 data-ch0 +0018 packet memory space +0000 +0008 +0010 +0000 +0008 +0010 +0018 ocrf-ch1f +0070 +0078 ch 1f ... ... ch 0 8 results per channel drf0,1-ch1f ocrf-ch1f ocrf-ch1f drf0,1-ch1f drf0,1-ch1f +0000 +0008 +0010 +0000 +0008 +0010 +0018 ocrf-ch0 +0000 +0008 +0010 +0018 +0070 +0078 drf0,1-ch0 ocrf-ch0 ... ocrf-ch0 drf0,1-ch0 ... drf0,1-ch0 +0000 +0008 +0010 +0018 ... ch 0 1 result group per channel, 32 bytes ch 0-7 result memory space 1 pocrh,pocrl drf2,3-ch0 drf4,5-ch0 drf6-ch0 pocrh,pocrl drf2,3-ch0 drf4,5-ch0 drf6-ch0 ... ... ch 1f +0018 +0010 aoccr 8270 eop-d1-ch1f 85f8 ch 0 ... ... ch 1f cid0 cid1 cid2 cid4 cid6 cid3 cid5 cid7 e000 e800 f000 f800 e400 ec00 f400 fc00 base 2 addr. base 1 addr. base 0 addr.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 77 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 18 summarizes the address assignments. note that all reserved bits must be written with zeroes. when read, reserved bit values returned will be invalid and must be masked out by the processor. table 18 shows the channel register block base addresses for each of the 32 channels. note that each channel has four blocks of registers at four separate base addresses. relative to the base addresses, individual channel registers can be accessed as shown in table 19 below. table 18 channel register block base addresses base 0 base 1 base 2 base 3 channel number csr and eop-d1 oc result and data result 0/ 1 data result 2/ 3, data result 4/5, and data result 6 packet input and eop d0 0 8400h c000h d000h e000h 1 8410h c080h d020h e100h 2 8420h c100h d040h e200h 3 8430h c180h d060h e300h 4 8440h c200h d080h e400h 5 8450h c280h d0a0h e500h 6 8460h c300h d0c0h e600h 7 8470h c380h d0e0h e700h 8 8480h c400h d100h e800h 9 8490h c480h d120h e900h 10 84a0h c500h d140h ea00h 11 84b0h c580h d160h eb00h 12 84c0h c600h d180h ec00h 13 84d0h c680h d1a0h ed00h 14 84e0h c700h d1c0h ee00h 15 84f0h c780h d1e0h ef00h 16 8500h c800h d200h f000h 17 8510h c880h d220h f100h 18 8520h c900h d240h f200h 19 8530h c980h d260h f300h 20 8540h ca00h d280h f400h 21 8550h ca80h d2a0h f500h 22 8560h cb00h d2c0h f600h 23 8570h cb80h d2e0h f700h 24 8580h cc00h d300h f800h 25 8590h cc80h d320h f900h 26 85a0h cd00h d340h fa00h 27 85b0h cd80h d360h fb00h 28 85c0h ce00h d380h fc00h 29 85d0h ce80h d3a0h fd00h 30 85e0h cf00h d3c0h fe00h 31 85f0h cf80h d3e0h ff00h
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 78 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 19 channel registers #register namemode local or global source (processor read) destination (processor write) address 1 channel status register ro global cid 0 na base 0 +00h 2 end of packet data direction1 wo global na cid n base 0 +08h 3 oc result fifo/ oc result 0 ro global cid n a na base 1 +00h 4 data result 0/1 fifo/ data result 0/1 0 ro global cid n na base 1 +08h 5 oc result 1 ro global cid n a na base 1 +10h 6 data result 0/1 1 ro global cid n na base 1 +18h 7 oc result 2 ro global cid n a na base 1 +20h 8 data result 0/1 2 ro global cid n na base 1 +28h 9 oc result 3 ro global cid n a na base 1 +30h 10 data result 0/1 3 ro global cid n na base 1 +38h 11 oc result 4 ro global cid n a na base 1 +40h 12 data result 0/1 4 ro global cid n na base 1 +48h 13 oc result 5 ro global cid n a na base 1 +50h 14 data result 0/1 5 ro global cid n na base 1 +58h 15 oc result 6 ro global cid n a na base 1 +60h 16 data result 0/1 6 ro global cid n na base 1 +68h 17 oc result 7 ro global cid n a na base 1 +70h 18 data result 0/1 7 ro global cid n na base 1 +78h 19 previous oc result ro global cid n a na base 2 +00h 20 data result 2/3 ro global cid n na base 2 +08h 21 data result 4/5 ro global cid n na base 2 +10h 22 data result 6 ro global cid n na base 2 +18h
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 79 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet note: a. cid n or cid 0 if no valid result is available. 4.2.2 register description this section provides a description of the registers in the PM2329. this section also specifies the access mode: local vs.global, and the access type: read only, write only, or read/write, for each register. in each register bit description table, the reset values shown in the ? value after reset ? column applies to both soft and hard reset conditions. for local addresses shown, substitute cid numbers 0, 1, 2,... or 7 for ? n ? depending on the PM2329 to be accessed. 23 packet buffer input wo global na cid 0~7 base 3 +00h +08h ... +f0h 24 end of packet data direction0 wo global na cid 0~7 base 3 +f8h table 19 channel registers #register namemode local or global source (processor read) destination (processor write) address
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 80 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.1 local configuration register (lcr; n000h) access mode: read/write, local this register returns bits that indicate the hardware configuration of the PM2329. all bits, except bit 62, are read-only. bist result this bit indicates the result of the last bist run. it should be read after the bist operation has been enabled (bist enable/status lcr[62] is written with 1) and the bist execution is complete (indicated by bist enable/status lcr[62] = 0). when sampled, if this bit lcr[63] is 0, then the bist failed; if this bit is 1, then the bist passed. this bit is set to 0 when bist enable/status lcr[62] is written with 1. this bit is 0 after reset. bist enable/status this bit controls the operation of the on-chip bist facility for internal ram blocks. writing a 1 to this bit activates the bist operation inside the device. this bit will stay 1 as long as the bist operation is in progress, and it will become 0 when the bist execution is complete. after the bist sequence is completed successfully, the following on-chip resources are initialized: rule memory:no match ocds: invalid oc since all rules are loaded with no match and all ocds are loaded with invalid ocs, control software need not initialize unused rules and ocds. this bit is 0 after reset. bit range size name value after reset 63 1 bist result 0 62 1 bist enable/status 0 61:59 3 (reserved) undefined 58 1 sch timing mode select 0 57:53 5 (reserved) undefined 52:32 21 (reserved) 00 0000h 31:24 8 device revision number 04h 23:18 6 (reserved) undefined 17:16 2 pll multiplier pll multiplier 15:8 8 cascade mask cascade mask 7 1 (reserved) undefined 6 1 zbt enable zbt mode 5 1 system i/f bus width sys i/f bus width 4:2 3 cid number cid# 1:0 2 (reserved) undefined
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 81 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet sch timing mode select this bit controls the clock frequency at which the schstb and schnum operate. this bit can be configured as follows: 0: schstb and schnum[] operate at the same frequency as sclk. 1: schtb and schnum[] operate at half the frequency of sclk. device revision number this field indicates the revision number of the device. for the PM2329-a1, this field is hardwired to 04h. plla multiplier these two bits indicate the value of the plla multiplier sensed at reset. for a description of this field ? s value and the corresponding plla multiplier, see the pllactrl[1:0] description in chapter 2, section 2.2 pin description table. cascade mask these bits specify which of the chips in the cascade were detected via handshake using cocdout lines during reset. the external processor can read this field to determine the number of PM2329 devices in the cascade. zbt enable this bit indicates the value of zbt_mode signal sampled at reset. if this bit is ? 0 ? , a low level was sensed at reset and the PM2329 system interface is configured for syncburst mode. if this bit is ? 1 ? , a high level was sensed at reset and the PM2329 system interface is configured for zbt operation. system interface bus width this bit indicates the value of sd_width signal sampled at reset. if this bit is ? 0 ? , a low level was sensed at reset and the PM2329 is configured for 32-bit mode. if this bit is ? 1 ? , a high level was sensed at reset and the PM2329 is configured for 64-bit mode. cid number these 3 bits return the PM2329 id number for that particular PM2329 as set up by the cid[2:0] inputs sensed at reset.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 82 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.2 rule indirect command register (ricr; n008h) access mode: read/write, local this register controls the indirect access mechanism to the policy database rule memory cells in the PM2329. the values in rule memory cells are accessed using the ridr registers (explained in section 4.2.2.4). the diagram below shows the policy database rule memory cell mapping to these (ridr0~4) registers. figure 26 access to rule memory cells via ridr0-4 registers read/write data enable these bits enable or disable reading or writing to each of the 32-bit words comprising the 136-bit rule memory. when a bit is ? 1 ? , read or write of the corresponding word is enabled. during write, the value in the rule indirect data register will be written to the addressed rule memory location. when a bit is ? 0 ? , the corresponding word is disabled. the higher bit (bit 12) is for rule indirect data 0, and the lower bit bit range size name value after reset 63:13 51 (reserved) undefined 12:8 5 read/write data enable 00h 7:6 2 (reserved) undefined 5 1 auto-increment 0 4:2 3 trigger 000 1 1 (reserved) undefined 0 1 register set ready (ro) 1 63 0 63 0 63 0 rd0 rd1 rd2 rd3 rd4 rd5 rc 135 104103 72 71 56 55 40 39 32 31 24 23 0 r e s e r v e d ridr0 ridr2 ridr4 rd4 ridrs rule rule memory rd0 rd1 rd2 rd3 rc rd5 r e s e r v e d r e s e r v e d
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 83 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet (bit 8) is for rule indirect data 4. for example, programming a value of 01100 will enable writes to words 1 and 2 only. during read, only the enabled words are read. for a detailed description of the rule memory read and write operation, refer to the rule indirect data register set description. auto-increment if this bit is ? 1 ? , then after the read or write operation to the rule memory, the rule indirect address register is automatically incremented to point to the next cell (post-increment). this bit will normally be written with ? 1 ? when a block of data needs to be transferred to or from the rule memory. if this bit is ? 0 ? , the rule indirect address register is unchanged after a read or write operation to the rule memory. ? trigger these bits specify which of the five 32-bit data words will serve as the trigger for the PM2329 to perform the internal read or write operation to the rule memory. after the trigger word is written to or read from, the device performs read or write operation on the rule memory. these bits are programmed as follows: 000 rule indirect data register 0 001 rule indirect data register 1 010 rule indirect data register 2 011 rule indirect data register 3 100 rule indirect data register 4 101 (reserved) 110 (reserved) 111 (reserved) register set ready this bit when ? 1 ? indicates that the rule indirect registers are currently not in use. it is cleared when a read or write command is issued and remains ? 0 ? as long as the device is busy performing this operation. it is set when the device has internally executed the read or write operation. for correct operation, the processor must check that this bit is set before it writes to the ricr, riar or ridr. when the rsr bit is 0, write cycles to any of these (ricr, riar or ridr) registers are ignored. this is a read-only bit and is set to ? 1 ? after reset.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 84 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.3 rule indirect address register (riar; n010h) access mode: read/write, local this register is used to specify the address of the rule memory cell to be accessed. cell number this is the address of the rule to be accessed. this is an absolute cell number within the PM2329. if the auto-increment bit in rule indirect command register is set to ? 1 ? , then after a read or write operation is performed to the rule memory, the rule indirect address register is automatically incremented to point to the next cell (post-increment). for a detailed description of the rule memory read and write operation, refer to the rule indirect data register set description. bit range size name value after reset 63:14 50 (reserved) undefined 13:0 14 cell number 0000h
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 85 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.4 rule indirect data register set (ridr0; n018h) (ridr2; n020h) (ridr4; n028h) access mode: read/write, local this is a set of five 32-bit registers or three 64-bit registers . they are used by the processor to read or write data from the rule memory cells of the PM2329. the registers are organized as follows. register 0 register 2 register 4 note: the field names (e.g., sip, dip, sp and dp) shown in the table above are for user convenience only and generally correspond to header related fields described in the field extraction engine description. they are used for other functions depending on the usage of the rule (e.g., pattern searches use these fields to store patterns or mask values). bit range size name value after reset 63:32 32 rule bits (135:104) or rule data field #0 (sip) 0000 0000h 31:0 32 rule bits (103:72) or rule data field #1 (dip) 0000 0000h bit range size name value after reset 63:48 16 rule bits (71:56) or rule data field #2 (sp) 0000h 47:32 16 rule bits (55:40) or rule data field #3 (dp) 0000h 31:16 16 (reserved) undefined 15:8 8 rule bits (39:32) or rule data field #4 (protocol) 00h 7:0 8 rule bits (31:24) or rule data field #5 (flags (7:4) & mask (3:0)) 00h bit range size name value after reset 63:56 8 (reserved) undefined 55:32 24 rule bits (23:0) or rule control field 00 0000h 31:0 32 (reserved) undefined
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 86 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet rule memory write or read operation can be performed either in random access mode or in sequential access mode. in general, the processor should set up the rule indirect command register to specify the auto-increment mode, etc. it should then set up the address of the location or the starting address of the block of locations to be accessed. it can then access the addressed location or access sequential location depending on the programming of the auto-increment bit. note that read or write operations are performed internally when the trigger word is accessed as explained below. however, if the riar, ricr or ridr have not been written to since the last rule memory access, an internal read to the rule memory is not performed since the current ridr content correctly reflects the address rule memory content. during random reads, the processor must perform a dummy read (and discard the value read back) to trigger the actual read internally, and then perform a second read to get the real data. for sequential reads, only one (the first) dummy read is required for each block of data read sequentially. in either case, the first dummy read needs to be performed to the trigger word only. during writes, processor can simply write to the indirect data register and the device will execute the internal write cycle when the trigger word is written. there are no dummy writes to be performed, however, the processor must ensure that all the enabled data words are written to first, before the trigger word is written. as long as the processor manages rule memory write and read operations using the rsr handshake, the processor can perform these operations at any time even when oc sequencing is in progress--the read or write operation will take place arbitrated by PM2329 control logic. the software must ensure coherency of oc operation vs. its access operation. also, it must manage multiple rule word updates using the rsr bit. note that all the rules in the rule memory are initialized to no match after the bist sequence is completed successfully; control software need not initialize unused rules. rule updates when PM2329 is processing an oc when an oc is in progress, rule update for all columns that are in the partition of the current oc is deferred until the last result of the oc has been transferred out of the processing engine to the result fifo. this update deferral includes times when the processing engine has stalled if the result fifo is full, in other words, the update will not occur during processing engine stalls. note that these columns can contain rules that belong to the current partition (as defined by the rsa and rea fields) and those that do not belong to the current partition--none of the rules in these columns will be updated until the condition stated above occurs. columns that are not participating in the current oc can be updated at all times. however, note if a rule update is started that results in update deferral (since it belongs to a column of the current partition), the rsr handshake control will prevent loading of a new rule to be updated that could otherwise be updated (one that does not belong to a column of the current partition).
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 87 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet read and write sequences are explained in greater detail below. for random read operation, the processor must perform the following steps. 1. check the rsr bit is set to ? 1 ? to ensure the previous memory transaction is complete. 2. set up ricr with the data enable and trigger fields, and the auto-increment bit reset to ? 0 ? . 3. set up the riar with the address of the location to be read. 4. read the trigger word and discard the value read back. 5. wait for rsr bit to be set to ? 1 ? 6. read the content of the addressed location by reading the ridr (the ridr set as trigger word should be read last). to read a set of random locations, steps 1 through 6 outlined above can be repeated. however, a set of random reads can be optimized (only one dummy read for a set of random reads), if (step 5a) the address of the next random location to be read is loaded in the riar after step 5, before reading the previous locations content in step 6. in this case, the processor can simply repeat steps 5, 5a, and 6 until all the ramdom location have been accessed. for random write operation, the processor must perform the following steps. 1. check the rsr bit is set to ? 1 ? to ensure the previous memory transaction is complete. 2. set up ricr with the data enable and trigger fields, and the auto-increment bit reset to ? 0 ? . 3. set up the riar with the address of the location to be written. 4. write the ridr, the trigger word should be written last. for sequential read operation, the processor must perform the following steps. 1. check the rsr bit is set to ? 1 ? to ensure the previous memory transaction is complete. 2. set up ricr with the data enable and trigger fields, and the auto-increment bit set to ? 1 ? . 3. set up the riar with the start address of the locations to be read. 4. read the trigger word and discard the value read back. 5. wait for rsr bit to be set to ? 1 ? 6. read the content of the addressed location by reading the ridr (the trigger word should be read last). repeat steps 5 and 6 to read the rest of the memory block.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 88 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet for sequential write operation, the processor must perform the following steps. 1. check the rsr bit is set to ? 1 ? to ensure the previous memory transaction is complete. 2. set up ricr with the data enable and trigger fields, and the auto-increment bit set to ? 1 ? . 3. set up the riar with the start address of the locations to be written. 4. write the ridr, the trigger word should be written last. 5. wait for rsr bit to be set to ? 1 ? repeat steps 5 and 6 to write the rest of the memory block. 4.2.2.5 oc descriptors (ocd; n400h, n408h...n7f0h, n7f8h) access mode: read/write, local oc descriptor each ocd occupies two consecutive 64-bit locations: upper ocd [n] and lower ocd [n], where n is the oc descriptor index. ocdi. since each full oc descriptor is 96 bits wide spanning two 64-bit register locations or three 32-bit register locations, the user must exercise caution when updating the oc descriptor while an oc that uses this oc descriptor is executing. oc descriptors can be updated without any side effects when: 1) no oc execution is in progress, or 2) if the oc descriptor to be updated will not be used by the current oc that is executing. upper oc descriptor bit range size name value after reset 63 1 oc descriptor valid undefined 62:61 2 oc type undefined 60 1 enable multi-hit undefined 59:54 6 row start number undefined 53:48 6 row end number undefined 47:32 16 column select enable undefined 31:29 3 (reserved) undefined 28:16 13 pattern search start offset undefined 15 1 pattern search direction undefined 14:11 2 (reserved) undefined 12:0 13 pattern search count undefined
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 89 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet lower oc descriptor the PM2329 contains a total of 64 oc descriptors (ocd), which are used to describe the oc partition to be executed. the oc to be executed is specified by a 6-bit ocd index programmed into the oc conductor or into the e-ram control word. note that all the ocds are initialized to invalid oc after the bist sequence is completed successfully; control software need not initialize unused ocds. oc descriptor valid the ocd is executed only if this bit is set. if an ocd index points to an ocd with this bit cleared, it will terminate with oc done without match. no error condition is flagged in this case. oc type the field specifies the type of oc to be executed, valid values are: 00 header oc 01 attribute oc 10 pattern search short (up to 12 bytes) 11 pattern search long (up to 192 bytes) note that the header oc and pattern search ocs (short or long) use packet data information and their execution starts when the eop is detected during packet transfer. in case of attribute oc, if the attribute data is supplied during packet transfer, the same technique (eop) can be used to start oc execution, however, if the attribute data is in the packet information register, the processor must execute a dummy write cycle to the eop port in order to start the oc execution. enable multi-hit if this bit is ? 0 ? , the oc execution returns the highest priority result only (single hit oc). if the bit is ? 1 ? , then all the match results are returned in a prioritized order (multi-hit oc). the number of results generated by a multi-hit oc are not predictable. row start number this field specifies the rule memory row for the start of the partition which will participate in the oc. bit range size name value after reset 63:32 32 (reserved) undefined 31:29 3 (reserved) undefined 28:16 13 e-word segment base offset undefined 15:13 3 (reserved) undefined 12:0 13 partition start offset undefined
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 90 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet row end number this field specifies the last rule memory row which will participate in the oc. this field along with the row start field gives the range of rows for the partition. note that row start number and row end number specification wraps around. in other words, the following applies: 1. if row start number and row end number are equal, the partition spans one row. 2. if row start number is less than row end number, the partition spans from row start number from row end number 3. if row start number is greater than row end number, the partition spans from row start number to row 63 and then from row 0 up to row end number. column select enable this field specifies which columns are included in the oc partition. this field assign one bit per column, the highest bit specifies column 15 and the lowest bit specifies column 0. a column participates in the oc only if the corresponding bit is ? 1 ? . pattern search start offset this field is only valid for a pattern search (short or long) oc. this field specifies the starting offset in the packet data which will be scanned to search for a set of preloaded patterns. bytes are taken starting from this offset (and incrementing or decrementing based on search direction) to form the data source for the oc. the first byte of the packet is at offset 0. pattern search direction this field is only valid for a pattern search (short or long) oc. if this bit is ? 0 ? , the pattern search is in the forward direction (incrementing offsets). if this bit is ? 1 ? , the pattern search is in the reverse direction (decrementing offsets). pattern search count this field is only valid for a pattern search (short or long) oc. this field specifies the window (in bytes) in the packet data which will be scanned to search for a set of preloaded patterns. note that this window specifies the starting offset (0) of the string. e-word segment base offset this field defines the starting location of the e-word segment corresponding to this oc. an e-ram segment associated with an oc can start on a 16 location boundary, so the value in this field is multiplied by 16 for calculating the location of the e-word to access. partition start offset for any oc partition spanning multiple PM2329 devices, the relative cell offset of the first (highest priority) cell of the partition is defined by this field. since oc partitions can be defined only on 16 cell boundaries, this field is multiplied by 16 to get the actual absolute partition start address.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 91 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.6 e-ram indirect data register set (eidr0; 8200h) (eidr2; 8208h) (eidr2; 8208h) (eidr4; 8210h) (eidr6; 8218h) access mode: read/write, global the procesor views these registers as a set of 32-bit registers which are used to write or read data from locations in the e-ram devices attached to the PM2329. recall that each PM2329 device has a 32-bit e-ram control bus and a 32-bit e-ram data bus. further, the e-ram control bus from all devices is connected to a shared memory device, and the e-ram data bus from each device is connected to a separate memory device. to access all these memory devices over the e-ram bus, there are essentially two e-ram access registers implemented in the PM2329--one that can access the memory connected to the control bus and the other that can access the memory connected to the data bus. these two e-ram access registers are mapped to the c-word bus and d-word bus of the PM2329 cascade depending on the cid# of the PM2329 as shown in below. PM2329 0 c-word bus PM2329 0 d-word 0 bus PM2329 1 d-word 1 bus PM2329 2 d-word 2 bus PM2329 3 d-word 3 bus PM2329 4 d-word 4 bus PM2329 5 d-word 5 bus PM2329 6 d-word 6 bus PM2329 7 no d-word bus supported note that both the c-word and the d-word 0 buses are accessed using cid#0 and no d-word is supported on cid#7. in other words, both the e-ram access registers in the PM2329 with cid#0 are used, only one of the two e-ram access registers in cids #1 through #6 are used and neither of the e-ram access registers in cid#7 are used. this register set contains as many 32-bit registers as the physical width of the connected e-ram. based on the read/write data enable in the e-ram indirect address register, the cascaded PM2329 devices can read from or write to multiple 32-bit e-ram words in a single cycle. the e-ram configuration register defines how the e-ram is configured. based on the configuration, the e-ram contains a c-word (mandatory) and a set of (optional) d-words. since these registers are distributed across the cascaded PM2329 devices, their validity depends on the number of PM2329 devices in the cascade. shown below is the association of these registers with the cid# of the PM2329 devices:
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 92 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet eidr0 high cid#0 eidr0 low cid#0 eidr2 high cid#1 eidr2 low cid#2 eidr4 high cid#3 eidr4 low cid#4 eidr6 high cid#5 eidr6 low cid#6 the structure of the e-ram indirect data register set is as follows: control word/d-word 0 d-word 1/d-word 2 d-word 3/d-word 4 d-word 5/d-word 6 for a description of the fields and associated values in the e-ram, see section 4.3.2 for a detailed description of the e-ram access mechanism, refer to the rule memory indirect data register section. processor access mechanism to e-ram memory through the e-ram indirect register set (data, command and address) is similar to the rule memory access mechanism with the following differences. bit range size name value after reset 63:32 32 control word bus undefined 31:0 32 data word 0 bus undefined bit range size name value after reset 63:32 32 data word 1 bus undefined 31:0 32 data word 2 bus undefined bit range size name value after reset 63:32 32 data word 3 bus undefined 31:0 32 data word 4 bus undefined bit range size name value after reset 63:32 32 data word 5 bus undefined 31:0 32 data word 6 bus undefined
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 93 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet rule memory for each PM2329 device is local to it and contained on-chip, i.e., the processor sees as many rule memory blocks as the number of PM2329 devices in the cascade with their own associated address pointers and indirect data registers for access. while various PM2329 devices have separate e-rams attached to them, they present a unified view (a common block of memory) to the processor accessed via a common address pointer and a distributed yet common set of indirect data register set. additionally, the e-ram access mechanism supports the auto increment mode select bit as explained in the e-ram indirect command register section. it also has a depth level field (part of the e-ram address) as explained in the e-ram indirect address register section. as long as the processor manages e-ram write and read operations using the rsr handshake, the processor can perform these operations at any time even when oc sequencing is in progress--the read or write operation will take place arbitrated by PM2329 control logic. the software must ensure coherency of oc operation vs. the access operation. also, it must manage multiple e-ram updates using the rsr bit. unlike ridr (rule memory access mechanism) read operation, reading the eidr set as the trigger word will always cause an e-ram read operation regardless of whether the eicr, eiar or eidr were written to or not since the last eram read operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 94 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.7 e-ram indirect command register (eicr; 8220h) access mode: read/write, global read/write data enable this field enables or disables reading or writing to each of the 32-bit physical e-rams, which may be up to (32 x8) 256 bits wide. when a bit is ? 1 ? , it enables the corresponding e-ram access. when a bit is ? 0 ? , the corresponding e-ram access is disabled. the higher bit (bit 15) is for e-ram indirect data register 0, and the lowest bit (bit 8) is for e-ram indirect data register 7. for example, programming a value of ? 01101011 ? will enable writes to e-rams 1, 2, 4, 6 and 7 only. see figure 2.8 for eram # reference description. read/write data enable bits in the e-ram indirect command register have a specific assignment for each device as determined by its cid #, it controls the c-word and/or d-word connected to that device regardless of the type of d-word programming. this field is independent of d-word type or depth, in other words if a read/write data enable bit is disabled, all corresponding read/write access associated with that e-ram will be disabled. this field is applicable for e-ram indirect operation only, oc sequencing controlled accesses are not qualified by this field. auto increment mode select if this bit is ? 0 ? , increment operation is performed on the e-ram address value only. if this bit is ? 1 ? , the level value is also incremented in addition to the e-ram address value. see level field description for further explanation. auto increment enable this bit is written with ? 1 ? when a block of data needs to be transferred to or from the e-ram. after the read or write operation, the e-ram indirect address register is automatically incremented to point to the next memory location (post increment). if this bit is ? 0 ? , the e-ram indirect address register is unchanged after a read or write operation to the e-ram memory. bit range size name value after reset 63:16 48 (reserved) undefined 15:8 8 read/write data enable 00h 7 1 (reserved) undefined 6 1 auto increment mode select 0 5 1 auto increment enable 0 4:2 3 trigger 000 1 1 (reserved) undefined 0 1 register set ready (ro) 1
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 95 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet trigger this field specifies which of the (up to) eight 32-bit data words will serve as the trigger for the PM2329 to perform the read or write operation to the e-ram. after the trigger word is written to or read from, the device performs read or write operation on the e-ram. these bits are programmed as follows: 000 e-ram indirect data register 0 or c-word bus 001 e-ram indirect data register 1 or d-word 0 bus 010 e-ram indirect data register 2 or d-word 1 bus 011 e-ram indirect data register 3 or d-word 2 bus 100 e-ram indirect data register 4 or d-word 3 bus 101 e-ram indirect data register 5 or d-word 4 bus 110 e-ram indirect data register 6 or d-word 5 bus 111 e-ram indirect data register 7 or d-word 6 bus register set ready this bit when ? 1 ? indicates that the e-ram indirect registers are currently not in use. it gets cleared when a read or write command is issued and remains ? 0 ? as long as the device is busy performing this operation. it is set again as soon as the device has executed the read or write operation to the e-ram. for correct operation, the processor must check that this bit is set before it writes to the eicr, eiar or eidr. when the rsr bit is 0, write cycles to any of these (ricr, riar or ridr) registers are ignored. this is a read-only bit and is set to ? 1 ? after reset.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 96 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.8 e-ram indirect address register (eiar; 8228h) access mode: read/write, global this register is used to specify the indirect read/write address of the e-ram location to be accessed. level in case the e-word is larger than the physical width of the e-ram, in one indirect read or write operation of the e-ram, the number of 32-bit words read or written will be determined by the e-ram width. the level field thus provides a means to access the other parts of the e-word. the level is programmed as 00 level 0 01 level 1 10 level 2 11 level 3 note that the results returned in the data fifo correspond to level 0 only. exception to this rule is in the case of a single e-ram device where both the ecd and edd buses are connected in parallel to the same memory device. in this case, d-word 0 (at level 1) will be returned in the data fifo. higher levels in all cases must be accessed by the processor using e-ram indirect addressing mechanism. see e-ram configuration register for more details. when the auto-increment mode select bit enables increment of the level field, the PM2329 will increment the level field depending on the depth of e-word in the e-ram. if depth is 1, level field is not incremented. if depth is 2 level field is incremented from 0 to 1 and then rolls over. if depth is 4, level field is incremented from 0 to 3 and then rolls over. if level is programmed to an invalid value, e.g., level 2 when depth is 2, it will count up to 3 and then roll over. e-word address the location of the e-word in the e-ram to be written or read. bit range size name value after reset 63:24 40 (reserved) undefined 23:22 2 level 00 21:17 5 (reserved) undefined 16:0 17 e-word address 0 0000h
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 97 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.9 e-ram configuration register (ecr; 8230h) access mode: read/write, global the bits in this register are used to configure the logical e-word. this register must be programmed before any e-ram accesses are performed. this register should not be updated when e-ram operations are in progress, normally this register will be written during initialization only. in cascade mode, global write will configure all the devices together. e-ram enable when this bit is reset to 0, all e-ram operations are disabled. no c-word will be supported in this case. when this bit is set to 1, e-ram operations are enabled. c-word is always assumed to be present in this case. d-words are defined using the d-word definition fields as explained below. d-word definition if e-ram is present, up to 7 d-words (depending on the physical width of the e-ram) can be configured. these 21 bits define the d-word type for these 7 d-words. the PM2329 also interprets this register to obtain the logical e-word width. three bits define each of the d-words as follows: 000 d-word absent 001 packet count 010 byte count 011 timestamp/state 100 user defined 101 (reserved) 110 (reserved) 111 (reserved) the user can force gaps in the d-words by programming them to be user defined. bit range size name value after reset 63:32 32 (reserved) undefined 31 1 e-ram enable 0 30:28 3 d-word #0 definition 000 27:25 3 d-word #1 definition 000 24:22 3 d-word #2 definition 000 21:19 3 d-word #3 definition 000 18:16 3 d-word #4 definition 000 15:13 3 d-word #5 definition 000 12:10 3 d-word #6 definition 000 9:3 7 (reserved) undefined 2:0 3 e-ram width 00h
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 98 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet the logical e-word width is determined by scanning the d-word definition bits from dw6 down to dw0, until it encounters the first d-word field that is non-zero, i.e., d-word that is not absent. the e- word width is c-word plus the number of d-words present. e-ram width indicates the physical width of attached e-ram. the PM2329 devices in cascade assume that the first 32 bits (i.e., c-word) are connected to PM2329 #0, next 32 bits are also on cid #0, next 32 bits on cid #1 and so on. this sequence must be maintained and gaps in the physical connection are not allowed. the bits are written as follows: 001 32-bit 010 64-bit 011 96-bit 100 128-bit 101 160-bit 110 192-bit 111 224-bit 000 256-bit note that the PM2329 cascade allows a larger e-word to reside in an e-ram whose physical width is smaller than the logical e-word. this will happen whenever the d-word definition field indicates a larger e-word than what the e-ram width field specifies. consequently, the number of locations accessed to access the entire e-word (e-word depth) varies. given the e-word width and e-ram width, the PM2329 automatically enforces a depth of 1, 2 or 4 as shown in the table below. ema[18:17] lines carry the eram depth field. for most efficient eram utilization, ema[18] and ema[17] signals should be connected to the e-ram devices depending on the depth of the e-word as shown in the table below. table 20 e-word depth chart e-word depth for e-word logical width & e-ram physical width combinations physical e-ram width (bits) logical e-word width (bits), c-word plus d-word 32 64 96 128 160 192 224 256 number of devices required 32 1 2 4 4 na na na na 1 64 1 1 2 4 4 na na na 1 96 1 1 1 2 2 4 4 4 2 128 1 1 1 1 2 2 2 4 3 160 1 1 1 1 1 2 2 2 4 192 1 1 1 1 1 1 2 2 5 224 1 1 1 1 1 1 1 2 6 256 1 1 1 1 1 1 1 1 7
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 99 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.10 interrupt enable register (ier; 8238h) access mode: read/write, global this register specifies the mask bits for the various conditions that can cause the PM2329 to assert an external interrupt. if a bit is set, an occurrence of the corresponding condition causes the interrupt signal to be asserted. the ocst status bit is always cleared on reading the stsr. the interrupt signal will continue to be asserted until either the interrupting condition is removed, or the corresponding enable bit in this register is reset. the bits in this register are defined below. enable result fifo full interrupt (rfof) if this bit is set, an interrupt is generated when a result fifo is full. enable oc sequence halted interrupt (ocsh) if this bit is set, an interrupt is generated when the oc sequence is halted due to a ? break ? or ? wait ? condition (see status register for definitions of these conditions). oc sequence halted (status register bit 5) will be set when this interrupt is asserted. enable idle interrupt (idle) if this bit is set, an interrupt is generated when all packet buffers are empty and all result fifos are empty. table 21 ema[18:17] usage depth ema[18] ema[17] 1nc nc 2 nc connected 4 connected connected bit range size name value after reset 63:8 56 (reserved) undefined 7 1 enable result fifo full interrupt (rfof) 0 6 1 (reserved) undefined 5 1 enable oc sequence halted interrupt (ocsh) 0 4 1 enable idle interrupt (idle) 0 3 1 enable packet buffer available interrupt (pba) 0 2 1 enable result available interrupt (rav) 0 1 1 enable oc sequence terminated interrupt (ocst) 0 0 1 interrupt enable 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 100 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet enable packet buffer available interrupt (pba) if this bit is set, an interrupt is generated when a packet buffer is available for receiving new packet data from the external processor. enable result available interrupt (rav) if this bit is set, an interrupt is generated when there is at least one result in the result fifo. enable oc sequence terminated interrupt (ocst) if this bit is set, an interrupt is generated when an entire sequence of ocs has terminated, i.e., processing for the current packet is over. upon completion of an oc sequence, the current packet is discarded by the PM2329. interrupt enable sint* is never asserted if this bit is set to ? 0 ? . when ? 1 ? , an interrupt is generated when an interrupting condition exists and the interrupt enable bit for that condition is set to ? 1 ? as shown below. 4.2.2.11 status register (stsr; 8240h) access mode: read only, global the status register provides common information regarding the state of the single or cascaded PM2329 devices. this is a global read register, only the primary PM2329 responds to the read request. the bits defined hold true for all devices in a cascade of PM2329 devices. in single channel mode when interrupts are not used, it is possible to process the status using either this register or the appropriate channel status register. in multi-chanel mode, this register provides summary status of all the channels. channel specific information can be retrieved by reading the channel status registers. when interrupts are used, this register should be read to clear the oc sequence terminated bit. bit range size name value after reset 63:8 56 (reserved) undefined 7 1 result fifo full 0 6 1 oc sequence halt condition undefined 5 1 oc sequence halted 0 41idle 1 3 1 packet buffer available 1 2 1 result available 0 1 1 oc sequence terminated 0 0 1 status valid 1
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 101 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet bit definitions for this register are as follows: result fifo full this bit is set when any one of the result fifos becomes full. if this condition is not serviced by the processor, the internal processing engine will eventually stall since any results that are generated can not be transferred to the result fifo. the oc processing halt state bit indicates the reason for the halt condition. oc sequence halt condition if the oc sequence halted bit (bit 5) is 0, then this bit is a don ? t care. if the oc sequence halted bit is 1, and this bit is 0, the PM2329 has reached a ? break ? condition--it has completed execution of the previous oc, and that previous oc was not the last oc in the specified sequence. if the oc sequence halted bit is 1, and this bit is 1, the PM2329 has reached a ? wait ? condition--it has completed execution of the previous oc, and that previous oc was the last oc in the specified sequence. oc sequence halted this bit is set when the PM2329 is halted awaiting a command from the network processor, and either: 1. oc trace enable bit is 0 and oc sequence mode bit is 1 (processor controlled oc sequencing), or 2. oc trace enable bit is 1 and oc sequence mode bit is 0 (automated oc sequencing with trace). the oc sequence halt condition bit (bit 6) indicates the reason for the halt condition. if the processor writes to the aoccr register, this bit is reset. idle this bit is set when all packet buffers are empty and all result fifos are empty. when this bit is set, the PM2329 is in idle condition and the PM2329 operating modes can be reprogrammed without losing coherency. this bit is cleared when any of the packet buffers is written to or at least one result is present in the result fifo. if the PM2329 operating modes are reprogrammed when this bit is clear, data or results can be lost. packet buffer available this bit when set indicates that the PM2329 is ready to receive another packet into one or more of the packet buffers. when the PM2329 is operating in multi-channel mode, this bit when set indicates that at least one of the packet buffers is available. the channel packet buffer available bit in the channel status registers can be used to determine channel(s) for which the packet buffer(s) are available. for further information about packet buffer available status, see the channel status register description. this bit is cleared when all the individual channel packet buffer available bits are clear.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 102 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet result available this bit is set when there is at least one result in the result fifo. when the PM2329 is operating in multi-channel mode, this bit when set indicates that at least one of the result fifos have results available. the channel result available bit in the channel status registers can be used to determine channel(s) for which the result(s) are available. this bit is cleared when all the individual channel result available bits are clear. oc sequence terminated this bit is set when the packet processing on the current packet is complete. this bit is cleared when this register is read. this also causes the oc sequence interrupt, if enabled, to be deasserted. status valid this bit is set to indicate the status registers has at least one status bit set. this bit is cleared when all other status bits in this register are clear. 4.2.2.12 operation control register (opcr; 8248h) access mode: read/write, global notes: a. this bit is set to ? 1 ? when the reset signal reset* is asserted, it is reset to ? 0 ? eight sclk cycles after reset signal is deasserted. this register controls the operation modes of the PM2329. this register should be written by the processor when it detects the PM2329 is idle (stsr[4]= 1) and prior to supplying the packet data to the device and it should not be updated by the processor until after the eop for the packet has been transferred to the device. the bits in this register are as follows: soft reset writing a 1 to this bit causes the chip to perform a soft reset internally. on reading the register, the bit indicates 1 if a soft reset or hard reset is in progress. the bit automatically resets to 0 eight sclk cycles when the internal reset operation is done. soft reset forces all the registers to their reset state and the packet buffer and result fifos are cleared. soft reset does not affect strap option pins, they are sampled on hard reset only. bit range size name value after reset 63 1 soft reset see note (a) 62 1 hard reset status (ro) see note (a) 61:4 58 (reserved) 000 0000 0000 0000h 3 1 enable multi-channel mode 1 2 1 enable pi field 1 11enable occ field 1 0 1 direction specifier 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 103 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet hard reset status this is a read-only bit. on reading the register, this bit is 1 if a hard reset is in progress. this occurs immediately after a hardware reset is applied by asserting the reset* signal. after the reset* pin is deasserted, the PM2329 will keep this bit set for eight sclk cycles until it has completed its internal initializations. the bit automatically resets to 0 when the internal reset operation is complete. the external software should check for this bit ? 0 ? before issuing any other accesses to the PM2329. enable multi channel mode writing ? 0 ? to this bit causes the PM2329 to act as a single channel device. the packet buffer is configured to work like a single fifo for multiple incoming packets. the results buffer is similarly also configured to work as a single fifo for storing the results of multiple packets. setting this bit to ? 1 ? causes the PM2329 to work as a multi-channel device, where multiple contexts on the external processor can control individual channels within the PM2329. enable pi field if this bit is ? 1 ? , the PM2329 interprets the first 64 bits that it receives as packet data, as the packet information (pi) field. if this bit is ? 0 ? the packet information is taken from the packet information register. the pi contains the packet attribute as well as fields which inform the fee in the PM2329 how the header is to be extracted. setting this bit to ? 0 ? saves one write cycle during packet transfer but causes all packet headers to be processed similarly. enable occ field if this bit is set to ? 1 ? , the PM2329 assumes that the occ is contained within the first 64-bits of packet data that it receives after the pi field (if present). if ? 0 ? then the oc conductor (occ) is taken from the occ register. the occ contains instructions for packet processing in terms of the sequence of ocs to be executed. setting this bit to ? 0 ? saves a write cycle during packet transfer but causes all packets to be processed in a like manner. direction specifier there are several mechanisms by which packet direction can be indicated to the PM2329. this bit specifies to the PM2329 what source it will use to determine the direction sense of the packet as per the table below. table 22 direction specifier bit directon specifier bit packet data from packet source (dma) packet data from processor comment 0 pi indicates direction (enable pi field = 1) pi indicates direction (enable pi field = 0) pi controlled direction 1 pspd pin indicates direction (sampled on the last word [eop] transferred) address of packet buffer input register which processor writes to indicates direction (sampled on the last word [eop] transferred) hardware controlled direction
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 104 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.13 channel assignment register (car; 8250h) access mode: read/write, global this register is only valid in the multi-channel mode (see operation control register). in multi-channel mode, the PM2329 can support up to 32 simultaneous channels. for this reason, the packet buffer is comprised of 32 segments, one dedicated to each channel 0 through 31. similarly, the results fifo is also split into 32 segments corresponding to 32 input channels. in this way up to 32 external contexts can use the 32 PM2329 channels simultaneously, in an interleaved manner, without conflict. see context support description in chapter 3 for further information. each packet buffer segment is 256 bytes long and is associated with a results fifo of 8 entries. if a larger packet buffer or a larger results fifo is required, the PM2329 allows multiple adjacent segments to be concatenated to generate a larger segment. packet buffer and result segments are both concatenated in this case. with concatenation, the total number of channels is reduced accordingly. segments can be concatenated by writing a ? 1 ? to the bit of this register associated with the first channel, and a ? 0 ? to all subsequent channels, to be concatenated. thus as an example, segments 5 through 8 can be concatenated by writing ? 1 ? to the assignment bit for channel 5, and writing ? 0 ? to the assignment bits for channels 6, 7, and 8. provided the bit for channel 9 is ? 1 ? , this will assign a 1 kb packet buffer and a 32 deep oc result fifo to channel 5. channels 6, 7 and 8 will now become unavailable. as explained in the example above, a set of (one or more) higher numbered channels can be concatenated with a lower numbered channel to create a bigger (lowest numbered) input channel (note that channel concatenation does not wrap around from channel 31 to channel 0, consequently channel 0 assignment bit[0] is ignored and tied high permanently). bit range size name value after reset 63:32 32 (reserved) undefined 31:0 32 channel [31:0] assignment ffff ffffh
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 105 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.14 oc conductor register (occr; 8258h) access mode: read/write, global this register contains the oc conductor to specify the ocs to be executed. the oc conductor can be supplied either using this register or as part of the packet stream (preceding the packet header). the format of the occ field, which comes in preceding the packet header, is same as the oc conductor (occ) register format. if the occ field is received from the packet source, the content of this register is not used and its content are not changed. if the occ field is not supplied with the packet, this register should be written by the processor prior to supplying the current packet and it should not be updated by the processor until after the eop for the associated packet has been transferred to the device. if trace oc execution enable or processor controlled oc sequencing enable bits are set, the intial oc processing starts using the content of this register or the occ field received from the packet source depending on the state of the enable occ field in the opcr register. once the wait condition is reached, further oc processing continues using the content of the alternate occ register supplied by the processor. the register can be read at any time by the processor to find out which occ is currently active. the occ register supports two formats to specify the ocs to be executed as shown below. it can contain: 1. a set of up to 4 oc identifiers ocids, or 2. the address of an e-ram location that contains a valid c-word. if bit [63] of the occ register is ? 0 ? then the occ register contains up to four oc identifiers (ocids). the first ocid is located at bits [62:48], the following ocids at bits [46:32], [30:16] and [14:0], respectively. the od identifier format is shown below. if bit [63] of the occ register is ? 1 ? then the occ register contains the address of the first c-word to be executed from the e-ram, occ [16:0] supply the address. bit range size name value after reset 63:0 64 oc conductor 0000 0000 0000 0000h table 23 oc conductor register format forma t bits 63:48 bit 47:32 bits 31:16 bits 15:0 00:ocid 1 [14:0] 0:ocid 2 [14:0] 0:ocid 3 [14:0] 0:ocid 4 [14:0] 1 1xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxe 16 e[15:0]
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 106 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet oc identifier format each ocid has 15-bits, these fields are defined as follows: bit [14] d-word present : if this bit if set to ? 1 ? , it indicates that d-words corresponding to this oc are present in the e-ram. if this oc results in a match condition, the d-words will be updated depending on the setting of the d-word update control field in the c-word. the c-word and d- word are fetched from the e-word corresponding to the matched cell. when performing occ controlled sequencing, fields other than the d-word update control field in the c-word are ignored. bits [13:8] oc descriptor index : this field specifies the index of the descriptor in the oc descriptor table which will be used for executing this oc. bits [7:0] cascade oc enable : this field specifies which of the eight PM2329 devices in the cascade will participate in the oc. when the enable bit is set, the corresponding device will execute the oc. if the enable bit is reset, the corresponding device will not execute the oc. bit 0 corresponds to PM2329 device 0, bit 7 corresponds to PM2329 device 7 in the cascade. if this field is set to 00h (i.e., all devices are disabled), it signals an invalid ocid and the current oc execution will be terminated and the following ocids, if any, will be ignored. bits [14:8] of the ocid in this case are not used and should be set to zeroes.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 107 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.15 packet information register (pir; 8260h) access mode: read/write, global this register contains fields (control information) that define how the packet header is to be extracted. additionally, this register also contains a 6-byte user defined packet attribute field. note that the control information used to extract values from the header can either come from the packet information register, or can be supplied as part of the packet stream. if this control information is supplied as part of the packet stream, this register is not used and remains unchanged. if the packet information is not supplied with the packet, this register should be written by the processor prior to supplying the current packet and it should not be updated by the processor until after the eop for the associated packet has been transferred to the device. direction bit this bit specifies the value of the direction bit associated with the packet. this bit is used only if the direction specifier bit in the operation control register is reset to ? 0 ? . l3 header extraction enable if this bit is ? 0 ? , then 108 bits from the first two 64-bit words of the packet data are taken and used in place of the extracted header. this allows the PM2329 to accept header information from pre-extracted packets. if this bit is ? 1 ? , then layer 3 header extraction is enabled, and the header extraction is carried out based on the setting of the ethernet framing enable and layer 4 extraction enable control bits, explained below. ethernet framing enable if this bit is ? 0 ? , then the layer 3 header offset field is used as supplied in this pi word. if this bit is ? 1 ? , then the PM2329 field extraction engine assumes that the packet is an ethernet frame starting at offset 0, and the layer 3 header offset is calculated. sip, dip and protocol fields are then extracted. layer 4 extraction enable if this bit is ? 0 ? , then the sp, dp and flag (syn, fin and ack) fields are loaded with the default values. bit range size name value after reset 63 1 direction bit 0 62 1 l3 header extraction enable 0 61 1 ethernet framing enable 0 60 1 layer 4 extraction enable 0 59 1 oc sequence control mode 0 58 1 oc trace enable 0 57:48 10 layer 3 header offset 00 0000 0000 47:0 48 user defined packet attribute 0000 0000 0000h
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 108 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet if this bit is ? 1 ? , then the PM2329 field extraction engine (fee) identifies whether the l4 header is tcp or udp. if it is tcp, then the fee extracts the sp, dp and flag (syn, fin and ack) fields. the rst bit in the tcp flags field is also extracted; however this bit is used for updating the tcp state d-word only. if the l4 heder is udp, the fee extracts the sp and dp fields only. the following pseudo-code shows the header extraction flow based on the setting of these three control bits. if (l3 header extraction enable [62] == 0) pre extracted header else ([62] == 1) if (ethernet framing enable [61] == 0) use supplied l3 offset to extract sip, dip and protocol if (l4 header extraction enable [60] == 1) and (protocol == tcp/udp) compute l4 offset and extract sp, dp and flags else load sp, dp and flags with default values endif else ([61] == 1) if (ethertype == ip 0x800) parse packet to determine l3 offset and extract sip, dip and prot carry out l4 extraction shown above else load sip, dip, protocol, sp, dp and flags with default values endif endif endif
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 109 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet if a field cannot be extracted due to an extraction error, or if the extraction was disabled, then the corresponding fields in the extracted header are loaded with the default values shown below: sip:0ffff ffffh dip:0000 0000h protocol: 0000h sp: 0000h dp: 0000h flags (syn fin and ack): 0 oc sequence mode this bit is a don ? t care if the oc trace enable bit is ? 1 ? . if the oc trace enable bit is ? 0 ? and this bit is ? 0 ? , oc sequencing is automatic and PM2329 terminates packet processing at the end of the oc sequence. if the oc trace enable bit is ? 0 ? and this bit is ? 1 ? , oc sequencing is under processor control. at the end of the current oc sequence specified in the occ word, the PM2329 retains the current packet and enters a wait condition. it permits the processor to control the next sequence of ocs to be executed. for further description of this bit, see oc sequencing description in chapter 5. oc trace enable when this bit is 1, the PM2329 executes an oc and enters a break condition (if the oc just executed was not the last oc in the sequence) or a wait condition (if the oc just executed was the last oc in the sequence). for further description of break and wait conditions, see the alternate occ register description. the table below shows the operation of the device based on the setting of the oc sequencing mode and oc trace enable bits. layer 3 header offset these 10 bits specify the start of the layer 3 header with respect to the start ofthe packet. this field is used only if auto l3 header extraction is enabled and the ethernet framing bit is ? 0 ? . table 24 processor controlled oc sequencing & trace oc execution oc trace enable oc sequence mode operation 0 0 automated oc sequencing operation (original pm2328 compatible operation) 0 1 processor controlled oc sequencing (wait after each oc sequence) 1 x trace oc sequencing--break after each oc execution and wait after each oc sequence
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 110 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet user defined packet attributes this field contains 6 bytes of user defined attributes. these can serve as one of the data sources for an oc (see oc descriptors). this is useful for running an initial lookup for the packet to determine which oc sequence to execute.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 111 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.16 timer register (tmr; 8268h) access mode: read/write, global the contents of this register are used to update the aging information or timestamp d-word in the e- ram. the timestamp field of this register is used to update the specific d-word defined as timestamp. the divider field of this register specifies the frequency at which the timestamp field should be updated. this frequency is derived by dividing the system clock (sclk) by a 15 bit prescaler and then by the divider field specified in this register. the register can be reprogrammed with a new divider or timestamp by writing to it. whenever this register is written, the internal prescaler is loaded with the newly written value. the timestamp field is incremented at the following frequency: ( f sclk /(2 15 -prescaler + 1) ) / divider as an example, if the sclk frequency is 66 mhz, the prescaler output period is 0.4915 msec. as an example, the table below shows the rate at which the timestamp will be incremented for some example settings of divider value assuming the prescaler was loaded with 0h. figure 27 shows an overview of the timer logic. bit range size name value after reset 63 1 (reserved) undefined 62:48 15 prescaler 0000h 47:44 4 (reserved) undefined 43:32 12 divider 000h 31:24 8 (reserved) undefined 23:0 24 timestamp 00 0000h table 25 timestamp increment interval example (sclk 66.67 mhz) divider timestamp increment interval unit 0 2.0133 sec 1 0.4915 ms 50 24.576 ms
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 112 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 27 timer logic prescaler (15 bits) up counter (15 bits) =7fffh divider (12 bits) down counter (12 bits) =1 up counter (24 bits) timestamp sclk reload reload decrement increment
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 113 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.17 alternate occ register (aocc; 8270h) access mode: read/write, global writes to this register are recognized by the device only if the current oc execution has reached halt state- -either a break or a wait condition--as a result of one of the following two control settings: 1. oc trace enable is set (trace on), or 2. oc trace enable is reset and oc sequence mode is set (processor controlled sequencing on). when a break condition (end of oc execution) occurs, the processor can either terminate sequence or continue sequence. when a wait condition (end of oc sequence) occurs, the processor can either terminate sequence or start new sequence. the processor writes to the aocc register to issue terminate sequence, continue sequence or start new sequence commands in the following manner. 1. to issue a terminate sequence command that terminates the current packet processing, the processor writes an epp (end of packet processing) word (0000 xxxx xxxx xxxxh) to this register. 2. to issue a continue sequence command that continues the execution of remaining ocs in the sequence, the processor can write any non-epp word to this register. 3. to issue a start new sequence command that starts executing a new occ sequence on the current packet, the processor can write a new occ word to this register. the format of this register is identical to the occ register format described earlier. note: to issue the continue sequence or start new sequence commands, the processor writes a non-epp word to the aocc. this word is interpreted as ? continue sequence ? if a break condition has occurred (that is, the oc just executed is not the the last oc of the programmed sequence). it is interpreted as ? start new sequence ? if a wait condition has occurred (that is, the oc just executed is the last oc of the programmed sequence). in the automated oc sequencing operations (trace oc enable is reset and oc sequence mode bit is reset), this register is ignored. bit range size name value after reset 63:0 64 oc conductor 0000 0000 0000 0000h
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 114 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet switching between sequencing types sequencing can switch from occ sequencing to e-ram sequencing or vice versa, when a new sequence is initiated following a halt condition. the processor writes to the aocc register to initiate a sequence, selecting the type of sequencing desired by choice of aocc bit 63, regardless of the previous state of bit 63. when the hardware is in the "wait" state (that is, after completing an oc sequence), the PM2329 interprets a processor write to the aocc as follows: if aocc[63] = ? 1 ? , the PM2329 initiates e-ram sequencing, jumping to the specified c-word address. if aocc[63] = ? 0 ? and aocc[55:48] = ? 00000000 ? , the PM2329 terminates sequencing. if aocc[63] = ? 0 ? and aocc[55:48] not= ? 00000000 ? , the PM2329 initiates occ sequencing as specified by the aocc[55:48] value. when the hardware is in the "break" state (that is, after any oc except the last one), the PM2329 interprets a processor write to the aocc as follows: if aocc[63] = ? 1 ? , the PM2329 continues the next oc. if aocc[63] = ? 0 ? and aocc[55:48] = ? 00000000 ? , the PM2329 terminates sequencing. if aocc[63] = ? 0 ? and aocc[55:48] not= ? 00000000 ? , the PM2329 continues with the next oc.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 115 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.18 packet buffer input register (pbir; base 3 +00h, +08h,... +0e8h, +0f0h) (pbir, eopd0; base 3 +0f8h) (pbir, eopd1; base 0 +08h) channel register access mode: write only, global the external processor or the packet source device (or dma source) writes to this register to transfer the packet data to the PM2329. data written to this register fills the corresponding packet input buffer. the PM2329 supports two mechanisms to load the packet input buffer. a fifo-like load mechanism similar to the pm2328, and an sram-like write mechanism to support dma capabilities of some network processors. while the packet input buffer itself is a fifo (in the data path between the system interface and the field extraction engine) that supports a single write port type addressing, the fifo address logic also supports an sram like addressing mechanism. the last transfer of the packet that indicates the end of packet and also packet direction information must always be done to one of two separate eop addresses. when utilizing sram like addressing mechanism, the last transfer address is arranged to indicate eop- direction 0 in an efficient manner. for each channel (as determined by the base address), multiple address offsets are assigned to this register. depending on the offset, direction and end-of-packet information are communicated to the PM2329. this offset assignment is as follows: all data for the packet must be written to the pbir address except the last write, which is written to the appropriate eop (eopd0 or eopd1) address. for the last packet data write, valid data must be left justified and the rest of the word padded by nulls. the tables below shows the writes to be performed to transfer 64-, 96- and 128-bit packets in 32- or 64-bit modes. this can be used as a guideline for other packet sizes. also, this table shows the write cycles register address (64-bit write) address (32-bit write) direction eop pbir base 3 +00h, +08h,..., +0e8h, +0f0h base 3 +00h, +04h, +08h,..., +0f0h, +0f4h xno pbir eopd0 base 3 +0f8h base 3 +0fch 0 yes pbir eopd1 base 0 +08h base 0 +0ch 1 yes
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 116 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet required assuming fifo addressing (all writes at the same address, except the eop word) is to be used. note: for 64-bit mode, the last 32 bits must be left justified (63:32) and the lower 32 bits (31:0) should be padded with zeroes. the next table shows the write cycles required when sram-like addressing is utilized. note that when using the sram like addressing to input the packet data (non eop words), the lower address bits (sa[7:3], or sa[7:2]) are don ? t care whereas the eop word address is fixed depending on the direction to be indicated (eop d0 is base 3 +0f8h; eop d1 is base 0 +08h [64 bit mode]). this allows the packet data to be input using a block memory transfer mechanism where the destination address increments. packet data to be transferred with direction set to 0 can be transferred efficiently using a single block transfer--depending on the number of words to be transferred, the transfer can be started at the appropriate starting offset such that the eop word gets the last packet word. for example, when operating in 64-bit mode, in order to transfer 256-bit packet (four 64-bit words) with direction set to 0, block transfer can be started at base 3 +0e0h with a transfer count of 4. the first three fifo addressing 64-bit 32-bit packet size direction0101 64 bits not eop none base 3 +00h eop base 3 +0f8h base 0 +08h base 3 +0fch base 0 +0ch 96 bits not eop base 3 +00h 2x (base 3 +00h) eop (note1) base 3 +0f8h base 0 +08h base 3 +0fch base 0 +0ch 128 bits not eop base 3 +00h 3x (base 3 +00h) eop base 3 +0f8h base 0 +08h base 3 +0fch base 0 +0ch sram addressing 64-bit 32-bit packet size direction0101 64 bits not eop none base 3 +any offset other than 0fch eop base 3 +0f8h base 0 +08h base 3 +0fch base 0 +0ch 96 bits not eop base 3 +any offset other than 0f8h base 3 +any offset other than 0fch eop (note1) base 3 +0f8h base 0 +08h base 3 +0fch base 0 +0ch 128 bits not eop base 3 +any offset other than 0f8h base 3 +any offset other than 0fch eop base 3 +0f8h base 0 +08h base 3 +0fch base 0 +0ch
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 117 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet words will be written to base 3 +0e0h, +0e8h and +0f0h and the eop word will be written to +0f8h, as required. in case the transfer direction is 1, block moves can still be used; however, the eop d1 must be written at a separate non-contiguous address using a separate write cycle. when channels are concatenated, the eop address of the concatenated channel is the eop address of the highest channel in the concatenated set. for example, if channels 0 through 3 are concatenated to form a 1k deep channel, address +000 through +3f0 act as non-eop addresses and +3f8 will be the eop d0 adderss. if automatic header extraction is disabled for this packet, then the first two 64-bit words (or first four 32-bit words) in the packet can contain pre-extracted header data for use with policies which inspect the packet header. if the pre-extracted header is to be compatible with the fee extracted header (so that the same classification rules may be applied to this packet), these words must be formatted as follows. the flags field is further defined as follows: the packet input buffer is organized as 32 segments of 256 bytes each. regardless of the state of enable multi-channel mode bit, packets are stored starting at segment boundaries. in the single channel mode, up to 32 packets of up to 256 bytes each can be transferred into the packet input buffer. note that if a packet exceeds 256 bytes, the next byte is placed in the next segment and the full 256-byte segment is also assigned to this packet. as an example, if the processor downloads a 264-byte packet, only 30 additional packets up to 256 bytes each can be input. in the multi-channel mode, up to 32 packets of 256 bytes each can be input. for further information regarding packet input in multi-channel mode, refer to the channel assignment register description. 1st word 63.............................................32 sip 31................................................0 dip 2nd word 63................48 sp 47.................32 dp 31.........24 protocol 23...20 flags 19...............0 (reserved) bit position flag 23 reserved; set to 0 a a. regardless of the source of the header information (pre-extracted or on- chip extraction), the dir bit is always derived as described in the direction specifier control bit description in operation control register and inserted into this bit position in the internal header holding register. 22 ack 21 syn 20 fin
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 118 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.19 channel status register (csr; base 0 +00h) channel register access mode: read only, global this register indicates the status of the corresponding channel. in single-channel mode, only csr0 is valid. since this is a channel register, each channel has a corresponding channel status register when the PM2329 is in the multi-channel mode. when channels are concatenated, the status for the concatenated channel are all available by reading the channel status register corresponding to the lowest numbered concatenated channel. reading a channel status register corresponding to an unassigned channel in the channel assignment register will return invalid value. channel result fifo full this bit is set when the result fifo of the corresponding channel becomes full. if this condition is not serviced by the processor, the internal processing engine will eventually stall since any results that are generated can not be transferred to the result fifo. channel oc sequence halted this bit is set when the PM2329 has completed the current oc processing for the corresponding channel and... 1. oc trace enable bit is 0 and oc sequence mode bit is 1 (processor controlled oc sequencing), or 2. oc trace enable bit is 1 and oc sequence mode bit is 0 (automated oc sequencing with trace) the oc sequnce halt state bit indicates the reason for the halt condition. channel oc sequence halt condition if the oc sequence halted bit is 0 then this bit is a don ? t care. if the oc sequence halted bit is 1 and this bit is 0, the PM2329 has reached a break condition for the corresponding channel--it has completed execution of the previous oc and this just completed oc was not the last oc in the specified sequence. bit range size name value after reset 63:8 56 (reserved) undefined 7 1 channel result fifo full 0 6 1 channel oc sequence halted 0 5 1 channel oc sequence halt condition undefined 4 1 (reserved) undefined 3 1 channel packet buffer available 1 2 1 channel result available 0 1 1 channel oc sequence terminated 0 0 1 (reserved) undefined
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 119 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet if the oc sequence halted bit is 1 and this bit is 1, the PM2329 has reached a wait condition for the corresponding channel--it has completed execution of the previous oc and this just completed oc was the last oc in the specified sequence. channel packet buffer available this bit is set to indicate that the corresponding packet buffer is empty. a packet buffer is empty as soon as the oc processing for that channel is complete. depending on the single- vs. multi-channel mode setting, the behavior of the pba bit is different as explained below. in single-channel mode, the pba bit is set as long as a 256 byte block is available in the packet buffer. this bit is cleared when the first packet data word is written to the last available 256 byte block in the packet buffer. in multi-channel mode, the pba bit is set as long as the 256 byte block corresponding to this channel is available. this bit is cleared when the first packet data word is written to the 256 byte block in the packet buffer. in multi channel mode with concatenation enabled, this bit (for the lowest numbered channel in the concatenated chain, all other concatenated channels in this chain are not used) behaves the same as the multi channel mode except the block size now refers to (n x 256) bytes where n is the number of channels concatenated together. channel result available this bit is set whenever one or more results are available in the corresponding results fifo. this bit is cleared when all of the results are read out by the processor. channel oc sequence terminated this bit is set whenever the packet processing is completed and all the results have been transferred into the results fifo corresponding to that channel. this bit is cleared when the channel status register is read by the processor or the eop for the corresponding channel is detected. the stsr contains summary status of all csrs. note that the oc sequence terminated bit in the stsr is set when any of the channel oc sequence terminated bit are set. each oc sequence terminated bit is cleared when the corresponding register is read. if in response to an interrupt generated due to the oc sequence terminated condition, the processor reads the stsr (thereby clearing the oc sequence terminated bit in the stsr) without reading the csrs (thus leaving the oc sequence terminated bit set in the csrs) and another oc sequence is terminated, the PM2329 will set the oc sequence terminated bit in the stsr.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 120 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.20 oc results fifo output reg (ocrf; base 1 +00h) channel register access mode: read only, global the results of packet processing are stored in the results fifo, which can be accessed by reading this register (read port). in 32-bit mode, the upper word (bits 63:32) of this register should be read first. regardless of the result of the processing (match, no match, invalid submission, etc.) at least one result is generated for each oc submitted. this is a channel register; each channel has a corresponding results fifo read port when the PM2329 is in the multi-channel mode. when channels are concatenated, the result segments are also concatenated. results for the concatenated channel will all be available by reading a single read port corresponding to the lowest numbered concatenated channel. reading a result fifo read port register corresponding to an bit range size name value after reset 63 1 oc match undefined 62 1 oc result valid 0 61 1 oc seq control mode undefined 60 1 packet first result undefined 59 1 packet last resut / sequence terminate undefined 58 1 oc done undefined 57 1 trace enable undefined 56 1 ocd single or multi-hit oc undefined 55:54 2 ocd oc type undefined 53:48 6 ocd index undefined 47:45 3 PM2329 id number undefined if oc type is ? pattern search oc ? : 44:32 13 pattern search match offset undefined if oc type is ? header oc ? : 44:36 9 (reserved) undefined 35:33 3 extraction error code undefined 32 1 ttl equal to 0 undefined 31:24 8 cascade oc enable undefined 23 1 oc match undefined 22 1 oc result valid 0 21 1 data result available undefined 20 1 match rule attribute undefined 19:17 3 (reserved) undefined 16:0 17 match cell number undefined
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 121 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet unassigned channel in the channel assignment register will return invalid value. every time the oc results fifo read port register is read, the oc results fifo advances and the next result is returned in the next read of the register. in case the pp performs 32-bit reads, it should read the higher word first and then the lower word since the fifo advances when the lower word (bits 31:0) is read. also see data result valid bit below regarding sequence of reads to the oc results fifo and data results fifo. in the single-channel mode, only channel 0 is valid. oc match this bit is set to ? 1 ? when an oc results in a match condition. other fields of the result word contain further information about the result. this bit is reset to ? 0 ? when no match was found. this function appears in both bit 63 and bit 23, for compatibility with some network processors and the original pm2328, while still facilitating easy access in 32-bit mode. oc result valid this bit is set to ? 1 ? for a valid result. all other bits in the result register are valid only if this bit is set. this bit is reset to ? 0 ? for an invalid result to indicate no result is available (other bits in this case are invalid). upon power-on reset, this bit is reset to 0. this function appears in both bit 62 and bit 22, for compatibility with some network processors and the original pm2328, while still facilitating easy access in 32-bit mode. oc sequence control mode this bit is interpreted only if trace enable (bit 57) is ? 0 ? . its description is as follows: if this bit is ? 0 ? it indicates automated oc sequencing (aos). the PM2329 performs oc sequencing without processor intervention. if this bit is ? 1 ? it indicates processor controlled oc sequencing (pcos). the PM2329 stops after completion of an oc sequence, and then waits for the processor to issue a command. the command could be to start another oc sequence or to end packet processing. note that in this mode, the PM2329 does not stop after every oc. packet first result if this bit is set, it indicates that this result is the first result of the first oc run on the packet. packet last result / sequence terminate if this bit is set, it specifies that the last result for a packet is in the fifo, and indicates termination of the oc sequence. oc done if this bit is set, it indicates that this result was the last result for the specified oc. every oc always generates at least one result and a single-hit oc generates only one result.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 122 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet trace enable if this bit is ? 1 ? then the PM2329 is in ? trace mode ? . it will stop after every oc and wait for the processor to issue a command. in this mode, oc sequence control mode (bit 61) is ignored. if this bit is ? 0 ? , the PM2329 mode is decided by oc sequence control mode (bit 61). ocd single or multi-hit oc this bit is valid only if the oc match bit is set. this bit is set to ? 1 ? if this was a multi-hit oc. it is reset to ? 0 ? if this was a single-hit oc. ocd oc type this bit is valid only if the oc match bit is set. this field has the same value as the oc-type field in the ocd which was used to run this oc. this field indicates a header, attribute, pattern search short or pattern search long oc. ocd index this bit is valid only if the oc match bit is set. this field contains the 6-bit index which gives the position of the descriptor within the ocd table. PM2329 id number this field is valid only if the oc match bit is set to ? 1 ? . these bits specify which of the PM2329 devices has generated this result. pattern search match offset this field is valid only if the oc was a short or long pattern search oc and the oc match bit is set to ? 1 ? . this field indicates the position at which a match occurred. the value returned is the absolute offset of the first byte for forward searches or last byte for reverse searches of the packet data which matched. extraction error code this field is valid only if the oc type was header. this field indicate the cause of extraction error. they are defined as follows. 000 no extraction error 001 incomplete header extraction due to offset error 010 intermediate ip fragment when l4 bit in pi was set 011 ihl field has a value less than 5 (20 bytes) 100 ip version is not 4 101 (reserved) 110 (reserved) 111 (reserved) this field returns 000 for attribute ocs.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 123 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet ttl equal to 0 this bit is valid only if the oc type was header. this bit is set to ? 1 ? to indicate that the time to live field within the ip header is ? 0 ? . this field is valid only if no extraction error occurred and it was not a pre-extracted header packet. cascade oc enable this field contains a copy of the cascade oc enable field from the occ of the packet corresponding to this result. data result available the condition when this bit is set are as follows: 1. occ controlled sequencing is selected, 2. d-word update enable was set for this oc, 3. ecr defined at least one d-word, and 4. the oc results in a match condition. or 1. e-ram controlled sequencing is selected, 2. d-word update enable was set for this oc, 3. ecr defined at least one d-word, 4. the oc results in a match condition, and 5. the specified branch opcode was not terminate. if this bit is set, then some e-ram data fields were either read or updated and are present in the data results fifo. the operation of the data results fifo is linked to the reading out of the oc results fifo. the data results, if required, should be read out before the next read access to the oc results fifo. match rule attribute this bit is valid only if the oc match bit is set. this bit is a copy of the attribute bit within the rule for the cell which matched. match cell number this field is valid only if the oc match bit is set to ? 1 ? . this field returns the 17-bit cell number of the rule within the partition that resulted in the match. this cell number corresponds to a relative cell number, i.e., the cell number within the oc partition across multiple PM2329 devices regardless of the physical partition fragmentation within a device or across multiple devices.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 124 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet for the following three conditions, the PM2329 will not execute an oc. 1. the oc descriptor is invalid. 2. the oc type is pattern search and the search range lies outside the packet. 3. the column select mask of the specified partition is 00h. under these conditions, the following result is generated: oc match = 0, oc done = 1 for the following three error conditions, the PM2329 cannot execute an oc, since it cannot identify a valid oc descriptor: 1. with occ sequencing, the cascade id mask for the first ocid is 00h. 2. occ specifies e-ram sequencing, but the ecr specifies no e-ram is present. 3. with e-ram sequencing, each c-word has the cascade id mask set to 00h and the last c-word spec- ifies the terminate condition. under the above three conditions, the result shown below is generated: oc match = 0 result valid = 1 data result = x packet first = 1 packet last = 1 oc done = 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 125 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.2.2.21 data results fifo output register (drfo 0/1; base 1 +08h ) (drfo 2/3; base 2 +08h) (drfo 4/5; base 2 +10h) (drfo 6; base 2 +18h) channel register access mode: read only, global in the extended mode of operation, the PM2329 supports external e-ram. besides control words, this e- ram array can also contain data words. these data words can contain information such as packet count, byte count, timestamp, tcp state or user defined results field. if a match is found while running an oc then a result is generated and placed in the oc results fifo. additionally, the PM2329 also accesses the data words in e-ram and updates them as needed. note that the PM2329 will update the d-words regardless of the depth level. however, see the note below regarding depth and d-words returned in the data results fifo. typically the processor might want information about the data words associated with the match result. to support this, the PM2329 contains a 32-bit data results fifo that is synchronized with the oc results fifo. for each oc results fifo entry which has the match bit set, the PM2329 will copy the information from the data word e-ram, corresponding to the matched cell location, into the data results fifo. this is only done by the PM2329 that is configured to connect to external data ram. this makes it possible for the processor to first get information about a match condition, and then to read data results fifo read port to get information such as packet count, byte count, timestamp, state and user defined results. this saves the processor explicit read requests to the e-ram to get the same information. providing user defined results also saves the processor translation time which it would otherwise spend in translating the cell number to final results. the information read from the data results fifo will always correspond to the last oc result read from the oc results fifo. the data results fifo is organized at 4 consecutive addresses so that a long e-word can be transferred easily out of the PM2329 for either 32- or 64-bit accesses. table 26 data results fifo output register (64-bit mode) bit range register name size responding device address 63:32, 31:0 data result fifo output register 0 (dw0 / dw1) 64 cid 0, cid 1 base 1 + 08h 63:32, 31:0 data result fifo output register 2 (dw2 / dw3) 64 cid 2, cid 3 base 2 + 08h 63:32, 31:0 data result fifo output register 4 (dw4 / dw5) 64 cid 4, cid 5 base 2 + 10h 63:32 data result fifo output register 6 (dw6) 32 cid 6 base 2 + 18h
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 126 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet note that the data results fifo returns values associated with depth level 0 only. words at other levels, if defined, must be accessed using e-ram indirect addressing mechanism. (the only exception is in case of a single device connected to a single external e-ram memory device with both ecd and edd buses connected to the same physical memory device. in this case, d-word 0 at the next sequential address is accessed and returned in the data results fifo.) 4.3 indirectly addressable locations this section describes indirectly addressable locations in the PM2329 and in the e-ram, which fall in one of the following two classes: rule memory cells e-words 4.3.1 rule memory cells indirect access using: rule indirect registers access mode: local rule memory cells are accessed by indirect addressing using the rule indirect address, command and data register set. the rule memory cells store the rule data and the rule control fields used when an oc is executed. the rule memory cells are 136 bits in size. the format of the rule memory cells is same as the rule indirect data register set. detailed rule operation is described in chapter 5. table 27 data results fifo ouput register (32-bit mode) register name size responding device address data result fifo output register 0 (dw0) 32 cid 0 base 1 + 08h data result fifo output register 1 (dw1) 32 cid 1 base 1 + 0ch data result fifo output register 2 (dw2) 32 cid 2 base 2 + 08h data result fifo output register 3 (dw3) 32 cid 3 base 2 + 0ch data result fifo output register 4 (dw4) 32 cid 4 base 2 + 10h data result fifo output register 5 (dw5) 32 cid 5 base 2 + 14h data result fifo output register 6 (dw6) 32 cid 6 base 2 + 18h
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 127 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.3.2 e-ram words indirect access using: e-ram indirect registers access mode: global e-ram is accessed by indirect addressing using the e-ram indirect address, command and data register set. a single location in the e-ram is referred to as an e-word. the e-word is made up of several 32-bit words, which are either a c-word or d-words. the size of the e-word depends on the number of PM2329 devices in the cascade (see e-ram indirect data register set). the format of the c-word is given below. this must be written to the upper half of the c-word/d-word register of the e-ram indirect data register set. control word d-word present if this bit is set to ? 1 ? , it indicates that d-words corresponding to this oc are present in the e-ram. if this oc ends in a match condition, the d-words will be updated depending on the setting of the d-word update control field. if this bit is reset to ? 0 ? , no d-word updates are performed based on the result of the current oc. note, when ocs are executed from e-ram, the d-word fields corresponding to the first c-words fetched (to determine the oc to be executed) are updated regardless of the state of this bit provided the updates are enabled using the update control bits in the c-word. oc descriptor index this field specifies the index of the descriptor in the oc descriptor table which will be used for executing this oc. cascade oc enable this field specifies which of the eight PM2329 devices in the cascade will participate in the oc. when the enable bit is set, the corresponding device will execute the oc. if the enable bit is reset, the corresponding device will not execute the oc. bit 16 corresponds to PM2329 device 0, bit 23 corresponds to PM2329 device 7 in the cascade. bit range size name value after reset 31 1 reseved undefined 30 1 d-word present undefined 29:24 6 oc descriptor index undefined 23:16 8 cascade oc enable undefined 15:12 4 d-word update control undefined 11:8 4 branch opcode undefined 7:0 8 immediate address undefined
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 128 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet if this field is set to 00h (i.e., all devices are disabled), it signals an invalid ocid and current oc execution will be skipped and based on the branch code in the current c-word, the next c-word will be fetched and processed. d-word update control this field specifies which of the d-word fields (if defined) need to be updated. the 4 bits are defined as follows. bit 15 update byte count bit 14 update packet count bit 13 update timestamp bit 12 update tcp state branch opcode this 4 bit field specifies the following opcodes. 0000 continue 0001 return return address is popped from an internal single-level stack. 0010 goto immediate 0011 call immediate return address is pushed into an internal single-level stack. 0100 goto immediate address on match, else continue 0101 call immediate address on match, else continue 0110 goto immediate address on match else terminate 0111 call immediate address on match, else terminate 1000 goto cell number address on match, else continue 1001 call cell number address on match, else continue 1010 goto cell number address on match, else terminate 1011 call cell number address on match, else terminate 1100 goto cell number address on match, else goto immediate 1101 call cell number address on match, else call immediate 1110 (reserved) 1111 terminate the cell number address is the relative address of the rule within the oc partition that generated the match. the address is used as the 17-bit (target) address in the e-ram. immediate address this is an 8-bit field which specifies one of 256 c-words to branch to using a goto or a call opcode. hence, the target for any immediate address must always lie within the first 256 locations of the e-ram c-words.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 129 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet byte count or packet count d-word timestamp and state d-word user defined data d-word byte count the d-word containing byte count is incremented by the byte count for the current packet. this is determined by the fee header extraction. the 32-bit value will wraparound unless it is cleared periodically by the processor. if the fee cannot determine the byte count field, it is assumed to be ? 0 ? . packet count the packet count is incremented by 1 every time this d-word is updated. the 32-bit value will wraparound unless it is cleared periodically by the processor. tcp state this d-word field is updated to reflect the current state of the packet. timestamp this d-word is updated with the current timestamp value from the timer register in the PM2329. user defined data this field can be set to any 32-bit value. it provides a lookup mechanism for oc matches. note: updates of byte count and tcp state fields are valid only if a prior oc using header has been executed. bit range size name value after reset 31:0 32 byte count or packet count undefined bit range size name value after reset 31:28 4 (reserved) undefined 27:24 4 tcp state undefined 23:0 24 timestamp undefined bit range size name value after reset 31:0 32 user defined data undefined
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 130 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 4.4 register summary 63 0 local configuration lcr (0000) 32 31 24 23 18 17 16 15 8 7 6 5 4 2 1 rsv rev rsv pll cmsk r s v z b t w i d cid rsv 63 6 rule indirect command ricr (0008) 13 12 8 1 0 54 2 7 rsv rwenb r s v r s r a i trg rsv rsv 32 31 63 rule indirect address riar (0010) 13 0 rsv cell rsv 32 31 14 63 0 rd0 rule [135:104] rd1 rule[103:72] 32 31 rule indirect data 0 ridr0 (0018) 63 0 rd2 rule [71:56] rsv 32 31 rule indirect data 2 ridr2 (0020) rd3 rule [55:40] 48 47 rd4 rule[39:32] 16 15 rd5 rule[31:24] 87 63 0 rsv rsv 32 31 rc rule [23:0] 56 55 rule indirect data 4 ridr4 (0028) r e s e n b 62
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 131 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 63 upper oc descriptor uocd (0400~07f0) 0 v a l pso 32 31 60 28 48 rsv 54 59 rows col 53 29 47 14 rsv 16 p s d 15 13 12 psc 62 typ 61 h i t rowe 63 lower oc descriptor locd (0408~07f8) 0 eofs 32 31 28 rsv rsv 29 13 rsv 16 15 12 pofs 63 0 dw3 dw4 32 31 e-ram indirect data 4 eidr4 (8210) 63 0 dw5 dw6 32 31 e-ram indirect data 6 eidr6 (8218) 63 0 cw dw0 32 31 e-ram indirect data 0 eidr0 (8200) 63 0 dw1 dw2 32 31 e-ram indirect data 2 eidr2 (8208)
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 132 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 63 6 e-ram indirect c ommand eicr (8220) 15 8 1 0 54 2 7 rsv rwenb r s v r s r a i trg r s v rsv 32 31 63 e-ram indirect address eiar (8228) 16 0 rsv eadr rsv 32 31 17 a i m 16 23 24 22 lvl rsv 63 e-ram configuration ecr (8230) 30 rsv eadr e n b 32 31 9 28 30 22 def0 def3 25 27 def1 def2 24 19 21 13 def6 16 18 def4 def5 15 10 12 ewid 2 63 interrupt enable ier (8238) 30 rsv e n b 32 31 2 o c s t i d l e p b a r a v rsv 1 4 63 status stsr (8240) 30 rsv s v 32 31 2 o c s t i d l e p b a r a v rsv 1 4 63 operation control opcr (8248) 30 rsv d i r 32 31 2 o c c m c m p i rsv 1 4 s r s t 62 h r s t 21 5 5 61 6 7 6 7 o c s h r s v r f o f o c s h c o n d r f o f
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 133 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 63 0 rsv 32 31 channel assignment car (8250) 63 0 ocid1 rsv 32 31 oc conductor occr (8258) 63 packet information pir (8260) 47 0 d i r l3o ual uah c t l 32 31 63 timer tmr (8268) 0 r s v stmp rsv 32 31 48 23 24 rsv 63 packet buffer input reg pbir (base 3 +00h, +08h, +10h, ..., +e8h,+f0h) pbir eopd0 (base 3 +f8h) pbir eopd1 (base 0 +08h) 0 data 32 31 63 channel status csr (base 0 +0) 30 data r s v 32 31 2 o c s t p b a r a v rsv 1 4 6 15 8 1 0 54 2 7 16 3 14 9 13 12 10 11 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 1 0 c 1 1 c 1 2 c 1 3 c 1 4 c 1 5 0 47 ocid2 0 48 1 ocid3 rsv 0 ocid4 0 eadr 15 16 17 62 46 14 30 l 3 e e f r l 4 e 62 61 60 58 59 57 pscl 48 62 47 44 43 div rsv c 1 6 c 1 7 c 1 8 c 1 9 c 2 0 c 2 1 c 2 2 c 2 3 c 2 4 c 2 5 c 2 6 c 2 7 c 2 8 c 2 9 c 3 0 c 3 1 t r 63 alternate occ aocc (8270) 0 aoccl 32 31 aocch
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 134 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet t r e n 6 3 0 dw0 dw1 3 2 3 1 data result fifo output drfo 0/1 (base 1 +08h) 6 3 0 dw2 dw3 3 2 3 1 6 3 0 dw4 dw5 3 2 3 1 drfo 4/5 (base 2 +10h) 6 3 0 dw6 (rsvd) 3 2 3 1 drfo 6 (base 2 +18h) drfo 2/3 (base 2 +8h) oc result fifo output ocrf (base 1 +0h) 2 1 0 ty p mcel 3 2 3 1 rsv cenb 2 3 m t c h v a l d a v 6 1 6 0 p k f 5 9 t r m d o n e 5 8 5 7 h i t 5 6 5 5 5 4 5 3 ocidx 4 8 4 7 pattern search: mofs 3 5 3 3 3 6 2 4 1 7 1 6 1 9 id 4 5 header: rsvd err 2 0 m r a d a v m t c h t t l v a l 2 2 4 4 6 3 6 2
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 135 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 5 rule formats and oc sequencing 5.1 rule formats the PM2329 can perform powerful policy-based search operations. these operations involve comparing the packet data fields with a pre-loaded set of policy rules in the policy database of the device. results of search operations are returned in the results fifo. additionally, based on the result of the operation, further operations can be performed on the same packet. PM2329 rules have been designed to handle a wide range of packet processing applications. key features of the rule format are listed below: supports multi-operand (up to 6) operations within an instruction eq, ge, or le (unsigned integers) operations bit-wise mask capability force match function rule attribute bit composite rules made of up to 4 rules rule negation function rule structure all PM2329 policy rules have a uniform structure, consisting of two parts: a rule control field (rc) and a rule data field (rd). the rule control field determines the operation to be performed on the packet data and policy contents of the rule data field. a policy rule is 136 bits wide, comprised of the 24-bit rule control field and the 112-bit rule data field. rule control and rule data fields are further divided into six sub-fields. this allows different operations to be performed on the rule data sub-fields, with the operations being specified by the corresponding sub- fields in the rule control sub-fields. figure 28 shows the organization of the 136-bit rule memory word. figure 28 rule control and data field rule 0 rd0 r d rd rd3 rd rd 23 31 39 103 55 71 135
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 136 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 5.1.0.1 rule data field the rule data field is 112 bits wide and is equal to the width of the PM2329 policy rules which are compared with the packet data field. these 112 bits are divided into sub-fields, each of which can be used independently of the others. there are a maximum of 6 sub-fields: two 32-bit fields (rd0 and rd1), two 16-bit fields (rd2 and rd3) and two 8-bit fields (rd4 and rd5). sub-fields rd2 and rd3 can be used separately as two 16-bit sub-fields, or they can be merged into a single 32-bit sub-field. by programming the rule control field appropriately, the individual rule data sub-fields can effectively be combined into wider fields to perform equal operation. some rule data sub-fields can act as mask fields for other rule data sub-fields. a rule data sub-field and the corresponding packet data sub-field are masked with the associated mask field (if enabled) and are then compared. this enables the PM2329 to implement power-of-2 (binary) range compare operations. further details about masking are provided in section 5.1.3. 5.1.0.2 rule control field the rule control field controls the selection of packet data fields, operations to be performed on the rule and packet data fields, and other actions related to the rule. each rule has a set of common control (cc) bits and field control (fc) bits associated with each rule data sub-field. since the rule data is divided into a number of sub-fields, the packet data must also be divided into a compatible set of sub-fields. the sub-fields are then compared with the corresponding rule data sub-fields. common control bits there are three common control (cc) bits used to specify global properties of the rule, or for indicating the action to be performed on a rule match. these bits are described in table 28: table 28 common control rule - ccr bits rule control bits no of bits description rule attribute 1 this bit is returned as part of the result and can be interpreted by the user as desired composite rule bit 1 specifies if the rule is part of a composite rule. up to 4 rules can be combined to form a composite rule. this bit cannot be used with a long pattern search oc and must be reset to ? 0 ? in that case. negation bit 1 this bit allows negation of the match result for the entire rule. in case the rule is part of a composite rule, result negation is applied for each rule, and then the results from all appropriate rules are combined.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 137 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet field control bits the field control (fc) bits corresponding to each rule data sub-field specify the following: opcode bits specify the operation on the corresponding data sub-field and the packet data. the packet data mux (pdm) selection bit specifies the association of fields in the packet data with the rule data sub-fields. the corresponding mask bits specify whether the mask field for this rule data sub-field should be applied. the merge bit (specific to rd2 and rd3 only) specifies that the two rule data sub-fields are to be combined into a wider 32-bit field. a brief overview of the rule control fields is presented below. for further details, contact switchon networks. figure 29 rule control fields common control rule bits ccr ra rule attribute bit comp composite rule bit neg rule negation bit field control rule bits fcr phm packet data mux bit opcode opcode bits mask enable bit for mask function merge used to merge rd2 and rd3 23 0 rule data sub-fields - rd0 through rd5 135 rule control rc fcr 0 (rd0) fcr 1 (rd1) fcr 2 (rd2) fcr 3 (rd3) fcr 4 (rd4) opcode phm merge 16 15 14 13 1211109876543210 20 opcode phm mask 19 18 17 opcod e ra comp 23 22 neg 21 opcod e opcode phm mask mask opcode phm mask common control rule bits fcr 5 (rd5)
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 138 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 5.1.1 rule operations the PM2329 supports different operations that can be performed on the rule data fields. the six rule data fields can be controlled separately to perform different operations on each of these fields. operations supported by the PM2329 are as follows: equal to (with or without masks) greater than or equal to (with or without masks) less than or equal to (with or without masks) match equal to, greater than or equal, and less than or equal operations compare the corresponding packet and rule data fields for the specified condition using unsigned integer arithmetic. the match operation is used to force a true result regardless of the input operands. each of the six rule data sub-fields supports operations as shown in the table below. using the above operations, it is possible for the PM2329 to perform the following operations: binary range compares non-binary range compares longest prefix (lp) matches pattern or string searches 5.1.2 masking comparison operations between rule and packet data fields can be qualified by bit mask fields. using bit masks, it is possible to store a "don ? t care" (as opposed to a ? 1 ? or a ? 0 ? ) in the PM2329 rule data bits, for comparison against packet data bits. both the rule data sub-fields and their associated mask bits are stored in the same PM2329 rule where some of the rule data sub-fields are used as the mask fields for the non-mask rule data sub-fields. this sub- field correspondence (data vs. mask) is fixed, as shown in table 30 below. this imposes some restrictions on the number of mask fields, but improves the memory efficiency of the PM2329 policy rule set. table 29 operations supported for rule data sub-fields operation rd0 rd1 rd2 rd3 rd4 rd5 match (00 or 0) yes yes yes yes yes yes eq (01 or 1) yes yes yes yes yes yes ge (10) yes yes yes yes -- le (11) yes yes yes yes --
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 139 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 30 masked sub-field and associated mask source in general, each rule data sub-field can be masked from the next rule data field. however, the following special cases should be noted. 1. the first rule data sub-field rd0 cannot act as the mask field for any other sub-field. 2. the upper 8 bits of rd3 cannot be masked using this mechanism; however, rd3 (all 16 bits) can be ignored using appropriate rule programming. 3. rd4 can never be masked; however, rd4 can be ignored using appropriate rule programming. 4. the last rule data sub-field, rd5, is divided into a 4-bit data and a 4-bit mask field. the 4-bit mask field cannot be used as a data sub-field. also note that while a sub-field has been enabled as a mask field, it is still used to generate the result as specified in the corresponding fcr sub-field. it is up to the user to program the rules and interpret the results appropriately. alternatively, if a field is used as a mask field, its corresponding opcode field could be set to match, to effectively ignore the result of the processing of the corresponding processing unit. 5.1.3 composite rules the PM2329 rule set supports creation of composite rules using the composite rule enable bit. composite rules combine up to 4 (or less) rules into one wide-policy rule. this composite rule would result in a compare condition, which is a combination of all the rules that constitute the composite rule. a composite rule set must lie within the same rule pack. note that the same packet data bits are compared against the composite rule. a composite rule generates a match only if all members of the composite rule match the packet data bits. this makes it possible for the PM2329 to impose highly complex policies on the packet data. for all other purposes, a composite rule behaves in the same way as any other single rule. the packet data bits are compared with each of the member rules, as specified by the individual rule control bits. the results of the individual compares are logically anded for generating the match result of the composite rule. in case of a long pattern search oc, the composite rule enable bit should be reset to ? 0 ? , since this oc uses multiple rules (16 total) by default. rule and packet data field (size) bits masked mask source rd0 (32 bits) all 32 bits rd1 (32 bits) rd1 (32 bits) all 32 bits rd2 (16 bits) & rd3 (16 bits) rd2 (16 bits) all 16 bits rd3 (16 bits) rd3 (16 bits) lower 8 bits only rd4 (8 bits) rd4 (8 bits) none none rd5 (8 bits) upper 4 bits lower 4 bits of rd5
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 140 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 5.1.4 rule attribute bit each PM2329 rule contains a rule attribute bit. this bit does not participate in rule processing operations; it is intended for use by the external processor. when a particular rule matches, the match result will contain the attribute bit taken from the rule that matched. this provides an additional degree of flexibility for the external processor software when handling match results. 5.1.5 rule negation the PM2329 performs operations between various data sub-fields of the rule and packet data as described earlier, and returns a combined result of this operation. the rule negation bit allows the returned result to be negated. for example, if this bit is set to ? 0 ? and an equality check is performed between rule and data sub-fields and the packet and rule data are equal, the result will indicate a match condition. however, if this bit is set to '1' for the same example, the result will indicate a ? no match ? condition. 5.2 operation cycles the operation cycle ( oc) is the basic classification operation performed by the PM2329 on the data extracted from a packet. it consists of comparing a string of extracted data against a set of rules and returning the relative offset of the rule that matched (single-hit oc), or a set of relative offsets of rules that matched (multi-hit oc). ocs specify the set of rules on which the oc will be executed (also called the rule partition) and the type of extracted packet data that will be classified (also known as the data source). the rule partition defines a subset of the policy database that will be used during the execution of an oc. the policy database is organized with a total of 16 columns and 64 rows. each column is further made up of 16 rule cells. a rule partition is defined by two sets of values: a) the set of columns containing the rules, and b) the set of rows containing the rules within the partition. for a given rule partition, individual columns (between 1 and 16, in any combination) can be specified. the rows of a rule partition must be defined with a start and end row (both inclusive). given this definition scheme, note that the columns of the partition need not be contiguous, whereas the rows within a column will always be contiguous. the minimum partition granulariy permitted by this scheme is 16 rule cells (a single row of a single column) and the maximum is the entire policy database rule memory in the device. the number of rule cells in a rule partition will always be a multiple of 16.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 141 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet the data source can be one of the following types: a) extracted packet header , which can contain the extracted ip and also tcp/udp fields, or alternatively can be pre-constructed by the external processor. b) packet attribute , which is the 48-bit field obtained from the packet information field. c) packet data , for pattern search ocs which can be taken from any starting byte offset within the packet. pattern search ocs could be applied to search for up to 12-byte (short) strings or up to 192-byte (long) strings. additionally, ocs can be specified to be single-hit or multi-hit ocs. when the oc is executed, it can either result in no matches, or yield one or more matches. in case one or more matches occur, a single-hit oc will return the only match or the highest priority match, whereas a multi-hit oc will return all the matches in the order of priority. 5.3 oc sequencing 5.3.1 oc conductor the PM2329 is capable of running different ocs on the same packet. the entire set of ocs that are applied to the same packet is called an oc sequence . the oc sequence is specified by the oc conductor (occ) word associated with each packet. the occ can be either specified one time in the occ register, or it can be supplied preceding each packet when the packet is written into the PM2329. the occ format can be one of two types: a) the occ contains up to 4 oc identifiers, or b) the occ contains the address of an e-ram location. format (a) results in occ controlled sequencing, where a fixed set of up to 4 ocs are executed on the corresponding packet. no conditional oc sequencing is possible, and the e-ram is not used for sequencing, since the sequence is fixed. however, d-word updates are supported and performed, if enabled. format (b) results in e-ram controlled sequencing, where the next oc to be executed is defined by a control word stored in the e-ram. the oc sequence can now be variable where the next oc depends on the result of the previous oc. d-word updates are perfomed, if enabled. the PM2329 contains a table of 64 oc descriptors. each entry in this table contains an oc descriptor that can specify up to 64 different types of ocs. additional information including the oc descriptor format is available in chapter 4.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 142 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 5.3.2 occ sequencing the PM2329 supports automated (pm2328 compatible) oc sequencing or processor controlled oc sequencing. additionally, the PM2329 can be programmed to trace oc execution for debug. various control bits, status bits, and registers determine the sequencing operation. they are summarized below: table 31 occ sequencing control bits location control bits in pi word oc sequence control mode oc trace enable in interrupt enable register oc processing halted enable table 32 occ sequencing status bits location status bits in status register oc processing halted oc processing halt condition table 33 registers applicable to occ sequencing registers action function occ determine ocs executed (ocid word or eram pointer) aocc determine ocs executed (ocid word or eram pointer) aocc write to: -- terminate -- continue -- start new sequence determines oc sequence executed in processor controlled mode or with trace enabled
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 143 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 5.3.2.1 trace feature oc trace enable can be set to debug the oc processing regardless of the oc sequencing employed (automated or processor controlled). with the oc trace enable bit set, the PM2329 will enter a halt state at the end of each oc execution. the status register will indicate the halted state and the halt condition (break or wait). the processor can examine the state of the device between oc execution by reading various registers, rule memory or eram memory locations. the oc execution can be terminated or continued, as explained below. note that processor intervention is required if the trace feature is enabled, regardless of the oc seqencing mode employed. when the PM2329 enters the halt condition (break or wait), the processor can use the aocc register to determine how the oc processing is to continue. the operations and conditions for their employ are listed below. 1. terminate sequence when a break or wait condition occurs, the processor can write an epp word to the aocc register. this terminates the current packet processing, and packet is discarded. 2. continue sequence when a break condition (end of oc execution) occurs, the processor can issue a continue sequence command by writing a non-epp word to the aocc register. this causes the PM2329 to continue processing the current packet with the next specified oc. 3. start new sequence when a wait condition (end of oc sequence) occurs, the processor can start new sequence by writing a non-epp, occ format-compatible word to the aocc register. figure 30 shows the halt state (break or wait) entered by the PM2329 as the oc execution proceeds with the trace feature enabled.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 144 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 30 trace feature 5.3.2.2 sequencing control modes oc sequence control mode bit determines if automated or processor controlled sequencing is enabled. 5.3.2.2.1 automated sequencing when the oc sequence control mode bit is reset and oc trace enable bit is reset, the PM2329 operates in automated sequencing (pm2328 compatible) mode. refer to the occ or eram sequencing description below for device operation. in this mode, after the specified sequence has been executed, the packet is discarded. occ sequencing occ ocd occ eram ocd eram sequencing wait wait aocc aocc note 1. when a break condition occurs, the processor can continue sequence or terminate sequence using the aocc register. note 2. when a wait condition occurs, the processor can start new sequence or terminate sequence using the aocc register brk brk brk brk
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 145 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 5.3.2.2.2 processor controlled sequencing when the oc sequence control mode bit is set and oc trace enable bit is reset, the PM2329 operates in processor controlled sequencing mode. in this case, the device will enter a halt state at the end of oc sequence, and set the halt status to indicate a wait condition. refer to figure 31 and the trace feature description above regarding the options available to the processor in this case (terminate sequence or start new sequence). in this mode, the packet is retained until the processor issues a terminate sequence command. figure 31 processor controlled sequencing when processor controlled sequencing is enabled, it is possible to switch between occ sequencing and eram sequencing by writing the appropriate control word to the aocc when the start new sequence command is issued. note 1. when a wait condition occurs, the processor can start new sequence or terminate sequence using the aocc register occ sequencing occ ocd occ eram ocd eram sequencing wait wait aocc aocc
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 146 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 5.3.2.3 occ sequencing if the occ contains an occ word containing oc identifiers (the structure of the occ word is as described for the occ register in chapter 4 along with the format of the oc identifiers) then occ sequencing is employed. oc execution starts when the eop for the packet is detected. the occ can specify up to 4 ocs. this allows up to 4 ocs to be run in a fixed sequence. packet processing terminates when an oc with the cascade oc enable field value set to 00 is encountered, or when the last (fourth) oc is executed. when operating in the cascaded mode, each oc identifier also identifies the set of devices in the cascade which will participate in the oc. the oc descriptor index across all devices in the cascade executing this oc must be identical. while eram sequencing using c-words (described in the next section) is not supported in this case, e- ram d-words can be updated, if enabled. in other words, all fields of the c-word except the d-word update control field are ignored, and d-words are updated as specified in the d-word update control field. figure 32 shows the sequence of events during oc execution when occ sequencing is performed.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 147 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 32 general overview of occ sequencing 5.3.2.4 e-ram sequencing if the occ does not contain oc identifiers, it must contain a pointer to an e-ram address that contains a valid c-word. in this case, an oc execution sequence is initiated with e-ram sequencing. in e-ram sequencing, each c-word contains an oc identifier, a d-word update control field and a branch condition. ocs to be occ register occ field from input packet or policy database eram oc descriptor from input data fifo etc. + + e word cell ofs match result fifo 1 3 2 4 6 5 7 0. eop detected 1. select ocid source 2. extract oc to be executed from oc 5. update result fifo 6. update d-words 7. transfer to data fifo eop detected 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 148 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet for every c-word executed, the following steps are performed by the PM2329 in the order shown: 1. update the d-words based on the d-word update control field 2. execute the oc specified by the oc identifier. 3. upon completion of the oc and based on its results, execute the branch condition. the branch conditions supported can be grouped into three categories, as follows: unconditional branches 1. terminate no further ocs are executed on the current packet. the current packet processing is terminated. 2. continue (with the next c-word) the next c-word is fetched from the next e-ram location and a new oc execution is started. 3. goto immediate address the next c-word is fetched from the specified address in the immediate address field and a new oc execution is started. 4. call immediate address the address of the current c-word is incremented and pushed onto a single-level stack. the next c- word is fetched from the specified address and a new oc execution is started. 5. return fetch the next c-word after popping the single location stack. 2-way conditional branches these are conditional branches. each opcode specifies an address to call or goto if a match occurs, and a default action in case of no match. 6. on match, goto immediate address else continue 7. on match, call immediate address else continue 8. on match, goto immediate address else terminate 9. on match, call immediate address else terminate
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 149 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet multi-way conditional branches these are conditional branches with more than two possible outcomes. if the oc results in a match, then the branch taken depends on the cell number that matched. this depends on the e-ram offset and the partition offset specified for the oc executed. each branch opcode also has a default action which is taken in case the oc does not result in a match. 10. on match goto cell number which matched, else continue 11. on match goto cell number which matched, else terminate 12. on match goto cell number which matched, else goto immediate 13. on match call cell number which matched, else continue 14. on match call cell number which matched, else terminate 15. on match call cell number which matched, else call immediate figure 33 shows the sequence of events during oc execution when eram sequencing is performed:
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 150 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 33 general overview of eram sequencing 5.3.3 e-word association with cells every oc (which requires e-ram) is mapped to a set of e-words. the mapping between a cell in an oc and the corresponding address in the e-ram is done as follows: each oc is assigned a block of e-words in the e-ram. generally, the number of e-words in this block would equal the number of cells in the oc (this is, however, not mandatory). an e-word segment start offset is programmed within each PM2329 to correspond to the start address of its e- word block. c-word address occ register occ field from input packet or policy database e-ram oc descriptor from input data fifo + + e word cell ofs match result fifo 1a 3 2 4 6 5 7 0. eop detected 1a. select c-word in e-ram 1b. update associated d-words 5. update result fifo 6. if result match and not terminate, update d-words 7. transfer to data fifo eop detected 0 1b
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 151 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet a partition start offset is further associated with each descriptor to specify the cell number offset of the oc partition within the entire oc. this is useful in cascade applications. for example, if an oc has 4k cells and has four partitions across four PM2329 devices where each partition is 1k cells in length, then the partition offsets within the four PM2329 devices should be programmed to be 0, 1k, 2k and 3k respectively. in a single PM2329 configuration, this field will be normally programmed to 0. when a match occurs, the location of the e-word to be fetched is calculated by adding the e-word segment start offset, the partition start offset, and the relative offset of the matching cell within that partition. this computation is performed for a multi-way branch condition only. in case of a two way or unconditional branch, the e-word address to be fetched is not dependent on the cell number.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 152 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 6 electrical and timing characteristics general notes: 1. all parameters are characterized for dc conditions after thermal equilibrium has been established. 2. unused inputs must always be tied to appropriate logic level (either v ss or v dd ). 3. the input pin contains circuitry to protect the inputs against damage due to high static voltages or electric fields; how- ever, it is advised that normal precautions be taken to avoid applying any voltage higher than the maximum rated voltages. for proper operation it is recommended that v in be constrained to the range v ss < v in < v dd . 4. the device requires two digital power supplies: v dd = 3.3v and cv dd = 1.5v or 1.6v , and one analog power supply: av dd = cv dd . 5. correct association between the sclk frequency and the cv dd supply voltage must be followed. table 34 absolute maximum a ratings a. maximum ratings are those values beyond which damage to the device may occur. item parameter symbol conditions value unit 1 power supply voltage (i/o) v dd vss=0, cvss=0, avss=0, -0.5 to 4.0 v 2 power supply voltage (core) cv dd -0.5 to 2.5 v 3 input voltage v in -0.5 to v dd +0.5 v 4 short circuit output current i 0 + 20 ma 5 electro-static discharge voltage v esd + 1000 v 6 latch-up current i lu + 100 ma 7 junction temperature t jmax 125 c 8 storage temperature t stg -40 to 150 c table 35 recommended operating conditions item parameter symbol conditions min. typ. max unit 1 power supply voltage (i/o) v dd v ss =0v 3.14 3.3 3.46 v 2 power supply voltage (core) cv dd cv ss =0v (see note a ) a.the required core power supply voltage when running at sclk = 100mhz or below 1.44 1.5 1.56 v cv ss =0v (see note b ) b.the required core power supply voltage when running at sclk = 116mhz 1.54 1.6 1.66 v 3 analog power supply voltage av dd av ss =0v (see note c ) c.the required analog power supply when using core power supply voltage of 1.5v (nominal) 1.44 1.5 1.56 v av ss =0v (see note d ) d.the required analog power supply when using core power supply voltage of 1.6v (nominal) 1.54 1.6 1.66 v 4 ambient temperature t a 02570 c table 36 terminal capacitance item parameter symbol conditions min. typ max unit 1 input c i measured at v dd =v in =v out =v ss f=1mhz t a =25 c -5-pf 2output c o -5-pf 3 bidirectional c io -5-pf
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 153 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 6.1 dc characteristics general note: 1. all dc parameters are guaranteed across recommended operating conditions. table 37 dc characteristics item parameter symbol conditions min. max unit 1 high-level input voltage v ih ttl input 2.0 v 2 low-level input voltage v il ttl input 0.8 v 3 input leakage current (for input-only pins without pull- up resistor) i ih v in =v dd 10 a i il v in =v ss 10 a 4 input leakage current (for bi-directional pins with pull- up resistor) i upih v in =v dd 15 a i upil v in =v ss 20 100 a 5 high-level output voltage v oh i oh = -400ua 2.4 v 6 low-level output voltage v ol i ol = 4ma 0.4 v 7 output leakage current tri- state output (for output-only pins without pull- up resistor) i ozh v out = v dd 15 a i ozl v out = v ss 15 a 8 max current at v dd power supply i ddop sclk = 100mhz, sd, edd load = 15pf ema, ecd load = 20pf see note a a.the maximum current at v dd power supply (i ddop ) is based on worst case simulation data. the following specification applies, max = 0.5a (condition: sclk = 100mhz). a sclk = 116mhz, sd, edd load = 15pf ema, ecd load = 20pf see note b b.the maximum current at v dd power supply (i ddop ) is based on worst case simulation data. the following specification applies, max = 0.6a (condition: sclk = 116mhz) a 9 max current at cv dd power supply ci ddop cv dd = 1.5v + 4%, sclk = 100mhz, aclk = 200mhz 2.0 a cv dd = 1.6v + 4%, sclk = 116mhz, aclk = 232mhz 2.5 a
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 154 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 6.2 switching characteristics 6.2.1 reset timing parameters 6.2.1.1 vdd power on sequence v dd can be applied concurrently with, or prior to c v dd . the recommended sequence is to apply v dd prior to c v dd and av dd . the recommended power-on sequence is illustrated in figure 34. figure 34 recommended v dd power on sequence table 38 reset timing item parameter symbol conditions min. max unit 1v dd rise time tr vdd 1ms 2cv dd rise time tr cvdd 1ms 3av dd rise time tr avdd 1ms 4 reset low time trst after v dd and cv dd are stable a a.the minimum reset low time should be the larger of the two given values. 10 ms 100 valid sclk cycles reset* sclk cvdd/ 10ms min 100 clocks min. .96cvdd vdd .95vdd 10 ms min avdd
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 155 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 6.2.2 clock timing parameters general notes: 1. the specified input clock swing of 10% to 90% refers to percentages of nominal rail-to-rail supply voltage (0v to 3.3v). 2. equivalent slew rates are 5.28 v/ns (max) and 1.76 v/ns (min). 3. sclk duty cycle must ensure that the specified high and low times are met. 4. correct association between the sclk frequency and the cv dd supply voltage must be followed. figure 35 sclk to eclkout skew table 39 clock timing item parameter symbol conditions min. max unit 1 sclk period tsck cv dd = 1.5v + 4% 10.0 100.0 ns cv dd = 1.6v + 4% 8.6 100.0 ns 2 sclk rise time trsck 10% to 90% see note a a.the sclk rise time is based on simulation data. the following specification applies, min = 0.5ns, max = 1.5ns. see note a ns 3 sclk fall time tfsck 10% to 90% see note b b.the sclk fall time is based on simulation data. the following specification applies, min = 0.5ns, max = 1.5ns. see note b ns 4 sclk high time thsck cv dd = 1.5v + 4% 4.0 ns cv dd = 1.6v + 4% 3.6 ns 5 sclk low time tlsck cv dd = 1.5v + 4% 4.0 ns cv dd = 1.6v + 4% 3.6 ns 6 sclk to eclkout skew tskew -0.5 1.0 ns tsck trsck tfsck thsck tlsck tskew tskew sclk eclkout
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 156 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 6.2.3 system interface timing figure 36 system interface timing parameters sclk sce0*/sce1* soe* srw* swhe* swle* sa[15:3] sd[63:0] wd sa rd tas tah twds twdh trdh1 trdz1 trdv2 trdlz2 trdlz1 trdv1 tces tceh twls twes tweh twhh twlh trdz2 this diagram shows timing relationships with respect to sclk. for functional timing, see chapter 2 pscc pseop pspd pspba schstb schnum tpsccs tpscch tpseops tpseoph tpspds tpspdh twhs sce2 tstbv tstbh tsnumv tsnumh tpbav tpbah common to write or read write read
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 157 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 40 system interface timing parameters item parameter symbol conditions min. max unit 1 sa setup time tas 2.00 ns 2 sa hold time tah 0.50 ns 3 sclk to sd lo-z (read) trdlz1 1.50 ns 4 sclk to sd valid (read) trdv1 sclk = 100mhz, cv dd = 1.5v + 4% 5.00 ns sclk = 116mhz, cv dd = 1.6v + 4% 4.50 ns 5 sclk to sd invalid (read) trdh1 1.15 ns 6 sclk to hi-z (read) trdz1 5.00 ns 7 soe* to lo-z (read) trdlz2 1.20 ns 8 soe* to data valid trdv2 5.00 ns 9 soe* to hi-z (read) trdz2 4.50 ns 10 sce0*, sce1*, sce2 setup time tces 2.00 ns 11 sce0*, sce1*, sce2 hold time tceh 0.50 ns 12 sd setup time (write) twds 2.00 ns 13 sd hold time (write) twdh sclk = 100mhz, cv dd = 1.5v + 4% 1.00 ns sclk = 116mhz, cv dd = 1.6v + 4% 0.90 ns 14 srw* setup time (write) twes 2.00 ns 15 srw* hold time (write) tweh 0.50 ns 16 swhe* setup time (write) twhs 2.00 ns 17 swhe* hold time (write) twhh 0.50 ns 18 swle* setup time (write) twls 2.00 ns 19 swle* hold time (write) twlh 0.50 ns 20 sint* valid tsintv 5.00 ns 21 sint* invalid tsinth 1.50 ns 22 schstb valid tstbv 5.00 ns 23 schstb invalid tstbh 1.50 ns 24 schnum valid tsnumv 5.00 ns 25 schnum invalid tsnumh 1.50 ns 26 pscc setup time tpsccs 2.00 ns 27 pscc hold time tpscch 0.60 ns 28 pseop setup time tpseops 2.00 ns 29 pseop hold time tpseoph 0.50 ns 30 pspd setup time tpspds 2.00 ns 31 pspd hold time tpspdh 0.50 ns 32 pspba valid tpbav 5.00 ns 33 pspba invalid tpbah 1.50 ns
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 158 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet general notes: 1. depending on the clock to output delay of other devices on the system bus and the bus protocol characteristics (back- to-back read and write cycles), bus contention may occur. 2. the output load used in the timing measurement is shown in figure 37. 3. correct association between the sclk frequency and the cv dd supply voltage must be followed. figure 37 load equivalents 3.3v i/o output load equivalents z o =50 ? ? 50 q v t =1.5v load figure a (tester) q +3.3v 317 351 15pf load figure b (simulation) ? ?
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 159 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 6.2.4 e-ram interface timing figure 38 e-ram interface timing ema[16:0] emce* emoe* sclk ecwe*/ edwe* addr temav temcev temah twdhz ecd[31:0]/ edd[31:0] write wd twdlz twdv twdhv tedwev/ tecwev read rd temoev trds trdh common to write or read tedweh/ tecweh this diagram shows timing relationships with respect to sclk. for functional timing, see chapter 2 temceh temoeh
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 160 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet general note: 1. the eram interface timing parameters are specified with reference to sclk. 2. correct eram device should be chosen according to clock speed. 6.2.5 cascade interface timing figure 39 cascade interface timing table 41 e-ram interface timing parameters item parameter symbol conditions min. max unit 1 sclk to ema valid temav max c l =20pf 5.0 ns 2 sclk to ema invalid temah max c l =20pf 1.5 3 sclk to emoe* valid temoev max c l =20pf 5.0 ns 4 sclk to emoe* invalid temoeh max c l =20pf 1.5 ns 5 sclk to emce* valid temcev max c l =20pf 5.0 ns 6 sclk to emce* invalid temceh max c l =20pf 1.5 ns 7 sclk to edwe*/ ecwe* valid tedwev/ tecwev max c l =15pf 5.0 ns 8 sclk to edwe*/ ecwe* invalid tedweh/ tecweh max c l =15pf 1.5 ns 9 sclk to ecd/edd low-z twdlz c l (see note a ) a. the shown data bus timing parameters are based on ecd load of 20 pf and edd load of 15 pf. 1.5 ns 10 sclk to ecd/edd valid twdv c l (see note a )5.0ns 11 sclk to ecd/edd invalid twdhv c l (see note a )1.0 ns 12 sclk to ecd/edd hi-z twdhz c l (see note a )5.5ns 13 edd/ecd setup time trds c l (see note a )2.0 ns 14 edd/ecd hold time trdh c l (see note a )0.5 ns sclk cocdin cocdout cocm* input output tcocs tcoch tcoms tcomh tdoutv tcomv
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 161 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet general note: 1. the cascade interface timing parameters are specified with reference to sclk. 2. number of devices in cascade is limited by the sclk frequency as follows: 116mhz : 1 device, 100mhz : 2 devices, 77mhz: 3 devices, 66mhz : 4 devices, 50mhz : 8 devices. note that the number of devices in cascade is also determined by the capacitive loading due to board layout and the presence of other devices on the system bus. 6.2.6 jtag interface timing figure 40 jtag interface timing table 42 cascade interface timing parameters item parameter symbol conditions min. max unit 1 cocs (input mode) setup time tcocss 1.2 ns 2 cocs (input mode) hold time tcocsh 0.5 ns 3 sclk to cocs (output mode) valid tcocsv 7.8 ns 4 cocdin[n] setup time tcocds 3.0 ns 5 cocdin[n] hold time tcocdh 0.5 ns 6 sclk to cocdout valid tcocdv 5.0 ns 7 cocm* (input mode) setup time tcocms 1.5 ns 8 cocm* (input mode) hold time tcocmh 0.5 ns 9 sclk to cocm* (output mode) valid tcocmv 8.0 ns 10 cemrq (input mode) setup time tcems 1.8 ns 11 cemrq (input mode) hold time tcemh 0.5 ns 12 sclk to cemrq (output mode) valid tcemv 7.7 ns ts jtm s th jtm s jtm s jtc k ts jtdi th jtdi jtdi tv jtdo jtd o jtc k jtrst tp jtrst
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 162 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet figure 41 jtag idcode register table 43 jtag interface timing parameters item parameter symbol conditions min typ max unit 1 jtck frequency 10 mhz 2 jtck duty cycle 40 60 % 3 jtms set-up time to jtck ts jtms 4.0 ns 4 jtms hold time to jtck th jtms 1.0 ns 5 jtdi set-up time to jtck ts jtdi 4.0 ns 6 jtdi hold time to jtck th jtdi 1.0 ns 7 jtck to jtdo valid tv jtdo 2.0 10.0 ns 8 jtrst pulse width tp jtrst 200.0 ns version part number manufacturer identity 1 4 bits 16 bits 11 bits 31 28 27 12 11 1 0 msb lsb version 0h part number 0040h manufacturer identity 038h
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 163 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 7 package details 7.1 package type, characteristics and mechanical drawing 7.1.1 package type 352 pin tebga package, 35x35 mm (1.378 ? x 1.378 ? ) 7.1.2 thermal characteristics figure 42 device compact model junction bottom (board) top (case) jt jb
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 164 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet table 44 thermal characteristics item parameter symbol conditions a a. specified parameter values vary depending on the given device operation conditions. value unit 1 junction to ambient thermal resistance (theta ja) ja sclk = 100mhz, aclk = 200mhz, v dd = 3.3v+5%, cv dd = 1.5v+4% natural convection 12.50 c/w airflow = 1 m/s (200 lfpm) 10.00 c/w airflow = 2 m/s (400 lfpm) 7.80 c/w sclk = 116mhz, aclk = 232mhz, v dd = 3.3v+5%, cv dd = 1.6v+4% natural convection 12.20 c/w airflow = 1 m/s (200 lfpm) 9.50 c/w airflow = 2 m/s (400 lfpm) 7.70 c/w 2 junction to top thermal resistance (theta jt) jt 0.43 c/w 3 junction to bottom thermal resistance (theta jb) jb sclk = 100mhz, aclk = 200mhz, v dd = 3.3v+5%, cv dd = 1.5v+4% 9.00 c/w sclk = 116mhz, aclk = 232mhz, v dd = 3.3v+5%, cv dd = 1.6v+4% 7.20 c/w 4 maximum operating power dissipation p op-max sclk = 100mhz, aclk = 200mhz, v dd = 3.3v+5%, cv dd = 1.5v+4% sd, edd load = 15pf ema, ecd load = 20pf (see note b ) b. the shown maximum operating power dissipation is based on simulated data. 4.0 w sclk = 116mhz, aclk = 232mhz, v dd = 3.3v+5%, cv dd = 1.6v+4% sd, edd load = 15pf ema, ecd load = 20pf (see note b ) 5.5 w 5 maximum long-term operating junction temperature t j-op (see note c ) c. the maximum long-term operating junction temperature is to ensure adequate long-term life. the absolute maximum junction temperature of 125 c is for short-term excursions with guaranteed continued functional performance. short-term is understood as the definition stated in bellcore generic requirements gr-63-core. 105 c
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:39:44 pm proprietary and confidential to pmc-sierra, inc and for its customers ? internal use 165 document id: pmc-2010146, issue 4 PM2329 classipi network classification processor datasheet 7.1.3 package mechanical drawing figure 43 package mechanical drawing

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