? semiconductor components industries, llc, 2003 may, 2003 - rev. 7 1 publication order number: nbsg111/d nbsg111 2.5v/3.3vsige differential 1:10 clock/data driver with rsecl* outputs *reduced swing ecl the nbsg111 is a 1-to-10 differential clock/data driver. the device is functionally equivalent to the lvep111 device with much higher bandwidth and lower emi capabilities. inputs incorporate internal 50 termination resistors (input to vt pad) and accept necl (negative ecl), pecl (positive ecl), lvttl, lvcmos, cml, or lvds. outputs are rsecl (reduced swing ecl), 400 mv. the q[0:9] / q[0:9] outputs have a differential synchronous enable (en/en ) pin. the synchronous enable pin is used to avoid a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. the internal flip flop is clocked on the falling edge of selected clock (clk0/clk0 or clk1/clk1 ), therefore all associated specification limits are referenced to the negative edge of the selected clock input. the v bb and v mm pins are internally generated voltage supplies available to this device only. the v bb is used for single-ended necl or pecl inputs and the v mm pin is used for lvcmos inputs. for single- ended input operation, the unused differential input is connected to v bb or v mm as a switching reference voltage. v bb or v mm may also rebias ac coupled inputs. when used, decouple v bb and v mm via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb and v mm outputs should be left open. ? maximum input clock frequency > 6 ghz typical ? maximum input data rate > 6 gb/s typical ? 300 ps typical propagation delay ? 60 ps typical rise and fall times ? rspecl output with operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? rsnecl output with rsnecl or necl inputs with operating range: v cc = 0 v with v ee = -2.375 v to -3.465 v ? rsecl output level (400 mv peak-to-peak output), differential output ? 50 internal input termination resistors ? compatible with existing 2.5 v/3.3 v lvep and ep devices ? v bb and v mm reference voltage output sg111 = device code l = wafer lot y = year w = work week *for further details, refer to application note and8002/d fcbga-49 ba suffix case 489a marking diagram* sg 111 device package shipping ordering information nbsg111ba 8x8 mm fcbga-49 100 units/tray nbsg111bar2 8x8 mm fcbga-49 500/tape & reel lyw board description nbsg111baevb nbsg111ba evaluation board http://onsemi.com
nbsg111 http://onsemi.com 2 vcc nc q7 figure 1. bga-49 pinout (top view) v ee q0 q0 v ee q1 en v mm q9 q9 q8 clk1 vtclk1 vten v cc vtclk1 clk1 a b c d 123 4 q8 q7 v ee 567 vtsel sel q6 vtsel sel q6 q1 q2 v ee q2 nc en vten v cc q3 vtclk0 q3 clk0 clk0 vtclk0 q4 v bb v ee q4 q5 q5 v ee e f g
nbsg111 http://onsemi.com 3 table 1. pin description pin name i/o description a1,a7,g1,g7,c2,e6 v ee - negative supply voltage. all v ee pins must be externally con- nected to power supply to guarantee proper operation. f3,d4,b5 v cc - positive supply voltage. all v cc pins must be externally connected to power supply to guarantee proper operation. b2 v mm - lvcmos reference voltage output (v cc - v ee ) / 2. f6 v bb - ecl reference voltage output e4 vtclk0 - internal 50 termination pin for clk0. see table 4. (note 1) f4 clk0 ecl, cml, lvcmos, lvds, lvttl input noninverted differential input clk0. internal 75 k to v ee . e5 vtclk0 - internal 50 termination pin for clk0 . see table 4. (note 1) f5 clk0 ecl, cml, lvcmos, lvds, lvttl input inverted differential input clk0 . internal 75 k to v ee and 36.5 k to v cc . c4 vtclk1 - internal 50 termination pin 1. see table 4. (note 1) b4 clk1 ecl, cml, lvcmos, lvds, lvttl input noninverted differential input clk1. internal 75 k to v ee . c3 vtclk1 - internal 50 termination pin for clk1 . see table 4. (note 1) b3 clk1 ecl, cml, lvcmos, lvds, lvttl input inverted differential input clk1 . internal 75 k to v ee and 36.5 k to v cc . b1,d1,f1,g3,g5,f7, d7,b7,a5,a3 q[0:9] rsecl output noninverted differential outputs [0:9]. typically terminated with 50 to v tt = v cc - 1.5 v c1,e1,g2,g4,g6,e7, c7,a6,a4,a2 q[0:9] rsecl output inverted differential outputs [0:9]. typically terminated with 50 to v tt = v cc - 1.5 v d5 vtsel - internal 50 termination pin for sel. see table 4. (note 1) d6 sel ecl, cml, lvcmos, lvds, lvttl input noninverted differential select logic input. internal 75 k to v ee . c5 vtsel - internal 50 termination pin for sel . see table 4. (note 1) c6 sel ecl, cml, lvcmos, lvds, lvttl input inverted differential select logic input. internal 75 k to v ee and 36.5 k to v cc . d3 vten - internal 50 termination pin for en. see table 4. (note 1) d2 en ecl, cml, lvcmos, lvds, lvttl input noninverted differential output enable pin. internal 75 k to v ee . e3 vten - internal 50 termination pin for en . see table 4. (note 1) e2 en ecl, cml, lvcmos, lvds, lvttl input inverted differential output enable pin. internal 75 k to v ee and 36.5 k to v cc . f2,b6 nc - no connect. the nc pins are electrically connected to the die and omust beo left open. 1. in the differential configuration when the input termination pins (vtclk, vtdclk ) are connected to a common termination voltage and if no signal is applied, then the device will be susceptible to self-oscillation.
nbsg111 http://onsemi.com 4 (f6) v bb 0 1 (f4) clk0 (f5) clk0 (b4) clk1 (b3) clk1 (d6) sel q 0 (b1) q 0 (c1) q 1 (d1) q 1 (e1) q 2 (f1) q 2 (g2) q 3 (g3) q 3 (g4) q 4 (g5) q 4 (g6) q 5 (f7) q 5 (e7) q 6 (d7) q 6 (c7) q 7 (b7) q 7 (a6) q 8 (a5) q 8 (a4) q 9 (a3) q 9 (a2) (a1, a7, g1, g7) v ee (b5, d4, f3) v cc table 2. function table active input disabled outputs clk0, clk0 disabled outputs clk1, clk1 sel l l h h en l h l h (b2) v mm (e3) vten (e2) en (d3) vten (d2) en (c6) sel (c5) vtsel (e4) vtclk0 (e5) vtclk0 (c4) vtclk1 (c3) vtclk1 (d5) vtsel figure 2. logic diagram sync 2. sel /en are the inverse of sel/en unless specified otherwise. r tin r 1 r 2 r tin r 2 r tin r 2 r 1 r 2 r 2 r 1 r tin r tin r tin r tin r 2 r 2 r tin r 2 r 1 table 3. interfacing options interfacing options connections cml connect vtclk0, vtclk1, vten, vtsel and vtclk0 , vtclk1 , vten , vtsel to v cc lvds connect vtclk0, vtclk1, vten, vtsel and vtclk0 , vtclk1 , vten , vtsel together ac-coupled bias vtclk0, vtclk1, vten, vtsel and vtclk0 , vtclk1 , vten , vtsel inputs within common mode range (v ihcmr ) rsecl, pecl, necl standard ecl termination techniques lvttl, lvcmos see text on page 1. unused differential input switching voltage reference range is from v ee + 1125 mv to v cc - 75 mv
nbsg111 http://onsemi.com 5 table 4. attributes characteristics value internal input pulldown resistor, r2 (clk0, clk0 , clk1, clk1 , sel, sel , en, en ) 75 k internal input pullup resistor, r1 (clk0 , clk1 , sel , en ) 36.5 k esd protection human body model machine model charged device model > 2 kv > 100 v > 1 kv moisture sensitivity (note 3) level 3 flammability rating oxygen index: 28 to 34 ul 94 v-0 @ 0.125 in transistor count 479 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 5. maximum ratings (note 4) symbol parameter condition 1 condition 2 rating units v cc positive power supply v ee = 0 v 3.6 v v i positive input negative input v ee = 0 v v cc = 0 v v i v cc v i v ee 3.6 -3.6 v v v ee negative power supply v cc = 0 v -3.6 v v inpp differential input voltage |clk - clk | v cc - v ee 2.8 v v cc - v ee 2.8 v 2.8 |v cc - v ee | v v i out output current continuous surge 25 50 ma ma i in input current through r t (50 resistor) static surge 45 80 ma ma i bb v bb sink/source 1 ma i mm v mm sink/source 1 ma ta operating temperature range -40 to +70 c t stg storage temperature range -65 to +150 c ja thermal resistance (junction-to-ambient) (note 5) 0 lfpm 500 lfpm 49 fcbga 49 fcbga 67 57 c/w c/w jc thermal resistance (junction-to-case) 2s2p (note 5) 49 fcbga 2 to 4 c/w t sol wave solder < 15 sec. 225 c 4. maximum ratings are those values beyond which device damage may occur. 5. jedec standard 51-6, multilayer board - 2s2p (2 signal, 2 power).
nbsg111 http://onsemi.com 6 table 6. dc characteristics, input with rspecl output v cc = 2.5 v; v ee = 0 v (note 6) -40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 70 85 100 70 85 100 70 85 100 ma v oh output high voltage (note 7) 1490 1540 1590 1510 1560 1610 1520 1570 1620 mv v outpp output voltage amplitude 300 370 450 300 370 450 300 370 450 mv v ih input high voltage (single-ended) (notes 9 and 10) v thr + 75 v cc - 1000* v cc v thr + 75 v cc - 1000* v cc v thr + 75 v cc - 1000* v cc mv v il input low voltage (single-ended) (notes 9 and 11) v ih - 2500 v cc - 1400* v thr - 75 v ih - 2500 v cc - 1400* v thr - 75 v ih - 2500 v cc - 1400* v thr - 75 mv v bb pecl output voltage reference 1080 1140 1200 1080 1140 1200 1080 1140 1200 mv v ihcmr input high voltage common mode range (differential configuration) (note 8) 1.2 2.5 1.2 2.5 1.2 2.5 v v mm lvcmos output voltage reference (v cc - v ee ) / 2 1100 1250 1400 1100 1250 1400 1100 1250 1400 mv r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 30 100 30 100 30 100 a i il input low current (@ v il ) 25 100 25 100 25 100 a table 7. dc characteristics, input with rspecl output v cc = 3.3 v; v ee = 0 v (note 12) -40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 70 85 100 70 85 100 70 85 100 ma v oh output high voltage (note 7) 2290 2340 2390 2310 2360 2410 2320 2370 2420 mv v outpp output voltage amplitude 300 370 450 300 370 450 300 370 450 mv v ih input high voltage (single-ended) (notes 9 and 10) v thr + 75 v cc - 1000* v cc v thr + 75 v cc - 1000* v cc v thr + 75 v cc - 1000* v cc mv v il input low voltage (single-ended) (notes 9 and 11) v ih - 2500 v cc - 1400* v thr - 75 v ih - 2500 v cc - 1400* v thr - 75 v ih - 2500 v cc - 1400* v thr - 75 mv v bb pecl output voltage reference 1880 1940 2000 1880 1940 2000 1880 1940 2000 mv v ihcmr input high voltage common mode range (differential configuration) (note 8) 1.2 3.3 1.2 3.3 1.2 3.3 v v mm lvcmos output voltage reference (v cc - v ee )/2 1500 1650 1800 1500 1650 1800 1500 1650 1800 mv r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 30 100 30 100 30 100 a i il input low current (@ v il ) 25 100 25 100 25 100 a note: sige circuits are designed to meet the dc specifications shown in the above tables after thermal equilibrium has been established. t he circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. input and output parameters vary 1:1 with v cc . v ee can vary +0.125 v to -0.965 v. 7. all outputs loaded with 50 to v cc - 1.5 v. v oh /v ol measured at v ih /v il (typical). 8. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 9. v thr is the voltage applied to the complementary input, typically v bb or v mm . v thr(min) = v ihcmr + 75 mv. v thr(max) = v ihcmr - 75 mv. 10. v ih cannot exceed v cc . 11. v il always v ee . 12. input and output parameters vary 1:1 with v cc . v ee can vary +0.925 v to -0.165 v. *typicals used for testing purposes.
nbsg111 http://onsemi.com 7 table 8. dc characteristics, necl or rsnecl input with necl output v cc = 0 v; v ee = -3.465 v to -2.375 v (note 13) -40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 70 85 100 70 85 100 70 85 100 ma voh output high voltage (note 14) -1010 -960 -910 -990 -940 -890 -980 -930 -880 mv v outpp output voltage amplitude 300 370 450 300 370 450 300 370 450 mv v ih input high voltage (single-ended) (notes 16 and 17) v thr + 75 v cc - 1000* v cc v thr + 75 v cc - 1000* v cc v thr + 75 v cc - 1000* v cc mv v il input low voltage (single-ended) (notes 16 and 18) v ih - 2500 v cc - 1400* v thr - 75 v ih - 2500 v cc - 1400* v thr - 75 v ih - 2500 v cc - 1400* v thr - 75 mv v bb necl output voltage reference -1420 -1360 -1300 -1420 -1360 -1300 -1420 -1360 -1300 mv v ihcmr input high voltage common mode range (differential configuration) (note 15) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 v v mm lvcmos output voltage reference (v cc - v ee )/2 (note 19) v mmt - 150 v mmt v mmt + 150 v mmt - 150 v mmt v mmt + 150 v mmt - 150 v mmt v mmt + 150 mv r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 30 100 30 100 30 100 a i il input low current (@ v il ) 25 100 25 100 25 100 a note: sige circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 13. input and output parameters vary 1:1 with v cc . 14. all outputs loaded with 50 to v cc - 1.5 v. v oh /v ol measured at v ih /v il (typical). 15. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 16. v thr is the voltage applied to the complementary input, typically v bb or v mm . v thr(min) = v ihcmr + 75 mv. v thr(max) = v ihcmr - 75 mv. 17. v ih cannot exceed v cc . 18. v il always v ee . 19. v mm typical = |v cc - v ee | / 2 + v ee = v mmt . *typicals used for testing purposes.
nbsg111 http://onsemi.com 8 table 9. ac characteristics v cc = 0 v; v ee = -3.465 v to -2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v -40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit v outpp output voltage amplitude f in < 3 ghz (see figure 3) (note 20) f in = 5.5 ghz 320 180 420 250 300 150 400 220 300 100 400 200 mv t plh , t phl propagation delay to output differential output enable clock select 250 430 400 300 550 450 350 700 500 250 430 400 300 550 450 350 700 500 250 430 400 300 600 480 350 750 550 ps t skew duty cycle skew (note 21) within-device skew (note 22) device-to-device skew (note 23) 2 5 15 15 20 85 2 5 15 15 20 85 2 5 15 15 20 85 ps t s setup time to clk (en to selected clk0:1) 110 70 110 70 115 80 ps t h hold time (en to selected clk0:1) 110 70 110 70 115 80 ps t jitter rms random clock jitter(figure 3) (note 25) f in = 5 ghz peak-to-peak data dependent jitter (note 26) f in = 5 gb/s 0.5 2.0 0.5 14 2.0 0.5 2.0 ps v inpp input voltage swing/sensitivity (differential configuration) (note 24) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times (20% - 80%) @ 1 ghz q, q 40 60 80 40 60 80 40 60 80 ps 20. measured using a 500 mv source, 50% duty cycle clock source. all outputs loaded with 50 to v cc - 1.5 v. input edge rates 40 ps (20% - 80%). 21. t skew = |t plh - t phl | for a nominal 50% differential clock input waveform (figure 4). 22. within-device skew is measured between outputs under identical transitions and conditions on any one device. 23. device-to-device skew for identical transitions at identical v cc levels. 24. v inpp (max) cannot exceed v cc - v ee (applicable only when v cc -v ee 2600 mv). 25. additive rms jitter with 50% duty cycle clock signal at 5 ghz. 26. additive peak-to-peak jitter with input nrz data at prbs 2 31 -1 at 5 gb/s.
nbsg111 http://onsemi.com 9 150 250 350 450 550 123456 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 rms jitter (ps) input frequency (ghz) figure 3. output voltage amplitude (v outpp ) / rms jitter vs. input frequency (f in ) at ambient temperature (typical) output voltage amplitude (mv) rms jitter (ps) q amp (mv) 3.3 v 2.5 v driver device receiver device qd 50 50 v tt q d figure 4. ac reference measurement clk clk q q t phl t plh v inpp = v ih (clk) - v il (clk) figure 5. typical termination for output driver and device evaluation (refer to application note and8020 - termination of ecl logic devices) v tt = v cc - 1.5 v v outpp = v oh (q) - v ol (q) z = 50 z = 50
nbsg111 http://onsemi.com 10 package dimensions fcbga-49 ba suffix plastic 8x8 mm (1.0 mm pitch) bga flip chip package case 489a-02 issue a 0.15 terminal a1 corner z 0.12 c 0.20 c view z-z e1 z a 0.15 c 0.08 c b 49 x feducial for pin a1 identification in this area 43 21 a e f g 49 x notes: 1. controlling dimension: millimeter. 2. dimensions and tolerances per asme y14.5m-1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane c. 4. datum c (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. 6. 489a-01 obsolete, new standard 489a-02. m m 765 b c d e note 5 note 4 a2 a dim a min max millimeters a1 a2 0.91 ref b 0.40 0.60 d 8.00 bsc d1 6.00 bsc e 8.00 bsc e1 1.00 bsc e a b e d c 4 x c d1 e b note 3 detail a a1 seating plane detail a (rotated 90 c.w.) --- 1.40 6.00 bsc 0.3 0.5 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. typicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 phone : 81-3-5773-3850 on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nbsg111/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 800-282-9855 toll free usa/canada
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