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1 msps 12-bit impedance converter, network analyzer prelim inary technical data AD5933 rev. pr a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . specifications subjec t to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures 50khz max excitation output impedance range .1k-20m, 1 2 bit resolutio n selectable sys t em clock from the following: pll, rc oscillator, external clo ck dsp real and i m aginary ca lculation (fft) 3v power supp ly, programmable sinewave out p ut frequency r e s o lution 27 bits (<0.1h z) frequency sweep capability 12 bit samplin g adc adc s a mpling 1msps, inl +/- 1lsb max. on chip temp sensor allows +/-2 oc accurac y serial i2 c loa d i n g temperature r a nge C40-1 25oc 16 ssop applic ati o ns complex impedance measur e m ent impedance spectrometry biomedical and a u tomotive sensors proximity sens ors fft processing general description the AD5933 is a hig h p r ecisio n im p e dan c e con v er t e r sys t em s o lut i on w h i c h c o mb i n e s a n o n b o ard f r e q u e nc y ge ne r a tor w i t h a 12 b i t 1ms p s ad c. th e f r eq u e n c y g e n e ra t o r al lo ws a n ext e r n al co m p lex im p e dan c e t o b e exci t e d wi t h a k n o w n f r e q uen c y . th e r e s p o n s e sig n al f r o m t h e i m p e da n c e is s a m p le d b y t h e o n b o a r d ad c and f f t p r o c ess e d b y a n o n - b o a r d dsp e n g i ne. t h e f f t a l gor i t h m re tu r n s a r e a l ( r ) an d i m ag i n ar y (i) da t a wo rd , al lowing im p e dan c e to be con v e n ie n t ly c a lc u l a t e d . the i m p e dan c e ma g n i t ude an d phas e is e a si l y c a lc u l a t e d usin g th e f o llo w i n g e q ua ti o n s: ma g ni t ud e = r + i 22 ph a s e = t an ( i / r ) -1 t o deter m i n e t h e ac t u al r e al im p e dan c e va l u e z(w) , g e n e ral l y a f r e q u e nc y s w e e p i s p e r f or me d. t h e i m p e d a nc e c a n b e cal c ul a t ed a t eac h po in t a n d a f r eq ue n c y v s m a gn i t ud e p l o t ca n be cr ea t e d . the sys t e m al lo ws t h e us er t o pr og ra m a 2v pk-pk sin u s o i d a l sig n a l as exci t a t i o n t o an ext e r n a l lo ad . o u t p u t ra n g es o f 1v , 500mv , 200mv ca n als o be p r og ra mm e d . th e s i g n al is p r o v ide d on ch i p usin g dds t e chniq u es. f r e q ue n c y r e s o l u t i o n o f 27 b i ts (les s t h a n 0.1h z) can be ac hieved . the c l o c k f o r th e dds can b e ge ner a te d f r o m a n ex ter n a l r e fer e n c e clo c k, a n in t e r n al r c os ci l l a t o r o r a n in t e r n al p ll. the pll has a ga in s t a g e o f 512 and typ i cal l y n e eds a r e f e r e n c e c l o c k o f 32kh z o n th e m c l k p i n. t o p e r f o r m t h e f r e q uen c y sw e e p , t h e us er m u s t f i rs t p r og ra m th e co n d i ti o n s r e q u i r ed f o r th e sw ee p; s t a r t f r eq ue n c y , d e l t a f r eq ue n c y , s t e p f r eq ue n c y , e t c. a s t a r t c o m m a n d i s th en r e q u i r ed t o be gin th e s w eep . a t eac h p o in t on the sw eep t h e ad c wil l ta k e 1 024 s a m p les and c a l c u l a t e a d i s c re te f o u r i e r t r ans f or m to prov i d e t h e re a l a n d ima g in a r y da t a fo r t h e wa v e fo r m . t h e r e a l and ima g ina r y d a t a is a v a i la b l e t o t h e us er t h r o ug h t h e 12c in t e r f ace . t o deter m i n e t h e im p e dan c e o f t h e lo ad a t an y o n e f r e q ue n c y p o in t, z(w), a me as ur emen t sys t em com p r i s e d of a t r a n s im p e d a n c e am plif ier , ga in st a g e a nd a d c a r e us e d t o r e co r d da t a . the ga i n st a g e fo r t h e r e sp o n s e s t a g e is 1 or 5. the ad c is a low n o is e , hig h s p eed 1ms p s s a m p lin g ad c tha t o p era t es f r o m a 3v s u p p l y . c l o c kin g fo r b o t h t h e d d s an d ad c sig n als is p r o v ide d ext e r n al l y via the mc lk r e fer e n c e clo c k, w h ich is p r o v ide d ext e r n a l ly f r o m a cr y s ta l os ci l l a t o r . t h e AD5933 is a v a i l a b l e in a 16 ld s s o p . dd s c o r e (2 7 b it s ) da c adc (1 2 b i t ) i2c i nter f a ce d i gital c o n tr ol l ogic sc l sd a vo u t = 2 v ( g = 1 ) 1 0 2 4 p oint df t z( w ) g = 1/ 0 . 5 / 0. 2/ 0 . 1 vb rc o s c 4 g= 1/ 5 4 rfb i m a g ed a t a1 6 b i t s r e al d a t a 16 bi t s int e rn a l ba n d g a p ref e ren c e pl l te m p se n s or mclk
AD5933 preliminary technical data rev. pra | page 2 of 20 table of contents specifications ..................................................................................... 3 timing characteristics ..................................................................... 5 pin configuration and function description ................................ 6 general description ......................................................................... 7 output stage .................................................................................. 7 circuit description ....................................................................... 7 numerical controlled oscillator + phase modulator ............. 7 sin rom ....................................................................................... 8 response stage .............................................................................. 8 adc operation ............................................................................ 8 dft conversion ........................................................................... 8 temperature sensor ..................................................................... 9 register map (each row equals 8 bits of data) ......................... 11 control register .......................................................................... 13 control register decode: .......................................................... 14 initialize sensor with start frequency ..................................... 14 start frequency sweep ............................................................... 14 increment frequency ................................................................. 14 repeat frequency ....................................................................... 14 power down ................................................................................ 14 standby mode ............................................................................. 14 read temperature ...................................................................... 14 error checking ........................................................................... 14 reset .......................................................................................... 14 system clock ............................................................................... 14 output voltage ............................................................................ 14 post gain ..................................................................................... 14 performing a frequency sweep C flow chart ............................ 15 serial bus interface ..................................................................... 15 general i 2 c timing .................................................................... 15 writing/reading to the AD5933 .............................................. 16 block write .................................................................................. 17 AD5933 read operations ......................................................... 17 error correction ......................................................................... 18 p. e . c . ............................................................................................ 18 checksum .................................................................................... 18 user command codes .............................................................. 18 outline dimensions ....................................................................... 20 esd caution ................................................................................ 20 revision history 12/04revision prapreliminary version
preliminary technical data AD5933 rev. pra | page 3 of 20 specifications v dd = +3.0 v +/- 10%, t min to t max unless otherwise noted. table 1. parameter b version 1 min typ max unit test conditions/comments system specs: impedance range .0001 20 m ohm total system accuracy 1 % system ppm tdb ppm/oc mclk update rate 16 msps output stage frequency specs output frequency range 0 50khz hz uni-polar sinusoidal signal. frequency resoltuion 27 bits. <0.1 hz resolution mclk external rerference clock. typically 16.667mhz. initial frequency accuracy 0.1 hz output exitation accuracy. 0 -50khz range. rc oscillator internal rc oscillator. initial frequency accuracy 1.5 % output excitation accuracy. 0 -50khz range. calibrated frequency accuracy 0.1 hz 0 -50khz range. 1 point offset calibration frequency tempco 10 ppm/oc requires 2 point user calibration. frequency jitter tdb jitter on vout pin, 30khz output. pll pll gain 512 input clock range 32 khz frequency jitter tdb jitter on vout pin, 30khz output. output voltage specs ac voltage range 2.0 volts pk-pk unipolar voltage on output. output voltage error tbd % voltage error on pk-pk output. dc bias vdd/2 volts dc bias of ac signal dc bias error tbd % tolerance of dc bias ac voltage range 1.0 volts pk-pk unipolar voltage on output. output voltage error tbd % voltage error on pk-pk output. dc bias vdd/4 volts dc bias of ac signal dc bias error 1 % tolerance of dc bias ac voltage range 0.4 volts pk-pk unipolar voltage on output. output voltage error tbd % voltage error on pk-pk output. dc bias vdd/8 volts dc bias of ac signal dc bias error tbd % tolerance of dc bias ac voltage range 0.2 volts pk-pk unipolar voltage on output. output voltage error tbd % voltage error on pk-pk output. dc bias vdd/16 volts dc bias of ac signal dc bias error tbd % tolerance of dc bias dc output impedance 120 ohm short circuit current 75 ma at 3 volts. short circuit current 100 ma at 5 volts. ac characteristics signal to noise ratio 60 db total harmonic distortion -66 db spurious free dynamic range wideband 60 db
AD5933 preliminary technical data rev. pra | page 4 of 20 parameter b version 1 min typ max unit test conditions/comments narrowband 80 db clock feedthrough tbd db system response stage analog input vin input leakage current 1 na to pin vin input capacitance 0.5 pf to pin vin input impedance 100m ohm to pin vin adc accuracy resolution 12 sampling rate 1 msps integral nonlinearity 1 lsb no missing codes differential nonlinearity 1 lsb offset error gain error temperature sensor accuracy 1 oc ta = -40 - 125 degrees resolution 0.03125 oc temperature conversion time tbd us logic inputs vih, input high voltage 2.2 vdd = 3v vil, input low voltage 0.8 vdd = 3v input current 1 ua input capacitance 3 pf power requirements vdd 3.0 volts idd (normal mode) 15 ma idd (powerdown mode) tbd ua 1 temperature ranges are as follows: b ve rsion: C40c to +125 c, typical at 25c. 2 guaranteed by design and characterization, not production tested.
prelim inary technical data AD5933 r e v. pr a | pa g e 5 of 20 timing characteristics table 2. i 2 c serial in terface p a r a me t e r 1 limit a t t min , t ma x u n i t d e s c r i p t i o n f scl 400 khz max scl clock frequ e ncy t 1 2.5 s min scl cycle time t 2 0 . 6 s m i n t high , scl high time t 3 1 . 3 s m i n t low , scl low time t 4 0 . 6 s m i n t hd , st a , start/rep e ated start condition hold time t 5 1 0 0 n s m i n t su , dat , data setu p time t 6 2 0 . 9 s m a x t hd , dat data hold time 0 s m i n t hd , dat data hold time t 7 0 . 6 s m i n t su , st a setup tim e for repeated start t 8 0 . 6 s m i n t su , st o stop con d ition setup time t 9 1 . 3 s m i n t bu f , bus free time between a sto p and a start co ndition t 10 3 0 0 n s m a x t f , fall time of sda when transmitting 0 n s m i n t r , rise time of scl and sda when receiving (c mos compatible) t 11 3 0 0 n s m a x t f , fall time of sda when transmitting 0 n s m i n t f , fall time of sda when receivi n g (cmos compatible) 3 0 0 n s m a x t f , fall time of scl and sda when receiving 20 + 0.1 c b ns min t f , fall time of scl and sda when transmitting c b 3 400 pf max capacitive load for each bus li ne 03773-0-007 scl sd a start condition repeated start condition stop condition t 9 t 3 t 10 t 11 t 4 t 4 t 6 t 2 t 5 t 7 t 8 t 1 fi g u r e 1 . i 2 c i n t e r f ac e timing d i agr a m
AD5933 prelim inary technical data r e v. pr a | pa g e 6 of 20 pin conf iguration and fu nction descriptions to p v i e w ( n o t t o s cale) dv d d av d d 2 mc lk vo u t vi n a d 593 x av d d 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 dg nd ag n d 2 ag n d 1 rf b _ p i n n/c n/c n/c sc l n/c sd a table 3. m n e m o n i c f u n c t i o n n/c no connect. rfb_pin external feedback resistor. this is used to set the gain of the input signal of the vin node. v o u t o u t p u t ac ex citation signal. programmble fre qunency range 0-50khz. vin input signal to transim p edance amplif ier. exter n al feed bac k re sistor wi ll co ntrol gain of transi mped ance am pl ifier. mclk master clock for the system. used to provide ou t p ut ex citation signal and as sampling of adc. dvdd digital supply voltage avdd1 analog supply voltage 1 avdd2 analog supply voltage 2 d g n d d i g i t a l g r o u n d agnd1 analog gnd 1 agnd2 analog gnd 2 sda i2c data inpu t scl i2c clock inpu t.
prelim inary technical data AD5933 r e v. pr a | pa g e 7 of 20 gene ral description the AD5933 is a hig h p r ecisio n im p e dan c e con v er t e r sys t em s o lut i on w h i c h c o mb i n e s a n o n b o ard f r e q u e nc y ge ne r a tor w i t h a 12 b i t 1ms p s ad c. th e f r eq u e n c y g e n e ra t o r al lo ws a n ext e r n al co m p lex im p e dan c e to b e exci t e d wi t h a k n o w n f r e q uen c y . th e r e s p o n s e sig n al f r o m t h e i m p e da n c e is s a m p le d b y t h e o n b o a r d ad c and f f t p r o c ess e d b y a n o n - b o a r d dsp en g i n e . th e ff t alg o r i t h m r e t u r n s tw o re al ( r ) a nd i m a g inar y (i) da t a w o r d s. the i m p e dan c e ma g n i t ude an d phas e is e a si l y ca lc u l a t e d usin g t h e fol l o w in g e q ua t i o n s: ma g ni t ud e = r + i 22 ph a s e = t an ( i / r ) -1 t o deter m i n e t h e ac t u al r e al im p e dan c e va l u e z(w) , g e n e ral l y a f r e q u e nc y s w e e p i s p e r f or me d. t h e i m p e d a nc e c a n b e cal c ul a t ed a t eac h po in t a n d a f r eq ue n c y v s m a gn i t ude p l o t ca n be cr ea t e d . gain fr e q uenc y fi g u r e 2 . the sys t e m al lo ws t h e us er t o pr og ra m a 2v pk-pk sin u s o i d a l sig n al as exci ta t i o n t o an ext e r n al lo ad . o u t p u t ra n g es o f 1v , 500mv , 200mv ca n als o be p r og ra mmed . the sig n al is p r o v ided on ch ip u s i n g d d s te ch n i qu e s . f r e q u e nc y re s o lut i on of 2 7 bit s (les s tha n 0.1h z) ca n b e ac hie v ed . th e c l o c k f o r th e d d s c a n be g e n e ra t e d f r o m a n e x t e rn al r e f e r e n c e c l oc k , a n in t e rn al r c os cil l a t o r o r a n in t e r n al p l l. th e pll has a ga in s t a g e o f 520 a nd ty pica l l y ne e d s a r e fer e n c e clo c k o f 32khz o n t h e mclk pi n . outpu t st age t h e output s t ag e of t h e a d 5 9 3 3 , show n i n d i a g r a m b e l o w , prov i d e s a c o n s t a n t output f r e q u e nc y or f r e q u e nc y s w e e p f u n c t i on w h ich has a p r o g ra m m a b le o u t p u t vol t a g e o f 2/1/0.5/0.2 v . the f r eq uen c y sw e e p s e q u en ce is p r e-p r oga m m e d thr o ug h th e i2 c in t e r f ace . an i2 c co mmand is us ed t o s t a r t t h e e x ci ta ti o n seq u en ce . rg a i n rl o a d v dd/ 8 tf 1 fi g u r e 3 . circuit description the AD5933 has a f u l l y in t e g r a t ed dir e c t dig i t a l s y n t h e sis ( d d s ) c o re to ge ne r a te re qu i r e d f r e q u e nc i e s . t h e bl o c k re qu i r e s a re fe re nc e cl o c k to prov i d e di g i t a l l y c r e a te d s i ne w a ve s up to 50khz. this is p r o v ide d t h r o u g h a n ext e r n a l refer e n c e clo c k, mclk. this clo c k is in ter n a l ly divide d do w n b y 4 to p r o v ide t h e r e fer e n c e clo c k o r fmclk t o t h e d d s. the i n t e r n al circ ui t r y o f t h e d d s co n s is ts o f t h e fol l o w in g main secti o n s : a n u m e ri c a l c o n t r o ll ed o s c i lla t o r (n co ), a f r e q uen c y m o d u la to r , s i n rom a nd a d i g i t a l - to -ana lo g co n v e r t e r . numerical controlled oscillator + phase modulator the ma i n com p o n e n t o f t h e nc o is a 27- b i t phas e acc u m u l a to r w h ich as s e m b le s t h e phas e com p o n e n t o f t h e ou t p ut sig n al . fi g u r e 4 c o n t in uo us t i me sig n als ha v e a phas e ra n g e o f 0 t o 2p i . o u tside t h is ra n g e o f n u m b ers, t h e sin u s o id f u n c t i o n s r e p e a t t h e m s e l v es in a p e r i o d ic m a nner . the dig i t a l im ple m e n t a t i o n is n o dif f er en t. th e acc u m u l a t o r sim p l y s c ales t h e ran g e o f phas e n u m b ers in t o a m u l t i - b i t d i g i t a l w o r d . t h e phas e acc u m u l a t o r in t h e d d s is im p l em en t e d wi th 28 b i ts. th er ef o r e , 2p i = 227. lik e w i se , t h e d p h a se t e rm i s scal ed in t o th i s ra n g e o f n u m b e r s 0 < d p has e < 2 27 C 1. m akin g t h es e s u bsti t u tion s in t o th e e q u a t i on a b ove f = d p has e x fm clk/227 wher e 0 < d p has e < 227 - 1. (n o t e . f m c l k = m c lk/4) the i n p u t t o t h e phas e acc u m u l a t o r (i .e ., t h e phas e s t ep) is s e l e c t ed fr o m t h e fr e q u e n c y r e g i s t e r . n c o s i n h e r e n t l y g e n e r a t e co n t in uo us p h as e sig n als, th us a v o i din g an y o u t p u t d i sco n t i n u i t y w h en sw i t c h i n g b e t w een f r eq uen c i e s .
AD5933 prelim inary technical data r e v. pr a | pa g e 8 of 20 sin rom t o ma k e t h e o u t p u t f r o m t h e nc o us ef u l , i t m u s t b e con v er t e d f r o m phas e infor m a t io n i n t o a s i n u s o i d a l va l u e. sin c e phas e info r m a t io n m a ps dir e c t ly in t o a m pli t ude , t h e sin ro m us es t h e dig i t a l phas e info r m a t io n as a n addr es s t o a lo ok-u p t a b l e , a nd con v er ts t h e phas e i n fo r m a t io n i n t o am pli t ude . a l t h o u g h t h e n c o con t ai n s a 27- b i t phas e acc u m u l a t o r , t h e o u t p ut o f t h e n c o i s tr un ca t e d t o 12 b i t s . u s i n g th e full r e so l u ti o n o f th e phas e acc u m u l a t o r is im p r ac t i c a l a nd un n e ce ss a r y as t h is w o u l d r e q u ir e a lo ok-u p ta b l e o f 227 en tr ies. i t is n e ces s a r y o n l y t o ha v e s u f f i cien t phas e r e s o l u t i on s u ch t h a t t h e er r o rs d u e t o tr un ca t i o n a r e sm alle r th a n th e r e so l u ti o n o f th e 10- b i td a c . this r e q u ir es t h e s i n r o m t o ha v e tw o b i ts o f phas e r e s o l u t i on m o r e t h an t h e 1 0 -b i t d a c. th e d d s i n cl udes a hig h i m p e dan c e c u r r en t s o ur ce 10-b i t d a c. response s t age the dia g ram b e lo w s h o w s t h e i n p u t s t a g e t o p i n tf1. c u r r en t f r om t h e e x te r n a l s e ns or l o a d f l ow s t h rou g h t h e t f 1 pi n a n d in t o a t r an sim p e d an c e am plif ie r w h ich h a s a n e x t e r n a l r e sist o r acr o s s i t s f e e d bac k . th e us er ne eds t o c h o o s e a p r ecisio n r e sis t o r in t h e fe e d b a ck lo o p s u ch t h a t t h e d y namic ra n g e o f t h e a d c i s use d . th e posi ti v e n o de o f th e tra n sim p e d a n ce a m plif ier is b i a s e d t o vdd / 2. t h e o u t p ut o f t h e t r a n sim p e d anc e a m p l if ier c a n t h en b e ga in e d b y ei th er 1 o r 5, a nd is fe d dir e c t ly in to t h e in p u t o f t h e a d c. v dd/ 2 r r 5r adc tf 1 fi g u r e 5 . adc opera t ion the AD5933 has a n in t e g r a t e d o n bo a r d 12 b i t ad c. th e ad c co n t a i n s an o n - c hi p t r ack and h o ld am plif ier , a successi ve a p p r o x im a t ion a/d con v er t e r . c l o c k i n g fo r t h e a/ d is p r o v id e d usin g a divid e d do wn r a t i o o f t h e r e fer e nce clo c k. the a / d is a s u cces si v e a p p r o x i m a t ion a n alog to dig i t a l co n v er t e r , b a s e d o n a c a p a c i t i ve d a c desig n ar chi t e c t u r e . th e f i gur e s be lo w s h o w sim p lif i e d s c h e ma tics o f t h e ad c. th e ad c is co m p r i s e d o f co n t r o l log i c, a sar , an d a c a p a ci t i ve d a c, a l l o f w h ich a r e us e d to ad d and sub t r a c t f i xe d am o u n t s o f cha r ge f r om t h e s a m p l i ng c a p a c i tor to b r i n g t h e c o m p ar a t or b a c k i n to a b a lance d cond i t io n. the 1st f i gur e sh o w s t h e ad c d u r i n g i t s acq u isi t ion pha s e . sw2 is clos e d an d s w 1 is i n p o si t i o n a, t h e co m p a r a t o r is he ld in a ba lan c e d con d i t io n, and the s a m p lin g ca p a c i t o r acq u ires t h e sig n al on v a 1, fo r exa m pl e . fi g u r e 6 . w h en t h e ad c s t a r ts a con v ersio n , sw2 wi l l op en and s w 1 wil l m o v e t o p o si tio n b , as sh o w n b e lo w , ca usin g th e co m p a r a t o r t o b e co me u n bal a nced . th e con t r o l log i c a n d t h e ca p a c i t i ve d a c a r e us e d to ad d a nd sub t r a c t f i x e d am o u n t s o f ch arge f r om t h e s a m p l i ng c a p a c i tor to b r i n g t h e c o m p ar a t or bac k in t o a b a lan c e d con d i t ion. w h en t h e com p a r a t o r is r e - b a lan c e d , t h e con v ersio n is com p let e . th e con t r o l log i c ge ne r a te s t h e a d c output c o de . fi g u r e 7 . the s t a r t con v e r sio n fo r t h e a d c is ei t h er us e r co n t r o l l e d v i a a n ext e r n al adc _ tr ig p i n o r can be in t e r n al l y p r og ra mm e d as a de l a y f r o m t h e st a r t o f t h e exi t a t io n sig n al . th e da t a f r o m t h e ad c is dir e c t l y a v a i la b l e on t h e i2c in ter f ace o r ca n e i t h er b e s t o r ed in a fifo ra m un t i l th e e n ti r e f r eq uen c y s w ee p i s co m p let e d . df t co nve r sion a dis c r e t e f o ur ier t r a n sfo r m is ca lc u l a t e d fo r e a ch f r e q uen c y p o in t in t h e sw e e p . the r e t u r n s i g n al is con v er t e d b y t h e a d c, wi n d o w e d and t h e n m u l t i p lie d wi t h a t e st ph as o r va l u e t o g i ve a r e al a nd ima g ina r y o u t p u t . this is r e p e a t e d f o r 1024 s a m p le po i n t s o f th e in p u t si gn al a n d th e r e s u l t s o f ea c h m u l t i p li ca ti o n s u mm e d t o g i v e a f i nal a n s w er as a co m p lex n u m b er . th e r e s u l t a n t a n s w er a t ea c h f r eq uen c y i s t w o 16 b i t w o r d s , th e r e al a nd im a g ina r y d a t a in com p lex fo r m .
prelim inary technical data AD5933 r e v. pr a | pa g e 9 of 20 fi g u r e 8 . the d f t alg o r i t h m is r e p r es en te d b y x(f ) = s u m x(n)[c os(n )-j s in e(n ) ] b o th th e r e al a n d i m a g i n a r y da t a r e gi s t e r ha v e 15 b i ts o f da ta a nd on e sig n b i t . th e 15 b i ts o f da t a a r e in 2 s c o m p li m e n t fo r m a t . the mag n i t ude o f t h e si g n al ca n b e r e p r es en t e d b y ma g ni t ud e = r + i 22 t h i s m a gn i t u d e t h a t s r e t u rn ed i s a s c a l ed v a l u ed o f t h e a c t u a l co m p lex im p e da n c e m e as ur e d . the m u l t i p lic a t i o n fac t o r b e tw e e n t h e mag n i t ude r e t u r n e d an d t h e ac t u al im p e dan c e is call ed t h e ga in f a c t o r . th e use r n eed s t o th en cal c ula t e thi s gain f a ct o r val u e an d us e i t f o r cali b r a t io n in the sys t em. temperature sensor the t e m p er a t ure s e n s o r is a 13 - b i t dig i t a l t e m p era t ur e s e n s o r wi t h a 14t h b i t t h a t ac ts as a sig n b i t. t h e b l o c k h o us es an o n - chi p t e m p er a t ure s e n s o r , a 13- b i t a/ d con v er t e r a nd a r e fer e nce cir c ui t. th e a/d co n v er t e r s e c t io n co n s ists o f a con v en tional successi ve- a p p r o x ima t ion con v er ter b a s e d a r o u nd a c a p a ci to r da c . the o n -chi p t e m p er a t ur e s e n s o r al lo ws a n acc u ra t e m e as ur e- m e n t o f t h e am b i e n t de vice t e m p er a t ur e t o b e made . th e s p ecif ie d m e as u r em en t ra n g e o f th e s e n s o r is ?40c t o +150c. a t +150c. th e s t r u c t ural in teg r i t y o f th e de vic e s t a r ts t o det e r i o r a t e w h e n o p era t e d a t v o l t a g e and t e m p e r a t ur e max i m u m sp e c i f ica t io n s . tem p er at ur e conversion d e tails the con v ersio n clo c k fo r t h e p a r t is in t e r n al l y g e n e r a t e d; n o ext e r n al clo c k is r e q u ir e d excep t w h en r e adin g f r o m a nd wr i t i n g t o t h e s e ri a l p o rt . i n n o r m a l m o de, a n i n ter n a l clo c k o s ci l l a t o r r u n s a n a u t o ma tic co n v ersion s e q u ence . dur i n g this a u t o ma tic co n v ersio n s e q u en c e , a con v ersio n is ini t i a te d e v er y 1 s e co n d . a t th i s tim e , th e pa r t po w e r s u p i t s a n alog ci r c ui tr y a n d pe rf o r m s a t e m p era t ur e con v ersio n . this tem p er a t ur e con v ersio n typ i c a l l y tak e s 800 s, a f ter whic h t i m e t h e analog cir c ui tr y o f th e p a r t a u tom a t i c a l l y s h ut s d o w n . t h e an a l o g c i rc u i t r y p o we rs up ag ai n w h en t h e 1 s e cond t i m e r t i m e s o u t an d t h e n e x t co n v ersion b e g i n s . th e r e su l t o f t h e m o s t re cen t t e m p era t u r e co n v ersio n is al wa ys a v a i lab l e in t h e s e r i al ou t p u t r e g i s t er b e c a us e t h e s e r i al in t e r f ace c i r c ui t r y n e v e r sh uts d o wn. the t e m p er a t ure s e n s o r b l o c k wil l def a u l t t o a p o w e r - do w n s t a t e . t o p e r f o r m a tem p era t ur e m e as ur e m en t a co mmand is wr i t t e n t o t h e c o n t r o l r e g i s t er . af t e r t h e tem p e r a t ur e o p er a t ion i s c o m p l e te, t h e bl o c k a u tom a t i c a l l y p o we rs dow n u n t i l t h e ne x t t e m p era t ur e comman d is is s u e d . i n n o r m al con v ersio n m o de , t h e in ter n al clo c k os ci l l a t o r is r e s e t a f t e r e v er y r e ad o r wr i t e o p era t i o n. this c a us es t h e de vice t o s t a r t a t e m p er a t ur e co n v ersio n , t h e r e s u l t o f w h ich is typ i cal l y a v a i la b l e 800 s la t e r . s i mila rl y , when t h e p a r t is tak e n o u t o f sh u t do w n m o de, t h e i n ter n a l clo c k o s ci l l a t o r is st a r te d and a co n v ersio n is ini t ia ted . the con v ersio n r e s u l t is a v a i la b l e 800 s la t e r , ty pica l l y . r e adin g f r o m t h e de vice b e fo r e a co n v ersio n is co m p let e ca us es t h e b l o c k t o st op co n v er t i n g ; t h e p a r t s t a r ts a g a i n w h e n s e r i a l co mm un ic a t i o n is f i nish e d . tem p er at ur e valu e r e giste r the t e m p er a t ure val u e r e g i s t er i s a 16- b i t r e ad- o nl y r e g i s t er t h a t s t o r es t h e t e m p era t ur e r e adin g f r o m t h e ad c i n 13- b i t tw os co m p le m e n t fo r m a t pl us a sig n b i t. th e tw o msb b i ts a r e don t ca r e s. d b 13 is th e sig n b i t. the ad c c a n t h eo retical l y m e as ur e a 255c t e m p er a t ur e s p a n . th e in t e r n al t e m p era t ur e s e n s o r is gua r a n te e d t o a lo w va l u e limi t o f C40c an d a hig h li mi t o f +150c. table 4. tem p e r ature data format t e m p e r a t u r e d i g i t a l output d b 1 3 d b 0 ?40c 11, 1011 0000 0 000 ?30c 11, 1100 0100 0 000 ?25c 11, 1100 1110 0 000 ?10c 11, 1110 1100 0 000 ?0.03125c 11, 1111 1111 1 111 0c 00, 0000 0000 0 000 +0.03125c 00, 0000 0000 0 001 +10c 00, 0001 0100 0 000 +25c 00, 0011 0010 0 000 +50c 00, 0110 0100 0 000 +75c 00, 1001 0110 0 000 +100c 00, 1100 1000 0 000 +125c 00, 1111 1010 0 000 +150c 01, 0010 1100 0 000 tem p er at ur e conversion f o rmul a 1. p o si ti v e t e m p er a t ur e = ad c c o de(d)/32 2. n e g a ti v e t e m p era t ur e = (ad c c o de*(d) C 163 84)/32 *u sin g al l 14 b i t s o f t h e da t a b y te , in cl udes t h e sig n b i t. n e g a ti v e t e m p era t ur e = (ad c c o de(d)* C 819 2)/32 *db13 (sig n b i t ) is r e m o v e d f r o m t h e a d c co d e
AD5933 prelim inary technical data r e v. pr a | pa g e 10 o f 20 digital outp ut ?40c ?0.03125c ?30c 11, 1111, 1111, 1111 11, 1100, 0100, 0000 11, 1011, 0000, 0000 temperature (c) 75c 02884- 0- 006 150 c 01, 0010, 1100, 0000 00, 1001, 0110, 0000 00, 0000, 0000, 0001 f i gure 9. t e mper at ur e to d i git a l t r ans f er f u nc ti on
preliminary technical data AD5933 rev. pra | page 11 of 20 register map (each row equals 8 bits of data) table 5. register name reg add. register data [8bits] read/write register register type ram control register 80h d15-d8 read/write ram 81h d7-d0 read/write ram start frequency (24 bits) 82h d23-d16 read/write ram 83h d15-d8 read/write ram 84h d7-d0 read/write ram frequency increment word 85h d23-d16 read/write ram 86h d15-d8 read/write ram 87h d7-d0 read/write ram no of increments (9 bits) bits d15-d9 = dont care bits d8-d0= number of frequency increments. 88h d15-d8 read/write ram 89h d7-d0 read/write ram settling time cycles (16 bits) d15 C d11= dont care d10 Cd9 = 2 bit decode d8-d0 = number of cycles d10 d9 0 default 0 1 number of cycles x2 1 0 reserved 1 1 number of cycles x4 8ah d15-d8 read/write ram 8bh d7-d0 read/write ram leakage limit for test a d7 C d4 = dont care d3 C d0 = 4 bit limit 8ch d7-d0 read/write ram leakage limit for test b d7 C d4 = dont care d3 C d0 = 4 bit limit 8dh d7-d0 read/write ram leakage limit for test c d7 C d4 = dont care d3 C d0 = 4 bit limit 8eh d7-d0 read/write ram status register 8fh d7-d0 read/write ram index counter of frequency (9 bits) bits d15 Cd9 = dont care bits d8- d0 = increments register after a frequency increment command. set to zero at initial frequency. 90h d15-d8 read only ram 91h d7-d0 read only temperature data register 92h d15-d8 read only ram 93h d7-d0 read only ram
AD5933 preliminary technical data rev. pra | page 12 of 20 register name reg add. register data [8bits] read/write register register type real data 94h d15-d8 read only ram 95h d7-d0 read only ram imaginary data 96h d15-d8 read only ram 97h d7-d0 read only ram checksum 98h d7-d0 read only ram
preliminary technical data AD5933 rev. pra | page 13 of 20 control register the AD5933 contains a 16 bit control register (address 80h and 81h) that set the AD5933 control modes. the five msbs of the control register are decoded to provide control functions for frequency sweep, power down and various other control functions, defined in table below. the other command functions of the control register are explained on the following pages. note: for error checking on the control register it is advised to write one byte at a time with pec enabled. this allows full error checking to be completed before the control register is updated and therefore ensures the control is not updated with incorrect data. the control register will power-up in the following state xa000h (i.e. in power-down) table 6. control register map bit d15 d15 d14 d13 d12 d11 frequency sweep d14 0 0 0 0 0 no operation/ exit fuse blow mode d13 0 0 0 0 1 initialize sensor with start frequency d12 0 0 0 1 0 start frequency sweep d11 0 0 0 1 1 increment frequency 0 0 1 0 0 repeat frequency 0 1 0 0 0 reserved. 0 1 0 0 1 measure temperature 0 1 0 1 0 power down 0 1 0 1 1 standby mode d10 external calibration mode = 1 d9 d9 d8 output voltage d8 0 0 no divide. (normal mode = 2.0v) 0 1 divide by 10 (200mv) 1 0 divide by 5 (400mv) 1 1 divide by 2 (1.0v) d7 post gain 0 = multiply x 5; 1 = multiply x 1. d6 error checking enable = 1; disable=0 d5 reserved. set to 0 d4 reset d3 d3 d2 system clock d2 0 0 internal oscillator 0 1 reserved. 1 0 external oscillator 1 1 pll d1 0 reserved d0 0 reserved
AD5933 preliminary technical data rev. pra | page 14 of 20 control register decode: initialize sensor with start frequency this command enables the dds to output the start frequency for an indefinite time. it is used is to excite the sensor initially. when the output load (sensor) has settled after a time determined by the user, the user must initiate a start frequency sweep command to begin the frequency sweep. start frequency sweep this command start the frequency sweep routine. when the ad11/2043 receives this command, it starts counting a delay cycle that will gate the adc conversion pulse. this delay cycle has already been pre-programmed as number of output cycles by the user. increment frequency the increment frequency command is used to step to the next frequency point in the sweep. this usually happens after data from the previous step has been transferred and verified by the dsp. repeat frequency repeat frequency allows the user to repeat any given frequency if the data gets corrupted or the measurement sequence doesnt complete. power down power down powers down all the blocks in the chip except the interface. all amplifiers and the oscillator will be powered off. the default on power-up of the ad11/2043 is power-down and the control register will contain the code 1010000000000000. in this mode both the output and input pins dds_out and in_adc will be tied to gnd. standby mode powers the part up for general operation; all the amplifiers will be powered up but their outputs will be tied to gnd. the internal oscillator will also be powered up and running. read temperature this initiates a temperature reading from the part. the part does not need to be in power up mode to perform a temperature reading. the block will power itself up, take the reading and then power down again. error checking set bit in control register to enable this. enable = 1; disable=0 reset a reset will refresh all memory, reset adc, frequency reverts to the initial start frequency system clock allows the user to configure either the internal oscillator, an external reference clock or to allow an internal pll to provide a clock for the system. in pll mode the user will have to provide a stable ~32khz clock as reference to the pll. output voltage this allows the user to change the excitation voltage levels. there are for output ranges, 2v, 1v, 500mv, 200mv. post gain allows the user to multiply pre-amp the response signal by a multiplication factor of 5 into the adc if required.
prelim inary technical data AD5933 r e v. pr a | pa g e 15 o f 20 performing a frequency sweep C flow chart pu t p a r t i n s t a nd b y mo de ( o nl y i f i n p o w e r do w n m o d e ) p r og r a m ? in i t ia li z e s e n s o r w i t h s t ar t f r e qu en cy ? c om man d w a i t u n ti l s en so r h as se tt led . p r o g r a m ? s t ar t f r e qu en cy sw e e p ? c o m m a n d wa i t d e l a y u n t i l ff t c o m p l e t e c h ec k s t a t u s r egi s t e r ? (v er i f y d a t a c o m p l e t ed ) y/ n ? r e pe a t f r eq ue nc y p oi nt read da t a fr o m a d 59 3 3 dat a o k ? r eset s w ee p f i n ish e d y /n ? pr og ra m a d 5 9 3 3 i nt o po w e r d o w n m o d e n y n y y n pr o g r a m ? i n cr e m e n t f r e que nc y? c m d f i g u re 10. serial bus interface c o n t r o l o f th e AD5933 is ca r r i ed o u t via t h e 1 2 c se ri al i n t e rf ac e p r o t o c ol . the AD5933 is co nn e c t e d t o this b u s as a sla v e de vic e , un der t h e con t rol o f a mas t er de v i ce . the AD5933 has a 7-b i t s e r i al b u s s l a v e addr es s. w h en t h e de vice is p o w e r e d u p , i t w i l l do s o wi t h a d e fa u l t s e r i a l b u s addr es s; 000110 1 general i 2 c timing t h e dia g ram belo w s h o w s the timin g dia g ra m fo r g e n e ral r e ad a nd wr i t e op era t io n s usin g t h e i 2 c in ter f ace . the g e n e ral i2 c proto c o l op e r at e s a s f o l l ow s :
AD5933 prelim inary technical data r e v. pr a | pa g e 16 o f 20 f i g u re 11. 1. th e mas t er ini t ia t e s da t a tra n sf er b y es ta b l is hin g a s t ar t co ndi t i on, def i ne d as a hig h to lo w t r a n si t i o n on t h e s e r i a l d a t a li n e s d a while th e se r i al c l oc k li n e scl r e m a in s h i gh . th i s indic a te s t h a t a d a t a st re am wi l l fol l ow . the sl a v e re sp onds to th e s t a r t co n d i ti o n a n d s h i f t i n t h e n e xt 8 b i ts, co n s i s ti n g o f a 7-b i t sl a v e address (ms b f i rst) pl us a n r/ w b i t , w h ich det e r m i n es t h e dir e c t io n o f t h e da t a t r an sfer , i . e . w h et her da t a wi l l b e wr i t t e n to o r r e ad f r o m t h e sla v e d e vice ( 0 = wr i t e , 1 = re a d ) . the s l a v e r e sp on ds b y p u l l in g t h e da t a l i n e lo w d u r i n g t h e lo w p e r i o d b e fo r e t h e nin t h clo c k p u ls e, k n o w n as t h e ack n o w le dge b i t, an d h o ldin g i t lo w d u r i n g t h e hig h p e r i o d o f this c l o c k p u ls e . al l o t h e r de vices on the b u s n o w r e ma in idle while t h e s e l e c t e d d e v i c e w a i t s for da t a to b e re a d f r om or w r i tte n to i t . i f t h e r / w b i t is a 0, t h en t h e mas t er wi l l wr i t e t o t h e sla v e de vice . i f t h e r / w b i t is a 1, t h e mas t er wi l l r e ad f r o m t h e sla v e de vice . 2. da ta is s e n t o v er th e s e r i al b u s in s e q u ences of nin e c l o c k pu l s e s , 8 bit s of d a t a f o l l owe d by an a c k n ow l e d g e bit , w h i c h c a n b e f r om t h e m a ste r or sl ave d e v i c e . d a t a t r ans i t i ons on t h e d a t a l i n e m u s t oc cu r d u ri n g th e l o w pe ri od o f th e c l oc k s i gn al a n d r e m a i n sta b le d u ri n g th e h i gh p e ri od , a s a lo w t o h i gh tra n si ti o n w h en t h e clo c k is hig h m a y b e i n t e r p r e t e d as a s t op sig n a l . i f t h e o p era t ion is a wr i t e o p er a t ion, t h e f i rs t da t a b y t e a f t e r t h e s l a v e addr es s is a co mmand b y te . this te l l s t h e s l a v e de vi ce w h a t t o exp e c t n e x t . i t ma y b e an in st r u c t io n t e l l in g t h e sla v e d e vice t o exp e c t a b l o c k wr i t e , o r i t ma y sim p l y be a reg i s t er addr es s t h a t te l l s t h e s l a v e w h er e s u bs e q uen t da t a is t o b e wr i t t e n. si n c e d a t a can f l o w in o n ly o n e dir e c t io n as def i ne d b y t h e r/ w b i t, i t is n o t p o ssi b le to s e nd a co m m a nd to a sl a v e d e v i ce d u r i n g a r e ad o p era t io n. b e fo r e do in g a re ad o p er a t ion, i t ma y f i rst b e ne c e ss ar y to do a w r ite op e r a t i o n to tel l t h e sl a v e w h a t s o r t of r e ad o p er a t io n to ex p e c t a nd/o r t h e ad dr ess f r o m w h ich d a t a is to b e re a d . 3. w h en all d a t a b y t e s h a v e been r e a d o r w r i t t e n , s t o p co n d i ti o n s a r e es ta b l i s h e d . i n wr it e m o de , th e m a s t e r w i ll p u ll t h e da t a li ne hig h d u r i n g t h e 10t h clo c k p u ls e t o as s e r t a st o p co ndi t i on. i n r e ad m o de , t h e mas t er de vice w i l l r e le as e t h e s d a line d u r i ng th e lo w p e r i o d b e f o r e th e 9t h c l o c k p u ls e , b u t th e s l a v e devi c e w i ll n o t p u ll i t lo w . t h i s i s kn o w n a s n o a c kn o w le dg e . th e mas t er wi l l t h e n t a k e t h e da t a li n e lo w d u ri n g th e lo w pe ri od be f o r e th e 10th c l oc k p u lse , th en h i g h d u r i n g t h e 10t h clo c k p u ls e t o as s e r t a st o p con d i t ion. writing/reading to the AD5933 the i n t e r f ace sp e c if ica t ion def i nes s e v e ral dif f er en t p r o t o c ols fo r dif f er en t typ e s o f r e ad a nd wr i t e op era t io ns. th e on es us e d in t h e AD5933 a r e dis c us s e d b e lo w . th e f o l l o w in g a b b r e v ia t i o n s are u s e d : s - s t a r t p - s t o p r - re ad w - w r i t e a - a c k n o w le dge - n o a c k n o w le dge write byt e /command byt e i n t h is o p era t ion t h e mast er de vice s e n d s a b y te o f da t a t o t h e s l a v e de vi ce . the wr i t e b y t e ca n ei t h er b e a da t a b y t e wr i t e t o a r a m lo c a t i o n or ca n b e a co m m a nd o p er a t ion . t o wr i t e da t a t o a r e g i s t er t h e c o mman d s e q u e n ce is as fol l o w s : 1. th e mas t er de v i ce as s e r t s a st a r t co n d i t ion on s d a. 2. th e mas t er s e n d s t h e 7 - b i t sla v e addr es s fol l o w e d b y t h e wr i t e b i t (lo w ). 3. th e addr es s e d s l a v e de vice as s e r t s a c k on sd a. 4. th e mas t er s e n d s a r e g i s t er addr es s. 5. th e s l a v e as s e r t s a c k o n s d a. 6. th e mas t er s e n d s a da t a b y t e . 7. th e s l a v e as s e r t s a c k o n s d a. 8. th e mas t er ass e r t s a s t o p con d i t ion o n s d a t o end t h e tra n sa cti o n .
prelim inary technical data AD5933 r e v. pr a | pa g e 17 o f 20 f i gur e 1 2 . w r i t i n g regi st er d a ta t o r e gi st er a ddr ess i n t h e AD5933, th e wr i t e b y t e p r o t o c ol is als o u s ed t o s e t a p o in t e r t o a r e g i st er lo ca t i o n . t h is is us e d fo r a subs e q uen t sin g le b y t e r e ad f r o m t h e s a me a ddr ess o r b l o c k r e ad o r wr i t e st a r t i n g a t t h a t addr ess. this is do ne as fol l o w s: t o s e t a r e g i st er p o in t e r t h e fol l o w i n g s e q u e n c e is a p plie d: 1. th e mas t er de v i ce as s e r t s a st a r t co n d i t ion on s d a. 2. th e mas t er s e n d s t h e 7 - b i t sla v e addr es s fol l o w e d b y t h e wr i t e b i t (lo w ). 3. th e addr es s e d s l a v e de vice as s e r t s a c k on sd a. 4. th e mas t er s e n d s a co mmand co de (p o i n t er c o mman d 1011 0000). 5. th e s l a v e as s e r t s a c k o n s d a. 6 . the m a st e r s e nds a d a t a b y te ( r e g i s te r l o c a t i on p o i n te r i s to po i n t t o ) . 7. th e s l a v e as s e r t s a c k o n s d a. 8. th e mas t er ass e r t s a s t o p con d i t ion o n s d a t o end t h e tra n sa cti o n . sl a v e addre ss s p o i n t e r c omma nd 10 1 1 00 0 0 w r e gi st er lo cat i on to p o i n t t o a a a p f i gur e 1 3 . setting p o i n t e r t o regi st er addr ess block write i n t h is o p era t ion, t h e mas t er de vice wr i t es a b l o c k o f da t a t o a sl a v e d e v i c e . t h e st ar t addre s s for a bl o c k wr i t e m u st p r e v iou sly ha v e been s e t. i n the cas e o f the AD5933 this is do ne b y s e t t ing a p o i n te r to s e t t h e r a m / otp a d dre s s . 1. th e mas t er de v i ce as s e r t s a st a r t co n d i t ion on s d a. 2. th e mas t er s e n d s t h e 7 - b i t sla v e addr es s fol l o w e d b y t h e wr i t e b i t (lo w ). 3. th e addr es s e d s l a v e de vice as s e r t s a c k on sd a. 4 the mast er s e n d s an 8 b i t comman d c o de (1 0100000) tha t t e l l s t h e s l a v e de vice t o exp e c t a b l o c k wr i t e . 5. th e s l a v e as s e r t s a c k o n s d a. 6. th e mas t er s e n d s a da t a b y t e t h a t te l l s t h e s l a v e de vic e t h e n u m b e r of da t a b y te s w i l l b e s e n t to i t . 7. th e s l a v e as s e r t s a c k o n s d a. 8. th e mas t er s e n d s t h e da t a b y tes. 9. th e s l a v e as s e r t s a c k o n s d a a f t e r e a ch da t a b y t e . 10. th e m a ster ass e r t s a s t op co ndi t i on o n sd a to e nd t h e tra n sa cti o n . f i g u re 14. w r it ing a bl ock wr ite AD5933 read operations the AD5933 us es th e f o l l o w in g i2c r e ad p r o t o c ols: recei v e byte i n this o p era t ion, th e mas t er de vice r e cei v es a s i n g le b y t e f r o m a sl a v e d e v i c e as f o l l ows : 1. th e mas t er device as s e r t s a s t ar t con d i t ion o n s d a. 2. th e mas t er s e n d s t h e 7 - b i t sla v e addr es s fol l o w e d b y t h e r e ad bi t ( h i g h ) . 3. th e addr es s e d s l a v e de vice as s e r t s a c k on sd a. 4. th e mas t er r e cei v es a da t a b y te . 5. th e mas t er ass e r t s n o a c k o n s d a. (s la v e n e e d s t o ch ec k th a t m a s t e r h a s r e ce i v ed da ta ) 6. th e mas t er ass e r t s a s t o p con d i t ion o n s d a a nd t h e tra n sa cti o n en ds. i n t h e AD5933, th e r e cei v e b y t e p r o t o c ol is us ed t o r e ad a sin g le b y t e o f da ta f r om a r a m o r otp m e m o r y lo ca tio n w h os e addr es s has p r e v io us l y b e en s e t t in g t h e addr es s p o in t e r .
AD5933 prelim inary technical data r e v. pr a | pa g e 18 o f 20 f i gure 1 5 . rea d i n g regi st er d a ta block r e ad i n t h is o p era t ion, t h e m a ster de vice r e ads a b l o c k o f d a t a f r o m a sl a v e d e v i c e . t h e st ar t addre s s for a bl o c k re a d m u st p r e v iou sly ha ve b e e n s e t. t h is is a g a i n done b y s e t t i n g a p o in ter to s e t t h e ra m/ o t p ad dr e s s . 1. th e mas t er device as s e r t s a s t ar t con d i t ion o n s d a. 2. th e mas t er s e n d s t h e 7 - b i t sla v e addr es s fol l o w e d b y t h e wr i t e b i t (lo w ). 3. th e a ddr ess e d sl a v e d e vice a s s e r t s a c k on sd a. 4. th e mas t er s e n d s a co mmand co de (10100001) tha t t e l l s t h e sla v e d e vi ce t o e x p e c t a b l o c k r e ad . 5. th e s l a v e as s e r t s a c k o n s d a. 6. th e mas t er s e n d s a b y t e co u n t da t a b y t e t h a t te l l s t h e sla v e how ma n y da t a b y te s to e x p e c t . 7. th e mas t er ass e r t s a c k on sd a. 8 . th e mas t er as s e r t s a r e p e a t sta r t co ndi tion on s d a. (this is r e q u ir e d t o s e t re a d b i t h i g h ) 9. th e mas t er s e n d s t h e 7 - b i t sla v e addr es s fol l o w e d b y t h e r e ad bi t ( h i g h ) . 10. th e s l a v e ass e r t s a c k on sd a. 11. th e mas t er r e cei v es t h e da t a b y t e s. 12. th e mas t er as s e r t s a c k o n s d a a f t e r e a ch da t a b y te . 1 4 . a n a c k i s ge ne r a te d af te r t h e l a st b y te to s i g n a l t h e e n d of th e r e ad . 15. th e m a ster ass e r t s a s t op co ndi t i on o n sd a to e nd t h e tra n sa cti o n . bl o c k r ead w a a sl a v e add r e s s s s r a num b e r byt es r ead byt e 0 a a a by te 1 by te 2 p a s sl a v e a ddres s f i g u re 16. p e r f or mi ng a b l o c k read error correction p.e.c. the AD5933 p r o v ides the o p tion o f is s u in g a pec (p ac k e t er r o r c o r r e c t i o n ) b y t e a f t e r al l co mma n ds. this enab les t h e us er t o v e r i f y tha t th e da ta r e c e i v e d b y o r s e n t f r o m t h e AD5933 is co r r ec t. th e p e c b y t e is an o p tio n al b y t e s e n t a f t e r tha t l a s t da t a b y te h a s b e e n w r i t te n to or re a d f r om t h e a d 5 9 3 3 . the proto c o l is as fol l o w s: 1. the AD5933 is sues a p e c b y t e to th e mas t er . the mast er sh o u ld ch e c k t h e pec b y t e an d issue ano t h e r b l o c k r e ad if t h e pec b y t e is in co r r e c t. 2 . a n a c k i s ge ne r a te d af te r t h e pe c b y te to s i g n a l t h e end o f t h e r e a d . 3. the pec is ge nera t e d p e r t h e fol l o w in g sp e c if i c a t ion s . n o t e : the p e c b y t e is calc u l a t e d usin g cr c - 8. the f r am e ch eck s e q u en ce (fc s ) co n f o r m s t o c r c- 8 b y th e po l y n o m i al: () 1 x x x x c 1 2 8 + + + = checksum a che c ks u m r e g i s t er is a v ai lab l e t o al lo w t h e us er t o v e r i f y t h e co rr ect co n t e n t s o f th e f r eq ue n c y r e gi s t e r , f r eq u e n c y in cr em e n t r e g i s t er , a nd n u m b er o f in cr emen ts. th e che c ks um r e g i s t er is b a s e d o n a er r o r ch e c ki n g alg o r i t h m f r o m t h e ab o v e r e g i s t ers. tbd . the us er r e ads t h is ch e c ksum r e g i s t er and v e r i f i es co n t en ts a r e co r r ec t. user command c o des th e s e co mmand co des a r e us e d fo r r e adin g/ w r i t in g t o t h e in t e r f ace a nd t h e m e m o r y . th e y a r e f u r t h e r expla i ne d in t h e a ppropr i a t e s e c t i o ns but are g r oup e d he re f o r e a s e of re f e re nc e.
preliminary technical data AD5933 rev. pra | page 19 of 20 table 7. command code code name code description. 1010 0000 block write this command is used when writing multiple bytes to the ram. see block write section for further explanations. 1010 0001 block read this command is used when reading multip le bytes from the ram/memory. see block write section for further explanations. 1011 0000 address pointer this command enables the user to set the address pointer to any location in the memory. the data will contain the address regi ster of the register the pointer should be pointing to.
AD5933 prelim inary technical data r e v. pr a | pa g e 20 o f 20 outline dimensions 16 9 8 1 6.50 6.20 5.90 8.20 7.80 7.40 seating plane 0.05 min 0.65 bsc 2.00 max 0.25 0.09 0.95 0.75 0.55 0.38 0.22 5.60 5.30 5.00 co p l ana ri t y 0. 10 8 4 0 1.85 1.75 1.65 compliant to jedec standards mo-150ac f i gure 17 1 6 -l ead shrink sm al l o u t lin e p a ckage [s sop ] (r s-16) di me nsio ns sho w n i n mi ll im e t e r s esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners .

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