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w49l102 64k 16 cmos 3.3v flash memory publication release date: february 19, 2002 - 1 - revision a4 general description the w49l102 is a 1 - megabit, 3.3 - volt only cmos flash memory organized as 64k 16 bits. the device can be programmed and erased in - system with a standard 3.3v power supply. a 12 - volt v pp is not required. the unique cell architecture of the w49l102 results in fast program/erase operations with extremely low current consumption (compared to other comparable 3.3 - volt flash memory products). the device can also be programmed and erased using standard eprom programmers. features single 3.3 - volt operations: - 3.3 - volt read - 3.3 - volt erase - 3.3 - volt program fast program operation: - word - by - word programming: 60 m s (max.) fast erase operation : 100 ms (typ.) fast read access time: 70/90/120 ns endurance: 10k cycles (typ.) twenty - year data retention hardware data pr otection 8k word boot block with lockout protection low power consumption - active current: 15 ma (typ.) - standby current: 10 m a (typ.) automatic program and erase timing with internal v pp generation end of program or erase detection - toggle bit - data polling latched address and data ttl compatible i/o jedec standard word - wide pinouts available packages: 40 - pin stsop (10 x 14 mm) and 44 - pin plcc
w49l102 - 2 - pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vss a8 a7 a15 a14 a13 a12 a11 a10 a9 #oe dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 vss 40-pin stsop 24 23 22 21 d q 15 n c v d d w e 1 4 a 1 5 a n c n c # c e d q 14 d q 13 11 12 13 39 38 37 36 35 34 33 44 1 2 3 4 5 6 26 25 24 23 22 21 20 44-pin plcc 28 27 40 41 42 43 7 8 9 a9 vss nc a8 a7 a6 a5 a13 a12 a11 a10 10 14 15 16 17 19 18 32 31 30 29 vss dq12 dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 nc d q 3 d q 2 # o e n c a 0 a 1 a 2 a 3 a 4 d q 1 d q 0 nc #we v dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 dd nc #ce a6 a5 a4 a3 a2 a1 a0 # block diagram control output buffer decoder main memory #ce #oe #we a0 . . a15 . . dq0 dq15 v dd v ss (56k words) bootblock (8k words) pin des cription symbol pin name a0 - a15 address inputs dq0 - dq15 data inputs/outputs #ce chip enable #oe output enable #we write enable v dd power supply v ss ground nc no connection
w49l102 publication release date: february 19, 2002 - 3 - revision a4 functional descripti on read mode the read operation of the w49l 102 is controlled by #ce and #oe, both of which have to be low for the host to obtain data from the outputs. #ce is used for device selection. when #ce is high, the chip is de - selected and only standby power will be consumed. #oe is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either #ce or #oe is high. refer to the timing waveforms for further details. boot block operation there is one 8k - word boot block in this device, which can be used to store boot code. it is located in the first 8k words of the memory with the address range from 0000 hex to 1fff hex. see command codes for boot block lockout enable for the specific code. once this feature is set the data for the designated block can not b e erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. once the boot block programming lockout feature is activated, the chip erase function will only affect the main memory. in order to dete ct whether the boot block feature is set on the 8k - words block, users can perform software command sequence: enter the product identification mode (see command codes for identification/boot block lockout detection for specific code), and then read from add ress "0002 hex". if the output data is "ff hex," the boot block programming lockout feature is activated; if the output data is "fe hex," the lockout feature is inactivated and the block can be erased/programmed. to return to normal operation, perform a t hree - byte command sequence (or an alternate single - word command) to exit the identification mode. for the specific code, see command codes for identification/boot block lockout detection. input levels while operating with a 3.0v - 3.6v power supply, the a ddress inputs and control inputs ( #oe , #ce and #we) may be driven from 0 to 5.5v without adversely affecting the operation of the device. the i/o lines can only be driven from 0 to 3.6v. chip erase operation the chip - erase mode can be initiated by a six - w ord command sequence. after the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed in a fast 100 ms (typical). the host system is not required to provide any control or timing during th is operation. if the boot block programming lockout is activated, only the data in the main memory will be erased to ff(hex), and the data in the boot block will not be erased (remains same as before the chip erase operation). the entire memory array (main memory and boot block) will be erased to ff hex. by the chip erase operation if the boot block programming lockout feature is not activated. the device will automatically return to normal read mode after the erase operation completed. data polling and/or toggle bits can be used to detect end of erase cycle. main memory erase operation the main memory erase mode can be initiated by a six - word command sequence. after the command loading cycle, the device enters the internal main - memory erase mode, which is a utomatically timed and will be completed in a fast 100 ms (typical). the host system is not required to provide any control or timing during this operation. the device will automatically return to normal read mode after the erase operation completed. data polling and/or toggle bits can be used to detect end of erase cycle.
w49l102 - 4 - program operation the w49l102 is programmed on a word - by - word basis. program operation can only change logical data "1" to logical data "0" the erase operation (changed entire data in mai n memory and/or boot block from "0" to "1" is needed before programming. the program operation is initiated by a 4 - word command cycle (see command codes for word programming). the device will internally enter the program operation immediately after the wor d - program command is entered. the internal program timer will automatically time - out (60 m s max. - t bp ) once completed and return to normal read mode. data polling and/or toggle bits can be used to detect end of program cycle. hardware data protection the integrity of the data stored in the w49l102 is also hardware protected in the following ways: (1) noise/glitch protection: a #we pulse of less than 15 ns in duration will not initiate a write cycle. (2) v dd power up/down detection: the programming and read operation are inhibited when v dd is less than 1.8v typical. (3) write inhibit mode: forcing #oe low, #ce high, or #we high will inhibit the write operation. this prevents inadvertent writes during power - up or power - down periods. (4) v dd power - on delay: when v dd has reached its sense level, the device will automatically time - out 10 ms before any write (erase/program) operation. data polling (dq 7 & dq 15 ) - write status detection the w49l102 includes a data polling feature to indicate the end of a program o r erase cycle. when the w49l102 is in the internal program or erase cycle, any attempt to read dq 7 or dq 15 of the last word loaded will receive the complement of the true data. once the program or erase cycle is completed, dq 7 or dq 15 will show the true d ata. note that dq 7 or dq 15 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has completed. toggle bit (dq 6 & dq 14 ) - write status detection in addition to data polling, the w49l102 provides another meth od for determining the end of a program cycle. during the internal program or erase cycle, any consecutive attempts to read dq 6 or dq 14 will produce alternating 0's and 1's. when the program or erase cycle is completed, this toggling between 0's and 1's wi ll stop. the device is then ready for the next operation. product identification the product id operation outputs the manufacturer code and device code. programming equipment automatically matches the device with its proper erase and programming algorithms . the manufacturer and device codes can be accessed by software or hardware operation. in the software access mode, a six - word (or jedec 3 - word) command sequence can be used to access the product id. a read from address 0000h outputs the manufacturer code (00dah). a read from address 0001h outputs the device code (002fh). the product id operation can be terminated by a three - word command sequence or an alternate one - word command sequence (see command definition table). in the hardware access mode, access to the product id is activated by forcing #ce and #oe low, #we high, and raising a9 to 12 volts. note: the hardware sid read function is not included in all parts; please refer to ordering information for details.
w49l102 publication release date: february 19, 2002 - 5 - revision a4 table of operating m odes operating mode sele ction (v hh = 12v 0.5v) mode pins #ce #oe #we address dq. read v il v il v ih a in dout write v il v ih v il a in din standby v ih x x x high z write inhibit x v il x x high z/d out x x v ih x high z/d out output disable x v ih x x high z product id v il v il v i h a0 = v il ; a1 - a15 = v il ; a9 = v hh manufacturer code 00da (hex) v il v il v ih a0 = v ih ; a1 - a15 = v il ; a9 = v hh device code 002f (hex) table of command def inition command no. of 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle description cycles addr. data addr. data addr. data addr. data addr. data addr. data read 1 a in d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 main memory erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 30 w ord program 4 5555 aa 2aaa 55 5555 a0 a in d in boot block lockout 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (1) 3 5555 aa 2aaa 55 5555 f0 produ ct id exit (1) 1 xxxx f0 note: address format: a14 - a0 (hex); data format: dq15 - dq8 (don't care); dq7 - dq0 (hex) either one of the two product id exit commands can be used.
w49l102 - 6 - embedded programming algorithm start write program command sequence (see below) increment address programming completed 5555h/aah 2aaah/55h 5555h/a0h program address/program data #data polling/ toggle bit last address ? no yes program command sequence (address/command): pause t bp
w49l102 publication release date: february 19, 2002 - 7 - revision a4 embedded erase a lgorithm 5555h/aah 5555h/aah 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 2aaah/55h 2aaah/55h 5555h/80h 5555h/80h 5555h/30h 5555h/10h chip erase command sequence (address/command): main memory erase command sequence (address/command): start write erase command sequence (see below) erasure completed #data polling or toggle bit successfully completed pause t ec /t sec
w49l102 - 8 - embedded #data polling algorithm start read byte (dq0 - dq7) address = va pass dq7 = data ? yes no va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = valid address equals any sector group address during chip erase embedded toggle bit algorithm start read byte (dq0 - dq7) address = don't care dq6 = toggle ? yes no fail
w49l102 publication release date: february 19, 2002 - 9 - revision a4 software product identification and boot block lockout detection acquisition flow product identification entry (1) load data 55 to address 2aaa load data 90 to address 5555 pause 10 s product identification and boot block lockout detection mode (3) read address = 00000 data = da read address = 00001 data = 2f read address = 00002 data = ff/fe (4) product identification exit(6) load data 55 to address 2aaa load data f0 to address 5555 normal mode (5) (2) (2) load data aa to address 5555 m load data aa to address 5555 pause 10 s m notes for software product identification/boot block lockout detection: (1) data format: dq15 - dq8 (don't care), dq7 - dq0 (hex); address format: a14 - a0 (hex) (2) a1 - a15 = v il ; manufacture code is read for a0 = v il ; device code is read for a0 = v ih . (3) the device does not remain in identification and boot block lockout detection mode if power down. (4) if the output data is "ff hex," the boot block programming lockout feature is activated; if the output data "fe hex," the lockout feature is inactivated and the block can be programmed. (5) the device returns to standard operation mode. (6) optional 1 - write cycle (write f0 hex at xxxx address) can be used to exit the product identification/boot block lockout detection.
w49l102 - 10 - boot block lockout enable acquisition flow boot block lockout feature set flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 pause 1 sec. exit
w49l102 publication release date: february 19, 2002 - 11 - revision a4 dc characteristics absolute maximum ratings parameter rating unit power supply voltage to v ss potential - 0.5 to +4.6 v operating temperature 0 to +70 c storage temperature - 65 to +150 c d.c. voltage on any pin to ground potential e xcept a9 - 0.5 to v dd +1.0 v transient voltage (<20 ns) on any pin to ground potential - 1.0 to v dd +1.0 v voltage on a9 pin to ground potential - 0.5 to 12.5 v note: exposure to conditions beyond those listed under absolute maximum ratings may adversely a ffect the life and reliability of the device. dc operating characteristics (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) parameter sym. test conditions limits unit min. typ. max. power supply current i dd #ce = #oe = v il , #we = v ih , all i/os open a ddress inputs = v il /v ih , at f = 5 mhz - 15 25 ma standby v dd current (ttl input) i sb 1 #ce = v ih , all i/os open other inputs = v il /v ih - - 1 ma standby v dd current (cmos input) i sb 2 #ce = v dd - 0.3v, all i/os open other inputs = v dd - 0.3v/ v ss - 10 50 m a input leakage current i li v in = v ss to v dd - - 10 m a output leakage current i lo v out = v ss to v dd - - 10 m a input low voltage v il - - 0.3 - 0.6 v input high voltage v ih - 2.0 - v dd +0.5 v output low voltage v ol i ol = 1.6 ma - - 0.45 v output high v oltage v oh i oh = - 0.1 ma 2.4 - - v
w49l102 - 12 - power - up timing parameter symbol typical unit power - up to read operation t pu . read 200 m s power - up to write operation t pu . write 10 ms capacitance (v dd = 3.3v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit i/o pin capacitance c i/o v i/o = 0v 12 pf input capacitance c in v in = 0v 6 pf ac characteristics ac test conditions parameter conditions input pulse levels 0.4v/2.4v input rise/fall time <5 ns input/output timing level 1.5v/1.5v output load 1 tt l gate and c l = 30 pf for 70 ns c l = 100 pf for 90 and 120 ns ac test load and waveform +3.3v 1.8k 1.3k d out w w 30 pf for 70 ns 100 pf for 90 and 120 ns (including jig and scope) input 2.4v 0.4v test point test point 1.5v 1.5v output
w49l102 publication release date: february 19, 2002 - 13 - revision a4 ac characteristics, continued read cycle timing parameters (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) parameter sym. w49l102 - 70b w49l102 - 90b w49l102 - 12b unit min. max. min. max. min. max. read cycle time t rc 70 - 90 - 120 - ns chip enable access time t ce - 70 - 90 - 120 ns address access time t aa - 70 - 90 - 120 ns output enable access time t oe - 35 - 40 - 50 ns #ce low to active outpu t t clz 0 - 0 - 0 - ns #oe low to active output t olz 0 - 0 - 0 - ns #ce high to high - z output t chz - 30 - 30 - 30 ns #oe high to high - z output t ohz - 30 - 30 - 30 ns output hold from address change t oh 0 - 0 - 0 - ns write cycle timing parameters param eter symbol min. typ. max. unit address setup time t as 10 - - ns address hold time t ah 100 - - ns #we and #ce setup time t cs 0 - - ns #we and #ce hold time t ch 0 - - ns #oe high setup time t oes 0 - - ns #oe high hold time t oeh 0 - - ns #ce pulse wid th t cp 200 - - ns #we pulse width t wp 200 - - ns #we high width t wph 200 - - ns data setup time t ds 100 - - ns data hold time t dh 10 - - ns word programming time t bp - 50 60 m s erase cycle time t ec - 0.1 1 sec. note: all ac timing signals observe th e following guidelines for determining setup and hold times: (a) high level signal's reference level is v ih and (b) low level signal's reference level is v il .
w49l102 - 14 - ac characteristics, continued data polling and toggle bit timing parameters parameter sym. w49l102 - 70b w49l102 - 90b w49l102 - 12b unit min. max. min. max. min. max. #oe to data polling output delay t oep - 35 - 40 - 50 ns #ce to data polling output delay t cep - 70 - 90 - 120 ns #oe to toggle bit output delay t oet - 35 - 40 - 50 ns #ce to tog gle bit output delay t cet - 70 - 90 - 120 ns timing waveforms read cycle timing diagram address a15-0 dq15-0 data valid data valid high-z #ce #oe #we t rc v ih t clz t olz t oe t ce t oh t aa t chz t ohz high-z
w49l102 publication release date: february 19, 2002 - 15 - revision a4 timing waveforms, continued #we controlled command write cycle timing diagram address a15-0 dq15-0 data valid #ce #oe #we t as t cs t oes t ah t ch t oeh t wph t wp t ds t dh #ce controlled comm and write cycle timing diagram high z data valid #ce #oe #we dq15-0 t as t ah t cph t oeh t dh t ds t cp t oes address a15-0
w49l102 - 16 - timing waveforms, continued program cycle timing diagram address a15-0 word 0 word 1 word 2 internal write start dq15-0 #ce #oe #we word program cycle t bp t wph t wp 5555 5555 2aaa aa a0 55 address data-in word 3 #data polling timing diagram address a15-0 dq7/dq15 #we #oe #ce x x x x t cep t oeh t oep t oes t ec t bp or an an an an
w49l102 publication release date: february 19, 2002 - 17 - revision a4 timing waveforms, continued toggle bit timing diagr am address a15-0 dq6/dq14 #ce #oe #we t oeh t oes t bp or t ec boot block lockout enable timing diagram sw23 sw1 sw0 address a15-0 dq15-0 #ce #oe #we sw3 sw4 sw5 six-word code for boot block lockout feature enable t wc t wp t wph 5555 2aaa 5555 5555 2aaa 5555 xxaa xx55 xx80 xxaa xx55 xx40
w49l102 - 18 - timing waveforms, continued chip erase timing diagram sw2 sw1 sw0 address a15-0 dq15-0 #ce #oe #we sw3 sw4 sw5 internal erase starts six-word code for 3.3v-only software chip erase t wp t wph t ec 5555 2aaa 5555 5555 2aaa 5555 xxaa xx55 xx80 xxaa xx55 xx10 main memory erase timing diagram sw2 sw1 sw0 address a15-0 dq15-0 #ce #oe #we sw3 sw4 sw5 internal erase starts six-word code for 3.3v-only software main memory erase t wp t wph t ec 5555 2aaa 5555 5555 2aaa 5555 xxaa xx55 xx80 xxaa xx55 xx30
w49l102 publication release date: february 19, 2002 - 19 - revision a4 ordering information part no. access time ( n s) power supply current max. ( m a) standby v dd current max. ( m a) package cycle hardware sid read function w49l102q - 70 70 25 50 (cmos) 40 - pin stsop (10 mm 14 mm) 10k y w49l102q - 90 90 25 50 (cmos) 40 - pin stsop (10 mm 14 mm) 10k y w49l102q - 12 120 25 50 (cmos) 40 - pin stsop (10 mm 14 mm) 10k y w49l102p - 70 70 25 50 (cmos) 44 - pin plcc 10k y w49l102p - 90 90 25 50 (cmos) 44 - pin plcc 10k y w49l102p - 12 120 25 50 (cmos) 44 - pin plcc 10k y not es: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a co nsequence of product failure. 3. in hardware sid read column: y = with sid read function; n = without sid read function. how to read the top marking example: the top marking of 44 - pin plcc w49l102 1 st line: winbond logo 2 nd line: the part number: w49l102 3 rd line: the lot number 4 th line: the tracking code: 149 o b sa 149: packages made in ?01, week 49 o: assembly house id: a means ase, o means ose, ...etc. b: ic revision; a means version a, h means version h, ?etc. sa: process code w49l102p - 70 2138977a - a12 149obsa
w49l102 - 20 - package dimensions 44 - pin plcc 44 40 39 29 28 18 17 7 6 1 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar 1. dimension d & e do not include interlead flash. 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.51 3.68 0.66 0.41 0.20 16.46 14.99 17.27 2.29 3.81 0.71 0.46 0.25 16.59 15.49 17.53 2.54 1.27 4.70 3.94 0.81 0.56 0.36 16.71 16.00 17.78 2.79 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680 q 40 - pin stsop (10 mm 14 mm) a a a 2 1 l l 1 y c e h d d b e m 0.10(0.004) 1 q dimension in mm dimension in inches min. nom. max. symbol a d e e l l y 1 1 a h d controlling dimension: millimeters 0.05 12.30 9.90 13.80 0.50 0.00 0 12.40 10 14.00 0.50 0.60 0.8 3 1.20 0.15 12.50 10.10 14.20 0.70 0.10 5 0.047 0.006 a 2 1.00 0.95 1.05 0.041 0.039 0.037 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.10 0.15 0.20 0.004 0.006 0.008 0.484 0.488 0.492 0.390 0.394 0.398 0.543 0.551 0.559 0.020 0.020 0.024 0.028 0.031 0.000 0.004 0 3 5 0.002 min. nom. max. q
w49l102 publication release date: february 19, 2002 - 21 - revision a4 version history version date page description a1 june 1999 - renamed from w29n102c a2 ja n. 2001 4, 5, 9 change device code from bf to 2f 1, 12, 13, 14, 19 delete 55 ns 1, 19 endurance: 10k cycles 13 change word programming time (t bp ) as 50 m s (typ.) and 60 m s (max.) 1, 12, 13, 14, 19 add in 120 ns a3 feb. 2001 4, 19 add in hardwa re sid read function note 19 correct part no. in ordering information a4 feb. 19, 2002 1, 2, 19, 21 rename tsop (10 x 14 mm) as stsop (10 x 14 mm) 4 modify v dd power up/down detection in hardware data protection 6, 7, 8 delete old flow chart and add embedded algorithm 19 add how to read the top marking 19 remove part. no of w49l102q - 70n & w49l102p - 70n for ordering information headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu chiu, taipei, 114, taiwan, r.o.c.

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