6/98 block diagram control boost pwm to 0.99 power factor limit line current distortion to <5% world-wide operation without switches feed-forward line regulation average current-mode control low noise sensitivity low start-up supply current fixed-frequency pwm drive low-offset analog multiplier/divider 1a totem-pole gate driver precision voltage reference the uc1854 provides active power factor correction for power sys- tems that otherwise would draw non-sinusoidal current from sinusoi- dal power lines. this device implements all the control functions necessary to build a power supply capable of optimally using available power-line current while minimizing line-current distortion. to do this, the uc1854 contains a voltage amplifier, an analog multiplier/divider, a current amplifier, and a fixed-frequency pwm. in addition, the uc1854 contains a power mosfet compatible gate driver, 7.5v ref- erence, line anticipator, load-enable comparator, low-supply detector, and over-current comparator. the uc1854 uses average current-mode control to accomplish fixed- frequency current control with stability and low distortion. unlike peak current-mode, average current control accurately maintains sinusoidal line current without slope compensation and with minimal response to noise transients. the uc1854s high reference voltage and high oscillator amplitude minimize noise sensitivity while fast pwm elements permit chopping frequencies above 200khz. the uc1854 can be used in single and three phase systems with line voltages that vary from 75 to 275 volts and line frequencies across the 50hz to 400hz range. to reduce the burden on the circuitry that supplies power to this device, the uc1854 features low starting supply current. these devices are available packaged in 16-pin plastic and ceramic dual in-line packages, and a variety of surface-mount packages. uc1854 uc2854 uc3854 high power factor preregulator features description udg-92055
supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35v gt drv current, continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5a gt drv current, 50% duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . 1.5a input voltage, v sense , v rms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11v input voltage, i sense , mult out . . . . . . . . . . . . . . . . . . . . . . . . . . . 11v input voltage, pklmt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v input current, r set , i ac , pklmt, ena . . . . . . . . . . . . . . . . . . . 10ma power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1w storage temperature . . . . . . . . . . . . . . . . . . . . C65 o c to +150 o c lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . +300 o c absolute maximum ratings package pin function function pin n/c 1 gnd 2 pklmt 3 ca out 4 i sense 5 n/c 6 mult out 7 i ac 8 va out 9 v rms 10 n/c 11 v ref 12 ena 13 v sense 14 r set 15 n/c 16 ss 17 c t 18 v cc 19 gt drv 20 plcc-20 & lcc-20 (top view) q & l packages connection diagrams dilC16 & soic-16 (top view) j, n & dw packages unless otherwise stated, v cc =18v, r set =15k to ground, c t =1.5nf to ground, pklmt=1v, ena=7.5v, v rms =1.5v, i ac =100 m a, i sense =0v, ca out=3.5v, va out=5v, v sense =7.5v, no load on ss, ca out, va out, ref, gt drv, C55 o c parameter test conditions min typ max units current amplifier current amp offset voltage C4 4 mv i sense bias current C500 C120 500 na input range, i sense , mult out C0.3 to 2.5 v current amp gain 80 110 db current amp output swing 0.5 to 16 v current amp short circuit current ca out=0v C36 C20 C5 ma current amp gain-bw product t a =25 o c (note 6) 400 800 khz reference reference output voltage i ref =0ma, t a =25 o c 7.4 7.5 7.6 v i ref =0ma, over temp. 7.35 7.5 7.65 v v ref load regulation C10ma gnd (pin 1) (ground): all voltages are measured with re- spect to gnd. v cc and ref should be bypassed directly to gnd with an 0.1 m f or larger ceramic capacitor. the tim- ing capacitor discharge current also returns to this pin, so the lead from the oscillator timing capacitor to gnd should also be as short and as direct as possible. pklmt (pin 2) (peak limit): the threshold for pklmt is 0.0v. connect this input to the negative voltage on the current sense resistor as shown in figure 1. use a resis- tor to ref to offset the negative current sense signal up to gnd. ca out (pin 3) (current amplifier output): this is the out- put of a wide-bandwidth op amp that senses line current and commands the pulse width modulator (pwm) to force the correct current. this output can swing close to gnd, allowing the pwm to force zero duty cycle when neces- sary. the current amplifier will remain active even if the ic is disabled. the current amplifier output stage is an npn emitter follower pull-up and an 8k resistor to ground. i sense (pin 4) (current sense minus): this is the inverting input to the current amplifier. this input and the non-in- verting input mult out remain functional down to and be- low gnd. care should be taken to avoid taking these inputs below C0.5v, because they are protected with di- odes to gnd. mult out (pin 5) (multiplier output and current sense plus): the output of the analog multiplier and the non-in- verting input of the current amplifier are connected to- gether at mult out. the cautions about taking i sense below C0.5v also apply to mult out. as the multiplier out- put is a current, this is a high impedance input similar to i sense , so the current amplifier can be configured as a differential amplifier to reject gnd noise. figure 1 shows an example of using the current amplifier differentially. i ac (pin 6) (input ac current): this input to the analog multiplier is a current. the multiplier is tailored for very low distortion from this current input (i ac ) to mult out, so this is the only multiplier input that should be used for sensing instantaneous line voltage. the nominal voltage on i ac is 6v, so in addition to a resistor from i ac to recti- fied 60hz, connect a resistor from i ac to ref. if the resis- tor to ref is one fourth of the value of the resistor to the rectifier, then the 6v offset will be cancelled, and the line current will have minimal cross-over distortion. va out (pin 7) (voltage amplifier output): this is the out- put of the op amp that regulates output voltage. like the current amplifier, the voltage amplifier will stay active even if the ic is disabled with either ena or v cc . this means that large feedback capacitors across the amplifier will stay charged through momentary disable cycles. volt- age amplifier output levels below 1v will inhibit multiplier output. the voltage amplifier output is internally limited to approximately 5.8v to prevent overshoot. the voltage amplifier output stage is an npn emitter follower pull-up and an 8k resistor to ground. v rms (pin 8) (rms line voltage): the output of a boost pwm is proportional to the input voltage, so when the line voltage into a low-bandwidth boost pwm voltage regula- tor changes, the output will change immediately and slowly recover to the regulated level. for these devices, the v rms input compensates for line voltage changes if it is connected to a voltage proportional to the rms input line voltage. for best control, the v rms voltage should stay between 1.5v and 3.5v. ref (pin 9) (voltage reference output): ref is the output of an accurate 7.5v voltage reference. this output is ca- pable of delivering 10ma to peripheral circuitry and is in- ternally short circuit current limited. ref is disabled and will remain at 0v when v cc is low or when ena is low. bypass ref to gnd with an 0.1 m f or larger ceramic ca- pacitor for best stability. ena (pin 10) (enable): ena is a logic input that will en- able the pwm output, voltage reference, and oscillator. ena also will release the soft start clamp, allowing ss to rise. when unused, connect ena to a +5v supply or pull ena high with a 22k resistor. the ena pin is not intended to be used as a high speed shutdown to the pwm output. v sense (pin 11) (voltage amplifier inverting input): this is normally connected to a feedback network and to the boost converter output through a divider network. r set (pin 12) (oscillator charging current and multiplier limit set): a resistor from r set to ground will program os- cillator charging current and maximum multiplier output. multiplier output current will not exceed 3.75v divided by the resistor from r set to ground. ss (pin 13) (soft start): ss will remain at gnd as long as the ic is disabled or v cc is too low. ss will pull up to over 8v by an internal 14 m a current source when both v cc be- comes valid and the ic is enabled. ss will act as the ref- erence input to the voltage amplifier if ss is below ref. with a large capacitor from ss to gnd, the reference to the voltage regulating amplifier will rise slowly, and in- crease the pwm duty cycle slowly. in the event of a dis- able command or a supply dropout, ss will quickly discharge to ground and disable the pwm. c t (pin 14) (oscillator timing capacitor): a capacitor from c t to gnd will set the pwm oscillator frequency accord- ing to this relationship: f = 1.25 r set c t v cc (pin 15) (positive supply voltage): connect v cc to a stable source of at least 20ma above 17v for normal op- eration. also bypass v cc directly to gnd to absorb supply current spikes required to charge external mosfet gate capacitances. to prevent inadequate gt drv signals, these devices will be inhibited unless v cc exceeds the upper under-voltage lockout threshold and remains above the lower threshold. pin descriptions (pin numbers refer to dil packages) uc1854 uc2854 uc3854 4
gt drv (pin 16) (gate drive): the output of the pwm is a totem pole mosfet gate driver on gt drv. this output is internally clamped to 15v so that the ic can be operated with v cc as high as 35v. use a series gate resistor of at least 5 ohms to prevent interaction between the gate im- pedance and the gt drv output driver that might cause the gt drv output to overshoot excessively. some over- shoot of the gt drv output is always expected when driv- ing a capacitive load. typical characteristics at t a = t j = 25 c uc1854 uc2854 uc3854 load capacitance, m f ns 0 100 200 300 400 500 600 700 0 0.01 0.02 0.03 0.04 0.05 rise time fall time r set , k w duty cycle 70% 75% 80% 85% 90% 95% 100% 1 10 100 i,a ac m multiplier output m a 0 100 200 300 400 500 600 0 100 200 300 400 500 600 700 800 mult out=1 mult out=2v mult out=3v mult out=0v v =2v, va out=5v rms r,k set w frequency khz 10 100 1000 1 10 100 100pf 200pf 5nf 10nf 3nf 500pf 2nf 1nf frequency khz phase margin degrees open-loop gain db -20 0 20 40 60 80 100 120 0.1 1 10 100 1000 10000 frequency khz phase margin degrees open-loop gain db -20 0 20 40 60 80 100 120 0.1 1 10 100 1000 10000 pin descriptions (cont.) voltage amplifier gain and phase vs frequency current amplifier gain and phase vs frequency gate drive rise and fall time gate drive maximum duty cycle multiplier output vs voltage on mult oscillator frequency vs r set and c t 5
typical characteristics at t a = t j = 25 o c (cont.) uc1854 uc2854 uc3854 i ac , m a mult out m a 0 100 200 300 400 500 600 0 100 200 300 400 500 v rms =1.5v va out=1.25v va out=2.5v va out=3.5v i ac , m a mult out m a 0 50 100 150 200 250 0 100 200 300 400 500 v rms =3v va out=1.25v va out=2v va out=3v va out=5v i ac , m a mult out, m a 0 20 40 60 80 100 120 140 0 100 200 300 400 500 v rms =5v va out=5v va out=1.5v va out=3v i ac , m a mult out m a 0 20 40 60 80 100 120 140 160 0 100 200 300 400 500 v rms =4v va out=1.25v va out=2v va out=3v va out=4v va out=5v multiplier output vs multiplier inputs with mult out=0v applications information a 250w preregulator the circuit of figure 1 shows a typical application of the uc3854 as a preregulator with high power factor and effi- ciency. the assembly consists of two distinct parts, the control circuit centering on the uc3854 and the power section. the power section is a "boost" converter, with the induc- tor operating in the continuous mode. in this mode, the duty cycle is dependent on the ratio between input and output voltages; also, the input current has low switching frequency ripple, which means that the line noise is low. furthermore, the output voltage must be higher than the peak value of the highest expected ac line voltage, and all components must be rated accordingly. in the control section, the uc3854 provides pwm pulses (gt drv, pin 16) to the power mosfet gate. the duty cycle of this output is simultaneously controlled by four separate inputs to the chip: input pin # function v sense ........................ 11 .......... output dc voltage i ac .................................6 .......... linevoltage waveform i sense /mult out .........4/5 .......... line current v rms .............................8 .......... rms line voltage additional controls of an auxiliary nature are provided. they are intended to protect the switching power mos- fets from certain transient conditions, as follows: input pin # function ena ............................10 .......... start-up delay ss ...............................13 .......... soft start pklim...........................2 .......... maximum current limit 6
uc1854 uc2854 uc3854 protection inputs ena (enable): the ena input must reach 2.5 volts be- fore the ref and gt drv outputs are enabled. this pro- vides a means to shut down the gate in case of trouble, or to add a time delay at power up. a hysteresis gap of 200mv is provided at this terminal to prevent erratic op- eration. undervoltage protection is provided directly at pin 15, where the on/off thresholds are 16v and 10v. if the ena input is unused, it should be pulled up to v cc through a current limiting resistor of 100k. ss (soft start): the voltage at pin 13 (ss) can reduce the reference voltage used by the error amplifier to regu- late the output dc voltage. with pin 13 open, the refer- ence voltage is typically 7.5v. an internal current source delivers approximately -14 m a from pin 13. thus a capaci- tor connected between that pin and ground will charge linearly from zero to 7.5v in 0.54c seconds, with c ex- pressed in microfarads. pklim (peak current limit): use pin 2 to establish the highest value of current to be controlled by the power mosfet. with the resistor divider values shown in figure 1, the 0.0v threshold at pin 2 is reached when the voltage drop across the 0.25 ohm current sense resistor is 7.5v*2k/10k=1.5v, corresponding to 6a. a bypass capaci- tor from pin 2 to ground is recommended to filter out very high frequency noise. control inputs v sense (output dc voltage sense): the threshold voltage for the v sense input is 7.5v and the input bias current is typically 50na. the values shown in figure 1 are for an output voltage of 400v dc. in this circuit, the voltage am- plifier operates with a constant low frequency gain for minimum output excursions. the 47nf feedback capacitor places a 15hz pole in the voltage loop that prevents 120hz ripple from propagating to the input current. i ac (line waveform): in order to force the line current waveshape to follow the line voltage, a sample of the power line voltage in waveform is introduced at pin 6. this signal is multiplied by the output of the voltage amplifier in the internal multiplier to generate a reference signal for the current control loop. this input is not a voltage, but a current (hence i ac ). it is set up by the 220k and 910k resistive divider (see figure 1). the voltage at pin 6 is internally held at 6v, and the two resistors are chosen so that the current flowing into pin 6 varies from zero (at each zero crossing) to about 400 m a at the peak of the waveshape. the following for- mulas were used to calculate these resistors: r ac = v pk i acpk = 260 vac ? `` 2 400 m a = 910 k r ref = r ac 4 = 220 k (where vpk is the peak line voltage) i sense /mult out (line current): the voltage drop across the 0.25 ohm current-sense resistor is applied to pins 4 and 5 as shown. the current-sense amplifier also oper- ates with high low-frequency gain, but unlike the voltage amplifier, it is set up to give the current-control loop a very wide bandwidth. this enables the line current to follow the line voltage as closely as possible. in the present exam- ple, this amplifier has a zero at about 500hz, and a gain of about 18db thereafter. v rms (rms line voltage) : an important feature of the uc3854 preregulator is that it can operate with a three-to- one range of input line voltages, covering everything from low line in the us (85vac) to high line in europe (255vac). this is done using line feedforward, which keeps the input power constant with varying input voltage (assuming constant load power). to do this, the multiplier divides the line current by the square of the rms value of the line voltage. the voltage applied to pin 8, proportional to the average of the rectified line voltage (and propor- tional to the rms value), is squared in the uc3854, and then used as a divisor by the multiplier block. the multi- plier output, at pin 5, is a current that increases with the current at pin 6 and the voltage at pins 7, and decreases with the square of the voltage at pin 8. pwm frequency: the pwm oscillator frequency in figure 1 is 100khz. this value is determined by c t at pin 14 and r set at pin 12. r set should be chosen first be- cause it affects the maximum value of i mult according to the equation: i mult max = - 3.75 v r set this effectively sets a maximum pwm-controlled current. with r set =15k, i mult max = - 3.75 v 15 k = - 250 m a also note that the multiplier output current will never ex- ceed twice i ac . with the 4k resistor from mult out to the 0.25 ohm current sense resistor, the maximum current in the current sense resistor will be i max = - i mult max 4 k 0.25 w = - 4 a having thus selected r set , the current sense resistor, and the resistor from mult out to the current sense resis- tor, calculate c t for the desired pwm oscillator frequency from the equation c t = 1.25 f r set applications information (cont.) 7
figure 1 - typical application note: boost inductor can be fabricated with arnold mpp toroidal core part number a-438381-2, using a 55 turn primary and a 13 turn secondary. unitrode corporation 7 continental blvd. merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 these products contain patented circuitry and are sold under license from pioneer magnetics, inc. this diagram depicts a complete 250 watt preregulator. at full load, this preregulator will exhibit a power factor of 0.99 at any power line voltage between 80 and 260 v rms . this same circuit can be used at higher power levels with minor modifications to the power stage. see design note 39b and application note u-134 for further details. uc1854 uc2854 uc3854 udg -92056-1 8
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated
|
