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vishay siliconix dg3408/3409 document number: 72858 s-70853-rev. d, 30-apr-07 www.vishay.com 1 precision 8-ch/dual 4-ch lo w voltage analog multiplexers features ? 2.7 to 12 v single supply or 3 to 6 v dual supply operation ? low on-resistance-r on : 3.9 typ. ? fast switching: t on - 42 ns, t off - 24 ns ? break-before-make guaranteed ? low leakage ? ttl, cmos, lv logic (3 v) compatible ? 2000 v esd protection (hbm) ? micro foot ? package ? lead (pb)-free solder bumps benefits ? high accuracy ? single and dual power rail capacity ? wide operating voltage range ? simple logic interface applications ? data acquisition systems ? battery operated equipment ? portable test equipment ? sample and hold circuits ? communication systems ?sdsl, dslam ? audio and video signal routing description the dg3408/3409 uses bicm os wafer fabrication technology that allows the dg3408/3409 to operate on sin- gle and dual supplies. single supply voltage ranges from 3 to 12 v while dual supply operation is recommended with 3 to 6 v. the dg3408 is an 8-channel single-ended analog multiplexer designed to connect one of eight inputs to a common output as determined by a 3-bit binary address (a 0 , a 1 , a 2 ). the dg3409 is a dual 4-channel differential analog multiplexer designed to connect one of four differential inputs to a common dual output as determined by its 2-bit binary address (a 0 , a 1 ). break-before-make switching action to protect against momentary crosstalk between adjacent channels. functional block diagram and pin configuration dg3409 micro foot 16-bump s 4a s 3a s 1a decoder/driver s 2a s 4b s 3b s 1b s 2b d b a 1 a 0 en gnd v+ v- d a xxx 3409 a1 locator device marking: 3409 xxx = data/lot traceabiliity code gnd s 1a en v+ v- a 1 a 0 d a 1 a 234 b c d top view s 2a s 3a s 4a d b s 1b s 2b s 3b s 4b dg3408 micro foot 16-bump s 4 s 3 s 1 decoder/driver s 2 s 8 s 7 s 5 s 6 d a 1 a 2 a 0 en gnd v+ v- xxx 3408 a1 locator device marking: 3408 xxx = data/lot traceabiliity code gnd s 5 s 6 s 7 s 8 s 1 s 2 s 3 s 4 en v+ v- a 1 a 2 a 0 d 1 a 234 b c d top view rohs compliant
www.vishay.com 2 document number: 72858 s-70853-rev. d, 30-apr-07 vishay siliconix dg3408/3409 truth tables and ordering information x = do not care for low and high voltage levels for v ax and v en consult "digital control" parameters for specific v+ operation. see specifications tables for: single supply 12 v dual supply v+ = 5 v, v- = - 5 v single supply 5 v single supply 3 v notes: a. signals on s x , d x or in x exceeding v+ or v- will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. refer to ipc/jedec (j-std-020b). c. all bumps soldered or welded to pc board. d. derate 9.0 mw/c above 70 c. truth table - dg3408 a 2 a 1 a 0 en on switch x x x 1 none 00 0 0 1 00 1 0 2 01 0 0 3 01 1 0 4 10 0 0 5 10 1 0 6 11 0 0 7 11 1 0 8 truth table - dg3409 a 1 a 0 en on switch x x 1 none 00 0 1 01 0 2 10 0 3 11 0 4 ordering information - dg3408 temperature range package part number - 40 to 85 c micro foot: 16-bump (4 x 4, 0.5 mm pitch, 238 m bump height) dg3408db-t2-e1 (lead (pb)-free) ordering information - dg3409 temperature range package part number - 40 to 85 c micro foot: 16-bump (4 x 4, 0.5 mm pitch, 238 m bump height) DG3409DB-T2-E1 (lead (pb)-free) absolute maximum ratings t a = 25 c, unless otherwise noted parameter limit unit voltage referenced v+ to v- 14 v gnd 7 digital inputs a , v s , v d (v-) - 0.3 v to (v) + 0.3 v current (any terminal except s or d) 30 ma continuous current, s or d) 100 peak current, s or d (pulsed at 1 ms, 10 % duty cycle max) 200 package solder reflow conditions b ir/convection 250 c storage temperature - 65 to 150 power dissipation (package) c , (t a = 70 c) 16-bump (4 x 4 mm) micro foot d 719 mw
document number: 72858 s-70853-rev. d, 30-apr-07 www.vishay.com 3 vishay siliconix dg3408/3409 specifications (single supply 12 v) parameter symbol test conditions unless otherwise specified v+ = 12 v, 10 % , v- = 0 v v a , v en = 0.8 v or 2.4 v f temp b limits - 40 to 85 c unit min c typ d max c analog switch analog signal range e v analog full 0 12 v on-resistance r on v+ = 10.8 v, v d = 2 v or 9 v, i s = 50 ma sequence each switch on room full 47 7.5 r on match between channels g r on v+ = 10.8 v, v d = 2 v or 9 v, i s = 50 ma room 3.6 on-resistance flatness i r on flatness room 8 switch off leakage current i s(off) v en = 2.4 v, v d = 11 v or 1 v, v s = 1 v or 11 v room full - 2 - 20 2 20 na i d(off) room full - 2 - 20 2 20 channel on leakage current i d(on) v en = 0 v, v s = v d = 1 v or 11 v room full - 2 - 20 2 20 digital control logic high input voltage v inh full 2.4 v logic low input voltage v inl full 0.8 input current i in v ax = v en = 2.4 v or 0.8 v full - 1 1 a dynamic characteristics transition time t trans v s1 = 8 v, v s8 = 0 v, (dg3408) v s1b = 8 v, v s4b = 0 v, (dg3409) see figure 2 room full 42 71 75 ns break-before-make time t bbm v s(all) = v da = 5 v see figure 4 room full 224 enable turn-on time t on(en ) v ax = 0 v, v s1 = 5 v (dg3408) v ax = 0 v, v s1b = 5 v (dg3409) see figure 3 room full 42 70 75 enable turn-off time t off(en ) room full 24 44 46 charge injection e q c l = 1 nf, v gen = 0 v, r gen = 0 room 29 pc off isolation e, h oirr f = 100 khz, r l = 1 k room - 80 db crosstalk e x ta l k room - 85 source off capacitance e c s(off) f = 1 mhz, v s = 0 v, v en = 2.4 v dg3408 room 21 pf dg3409 room 23 drain off capacitance e c d(off) f = 1 mhz, v d = 0 v, v en = 2.4 v dg3408 room 211 dg3409 room 112 drain on capacitance e c d(on) f = 1 mhz, v d = 0 v, v en = 0 v dg3408 room 238 dg3409 room 137 power supplies power supply current i+ v en = v a = 0 v or v+ room 1.0 a
www.vishay.com 4 document number: 72858 s-70853-rev. d, 30-apr-07 vishay siliconix dg3408/3409 specifications (dual supply v+ = 5 v, v- = - 5 v) parameter symbol test conditions unless otherwise specified v+ = 5 v, v- = - 5 v , 10 % v a , v en = 0.8 v or 2.0 v f temp b limits - 40 to 85 c unit min c typ d max c analog switch analog signal range e v analog full - 5 5 v on-resistance r on v+ = 4.5 v, v- = - 4.5 v, v d = 3.5 v, i s = 50 ma, sequence each switch on room full 58 8.5 r on match between channels g r on v+ = 4.5 v, v- = - 4.5 v, v d = 3.5 v, i s = 50 ma room 3.6 on-resistance flatness i r on flatness room 8.2 switch off leakage current a i s(off) v+ = 5.5, v- = - 5.5 v v en = 2.4 v, v d = 4.5 v, v s = 4.5 v room full - 2 - 20 2 20 na i d(off) room full - 2 - 20 2 20 channel on leakage current a i d(on) v+ = 5.5 v, v- = - 5.5 v v en = 0 v, v d = 4.5 v, v s = 4.5 v room full - 2 - 20 2 20 digital control logic high input voltage v inh full 2.0 v logic low input voltage v inl full 0.8 input current a i in v ax = v en = 2.0 v or 0.8 v full - 1 1 a dynamic characteristics transition time e t trans v s1 = 3.5 v, v s8 = - 3.5 v, (dg3408) v s1b = 3.5 v, v s4b = - 3.5 v, (dg3409) see figure 2 room full 68 89 94 ns break-before-make time e t bbm v s(all) = v da = 3.5 v see figure 4 room full 116 enable turn-on time e t on(en ) v ax = 0 v, v s1 = 3.5 v (dg3408) v ax = 0 v, v s1b = 3.5 v (dg3409) see figure 3 room full 68 88 94 enable turn-off time e t off(en ) room full 58 78 81 source off capacitance e c s(off) f = 1 mhz, v s = 0 v, v en = 2.0 v dg3408 room 23 pf dg3409 room 23 drain off capacitance e c d(off) f = 1 mhz, v d = 0 v, v en = 2.0 v dg3408 room 223 dg3409 room 113 drain on capacitance e c d(on) f = 1 mhz, v d = 0 v, v en = 0 v dg3408 room 246 dg3409 room 137 power supplies power supply current i+ v en = v a = 0 v or v+ room 1.0 a i- room - 1.0
document number: 72858 s-70853-rev. d, 30-apr-07 www.vishay.com 5 vishay siliconix dg3408/3409 specifications (single supply 5 v) parameter symbol test conditions unless otherwise specified v+ = 5 v, 10 %, v- = 0 v v a , v en = 0.8 v or 2.0 v f temp b limits - 40 to 85 c unit min c typ d max c analog switch analog signal range e v analog full 0 5 v on-resistance r on v+ = 4.5 v, v d or v s = 1 v or 3.5 v, i s = 50 ma room full 7 10.5 11 r on match between channels g r on v+ = 4.5 v, v d = 1 v or 3.5 v, i s = 50 ma room 3.6 on-resistance flatness i r on flatness room 9 switch off leakage current a i s(off) v+ = 5.5 v v s = 1 v or 4 v, v d = 4 v or 1 v room full - 2 - 20 2 20 na i d(off) room full - 2 - 20 2 20 channel on leakage current a i d(on) v+ = 5.5 v v d = v s = 1 v or 4 v, sequence each switch on room full - 2 - 20 2 20 digital control logic high input voltage v inh v+ = 5 v full 2.0 v logic low input voltage v inl full 0.8 input current a i in v ax = v en = 2.0 v or 0.8 v full - 1 1 a dynamic characteristics transition time e t trans v s1 = 3.5 v, v s8 = 0 v, (dg3408) v s1b = 3.5 v, v s4b = 0 v, (dg3409) see figure 2 room full 73 94 104 ns break-before-make time e t open v s(all) = v da = 3.5 v see figure 4 room full 229 enable turn-on time e t on(en ) v ax = 0 v, v s1 = 3.5 v (dg3408) v ax = 0 v, v s1b = 3.5 v (dg3409) see figure 3 room full 74 94 104 enable turn-off time e t off(en ) room full 38 57 61 charge injection e q c l = 1 nf, r gen = 0 , v gen = 0 v room 20 pc off isolation e, h oirr r l = 1 k , f = 100 khz room - 81 db crosstalk e x ta l k room - 85 source off capacitance e c s(off) f = 1 mhz, v s = 0 v, v en = 0 v dg3408 room 22 pf dg3409 room 24 drain off capacitance e c d(off) f = 1 mhz, v d = 0 v, v en = 2.0 v dg3408 room 223 dg3409 room 113 drain on capacitance e c d(on) f = 1 mhz, v d = 0 v, v en = 0 v dg3408 room 244 dg3409 room 143 power supplies power supply current i+ v en = v a = 0 v or v+ room 1.0 a
www.vishay.com 6 document number: 72858 s-70853-rev. d, 30-apr-07 vishay siliconix dg3408/3409 notes: a. leakage parameters are guaranteed by worst case test condition and not subject to production test. b. room = 25 c, full = as determin ed by the operating temperature suffix. c. the algebraic convention whereby the most negative value is a minimum and the most po sitive a maximum, is used in this data sheet. d. typical values are for design aid only, not guaranteed nor subject to production testing. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. g. r don = r don max - r don min. h. worst case isolation occurs on c hannel 4 due to proximity to the drain pin. i. r don flatness is measured as the difference between the minimum and maximum measured values across a defined analog signal. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (single supply 3 v) parameter symbol test conditions unless otherwise specified v+ = 3 v, 10 % , v- = 0 v v en = 0.4 v or 1.8 v f temp b limits - 40 to 85 c unit min c typ d max c analog switch analog signal range e v analog full 0 3 v on-resistance r on v+ = 2.7 v, v d = 0.5 or 2.2 v, i s = 5 ma room full 12 25.5 26.5 r on match between channels g r on v+ = 2.7 v, v d = 0.5 v or 2.2 v, i s = 5 ma room 3.6 on-resistance flatness i r on flatness room 13 switch off leakage current a i s(off) v+ = 3.3 v v s = 2 or 1 v, v d = 1 or 2 v room full - 2 - 20 2 20 na i d(off) room full - 2 - 20 2 20 channel on leakage current a i d(on) v+ = 3.3 v v d = v s = 1 or 2 v, sequence each switch on room full - 2 - 20 2 20 digital control logic high input voltage v inh full 1.8 v logic low input voltage v inl full 0.4 input current a i in v ax = v en = 1.8 v or 0.4 v full - 1 1 a dynamic characteristics transition time t trans v s1 = 1.5 v, v s8 = 0 v, (dg3408) v s1b = 1.5 v, v s4b = 0 v, (dg3409) see figure 2 room full 140 165 182 ns break-before-make time t bbm v s(all) = v da = 1.5 v see figure 4 room full 263 enable turn-on time t on(en ) v ax = 0 v, v s1 = 1.5 v (dg3408) v ax = 0 v, v s1b = 1.5 v (dg3409) see figure 3 room full 140 162 178 enable turn-off time t off(en ) room full 76 97 104 charge injection e q c l = 1 nf, r gen = 0, v gen = 0 v room 7 pc off isolation e, h oirr f = 100 khz, r l = 1 k room - 81 db crosstalk e x ta l k room - 85 source off capacitance e c s(off) f = 1 mhz, v s = 0 v, v en = 1.8 v dg3408 room 23 pf dg3409 room 25 drain off capacitance e c d(off) f = 1 mhz, v d = 0 v, v en = 1.8 v dg3408 room 230 dg3409 room 120 drain on capacitance e c d(on) f = 1 mhz, v d = 0 v, v en = 0 v dg3408 room 256 dg3409 room 147 power supplies power supply current i+ v en = v a = 0 v or v+ room 1.0 a
document number: 72858 s-70853-rev. d, 30-apr-07 www.vishay.com 7 vishay siliconix dg3408/3409 typical characteristics 25 c, unless otherwise noted r on vs. v com and single supply voltage r on vs. analog voltage and temperature leakage current vs. analog voltage 0 2 4 6 8 10 12 14 16 036912 v+ = 3.0 v i s = 5 ma v com - analog voltage (v) - on-resistance ( ) r on t = 25 c v+ = 5.0 v i s = 50 ma v+ = 12.0 v i s = 50 ma 0 2 4 6 8 10 12 -5 -3 - 1 1 3 5 v = 5 v i s = 50 ma v com - analog voltage (v) - on-resistance ( ) r on a = 85 c b = 25 c c = - 40 c a b c - 500 - 400 - 300 - 200 - 100 0 100 024681012 v com , v no , v nc - analog voltage leakage current (pa) v+ = 12 v v- = 0 v i com(on) i no(off) /i nc(off) i com(off) r on vs. analog voltage and temperature supply current vs. temperature leakage current vs. analog voltage 0 2 4 6 8 10 12 14 16 024681012 a b c a = 85 c b = 25 c c = - 40 c - on-resistance ( ) r on v com - analog voltage (v) v+ = 12.0 v i s = 50 ma a b c v+ = 5.0 v i s = 50 ma a b c v+ = 3.0 v i s = 5 ma 1 10 100 1000 10000 - 60 - 40 - 20 0 20 40 60 80 100 temperature ( c) i+ - supply current (pa) v ax , v en = 0 v v+ = 5 v v- = - 5 v v+ = 12 v v- = 0 v - 120 - 100 -80 -60 -40 -20 0 20 -5 -3 -1 1 3 5 v com , v no , v nc - analog voltage leakage current (pa) v+ = 5 v v- = - 5 v i com(on) i no(off) /i nc(off) i com(off)
www.vishay.com 8 document number: 72858 s-70853-rev. d, 30-apr-07 vishay siliconix dg3408/3409 typical characteristics 25 c, unless otherwise noted switching time vs. temperature and single supply voltage leakage current vs. temperature insertion loss, off isolation and crosstalk vs. frequency (dg3408) 0 20 40 60 80 100 120 140 160 - 60 - 40 - 20 0 20 40 60 80 100 t on v+ = 3 v t off v+ = 3 v temperature ( c) t on v+ = 5 v t on v+ = 12 v t off v+ = 5 v t off v+ = 12 v - 60 - 40 - 20 0 20 40 60 80 100 10000 100 1 v+ = 5 v v- = - 5 v leakage current (pa) i com(on) temperature ( c) 10 i com(off) 1000 i no(off) , i nc(off) 100 k -90 1 m -20 10 -50 -40 100 m 1 g frequency (hz) -70 oirr crosstalk insertion loss 10 m 0 -80 -60 -30 -10 v+ = 12 v v- = 0 v r l = 50 (db) loss, oirr, x talk transition time vs. temperature and single supply voltage switching threshold vs. supply voltage insertion loss, off isolation and crosstalk vs. frequency (dg3409) 0 30 60 90 120 150 180 - 60 - 40 - 20 0 20 40 60 80 100 temperature ( c) transistion time (ns) t trans+ v+ = 3 v t trans - v+ = 5 v t trans+ v+ = 5 v t trans - v+ = 3 v t trans - v+ = 12 v t trans+ v+ = 12 v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 2468101214 v+ - supply voltage (v) - switching threshold (v) v t 90 100 k - 1 m -20 10 -50 -40 100 m 1 g frequency (hz) -70 crosstalk 10 m 0 -80 -60 -30 -10 insertion loss oirr v+ = 12 v v- = 0 v r l = 50 (db) loss, oirr, x talk
document number: 72858 s-70853-rev. d, 30-apr-07 www.vishay.com 9 vishay siliconix dg3408/3409 typical characteristics 25 c, unless otherwise noted schematic diagram (typical channel) supply current vs. input switching frequency input switching frequency (hz) i+ - supply current (a) v+ = 5 v v- = - 5 v 100 m 10 m 1 m 100 10 1 100 n 10 n 1 n 10 100 1 k 10 k 100 k 1 m 10 m figure 1. en a 0 s 1 d v+ s n v- decode/ drive level shift v- v+ a x v+ gnd
www.vishay.com 10 document number: 72858 s-70853-rev. d, 30-apr-07 vishay siliconix dg3408/3409 test circuits figure 2. transition time a 1 a 0 a 2 a 1 a 0 v+ v- v+ v- gnd d 35 pf v o s 1 s 2 - s 7 s 8 50 300 v s8 v s1 v+ v- v+ v- gnd 35 pf v o s 1b s 1a - s 4a , d a s 4b 300 d b logic input switch output v s8 v o t trans t r < 5 ns t f < 5 ns s 8 on (dg3408) or s 4 on (dg3409) s 1 on t trans 50 % v s1 50 % 90 % 90 % 3 v 0 v dg3408 dg3409 v s4b v s1b v ax 50 en en return to specifications: single supply 12 v dual supply v+ = 5 v, v- = - 5 v single supply 5 v single supply 3 v figure 3. enable switching time logic input switch output v o t r < 5 ns t f < 5 ns 3 v 0 v 0 v t on(en ) t off(en ) 50 % 90 % 90 % v o s 1 s 2 - s 8 a 0 a 1 a 2 50 300 v o v+ gnd v- d 35 pf v- v+ s 1b s 1a - s 4a , d a s 2b s 4b d b a 0 a 1 50 300 v o v+ gnd v- 35 pf v- dg3408 dg3409 v s1 v+ v s1 en en return to specifications: single supply 12 v dual supply v+ = 5 v, v- = - 5 v single supply 5 v single supply 3 v
document number: 72858 s-70853-rev. d, 30-apr-07 www.vishay.com 11 vishay siliconix dg3408/3409 test circuits figure 4. break-before-make interval 50 % 90 % logic input switch output v o v s t open t r < 5 ns t f < 5 ns 0 v 3 v 0 v v+ gnd v- 35 pf v- a 2 d b , d all s and d a 300 v o 50 a 1 a 0 dg3408 dg3409 v s1 en return to specifications: single supply 12 v dual supply v+ = 5 v, v- = - 5 v single supply 5 v single supply 3 v figure 5. charge injection a 0 a 1 a 2 v o v+ gnd v- d v g r g s x c l 1 nf channel select 3 v 0 v off on logic input switch output v o v o is the measured voltage due to charge transfer error q, when the channel turns off. q = c l x v o off v+ v- en figure 6. off isolation r l 50 v out v+ gnd v- a 2 d a 1 a 0 s 8 s x r g = 50 off isolation = 20 log v out v in v in v+ v- en
www.vishay.com 12 document number: 72858 s-70853-rev. d, 30-apr-07 vishay siliconix dg3408/3409 test circuits figure 7. crosstalk r l 50 v out v+ gnd v- a 2 d a 1 a 0 s 8 s x r g = 50 crosstalk = 20 log v out v in v in s 1 v+ v- en r in 50 figure 8. insertion loss r l 50 a 2 v out d r g = 50 insertion loss = 20 log v out a 1 v in a 0 v in s 1 v+ gnd v- v- v+ en figure 9. source drain capacitance f = 1 mhz s 1 d gnd v+ v- meter hp4192a impedance analyzer or equivalent s 8 a 1 a 2 a 0 channel select v- v+ en
document number: 72858 s-70853-rev. d, 30-apr-07 www.vishay.com 13 vishay siliconix dg3408/3409 package outline micro foot: 16-bump (4 x 4, 0.5 mm pitch, 0.238 mm bump height) notes (unless other wise specified): a. bump is lead free sn/ag/cu. b. non-solder mask defined copper landing pad. c. laser mark on silicon die back; back-lapped, no coat ing. shown is not actual marking; sample only. notes: a. use millimeters as the primary measurement. vishay siliconix maintains worldwide manufac turing capability. products ma y be manufactured at one of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a composite of all qua lified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see http://www.vishay.com/ppg?72858 . index-bump a1 note c top side (die back) xxx 3408 recommended land pattern 0.5 0.5 6 x ? 0.150 ~ 0.229 note b solder mask ? ~ pad diameter + 0.1 bump note a 321 a b e d e a a 2 a 1 s s e silicon c d 4 b diameter e e e e dim millimeters a inches min max min max a 0.688 0.753 0.0271 0.0296 a 1 0.218 0.258 0.0086 0.0102 a 2 0.470 0.495 0.0185 0.0195 b 0.306 0.346 0.0120 0.0136 d 1.980 2.020 0.0780 0.0795 e 1.980 2.020 0.0780 0.0795 e 0.5 basic 0.0197 basic s 0.230 0.270 0.0091 0.0106
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.

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