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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. october 1995 copyright ? intel corporation, 1996 order number: 290421-004 82503 dual serial transceiver (dst) 82503 product feature set overview y single component ethernet * interface to both 802.3 10base-t and aui y automatic or manual port selection y manchester encoder/decoder and clock recovery y no glue interface to industry-standard lan controllers e intel 82586, 82590, 82593 and 82596 e amd 7990 (lance * ) e national semiconductor 8390 and 83932 (sonic * ) e western digital 83c690 e fujitsu 86950 (etherstar * ) y diagnostic loopback y reset, low power modes y network status indicators y defeatable jabber timer y user test modes y 10 mhz transmit clock generator y one micron chmos ** iv (px48) technology y single 5-v supply interface features tpe y complies with 10base-t, ieee std. 802.3i-1990 for twisted pair ethernet y selectable polarity switching y direct interface to tpe analog filters y on-chip tpe squelch y defeatable link integrity (li) y support of cable lengths l 100m aui y complies with ieee 802.3 aui standard y direct interface to aui transformers y on-chip aui squelch a block diagram of a typical application is shown in figure 1. the 82503 dual serial transceiver is a high-inte- gration cmos device designed to simplify interfacing industry standard ethernet lan controllers to ieee 802.3 local area network applications (10base5, 10base2, and 10base-t). the component supports both an attachment unit interface (aui) and a twisted pair ethernet interface (tpe). it allows oems to design a state-of-the-art media interface that is jumperless and fully automatic. the 82503 includes on-chip aui and tpe drivers and receivers; it offers designers a cost-effective, integrated solution for interfacing lan control- lers to the wire medium. ** chmos is a patented process of intel corporation. * ethernet is a registered trademark of xerox corporation. lance is a registered trademark of advanced micro devices. etherstar is a registered trademark of fujitsu electronics. sonic is a registered trademark of national semiconductor corporation.
82503 dual serial transceiver (dst) contents page 1.0 82503 product features 3 2.0 pin definition 5 2.1 power pins 6 2.2 clock pins 6 2.3 aui pins 6 2.4 tpe pins 7 2.5 controller interface pins 7 2.6 mode pins 8 2.7 led pins 9 3.0 82503 architecture 10 3.1 clock generation 10 3.2 transmit blocks 10 3.3 receive blocks 11 3.4 collision detection 13 3.5 link integrity 13 3.6 jabber function 13 3.7 tpe loopback 13 3.8 sqe test function 14 3.9 port selection 14 3.10 led description 14 3.11 polarity switching 14 3.12 controller interface 15 contents page 4.0 reset, low power and test modes 16 4.1 reset 16 4.2 low power and high impedance modes 16 4.3 diagnostic loopback 16 4.4 customer test modes (continuous aui/tpe transmit) 16 5.0 application example 17 5.1 introduction 17 5.2 design guidelines 17 5.3 layout guidelines 17 6.0 package thermal specifications 19 7.0 electrical specifications and timings 20 2
82503 290421 1 figure 1. application block diagram 1.0 82503 product features the 82503 incorporates all the active circuitry re- quired to interface ethernet controllers to 10base-t networks or the attachment unit interface (aui). it supports a direct no-glue interface to intel's family of high-performance lan controllers (82586, 82590, 82593, and 82596). the 82503 also provides a di- rect no-glue interface to the national semiconductor 8390 and 83932 (sonic), the western digital 83c690, the advanced micro devices 7990 (lance) and 79c900 (ilacc), and the fujitsu 86950 (etherstar) controllers. this component includes three advanced features: jumperless two-port design capability, automatic port selection, and polarity switching. the jumperless tpe or aui port selection capability allows design- ers maximum ease-of-use and network flexibility. au- tomatic port selection ensures complete software compatibility with existing 10base2 and 10base5 software drivers. the 82503's polarity switching fea- ture will detect and correct polarity errors on the twisted pairethe most common wiring fault in twist- ed pair networks. the 82503 contains all the circuitry needed to meet the 10base-t specification, including link integrity, a jabber timer and internal predistortion. deselecting link integrity allows the component to be used in some prestandard networks. the 82503's jabber timer prevents the station from continuously trans- mitting and is defeatable for simple design charac- terization. the predistortion circuitry eliminates line overcharge and reduces jitter on 10base-t links. the 82503 can also support twisted pair cable lengths of up to 200m when placed in tpe extended squelch mode (xsq). this component incorporates six led drivers to dis- play transmit data, receive data, collision, link integri- ty, polarity faults and port selections, allowing for complete network monitoring by the user. the trans- mit, receive and collision leds indicate the rate of activity by the frequency of flashing. the 82503 also has a low power mode. during low power, many of the 82503's pins are in a high-impedance state to facilitate board-level testing. the 82503's diagnostic loopback control enables it to route a transmission signal from the lan control- ler through its manchester encoder-decoder circuitry and back to the lan controller. this provides effec- tive network node fault detection and isolation capa- bilities. in addition, the 82503 supports diagnostic test modes that generate continuous tranmission of data through the twisted pair port, allowing design- ers to measure the analog performance of their de- sign. the 82503 is available in 44-lead plcc and 44-lead qfp packages and is fabricated with intel's low- power, high-speed, chmos iv technology using a single 5-v supply. 3
82503 290421 2 figure 2. 82503 functional block diagram 4
82503 2.0 pin definition 290421 3 figure 3. 44-lead plcc pin configuration 290421 44 figure 4. 44-lead qfp pin configuration 5
82503 2.1 power pins symbol plcc qfp type name and function pin pin v ss (1) 7, 17, 39 1, 11, 33 supply digital ground. v cc (1) 6, 18, 40 44, 12, 34 supply digital v cc . a 5-v g 5% power supply. v cca (1) 28 22 supply analog v cc . a 5-v g 5% power supply. v ssa (1) 29 23 supply analog ground. note: 1. v cc and v cca must be connected to the same power supply. v ss and v ssa must be connected to the same ground. separate decoupling and noise conditioning (e.g., ferrite beads) should be used. 2.2 clock pins symbol plcc qfp type name and function pin pin x1 21 15 i clock crystal. a 20 mhz crystal input. this pin can be driven with an external mos level clock when x2 is left floating. x2 20 14 o clock crystal. a 20 mhz crystal output. x1 can be driven with an external mos level clock when this pin is left floating. 2.3 aui pins symbol plcc qfp type name and function pin pin trmt 27 21 o transmit pair. a differential output driver pair that drives the transmit pair of the transceiver cable. the output bit stream is trmt 26 20 o manchester encoded. following the last transition, which is positive at trmt, the differential voltage is reduced to zero volts. rcv 31 25 i receive pair. a differentially driven input pair which is tied to the receive pair of the ethernet transceiver cable. the first transition on rcv 30 24 i rcv is negative-going to indicate the beginning of the frame. the last transition is positive-going to indicate the end of the frame. the received bit stream is assumed to be manchester encoded. clsn 25 19 i collision pair. a differentially driven input pair tied to the collision presence pair of the ethernet transceiver cable. the clsn 24 18 i collision presence signal is a 10 mhz square wave. the first transition at clsn is negative-going to indicate the beginning of the signal; the last transition is positive-going to indicate the end of the signal. 6
82503 2.4 tpe pins symbol plcc qfp type name and function pin pin tdh 35 29 o tp transmit pair drivers. these four outputs constitute the twisted-pair drivers, which have predistortion capabilities. the tdh/ tdh 37 31 o tdh outputs generate the 10 mb/s manchester encoded data. the tdl 34 28 o tdl/tdl outputs mirror the tdh/tdh outputs except for fat bit tdl 36 30 o occurrences (100 ns pulses). during the second half of a fat bit (either high or low), the tdl/tdl outputs are inverted with respect to tdh/tdh outputs. this signal behavior reduces the amount of jitter by preventing overcharge on the twisted pair medium. rd 32 26 i tp receive pair. the differential twisted pair receiver. the receiver pair is connected to the twisted pair medium and is driven rd 33 27 i with 10 mb/s manchester encoded data. 2.5 controller interface pins symbol plcc qfp type name and function pin pin txc 93o transmit clock. a 10 mhz clock output tied directly to the transmit clock pin of the ethernet controller. changes sense depending on controller selected. active low for intel and fujitsu controller interfaces, active high for national and amd interfaces. can drive one ttl load. txd 16 10 i transmit data. ttl input. nrz serial data is clocked in on txd from the ethernet controller. connects directly to the transmit data pin of the ethernet controller. rts 15 9 i request to send. ttl input. an active low input signal synchronous to txc which enables data transmission on the active port. changes sense depending on controller selected. active low for the intel controller interface, active high for national, amd, and fujitsu interfaces. rxc 14 8 o receive clock. a 10 mhz clock output tied directly to the receive clock pin of the ethernet controller. this clock is the recovered clock from incoming data on the active port. changes sense depending on controller selected. active low for intel and fujitsu controller interfaces, active high for national and amd interfaces. can drive one ttl load. rxd 13 7 o receive data. received nrz data (synchronous to rxc ) passed to the ethernet controller. connect directly to the receive data pin of the controller. can drive one ttl load. crs 10 4 o carrier sense. output that alerts the ethernet controller that data is present on the active port. connects directly to the carrier sense pin of the ethernet controller. changes sense depending on controller mode selected. active low for intel controller interface, active high for national, amd, and fujitsu interfaces. can drive one ttl load. cdt 12 6 o collision detect. output that indicates presence of a collision. connects directly to the collision detect pin of the ethernet controller. changes sense depending on controller selected. active low for intel and fujitsu controller interfaces, active high for national and amd interfaces. can drive one ttl load. 7
82503 2.6 mode pins symbol plcc qfp type name and function pin pin tpe/aui 2 40 i/o port select. ttl input/led output. if aport is low, tpe/aui is an input and selects either the tpe port (tpe/aui high) or aui port (tpe/aui low). if aport is high, the 82503 will indicate the port selected by driving tpe/aui high (tpe) or low (aui). tpe/aui can drive an led pull-up. aport 3 41 i automatic port selection. ttl input. when high, 82503 will automatically select tpe or aui port based on presence of valid link beats or frames on the tpe receive input. mode selected will be indicated on tpe/aui . apol/xsq 4 42 i automatic polarity correction/extended squelch enable. ttl input. when high, the extended squelch mode is disabled and automatic polarity correction is enabled. both junctions (apol and xsq) are enabled when this pin is at a high impedance state. when low, both functions become disabled. the presence of a polarity fault on the tpe receive pair is indicated on poled regardless of the state of apol. lid 38 32 i link integrity disable. ttl input. if high, link integrity function is disabled. if low, link integrity function is enabled. cs0 5 43 i controller select. selects the appropriate interface for the desired ethernet controller. when cs0/1 e 0/0, supports cs1 8 2 i intel controllers. when cs0/1 e 0/1, supports fujitsu controllers. when cs0/1 e 1/0, supports western digital and national controllers. when cs0/1 e 1/1, supports amd controllers. (see table 2.) lpbk 11 5 i loopback. ttl input. an active low input signal that causes the 82503 to enter diagnostic loopback mode. the twisted pair or aui medium will be removed from the circuit, thus isolating the node from the network. when not connected, this pin assumes the inactive (high) state. diagnostic loopback does not disable the operation of the link integrity processor, link beat generator, or automatic port selection. jabd 23 17 i jabber disable. ttl input. when high, this pin disables the jabber function. when low, the jabber function is enabled and the device performs aui or tp jabber protection for the active port. if this pin and test are asserted during a falling edge of reset, the 82503 enters its low power mode; when either this pin or test deasserts, then the 82503 transitions to its normal operating mode. test 19 13 i test mode enable. ttl input. when test is high and reset is deasserted, a customer test mode is directly accessed. when driven low, test mode is disabled. if this pin and jabd are asserted during a falling edge of reset, the 82503 enters its low power mode; when either this pin or jabd deasserts, then the 82503 transitions to its normal operating mode. reset 22 16 i reset. ttl input. when high, resets internal circuitry. on the falling edge of reset, either test mode or low power mode can be entered depending on the state of jabd and test. 8
82503 2.7 led pins symbol plcc qfp type name and function pin pin txled 42 36 i/o transmit led. led output. indicates transmit status of the aui or tpe port. normally off (high) output. turns on to indicate transmission. flashes at a rate dependent on the level of transmit activity. upon entering a customer test mode, this pin must be driven high either through an led, or a resistor. rxled 43 37 i/o receive led. led output. indicates receive status of the aui or tpe port. normally off (high) output. turns on to indicate reception. flashes at a rate dependent on the level of receive activity. upon entering a customer test mode, this pin must be driven high either through an led, or a resistor. coled 44 38 i/o collision led. led output. indicates collision status of the aui or tpe port. normally off (high) output. turns on to indicate collision. flashes at a rate dependent on the level of collision activity. this pin is also used to determine which customer test modes are entered. liled 41 35 o link integrity led. led output. normally on (low) output which indicates good link integrity on the tpe port during tpe mode. remains on when link integrity function has been disabled. turns off during aui mode or when link integrity fails in tpe mode. minimum off time is 100 ms, minimum on time is set by the link integrity function. poled 1 39 o polarity indication. led output. if the 82503 detects that the receive tpe wires are reversed, poled will turn on (low) to indicate the fault. poled remains on even if apol/xsq is high and the 82503 has automatically corrected for the reversed wires. note: 1. the led outputs have a weak pull-up capable of sourcing 500 m a. they can sink 10 ma while still meeting ttl levels. all leds can be used as indication pins if no led is needed. some of these outputs include pulse width conditioning, which should be accounted for in software. 9
82503 3.0 82503 architecture 3.1 clock generation a 20 mhz parallel resonant crystal is used to control the clock generation oscillator, which provides the basic 20 mhz clock source. an internal divide-by- two counter generates the 10 mhz g 0.01% clock required by the ieee 802.3 specification. we recommend a crystal that meets the following specifications be used. # quartz crystal # 20 mhz g 0.002% at 25 c # accuracy g 0.005% over full operating tempera- ture, 0 cto a 70 c # parallel resonant with 20 pf load fundamental mode # maximum series resistance: r series e 30 x several vendors have such crystals; either-off-the shelf or custom made. two possible vendors are: 1. m-tron industries, inc. yankton, sd 57078 specifications; part no. hc49 with 20 mhz, 50 ppm over 0 cto a 70 c, and 20 pf fundamental load. 2. crystek corporation 100 crystal drive ft. myers, fl 33907 part no. 013212 the accuracy of the crystal oscillator frequency de- pends on the pc board characteristics, therefore it is advisable to keep the x1 and x2 traces as short as possible. the optimum value of c1 and c2 should be determined experimentally under nominal operat- ing conditions. the typical value of c1 and c2 is between 22 pf and 35 pf. an external 20 mhz mos-level clock may be applied to pin x1, if pin x2 is left floating. 3.2 transmit blocks 3.2.1 manchester encoder the 20 mhz clock is used to manchester-encode data on the txd input. this clock is also divided by two to produce the 10 mhz clock the lan controller needs for synchronizing its rts and txd signals. data encoding and transmission begins with rts asserting. since the first bit of a transmission is a 1, the first transition is always negative on the transmit outputs (trmt or td pins). transmission ends when rts deasserts. the last transition is always positive at the transmit outputs (trmt or td pins) and may occur at the center of the bit cell if the last data bit to be transmitted is a 1, or at the boundary of the bit cell if the last data bit to be sent is a 0. immediately after the end of a transmission, all sig- nals on the rcv pair (when aui mode is selected) are inhibited for 4 to 5 m s. this dead time is neces- sary for proper operation of the sqe (heartbeat) test. 3.2.2 aui cable driver the aui cable driver (trmt pair) is a differential circuit, which interfaces to the aui cable through a pulse transformer. high voltage protection is achieved by using a trans- former to isolate the transmit pins (trmt pair) from the transceiver cable. the total transmit circuit in- ductance, including the 802.3 transceiver transform- ers, should be a minimum of 27 m h for ethernet ap- plications. 3.2.3 twisted pair cable driver the twisted pair line drivers (td pairs) begin trans- mitting the serial manchester bit stream 3 bit times after rts is asserted. the line drivers use a predis- tortion algorithm to improve jitter performance for up to 100 meters of twisted pair cable. the line drivers reduce their drive level during the second half of ``fat'' (100 ns) manchester pulses and maintain a full drive level during all ``thin'' (50 ns) pulses and during the first half of the ``fat'' pulses. this reduces line overcharging during ``fat'' pulses, a major source of jitter. 10
82503 290421 4 figure 5. tpe predistortion 3.3 receive blocks 3.3.1 manchester decoder and clock recovery the 82503 performs manchester decoding and tim- ing recovery of the incoming data in aui and tpe modes. the manchester-encoded data stream is decoded to separate the receive clock (rxc ) and the receive data (rxd) from the differential signal. the 82503 uses an advanced digital technique to perform the decoding function. the use of digital circuitry instead of analog circuitry (e.g., a phase-lock loop) to per- form the decoding ensures that the decoding func- tion is less sensitive to variations in operating condi- tions. a high-resolution phase reference is used to digitize the phase of the incoming data bit-center transition. the digitizer has a phase resolution of 1/32 of a bit time. the digitized phase is filtered by a digital low-pass filter to remove rapid phase variations, i.e., phase jitter. slow phase variations, such as those caused by small differences between the data frequency and the clock frequency, are not filtered by the low- pass filter. the rxc generator digitally sets the phases of the two rxc transitions to respectively lead and lag the bit-center transition by (/4 bit time. rxc is used to recover rxd by sampling the incoming data with an edge-triggered flip-flop. lock is achieved by reducing the time constant of the digital filter to zero at the start of a new frame. any uncertainty in the bit-center phase of the first transition that is caused by jitter is subsequently re- moved by gradually increasing the filter time con- stant during the following preamble. by that time, the phase of the bit center is output by the filter, and lock is achieved. lock is achieved within the first 14 bit times as seen by the aui inputs. the maximum bit-cell timing distortion (jitter) tolerated by the man- chester decoder circuitry is g 12 ns (preamble), g 18 ns (data) for aui, and g 13.5 ns for tpe (data and preamble). 11
82503 290421 5 figure 6. manchester decoder and clock recovery 3.3.2 aui receive and collision buffers the aui receive and collision inputs are driven through isolation transformers to provide high volt- age protection and dc common mode voltage rejec- tion. the incoming signals are converted to digital levels and passed to the manchester decoder and collision detection circuitry. 3.3.3 aui receive and collision squelch circuits both the receive (rcv) and collision (clsn) pairs have the following squelch characteristics. # the squelch circuits are turned on at idle. # a pulse is rejected if the peak differential voltage is more positive than b 160 mv regardless of pulse width. # a pulse is considered valid if its peak differential voltage is more negative than b 300 mv and its width, measured at b 285 mv, is greater than 25 ns. # the squelch circuits are disabled by the first valid negative differential pulse on either the aui re- ceive (rcv) or the aui collision (clsn) pair. # if a positive differential pulse occurs on either the aui receive or collision pairs for greater than 160 ns, end of frame (eof) is assumed and the squelch circuitry is turned on. 3.3.4 tpe receive buffer the tpe receive pins (rd and rd ) are connected to the twisted pair medium through an analog front end. the analog front end contains the line coupling devices and emi filters necessary to conform to the 10base-t standards and local rf regulations. the input differential voltage range for the tpe receiver is greater than 500 mv and less than 3.1v differen- tial. 3.3.5 tpe receive squelch circuits the tpe receive buffer distinguishes valid receive differential data, link test pulses, and the idle condi- tion according to the requirements of the 10base-t standard. signals at the output of the emi filter (thus at the rd and rd pair) are rejected as follows: # all differential pulses of peak magnitude less than 300 mv are rejected. # all continuous sinusoids with a differential ampli- tude less than 6.2 v pp and a frequency less than 2 mhz are rejected. # all sine waves of single cycle duration starting with phase 0 or 180 that have an amplitude less than 6.2 v pp , and a frequency of 2 mhz to 16 mhz are rejected, if the single cycle is pre- ceeded and followed by 4 bit times of silence (i.e., a signal less than 300 mv). 3.3.6 tpe extended squelch mode by placing the 82503 into tpe extended squelch mode, the 82503 can support cable lengths greater than the 100m specified in the 10base-t ieee stan- dard (802.3i-1990). the squelch thresholds for the signals at the rd/rd pair are typically reduced by 4.5 db. this allows grade 5 twisted-pair cable to be used to overcome attenuation and multipair cross- talk for cable lengths up to 200 meters. 12
82503 tpe extended squelch mode is enabled by present- ing a high-impedance ( l 100 k x ) at the apol/xsq pin. this can be done by floating the apol/xsq pin, tying apol/xsq low through a 100 k x resistor, or driving apol/xsq with a three-state buffer. when driven high or low using a ttl driver or a low imped- ance pull-up or pull-down ( k 2k x ) extended squelch is disabled and the driven level at the apol/xsq pin determines the state of the polarity- correction function (apol/xsq e 1 enables polari- ty correction, apol/xsq e 0 disables polarity cor- rection). the tpe extended squelch feature is trans- parent to previous steppings of the 82503. polarity correction is always enabled when the tpe extend- ed-squelch feature is enabled (apol/xsq e z). the apol/xsq pin senses a high-impedance state by an active-polling circuit implemented at the pin. two small polling devices attempt to pull the apol/ xsq pin up to v cc and down to v ss . if the pin is in a high-impedance state, the devices will be successful in pulling the apol/xsq pin high and low. if the pin is driven high or low, the polling devices will not be able to successfully pull the pin in the opposite di- rection. in this way, an internal state machine can correctly determine one of three states of the apol/xsq pin. the pin is polled every 25.6 m s. 3.4 collision detection 3.4.1 aui collision detection collision detection in the aui mode is performed by the attached transceiver, and signalled to the 82503 on the clsn pair. a 10 mhz a 25%, or b 15%, square wave with transition times between 35 ns and 70 ns indicates the collision. the 82503 reports this to the lan controller on the cdt pin. 3.4.2 tpe collision detection collision detection in the tpe mode is indicated by simultaneous transmission and reception on the twisted pair link segment. the cdt signal is assert- ed for the duration of both rts and the presence of received data; crs is asserted for the duration of either rts or the presence of received data. during a collision, the source of rxd will be the received data. if the received data stream ends before the transmit data stream, the rxd source will be changed to transmit data stream until it ends. 3.5 link integrity the 82503 supports the link integrity function as de- fined by 10base-t. during long periods of idle on the transmitter, link test pulses will be transmitted on to the twisted pair medium as an indication to the remote mau that the link is good. these pulses will be transmitted 8 ms to 24 ms after the end of the last transmission or link test pulse. the link integrity function continuously monitors ac- tivity on the receive circuit. if neither valid data nor link test pulses are received, the link integrity proc- essor declares the link bad, and disables transmis- sion and reception on the media, loopback, and the sqe test function. transmission of link test pulses and monitoring receive activity are not affected. the idle time required for the link integrity processor to determine the link is bad is 50 ms to 150 ms. once a frame or a sequence of 2 to 10 valid consec- utive link test pulses are detected, the link integrity processor declares the link is good, and reconnects the transmitter and receiver. the link integrity function can be disabled by driving the lid pin high or by disabling automatic port selec- tion (aport e 0) and selecting the aui port. this option is intended primarily for use with pre- 10base-t networks. 3.6 jabber function the 82503 contains a jabber timer to implement the jabber function. if a transmission continues beyond the limits specified, the jabber function inhibits fur- ther transmission and asserts the collision indicator, cdt . the limits for jabber transmission are 20 ms to 150 ms in tpe mode, and 8 ms to 16 ms in aui mode. for both aui and tpe mode, the transmis- sion inhibit period extends until the 82503 detects sufficient idle time (between 250 ms and 750 ns) on the rts signal. the jabber function can be disabled by driving the jabd high. in tpe mode the link integrity function continues to operate even if the jabber function is inhibiting trans- mission. link test pulses continue to be sent and the receive circuit continues to be monitored. additional- ly, the link integrity function reconnects to a restored link without waiting for the transmit input to go idle when the jabber function is inhibiting transmission. 3.7 tpe loopback in tpe mode the 82503 implements the transmit to receive loopback (do to di) mode specified in the 10base-t standard. this mode loops back transmit- ted data through the receive path. this function is required to maintain full compatibility with coax maus where the data loopback is a natu- ral result of the architecture. 13
82503 the transmit to receive loopback function is disabled when the jabber function or link integrity function is inhibiting transmission. 3.8 sqe test function the 82503 supports the sqe test function when in tpe mode or in diagnostic loopback mode. the 82503 will assert its cdt pin within 0.6 m sto1.6 m s after the end of a transmission, and it will remain asserted for 5- to 15-bit times. if the 82503 is in the tpe mode and is not in diagnostic loopback mode, the link integrity function will disable the sqe test function when it detects a bad link. 3.9 port selection the 82503 features both manual and automatic port selection. to enable automatic port selection, con- nect aport to v cc . the 82503 then starts in tpe mode and monitors link integrity. if the link is good, the 82503 stays in tpe mode and pulls tpe/aui high to indicate that the tpe port was selected. if link integrity fails, the 82503 switches to aui mode and pulls tpe/aui low to indicate that the aui port is now active. tpe/aui can drive an led to indicate port selection (on for aui, off for tpe mode). note that liled will be on if tpe mode is selected and off if aui mode is selected. if link integrity is disabled while automatic port selection is enabled, the 82503 defaults to tpe mode. if the 82503 changes ports while rts is active, transmission is terminated with an end of frame marker on the old port. transmis- sion of the remaining packet fragment is not allowed on the new port. transmissions will begin with a complete data packet. the port can be manually selected by driving aport low. tpe/aui e 0 selects aui mode, and tpe/aui e 1 tpe mode. when the port is manually selected, the circuitry for the unused port is powered down. changing ports requires 100 m s to allow the circuitry for the new port to resume normal opera- tion. table 1. port selection configuration state lid aport tpe/aui x 0 0 aui (tpe port powered down) x 0 1 tpe (aui port powered down) 01 x * automatic port selection 11 x * tpe note: * tpe/aui is an output pin when aport e 1. 3.10 led description the 82503 supports six led pins to indicate the status of important states; tpe/aui , txled, poled, liled, rxled, coled. each pin is capable of directly driving an led. 3.10.1 tpe/aui when automatic port selection is enabled (aport is high), tpe/aui becomes an led output and turns off if tpe mode is selected and on if aui mode is selected. 3.10.2 txled transmit status. this led is normally off and flashes at 2.5 hz, 5 hz, and 10 hz to indicate respectively a low, medium, and high rate of transmit activity. 3.10.3 rxled receive led. this led is normally off and flashes at 2.5 hz, 5 hz, and 10 hz to indicate respectively a low, medium, and high rate of receive activity. 3.10.4 coled collision led. this led is normally off and flashes at 2.5 hz, 5 hz, and 10 hz to indicate respectively a low, medium, and high rate of collision activity. 3.10.5 poled polarity fault. this led is normally off and turns on to indicate a polarity fault in the receive pair of the 10base-t link. operation of this pin is not affected by the state of the polarity correction function (apol/xsq e x). 3.10.6 liled link integrity status. when aport is enabled (aport e 1), this led is normally on (driven low) to indicate the presence of a valid 10base-t link when the tpe port is active. the led will turn off (driven high) when the link fails. when link integrity is disabled (lid e 1) while aport is enabled (aport e 1) this led is turned on (driven low). if aport is disabled (aport e 0) and the aui port is manually selected (tpe/aui e 0) the led output is tristated. 3.11 polarity switching in tpe mode, the 82503 monitors receive link beats and end-of-frame delimiters for a possible receiver 14
82503 290421 6 figure 7. polarity fault state diagram polarity error due to crossed wires. if pin 4 of the 82503 is high and the tpe receive pins are re- versed, the 82503 will correct the error by reversing the signals internally, and turn poled on (low) to indicate that the fault has been detected and cor- rected. the polarity correction function is defeatable by driving the apol/xsq input low. however, the polarity fault will continue to be indicated on the poled. 3.12 controller interface connecting the 82503 to one of the intel ethernet controllers (82586, 82590, 82593, 82596) requires no additional components. simply drive cs0 and cs1 both low, and connect txc , txd, rts , rxc , rxd, crs , cdt , and lpbk to the corresponding controller pins. the 82503 also works with other ethernet control- lers without additional components, including the national semiconductor 8390 and 83932 (sonic), western digital 83c690, fujitsu 86950 (etherstar), depending on the state of and cs0 and cs1 inputs. the interface of the 82503 to the amd 7990 (lance) requires external logic to control the lpbk pin of the 82503. note that when an amd lan con- troller is used to interface to the 82503, the lpbk pin of the 82503 becomes active high. that is, the 82503 enters diagnostic loopback mode when lpbk pin is high and is in normal operation mode when lpbk pin is low. the logic sense of the 82503 controller pins will change and should be connected to the controller pins according to the following table. 15
82503 table 2. controller interface selection intel national, wd amd fujitsu 82503 controller controllers controller controllers pin 825xx 8390, 83c690, 7990 (lance), 86950 (etherstar) 83832 (sonic) 79c900 (ilacc) cs0 (1) 01 1 0 cs1 0 0 1 1 pin pin sense pin sense pin sense pin sense txc txc low txc high tclk high tckn low txd txd high txd high tx high txd high rts rts low txe high tena high ten high rxc rxc low rxc high rclk high rckn low rxd rxd high rxd high rx high rxd high crs crs low crs high rena high xcd high cdt cdt low col high clsn high xcol low lpbk lpbk low lpbk high lpbk high (note 2) notes: 1. cs0 and cs1 are intended to be static pins only. switching cs0 and cs1 during network reception or transmission will produce unpredictable results. 2. refer to section 3.12. 4.0 reset, low-power and test modes 4.1 reset when reset is asserted the device resets its inter- nal circuits. reset is required after power up, and before data can be transmitted or received. it is al- lowed any time thereafter, but any existing receive or transmit activity will be lost, and all state machines (link integrity, jabber, and polarity correction) re- turn to their initial states. test must be held low for a device reset to prevent entering a test for low pow- er mode. during reset, txc continues without in- terruption (in fujitsu mode both txc and rxc run continuously). 4.2 low power and high impedance modes when reset is deasserted while both test and jabd are held high, the 82503 enters its low power and high impedance modes. the majority of internal circuitry is powered down, and many inputs and out- puts are three-stated. these pins are: aport, apol/xsq, lid, tpe/aui , poled, liled, rts , lpbk , rxd, txd, crs and cdt . when either jabd or test is deasserted, the device begins a power on cycle which lasts less than 1 ms. during this cy- cle, all inputs are ignored and all transmissions are disabled. if rts is active when the device returns to normal operation, the remainder of that packet frag- ment is not transmitted. normal transmissions are resumed at the start of the first complete data pack- et. 4.3 diagnostic loopback this is a diagnostic test mode to help in fault isola- tion and detection. serial nrz data input on txd is manchester encoded and then looped back through the manchester decoder (tmd) appearing at the rxd output. collision detect is asserted following each transmission to simulate the sqe test. output cable drivers and input amplifiers are disconnected from the controller interface pins while in this mode. the link integrity and polarity fault detection func- tions are not inhibited by diagnostic loopback mode. if otherwise enabled, they continue to function. 4.4 customer test mode (continuous aui/tpe transmit) in this mode, the 82503 continuously transmits data without the intervention of a lan controller. trans- mission is at 10 mhz (11-bit pattern), and can occur on either the tpe or aui port. the jabber timer is disabled in this mode, allowing users to easily test the 10base-t harmonic content specification and the quality of their analog front end design without complex software exercisers. customer test modeeand low power mode are se- lected at the deassertion of reset as shown in the following table. (note that the 82503 must be in non- loopback mode before it can enter the customer test mode.) 16
82503 table 3. test and low power mode selection reset test jabd txled (1) rxled (1) coled (1) mode selected v 0 x x x x normal mode v 1 0 1 1 1 cont tx 10 mhz v 1 1 x x x low power note: 1. a standard led connection to these pins is sufficient to pull them to a logic 1. the port on which the continuous transmit appears is determined by the aport and tpe/aui pins. if automatic port selection is enabled (aport e 1) then the tpe port broadcasts the continuous trans- mit. if manual port selection is enabled (aport e 0), then tpe/aui selects the port (1 for tpe, 0 for aui). test mode is disabled when test is deassert- ed and the device is reset. 5.0 application example 5.1 introduction the 82503 is designed to work directly with the intel lan controllers (82586, 82590, 82593, and 82596), as well as amd's am7990, national semiconduc- tor's 8390, western digital's 82c690, and fujitsu's 86950. the serial interface signals connect directly between one of the aforementioned lan controllers and the 82503 without the need for external logic. this example is targeted toward interfacing the 82503 to the intel 82596 in a two-port (tpe/aui) application. 5.2 design guidelines aui pulse transformer in order to meet the 16v fault tolerance specification of 802.3 a pulse transformer is recommended for the transmit, receive and collision pairs. the transformer should be placed between the trmt, rcv, and clsn pairs of the 503, and the do, di, and ci pairs respectively, of the aui (db-15 connector). the pulse transformer should have a parallel inductance of 75 m h minimum (100 m h recommended). several vendors stock such transformers. two pos- sible vendors are: 1. pulse engineering (p/n pe-64103) 2. valor electronics (p/n lt6003) terminating resistors the terminating resistors used across the receive and collision pairs are recommended to be 78.7 x g 1%. analog front-end the 82503 provides six tpe pins (tdh, tdh , tdl, tdl , rd, and rd ) that connect to the analog front end through a resistor summing network (figure 7). afe solutions can be made discretely or purchased from several manufacturers. two different solutions are described in application note 356. the example shown here uses a pulse engineering afe package pe65434 which includes emi filter, isolation trans- former, and common mode choke. the output of the afe connects directly to the 10base-t connector (rj-45). decoupling it is recommended that 0.01 m f x7r and 0.001 m f npo decoupling capacitors be placed between the v cca and v ccd of the 82503 to v ssa and v ssd . clock generation the clock input to the 82503 can be from a clock oscillator or a crystal. if a clock oscillator is used, x1 should be driven, and x2 left floating. if a crystal oscillator is used, refer to section 3.1 for crystal specifications. a complete 82596/82503 tpe/aui ethernet solu- tion is shown at the end of this section. 5.3 layout guidelines general the analog section, as well as, the entire board itself should conform to good high-frequency practices and standards to minimize switching transients and parasitic interaction between various circuits. to achieve this, the following guidelines are presented. 17
82503 290421 7 figure 8. application example schematic 18
82503 make power supply and ground traces as thick as possible. this will reduce high-frequency cross cou- pling caused by the inductance of thin traces. connect logic and chassis ground together. separate and decouple all of the analog and digital power supply lines. close signal paths to ground as close as possible to their sources to avoid ground loops and noise cross coupling. use high-loss magnetic beads on power supply dis- tribution lines. crystal the crystal should be adjacent to the 82503 and trace lengths should be as short as possible. the x1 and x2 traces should be symmetrical. 82503 analog differential signals the differential signals from the 82503 to the trans- formers, analog front end, and the connectors should be symmetrical for each pair and as short as possible. differential signal layout should be per- formed to a characteristic impedance of 78 x (for aui) or 100 x (for tpe). as a general rule, the trace widths should be one to three times the distance between the pcb layers to eliminate excessive trace inductance. the differential signals should also be isolated from the high speed logic signals on the same layer as well as on any sublayers of the pcb. group each of the circuits together, but keep them separate from each other. separate their grounds. in layout, the circuitry from the connectors to the filter network, should have the ground plane re- moved from beneath it. this will prevent ground noise from being induced into the analog front end. all trace bends should not exceed 45 degrees. 6.0 package thermal specifications the 82503 dual serial transceiver is specified for operation when case temperature (t c ) is within the range of 0 cto a 85 c. the case temperature can be measured in any environment, to determine if the 82503 is within the specified operating range. the case temperature should be measured at the center of the top surface opposite the pins. the acceptable operating ambient temperature (t a ) is guaranteed as long as t c is not violated. the am- bient temperature can be calculated from the i ja and i jc from the following equations: t j e t c a p c i jc t j e t a a p c i ja t a e t c b p c ( i ja b i jc ) values for i ja and i jc are given in table 4 for the 44- lead plcc and 44-lead qfp packages. various val- ues for i ja at different airflows. table 5 shows the maximum t a allowable (without exceeding t c )at various airflows. table 4. thermal resistance ( c/watt) i jc and i ja i ja vs airfloweft/min (m/s) package i jc 0 200 400 600 800 1000 (0) (1.01) (2.03) (3.04) (4.06) (5.07) 44-lead 19 57 48 43 41 39 37 plcc 44-lead 26 98 94 78 70 66 64 qfp table 5. maximum t a at various airflows i ja vs airfloweft/min (m/s) package 0 200 400 600 800 1000 (0) (1.01) (2.03) (3.04) (4.06) (5.07) 44-lead 66 71 73 74 75 76 plcc 44-lead 49 51 59 63 65 66 qfp 19
82503 7.0 electrical specifications and timings absolute maximum ratings case temperature under bias 0 cto a 85 c storage temperature b 65 cto a 140 c all output and supply voltages b 0.5v to a 7v all input voltages b 1.0v to a 6.0v (1) notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. dc characteristics (t c e 0 cto a 85 c, v cc e 5v g 5%, v cca e 5v g 5%) symbol parameter min max units test conditions v il (ttl) (2) input low voltage b 0.3 0.8 v v ih (ttl) (2) input high voltage 2.0 v cc v i li (2) input leakage current g 10 m a 0.0v s v i s v cc , reset e 1 v ol (mos) (3) output low voltage 0.45 v i ol e 4ma v oh (mos) output high voltage 3.9 v i oh eb 500 m a v ol (led) (4) output low voltage 0.45 v i ol e 10 ma v oh (led) output high voltage 3.9 v i oh eb 500 m a i lp leakage current, low g 10 m a 0.0v s v i s v cc power mode (5) r diff input differential resistance (6) 10 k x dc v idf (tpe) (7) input differential accept g 0.500 g 3.1 v p 5 mhz s f s 10 mhz input differential reject g 0.300 v p input differential accept (xsq) (note 8) g 3.1 v p input differential reject (xsq) g 0.180 v p r s (tpe) (8) output source resistance 6 13 x l i load l e 25 ma v idf (aui) (9) input differential accept g 0.300 g 1.5 v p input differential reject g 0.160 v p v odf (aui) (10) output differential voltage g 0.450 g 1.20 v notes: 1. the voltage levels for rcv, clsn, and rd pairs are b 0.75v to a 8.5v. 2. ttl input pins: txd, rts , tpe/aui , aport, apol/xsq, lid, cs0, cs1, lpbk , jabd, test, reset. 3. mos output pins: txc , rxd, rxc , crs , cdt . 4. led pins: tpe/aui , txled, rxled, coled, poled, liled. v ol measured 10 ns after falling edge of txc . 5. pins: aport, apol/xsq, lid, tpe/aui , poled, liled, rts , lpbk , rxd, txd, crs , cdt , cs0, cs1, jabd, test, and reset. 6. pins: rd to rd , rcv to rcv , and clsn to clsn . 7. tpe input pins: rd, and rd . see section 3.3.4 and section 3.3.5. 8. typically it is b 4.5 db below normal squelch level. 9. tpe output pins: tdh, tdh , tdl, and tdl .r s measures v cc or v ss to pin. 10. aui input pins: rcv, and clsn pairs. 11. aui output pins: trmt pair. 20
82503 dc characteristics (t c e 0 cto a 85 c, v cc e 5v g 5%, v cca e 5v g 5%) (continued) symbol parameter min max units test conditions i osc (aui) aui output short circuit current g 150 ma short circuit to v cc or gnd v u (aui) output differential undershoot b 100 mv v odi (aui) differential idle voltage (11) g 40 mv i cc (hot) power supply current (12) 65 ma aport e 1 i cc power supply current 75 ma aport e 1 i cc power supply current 60 ma aport e 0 i ccsb standby supply current (13) 1 ma low power mode, 20 m a typical pd (hot) power dissipation (12) 0.38 w aport e 1, continuous transmission on aui pd power dissipation 0.40 w aport e 1, continuous transmission on aui pd sb standby power dissipation (13) 5.25 mw low power mode, 105 m w typical c in (14) input capacitance 10 pf at f e 1 mhz notes: 11. measured 8.0 m s after last positive transition of data packet. 12. i cc hot measurements made at t c ea 85 c. additionally, trmt, trmt , tdh, tdh , tdl, tdl are loaded with 20 pf and load resistors removed. 13. pins cs0 and cs1 connected to v cc or v ss through a 2.5 k x (or less) resistor. i ccsb is typically at 20 m a after 30s from power down assertionenot tested. 14. characterized, not tested. (controller interface and mode pins only.) ac timing characteristics 290421 8 figure 9. mos input voltage levels (ttl compatible) for timing measurements (txd, rts , tpe/aui , aport, apol/xsq, lid, lpbk , jabd, test, and reset). 290421 9 figure 10. voltage levels for mos level output timing measurements (txc , rxd, rxc , crs , and cdt ). 290421 10 figure 11. voltage levels for differential input timing measurements (rcv and clsn pairs). 290421 11 figure 12. voltage levels for trmt pair output timing measurements. 21
82503 ac timing characteristics (continued) 290421 12 figure 13. voltage levels for tdh, tdl, tdh , and tdl . 290421 13 figure 14. voltage levels for differential input timing measurements (rd pair). ac measurement conditions 1. t c e 0 cto a 85 c, v cc e 5v g 5%. 2. the ac mos, ttl and differential signals are referred to in figures, 8, 9, 10, 11, 12, and 13. 3. ac loads a. mos: 20 pf total capacitance to ground. b. aui differential: a 10 pf total capacitance from each terminal to ground and a load resistor of 78 x g 1% in parallel with a 27 m h g 1% inductor between terminals. c. tpe: 20 pf total capacitance to ground. 4. all parameters become valid 200 m s after the supply voltage and input clock has stabilized, or after reset deasserts. clock timing (15) symbol parameter min typ max units t 1 x1 cycle time 49.995 50.005 ns t 2 x1 fall time 5 ns t 3 x1 rise time 5 ns t 4 x1 low time 15 ns t 5 x1 high time 15 ns note: 15. refers to external clock input. 290421 14 figure 15. x1 input voltage levels for timing measurements 22
82503 controller interface timings (intel mode) transmit timings (intel) symbol parameter min typ max units t 10 txc cycle time 99.99 100.01 ns t 11 txc high/low time 40 ns t 12 txc rise/fall time 5 ns t 13 txd and rts rise/fall time 10 ns t 14 txd setup time to txc v 45 ns t 15 txd hold time from txc v 0ns t 16 rts setup time to txc v 45 ns t 17 rts hold time from txc v 0ns 290421 15 figure 16. transmit timing (intel) 23
82503 receive timing (intel) symbol parameter min typ max units t 20 rxc cycle time 96 100 ns t 21 rxc high time 36 ns t 22 rxc low time 40 ns t 23 rxc rise/fall time 5 ns t 24 rxc delay from crs v 1100 1400 ns t 25 rxd rise/fall time 5 ns t 26 rxd setup from rxc v 30 ns t 27 rxd hold from rxc v 30 ns t 28 crs deassertion hold time from rxc high 10 40 ns 290421 16 figure 17. receive timing (intel) 24
82503 controller interface timings (national mode) transmit timings (national) symbol parameter min typ max units t 30 txc cycle time (16) 99.99 100.01 ns t 31 txc high/low time 40 50 ns t 32 txc rise/fall time at 20% to 80% 5 ns t 33 txd setup time to txc u 20 ns t 34 txd hold time from txc u 0ns t 35 txe setup time to txc u 20 ns t 36 txe hold time from txc u 0ns note: 16. all delay and width measurements on txc are made at 1.5v. 290421 17 figure 18. transmit timing (national) 25
82503 receive timings (national) symbol parameter min typ max units t 40 rxc cycle time 96 100 ns t 41 rxc high/low time (17) 40 50 60 ns t 42 rxc rise/fall time at 20% to 80% 5 ns t 43 rxd rise/fall time at 20% to 80% 5 ns t 44 rxd setup time to rxc u 30 ns t 45 rxd hold time from rxc u 20 ns t 46 rxc delay from crs u 1400 ns t 47 rxc continuing beyond crs v 5 cycles note: 17. all delay and width measurements on rxc are made at 1.5v. 290421 18 figure 19. receiving timings (national) 26
82503 controller interface timing (amd mode) transmit timings (18) (amd) symbol parameter min typ max units t 50 tclk cycle time 99.99 100.01 ns t 51 tclk high time ( @ 0.8v to 2.0v) 45 50 58 ns t 52 tclk low time ( @ 2.0v to 0.8v) 45 50 58 ns t 53 tclk rise/fall time ( @ 0.8v to 2.0v) 2.5 5 ns t 54 tx setup time to tclk u 20 ns t 55 tx hold time from tclk u 5ns t 56 tena setup time to tclk u 20 ns t 57 tena hold time from tclk u 5ns note: 18. delay times for tx, tena, and tclk are measured from 0.8v for falling edges, and 2.0v for rising edges. 290421 19 figure 20. transmit timings (amd) 27
82503 receive timings (19) (amd) symbol parameter min typ max units t 60 rclk cycle time 96 100 ns t 61 rclk high time ( @ 0.8v to 2.0v) 38 50 ns t 62 rclk low time ( @ 2.0v to 0.8v) 38 50 ns t 63 rclk rise/fall time ( @ 0.8v to 2.0v) 2.5 5 ns t 64 rx rise/fall time ( @ 0.8v to 2.0v) 2.5 5 ns t 65 rx hold time from rclk u 10 ns t 66 rx setup time to rclk u 45 ns t 67 rena deassertion hold time from rclk u 40 50 80 ns t 68 rclk delay from rena u 450 ns note: 19. delay times for rx, rena, and rclk are measured from 0.8v for falling edges and 2.0v for rising edges. 290421 20 figure 21. receive timings (amdestart of frame) 290421 21 figure 22. receive timings (amdeend of frame) 28
82503 controller interface timings (fujitsu mode) transmit timings (fujitsu) symbol parameter min typ max units t 70 tckn cycle time 99.99 100.01 ns t 71 tckn high/low time (20) 40 50 ns t 72 tckn rise/fall time at 20% to 80% 5 ns t 73 txd setup time to tckn v (20) 20 ns t 74 txd hold time from tckn v (20) 0ns t 75 ten setup time to tckn v (20) 20 ns t 76 ten hold time from tckn v (20) 0ns note: 20. timing measurements are referenced at 1.5v level. 290421 22 figure 23. transmit timings (fujitsu) 29
82503 receive timings (fujitsu) symbol parameter min typ max units t 80 rckn cycle time 96 100 ns t 81 rckn high/low time (21) 35 50 60 ns t 82 rckn rise/fall time at 20% to 80% 5 ns t 83 rxd setup time from rckn v (21) 20 ns t 84 rxd hold time from rckn v (21) 10 ns t 85 xcd assertion hold time from rckn v (21) 010 ns t 86 xcd deassertion hold time from rckn v (21) 120 ns t 87 xcd deassertion setup time from rckn v (21) 80 130 ns t 88 rckn delay from xcd u (21) 1400 ns note: 21. timing measurements are referenced at 1.5v. 290421 23 figure 24. receive timings (fujitsuestart of frame) 290421 24 figure 25. receive timings (fujitsueend of frame) 30
82503 tpe timings tpe transmit timings symbol parameter min typ max units t 90 txd to td bit loss at start of packet 2 bits t 91 txd to td steady state propagation delay 400 ns t 92 txd to td startup delay 600 ns t 93 tdh and tdl pairs edge skew ( @ v cc /2) 1.5 3 ns t 94 tdh and tdl pairs rise/fall times ( @ 0.5v to v cc b 0.5v) 2 5 ns t 95 tdh and tdl pairs bit cell center to center 99 100 101 ns t 96 tdh and tdl pairs bit cell center to boundary 49 50 51 ns t 97 tdh and tdl pairs return to zero from last tdh u 250 400 ns t 98 link test pulse width 98 100 102 ns t 99 last td activity to link test pulse 8 13 24 ms t 100 link test pulse to data separation 190 200 ns 290421 25 figure 26. tpe transmit timings (start of frame) 290421 26 figure 27. tpe transmit timings (end of frame) 31
82503 290421 27 figure 28. tpe transmit timings (link test pulse) tpe receive timings symbol parameter min typ max units t 105 rd to rxd bit loss at start of packet 4 19 bits t 106 rd to rxd invalid bits allowed at start of packet 1 bits t 107 rd to rxd steady state propagation delay 400 ns t 108 rd to rxd start up delay 2.4 m s t 109 rd pair bit cell center jitter g 13.5 ns t 110 rd pair bit cell boundary jitter g 13.5 ns t 111 rd pair held high from last valid positive transition 230 400 ns t 112 crs assertion delay (intel, ns, and fuji mode) 700 ns (amd mode) 1500 ns t 113 crs deassertion delay 450 ns 290421 28 figure 29. tpe receive timings (start of frame) 32
82503 290421 29 figure 30. tpe receive timings (end of frame) tpe collision timings symbol parameter min typ max units t 115 onset of collision (rd pair and rts active) to cdt assert 900 ns t 116 end of collision (rd pair or rts inactive) to cdt deassert 900 ns t 117 cdt assert to rxd sourced from rd pair 900 ns t 118 cdt deassert (rd pair inactive) to rxd sourced from txd 900 ns 290421 30 figure 31. tpe collision timings (start of collision) 33
82503 290421 31 figure 32. tpe collision timings (end of collision) tpe link integrity timings symbol parameter min typ max units t 120 last rd activity to link fault (link loss timer) 50 100 150 ms t 121 minimum received linkbeat separation (20) 25 7ms t 122 maximum received linkbeat separation (21) 25 50 150 ms notes: 20. linkbeats closer in time to this value are considered noise, and are rejected. 21. linkbeats further apart in time than this value are not considered consecutive, and are rejected. 290421 32 figure 33. tpe link integrity timings 34
82503 aui timings aui transmit timings symbol parameter min typ max units t 125 txd to trmt pair steady state propagation delay 200 ns t 126 trmt pair rise/fall times 3 5 ns t 127 bit cell center to bit cell center of trmt pair 99.5 100 100.5 ns t 128 bit cell center to bit cell boundary of trmt pair 49.5 50 50.5 ns t 129 trmt pair held at positive differential at start of idle 200 ns t 130 trmt pair return to s 40 mv from last positive transition 8.0 m s 290421 33 figure 34. aui transmit timings aui receive timings symbol parameter min typ max units t 135 rcv pair rise/fall times 10 ns t 136 rcv pair bit cell center jitter in preamble g 12 ns t 137 rcv pair bit cell center/boundary jitter in data g 18 ns t 138 rcv pair idle time after transmission 8 m s t 139 rcv pair return to zero from last positive transition 160 ns t 140 crs assertion delay (intel, national, fujitsu modes) 100 ns (amd mode) 1050 ns t 141 crs deassertion delay 350 ns t 142 crs inhibited after frame transmission 4 4.3 5 m s 290421 34 figure 35. aui receive timings 35
82503 aui collision timings symbol parameter min typ max units t 145 clsn pair cycle time 80 118 ns t 146 clsn pair rise/fall times 10 ns t 147 clsn pair return to zero from last positive transition 160 ns t 148 clsn pair high/low times 35 70 ns t 149 cdt assertion time 75 ns t 150 cdt deassertion time 300 ns t 151 crs deassertion time (intel mode only, rcv pair idle) 450 ns 290421 35 figure 36. aui collision timings aui noise filter timings symbol parameter min typ max units t 152 rcv pair noise filter pulse width accept ( @ b 285 mv) 25 ns t 153 clsn pair noise filter pulse width accept ( @ b 285 mv) 25 ns 290421 36 figure 37. aui noise filter timings 36
82503 loopback timings symbol parameter min typ max units t 155 txd to rxd bit loss at start of packet 16 bits t 156 txd to rxd steady state propagation delay 600 ns t 157 txd to rxd startup delay 2.2 m s t 158 sqe test wait time 0.6 1.2 1.6 m s t 159 sqe test duration 0.5 0.8 1.5 m s t 160 lpbk setup/hold times to rts (22) 1.0 m s note: 22. guarantees proper processing of transmitted packets. violation of this specification will not result in spurious data trans- mission. incoming data packets occuring during transitions on lpbk will not be accepted. 290421 37 figure 38. loopback timings 37
82503 jabber timings symbol parameter min typ max units t 165 maximum length transmission before jabber fault (tpe) 20 25 150 ms t 166 maximum length transmission before jabber fault (aui) 10 13 18 ms t 167 minimum idle time to clear jabber function 250 420 750 ms 290421 38 figure 39. jabber timings led timings symbol parameter min typ max units t 170 txled, rxled, coled on time 50 450 ms t 171 txled, rxled, coled off time 50 ms t 172 liled on time 50 ms t 173 liled off time 100 ms 290421 39 figure 40. led timings 38
82503 mode timings (23, 24) symbol parameter min typ max units t 175 mode pins setup to rts v 100 ms t 176 mode pins hold from rts u 100 ms t 177 mode pins setup to rd active (25) 100 ms t 178 mode pins hold from rd active (25) 100 ms notes: 23. guarantees proper processing of data packets. violation of these specifications will not affect the integrity of the network. 24. mode pins are: aport, apol/xsq, lid, jabd, and tpe/aui . 25. any data received within 100 ms of a mode transmission will be considered invalid. 290421 53 figure 41. mode timings 39
82503 reset, test, and low power mode timings symbol parameter min typ max units t 180 test and jabd setup time to reset v 50 ns t 181 reset pulse width 300 ns t 182 low power mode deactivation from test and jabd v 1ms 290421 41 figure 42. reset timings (test mode) 290421 43 figure 43. reset timings (start of low power mode) 290421 42 figure 44. reset timings (end of low power mode) 40
82503 package dimensions plastic leaded chip carrier 290421 45 figure 45. principle dimensions and data 290421 46 figure 46. molded details 41
82503 290421 47 figure 47. terminal details 290421 48 figure 48. standard package bottom view (tooling option 1) 42
82503 290421 49 figure 49. standard package bottom view (tooling option ii) 290421 50 figure 50. detail j. terminal detail 43
82503 290421 51 figure 51. detail l. terminal details notes: the above diagrams use a 20-lead plcc package to show symbols for package dimensions. the table below indicates dimensions in mm that are specific to the 44-lead plcc package. 1. all dimensions and tolerances conform to ansi y14.5m-1982. 2. datum plane ehe located at top of mold parting line and coincident with top of lead, where lead exits plastic body. 3. datums de and fg to be determined where center leads exit plastic body at datum plane ehe . 4. to be determined at seating plane ece . 5. dimensions d 1 and e 1 do not include mold protrusion. 6. pin 1 identifier is located within one of the two defined zones. 7. locations to datum eae and ebe to be determined at plane ehe . 8. these two dimensions determine maximum angle of the lead for certain socket applications. if unit is intended to be socketed, it is advisable to review these dimensions with the socket supplier. 9. controlling dimension, inch. 10. all dimensions and tolerances include lead trim offset and lead plating finish. 11. tweezing surface planarity is defined as the furthest any lead on a side may be from the datum. the datum is estab- lished by touching the outermost lead on that side and parallel to de or fg . symbol description min max a overall height 4.19 4.57 a 1 distance from lead shoulder to seating plane 2.29 3.05 d overall package dimension 17.4 17.7 d 1 plastic body dimension 16.5 16.7 d 2 foot print 15.0 16.0 e overall package dimension 17.4 17.7 e 1 plastic body dimension 16.5 16.7 e 2 foot print 15.0 16.0 cp seating plans coplanarity 0.00 0.10 tcp tweezing coplanarity 0.00 0.10 lt lead thickness 0.23 0.38 44
82503 44-lead quad flatpack package 290421 52 figure 52. 44-lead quad flatpack package symbol description min nom max a package height 2.35 a1 stand off 0 0.60 b lead width 0.2 0.3 0.4 c lead thickness 0.1 0.15 0.2 d 1 package body 10 e 1 package body 10 e 1 lead pitch 0.65 0.8 0.95 d terminal dimension 12.0 12.4 12.8 e terminal dimension 12 12.4 12.8 l 1 foot length 0.38 0.58 0.78 y coplanarity 0.1 t lead angle 0 10 note: unless otherwise specified, all units are in millimeters. 45

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