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rev. 0.4 8/09 copyright ? 2009 by silicon labora tories sdbc-dk3 ug sdbc-dk3 ug c8051f930 w ireless s oftware d evelopment k it u ser ? s g uide 1. introduction the silicon labs wireless pr oduct software developmen t board, msc-dbsb8, is de signed to help engineers develop code for the silicon lab's ezradio? and ezradiopro? wireles s products using the silicon labs c8051f9xx microcontroller platform. the c8051f9xx wireless software development board (msc-dbsb8) is designed for code development. a second platform, the wds loadboard, may also be purchas ed allowing for exhaustive rf lab based testing. the loadboard can be bought under the part number msc-dklb2 but also within the ism-dk3 kit. figure 1. msc-dbsb8 software development board (sdb) figure 2. msc-dblb2 (not included) testing platform for controlled lab tests (loadboard) both boards come with the silic on labs standard 40-pin socket for co nnecting standard ezradio? and ezradiopro? evaluation testcards such as the si4432- dkdb1. the onboard c8051f930 comes preloaded with sample firmware to demonstrate a packet -based wireless link between two systems. the msc-dbsb8 c8051f9x x software developm ent board includes: ? one 40-pin socket for ezradio and ezradiopro testcards ? c8051f930 microcontroller preloaded with demonstration software ? standard debug connector for silicon labs c 8051 progra mming and debugging ? 4 buttons and 4 leds for custom purposes ? lcd display for setup paramete rs and information display ? rs232 interface via a 9-pin dsub male connector ? usb type b connector with silicon labs cp2102 usb > serial converter onboard ? on board 3.3 v psu ? 5 x 19 through hole breadboard area for customer's application
sdbc-dk3 ug 2 rev. 0.4
sdbc-dk3 ug rev. 0.4 3 t able of c ontents section page 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2. power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1. on board psu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.2. external psu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.3. powered by usb port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. system introduction: msc- dbsb8 icd connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4. system introduction: schematic (msc -dbsb8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 5. typical testboard schematic (si44 3x testcard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6. using the sdb with a standard testcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. radio evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.1. demonstration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 7.1.1. packet error rates (per) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.1.2. screen 2: setting up the rf parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1.3. screen 3: setting up further rf parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1.4. understanding antenn a diversity and where to use it . . . . . . . . . . . . . . . . . . . 16 7.1.5. packet length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1.6. max packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1.7. screen 5: the ready screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 7.1.8. running the demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2. lab mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 7.2.1. transmitter evaluation setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 7.2.2. receiver evaluation setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2.3. transmitter measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2.4. results (cw tests) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 7.2.5. pn9 measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2.6. results (pn9 tests) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2.7. receiver measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 7.2.8. results (ber test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 7.2.9. packet error test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 7.2.10. results (per test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 7.3. additional inform ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3.1. usb communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3.2. packet structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8. custom software development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1. program structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1.1. basic code overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 8.2. basic hardware co nnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9. main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1. flow chart main ( ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.2. main source file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10. si4432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
sdbc-dk3 ug 4 rev. 0.4 10.1. flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 10.1.1. rf packet received( ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.1.2. rftransmit( ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.2. si4432 header file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 10.3. si4432 source file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11. c8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.1. c8051 header file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2. c8051 source file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12. troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
sdbc-dk3 ug rev. 0.4 5 2. power supply the board has three power options. the user can select between these options by the supply source selector switch (sw1). 2.1. on board psu the on board psu supplies 3.3 vdc. in this mode, the board should be powered by a standard 9 v ac or 9?12 v dc adapter. 2.2. external psu in this mode, the board can be powered via the direct dc supply connector by an external psu. any supply voltage can be used in the 3.3?4 v range. polarity is marked on the pcb. 2.3. powered by usb port in this mode, the board can be powered via the usb connector. note: when using the white led flash option, it is recommend to use an alternative power supply.
sdbc-dk3 ug 6 rev. 0.4 3. system introduction: msc-dbsb8 icd connector figure 3. debug connector (emulator and programmer interface) table 1. debug connector pin # description 1 vdd (3.3 v) 2gnd 3gnd 4p2.7 5 reset 6p2.7 7rst/c2ck 8? 9gnd 10 ?
sdbc-dk3 ug rev. 0.4 7 table 2. 40-pin testcard connector (j5) pin # description pin # description 1 j6/1 (spi_mosi) 21 gnd 2 j7/1 22 j15/1 3 j6/2 (spi_sck) 23 gnd 4 j7/2 24 j15/2 5 j6/3 (rf_nsel) 25 j8/1 6 j7/3 26 ebid port (spi_mosi) 7 j6/4 27 gnd 8 j7/4 28 ebid port (spi_miso) 9 j6/5 29 j8/2 10 j7/5 30 ebid port (spi_sck) 11 j6/6 31 gnd 12 j7/6 (rf_nirq) 32 ebid port (ee_nsel) 13 j6/7 (pwrdn) 33 j8/3 14 j7/7(rf_nirq) 34 j15/3 15 j6/8 (gpio) 35 gnd 16 j7/8(spi_miso 36 j15/4 17 vdd (3.3 v) 37 j8/4 18 vdd (3.3 v) 38 j15/5 19 vdd (3.3 v) 39 gnd 20 vdd (3.3 v) 40 j15/6
sdbc-dk3 ug 8 rev. 0.4 4. system introduction: schematic (msc-dbsb8) figure 4. msc-dbsb8 schematic (1 of 2)
sdbc-dk3 ug rev. 0.4 9 figure 5. msc-dbsb8 schematic (2 of 2)
sdbc-dk3 ug 10 rev. 0.4 5. typical testboard sc hematic (si443x testcard) figure 6. si443x testcard schematic
sdbc-dk3 ug rev. 0.4 11 6. using the sdb with a standard testcard the standard ezradio or ezradiopro testcards that are typically plugged into the msc-dblb2 loadboard when engineers are performing rf tests on the radio ics can also be plugged into the 40pin socket on the software development board (sdb), as demonstrated below. figure 7. software development board (msc-dbsb8) with a standard silicon labs testcard installed
sdbc-dk3 ug 12 rev. 0.4 7. radio evaluation 7.1. demonstration mode when shipped, the msc-dbsb8 comes with example firmware, which is used to demonstrate the basic rf capabilities of silicon labs? rfic. in the current public release of this firmware only the ezradiopro si4432 transceiver is supported, later releases are intended to demonstrate the ever increasing number of products from silicon labs. newer firmware versions of the factory firmware may be available on the silicon labs website or via the wds cdrom. introducing the per demonstrat ion (version 3.xr firmware) reference firmware v3.xr is designed to show the si443x in a packet error rate test demonstration. this firmware is preloaded on to the c8051f930 microcontroller, but it is also available on the wds cd-roms in the sdb section. source code to the silicon lab's firmw are is also available in the same location, and is pr ovided as-is for reference purposes. 7.1.1. packet error rates (per) packet errors are common place in wireless communications. in real life applications, these errors are handled through the use of acknowledgements and retries. in the demonstration software such techniques are not implemented such that system designers can understand range limitations in various environments, allowing them to design robust protocols into their designs. in order to use this demonstration, users should start th e demo then move the two boards apart until packet errors can be seen to start appearing and the average per is in the order of 5%. at this point, the per demonstration should be cleared, and the test should be left alone to be re-run without being disturbed. it is expected that the per % will be reduce since the environm ental factors will be more constant. re-run the previous steps until a 2? 3% per is found regularly at a given range. at this po int, and with the current environmental conditions, you are at a range where a higher level protocol is required. silicon labs has found that at a low dat arate and sending approximately 5000 packets, a 2?3 km range is attainable. the demonstration shown below was performed along the danube river in budapest, hungary using the si4432. figure 8. example range-vs.-data rate location: danube river in budapest, hungary data rate range 2.4 kbps 2.05 km 4.8 kbps 2.03 km 9.6 kbps 1.5 km 50 kbps 1.37 km 100 kbps 1.1 km 125 kbps 0.96 km
sdbc-dk3 ug rev. 0.4 13 note: the following screen shots reference firmware version 3.5r, screen shots may differ slightly from the version you have received. figure 9. welcome screen users may by pass the introduction screen by pressing any of the pushbutton 1-4, alternatively wait until the screen times out and moves on itself. the following screen allows users to select the mode of operation: figure 10. operating modes figure 11. screen 1: demonstration mode since the sdb's firmware recognized the si4432 test card inserted into the 40 pin socket the appropriate modes of operation are presented on the menu system?in this case trx (transceiver). it is possible however to operate a transceiver in a rx (receive) or tx (transmit) mode also so menu features allow users to override the functionality. menu's are driven through the push button's 1?4 under the lcd?the function of each button is shown on the screen. figure 12. push buttons and lcd labeling
sdbc-dk3 ug 14 rev. 0.4 the up/down button (pb1) moves the arrow up and down the lcd screen. figure 13. active menu item pointer the arrow is used to highlig ht the function that will change when the us er presses the '+' and '-' buttons. in the screen shown above, 'function:' is highlighted, pressing the '+' and '-' butt ons will switch the mode of operation between demonstration mode and lab mode. moving the arrow down to the ' =>de mo mode: trx' will allow the user to change betwe en trx, rx and tx functionality via the '+' and '?' buttons. for the purpose of this introduction to the system we sh all operate in 'demonstration mode'. please ensure demo mode is selected and trx is enabled. the same selections should be made on both of the software development boards. 7.1.2. screen 2: setting up the rf parameters figure 14. screen 2: rf parameters menu the 2nd screen sets up the rf parameters for the link. adjustments are made by scrolling up and down the lcd using pb1, highlighting the relevant item to be chan ged and using the '+' and '-' buttons accordingly. this introduction assume s the following settings: data rate: 2.4 kbps modulation: gfsk frequency: 868.00 mhz the same selections should be made on both of the software development boards. 7.1.3. screen 3: setting up further rf parameters on this screen, there may be a difference with respect to the screen shot available which is dependent on the testcard installed in to the 40 pin connector. several te stcard options are available fo r the sdbc-dk3 (see website for details). typically, testcard variants include antenna diversity cards for use with antennas, single-ended tx/rx testcards (also intended for use with antennas), and split tx/rx testcards designed for use with coaxial cable to lab equipment (see "7.2. lab mode" on page 22 for more details).
sdbc-dk3 ug rev. 0.4 15 figure 15. antenna diversity testcard (may be ordered separately) figure 16. split tx and rx testcard (rx: left sma, tx: right sma) for use with coaxial cable and rf test equipment for scientific rf evaluation (may be ordered separately) figure 17. single-ended tx and rx testcard
sdbc-dk3 ug 16 rev. 0.4 if an antenna diversity card is fitted then the 'antenna mode' option on the 3rd screen will be available, this line is automatically removed when non-antenna diversity cards su ch as the 4432-DKDB1 are inserted. with this options users have the ability to sele ct antenna 1, antenna 2 or both (antenna diversity enab led). for typical operation select ?1&2?. this screen also allows users to setup the pa output leve ls of the of the radio. fi gure 18 demonstrates an output power of +20 dbm selected. figure 18. screen 3: rf parameters (antenna diversity card fitted) 7.1.4. understanding antenna diversity and where to use it antenna diversity is a technique that is use to improve the quality and reliab ility of a wireless link. the technique is particularly useful in city-like urban and indoor environm ents where clear lines of sight between the transmitter and the receiver cannot be achieved. in environments where clear lines-of-sight (los) are not possible, signals reflect along multiple pathways (multipath) before being received, each reflection can introduce phase shifts, time delays, attenuations and distortions that can disrupt the quality of the signal wh ich can cause problems for the receiver. antenna diversity assists the receiver by allowing it to see the signal from two slightly different positions through the use of multiple antennas. studies have shown that antenna diversity in both indoor and urban environments can recover 8?10 db of the link budget that is usually lost to the environmen t when receivers use only single antenna implementations. the technique however does not provide any major benefits in open environments and often this mis- understanding can cause confusion during range test exerci ses. in fact, due to the extra components used in the antenna switch it is possible that th ere maybe a small addition loss in the link budget thus reducing range. see table 3 and table 4. table 3. illustrative effects of antenna diversity in indoor/urban?multipath environments single antenna implementation multiple antenna implementation transmit power +20 dbm +20 dbm receive sensitivity ?118 dbm ?118 dbm multipath losses ?10 dbm ?2 dbm loss in matching/switch ?2 dbm ?3 dbm link budget 126 dbm 133 dbm table 4. effects of antenna diversity in line of sight (los)?open air environments single antenna implementation multiple antenna implementation transmit power +20 dbm +20 dbm receive sensitivity ?118 dbm ?118 dbm multipath losses 0 dbm 0 dbm loss in matching/switch ?2 dbm ?3 dbm link budget 136 dbm 135 dbm
sdbc-dk3 ug rev. 0.4 17 it can be seen from table 3 and table 4 that while the effects of antenna diversity on los environments are negligible, the benefits in indoor/urban environments can significantly help create robust, higher quality robust links. figure 19. screen 4: setting up the node parameters the self id on each card should already be selected and is contained in the ebid eeprom on the testcard. the ebid is placed on the testcard so that our firmware and support gui' s (such as wds) can recognize the characteristics of the board. the ebid is not required as part of the bill-of -materials in an en d customers design. the ebid contains information such as the local id, dest ination id, matching network configuration and antenna/ test card configuration type. figure 20. test card characteristics eeprom (ebid) the sdbc-dk3 is initially configured wit h the same value for the destination id and the self id. in order to run the demo, you will need to configure the destinat ion id of the first board to that of the second and vice versa. this will allow the two sdb boards to communicate with ea ch other. the id is considered the address. 7.1.5. packet length the node parameters screen also allows users to adjust the packet length so that they may: 1. perform head-to-head comparisons with competitive radios 2. learn the effects of packet length with respect to data-rate and robustness many things affect the robustness of a radio link and ofte n the lack of understanding of some of these variables can skew test results quite substantially. a good example of when this misunderst anding takes place is during head to head comparisons of different radio ic suppliers. by using the 'packet length' option in the menu, users may adjust the length of the packet to match such that they are looking at the same packet structure during their tests. (see section 7.7 for further details on the packet structure) once designers are satisfied with their head-to head co mparisons of the radio ic's having based their tests on similar structures then designers can use the packet length option to experiment with their protocol. packet length can have many tradeoffs with respect to power savings, robustness, data rates, processing overheads, etc.
sdbc-dk3 ug 18 rev. 0.4 consider the following: ? during the transmission of long packets, there is an increased chance that a disturbance may occur somewhere along that packet?thus the need to implement good crc checks. ? during the transmission of short packets, there is an increased chance that the entire packet may be lost during a disturbance?thus the need to implement more retries. ? transmission of long/short packets with a slow data rates have good easily recognizable 1's and 0's but by comparison to fast data rates have a greater 'on time' and may use more power but retries may be less (in turn saving power). ? transmission of long/short packets with a fast data ra te may have a less 'on time' but retires may be greater, antenna diversity may help reduce the multipath effects. the trade offs in radio applications are many and the list above is by no means the only possible scenarios, every application has its own list of acceptable trade offs and th rough the use of menu options such as data-rate, packet length and antenna diversity engineers can learn to bes t understand what options work for them and their environments. 7.1.6. max packets so that designers can scientifically qualify the aforemen tioned trade offs, careful experimentation in applicable application-like environments is recommended, the 'max. packets' menu option allows designers to select the number of packets used to generate a packet error rate (per) result. ? a large number of packets (1000?9999) allows for a good averaged result but can take time particularly at low data rates. ? a small number of packets (100) allows for a quick environmental assessment to be made prior to an exhaustive test. 7.1.6.1. example?typical usage the designer will arrive at th eir test site and run a 100 packet test expe riment prior to exhaus tive testing. if the results are in accordance with previous tests then the en vironment is similar to those of the previous occasion. if there is a substantial difference in the results of a 100 packet test with any previous occasions results then new environmental factors are playing into tests and these should be recorded as comments so that results from exhaustive testing is better understood. . 7.1.7. screen 5: the ready screen the ready screen on the lcd is the final step before st arting your experimentation. the ready screen labels the leds 1?4 according to the function they will perform. in this demonstration they are tx, rx, antenna 1 and antenna 2. note if you have disabled any of the antenn a's or are using a none antenna diversity card then the associated antenna is not represented by the leds. figure 21. non-antenna diversity testcard note: only one antenna highlighted on the top row and no-antdiv shown in the second line of text.
sdbc-dk3 ug rev. 0.4 19 figure 22. antenna diversity testcard note: depending on antenna selection the relevant antennas are shown on the top row and either antdiv, a_div(1), or a_div(2) is shown in the second line of text. the ready screen is designed to allow you to review t he settings on both boards. in the example shown above, we illustrate the following configuration: ? our first board with id 091 is sending its message to board with the id 094 ? at 2.4 kbps ? with frequency 868.00 mhz using the ready screen, we can see that there is an error on the split tx/rx board in that it is configured with a selfid of 054, this does not match t he destinationid on the antenna diversity board. from the 'ready screen' we can update the antenna diversity board accordingly. to do this, we can press pb3 or pb4, which are highlighted as 'settings' where we can re-run the se tting accordingly. once the settings are correct we c an run the demonstration accordingly. if the user has the ability to see both ends of the link then a white led driver is made available on the sdb with which you can enable a high brightness led to make visual confirmation easier of the remote board.
sdbc-dk3 ug 20 rev. 0.4 figure 23. white led control this feature is only manually enabled since the brightne ss of the led may be distracting when on desk operation is being implemented. 7.1.8. running the demonstration longer tests provide better averages, but in the interest of time, this demonstration sends only 1000 packets. users that modify the code can send as many or as few packets as they wish. the fact only 1000 packets are sent can cause higher per percentages sinc e most of the dropped packets will occu r while the user is setting up the demonstration because he himself will ab sorb much of the radiation and add to multipath and fading effects. as users become more familiar with radio it is highly recommended a greater numb er of packets be sent such that a better average can be generated. to run the demonstration, pl ace one sdb in a fixed location. (if test ing an antenna diversity system, place the antenna diversity unit in the fixed loca tion while using a single-ended testcard as the roaming testcard). the sdb kept in the fixed location should be considered the ?base unit?. this unit will act as the base unit. on the mobile unit, the unit with the split tx and rx, press 'tx on' and walk away from the base unit until the per settles around 5-7%. when the per has settled and all 1000 packets are sent press the clear button and run the test again but avoid being to close to the demo during the second test. if the test completes with 0-2% per then the test should be run again with a greater range, if 4?6% then run again but with a lower range. once you reliably get 2-3% at the end of the series of tests then, in that environment this can be considered the typical range in an application with limited error handling - as is the purpose of this experiment. good protocols and handling of dropped packets enable users to get much greater ranges. during early experimentation, users may notice that th e lcd and leds show information that represents antenna strength.
sdbc-dk3 ug rev. 0.4 21 figure 24. active antenna and rssi indications
sdbc-dk3 ug 22 rev. 0.4 7.2. lab mode the lab mode is intended for users who want to evaluate t he performance of the silic on labs rfics, supported through the shipping factory firmware on the sdb platform. lab mode is intended so users can per form simple evaluations, such as: ? transmitter evaluation ?? output power ?? spectrum analysis ? receiver evaluation ?? ber sensitivity ?? per sensitivity ?? receiver parameters: ?? automatic frequency control ?? blocking ?? selectivity using lab mode, users can independently evaluate transmit and receive performance. table 5 lists the test cards available for ordering. table 5. test cards available for ordering type matching network configuration part number transceivers high band 4432 ? dkdb1 4431 ? dkdb1 low band 4432 ? dkdb5 4431 ? dkdb5 receivers high band 4330 ? dkdb1 low band 4330 ? dkdb5 transmitters high band 4032 ? dkdb1 4031 ? dkdb1 low band 4032 ? dkdb5 4031 ? dkdb5
sdbc-dk3 ug rev. 0.4 23 figure 25. 4432-DKDB1 - split tx/rx antenna card using coaxial cable rx connection tx connection
sdbc-dk3 ug 24 rev. 0.4 figure 26. lab equipment connection diagram
sdbc-dk3 ug rev. 0.4 25 figure 27. test card connection diagram figure 28. sdb connection diagram
sdbc-dk3 ug 26 rev. 0.4 7.2.1. transmitter evaluation setup the transmitter output of the 4432-DKDB1 test board can be connected to a spectrum ana lyzer in order to evaluate output power and spectrum plots. alternatively the transmitter output may be connected to a vector signal analyzer to evaluate conditions such as freq vs time. the 4432-DKDB1 testcard also provides access to the radi o's gpio which can be used as test-points for the radios internal signals - see diagram above. 7.2.2. receiver evaluation setup receiver evaluation can be performed by connecting the receiver port of the testcard to an rf signal generator. the rf generator may use a data source from an external iq generator or from its internal memory depending on its feature set, often rf generators have a pn9 pattern option. the 4432-DKDB1 testcard also provides access to the radi o's gpio which can be used as test-points for the radios internal signals - see test card connection diagram. two modes are typically used during evaluations: 1. direct mode: in this mode, data is continuousl y sent via a source such as a pn9 generator. 2. packet mode: in this mode, the data source is customized in a defined packet structure. typically: preamble + sync_word + data payload + crc. example of a 20 byte packet that can be received by the sdb firmware: 7.2.3. transmitter measurements 7.2.3.1. cw lab mode using the cw lab mode, users may evaluate the following: 1. output power 2. frequency offset in transmitter output 3. phase noise preamble: 1010101010101010101010101010101010101010101010101010101010101010 sync: 0010110111010100 date: 0001010000110100001100000000100101100110001011111001110101010101 0101011101100001010011110010101111010100010000111101001101000010 1111011110011010011100001001000111000011 crc : 1101011110011000
sdbc-dk3 ug rev. 0.4 27 7.2.3.2. test method figure 29. setup screen (1 of 4) 1. ensure ?lab mode? is selected as the operating function. 2. select cw. 3. press to move on from this screen. figure 30. setup screen (2 of 4) 1. select the appropriate frequency. when evaluating with cw, data rate and modulation have no effect. 2. press to move on from this screen.
sdbc-dk3 ug 28 rev. 0.4 figure 31. setup screen (3 of 4) 1. select the appropriate output power required for the test. 2. press to move on from this screen. note: if an alternate testcard is used, such as the antenna divers ity test cards, users may see slightly different screen shots than those shown. users must turn off the diversity function by selecting ?antenna 1? and connecting to the appropriate antenna connector using 50 ? coaxial cable. figure 32. setup screen (4 of 4) 1. parameters on setup screen 4 are not relevant to cw evaluations. silicon labs recommends leaving them at their default values. 2. press to move on from this screen. in figure 33, the runtime screen will su mmarize the curren t valid settings. figure 33. runtime screen
sdbc-dk3 ug rev. 0.4 29 7.2.4. results (cw tests) 7.2.4.1. output power 1. set the center frequency of spectrum analyzer to the frequency under test. 2. set span to 10 mhz. 3. measure the tx output power on displayed plot. figure 34. spectrum plot showing cw output at 917 mhz 7.2.4.2. frequency offset at transmitter output 1. set the center frequency of spectrum analyzer to the frequency under test. 2. set span to 100 khz. 3. measure the frequency offset between the expected fr equency as selected in the menu and the actual tx output frequency. figure 35. typical spectrum plot using a silicon labs branded testcard in figure 35, it can be seen that the frequency error is less than 1 khz. silicon labs testcards are designed to have a maximum frequency error of < 5 khz.
sdbc-dk3 ug 30 rev. 0.4 7.2.4.3. phase noise 1. set the spectrum analyz er to ?phase noise?. 2. set the center frequency of spectrum analyzer to the frequency selected. 3. set the spectrum analyzer to the desired span (typically from 100 hz to 10 mhz span). figure 36. typical phase noise plot at 917 mhz 7.2.5. pn9 measurement using the pn9 lab mode, users may evaluate the following: 1. tx output spectrum 2. transmitter spectral mask 7.2.5.1. test method figure 37. setup screen (1 of 4) 1. ensure ?lab mode? is selected as the operating function. 2. select pn9. 3. press to move on from this screen.
sdbc-dk3 ug rev. 0.4 31 figure 38. setup screen (2 of 4) 1. select the appropriate frequency, data rate, and modulation. 2. press to move on from this screen. figure 39. setup screen (3 of 4) 1. select the desired output power. 2. press to move on from this screen. figure 40. setup screen (4 of 4) 1. parameters in fi gure 40 are not relevant to pn9 evaluations. s ilicon labs recommends leaving them at their default values. 2. press to move on from this screen.
sdbc-dk3 ug 32 rev. 0.4 figure 41. runtime screen in figure 41, the runtime screen will su mmarize the curren t valid settings. 7.2.6. results (pn9 tests) 7.2.6.1. tx output spectrum 1. set the center frequency of spectrum analyzer to the frequency under test. 2. set span to 500 khz and observe the tx spectrum. 7.2.6.2. evaluation of tx spectral mask using the pn9 mode, users can observe the tx spectrum to evaluate fcc/etsi compliance. figure 42. spectrum plot demonstrating 40k data rate, 40k deviation, gfsk modulation
sdbc-dk3 ug rev. 0.4 33 7.2.7. receiver measurements 7.2.7.1. bit error rate test using the ber lab mode users may evaluate the following: 1. ber sensitivity. 2. direct mode operation using a continuous data streams 3. receiver modem parameters: i. automatic frequency control ii. blocking iii. selectivity 7.2.7.2. test method 1. set frequency, modulation type, data rate and deviation parameters on the rf signal generator. 2. select the desired data source for the rf generator (e.g. pn9) 3. connect the receiver's input to the signal generator's output. figure 43. setup screen (1 of 4) 1. ensure function is set to ?lab? 2. set lab mode to ?ber? 3. press to move on from this screen. figure 44. setup screen (2 of 4) 1. selections here should match those previo usly entered into the rf signal generator 2. press to move on from this screen.
sdbc-dk3 ug 34 rev. 0.4 figure 45. setup screen (3 of 4) 1. parameters on setup screen 3 are not relevant to ber evaluations. silicon labs recommends leaving them at their default values. 2. press to move on from this screen. figure 46. setup screen (4 of 4) 1. parameters on setup screen 4 are not relevant to ber evaluations. silicon labs recommends leaving them at their default values 2. press to move on from this screen figure 47. runtime screen in the figure 47, the runtime screen will summarize the current valid settings.
sdbc-dk3 ug rev. 0.4 35 7.2.8. results (ber test) 7.2.8.1. ber sensitivity evaluation ber results will be shown on the ber inst rument or recorded by ei ther rf generators or iq modulators that have a ber option installed. the top trace in figure 48 demonstrates tx_data as sent by a transmitter and the bottom trace is the data received on the gpio pin. please note that there is an expected shift caused by a delay between the data at the transmitter and the data received by the receiver. figure 48. tx data sent and received 7.2.8.2. other receiver measurements using the test setup described above, users may also pe rform automatic frequency control (afc), blocking and selectivity tests. all the required parameters are controlled by the external rf generator.
sdbc-dk3 ug 36 rev. 0.4 7.2.9. packet error test using the per lab mode users may evaluate the following: 1. per sensitivity 2. fifo mode using predefined packet structures (see data sheet for further details) 3. receiver modem parameters: i. automatic frequency control ii. blocking iii. selectivity 4. connect the receiver's input to the signal generator's output. 7.2.9.1. test method 1. set frequency, modulation type, data rate and deviation parameters on the rf signal generator. 2. program a predefined packet into the generator using the format: (preamble + sync_word(2dd4h) + data + crc). 3. set the signal generator to external single trigger mode. 4. the software development board (sdb) generates a trigger on test point p1.4, this should be connected to the rf signal generator's exter nal trigger input. the p1.4 pin will enable the signal generator to s end one packet for each trigger. figure 49. setup screen (1 of 5) 1. ensure function is set to ?lab? 2. set lab mode to ?per? 3. press to move on from this screen. figure 50. setup screen (2 of 5) 1. selections here should match those previo usly entered into the rf signal generator. 2. press to move on from this screen.
sdbc-dk3 ug rev. 0.4 37 figure 51. setup screen (3 of 5) 1. parameters on setup screen 4 are not relevant to per evaluations. silicon labs recommends leaving them at their default values. 2. press to move on from this screen. figure 52. setup screen (4 of 5) 1. ensure the packet length matches that programmed in the rf signal generator. 2. select number of packets to be received by the receiv er using the max. packets field. the appropriate number of triggers will be sent by the sdb according to this setting. 3. press to move on from this screen. figure 53. setup screen (5 of 5) 1. press to commence packet error rate evaluation. this will start generating pulses on p1.4 that are used to trigger the rf si gnal generator. the rf generator will send one packet for every external trigger. as the radio is set to receive mode it is waiting for a specific pre- programmed packet to be arrive at the pre-programmed frequency, modulation and data rate.
sdbc-dk3 ug 38 rev. 0.4 figure 54. runtime screen in figure 54, the runtime screen will su mmarize the curren t valid settings. notes: 1. tr = trigger sent on p1.4. 2. mp = missed packets 3. per = packet error rate 7.2.10. results (per test) 7.2.10.1. per measurement the result of per measurement is shown on the lcd displa y. connecting to the gpio and the trigger the user can see the following signals. figure 55. in figure 55, the top trace shows the trigger provided on p1.4 of the sdb, the middle trace shows the received data and the bottom trace shows the transm itted data from the rf signal generator. in the plot we can see the receiver is turned on before the packet arrived. once the valid packet is received the radio will return to tune mode. the ra dio will switch to receive mode prior to sending the next trigger. this is repeated for the value set in ?max. packets?. 7.2.10.2. other receiver measurements: using the test setup described above, users may also pe rform automatic frequency control (afc), blocking and selectivity tests. all the required parameters are controlled by the external rf generator.
sdbc-dk3 ug rev. 0.4 39 7.3. additional information 7.3.1. usb communications to enable greater analysis of the data information rega rding the test is sent out over the usb and can be viewed via a serial terminal emulator such as the wds terminal emulator found on the wds cdrom. to configure the msc-dbsb8 software development board to communicate with a pc vi a the usb port, a virtual serial port driver needs to be installed on the pc. when the msc-dbsb8 is connected, you may be prompted to insta ll the virtual com port driver. this driver can be found on the wds cdrom. the virtual com port settings of the soft ware development board are as follows: ? data rate is 19.2 kbps ? 1 stop bit ? no parity bit ? no handshake if usb to virtual serial port driver is installed correctly, when the software development board is connected to pc by usb port and the wds terminal emulator is running, test results like following can be seen in figure 56. figure 56. figure 3:test result displayed by usb virtual com port
sdbc-dk3 ug 40 rev. 0.4 7.3.2. packet structure the packet structure used by this demonstration is very si mple but is not much different than a typical packet found in many rf applications today. figure 57. packet format defined in the packet error rate test
sdbc-dk3 ug rev. 0.4 41 8. custom software development initially the sdbc-dk3 softwa re development kit offers th e ability to become acquaint ed with the basic capabilities of the ezradiopro product family, however, the kit is also designed to be used for basic code development on any of the rf products offered by silicon laboratories. by de sign, the kit offers two modes of operation; demonstration mode or lab mode. the source code to th e factory firmware is availa ble on the wds cdrom but may be somewhat complex for use as reference code. to aid in software development t he following chapter maybe used to illustrate basic code segment to create rf links using the ezradiopro platform. the code set forth in the following chapter demonstrates a simple push button application and is based upon the ezradiopro si443x transceiver using the c8051f930 microcontroller. 8.1. program structure figure 58. basic program structure block diagram (1 of 4) program start main ( ) mcu hardware initialization i/o port definition system clock init hardware spi initialization rf hardware initialization read and clear all interrupt status registers registers: 0x03, 0x04 sw reset register: 0x07 software reset the chip ? wait for chip to be in ready mode ?ichipready? registers: 0x05, 0x06, 0x03, 0x04 is the chip in ready ?
sdbc-dk3 ug 42 rev. 0.4 figure 59. basic program structure block diagram (2 of 4) set vcocurrenttrimming, dividercurrenttrimmingagcoveride, and deltasigmaadctuning value for optimization specific to chip version registers: 0x5a, 0x59, 0x6a, 0x68 set capacitance bank to adjust the offset register: 0x09 chip version v2 ? tx/rx offset? set center frequency of operation register: 0x75, 0x76, 0x77 configuring gpios register: 0x0b, 0x0c, 0x0d specific data rate and modem settings ? set up sync words 2 & 3 register: 0x37, 0x36 customize sync words? using gipos ? please use ezradiopro register calculator to configures the rf chip?s modem for different (predefined) data rate, deviation, and modulation index requirements. set tx/rx header for header check register: 0x32, 0x33 use tx/rx header ?
sdbc-dk3 ug rev. 0.4 43 figure 60. basic program structure block diagram (3 of 4) rf chip in idle mode set register 0x07 ( 0x8701 ) set register 0x07 ( 0x8705 ) rf chip in receive mode while (1) continuous receive mode rfreceive () button pushed ? pb1_pin == 0 no build packet 1) strcpy(&packet[0],"payload") yes rfpacketreceived ( &packet[0],&length) ) return: rf_no_packet nirq interrupt occurred? read out interrupt status registers read registers: 0x03, 0x04 packet received interrupt ? crc error interrupt occurred (itstatus1 & 0x01) == 0x01 packet received interrupt occurred (itstatus1 & 0x02) == 0x02 rftransmit ( &packet[0],&length) ) read packet length information return: rf_crc_error return: rf_no_packet
sdbc-dk3 ug 44 rev. 0.4 figure 61. basic program structure block diagram (4 of 4) do a burst read from fifo (<64 bytes) check packet for validation blink led to show packet received yes no rf chip in transmit mode set register 0x07 ( 0x8701 ) set packet length information do a burst write to fifo (<64 bytes) enable packet sent interrupt read out interrupt status registers set register 0x3e write register 0x7f ( write ) register 0x7f ( read ) set register 0x05 ( 0x8504 ) wait for packet sent interrupt while (rf_nirq_pin == 1) no packet sent sucessful yes read registers: 0x03, 0x04
sdbc-dk3 ug rev. 0.4 45 8.1.1. basic code overview main () (main.c) hardware initialization mcu hardware, system clock setup, and i/o init hardware spi pin definition (c8051.h) nsel and nirq pin definition spi read/write function protocol i.e., #define sysclk (16000000l/2) #define spi_clock (sysclk/4) //rf chip sbit(rf_nsel_pin, sfr_p1, 3); sbit(rf_nirq_pin, sfr_p0, 6); //spi port sbit(spi_miso_pin, sfr_p1, 1); sbit(spi_mosi_pin, sfr_p1, 2); sbit(spi_sck_pin, sfr_p1, 0); hardware spi setup (c8051.c) nsel and nirq pin setup spi read/write functions i.e., void sethwmasterspi(void) { spi1cfg = 0x40; //master spi, ckpha=0, ckpol=0 spi1cn = 0x00; //3-wire single master, spi enabled spi1ckr = (sysclk/(2*spi_clock))-1; spi1en = 1; // enable spi1 module //set nsel pins to high rf_nsel_pin = 1; } rf chip hardware and i/o init rf parameters definition (si4432.h) i.e., //define the default radio frequency #define freq_band_select 0x75 //frequency band select #define nominal_car_freq1 0xbb //default carrier frequency: 915 mhz #define nominal_car_freq2 0x80 rf hardware setup and parameters setting (si4432.c) i.e., // set frequency spirfwriteaddressdata((reg_write | frequencybandselect), freq_band_select); spirfwriteaddressdata((reg_w rite | nominalcarrierfrequency1), nominal_car_freq1); spirfwriteaddressdata((reg_write | nominalcarrierfrequency0), nominal_car_freq2); rf chip in continuous receive mode (main.c) check incoming data for valet packet blink led for valid packet response to push button command send data packet out
sdbc-dk3 ug 46 rev. 0.4 8.2. basic hardware connections figure 62. basic hardware connections c 8051f930 si4432 hw spi sck sdi sdo nsel nirq led 1 led 2 30mhz
sdbc-dk3 ug rev. 0.4 47 9. main the main module main.c should include the main () functi on that is called upon startup. the main function should first call several initialization routines and then the main program loop itself. many of the initialization and internal functions may be specific to the mcu hardware. in this example the main loop sets the rf device into a continuous receive mode and wait for any incoming packet(s). in addition, it also polls for a push button event by user. if a button is pressed, then it'll sends a payload out using the internal fifo and packet handler features of the ezradiopro device before returning to a continuous receive mode. 9.1. flow chart main ( ) figure 63. flow chart main() continuous loop in receive mode main 1) mcu and rf hardware init () 2) set rf chip in idle mode and start continuous receive mode button pressed ? yes yes no 1) blink the led 2) send a packet with <64 bytes of payload 3) disable transmission 4) start continuous receive again valid packet ? no blink led2 to show that the packet received
sdbc-dk3 ug 48 rev. 0.4 9.2. main source file /************************************************************************************ * * file --- main.c * * description * this is the main file of the project. * * created * silicon laboratories hungary ltd * * copyright * copyright 2008 silicon laboratories, inc. * http://www.silabs.com * *************************************************************************************/ /*------------------------------------------------------------------------------------- include -------------------------------------------------------------------------------------*/ #include "c8051.h" #include "si4432.h" /*-------------------------------------------------------------------------------------- function prototypes -------------------------------------------------------------------------------------*/ void hw_init(void); void delay_ms(uint8 delay); /* the real program starts here. */ /* after power-on, the first two tasks are the init of the mcu and the software development board. */ /* the main loop starts after that. while (1) means that it is a never ending loop. */ /*------------------------------------------------------------------------------------- main program -------------------------------------------------------------------------------------*/ void main (void) { idata uint8 packet[max_payload_length]; idata uint8 length; hw_init(); // initialize the mcu and the sw development board rfinithw(dr4800bps_dev45khz); // initialize the si4432 rfidle(); // set the radio into idle state rfreceive(); // start continuous receive
sdbc-dk3 ug rev. 0.4 49 the foreground loop continuously polls the nirq pin of the receiver. if the nirq is active (low), the microcontroller starts a status read. then reads out the data packets from the fifo. while (1) // stay in receiving mode { switch ( rfpacketreceived(&packet[0],&length) ) // check the status packet reception { case rf_no_packet: // chip is in rx mode, but no preamble detected yet if button#1 is pressed, the led1 will blink, and both the synthesizer and the power amplifier (pa) will be turned on. then the packet will be built, and transmitted via the fifo. once complete, the power amplifier will be turned off and the system will return to receive mode. if ( pb1_pin == 0 ) // on pb1, a packet send is initiated { while(pb1_pin == 0); // wait for release of the button led1_pin = 1; // blink the led length = 7; // send a packet (64 bytes payload) strcpy(&packet[0],"payload"); // set packet content rfidle(); // disable receiving rftransmit(&packet[0],length); // start packet transmission led1_pin = 0; // release the led rfidle(); // disable transmission rfreceive(); // start continuous receive again } break; at this point, the program is tests the packet length prior to a direct packet validation, blinking led2 if expected packet data is received. case rf_packet_received: // a packet received rfidle(); // disable the receiver if ( length == 7 ) // check packet content is valid { if ( memcmp(&packet[0], "payload", 7) == 0 ) { led2_pin = 1; // blink led2 if packet received delay_ms(100); led2_pin = 0; } } rfreceive(); // restart continuous receive break;
sdbc-dk3 ug 50 rev. 0.4 receiver will discard corrupted data packet and restart in continuous receive mode. case rf_crc_error: // packet received with wrong crc rfidle(); // disable receiver rfreceive(); // start continuous receive break; default: break; } } } /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + function name: void init(void) + description: this fun ction configures the hw + input: none + return: none + notes: none + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ void hw_init(void) { uint16 i; // disable the watchdog timer pca0md &= ~0x40; pca0md = 0x00; disableglobalit(); //i/o port init // p0.0 - skipped, open-drain, digital // p0.1 - skipped, open-drain, digital // p0.2 - skipped, open-drain, analog // p0.3 - skipped, open-drain, analog // p0.4 - tx0 (uart0), push-pull, digital // p0.5 - rx0 (uart0), open-drain, digital // p0.6 - skipped, open-drain, digital // p0.7 - skipped, open-drain, digital // p1.0 - sck (spi1), push-pull, digital // p1.1 - miso (spi1), open-drain, digital // p1.2 - mosi (spi1), push-pull, digital // p1.3 - skipped, push-pull, digital // p1.4 - skipped, push-pull, digital // p1.5 - skipped, push-pull, digital // p1.6 - skipped, push-pull, digital // p1.7 - skipped, push-pull, digital // p2.0 - skipped, open-drain, digital // p2.1 - skipped, open-drain, digital // p2.2 - skipped, push-pull, digital // p2.3 - skipped, push-pull, digital // p2.4 - skipped, push-pull, digital // p2.5 - skipped, push-pull, digital // p2.6 - skipped, push-pull, digital // p2.7 - skipped, push-pull, digital
sdbc-dk3 ug rev. 0.4 51 p0mdin = 0xf3; p0mdout = 0x10; p0skip = 0xcf; p1mdin = 0xff; p1mdout = 0xfd; p1skip = 0xf8; p2mdin = 0xff; p2mdout = 0xfc; p2skip = 0xff; sfrpage = config_page; p0drv = 0x10; p1drv = 0xfd; p2drv = 0xfc; sfrpage = legacy_page; xbr0 = 0x01; xbr1 = 0x40; xbr2 = 0x40; // set inputs p0 |= 0xe3; //set p0 inputs p1 |= 0x02; //set p1 inputs p2 |= 0x03; //set p2 inputs //default i/o port led1_pin = 0; led2_pin = 0; led3_pin = 0; led4_pin = 0; bled_pin = 0; lcd_nsel_pin = 1; lcd_a0_pin = 0; lcd_reset_pin = 0; // oscillator init: external xtal (16mhz), sysclk=xtal/2 oscxcn = 0x77; // 1ms delay for xtal stabilization for(i=0;i<500;i++); while ((oscxcn & 0x80) == 0); clksel = 0x01; //initialize spi sethwmasterspi(); led1_pin = 1; delay_ms(5); led2_pin = 1; delay_ms(5); led1_pin = 0; delay_ms(5); led2_pin = 0; }
sdbc-dk3 ug 52 rev. 0.4 /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + function name: void delay_ms(void) + description: this function generates milliseconds delay + input: number of milliseconds + return: none + notes: none + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ void delay_ms(uint8 delay) { xdata uint8 i; xdata uint16 j; for(i=0;i sdbc-dk3 ug rev. 0.4 53 10. si4432 the si4432.c module contains code for all si4432 relate d rf functions including rf setup parameters; status read, transmit, receive, and idle state. there is a global variable (a table) 'rfsettings', which contains the preset modem parameters for each set of different data rate s. these settings can be mo dified for other application specific settings using values calculated based on the data sheet or through the ez radiopro register calculator (available on wds cdrom). it is suggested to change an entire line in the table if a new setting is desired the rfinithw () function initializes rf chip registers, i/o ports, timer, and it routines needed by the rf stack. this function has to be called in the power-on routine. applicat ion specific parameters include: frequency band, carrier frequency, tx/rx headers, sync words, modem sett ing, test bus and gpio pin configurations. some of the core settings are listed below: 1. read interrupt status to release the pending interrupts 2. sw reset -> wait for por interrupt 3. disable all its, except chip ready -- 'ichiprdy' 4. set the non-default si4432 registers ?? set vco ?? set the agc ?? set adc reference voltage to 0.9v ?? set capacitance bank to adjust for adjust crystal ppm accuracy and tx/rx offsets ?? reset digital testbus, disable scan test ?? select nothing to the analog testbus ?? set center frequency ?? disable rx-tx headers ?? set the sync word ?? set gpios functionality ?? set modem and rf parameters according to the selected data rate the rfsetrfparameters() function configures the both the tx and rx rf parts of the radio for different (predefined) data rates, deviations and modulation index requirements. this sets up all of the modem settings in addition to the packet handler, crc, pr eamble, and preamble detection threshold. note: the modem setting is a very important part of the rf parameters configuration. to simplify; th ere is a table in the code to provide common parameter values for a number of data rate configurations, this can be seen below. the values shown have been derived using the ezradiopro register calculator, available on the wds cdrom or via the data sheet.
sdbc-dk3 ug 54 rev. 0.4 the rfidle() function sets the transceiver and the rf stack into an idle state independent of the actual state of the rf stack. it disables the transmit/receive mode and a ll the interrupts. it then reads the interrupt status registers from the radio and clears the it flags. the rftransmit() function starts packet transmission and ensures packets are sent successfully. the rfreceive() function enables packet reception by enabling th e receiver and setting up the relevant interrupts prior to and reading the interrupt status registers. the rfpacketreceived() function checks whether the packet is received or not. it reads the data packet from the fifo if all packet handlers and the crc are correct. table 6. registers bits register name register address ifbw: if filter bandwidth 0x1c cosr: clock recovery oversampling ratio 0x20 cro2: clock recovery offset 2 0x21 cro1: clock recovery offset 1 0x22 cro0: clock recovery offset 0 0x23 ctg1: clock recovery timing loop gain 1 0x24 ctg0: clock recovery timing loop gain 1 0x25 tdr1: tx data rate 1 0x6e tdr0: tx data rate 0 0x6f mmc1: modulation mode control 1 0x70 fdev: frequency deviation 0x72 afc: afc loop gear shift override 0x1d chargepumpct: charge pump current trimming override 0x58 ============================================================================ // this table contains the modem parameters for different data rates. see the comments for more details code uint8 rfsettings[nmbr_of_sample_setti ng][nmbr_of_parameter] = // revv2 { // ifbw, cosr, cro2, cro1, cro0, ctg1, ctg0, tdr1, tdr0, mmc1, fdev,afc, chargepumpct {0x01, 0x83, 0xc0, 0x13, 0xa9, 0x00, 0x05, 0x13, 0xa9, 0x20, 0x3a, 0x40, 0x80}, //dr: 2.4kbps, dev:+-36khz, bbbw: 75.2khz {0x04, 0x41, 0x60, 0x27, 0x52, 0x00, 0x0a, 0x27, 0x52, 0x20, 0x48, 0x40, 0x80}, //dr: 4.8kbps, dev: +-45khz, bbbw: 95.3khz {0x91, 0x71, 0x40, 0x34, 0x6e, 0x00, 0x18, 0x4e, 0xa5, 0x20, 0x48, 0x40, 0x80}, //dr: 9.6kbps, dev: +-45khz, bbbw:112.8khz {0x12, 0xc8, 0x00, 0xa3, 0xd7, 0x01, 0x13, 0x51, 0xec, 0x20, 0x13, 0x40, 0x80}, //dr: 10kbps, dev: +-12khz, bbbw: 41.7khz {0x13, 0x64, 0x01, 0x47, 0xae, 0x04, 0x46, 0xa3, 0xd7, 0x20, 0x13, 0x40, 0x80}, //dr: 20kbps, dev: +-12khz, bbbw: 45.2khz {0x02, 0x64, 0x01, 0x47, 0xae, 0x05, 0x21, 0x0a, 0x3d, 0x00, 0x20, 0x40, 0x80}, //dr: 40kbps, dev: +-20khz, bbbw: 83.2khz {0x05, 0x50, 0x01, 0x99, 0x9a, 0x06, 0x68, 0x0c, 0xcd, 0x00, 0x28, 0x40, 0x80}, //dr: 50kbps, dev: +-25khz, bbbw:112.8khz {0x9a, 0x3c, 0x02, 0x22, 0x22, 0x07, 0xff, 0x19, 0x9a, 0x00, 0x50, 0x00,0xc0}, //dr: 100kbps, dev: +-50khz, bbbw: 208 khz {0x89, 0x5e, 0x01, 0x5d, 0x86, 0x02, 0xab, 0x20, 0xc5, 0x00, 0x66, 0x00, 0xc0}, //dr: 128kbps, dev:+-64khz, bbbw:269.3khz }; ============================================================================
sdbc-dk3 ug rev. 0.4 55 10.1. flow chart 10.1.1. rf pack et received( ) figure 64. 10.1.2. rftransmit( ) figure 65. rf packet received () crc error interrupt occurred ? yes 1) disable receiver 2) return: rf_crc_error valid packet ? 1) get packet length from register 0x4b 2) do a fifo burst read from register 0x7f 3) disable receiver yes if nirq goes low 1) read out interrupt status 1 registers for valid packet bit no rftransmit () 1) set packet length with register 0x3e 2) do a burst write up to a maximum of 64 bits of data into the tx fifo using register 0x7f 3) enable packet sent interrupt with register 0x05 ? interrupt enable 1 read interrupt status registers 1 & 2 ? 0x03 and 0x04 wait for packet sent interrupt ? packet sent correctly yes no
sdbc-dk3 ug 56 rev. 0.4 10.2. si4432 header file /************************************************************************************* ** ** file --- si4432.h ** ** description ** header files for si4432 usage, cont ains rf specific definition and type declaration ** ** created ** silicon laboratories hungary ltd ** ** copyright ** copyright 2008 silicon laboratories, inc. ** http://www.silabs.com ** *************************************************************************************/ #ifndef si4432_h #define si4432_h #include "c8051.h" /* ========================================= * * application specific definitions * * ========================================= */ // define the default radio frequency #define freq_band_select 0x75 // frequency band select #define nominal_car_freq1 0xbb // default carrier frequency: 915 mhz #define nominal_car_freq2 0x80 //packet settings #define preamble_length (4) // 4 byte preamble #define pd_length (2) // pream ble detection threshold in nibbles the max length of the received data packet is defined here (in data bytes). #define max_payload_length (64) /* ========================================= * * d e f i n i t i o n s * * ========================================= */ // definitions for register usage #define reg_read (0x00) #define reg_write (0x80) #define nmbr_of_sample_setting (9) #define nmbr_of_parameter (13)
sdbc-dk3 ug rev. 0.4 57 /* ==========================================* * t y p e d e c l a r a t i o n * * ==========================================*/ // rf stack enumerations typedef enum _rf_enum { rf_ok = 0x00, // function response parameters rf_error_timing = 0x01, rf_error_parameter = 0x02, rf_packet_received = 0x03, rf_rx_fifo_almost_full = 0x04, rf_no_packet = 0x05, rf_crc_error = 0x06, } rf_enum; typedef enum _rf_sample_settings { // data rate; freq deviation; receiver bandwidth dr2400bps_dev36khz = 0, // dr = 2.4kbps; fdev = +-36khz; bbbw = 75.2khz; dr4800bps_dev45khz = 1, // dr = 4.8kbps; fdev = +-45khz; bbbw = 95.3khz; dr9600bps_dev45khz = 2, // dr = 9.6kbps; fdev = +-45khz; bbbw = 112.8khz; dr10000bps_dev12khz = 3, // dr = 10kbps; fdev = +-12khz; bbbw = 41.7khz; dr20000bps_dev12khz = 4, // dr = 20kbps; fdev = +-12khz; bbbw = 45.2khz; dr40000bps_dev20khz = 5, // dr = 40kbps; fdev = +-20khz; bbbw = 83.2khz; dr50000bps_dev25khz = 6, // dr = 50kbps; fdev = +-25khz; bbbw = 112.8khz; dr100000bps_dev50khz = 7, // dr = 100kbps; fdev = +-50khz; bbbw = 208khz; dr128000bps_dev64khz = 8, // dr = 128kbps; fdev = +-64khz; bbbw = 269.3khz; } rf_sample_settings; typedef enum _rf_reg_map // these settings are for silicon rev-v2 { devicetype = 0x00, deviceversion = 0x01, devicestatus = 0x02, interruptstatus1 = 0x03, interruptstatus2 = 0x04, interruptenable1 = 0x05, interruptenable2 = 0x06, operatingfunctioncontrol1 = 0x07, operatingfunctioncontrol2 = 0x08, crystaloscillatorloadcapacitance = 0x09, microcontrolleroutputclock = 0x0a, gpio0configuration = 0x0b, gpio1configuration = 0x0c, gpio2configuration = 0x0d, ioportconfiguration = 0x0e, adcconfiguration = 0x0f, adcsensoramplifieroffset = 0x10, adcvalue = 0x11, temperaturesensorcontrol = 0x12, temperaturevalueoffset = 0x13, wakeuptimerperiod1 = 0x14, wakeuptimerperiod2 = 0x15, wakeuptimerperiod3 = 0x16, wakeuptimervalue1 = 0x17, wakeuptimervalue2 = 0x18, lowdutycyclemodeduration = 0x19, lowbatterydetectorthreshold = 0x1a, batteryvoltagelevel = 0x1b, iffilterbandwidth = 0x1c,
sdbc-dk3 ug 58 rev. 0.4 afcloopgearshiftoverride = 0x1d, afctimingcontrol = 0x1e, clockrecoverygearshiftoverride = 0x1f, clockrecoveryoversamplingratio = 0x20, clockrecoveryoffset2 = 0x21, clockrecoveryoffset1 = 0x22, clockrecoveryoffset0 = 0x23, clockrecoverytimingloopgain1 = 0x24, clockrecoverytimingloopgain0 = 0x25, receivedsignalstrengthindicator = 0x26, rssithresholdforclearchannelindicator = 0x27, antennadiversityregister1 = 0x28, antennadiversityregister2 = 0x29, dataaccesscontrol = 0x30, ezmacstatus = 0x31, headercontrol1 = 0x32, headercontrol2 = 0x33, preamblelength = 0x34, preambledetectioncontrol = 0x35, syncword3 = 0x36, syncword2 = 0x37, syncword1 = 0x38, syncword0 = 0x39, transmitheader3 = 0x3a, transmitheader2 = 0x3b, transmitheader1 = 0x3c, transmitheader0 = 0x3d, transmitpacketlength = 0x3e, checkheader3 = 0x3f, checkheader2 = 0x40, checkheader1 = 0x41, checkheader0 = 0x42, headerenable3 = 0x43, headerenable2 = 0x44, headerenable1 = 0x45, headerenable0 = 0x46, receivedheader3 = 0x47, receivedheader2 = 0x48, receivedheader1 = 0x49, receivedheader0 = 0x4a, receivedpacketlength = 0x4b, analogtestbus = 0x50, digitaltestbus = 0x51, txrampcontrol = 0x52, plltunetime = 0x53, calibrationcontrol = 0x55, modemtest = 0x56, chargepumptest = 0x57, chargepumpcurrenttrimming_override = 0x58, dividercurrenttrimming = 0x59, vcocurrenttrimming = 0x5a, vcocalibration_override = 0x5b, synthesizertest = 0x5c, blockenableoverride1 = 0x5d, blockenableoverride2 = 0x5e, blockenableoverride3 = 0x5f, channelfiltercoefficientaddress = 0x60, channelfiltercoefficientvalue = 0x61, crystaloscillator_controltest = 0x62, rcoscillatorcoarsecalibration_override = 0x63, rcoscillatorfinecalibration_override = 0x64, ldocontroloverride = 0x65,
sdbc-dk3 ug rev. 0.4 59 deltasigmaadctuning1 = 0x67, deltasigmaadctuning2 = 0x68, agcoverride1 = 0x69, agcoverride2 = 0x6a, gfskfirfiltercoefficientaddress = 0x6b, gfskfirfiltercoefficientvalue = 0x6c, txpower = 0x6d, txdatarate1 = 0x6e, txdatarate0 = 0x6f, modulationmodecontrol1 = 0x70, modulationmodecontrol2 = 0x71, frequencydeviation = 0x72, frequencyoffset = 0x73, frequencychannelcontrol = 0x74, frequencybandselect = 0x75, nominalcarrierfrequency1 = 0x76, nominalcarrierfrequency0 = 0x77, frequencyhoppingchannelselect = 0x79, frequencyhoppingstepsize = 0x7a, txfifocontrol1 = 0x7c, txfifocontrol2 = 0x7d, rxfifocontrol = 0x7e, fifoaccess = 0x7f, } rf_reg_map; /* ========================================= * * f u n c t i o n p r o t o t y p e s * * ========================================= */ rf_enum rfinithw(u8 data_rate); rf_enum rfsetrfparameters(rf _sample_settings setting); rf_enum rfidle(void); rf_enum rftransmit(uint8 * packet, uint8 length); rf_enum rfreceive(void); rf_enum rfpacketreceived(uint8 * packet, uint8 * length); #endif
sdbc-dk3 ug 60 rev. 0.4 10.3. si4432 source file /************************************************************************************* ** ** file --- si4432.c ** ** description ** contains all si4432 rf functions ** ** created ** silicon laboratories hungary ltd ** ** copyright ** copyright 2008 silicon laboratories, inc. ** http://www.silabs.com ** *************************************************************************************/ #include "c8051.h" #include "si4432.h" /*-----------------------------------------------------------------------------------*/ /* global variables */ /*----------------------------------------------------------------------------------*/ // this table contains the modem parameters for different data rates. see the comments for more details code uint8 rfsettings[nmbr_of_sample_setti ng][nmbr_of_parameter] = // revv2 { // ifbw, cosr, cro2, cro1, cro0, ctg1, ctg0, tdr1, tdr0, mmc1, fdev, afc, chargepumpct {0x01, 0x83, 0xc0, 0x13, 0xa9, 0x00, 0x05, 0x13, 0xa9, 0x20, 0x3a, 0x40, 0x80}, //dr: 2.4kbps, dev:+-36khz, bbbw: 75.2khz {0x04, 0x41, 0x60, 0x27, 0x52, 0x00, 0x0a, 0x27, 0x52, 0x20, 0x48, 0x40, 0x80}, //dr: 4.8kbps, dev: +-45khz, bbbw: 95.3khz {0x91, 0x71, 0x40, 0x34, 0x6e, 0x00, 0x18, 0x4e, 0xa5, 0x20, 0x48, 0x40, 0x80}, //dr: 9.6kbps, dev: +-45khz, bbbw:112.8khz {0x12, 0xc8, 0x00, 0xa3, 0xd7, 0x01, 0x13, 0x51, 0xec, 0x20, 0x13, 0x40, 0x80}, //dr: 10kbps, dev: +-12khz, bbbw: 41.7khz {0x13, 0x64, 0x01, 0x47, 0xae, 0x04, 0x46, 0xa3, 0xd7, 0x20, 0x13, 0x40, 0x80}, //dr: 20kbps, dev: +-12khz, bbbw: 45.2khz {0x02, 0x64, 0x01, 0x47, 0xae, 0x05, 0x21, 0x0a, 0x3d, 0x00, 0x20, 0x40, 0x80}, //dr: 40kbps, dev: +-20khz, bbbw: 83.2khz {0x05, 0x50, 0x01, 0x99, 0x9a, 0x06, 0x68, 0x0c, 0xcd, 0x00, 0x28, 0x40, 0x80}, //dr: 50kbps, dev: +-25khz, bbbw:112.8khz {0x9a, 0x3c, 0x02, 0x22, 0x22, 0x07, 0xff, 0x19, 0x9a, 0x00, 0x50, 0x00, 0xc0}, //dr: 100kbps, dev: +-50khz, bbbw: 208 khz {0x89, 0x5e, 0x01, 0x5d, 0x86, 0x02, 0xab, 0x20, 0xc5, 0x00, 0x66,0x00, 0xc0}, //dr: 128kbps, dev:+-64khz, bbbw:269.3khz }; idata uint8 itstatus1,itstatus2; /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + function name: void rfinithw(void) + description: initializes the used i/o pins, spi and timer peripherals, + it routines needed for the rf stack + return: none + notes: 1) has to be called in the power-on routine + 2) it initializes the rf chip registers + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ rf_enum rfinithw(u8 data_rate) {
sdbc-dk3 ug rev. 0.4 61 rf_nsel_pin = 1; // initialize i/o port directions itstatus1 = spirfreadregister(interruptstatus1); // read interrupt status itstatus2 = spirfreadregister(interruptstatus2); // sw reset -> wait for por interrupt spirfwriteaddressdata((reg_write | operatingfunctioncontrol1), 0x80); // enable the por interrupt while ( rf_nirq_pin == 1); // wait for the por interrupt // disable all its, except 'ichiprdy' spirfwriteaddressdata((reg_write | interruptenable1), 0x00); spirfwriteaddressdata((reg_write | interruptenable2), 0x02); itstatus1 = spirfreadregister(interruptstatus1); itstatus2 = spirfreadregister(interruptstatus2); // set the non-default si4432 registers // set vco spirfwriteaddressdata((reg_write | vcocurrenttrimming), 0x7f); spirfwriteaddressdata((reg_write | dividercurrenttrimming), 0x40); // set the agc spirfwriteaddressdata((reg_write | agcoverride2), 0x0b); // set adc reference voltage to 0.9v spirfwriteaddressdata((reg_write | deltasigmaadctuning2), 0x04); the default value on power up should be able to oscillate the crystal. based on the crystal and pcb capacitance, these cap banks can be used to tune the tx/rx offset. // set cap. bank spirfwriteaddressdata((reg_write | crystaloscillatorloadcapacitance), 0xd7); // reset digital testbus, disable scan test spirfwriteaddressdata((reg_write | digitaltestbus), 41);//0x00); // select nothing to the analog testbus spirfwriteaddressdata((reg_write | analogtestbus), 0x0b); important: the band selector command (configuration command) should be sent prior to the receiver command since once band selection has been achieved, the synthesizer should be calibrated. calibration can be done by turning off and on the receiver chain using the receiver command. in the current application the receiver chain is continuously turned on. // set frequency spirfwriteaddressdata((reg_write | frequencybandselect), freq_band_select); spirfwriteaddressdata((reg_write | nominalcarrierfrequency1), nominal_car_freq1); spirfwriteaddressdata((reg_write | nominalcarrierfrequ ency0), nominal_car_freq2); // disable rx-tx headers, spirfwriteaddressdata((reg_write | headercontrol1), 0x00 ); spirfwriteaddressdata((reg_write | headercontrol2), 0x02 ); // set the sync word
sdbc-dk3 ug 62 rev. 0.4 figure 66. spirfwriteaddressdata((reg_write | syncword3), 0x2d); spirfwriteaddressdata((reg_write | syncword2), 0xd4); gpio definitions // set gpio0 to rx data spirfwriteaddressdata((reg_write | gpio0configuration), 0x14); // set gpio1 to tx state & gpio2 to rx state spirfwriteaddressdata((reg_write | gpio1configuration), 0x12); spirfwriteaddressdata((reg_write | gpio2configuration), 0x15); next, define your rf parameters based on application specific data rate, deviation, receive baseband bandwidth etc., // set modem and rf parameters according to the selected data rate rfsetrfparameters(data_rate); return rf_ok; }
sdbc-dk3 ug rev. 0.4 63 /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + function name: rf_enum rfsetrfparameters (rf_sample_settings setting) + description: this function configure s the rf part of the chip (both tx and rx) + for different (predefined) data rate, deviation an d modulation index + requirements. + return: rf_ok: the operation was successful + rf_error_p arameter: invalid paramete r, operation is ignored. + notes: + +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ rf_enum rfsetrfparameters(rf_sample_settings setting) { // setup the internal digital modem according the selected rf settings (data rate) spirfwriteaddressdata((reg_write | iffilterbandwidth), rfsettings[setting][0] ); spirfwriteaddressdata((reg_write | clockrecoveryoversamplingratio), rfsettings[setting][1]); spirfwriteaddressdata((reg_write | clockrecoveryoffset2), rfsettings[setting][2]); spirfwriteaddressdata((reg_write | clockrecoveryoffset1), rfsettings[setting][3]); spirfwriteaddressdata((reg_write | clockrecoveryoffset0), rfsettings[setting][4]); spirfwriteaddressdata((reg_write | clockrecoverytimingloopgain1), rfsettings[setting][5]); spirfwriteaddressdata((reg_write | clockrecoverytimingloopgain0), rfsettings[setting][6]); spirfwriteaddressdata((reg_write | txdatarate1), rfsettings[setting][7]); spirfwriteaddressdata((reg_write | txdatarate0), rfsettings[setting][8]); spirfwriteaddressdata((reg_write | modulationmodecontrol1), rfsettings[setting][9]); spirfwriteaddressdata((reg_write | frequencydeviation), rfsettings[setting][10]); spirfwriteaddressdata((reg_write | afcloopgearshiftoverride), rfsettings[setting][11]); spirfwriteaddressdata((reg_write | chargepumpcurrenttrimming_override), rfsettings[setting][12]); // enable packet handler & crc16 spirfwriteaddressdata((reg_write | dataaccesscontrol), 0x8d); spirfwriteaddressdata((reg_write | modulationmodecontrol2), 0x63); // set preamble length & detection threshold spirfwriteaddressdata((reg_write | preamblelength), (preamble_length << 1)); spirfwriteaddressdata((reg_write | preambledetectioncontrol), ( pd_length << 4)); spirfwriteaddressdata((reg_write | clockrecoverygearshiftoverride), 0x03); return rf_ok; }
sdbc-dk3 ug 64 rev. 0.4 /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + function name: rf_enum rfidle(void) + description: sets the transceiver and the rf stack into idle state, + independently of the actual state of the rf stack. + return: rf_ok: the operation was successful + notes: + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ rf_enum rfidle(void) { // disable transmitter and receiver spirfwriteaddressdata((reg_write | operatingfunctioncontrol1), 0x01); // disable all its spirfwriteaddressdata((reg_write | interruptenable1), 0x00); spirfwriteaddressdata((reg_write | interruptenable2), 0x00); // read the interrupt status registers from the radio to clear the it flags itstatus1 = spirfreadregister(interruptstatus1); itstatus2 = spirfreadregister(interruptstatus2); return rf_ok; } /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + function name: rf_enum rf transmit(uint8 * packet, uint8 length) + description: starts packet transmission + input: message structure + return: rf_ok: the packet sent correctly + + notes: + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ rf_enum rftransmit(uint8 * packet, uint8 length) { uint8 temp8; // set packet length spirfwriteaddressdata((reg_write | transmitpacketlength), length); for(temp8=0;temp8 sdbc-dk3 ug rev. 0.4 65 itstatus2 = spirfreadregister(interruptstatus2); // wait for the packet sent interrupt while(rf_nirq_pin == 1); // packet is sent correctly return rf_ok; } /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + function name: rf_enum rfreceive(void) + description: starts packet reception + input: none + return: rf_ok: the operation was successful + notes: + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ rf_enum rfreceive(void) { // enable receiver chain spirfwriteaddressdata((reg_write | operatingfunctioncontrol1), 0x05); // enable the wanted its spirfwriteaddressdata((reg_write | interruptenable1), 0x13); spirfwriteaddressdata((reg_write | interruptenable2), 0x00); // read interrupt status registers itstatus1 = spirfreadregister(interruptstatus1); itstatus2 = spirfreadregister(interruptstatus2); return rf_ok; }
sdbc-dk3 ug 66 rev. 0.4 /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + function name: rf_enum rfpacketreceived (uint8 * packet, uint8 * length) + description: check whether the packet received or not. + input: pointers for storing data and length + return: rf_packet_received: packet received + rf_no_packet: packet is not yet received + rf_crc_error: received a packet with crc error + notes: + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ rf_enum rfpacketreceived (uint8 * packet, uint8 * length) { xdata uint8 i; // check if it occurred or not if( rf_nirq_pin == 0 ) { /* check what caused the interrupt */ // read out it status register itstatus1 = spirfreadregister(interruptstatus1); itstatus2 = spirfreadregister(interruptstatus2); // packet received interrupt occurred if( (itstatus1 & 0x02) == 0x02) { // read buffer *length = spirfreadregister(receivedpacketlength) ; for(i=0;i<*length;i++) { *packet++ = spirfreadregister(fifoaccess); } // disable receiver spirfwriteaddressdata((reg_write | operatingfunctioncontrol1), 0x01); return rf_packet_received; } // crc error interrupt occurred if( (itstatus1 & 0x01) == 0x01 ) { // disable receiver spirfwriteaddressdata((reg_write | operatingfunctioncontrol1), 0x01); return rf_crc_error; } } return rf_no_packet; }
sdbc-dk3 ug rev. 0.4 67 11. c8051 the c8051.c module contains all the low level, 8051 de pendent functions. the code mostly comprises of hardware spi setup and spi read/ write function calls. the sethwmasterspi() function initializes the 3-wire hw spi port. this does not control the nsel pin. the nsel pin is controlled separately by rf_nsel_pin. the spiwrite() function sends data through the spi port (8 bits length). the nsel pin is controlled separately by rf_nsel_pin. the spireadwrite() function sends and reads data via th e spi port (8 bits length). the nsel pin is controlled separately by rf_nsel_pin. the spirfwriteaddressdata() function sends data through t he spi port (16 length - 8 bits address, 8 bits data). this function controls the nsel pin. the spirfwriteaddressdata() function reads the current valu e of the register. this func tion controls the nsel pin. 11.1. c8051 header file /************************************************************************************* * ** ** file --- c8051.h ** ** description ** contains the 8051 specific declarations, io declarations, type declarations ** ** created ** silicon laboratories hungary ltd ** ** copyright ** copyright 2008 silicon laboratories, inc. ** http://www.silabs.com ** ************************************************************************************** / #ifndef c8051_h #define c8051_h #include // compiler declarations #include #include #include #include
sdbc-dk3 ug 68 rev. 0.4 /* ========================================== * * t y p e d e c l a r a t i o n * * ========================================== */ //only these types of variables are used in this software #undef uint8 #undef sint8 #undef uint16 #undef sint16 #undef uint32 #undef sint32 #define uint8 unsigned char #define sint8 signed char #define uint16 unsigned short #define sint16 signed short #define uint32 unsigned long #define sint32 signed long typedef struct { unsigned int bit0 : 1; unsigned int bit1 : 1; unsigned int bit2 : 1; unsigned int bit3 : 1; unsigned int bit4 : 1; unsigned int bit5 : 1; unsigned int bit6 : 1; unsigned int bit7 : 1; } reg; typedef union { reg testreg; uint8 adat; }reg_union; typedef union { reg_union bytes[2]; uint16 adat; }reg16_union; /* ===========================================* * d e f i n i t i o n s * * ===========================================*/ #undef true #undef false #undef input #undef output #define true (1) #define false (0) #define input (1) #define output (0)
sdbc-dk3 ug rev. 0.4 69 i/o definitions. the rf_nsel_pin and rf_nirq_pin port are created separately as the hardware spi ports use only 3-wires. //i/o pin definitions sbit(led1_pin, sfr_p1, 4); sbit(led2_pin, sfr_p1, 5); sbit(led3_pin, sfr_p1, 6); sbit(led4_pin, sfr_p1, 7); sbit(bled_pin, sfr_p2, 2); sbit(pb1_pin, sfr_p0, 0); sbit(pb2_pin, sfr_p0, 1); sbit(pb3_pin, sfr_p2, 0); sbit(pb4_pin, sfr_p2, 1); //rf chip sbit(rf_nsel_pin, sfr_p1, 3); sbit(rf_nirq_pin, sfr_p0, 6); //spi port sbit(spi_miso_pin, sfr_p1, 1); sbit(spi_mosi_pin, sfr_p1, 2); sbit(spi_sck_pin, sfr_p1, 0); //test card eeprom sbit(ee_nsel_pin, sfr_p2, 6); //lcd sbit(lcd_nsel_pin, sfr_p2, 5); sbit(lcd_a0_pin, sfr_p2, 3); sbit(lcd_reset_pin, sfr_p2, 4); sbit(lcd_bl_pin, sfr_p2, 7); #define sysclk (16000000l/2) // sysclk frequency in hz #define spi_clock (sysclk/4) #define enableglobalit() ea = 1 #define disableglobalit() ea = 0 /* ========================================== * * f u n c t i o n p r o t o t y p e s * * ========================================== */ void sethwmasterspi(void); void spiwrite(uint8 spi_in); uint8 spireadwrite(uint8 spi_in); void spiwritebyte(uint8 spi_in); void spirfwriteaddressdata(uint8 address, uint8 d); uint8 spirfreadregister(uint8 address); uint8 spireadbytefromtestcardeeprom(uint16 address); void spiwritebytetotestcardeeprom(uint16 address, uint8 d); void spireadsegmentfromtestcardeeprom(uint16 start_address, uint8 * d, uint8 length); #endif
sdbc-dk3 ug 70 rev. 0.4 11.2. c8051 source file /************************************************************************************* ** file --- c8051.c ** ** description ** contains all the low level, 8051 dependent functions ** ** created ** silicon laboratories hungary ltd ** ** copyright ** copyright 2008 silicon laboratories, inc. ** http://www.silabs.com ** *************************************************************************************/ #include "c8051.h" /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + function name: void sethwmasterspi(void) + description: initialize the hw spi port + input: data + return: none + notes: it doesn't control the nsel pin + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ void sethwmasterspi(void) { spi1cfg = 0x40; //master spi, ckpha=0, ckpol=0 spi1cn = 0x00; //3-wire single master, spi enabled spi1ckr = (sysclk/(2*spi_clock))-1; spi1en = 1; // enable spi1 module //set nsel pins to high rf_nsel_pin = 1; }
sdbc-dk3 ug rev. 0.4 71 /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + function name: void spiwrite(uint8 spi_in) + description: sends 8 bits length data through the spi port + input: data + return: none + notes: it doesn't control the nsel pin + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ void spiwrite(uint8 spi_in) { spi1dat = spi_in; //write data into the spi register while( spif1 == 0); //wait for sending the data spif1 = 0; //clear interrupt flag } /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + function name: uint8 spireadwrite(uint8 data) + description: sends and read 8 bits length data through the spi port + input: data + return: received byte + notes: it doesn't control the nsel pin + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ uint8 spireadwrite(uint8 spi_in) { spi1dat = spi_in; //write data into the spi register while( spif1 == 0); //wait for sending the data spif1 = 0; //clear interrupt flag return spi1dat; //read received bytes } /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + function name: void spirf writeaddressdata(uint8 address, uint8 data1) + description: sends 16 length data through the spi port (address and data) + input: address - register address + data - 8bit data + return: none + notes: it controls the nsel pin + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ void spirfwriteaddressdata(uint8 address, uint8 d) { rf_nsel_pin = 0; spiwrite(address); spiwrite(d); rf_nsel_pin = 1; }
sdbc-dk3 ug 72 rev. 0.4 /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + function name: uint8 spireadregister(uint8 address) + description: read a register of the radio + input: address - register address + return: value of the register + notes: it controls the nsel pin of the radio + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ uint8 spirfreadregister(uint8 address) { uint8 temp8; rf_nsel_pin = 0; spireadwrite( address ); temp8 = spireadwrite( 0x00 ); rf_nsel_pin = 1; return temp8; }
sdbc-dk3 ug rev. 0.4 73 12. troubleshooting q1: my software development board (sdb) displays an error message on startup. a1: factory firmware is designed to operate with officia lly approved testcards. the ebi d (see figure 20, ?test card characteristics eeprom (ebid),? on page 17) contain an authentication code to enab le the use of the testcard with the factory firmware. note: the ebid is only used in conjunction with factory fi rmware. ebid restrictions ar e not implemented by default in customer firmware. figure 67. error message the standard error message highlights 1. a missing testcard 2. a missing eeprom 3. an invalid eeprom authentication code in addition, the firmware revision is highlighted in order for technical support to assist you. q2: after the silicon labs sp lash screen (which contains the firmware revision), there is an additional screen shown before the setup menu 's - what is this for? a2: authentication codes in the ebid e nable the silicon labs to qualify a factory firmwar e build to a particular testcard. if you received these message screens then a testcard is either an engineering testcard or is a specially modified testcard for specific customers. customers th at have opened a technical support request and that have special requirements may hav e received modified testcards?in this event, a notification will be displayed.
sdbc-dk3 ug 74 rev. 0.4 d ocument c hange l ist revision 0.2 to revision 0.3 ? added lab mode instructions. ? added software programmers guide. ? updated "7.1.3. screen 3: setting up further rf parameters" on page 14. ? updated "7.1.8. running the demonstration" on page 20. ? updated "7.2. lab mode" on page 22. ? added table 5, ?test cards available for ordering,? on page 22. revision 0.3 to revision 0.4 ? updated sdbc package kit to reflect new contents. ?? antenna diversity and split card no longer supplied in the kit.
sdbc-dk3 ug rev. 0.4 75 n otes :
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