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in t e l corporation assumes no responsi b il i t y for the use of any circuitry o t her t h a n circuit r y embod i ed in an in t e l produc t . no other circuit pa t e n t l icenses are i mpl i ed . i nfor m ati o n contain e d here i n supersedes previous l y p u blis h ed spec i f i cations on these devices f rom intel. ? i n tel corpor a t i on, 2004 august 2004 o rder number: 272543-003 ? 8xc 1 96 m h indu s tr i al mo t o r c o nt r o l chm o s m i cr o c o nt r ol l e r t he 8 x c196m h is a me m ber of in t els f a m i ly o f 16 - b i t mc s ? 9 6 m icrocon t rollers . i t is designed prim a ri l y t o con t rol th r ee-phase ac indu c tion and d c brushle s s m o tor s . i t f ea t ures an enhanced t hree-ph a se wa v efor m genera t or spe c i f ically designed fo r u se i n in v erte r mo t or-c o ntrol applica t i on s . t his peripheral provide s pul s e - width modula t i o n and t hree-pha s e sine w ave gene r ation w i t h m i ni m al cp u inter v ention . i t ge n erate s t h re e co m plemen t ary non - overlapping p w m pulse s with re s olutions o f 0 . 125 s ( edge t r i g g ered) or 0 . 250 s (cen t ered) . t he 8 x c196m h ha s t wo d ed i c ated se r i al por t periphe r a l s , allow i n g les s s of t ware overhead . the wa t chdog ti m e r can be p r ogram m ed w i t h one o f f our tim e op t i o ns. t h e 8 xc19 6 m h is availabl e as the 80c196mh, which does not have on-chip rom, the 87c196mh , which contains 32 kbytes of on-chip otprom* or factory programmed rom, and the 83c196mh, whic h contains 32 kbytes of factory programmed mask rom. it is available in 84-lead plcc, 80-lead shrink eiaj/qfp , and 64-lead sdip. the 64-lead package does not contain pins for the p5.1/inst and p6.7/pwm1 signals . o per a t i onal char a c ter i s ti c s are guara n t ee d o ver the t e m per a t ure rang e o f C 4 0 c t o + 8 5 c . * o ne - ti m e p r og r a m m a ble r e a d -o n ly m e m o ry ( o t prom ) is si m ilar to epro m b ut c o m e s in a n u nwi n dow e d p ack a ge an d c a n n o t b e e r as e d . i t is u s e r p r o g r a m m a b le . h i g h p er f o rm a n c e c h m o s 16 - b i t c p u 1 6 m h z o per a t i n g f r e q u e n c y 3 2 k by t e s o f o n - c h i p o t p r o m / r o m 74 4 b yte s o f o n - c h i p r e g i ster ra m r e g iste r - t o -re g i ster arc h i tec t u r e 1 6 p r i o r i t i z e d i n ter r u p t s o u rce s pe r i p h er a l t r a n sact i o n s erve r ( p t s ) w i t h 1 5 pr i or i t i ze d s o u rce s u p t o 52 i / o l i n e s 3 - p h a se c o m p l e m e n t ar y w ave f o r m g ener a t o r 8-c h a n ne l 8 - o r 10 - b i t a/d w it h sam p l e a n d h o l d 2- c h a n n e l u a r t e v e n t p roc e s sor arra y ( e p a ) w i t h 2 h i g h - s p ee d c apt u re / co m pare m o du les a n d 4 h i g h - s p ee d c om p are- o n ly m o du le s tw o p r ogramm a b l e 16 - b i t t i mer s w i t h qu a d rat u r e c o u nt i n g i n pu t s tw o p u l se - w i d t h m o d u l a t o r ( p w m ) o u t p u t s w i t h h i g h drive ca p ab i l ity f l ex i b le 8- or 16 - b i t e xter n a l bu s 1 . 7 5 s 1 6 1 6 m u l t i p l y 3 s 32/ 1 6 d i vi d e e xt e n d e d t e m p e r a t ure av a i l a b l e i d le an d p o w erd o w n m o d e s w a t c h d o g t ime r
8xc196mh industrial motor control chmos microcontroller ? 2 figure 1. 8xc196mh block diagram timer 1 timer 2 event processor array 3-phase waveform generator port 2 microcode engine ralu cpu peripheral transaction server 32k on-chip rom/ otprom port 4 ad15:8 port 3 ad7:0 port 5 control signals interrupt controller 16 8 744 byte register file memory controller queue port 6 port 6 waveform generator a2542-01 port 2 sio, epa 2 capture/compare 4 compare port 1 sio 0 sio 1 port 1 serial i/o baud rate generator port 0 a/d port 0 8/10-bit a/d converter mux s/h 24 bytes cpu sfrs watchdog timer extint pwm0 pwm1 8 8 4 4 26 8 6 2 8 8
8xc196 m h indu s t ria l m o t o r c o n t r o l ch m o s m i cr o c o nt r o l l e r ? 3 proc e s s infor m atio n thi s devi c e is manu f ac t ured o n p x 2 9 .5 , a chm os i v proce s s. a dditional proce s s and reliab i li t y i n f or m atio n i s available in i ntels componen t s q uali t y an d rel i a b i lit y han d boo k ( order numbe r 210997 ) . all t h ermal i m pedance data i s approxi m ate for s t ati c air c onditions a t 1 wa t t o f po w er d i s sipation . value s wi l l cha n ge d epending on operating c ond i t ions an d the applica t i o n. t he in t el pac k agin g handbook ( o rde r number 240800 ) d e scribe s i ntels t herm a l imp e danc e tes t m e t hodology . ta b l e 1 . t h erma l charac t erist i c s packa g e ty p e j a j c 84-lead plc c 3 3 c/ w 1 1 c / w 80-lead q f p 5 6 c/ w 1 2 c / w 64-lead sd i p 5 6 c/ w n / a f i g ure 2. t h e 8xc196 m h f am i l y n o me n cla t ur e x xx 8 x c 196 xx xx device speed: product family: no mark = 16 mhz k x , m x , n x chmos technology program memory options: 0 = romless, 3 = rom, 7 = otprom package - type options: temperature and burn in options: a2759-01 x = sdip, x = plcc, x = qfp x = C40?c C +85?c ambient with intel standard burn-in to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x". note:
8xc196mh industrial motor control chmos microcontroller ? 4 table 2. 8xc196mh memory map address (1) description notes 0ffffh 0a000h external memory 09fffh 02080h internal rom/otprom or external memory 0207fh 0205eh reserved 1, 2 0205dh 02040h pts vectors 0203fh 02030h interrupt vectors (upper) 0202fh 02020h rom/otprom security key 0201fh 0201ch reserved 1, 2 0201bh reserved (must contain 20h) 0201ah ccb1 02019h reserved (must contain 20h) 02018h ccb0 02017h 02014h reserved 02013h 02000h interrupt vectors (lower) 01fffh 01f00h internal sfrs 1 1effh 300h external memory 2ffh 18h register ram 3 17h 00h cpu sfrs 1 notes: 1. unless otherwise noted, write 0ffh to reserved memory locations and write 0 to reserved sfr bits. 2. warning: the contents and/or function of reserved locations may change with future revisions of the device. 3. code executed in locations 0000h to 02ffh will be forced external.
8xc196mh industrial motor control chmos microcontroller ? 5 table 3. signals arranged by functional categories address & data programming control input/output input/output (contd) ad15:0 ainc# p0.0/ach0 p2.5/comp1 cpver p0.1/ach1 p2.6/comp2 bus control & status pact# p0.2/ach2 p2.7/sclk1#/bclk1 ale/adv# pale# p0.3/ach3 p3.7:0 bhe#/wrh# pbus15:0 p0.4/ach4 p4.7:0 buswidth pmode.3:0 p0.5/ach5 p5.7:0 inst prog# p0.6/ach6/t1clk p6.0/wg1# ready pver p0.7/ach7/t1dir p6.1/wg1 rd# p1.0/txd0 p6.2/wg2# wr#/wrl# processor control p1.1/rxd0 p6.3/wg2 ea# p1.2/txd1 p6.4/wg3# power & ground extint p1.3/rxd1 p6.5/wg3 angnd nmi p2.0/epa0 p6.6/pwm0 v cc once# p2.1/sclk0#/bclk0 p6.7/pwm1 v pp reset# p2.2/epa1 v ref xtal1 p2.3/comp3 v ss xtal2 p2.4/comp0 note: the following signals are not available in the 64-pin package: p5.1, p6.7, inst, and pwm1.
8xc196mh industrial motor control chmos microcontroller ? 6 figure 3. 8xc196mh 64-lead shrink dip (sdip) package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 xx8xc196mh top view (looking down on component side of pc board) p5.6/ready p5.4/once# extint v ss xtal1 xtal2 p6.6/pwm0 p2.7/sclk1#/bclk1 p2.6/comp2/cpver p2.5/comp1/pact# p2.4/comp0/ainc# p2.3/comp3 p2.2/epa1/prog# p2.1/sclk0#/bclk0/pale# p2.0/epa0/pver p0.0/ach0 p0.1/ach1 p0.2/ach2 p0.3/ach3 p0.4/ach4/pmode.0 p0.5/ach5/pmode.1 v ref angnd p0.6/ach6/t1clk/pmode.2 p0.7/ach7/t1dir/pmode.3 p1.0/txd0 p1.1/rxd0 p1.2/txd1 p1.3/rxd1 p6.0/wg1# p6.1/wg1 p6.2/wg2# v ss p5.0/ale/adv# v pp p5.3/rd# p5.5/bhe#/wrh# p5.2/wr#/wrl# p5.7/buswidth p4.6/ad14/pbus.14 p4.5/ad13/pbus.13 p4.7/ad15/pbus.15 v cc p4.4/ad12/pbus.12 p4.3/ad11/pbus.11 p4.2/ad10/pbus.10 p4.1/ad9/pbus.9 p4.0/ad8/pbus.8 p3.7/ad7/pbus.7 p3.6/ad6/pbus.6 p3.5/ad5/pbus.5 p3.4/ad4/pbus.4 p3.3/ad3/pbus.3 p3.2/ad2/pbus.2 p3.1/ad1/pbus.1 p3.0/ad0/pbus.0 reset# nmi ea# v ss v cc p6.5/wg3 p6.4/wg3# p6.3/wg2 a2572-01
8xc196mh industrial motor control chmos microcontroller ? 7 table 4. 64-lead shrink dip (sdip) pin assignment pin name pin name pin name pin name 1v ss 17 p3.7/ad7 /pbus.7 33 p6.2/wg2# 49 p0.0/ach0 2 p5.0/ale/adv# 18 p3.6/ad6 /pbus.6 34 p6.1/wg1 50 p2.0/epa0/pver 3v pp 19 p3.5/ad5 /pbus.5 35 p6.0/wg1# 51 p2.1/sclk0# /bclk0/pale# 4 p5.3/rd# 20 p3.4/ad4 /pbus.4 36 p1.3/rxd1 52 p2.2/epa1 /prog# 5 p5.5/bhe#/wrh# 21 p3.3/ad3 /pbus.3 37 p1.2/txd1 53 p2.3/comp3 6 p5.2/wr#/wrl# 22 p3.2/ad2 /pbus.2 38 p1.1/rxd0 54 p2.4/comp0 /ainc# 7 p5.7/buswidth 23 p3.1/ad1 /pbus.1 39 p1.0/txd0 55 p2.5/comp1 /pact# 8 p4.6/ad14 /pbus.14 24 p3.0/ad0 /pbus.0 40 p0.7/ach7/t1dir /pmode.3 56 p2.6/comp2 /cpver 9 p4.5/ad13 /pbus.13 25 reset# 41 p0.6/ach6 /t1clk/pmode.2 57 p2.7/sclk1# /bclk1 10 p4.7/ad15 /pbus.15 26 nmi 42 angnd 58 p6.6/pwm0 11 v cc 27 ea# 43 v ref 59 xtal2 12 p4.4/ad12 /pbus.12 28 v ss 44 p0.5/ach5 /pmode.1 60 xtal1 13 p4.3/ad11 /pbus.11 29 v cc 45 p0.4/ach4 /pmode.0 61 v ss 14 p4.2/ad10 /pbus.10 30 p6.5/wg3 46 p0.3/ach3 62 extint 15 p4.1/ad9/pbus.9 31 p6.4/wg3# 47 p0.2/ach2 63 p5.4/once# 16 p4.0/ad8/pbus.8 32 p6.3/wg2 48 p0.1/ach1 64 p5.6/ready
8xc196mh industrial motor control chmos microcontroller ? 8 figure 4. 8xc196mh 84-lead plcc package 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 p2.5/comp1/pact# p2.4/comp0/ainc# nc nc p2.7/sclk1#/bclk1 p2.3/comp3 p2.2/epa1/prog# nc nc p2.1/sclk0#/bclk0/pale# p2.0/epa0/pver nc p0.0/ach0 p0.1/ach1 p0.2/ach2 p0.3/ach3 p0.4/ach4/pmode.0 p0.5/ach5/pmode.1 v ref angnd p0.6/ach6/t1clk/pmode.2 p4.7/ad15/pbus.15 p4.6/ad14/pbus.14 v cc p4.5/ad13/pbus.13 nc p4.4/ad12/pbus.12 p4.3/ad11/pbus.11 p4.2/ad10/pbus.10 p4.1/ad9/pbus.9 p4.0/ad8/pbus.8 nc nc p3.7/ad7/pbus.7 p3.6/ad6/pbus.6 p3.5.ad5/pbus.5 p3.4/ad4/pbus.4 p3.3/ad3/pbus.3 p3.2/ad2/pbus.2 p3.1/ad1/pbus.1 p3.0/ad0/pbus.0 nc p5.7/buswidth p5.2/wr#/wrl# nc p5.5/bhe#/wrh# p5.3/rd# v pp p5.0/ale/adv# v ss p5.1/inst p5.6/ready p5.4/once# extint v ss xtal1 xtal2 nc nc nc p6.6/pwm0 p6.7/pwm1 p2.6/comp2/cpver reset# nmi nc ea# v ss nc v cc p6.5/wg3 p6.4/wg3# p6.3/wg2 v ss p6.2/wg2# p6.1/wg1 p6.0/wg1# p1.3/rxd1 p1.2/txd1 nc nc p1.1/rxd0 p1.0/txd0 p0.7/ach7/t1dir/pmode.3 xx8xc196mh top view (looking down on component side of pc board) a2573-02
8xc196mh industrial motor control chmos microcontroller ? 9 table 5. 84-lead plcc pin assignment pin name pin name pin name pin name 1 p5.4/once# 22nc 43v ss 64 p2.0/epa0/pver 2 p5.6/ready 23 nc 44 p6.2/wg2# 65 p2.1/sclk0# /bclk0/pale# 3 p5.1/inst 24 p3.7/ad7 /pbus.7 45 p6.1/wg1 66 nc 4v ss 25 p3.6/ad6 /pbus.6 46 p6.0/wg1# 67 nc 5 p5.0/ale/adv# 26 p3.5/ad5 /pbus.5 47 p1.3/rxd1 68 p2.2/epa1 /prog# 6v pp 27 p3.4/ad4 /pbus.4 48 p1.2/txd1 69 p2.3/comp3 7 p5.3/rd# 28 p3.3/ad3 /pbus.3 49 nc 70 p2.7/sclk1# /bclk1 8 p5.5/bhe#/wrh# 29 p3.2/ad2 /pbus.2 50 nc 71 nc 9 nc 30 p3.1/ad1 /pbus.1 51 p1.1/rxd0 72 nc 10 p5.2/wr#/wrl# 31 p3.0/ad0 /pbus.0 52 p1.0/txd0 73 p2.4/comp0 /ainc# 11 p5.7/buswidth 32 nc 53 p0.7/ach7 /t1dir/pmode.3 74 p2.5/comp1 /pact# 12 p4.7/ad15 /pbus.15 33 reset# 54 p0.6/ach6 /t1clk/pmode.2 75 p2.6/comp2 /cpver 13 p4.6/ad14 /pbus.14 34 nmi 55 angnd 76 p6.7/pwm1 14 v cc 35 nc 56 v ref 77 p6.6/pwm0 15 p4.5/ad13 /pbus.13 36 ea# 57 p0.5/ach5 /pmode.1 78 nc 16 nc 37 v ss 58 p0.4/ach4 /pmode.0 79 nc 17 p4.4/ad12 /pbus.12 38 nc 59 p0.3/ach3 80 nc 18 p4.3/ad11 /pbus.11 39 v cc 60 p0.2/ach2 81 xtal2 19 p4.2/ad10 /pbus.10 40 p6.5/wg3 61 p0.1/ach1 82 xtal1 20 p4.1/ad9/pbus.9 41 p6.4/wg3# 62 p0.0/ach0 83 v ss 21 p4.0/ad8/pbus.8 42 p6.3/wg2 63 nc 84 extint
8xc196mh industrial motor control chmos microcontroller ? 10 figure 5. 8xc196mh 80-lead shrink eiaj/qfp package 1 2 3 4 5 6 7 8 9 10 12 17 13 14 16 18 19 11 15 20 21 24 25 26 28 2927 23 22 3938 37343230 31 33 35 36 40 42 41 43 44 45 46 47 48 49 52 53 50 51 55 54 56 57 59 58 60 61 62 63 64 65 6667 68 6973747679 77 75 72 71 70 80 78 p6.7/pwm1 p2.6/comp2/cpver p2.5/comp1/pact# p2.4/comp0/ainc# nc nc p2.7/sclk1#/bclk1 p2.3/comp3 p2.2/epa1/prog# p2.0/epa0/pver nc nc p0.6/ach6/t1clk/pmode.2 nc p2.1/sclk0#/bclk0/pale# angnd p0.0/ach0 p0.1/ach1 p0.2/ach2 p0.3/ach3 p0.4/ach4/pmode.0 v ref p0.5/ach5/pmode.1 p0.7/ach7/t1dir/pmode.3 p4.7/ad15/pbus.15 p5.2/wr#/wrl# p5.7/buswidth p4.6/ad14/pbus.14 v cc p4.5/ad13/pbus.13 nc p4.3/ad11/pbus.11 p4.4/ad12/pbus.12 p4.2/ad10/pbus.10 p3.7/ad7/pbus.7 p4.1/ad9/pbus.9 p4.0/ad8/pbus.8 p3.6/ad6/pbus.6 p3.4/ad4/pbus.4 p3.3/ad3/pbus.3 p3.1/ad1/pbus.1 p3.0/ad0/pbus.0 nmi nc ea# reset# p3.5/ad5/pbus.5 p3.2/ad2/pbus.2 v ss nc p6.4/wg3# p6.1/wg1 v cc p6.5/wg3 p6.3/wg2 v ss p6.2/wg2# p1.3/rxd1 p6.0/wg1# p1.2/txd1 nc nc p1.1/rxd0 p1.0/txd0 v pp p5.3/rd# p5.1/inst p5.0/ale/adv# p5.4/once# p5.6/ready v ss xtal1 extint xtal2 nc nc p6.6/pwm0 nc p5.5/bhe#/wrh# v ss xx8xc196mh top view (looking down on component side of pc board) a2574-01
8xc196mh industrial motor control chmos microcontroller ? 11 table 6. 80-lead shrink eiaj/qfp pin assignment pin name pin name pin name pin name 1 p5.2/wr#/wrl# 21 nc 41 p0.7/ach7/t1dir /pmode.3 61 p2.4/comp0 /ainc# 2 p5.7/buswidth 22 reset# 42 p0.6/ach6 /t1clk/pmode.2 62 p2.5/comp1 /pact# 3 p4.7/ad15 /pbus.15 23 nmi 43 angnd 63 p2.6/comp2 /cpver 4 p4.6/ad14 /pbus.14 24 ea# 44 v ref 64 p6.7/pwm1 5v cc 25 v ss 45 p0.5/ach5 /pmode.1 65 p6.6/pwm0 6 p4.5/ad13 /pbus.13 26 nc 46 p0.4/ach4 /pmode.0 66 nc 7nc 27v cc 47 p0.3/ach3 67 nc 8 p4.4/ad12 /pbus.12 28 p6.5/wg3 48 p0.2/ach2 68 nc 9 p4.3/ad11 /pbus.11 29 p6.4/wg3# 49 p0.1/ach1 69 xtal2 10 p4.2/ad10 /pbus.10 30 p6.3/wg2 50 p0.0/ach0 70 xtal1 11 p4.1/ad9/pbus.9 31 v ss 51 nc 71 v ss 12 p4.0/ad8/pbus.8 32 p6.2/wg2# 52 p2.0/epa0/pver 72 extint 13 p3.7/ad7/pbus.7 33 p6.1/wg1 53 p2.1/sclk0# /bclk0/pale# 73 p5.4/once# 14 p3.6/ad6/pbus.6 34 p6.0/wg1# 54 nc 74 p5.6/ready 15 p3.5/ad5/pbus.5 35 p1.3/rxd1 55 nc 75 p5.1/inst 16 p3.4/ad4/pbus.4 36 p1.2/txd1 56 p2.2/epa1 /prog# 76 v ss 17 p3.3/ad3/pbus.3 37 nc 57 p2.3/comp3 77 p5.0/ale/adv# 18 p3.2/ad2/pbus.2 38 nc 58 p2.7/sclk1# /bclk1 78 v pp 19 p3.1/ad1/pbus.1 39 p1.1/rxd0 59 nc 79 p5.3/rd# 20 p3.0/ad0/pbus.0 40 p1.0/txd0 60 nc 80 p5.5/bhe#/wrh#
8xc196mh industrial motor control chmos microcontroller ? 12 pin descriptions table 7. signal descriptions signal name type description multiplexed with ach7 ach6 ach5 ach4 ach3:0 i analog channels . these pins are analog inputs to the a/d converter. these pins are multiplexed with the port 0 pins. while it is possible for the pins to function simultaneously as analog and digital inputs, this is not recommended because reading the port while a conversion is in process can produce unreliable conversion results. the angnd and v ref pins must be connected for the a/d converter and the multiplexed port pins to function. p0.7/t1dir/pmode.3 p0.6/t1clk/pmode.2 p0.5/pmode.1 p0.4/pmode.0 p0.3:0 ad15:8 ad7:0 i/o address/data lines . these pins provide a multiplexed address and data bus. during the address phase of the bus cycle, address bits 0C15 are presented on the bus and can be latched using ale or adv#. during the data phase, 8- or 16-bit data is transferred. p4.7:0/pbus.15:8 p3.7:0/pbus.7:0 adv# o address valid . this active-low output signal is asserted only during external memory accesses. adv# indicates that valid address information is available on the system address/data bus. the signal remains low while a valid bus cycle is in progress and is returned high as soon as the bus cycle completes. an external latch can use the adv# signal to demultiplex the address from the address/data bus. used with a decoder, adv# can generate chip-selects for external memory. p5.0/ale ainc# i auto increment . in slave programming mode, this active-low input signal enables the autoincrement mode. auto increment allows reading from or writing to sequential otprom locations without requiring address transactions across the programming bus for each read or write. p2.4/comp0 ale o address latch enable . this active-high output signal is asserted only during external memory cycles. ale signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus. ale differs from adv# in that it is not returned high until a new bus cycle is to begin. an external latch can use ale to demultiplex the address from the address/data bus. p5.0/adv# angnd gnd analog ground . reference ground for the a/d converter and the logic used to read port 0. angnd must be held at nominally the same potential as v ss . bclk1 bclk0 i serial communications baud clock 0 and 1 . bclk0 and 1 are alternate clock sources for the serial ports. the maximum input frequency is f osc /4. p2.7/sclk1# p2.1/sclk0#/pale#
8xc196mh industrial motor control chmos microcontroller ? 13 bhe# o byte high enable . during 16-bit bus cycles, this active-low output signal is asserted for word reads and writes and for high-byte reads and writes to external memory. bhe# indicates that valid data is being transferred over the upper half of the system address/data bus. bhe#, in conjunction with a0, selects the memory byte to be accessed: bhe# a0 byte(s) accessed 0 0 both bytes 0 1 high byte only 1 0 low byte only p5.5/wrh# buswidth i bus width . when enabled in the chip configuration register, this active-high input signal dynamically selects the bus width of the bus cycle in progress. when buswidth is high, a 16- bit bus cycle occurs; when buswidth is low, an 8-bit bus cycle occurs. buswidth is active during a ccr fetch. p5.7 comp3 comp2 comp1 comp0 o event processor array (epa) compare pins . these signals are the output of the epa compare modules. these pins are multiplexed with other signals and may be configured as standard i/o. p2.3 p2.6/cpver p2.5/pact# p2.4/ainc# cpver o cumulative program verification . this active-high output signal indicates whether any verify errors have occurred since the device entered programming mode. cpver remains high until a verify error occurs, at which time it is driven low. once an error occurs, cpver remains low until the device exits programming mode. when high, cpver indicates that all locations have programmed correctly since the device entered programming mode. p2.6/comp2 ea# i external access . this active-low input signal directs memory accesses to on-chip or off-chip memory. if ea# is low, the memory access is off-chip. if ea# is high and the memory address is within 2000hC2fffh, the access is to on-chip rom or otprom. otherwise, an access with ea# high is to off-chip memory. ea# is sampled only on the rising edge of reset#. if ea# = v ea on the rising edge of reset#, the device enters the programming mode selected by pmode.3:0. for devices without rom, ea# must be tied low. epa1 epa0 i/o event processor array (epa) input/output pins . these are the high-speed input/output pins for the epa capture/compare modules. these pins are multiplexed with other signals and may be configured as standard i/o. p2.2/prog# p2.0/pver table 7. signal descriptions (continued) signal name type description multiplexed with
8xc196mh industrial motor control chmos microcontroller ? 14 extint i external interrupt . this programmable interrupt is controlled by the wg_protect register. this register controls whether the interrupt is edge triggered or sampled and whether a rising edge/high level or falling edge/low level activates the interrupt. this interrupt vectors through memory location 203ch. if the chip is in idle mode and if extint is enabled, a valid extint interrupt brings the chip back to normal operation, where the first action is to execute the extint service routine. after completion of the service routine, execution resumes at the instruction following the one that put the chip into idle mode. in powerdown mode, a valid extint interrupt causes the chip to return to normal operating mode. if extint is enabled, the extint service routine is executed. otherwise, execution continues at the instruction following the idlpd instruction that put the chip into powerdown mode. inst o instruction fetch . this active-high output signal is valid only during external memory bus cycles. when high, inst indicates that an instruction is being fetched from external memory. the signal remains high during the entire bus cycle of an external instruction fetch. inst is low for data accesses, including interrupt vector fetches and chip configu- ration byte reads. inst is low during internal memory fetches. p5.1 nmi i nonmaskable interrupt . in normal operating mode, a rising edge on nmi causes a vector through the nmi interrupt at location 203eh. nmi must be asserted for greater than one state time to guarantee that it is recognized. in idle mode, a rising edge on nmi brings the chip back to normal operation, where the first action is to execute the nmi service routine. after completion of the service routine, execution resumes at the instruction following the one that put the chip into idle mode. in powerdown mode, nmi causes a return to normal operating mode only if it is tied to extint. once# i on-circuit emulation . holding this pin low while the reset# signal transitions from a low to a high places the device into on-circuit emulation (once) mode. once mode isolates the device from other components in the system to allow the use of a clip-on emulator for system debugging. this mode puts all pins except xtal1 and xtal2 into a high- impedance state. to exit once mode, reset the device by pulling the reset# signal low. p5.4 table 7. signal descriptions (continued) signal name type description multiplexed with
8xc196mh industrial motor control chmos microcontroller ? 15 p0.7 p0.6 p0.5 p0.4 p0.3:0 i port 0 . this is a high-impedance, input-only port. port 0 pins should not be left floating. these pins may individually be used as analog inputs (ac h x ) or digital inputs (p0. x ). while it is possible for the pins to function simultaneously as analog and digital inputs, this is not recommended because reading port 0 while a conversion is in process can produce unreliable conversion results. angnd and v ref must be connected for port 0 and the a/d converter to function. ach7/t1dir/pmode.3 ach6/t1clk/pmode.2 ach5/pmode.1 ach4/pmode.0 ach3:0 p1.3 p1.2 p1.1 p1.0 i port 1 . this is a 4-bit, bidirectional, standard i/o port that is multiplexed with individually selectable special-function signals. (used as pbus.15:12 in auto-programming mode.) rxd1 txd1 rxd0 txd0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 i/o port 2 . this is an 8-bit, bidirectional, standard i/o port that is multiplexed with individually selectable special-function signals. p2.6 is multiplexed with a special test mode function. to prevent accidental entry into test modes, always configure p2.6 as an output. sclk1#/bclk1 comp2/cpver comp1/pact# comp0/ainc# comp3 epa1/prog# sclk0#/bclk0/pale# epa0/pver p3.7:0 i/o port 3 . this is an 8-bit, bidirectional, memory-mapped i/o port with open-drain outputs. the pins are shared with the multiplexed address/data bus, which has complementary drivers. in programming modes, port 3 serves as the low byte of the programming bus (pbus). ad7:0/pbus.7:0 p4.7:0 i/o port 4 . this is an 8-bit, bidirectional, memory-mapped i/o port with open-drain outputs. the pins are shared with the multiplexed address/data bus, which has complementary drivers. in programming modes, port 4 serves as the high byte of the programming bus (pbus). ad15:8/pbus.15:8 p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 i/o port 5 . this is an 8-bit, bidirectional, standard i/o port that is multiplexed with individually selectable control signals. because p5.4 is multiplexed with the once# function, always configure it as an output to prevent accidental entry into once mode. buswidth ready bhe#/wrh# once# rd# wr#/wrl# inst ale/adv# table 7. signal descriptions (continued) signal name type description multiplexed with
8xc196mh industrial motor control chmos microcontroller ? 16 p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 p6.0 o port 6 . this is an 8-bit output port that is multiplexed with the special functions of the waveform generator and pwm peripherals. the wg_out register configures the pins, establishes the output polarity, and controls whether changes to the outputs are synchronized with an event or take effect immediately. pwm1 pwm0 wg3 wg3# wg2 wg2# wg1 wg1# pact# o programming active . in auto-programming mode, pact# low indicates that programming activity is occurring. p2.5/comp1 pale# i programming ale . in slave programming mode, this active- low input indicates that ports 3 and 4 contain a command/address. when pale# is asserted, data and commands on ports 3 and 4 are read into the device. p2.1/sclk0#/bclk0 pbus.15:8 pbus.7:0 i/o programming bus . in programming modes, used as a bidirectional port with open-drain outputs to pass commands, addresses, and data to or from the device. used as a regular system bus to access external memory during auto- programming mode. when using slave programming mode, the pbus is used in open-drain i/o port mode (not as a system bus). in slave programming mode, you must add external pull-up resistors to read data from the device during the dump word routine. p4.7:0/ad15:8 p3.7:0/ad7:0 pmode.3 pmode.2 pmode.1 pmode.0 i programming mode select . determines the otprom programming algorithm that is to be performed. pmode is sampled after a device reset when ea# = v ea and must be stable while the device is operating. p0.7/ach7/t1dir p0.6/ach6/t1clk p0.5/ach5 p0.4/ach4 prog# i programming start . this active-low input is valid only in slave programming mode. the rising edge of prog# latches data on the pbus and begins programming. the falling edge of prog# ends programming. p2.2/epa1 pver o program verification . in programming modes, this active- high output signal is asserted to indicate that the word has programmed correctly. (pver low after the rising edge of prog# indicates an error.) p2.0/epa0 pwm1:0 o pulse width modulator outputs . these are pwm output pins with high-current drive capability. the duty cycle and frequency-pulse-widths are programmable. p6.7:6 rd# o read . read-signal output to external memory. rd# is asserted only during external memory reads. p5.3 table 7. signal descriptions (continued) signal name type description multiplexed with
8xc196mh industrial motor control chmos microcontroller ? 17 ready i ready input . this active-high input signal is used to lengthen external memory cycles for slow memory by generating wait states. when ready is high, cpu operation continues in a normal manner. if ready is low, the memory controller inserts wait states until the ready signal goes high or until the number of wait states is equal to the number programmed into the chip configuration register. ready is ignored for all internal memory accesses. p5.6 reset# i/o reset . reset input to and open-drain output from the chip. a falling edge on reset# initiates the reset process. when reset# is first asserted, the chip turns on a pull-down transistor connected to the reset pin for 16 state times. this function can also be activated by execution of the rst instruction. in the powerdown and idle modes, asserting reset# causes the chip to reset and return to normal operating mode. reset# is a level-sensitive input. rxd1 rxd0 i/o receive serial data 0 and 1 . in modes 1, 2, and 3, rxd0 and 1 are used to receive serial port data. in mode 0, they function as either inputs or open-drain outputs for data. p1.3 p1.1 sclk1# sclk0# i/o synchronous clock pin 0 and 1 . in mode 4, these are the bidrectional, shift clock signals that synchronize the serial data transfer. data is transferred 8 bits at a time with the lsb first. the dir bit (sp_con x .7) controls the direction of sclk x signal. dir = 0 the internal shift clock is output on sclk x . dir = 1 an external shift clock is input on sclk x . p2.7/bclk1 p2.1/bclk0 t1clk i external clock . external clock for timer 1. timer 1 increments (or decrements) on both rising and falling edges of t1clk. also used in conjunction with t1dir for quadrature counting mode. p0.6/ach6/pmode.2 t1dir i timer 1 external direction . external direction (up/down) for timer 1. timer 1 increments when t1dir is high and decrements when it is low. also used in conjunction with t1clk for quadrature counting mode. p0.7/ach7/pmode.3 txd1 txd0 o transmit serial data 0 and 1 . in serial i/o modes 1, 2, and 3, txd0 and 1 are used to transmit serial port data. in mode 0, they are used as the serial clock output. p1.2 p1.0 v cc pwr digital supply voltage . connect each v cc pin to the digital supply voltage. v pp pwr programming voltage . set to 12.5 v when programming the on-chip otprom. also the timing pin for the return from power-down circuit. table 7. signal descriptions (continued) signal name type description multiplexed with
8xc196mh industrial motor control chmos microcontroller ? 18 v ref pwr reference voltage for the a/d converter . v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. v ref must be connected for the a/d and port 0 to function. v ss gnd digital circuit ground (0 volts). connect each v ss pin to ground. wg3 wg2 wg1 o waveform generator phase 1 C 3 positive outputs . 3-phase output signals used in motion-control applications. p6.5 p6.3 p6.1 wg3# wg2# wg1# o waveform generator phase 1 C 3 negative outputs . complementary 3-phase output signals used in motion- control applications. p6.4 p6.2 p6.0 wr# o write . this active-low output indicates that an external write is occurring. this signal is asserted only during external memory writes. p5.2/wrl# wrh# o write high . during 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. during 8-bit bus cycles, wrh# is asserted for all write operations. p5.5/bhe# wrl# o write low . during 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes. during 8-bit bus cycles, wrl# is asserted for all write operations. p5.2/wr# xtal1 i clock/oscillator input . input to the on-chip oscillator inverter and the internal clock generator. also provides the clock input for the serial i/o baud-rate generator, timers, and pwm unit. if an external oscillator is used, connect the external clock input signal to xtal1 and ensure that the xtal1 v ih specification is met. xtal2 o oscillator output . output of the on-chip oscillator inverter. when using the on-chip oscillator, connect xtal2 to an external crystal or resonator. when using an external clock source, let xtal2 float. table 7. signal descriptions (continued) signal name type description multiplexed with
8xc196mh industrial motor control chmos microcontroller ? 19 electrical characteristics absolute maximum ratings* storage temperature ................................ C 65c to + 150c ambient temperature under bias.............................................. C 40c to + 85c voltage from v pp or ea# to v ss or angnd (note 1) ...................... C 0.5 v to + 13.0 v voltage with respect to v ss or angnd (note 1) ........................ C 0.5 v to + 7.0 v (this includes v pp on rom and cpu devices.) power dissipation .......................................................... 1.5 w (based on package heat transfer limitations, not device power consumption) operating conditions* t a (ambient temperature under bias) .........C 40c to + 85c v cc (digital supply voltage) .......................... 4.50 v to 5.50 v v ref (analog supply voltage) ....................... 4.50 v to 5.50 v f osc (oscillator frequency) (note 2) ........... 8 mhz to 16 mhz notes: 1. angnd and v ss should be at nominally the same potential. 2. testing is performed down to 8 mhz, although the device is static by design and will typically operate below 1 hz. notice : this data sheet contains preliminary infor- mation on new products in production. it is valid for the devices indicated in the revision his tory. the specifications are subject to change without notice. * warning : stre ssing the de vice b eyo n d the abs olute m axim u m ratin gs ma y cau se per m a nen t da m a g e . th ese a re stre ss ra ting s on ly. o per atio n b eyon d t he o p era ting co nditio ns is n ot r eco m m end ed and ex tend e d exp osu re b eyon d t he op era ting con dition s may aff ect d evice re li- a bility.
8xc196mh industrial motor control chmos microcontroller ? 20 dc characteristics table 8. dc characteristics over specified operating conditions symbol parameter min typ (4) max units test conditions v il input low voltage (standard inputs (1)) C 0.5 0.3 v cc v v il 1 input low voltage (reset#, ports 3, 4, and 5) C 0.5 0.8 v v ih input high voltage (standard inputs (1)) 0.7 v cc v cc + 0.5 v v ih 1 input high voltage (reset#, ports 3, 4, and 5) 0.2 v cc + 1.0 v cc + 0.5 v v ol output low voltage (reset#, ports 1, 2, 5, p6.6, p6.7, and xtal2) 0.3 0.45 1.5 v v v i ol = 200 a i ol = 3.2 ma i ol = 7.0 ma v ol 1 output low voltage (ports 3, 4) 1.0 v i ol = 7 ma v ol 2 output low voltage (p6.5:0) 0.45 v i ol = 10 ma v oh output high voltage (output pins and i/o configured as push/pull outputs) v cc C 0.3 v cc C 0.7 v cc C 1.5 v v v i oh = C 200 a i oh = C 3.2 ma i oh = C 7.0 ma v th + C v th C hysteresis voltage width on reset# pin 0.2 v i li input leakage current (standard inputs (1)) 10 a v ss < v in < v cc C 0.3v i li 1 input leakage current (port 0 C a/d inputs) 3av ss < v in < v ref i ih input high current (nmi) 300 a v in = 0.7 v cc i il input low current (port 2, except p2.6) - 70 a v in = 0.3 v cc notes: 1. standard input pins include xtal1, ea#, and ports 1 and 2 when configured as inputs. 2. maximum current that an external device must sink to ensure test mode entry. 3. violating these specifications during reset may cause the device to enter test modes. 4. typical values are based on a limited number of samples and are not guaranteed. operating conditions for typical values are room temperature and v ref = v cc = 5.5 v. 5. testing is performed down to 8 mhz, although the device is static by design and will typically operate below 1 hz. 6. all voltages are referenced relative to v ss . when used, v ss refers to the device pin. 7. table 9 lists the total current limits during normal (non-transient conditions). the total current listed is the sum of the pins listed for each specification value.
8xc196mh industrial motor control chmos microcontroller ? 21 i il 1 input low current (p5.4 and p2.6 during reset) (2) C 10 ma v in = 0.8 v i il 2 input low current (ports 3, 4, and 5, except p5.4) C 300 a v in = 0.8 v i il 3 input low current (port 1) C 300 a v in = 0.3 v cc i oh output high current (p5.4 and p2.6 during reset) (3) C 0.2 ma 0.7 v cc i oh 1 output high current (p6.5:0 during reset) C 6 C 40 a 0.7 v cc i cc v cc supply current 50 70 ma xtal1 = 16 mhz v cc = 5.5 v v pp = 5.5 v v ref = 5.5 v i ref a/d reference supply current 25ma i idle idle mode current 15 30 ma i pd powerdown mode current (4) 550a r rst reset pull-up resistor 6 65 k w c s pin capacitance (any pin to v ss ) 10 pf f test = 1.0 mhz table 8. dc characteristics over specified operating conditions (continued) symbol parameter min typ (4) max units test conditions notes: 1. standard input pins include xtal1, ea#, and ports 1 and 2 when configured as inputs. 2. maximum current that an external device must sink to ensure test mode entry. 3. violating these specifications during reset may cause the device to enter test modes. 4. typical values are based on a limited number of samples and are not guaranteed. operating conditions for typical values are room temperature and v ref = v cc = 5.5 v. 5. testing is performed down to 8 mhz, although the device is static by design and will typically operate below 1 hz. 6. all voltages are referenced relative to v ss . when used, v ss refers to the device pin. 7. table 9 lists the total current limits during normal (non-transient conditions). the total current listed is the sum of the pins listed for each specification value.
8xc196mh industrial motor control chmos microcontroller ? 22 figure 6. i cc , i idle versus frequency table 9. total current limits during normal (non-transient) conditions signal names maximum i ol limits maximum i oh limits port 1 25 ma C 25 ma port 2, p6.6, p6.7 40 ma C 40 ma port 3 40 ma C 30 ma port 4 40 ma C 30 ma port 5 40 ma C 30 ma p6.5:0 40 ma C 30 ma a2711-01 frequency (mhz) i cc (ma) 0410 16 0 10 20 30 40 50 60 70 i idle max i cc max i cc typ i idle typ
8xc196mh industrial motor control chmos microcontroller ? 23 explanation of ac symbols each symbol consists of two pairs of letters prefixed by t (for time). the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. for example, t rhdz is the time between signal r (rd#) condition h (high) and signal d (input data) condition z (floating). table 10 defines the signal and condition codes. ac characteristics (over specified operation conditions) table 11 defines the ac timing specifications that the external memory system must meet and those that the 8xc196mh will provide. table 10. ac timing symbol definitions signals conditions a address p prog# h high b bhe# q data out l low d data in r rd# v valid g buswidth v pver x no longer valid i t1dir/ainc# w wr#/wrh#/wrl# z floating k t1clk x xtal1 l ale/adv#/pale# y ready table 11. ac timing definitions ( 1 ) symbol parameter min max units notes f osc frequency on xtal1 8 16 mhz 4 t osc 1/f osc 62.5 125 ns the external memory system must meet these specifications t avyv address valid to ready setup 2t osc C 75 ns t llyv ale/adv# low to ready setup t osc C 70 ns t ylyh non ready time no upper limit ns t llyx ready hold after ale/adv# low t osc C 15 2t osc C 40 ns 2 t avgv address valid to buswidth setup 2t osc C 75 ns t llgv ale/adv# low to buswidth setup t osc C 60 ns notes: 1. test conditions: capacitive load on all pins = 100 pf, rise and fall times = 10 ns, f osc = 16 mhz. 2. exceeding the maximum specification causes additional wait states. 3. if wait states are used, add 2t osc n , where n = number of wait states. 4. testing is performed down to 8 mhz, although the device is static by design and will typically operate below 1 hz. 5. assuming back-to-back bus cycles. 6. 8-bit bus only.
8xc196mh industrial motor control chmos microcontroller ? 24 the external memory system must meet these specifications (continued) t llgx buswidth hold after ale/adv# low t osc ns t lhdv ale/adv# high to input data valid 3t osc C 55 ns t avdv address valid to input data valid 3t osc C 55 ns 3 t rldv rd# active to input data valid t osc C 30 ns 3 t rhdz end of rd# to input data float t osc ns t rxdx data hold after rd# inactive 0 ns the 8xc196mh will meet these specifications t xhlh xtal1 rising edge to ale rising 20 110 ns t xhll xtal1 rising edge to ale falling 20 110 ns t lhlh ale/adv# cycle time 4t osc ns 3 t lhll ale/adv# high period t osc C 10 t osc + 10 ns t avlh address valid to ale/adv# high t osc C 17 ns t avll address valid to ale/adv# low t osc C 17 ns t llax address hold after ale/adv# low t osc C 40 ns t llrl ale/adv# low to rd# low t osc C 30 ns t rlrh rd# low period t osc C 5 t osc + 25 ns 3 t rhlh rd# high to ale/adv# high t osc t osc + 25 ns 5 t rlaz rd# low to address float 5 ns t llwl ale/adv# low to wr# low t osc C 10 ns t qvwh data valid before wr# high t osc C 23 ns t wlwh wr# low period t osc C 30 ns 3 t whqx data hold after wr# high t osc C 25 ns t whlh wr# high to ale/adv# high t osc C 10 t osc + 15 ns 5 t whbx bhe#, inst hold after wr# high t osc C 10 ns t whax a15:8 hold after wr# high t osc C 30 ns 6 t rhbx bhe#, inst hold after rd# high t osc C 10 ns t rhax a15:8 hold after rd# high t osc C 30 ns 6 table 11. ac timing definitions ( 1 ) (continued) symbol parameter min max units notes notes: 1. test conditions: capacitive load on all pins = 100 pf, rise and fall times = 10 ns, f osc = 16 mhz. 2. exceeding the maximum specification causes additional wait states. 3. if wait states are used, add 2t osc n , where n = number of wait states. 4. testing is performed down to 8 mhz, although the device is static by design and will typically operate below 1 hz. 5. assuming back-to-back bus cycles. 6. 8-bit bus only.
8xc196mh industrial motor control chmos microcontroller ? 25 system bus timings figure 7. system bus timing diagram xtal1 ale rd# bus wr# bus inst a15:8 (8-bit bus) address out data data outaddress out address out t lhll t osc valid a2543-01 t xhlh t lhlh t llrl t rlrh t rhlh t avll t llax t rldv t rhdz t rlaz address out t avdv t llwl t wlwh t whlh t qvwh t whqx t rhbx t whbx t rhax t whax t xhll t lhdv t rxdx t avlh
8xc196mh industrial motor control chmos microcontroller ? 26 ready timing (one wait state) figure 8. ready timing diagram (one wait state) a2544-01 t avyv t llyx(max) address out data out address out data in address bus wr# bus rd# ready ale xtal1 t osc t lhlh + 2t osc t clyx(min) t llyv t llyx(min) t clyx(max) t rlrh + 2t osc t rldv + 2t osc t avdv + 2t osc t wlwh + 2t osc t qvwh + 2t osc t rldv + 2t osc 16 mhz 8 mhz
8xc196mh industrial motor control chmos microcontroller ? 27 buswidth timing figure 9. buswidth timing diagram external clock drive table 12. external clock drive timing symbol parameter min max units 1/t xlxl oscillator frequency 8 16 mhz t xlxl oscillator period (t osc ) 62.5 125 ns t xhxx high time 22 ns t xlxx low time 22 ns t xlxh rise time 10 ns t xhxl fall time 10 ns a2545-01 data in buswidth bus ale xtal1 t osc t avgv t llgv t llgx address out
8xc196mh industrial motor control chmos microcontroller ? 28 figure 10. external clock drive waveforms figure 11. external clock connections t xhxx t xlxx t xhxl t xlxl 0.7 v cc 0.8 v 0.8 v 0.7 v cc 0.7 v cc t xlxh a2578-01 xtal1 4.7k w * 8xc196 device xtal2 xtal1 external clock input clock driver no connect v cc a0274-01 note: *required if ttl driver is used. not needed if cmos driver is used.
8xc196mh industrial motor control chmos microcontroller ? 29 figure 12. external crystal connections figure 13. ac testing input, output waveforms 8xc196 device xtal2 xtal1 quartz crystal c1 c2 a0273-01 v ss note: keep oscillator components close to the chip and use short, direct traces to xtal1, xtal2, and v ss . when using crystals, c1=c2 ? 20pf. when using ceramic resonators, consult the manufacturer for recommended oscillator circuitry. test points 2.0 v 0.8 v ac testing inputs are driven at 3.5 v for a logic "1" and 0.45 v for a logic "0". timing measurements are made at 2.0 v for a logic "1" and 0.8 v for a logic "0". 3.5 v 0.45 v a2120-02 2.0 v 0.8 v
8xc196mh industrial motor control chmos microcontroller ? 30 figure 14. float waveforms ac characteristics serial port, shift register mode table 13. serial port timing shift register mode (mode 0) symbol parameter min max units notes t xlxl serial port clock period (baud-rate n 3 8002h) (baud-rate n = 8001h) 6t osc 4t osc ns ns 1, 2 t xlxh serial port clock low period (baud-rate n 3 8002h) (baud-rate n = 8001h) 4t osc C 50 2t osc C 50 4t osc + 50 2t osc + 50 ns ns 1, 2 t qvxh output data setup to clock high 2t osc C 50 ns t xhqx output data hold after clock high 2t osc C 50 ns t xhqv next output data valid after clock high 2t osc + 50 ns t dvxh input data setup to clock high t osc + 50 ns t xhdx input data hold after clock high 0 ns t xhqz last clock high to output float t osc ns notes: 1. n for baud-rate n signifies serial port 0 or 1. 2. maximum serial port mode 0 reception is with baud-rate n 3 8002h. v load + 0.1 v v load C 0.1 v timing reference points v load v oh C 0.1 v v ol + 0.1 v for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol /i oh 15 ma. a2579-01
8xc196mh industrial motor control chmos microcontroller ? 31 figure 15. serial port waveform shift register mode (mode 0) table 14. serial port timing mode 4 symbol parameter min max units t xlxl serial port clock period (dir=0) 16t osc 131072t osc ns t xlxx serial port clock low period (dir=0/1) (t xlxl /2) C 30 ns t xhxx serial port clock high period (dir=0/1) (t xlxl /2) C 30 ns t xlxl serial port clock period (dir=1) 16t osc ns t xhxl serial clock falling time (dir=1) 0 20 ns t xlxh serial clock rising time (dir=1) 0 20 ns t xlqv clock low to output data setup 7.5t osc C 50 ns t xlqx output data hold after clock low 0 ns t xhqx last output data hold after clock high (dir=1) 13.7t osc ns t dvxx input data setup to clock low invalid 0 ns t xhdh input data hold after clock high 6t osc ns (in) a2080-01 valid valid valid valid valid valid valid valid rxd n (out) txd n 01 2 3 4 5 6 7 t qvxh t xlxl t dvxh t xhqv t xhqz t xhdx t xhqx t xlxh rxd n
8xc196mh industrial motor control chmos microcontroller ? 32 figure 16. serial port waveform mode 4 figure 17. serial port waveform clock drive (dir = 1) a2550-01 txd n rxd n sck n # t xlxl t dvxx t xhdh t xlxx t xhxx t xhqx t xlqx t xlqv t xhxx t xlxx t xhxl t xlxl v ih v il sck n # a2582-01 t xlxh
8xc196mh industrial motor control chmos microcontroller ? 33 baud-rate clock drive table figure 18. baud-rate clock drive waveforms table 15. baud rate clock drive symbol parameter min max units t xlxl baud rate clock period 4t osc ns t xhxx baud rate clock high time 2t osc C 30 ns t xlxx baud rate clock low time 2t osc C 30 ns t xlxh baud rate clock rise time 20 ns t xhxl baud rate clock fall time 20 ns a2551-01 t xhxx t xlxx t xhxl t xlxl v ih t xlxh v il bclk n
8xc196mh industrial motor control chmos microcontroller ? 34 a/d sample and conversion times two parameters, sample time and conversion time, control the time required for an a/d conversion. the sample time is the length of time that the analog input voltage is actually connected to the sample capacitor. if this time is too short, the sample capacitor will not charge completely. if the sample time is too long, the input voltage may change and cause conversion errors. the conversion time is the length of time required to convert the analog input voltage stored on the sample capacitor to a digital value. the conversion time must be long enough for the comparator and circuitry to settle and resolve the voltage. excessively long conversion times allow the sample capacitor to discharge, degrading accuracy. the ad_time register programs the a/d sample and conversion times. use the t sam and t conv specifica- tions in tables 16 and 18 to determine appropriate values for sam and conv; otherwise, erroneous conversion results may occur. use the following formulas to determine the sam and conv values: where: sam = 1 to 7 conv = 2 to 31 t sam is the sample time, in m sec (tables 16 and 18) t conv is the conversion time, in m sec (tables 16 and 18) f osc is the xtal1 frequency, in mhz b is the number of bits to be converted (8 or 10) when the sam and conv values are known, write them to the ad_time register. do not write to this register while a conversion is in progress; the results are unpredictable. sam t sam f osc 2 C 8 ----------------------------------------= conv t conv f osc 3 C 2b ------------------------------------------- 1 C=
8xc196mh industrial motor control chmos microcontroller ? 35 ac characteristics a/d converter table 16. 10-bit a/d operating conditions (1) symbol description min max units notes t a ambient temperature C 40 + 85 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v 2 t sam sample time 1.0 m s3 t conv conversion time 10.0 20.0 m s3 f osc oscillator frequency 8 16 mhz notes: 1. angnd and v ss should nominally be at the same potential. 2. v ref must not exceed v cc by more than + 0.5 v because v ref supplies both the resistor ladder and the analog portion of the converter and input port pins. 3. program the ad_time register to meet the t sam and t conv specifications. table 17. 10-bit mode a/d characteristics over specified operating conditions (1) parameter typical (3) min max units (2) notes resolution 1024 10 1024 10 levels bits absolute error 0 3lsbs full-scale error 0.25 0.5 lsbs zero offset error 0.25 0.5 lsbs nonlinearity 1.0 2.0 3lsbs differential nonlinearity C 0.75 + 0.75 lsbs channel-to-channel matching 0.1 0 1 lsbs repeatability 0.25 0 lsbs notes: 1. testing is performed with v ref = 5.12 v and f osc = 16 mhz. 2. an ls b , as used here, has a value of approximately 5 mv. 3. typical values are based on a limited number of samples and are not guaranteed. operating conditions for typical values are room temperature and v ref = v cc = 5.5 v. 4. dc to 100 khz. 5. multiplexer break-before-make guaranteed. 6. resistance from device pin, through internal multiplexer, to sample capacitor. 7. these values may be exceeded if the pin current is limited to 2ma. 8. applying voltage beyond these specifications will degrade the accuracy of other channels being con- verted. 9. all conversions were performed with processor in idle mode.
8xc196mh industrial motor control chmos microcontroller ? 36 temperature coefficients: offset full-scale differential nonlinearity 0.009 0.009 0.009 lsb/c lsb/c lsb/c off-isolation C 60 db 4, 5 feedthrough C 60 db 4 v cc power supply rejection C 60 db 6 input series resistance 750 1.2k w 4 voltage on analog input pin angnd C 0.5 v ref + 0.5 v 7, 8 sampling capacitor 3 pf dc input leakage 1.0 0 3 m a table 18. 8-bit a/d operating conditions (1) symbol description min max units notes t a ambient temperature C 40 + 85 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v 2 t sam sample time 1.0 m s3 t conv conversion time 7.0 20.0 m s3 f osc oscillator frequency 8 16 mhz notes: 1. angnd and v ss should nominally be at the same potential. 2. v ref must not exceed v cc by more than + 0.5 v because v ref supplies both the resistor ladder and the analog portion of the converter and input port pins. 3. program the ad_time register to meet the t sam and t conv specifications. table 17. 10-bit mode a/d characteristics over specified operating conditions (1) (continued) parameter typical (3) min max units (2) notes notes: 1. testing is performed with v ref = 5.12 v and f osc = 16 mhz. 2. an ls b , as used here, has a value of approximately 5 mv. 3. typical values are based on a limited number of samples and are not guaranteed. operating conditions for typical values are room temperature and v ref = v cc = 5.5 v. 4. dc to 100 khz. 5. multiplexer break-before-make guaranteed. 6. resistance from device pin, through internal multiplexer, to sample capacitor. 7. these values may be exceeded if the pin current is limited to 2ma. 8. applying voltage beyond these specifications will degrade the accuracy of other channels being con- verted. 9. all conversions were performed with processor in idle mode.
8xc196mh industrial motor control chmos microcontroller ? 37 table 19. 8-bit mode a/d characteristics over specified operating conditions (1) parameter typical (3) min max units (2) notes resolution 256 8 256 8 levels bits absolute error 0 1lsbs full-scale error 0.5 lsbs zero offset error 0.5 lsbs nonlinearity 0 1lsbs differential nonlinearity C 0.5 + 0.5 lsbs channel-to-channel matching 0 1 lsbs repeatability 0.25 0 lsbs temperature coefficients: offset full-scale differential nonlinearity 0.003 0.003 0.003 lsb/ c lsb/ c lsb/ c off isolation C 60 db 4, 5 feedthrough C 60 db 4 v cc power supply rejection C 60 db 4 input series resistance 750 1.2k w 6 voltage on analog input pin angnd C 0.5 v ref + 0.5 v 7, 8 sampling capacitor 3 pf dc input leakage 10 3 m a notes: 1. testing is performed with v ref = 5.12 v and f osc = 16 mhz. 2. an ls b , as used here, has a value of approximately 20 mv. 3. typical values are based on a limited number of samples and are not guaranteed. operating conditions for typical values are room temperature and v ref = v cc = 5.5 v. 4. dc to 100 khz. 5. multiplexer break-before-make guaranteed. 6. resistance from device pin, through internal multiplexer, to sample capacitor. 7. these values may be exceeded if the pin current is limited to 2ma. 8. applying voltage beyond these specifications will degrade the accuracy of other channels being con- verted. 9. all conversions were performed with processor in idle mode.
8xc196mh industrial motor control chmos microcontroller ? 38 otprom specifications table 20. programming operating conditions symbol description min max units notes t a ambient temperature 20 30 c v cc supply voltage during programming 4.50 5.50 v 3 v ref reference supply voltage during programming 4.50 5.50 v 3 v pp programming voltage 12.25 12.75 v 2 v ea ea pin voltage 12.25 12.75 v 2 f osc oscillator frequency during auto and slave mode programming oscillator frequency during run-time programming 6 6 8 12 mhz mhz notes: 1. v cc and v ref should be at nominally the same voltage during programming. 2. if v pp and v ea exceed the maximum specification, the device may be damaged. 3. v ss and angnd should be at nominally the same potential (0 volts). 4. load capacitance during auto and slave mode programming = 150 pf. table 21. ac otprom programming characteristics symbol description min max units t avll address setup time 0 t osc t llax address hold time 100 t osc t dvpl data setup time 0 t osc t pldx data hold time 400 t osc t lllh pale# pulse width 50 t osc t plph prog# pulse width (1) 50 t osc t phll prog# high to next pale# low 220 t osc t phdx word dump hold time 50 t osc t phpl prog# high to next prog# low 220 t osc t lhpl pale# high to prog# low 220 t osc t pldv prog# low to word dump valid 50 t osc t shll reset# high to first pale# low 1100 t osc t phil prog# high to ainc# low 0 t osc t ilih ainc# pulse width 240 t osc note: 1. this specification is for word dump mode. for programming pulses, use the modified quick pulse algo- rithm explained in the users manual.
8xc196mh industrial motor control chmos microcontroller ? 39 otprom programming waveforms figure 19. slave programming mode data program mode with single program pulse t ilvh pver hold after ainc# low 50 t osc t ilpl ainc# low to prog# low 170 t osc t phvl prog# high to pver valid 220 t osc table 22. dc otprom programming characteristics symbol parameter min max units i pp v pp supply current (when programming) 100 ma note: do not apply v pp until v cc is stable and within specifications and the oscillator/clock has stabiliized. otherwise, the device may be damaged. table 21. ac otprom programming characteristics (continued) symbol description min max units note: 1. this specification is for word dump mode. for programming pulses, use the modified quick pulse algo- rithm explained in the users manual. a2549-01 data prog# pale# ports 3/4 reset# address/command pver address/command t phvl t shll t avll t llax t lllh t lhpl t dvpl t pldx t plph t phll
8xc196mh industrial motor control chmos microcontroller ? 40 figure 20. slave programming mode in word dump with autoincrement timing slave programming mode in word dump with autoincrement figure 21. slave programming mode in data program with repeated program pulse and autoincrement a2546-01 ver bits/word dump prog# pale# ports 3/4 reset# t ilpl address/command ainc# ver bits/word dump t pldv t phdx t pldv t phdx address address + 2 t phpl t shll note : p3.0 must be low ("0") a2547-01 data prog# pale# ports 3/4 reset# address/command pver address address + 2 data address data ainc# t ilvh t phil t ilih valid for pn valid for p1 t ilpl pn t phpl p1
8xc196mh industrial motor control chmos microcontroller ? 41 8xc196mc/md to 8xc196mh design considerations the 8xc196mh is not pin compatible with the 8xc196mc or the 8xc196md. be aware that signal multiplexing sometimes differs between the 8xc196mh and the 8xc196mc/md. for example, p2.7 is multiplexed with comp3 on the 8xc196mc/md and with sclk1# and bclk1 on the 8xc196mh. data sheet revision history the -003 revisions were made due to the changes required for the lead free initiative. to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".

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