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a43p26161 preliminary 1m x 16 bit x 4 banks low power synchronous dram preliminary (july, 2005, version 1.1) amic technology, corp. document title 1m x 16 bit x 4 banks low power synchronous dram revision history rev. no. history issue date remark 0.0 initial issue septem ber 13, 2004 preliminary 1.0 modify to 133mhz & 105mhz june 10, 2005 modify all dc specification for new product 1.1 modify t ss from 3ns to 2ns july 11, 2005
a43p26161 preliminary 1m x 16 bit x 4 banks low power synchronous dram preliminary (july, 2005, version 1.1) 1 amic technology, corp. features low power supply - vdd: 2.5v vddq : 2.5v lvcmos compatible with multiplexed address four banks / pulse ras mrs cycle with address key programs - cas latency (2 & 3) - burst length (1,2,4,8 & full page) - burst type (sequential & interleave) all inputs are sampled at the positive going edge of the system clock deep power down mode dqm for masking auto & self refresh 64ms refresh period (4k cycle) self refresh with programmable refresh period through emrs cycle programmable power reduction feature by partial array activation during self-refresh through emrs cycle industrial operating temperat ure range: -40oc to +85oc for -u series. available in 54 balls csp (8mm x 8mm) and 54-pin tsop(ii) packages. package is available to lead free (-f series) clock frequency (max) : 105mhz @ cl=3 (-95) 133mhz @ cl=3 (-75) general description the a43p26161 is 67,108,864 bits low power synchronous high data rate dynamic ram organized as 4 x 1,048,576 words by 16 bits, fabricated with amic?s high performance cmos technology. synchronous design allows precise cycle control with the use of system clock. i/o transactions are possible on every clock cycle. range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. pin configuration 54 balls csp (8 mm x 8 mm) top view 54 ball ( 6 x 9 ) csp 1 2 3 7 8 9 a vss dq 15 vssq vddq dq 0 vdd b dq 14 dq 13 vddq vssq dq 2 dq 1 c dq 12 dq 11 vssq vddq dq 4 dq 3 d dq 10 dq 9 vddq vssq dq 6 dq 5 e dq 8 nc vss vdd ldqm dq 7 f udqm clk cke cas ras we g nc a11 a9 ba0 ba1 cs h a 8 a 7 a 6 a 0 a 1 a 10 j vss a 5 a 4 a 3 a 2 vdd
a43p26161 preliminary (july, 2005, version 1.1) 2 amic technology, corp. pin configuration (continued) 54 tsop (ii) a43p26161v 54 53 52 51 50 49 48 47 46 45 43 44 42 41 40 39 38 37 36 35 34 33 32 31 30 123 45678 910 12 11 13 14 15 16 17 18 19 20 21 22 23 24 25 vss dq 15 vssq dq 14 dq 13 vddq dq 12 dq 11 vssq dq 10 dq 9 vddq dq 8 vss udqm clk cke nc a9 a8 a7 a6 a5 a4 vss vdd dq 0 vddq dq 1 dq 2 vssq dq 3 dq 4 vddq dq 5 dq 6 vssq dq 7 vdd ldqm we cas ras cs a10/ap bs1 bs0 a0 a1 a2 26 27 28 29 a3 vdd a11 nc block diagram bank select row buffer refresh counter address register row decoder column buffer lcbr lras clk add timing register data input register 1m x 16 sense amp column decoder latency & burst length programming register lras lcas lras lcbr lwe lwcbr dqm clk cke cs ras cas we dqm i/o control output buffer lwe dqm dqi 1m x 16 1m x 16 1m x 16
a43p26161 preliminary (july, 2005, version 1.1) 3 amic technology, corp. pin descriptions symbol name description clk system clock active on the positive going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and l(u)dqm cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one clock + tss prior to new command. disable input buffers for power down in standby. a0~a11 address row / column addresses are multiplexed on the same pins. row address : ra0~ra11, column address: ca0~ca7 bs0, bs1 bank select address selects bank to be activated during row address latch time. selects band for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. l(u)dqm data input/output mask makes data output hi-z, t shz a fter the clock and masks the output. blocks data input when l(u)dqm active. dq 0-15 data input/output data inputs/outputs are multiplexed on the same pins. vdd/vss power supply/ground power supply: +2.3v ~ 2.7v/ground vddq/vssq data output power/ground provide isolated power/ground to dqs for improved noise immunity. nc/rfu no connection
a43p26161 preliminary (july, 2005, version 1.1) 4 amic technology, corp. absolute maximum ratings* voltage on any pin relative to vss (vin , vout ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to +3.0v voltage on vdd supply relative to vss (vdd, vddq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0v to + 3.0v storage temperature (t stg ) . . . . . . . . . . -55 c to +150 c soldering temperature x time (t sloder ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 c x 10sec power dissipation (p d ) . . . . . . . . . . . . . . . . . . . . . . . . 0.8w short circuit current (ios) . . . . . . . . . . . . . . . . . . . . 50ma *comments permanent device damage may occur if ?absolute maximum ratings? are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time coul d affect device reliability. capacitance (t a =25 c, f=1mhz) parameter symbol condition min max unit input capacitance ci1 a0 to a11, bs0, bs1 2.0 4.0 pf ci2 clk, cke, cs , ras , cas , we , dqm 2.0 4.0 pf data input/output capacitance ci/o dq0 to dq15 3.5 6.0 pf dc electrical characteristics recommend operating conditions (voltage referenced to vss=0v, t a = 0oc to +70oc for commercial or t a =-40oc to +85oc for extended) parameter symbol min typ max unit note supply voltage vdd 2.3 2.5 2.7 v dq supply voltage vddq 2.3 2.5 2.7 v input high voltage v ih 0.8*vddq - vddq+0.3 v input low voltage v il -0.3 - 0.3 v note 1 output high voltage v oh vddq - 0.2 - - v i oh = -0.1ma output low voltage v ol - - 0.2 v i ol = 0.1ma input leakage current i il -1 - 1 a note 2 output leakage current i ol -1.5 - 1.5 a note 3 output loading condition see fig. 1 (page 6) note: 1. v il (min) = -1.5v ac (pulse width 5ns). 2. any input 0v vin vdd + 0.3v, all other pins are not under test = 0v 3. dout is disabled, 0v vout vdd
a43p26161 preliminary (july, 2005, version 1.1) 5 amic technology, corp. decoupling capacitance guide line recommended decoupling capacitance added to power line at board. parameter symbol value unit decoupling capacitance between vdd and vss c dc1 0.1 + 0.01 f decoupling capacitance between vddq and vssq c dc2 0.1 + 0.01 f note: 1. vdd and vddq pins are separated each other. all vdd pins are connected in chip. a ll vddq pins are connected in chip. 2. vss and vssq pins ar e separated each other all vss pins are connected in chip. a ll vssq pins are connected in chip. dc electrical characteristics (recommended operating condition unless otherwise noted, t a = 0oc to +70oc for commercial or t a = -40oc to +85oc for extended) speed symbol parameter test conditions -75 -95 units note i cc1 operating current (one bank active) burst length = 1 t rc t rc (min), t cc t cc (min ) , i ol = 0ma 40 ma 1 i cc2 p cke v il (max), t cc = 15ns 0.3 i cc2 ps precharge standby current in power-down mode cke v il (max), t cc = 0.5 ma i cc2 n cke v ih (min), cs v ih (min), t cc = 15ns input signals are changed one time during 30ns 5.5 i cc2 ns precharge standby current in non power-down mode cke v ih (min), clk v il (max), t cc = input signals are stable. 2 ma i cc3 p cke v il (max), t cc = 15ns 1.5 i cc3 n active standby current in non power-down mode (one bank active) cke v ih (min), cs v ih (min), t cc = 15ns input signals are changed one time during 30ns 12 ma i cc4 operating current (burst mode) i ol = 0ma, page burst all bank activated, t ccd = t ccd (min) 50 ma 1 i cc5 refresh current t rc t rc (min) 90 ma 2 tcsr range <45 c <70 c <85 c 4 banks 400 450 500 2 banks 250 260 300 1 banks 150 180 180 1/2 bank 100 120 120 i cc6 self refresh current cke 0.2v 1/4 bank 80 90 100 ua i cc7 deep power down current cke 0.2v 10 ua note: 1. measured with outputs open. addresses are changed only one time during t cc (min). 2. refresh period is 64ms. addresses are changed only one time during t cc (min).
a43p26161 preliminary (july, 2005, version 1.1) 6 amic technology, corp. ac operating test conditions (vdd = 2.3v~2.7v, t a = 0oc to +70oc for commercial or t a =-40oc to +85oc for extended) parameter value unit ac input levels 0.9 x vddq/0.2 v input timing measurement reference level 0.5 x vddq v input rise and all time (see note3) tr/tf = 1/1 ns output timing measurement reference level 0.5 x vddq v output load condition see fig.2 output 500 ? 500 ? (fig. 1) dc output load circuit z o =50 ? output 50 ? v tt =0.5v x vddq 30pf (fig. 2) ac output load circuit vddq 30pf v oh (dc) = vddq-0.2v, i oh = -0.1ma v ol (dc) = 0.2v, i ol = 0.1ma ac characteristics (ac operating conditions unless otherwise noted) -75 -95 symbol parameter min max min max unit note cl=3 7.5 9.5 t cc clk cycle time cl=2 12 1000 15 1000 ns 1 cl=3 - 6 - 7 t sac clk to valid output delay cl=2 - 9 - 8 ns 1,2 t oh output data hold time 2.5 - 2.5 - ns 2 cl=3 3 - 3.5 - t ch clk high pulse width cl=2 3 - 3.5 - ns 3 cl=3 3 - 3.5 - t cl clk low pulse width cl=2 3 - 3.5 - ns 3 cl=3 2 - 2 - t ss input setup time cl=2 2 - 2 - ns 3 t sh input hold time 1.5 - 1.5 - ns 3 t slz clk to output in low-z 1 - 1 - ns 2 cl=3 - 6 - 7 t shz clk to output in hi-z cl=2 - 8 - 8 ns cl=cas latency. *all ac parameters are measured from half to half. note : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [ (tr + tf)/2-1 ] ns should be added to the parameter.
a43p26161 preliminary (july, 2005, version 1.1) 7 amic technology, corp. operating ac parameter (ac operating conditions unless otherwise noted) version symbol parameter -75 -95 unit note t rrd(min) row active to row active delay 2 2 clk 1 t rcd(min) ras to cas delay 19 24 ns 1 t rp(min) row precharge time 19 24 ns 1 t ras(min) 45 60 ns 1 t ras(max) row active time 100 100 s t rc(min) row cycle time 64 84 ns 1 t cdl(min) last data in new col. address delay 7.5 9.5 ns 2 t rdl(min) last data in row precharge 2 2 clk 1, 2 t bdl(min) last data in to burst stop 7.5 9.5 ns 2 t ccd(min) col. address to col. address delay 7.5 9.5 ns note: 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write.
a43p26161 preliminary (july, 2005, version 1.1) 8 amic technology, corp. simplified truth table command cken-1 cken cs ras cas we dqm bs0 bs1 a10 /ap a9~a0, a11 notes register mode register set h x l l l l x op code 1,2 extended mode register set h x l l l l l op code 1,2 auto refresh h 3 entry h l l l l h x x 3 l h h h 3 refresh self refresh exit l h h x x x x x 3 bank active & row addr. h x l l h h x v row addr. 4 auto precharge disable l 4 read & column addr. auto precharge enable h x l h l h x v h column addr. 4,5 auto precharge disable l 4 write & column addr. auto precharge enable h x l h l l x v h column addr. 4,5 burst stop h x l h h l x x bank selection v l precharge both banks h x l l h l x x h x l h h h entry h l h x x x x clock suspend or active power down exit l h x x x x x x l h h h entry h l h x x x x l v v v precharge power down mode exit l h h x x x x x dqm h x v x 6 l h h h no operation command h x h x x x x x deep power down entry h l l h h l x x deep power down exit l h x x x x x x 7 (v = valid, x = don?t care, h = logic high, l = logic low) note : 1. op code: operand code a0~a11, bs0, bs1: program keys. (@mrs, emrs) 2. mrs can be issued only when all banks are at precharge state. a new command can be issued after 2 clock cycle of mrs, emrs. 3. auto refresh functions is same as cbr refresh of dram. the automatical precharge without row precharge command is meant by ?auto?. auto/self refresh can be issued only when all banks are at precharge state. 4. bs0, bs1 : bank select address. if both bs1 and bs0 are ?low? at read, write, row active and precharge, bank a is selected. if both bs1 is ?low? and bs0 is ?high? at read, wr ite, row active and precharge, bank b is selected. if both bs1 is ?high? and bs0 is ?low? at read, wr ite, row active and precharge, bank c is selected. if both bs1 and bs0 are ?high? at read, write, row active and precharge, bank d is selected. if a10/ap is ?high? at row precharge, bs1 and bs0 is ignored and all banks are selected. 5. during burst read or write with auto prec harge, new read/write command cannot be issued. another bank read/write command can be issued at every burst length. 6. dqm sampled at positive going edge of a clk masks the data-in at the very clk (write dqm latency is 0) but masks the data-out hi-z state after 2 clk cycles. (read dqm latency is 2) 7. after deep power down mode exit, a full new initialization of the memory device is mandatory.
a43p26161 preliminary (july, 2005, version 1.1) 9 amic technology, corp. mode register filed table to program modes register programmed with mrs address bs1 bs0 a11,a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function 0 0 rfu w.b.l tm cas latency bt burst length (note 3) (note 1) (note 2) test mode cas latency burst type burst length a8 a7 type a6 a5 a4 latency a3 type a2 a1 a0 bt=0 bt=1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 1 0 1 0 0 1 - 1 interleave 0 0 1 2 2 1 0 0 1 0 2 0 1 0 4 4 1 1 vendor use only 0 1 1 3 0 1 1 8 8 write burst length 1 0 0 reserved 1 0 0 reserved reserved a9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 reserved reserved 1 single bit 1 1 1 reserved 1 1 1 256(full) reserved note : 1. rfu(reserved for future use) should stay ?0? during mrs cycle. 2. if a9 is high during mrs cycle, ?burst read single bit write? function will be enabled. 3. bs0, bs1 must be 0,0 to select the mode register (vs. the extended mode register). extended mode register table bs1 bs0 a11, a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address bus (ax) 1 0 all have to be set to ?0? ds tcsr pasr (note) driver strength temperature-compensated self-refresh: partial-array self refresh: driver strength a4 a3 max. case temp. a6 a5 driver strength 0 0 70 c a2 a1 a0 banks to be self-refreshed 0 0 full 0 1 45 c 0 0 0 all banks 0 1 1/2 1 0 15 c 0 0 1 bank a, bank b 1 0 1/4 1 1 85 c 0 1 0 bank a 0 1 1 reserved 1 0 0 reserved 1 0 1 1/2 of bank a 1 1 0 1/4 of bank a 1 1 1 reserved note: bs1 and bs0 must be 1, 0 to select the extended mode register (vs. the mode register)
a43p26161 preliminary (july, 2005, version 1.1) 10 amic technology, corp. power up sequence 1. apply power and start clock, attempt to maintain cke = ?h ?, dqm = ?h? and the other pins are nop condition at inputs. 2. maintain stable power, stable clock and nop input condition for a minimum of 200 s. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the m ode register. the device is now ready for normal operation. 6. issue a extended mode regist er set command to define ds or pasr operat ing type of the device after normal mrs. cf.) sequence of 4 & 5 may be changed. emrs cycle is not mandatory and the emrs command needs to be issued only when ds or pasr is used. the default state without emrs command issued is the half driver strength and full array refreshed. the device is now ready for the operation selected by emrs. for operating with ds or pasr, set ds or pasr mode in emrs setting stage. in order to adjust another mode in the stat e of ds or pasr mode, additional emrs se t is required but power up sequence is not needed again at this time. in that case, all banks have to be in idle state prior to adjusting emrs set. burst sequence (burst length = 4) initial address a1 a0 sequential interleave 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 burst sequence (burst length = 8) initial address a2 a1 a0 sequential interleave 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
a43p26161 preliminary (july, 2005, version 1.1) 11 amic technology, corp. device operations clock (clk) the clock input is used as the reference for all sdram operations. all operations are synchronized to the positive going edge of the clock. the clock transitions must be monotonic between vil and vih. during operation with cke high all inputs are assumed to be in valid state (low or high) for the duration of set up and hold time around positive edge of the clock for proper functionality and icc specifications. clock enable (cke) the clock enable (cke) gates the clock onto sdram. if cke goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. all other inputs are ignored from the next clock cycle after cke goes low. when all banks are in the idle state and cke goes low synchronously with clock, the sdram enters the power down mode from the next clock cycle. the sdram remains in the power down mode ignoring the other inputs as long as cke remains low. the power down exit is synchronous as the internal clock is suspended. when cke goes high at least ?t ss + 1 clock ? before the high going edge of the clock, then the sdram becomes active from the same clock edge accepting all the input commands. bank select (bs0, bs1) this sdram is organized as 4 independent banks of 1,048,576 words x 16 bits memory arrays. the bs0, bs1 inputs is latched at the time of assertion of ras and cas to select the bank to be used for the operation. the bank select bs0, bs1 is latched at bank activate, read, write mode register set and precharge operations. address input (a0 ~ a11) the 20 address bits required to decode the 1,048,576 word locations are multiplexed into 12 address input pins (a0~a11). the 12 bit row address is latched along with ras , bs0 and bs1 during bank activate command. the 8 bit column address is latched along with cas , we , bs0 and bs1during read or write command. nop and device deselect when ras , cas and we are high, the sdram performs no operation (nop). nop does not initiate any new operation, but is needed to complete operations which require more than single clock like bank activate, burst read, auto refresh, etc. the device deselect is also a nop and is entered by asserting cs high. cs high disables the command decoder so that ras , cas and we , and all the address inputs are ignored. power-up the following sequence is recommended for power up 1. power must be applied to either cke and dqm inputs to pull them high and other pins are nop condition at the inputs before or along with vdd (and vddq) supply. the clock signal must also be asserted at the same time. 2. after vdd reaches the desired voltage, a minimum pause of 200 microseconds is required with inputs in nop condition. 3. all banks must be precharged now. 4. perform a minimum of 2 auto refresh cycles to stabilize the internal circuitry. 5. perform a mode register set cycle to program the cas latency, burst length and burst type as the default value of mode register is undefined. at the end of one clock cycle from the mode register set cycle, the device is ready for operation. when the above sequence is used for power-up, all the out-puts will be in high impedance state. the high impedance of outputs is not guaranteed in any other power-up sequence. cf.) sequence of 4 & 5 may be changed. mode register set (mrs) the mode register st ores the data for c ontrolling the various operation modes of sdram. it programs the cas latency, addressing mode, burst length, test mode and various vendor specific options to make sdram useful for variety of different applications. the default value of the mode register is not defined, therefore the mode register must be written after power up to operate the sdram. the mode register is written by asserting low on cs , ras , cas , we (the sdram should be in active mode with cke already high prior to writing the mode register). the state of address pins a0~a11, bs0 and bs1 in the same cycle as cs , ras , cas , we going low is the data written in the mode register. one clock cycle is required to complete the write in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length field uses a0~a2, burst type uses a3, addressing mode uses a4~a6, a7~a8, a9, bs0 and bs1 are used for vendor specific options or test mode. and the write burst length is programmed using a9. a7~a8, a10~a11, bs0 and bs1 must be set to low for normal sdram operation. refer to table for specific codes for various burst length, addressing modes and cas latencies. bs0 and bs1 have to be set to ?0? to enter the mode register. extended mode register (emrs) the extended mode register controls functions beyond those controlled by the mode register. these additional functions are unique to amic?s low power sdram and includes a refresh period field (tcsr) for temperature compensated self-refresh and a partial-array self refresh field (pasr). the pasr field is used to specify whether only bank a and bank b,or bank a,or 1/2 of bank a,or 1/4 of bank a be refreshed. disable banks w ill not be refreshed in self- refresh mode and written data will be lost. when only bank a is selected it is possible to partial select only half or one quarter of bank a. the tcr field has four entries to set refresh period during self-refresh depending on the case temperature of the low power devices. the extended mode register is programmed via the mode register set command (with bs0=0 and bs1=1) and retains
a43p26161 preliminary (july, 2005, version 1.1) 12 amic technology, corp. the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. violating either these requirements result in unspecified operation. unused bit a7 to a11 have to be set to ?0?. bank activate the bank activate command is used to select a random row in an idle bank. by asserting low on ras and cs with desired row and bank addresses, a row access is initiated. the read or write operation can occur after a time delay of t rcd (min) from the time of bank activation. t rcd (min) is an internal timing parameter of sdram, therefore it is dependent on operating clock frequency. the minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t rcd (min) with cycle time of the clock and then rounding off the result to the next higher integer. the sdram has 4 internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of all banks simultaneously. also the noise generated during sensing of eac h bank of sdram is high requiring some time for power supplies to recover before the other bank can be sensed reliably. t rrd (min) specifies the minimum time required between activating different banks. the number of clock cycles required between different bank activation must be calculated similar to t rcd specification. the minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t ras (min) specification before a precharge command to that active bank can be asserted. the maximum time any bank can be in the active state is determined by t ras (max). the number of cycles for both t ras (min) and t ras (max) can be calculated similar to t rcd specification. burst read the burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. the burst read command is issued by asserting low on c s and cas with we being high on the positive edge of the clock. the bank must be active for at least t rcd (min) before the burst read command is issued. the first output appears cas latency number of clock cycles after the issue of burst read command. the burst length, burst sequence and latency from the burst read command is determined by the mode register which is al ready programmed. the burst read can be initiated on any column address of the active row. the address wraps around if the initial address does not start from a boundary such that number of outputs from each i/o are equal to the burst length programmed in the mode register. the output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. the burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. the burst stop command is valid at every page burst length. burst write the burst write command is similar to burst read command, and is used to write data into the sdram consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. by asserting low on cs , cas and we with valid column address, a write burst is initiated. the data inputs are provided for the initial address in the same clock cycle as the burst write command. the input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. the burst write can be terminated by issuing a burst read and dqm for blocking data inputs or burst write in the same or the other active bank. the burst stop command is valid only at full page burst length where the writing continues at the end of burst and the burst is wrap around. the write burst can also be terminated by using dqm for blocking data and precharging the bank ?t rdl ? after the last data input to be written into the active row. see dqm operation also. dqm operation the dqm is used to mask input and output operation. it works similar to oe during read operation and inhibits writing during write operation. the read latency is two cycles from dqm and zero cycle for write, which means dqm masking occurs two cycles later in the read cycle and occurs in the same cycle during write cycle. dqm operation is synchronous with the clock, therefore the masking occurs for a complete cycle. the dqm signal is important during burst interrupts of write with read or precharge in the sdram. due to asynchronous nature of the internal write, the dqm operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. precharge the precharge operation is per formed on an active bank by asserting low on cs , ras , we and a10/ap with valid ba of the bank to be precharged. the precharge command can be asserted anytime after t ras (min) is satisfied from the bank activate command in the desired bank. ?t rp ? is defined as the minimum time required to precharge a bank. the minimum number of clock cycles required to complete row precharge is calculated by dividing ?t rp ? with clock cycle time and rounding up to the next higher integer. care should be taken to make sure that burst write is completed or dqm is used to inhibit writing before precharge command is asserted. the maximum time any bank can be active is specified by t ras (max). therefore, each bank has to be precharged within t ras (max) from the bank activate command. at the end of precharge, the bank enters the idle state and is ready to be activated again. entry to power down, auto refresh, self refresh and mode register set etc, is possible only when all banks are in idle state. auto precharge the precharge operation can al so be performed by using auto precharge. the sdram internally generates the timing to satisfy t ras (min) and ?t rp ? for the programmed burst length and cas latency. the auto precharge command is issued at the same time as burst read or burst write by asserting high on a10/ap. if burst read or burst write command is issued with low on a10/ap, the bank is left active until a new command is asserted. once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state.
a43p26161 preliminary (july, 2005, version 1.1) 13 amic technology, corp. all banks precharge all banks can be precharged at the same time by using precharge all command. asserting low on cs , ras and we with high on a10/ap after both banks have satisfied t ras (min) requirement, performs precharge on all banks. at the end of trp after performing precharge all, all banks are in idle state. auto refresh the storage cells of sdram need to be refreshed every 64ms to maintain data. an auto refresh cycle accomplishes refresh of a single row of storage cells. the internal counter increments automatically on every auto refresh cycle to refresh all the rows. an auto refresh command is issued by asserting low on cs , ras and cas with high on cke and we . the auto refresh command can only be asserted with all banks being in idle state and the device is not in power down mode (cke is high in the previous cycle). the time required to complete the auto refresh operation is specified by ?t rc (min)?. the minimum number of clock cycles required can be calculated by dividing ?t rc ? with clock cycle time and then rounding up to the next higher integer. the auto refresh command must be followed by nop?s until the auto refresh operation is comple ted. all banks will be in the idle state at the end of auto refresh operation. the auto refresh is the preferred refresh mode when the sdram is being used for normal data transactions. the auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms. self refresh the self refresh is another refresh mode available in the sdram. the self refresh is the preferred refresh mode for data retention and low power operation of sdram. in self refresh mode, the sdram disables the internal clock and all the input buffers except cke. the refresh addressing and timing is internally generated to reduce power consumption. the self refresh mode is entered from all banks idle state by asserting low on cs , ras , cas and cke with high on we . once the self refresh mode is entered, only cke state being low matters, all the other inputs including clock are ignored to remain in the self refresh. the self refresh is exited by restarting the external clock and then asserting high on cke. this must be followed by nop?s for a minimum time of ?t rc ? before the sdram reaches idle state to begin normal operation. if the system uses burst auto refresh during normal operation, it is recommended to used burst 4096 auto refresh cycles immediately after exiting self refresh. deep power down mode the deep power down mode is an unique function on low power sdrams with very low standby currents. all internal voltage generators inside the low power sdrams are stopped and all memory data will be lost in this mode. to enter the deep power down mode all banks must be precharged and the necessary precharged delay t rp must occur.
a43p26161 preliminary (july, 2005, version 1.1) 14 amic technology, corp. 1) click suspended during write (bl=4) masked by cke q0 q1 q3 q0 q2 q3 suspended dout 2) clock suspended during read (bl=4) wr masked by cke d0 d1 d2 d3 d0 d1 d2 d3 not written dq(cl3) dq(cl2) internal clk cke cmd clk rd q2 q1 note: clk to clk disable/enable=1 clock basic feature and function descriptions 1. clock suspend 2. dqm operation * note : 1. dqm makes data out hi-z after 2 cl ocks which should masked by cke ?l?. 2. dqm masks both data-in and data-out. 1) write mask (bl=4) masked by cke q0 q2 q3 q1 q2 q3 dqm to data-out mask = 2 2) read mask (bl=4) wr masked by cke d0 d1 d3 d0 d1 d3 dqm to data-in mask = 0clk dq(cl3) dq(cl2) dqm cmd clk rd hi-z hi-z q0 q2 q4 2) read mask (bl=4) rd hi-z hi-z hi-z q6 q7 q8 hi-z q1 q3 hi-z hi-z q5 q6 q7 clk cmd cke dqm dq(cl2) dq(cl3)
a43p26161 preliminary (july, 2005, version 1.1) 15 amic technology, corp. 3. cas interrupt (i) note : 1. by ?interrupt?, it is possible to stop burst read/write by external command before the end of burst. by ? cas interrupt?, to stop burst read/write by cas access; read, write and block write. 2. t ccd : cas to cas delay. (=1clk) 3. t cdl : last data in to new column address delay. (= 1clk). 1) read interrupted by read (bl=4) note 1 rd rd ab qa0 qb0 qb1 qb2 qb3 qa0 qb0 qb1 qb2 qb3 clk cmd add dq(cl2) dq(cl3) t ccd note2 2) write interrupted by write (bl =2) wr wr ab clk cmd add t ccd note2 da0 db0 db1 t cdl note3 dq 3) write interrupted by read (bl =2) wr rd ab t ccd note2 da0 qb0 qb1 t cdl note3 dq(cl2) qb0 qb1 dq(cl3) da0
a43p26161 preliminary (july, 2005, version 1.1) 16 amic technology, corp. 4. cas interrupt (ii) : read interrupted write & dqm * note : 1. to prevent bus contention, t here should be at least one gap between data in and data out. 2. to prevent bus contention, dqm should be issued which makes a least one gap between data in and data out. rd wr d0 d1 d2 d3 rd wr d0 d1 d2 d3 wr rd hi-z hi-z d0 d1 d2 d3 rd wr d0 d1 d2 d3 q0 hi-z note 1 rd wr d0 d1 d2 d3 rd wr d0 d1 d2 d3 wr rd hi-z d0 d1 d2 d3 rd wr d0 d1 d2 q0 hi-z note 2 d0 d1 d2 d3 rd wr wr (1) cl=2, bl=4 clk i) cmd dqm dq ii) cmd dqm dq iii) cmd dqm dq iv) cmd dqm dq (2) cl=3, bl=4 clk i) cmd dqm dq ii) cmd dqm dq iii) cmd dqm dq iv) cmd dqm dq v) cmd dqm dq d3
a43p26161 preliminary (july, 2005, version 1.1) 17 amic technology, corp. 5. write interrupted by precharge & dqm note : 1. to inhibit invalid write, dqm should be issued. 2. this precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank pr echarge of dual banks operation. 6. precharge 7. auto precharge * note : 1. the row active command of the precharge bank can be issued after t rp from this point. the new read/write command of other acti ve bank can be issued from this point. at burst read/write with auto precharge, cas interrupt of the same /another bank is illegal. wr pre d0 d1 d2 d3 clk cmd dq 1) normal write (bl=4) t rdl rd pre q0 q1 q2 q3 clk cmd dq(cl2) 2) read (bl=4) q0 q1 q2 q3 dq(cl3) wr d0 d1 d2 d3 clk cmd dq 1) normal write (bl=4) note 1 rd q0 q1 q2 q3 clk cmd dq(cl2) 2) read (bl=4) q0 q1 q2 q3 dq(cl3) auto precharge starts note 1 auto precharge starts wr pre note 2 note 1 d0 d1 d2 d3 masked by dqm clk cmd dqm dq
a43p26161 preliminary (july, 2005, version 1.1) 18 amic technology, corp. 8. burst stop & interrupted by precharge wr d0 d1 d2 d3 clk cmd dqm dq 1) normal write (bl=4) pre t rdl note 1 wr d0 d1 d2 d3 clk cmd dqm dq 2) write burst stop (bl=8) stop t bdl note 2 d4 d5 rd q0 q1 clk cmd dq(cl2) 1) read interrupted by precharge (bl=4) pre note 3 dq(cl3) q0 q1 1 2 rd q0 q1 clk cmd dq(cl2) 4) read burst stop (bl=4) stop dq(cl3) q0 q1 1 2 9. mrs note : 1. t rdl : 1clk 2. t bdl : 1clk; last data in to burst stop delay. read or write burst stop command is valid at every burst length. 3. number of valid output data after row precharge or burst stop: 1,2 for cas latency = 2, 3 respectively. 4. pre: all banks precharge if necessary. mrs can be issued only when all banks are in precharged state. pre mrs note 1 clk cmd mode register set 2clk act t rp
a43p26161 preliminary (july, 2005, version 1.1) 19 amic technology, corp. 10. clock suspend exit & power down exit 11. auto refresh & self refresh * note : 1. active power down : one or more bank active state. 2. precharge power down : both bank precharge state. 3. the auto refresh is the same as cbr refresh of conventional dram. no precharge commands are requir ed after auto refresh command. during t rc from auto refresh command, other command can not be accepted. 4. before executing auto/self refresh command, both banks must be idle state. 5. mrs, bank active, auto/self refresh, power down mode entry. 6. during self refresh mode, refresh interval and refresh operation are performed internally. after self refresh entry, self refresh mode is kept while cke is low. during self refresh mode, all inputs expect cke w ill be don?t cared, and outputs will be in hi-z state. during t rc from self refresh exit command, any other command can not be accepted. before/after self refresh mode, burst auto refresh cycle (4k cycles ) is recommended. 2) self refresh clk cmd 1) auto refresh cke internal clk clk cmd sr cke pre note 4 pre ar cmd note 5 ~ ~ ~ ~ ~ ~ ~ ~ t rp t rc note 3 note 6 ~ ~ cmd ~ ~ note 4 t rp t rc ~ ~ ~ ~ ~ ~ 2) power down (=precharge power down) exit note 1 clk cmd 1) clock suspend (=active power down) exit rd t ss cke internal clk note 2 clk cmd act cke internal clk t ss nop
a43p26161 preliminary (july, 2005, version 1.1) 20 amic technology, corp. 12. about burst type control sequential counting at mrs a3=?0?. see the b urst sequence tabe.(bl=4,8) bl=1,2,4,8 and full page wrap around. basic mode interleave counting at mrs a3=? 1?. see the bu rst sequence tabe.(bl=4,8) bl=4,8 at bl=1,2 interleave counting = sequential counting random mode random column access t ccd = 1 clk every cycle read/write command with random column address can realize random column access. that is similar to extended data out (edo) operation of convention dram. 13. about burst length control 1 at mrs a2,1,0 = ?000?. at auto precharge, tras should not be violated. 2 at mrs a2,1,0 = ?001?. at auto precharge, tras should not be violated. 4 at mrs a2,1,0 = ?010? basic mode 8 at mrs a2,1,0 = ?011?. special mode brsw at mrs a9=?1?. read burst = 1,2,4,8, full page/write burst =1 at auto precharge of write, tras should not be violated. ras interrupt (interrupted by precharge) before the end of burst, row precharge command of the same bank stops read/write burst with row precharge. t rdl = 2 with dqm, valid dq after burst stop is 1,2 for cl=2,3 respectively during read/write burst with auto precharge, ras interrupt cannot be issued. interrupt mode cas interrupt before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. during read/write burst with auto precharge, cas interrupt can not be issued.
a43p26161 preliminary (july, 2005, version 1.1) 21 amic technology, corp. power on sequence for low power sdram key key high level is necessary high-z 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr bs0 a10/ap we dqm dq precharge (all banks) auto refresh auto refresh normal mrs row active (a-bank) : don't care ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ra ~ ~ ~ ~ ~ ~ ~ ~ bs1 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ra ~ ~ ~ ~ ~ ~ ~ ~ t pr t rc t rc extended mrs
a43p26161 preliminary (july, 2005, version 1.1) 22 amic technology, corp. single bit read-write-read cycles (same page) @cas latency=3, burst length=1 rb high t rcd t rp 0 12345678910111213141516171819 clock cke cs ras cas addr bs0, bs1 a10/ap we dqm dq row active read write row active : don't care t ch t cl t cc ra ca cb cc bs bs bs bs bs bs ra rb qa db qc t ras t rc t sh t ss *note 1 t sh t ss t ccd t sh t ss t sh t ss t ss t sh *note 2 *note 2,3 *note 2,3 *note 2,3 *note 4 *note 2 *note 3 *note 3 *note 3 *note 4 t sh t ss t sh t ss t sh t ss t ra c t sa c t slz t oh t shz read precharge
a43p26161 preliminary (july, 2005, version 1.1) 23 amic technology, corp. * note : 1. all inputs can be don?t care when cs is high at the clk high going edge. 2. bank active & read/write are controlled by bs0, bs1. bs1 bs0 active & read/write 0 0 bank a 0 1 bank b 1 0 bank c 1 1 bank d 3. enable and disable auto precharge function are controlled by a10/ap in read/write command. a10/ap bs1 bs0 operation 0 0 disable auto precharge, leave bank a active at end of burst. 0 1 disable auto precharge, leave bank b active at end of burst. 1 0 disable auto precharge, leave bank c active at end of burst. 0 1 1 disable auto precharge, leave bank d active at end of burst. 0 0 enable auto precharge, prec harge bank a at end of burst. 0 1 enable auto precharge, prec harge bank b at end of burst. 1 0 enable auto precharge, prec harge bank c at end of burst. 1 1 1 enable auto precharge, prec harge bank d at end of burst. 4. a10/ap and bs0, bs1 control bank prec harge when precharge command is asserted. a10/ap bs1 bs0 precharge 0 0 0 bank a 0 0 1 bank b 0 1 0 bank c 0 1 1 bank d 1 x x all banks
a43p26161 preliminary (july, 2005, version 1.1) 24 amic technology, corp. read & write cycle at same bank @burst length=4 high t rc t rcd 0 12345678910111213141516171819 clock cke cs ras cas addr bs0 we dqm dq (cl = 2) row active (a-bank) read (a-bank) precharge (a-bank) row active (a-bank) precharge (a-bank) : don't care *note 1 *note 2 ra ca0 rb cb0 ra rb a10/ap qa0 t oh qa1 qa2 qa3 db0 db1 db2 db3 t rac t sac *note 3 t shz *note 4 qa0 t oh qa1 qa2 qa3 db0 db1 db2 db3 t rac t sac *note 3 t shz *note 4 t rdl write (a-bank) dq (cl = 3) bs1 t rdl *note : 1. minimum row cycle times is requir ed to complete internal dram operation. 2. row precharge can interrupt burst on any cycle. [c as latency-1] valid output data available after row enters precharge. last valid output will be hi-z after t shz from the clock. 3. access time from row address. t cc *(t rcd + cas latency-1) + t sac 4. output will be hi-z after the end of burst. (1,2,4 & 8)
a43p26161 preliminary (july, 2005, version 1.1) 25 amic technology, corp. page read & write cycle at same bank @burst length=4 t rdl high t rcd 0 12345678910111213141516171819 clock cke cs ras cas addr bs0 we dqm dq (cl=2) row active (a-bank) read (a-bank) precharge (a-bank) : don't care *note 2 ra ca cb cc ra a10/ap qa0 qa1 qb0 qb1 dc0 dc1 dd0 dd1 qa0 qa1 qb0 write (a-bank) cd t cdl *note1 *note3 dc0 dc1 dd0 dd1 read (a-bank) write (a-bank) dq (cl=3) bs1 qb2 qb1 *note : 1. to write data before burst read ends, dqm should be asserted three cycle prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input, t rdl before row precharge, will be written. 3. dqm should mask invalid input data on pr echarge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally.
a43p26161 preliminary (july, 2005, version 1.1) 26 amic technology, corp. page read cycle at different bank @burst length = 4 read (c-bank) row active (d-bank) read (b-bank) read (a-bank) high 0 12345678910111213141516171819 clock cke cs ras cas addr bs1 row active (a-bank) row active (b-bank) : don't care raa rbb a10/ap cbb row active (c-bank) *note 1 *note 2 caa raa we dqm qbb2 qbb1 qaa0 qaa1 qaa2 qbb0 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 qbb2 qbb1 qaa0 qaa1 qaa2 qbb0 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 read (d-bank) precharge (c-bank) precharge (d-bank) dq (cl=2) dq (cl=3) bs0 rbb rcc rdd precharge (a-bank) precharge (b-bank) rcc ccc rdd cdd * note : 1. cs can be don?t care when ras , cas and we are high at the clock high going edge. 2. to interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
a43p26161 preliminary (july, 2005, version 1.1) 27 amic technology, corp. page write cycle at different bank @burst length=4 high 0 12345678910111213141516171819 clock cke cs ras cas addr bs1 row active (a-bank) row active (b-bank) : don't care a10/ap write (a-bank) we dbb1 dbb0 daa0 daa1 daa2 daa3 dbb2 dbb3 dcc0 dcc1 write (c-bank) precharge (all banks) dqm dq t cdl ddd0 ddd1 *note 2 t rdl *note 1 write (d-bank) write (b-bank) row active (c-bank) row active (d-bank) raa rbb cbb caa rcc rdd ccc cdd raa bs0 rbb rcc rdd cdd2 * note: 1. to interrupt burst write by row precharge, dqm should be asserted to mask invalid input data. 2. to interrupt burst write by row precharge, both the write and precharge banks must be the same.
a43p26161 preliminary (july, 2005, version 1.1) 28 amic technology, corp. read & write cycle at different bank @burst length=4 high 0 12345678910111213141516171819 clock cke cs ras cas addr bs1 row active (a-bank) read (a-bank) : don't care raa caa a10/ap rdb precharge (a-bank) cdb cbc raa we qaa2 qaa1 qaa0 qaa3 ddb0 write (d-bank) read (b-bank) dqm qbc0 qbc1 rbc rbc rdb t cdl *note 1 qaa3 qaa2 qaa0 qaa1 ddb0 ddb1 qbc0 ddb2 ddb3 qbc1 qbc2 dq (cl=2) ddb1 ddb2 ddb3 dq (cl=3) row active (b-bank) row active (d-bank) bs0 * note : t cdl should be met to complete write.
a43p26161 preliminary (july, 2005, version 1.1) 29 amic technology, corp. read & write cycle with auto precharge @burst length=4 high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr bs1 row active (a-bank) row active (d-bank) : don't care raa rbb a10/ap caa auto precharge start point (a-bank/cl=2) raa we qaa2 qaa1 qaa0 qaa3 ddb0 auto precharge start point (d-bank) dqm cbb qaa3 qaa2 qaa0 qaa1 ddb0 ddb1 ddb2 ddb3 dq (cl=2) ddb1 ddb2 ddb3 dq (cl=3) write with auto precharge (d-bank) rbb read with auto precharge (a-bank) bs0 auto precharge start point (a-bank/cl=3) *note : trcd should be controlled to meet minimum tras before internal precharge start. (in the case of burst length=1 & 2, brsw mode)
a43p26161 preliminary (july, 2005, version 1.1) 30 amic technology, corp. clock suspension & dqm operation cycl e @cas latency = 2, burst length=4 0 12345678910111213141516171819 clock cke cs ras cas addr bs1 row active : don't care ra a10/ap ca ra we dqm qa1 qb0 qb1 dc0 dq clock suspension read bank 0 cb read bank 0 qa0 dc2 * note 1 qa2 cc clock suspension t shz qa3 t shz write dqm write bank 0 read dqm bs0 * note : dqm needed to prevent bus contention.
a43p26161 preliminary (july, 2005, version 1.1) 31 amic technology, corp. read interrupted by precharge command & read burst stop cycle @burst length=full page high 0 12345678910111213141516171819 clock cke cs ras cas addr bs1 row active (a-bank) : don't care raa a10/ap caa we qaa3 qaa2 qaa1 qaa4 qab0 dqm qaa4 qaa3 qaa1 qaa2 qab0 qab1 qab2 qab3 dq (cl=2) qab1 qab2 qab3 dq (cl=3) precharge (a-bank) read (a-bank) cab read (a-bank) burst stop 1 qaa0 qab4 qab5 1 qaa0 2 qab4 qab5 2 bs0 raa * note : 1. at full page mode, burst is wrap-around at the end of burst. so auto precharge is impossible. 2. about the valid dq?s after burst stop, it is same as the case of ras interrupt. both cases are illustrated above ti ming diagram. see the label 1,2 on them. but at burst write, burst stop and ras interrupt should be compared carefully. refer the timing diagram of ?full page write burst stop cycle?. 3. burst stop is valid at every burst length.
a43p26161 preliminary (july, 2005, version 1.1) 32 amic technology, corp. write interrupted by precharge command & write burst stop cycle @ burst length = full page high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr bs1 row active (a-bank) : don't care raa a10/ap caa we dqm daa4 daa3 daa1 daa2 dab0 dab1 dab2 dab3 dq precharge (a-bank) write (a-bank) cab write (a-bank) burst stop daa0 dab4 dab5 t rdl t bdl * note 2 bs0 raa * note : 1. at full page mode, burst is wrap-around at the end of burst. so auto precharge is impossible. 2. data-in at the cycle of interrupted by prec harge cannot be written into the corresponding memory cell. it is defined by ac parameter of t rdl (=2clk). dqm at write interrupted by precharge command is needed to prevent invalid write. dqm should mask invalid input data on precharge co mmand cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 3. burst stop is valid at every burst length.
a43p26161 preliminary (july, 2005, version 1.1) 33 amic technology, corp. active/precharge power down mode @cas lantency=2, burst length=4 0 12345678910111213141516171819 clock cke cs ras cas addr bs1 precharge power-down exit : don't care a10/ap active power-down entry row active we qa2 read precharge dqm dq qa0 qa1 precharge power-down entry t ss t ss * note 2 * note 1 *note 3 t ss t ss ra ca ra active power-down exit ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ bs0 ~ ~ ~ ~ ~ ~ ~ ~ t shz * note : 1. all banks should be in idle state prior to entering precharge power down mode. 2. cke should be set high at least ?1clk + t ss ? prior to row active command. 3. cannot violate minimum refresh specification. (64ms)
a43p26161 preliminary (july, 2005, version 1.1) 34 amic technology, corp. self refresh entry & exit cycle * note : to enter self refresh mode 1. cs , ras & cas and cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs including the system clock can be don?t care except for cke. 3. the device remains in self refresh mode as long as cke stays ?low?. (cf.) once the device enters self refresh mode, mi nimum tras is required before exit from self refresh. to exit self refresh mode 4. system clock restart and be stable before returning cke high. 5. cs starts from high. 6. minimum trc is required after cke going high to complete self refresh exit. 7. 4k cycle of burst auto refresh is required bef ore self refresh entry and after self refresh exit. if the system uses burst refresh. 0 12345678910111213141516171819 clock cke cs ras cas addr bs0, bs1 : don't care a10/ap we self refresh exit auto refresh dqm dq self refresh entry t ss * note 4 * note 1 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ * note 3 * note 2 ~ ~ t ss * note 6 t rc min. ~ ~ ~ ~ * note 5 ~ ~ ~ ~ * note 7 * note 7 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ hi-z hi-z
a43p26161 preliminary (july, 2005, version 1.1) 35 amic technology, corp. mode register set cycle auto refresh cycle 0 123456 012345678910 clock cke cs ras cas addr : don't care we auto refresh new command dqm dq mrs ~ ~ ~ ~ * note 1 ~ ~ ~ ~ hi-z hi-z high high ~ ~ ~ ~ t rc *note 2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ key * note 3 ~ ~ ~ ~ new command ~ ~ ~ ~ ra * all banks precharge should be completed before m ode register set cycle and auto refresh cycle. mode register set cycle * note : 1. cs , ras , cas & we activation at the same clock cycle with address key will set internal mode register. 2. minimum 2 clock cycles is required before new ras activation. 3. please refer to mode register set table.
a43p26161 preliminary (july, 2005, version 1.1) 36 amic technology, corp. deep power down mode entry clk cs addr cke we cas ras dqm dq input dq output high-z t rp precharge command deep power down entry normal mode deep power down mode
a43p26161 preliminary (july, 2005, version 1.1) 37 amic technology, corp. deep power down mode exit clk cke cs ras cas we ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 200 us t rp t rc deep power down exit all banks precharge auto refresh auto refresh mode register set extended mode register set new command accepted here the deep power down mode is exited by asserting cke high. a fter the exit, the following sequence is needed to enter a new command: 1. maintain nop input conditions for a minimum of 200 s 2. issue precharge commands for all banks of the device 3. issue eight or more auto-refresh commands 4. issue a mode register set command to initialize the mode register 5. issue an extended mode register set comm and to initialize the extended mode register
a43p26161 preliminary (july, 2005, version 1.1) 38 amic technology, corp. function truth table (table 1) current state cs ra s cas we bs address action note h x x x x x nop l h h h x x nop l h h l x x illegal 2 l h l x bs ca, a10/ap illegal 2 l l h h bs ra row active; latch row address l l h l bs a10/ap nop 4 l l l h x x auto refresh or self refresh 5 idle l l l l op code mode register access 5 h x x x x x nop l h h h x x nop l h h l x x illegal 2 l h l h bs ca,a10/ap begin read; latch ca; determine ap l h l l bs ca,a10/ap begin write; latch ca; determine ap l l h h bs ra illegal 2 l l h l bs pa precharge row active l l l x x x illegal h x x x x x nop(continue burst to end row active) l h h h x x nop(continue burst to end row active) l h h l x x term burst row active l h l h bs ca,a10/ap term burst; begin read; latch ca; determine ap 3 l h l l bs ca,a10/ap term burst; begin write; latch ca; determine ap 3 l l h h bs ra illegal 2 l l h l bs a10/ap term burst; precharge timing for reads 3 read l l l x x x illegal h x x x x x nop(continue burst to end row active) l h h h x x nop(continue burst to end row active) l h h l x x term burst row active l h l h bs ca,a10/ap term burst; begin read; latch ca; determine ap 3 l h l l bs ca,a10/ap term burst; begin write; latch ca; determine ap 3 l l h h bs ra illegal 2 l l h l bs a10/ap term burst; precharge timing for writes 3 write l l l x x x illegal h x x x x x nop(continue burst to end precharge) l h h h x x nop(continue burst to end precharge) l h h l x x illegal l h l h bs ca,a10/ap illegal 2 l h l l bs ca,a10/ap illegal 2 l l h x bs ra, pa illegal read with auto precharge l l l x x x illegal 2
a43p26161 preliminary (july, 2005, version 1.1) 39 amic technology, corp. function truth table (table 1, continued) current state cs ras cas we bs address action note h x x x x x nop(continue burst to end precharge) l h h h x x nop(continue burst to end precharge) l h h l x x illegal l h l h bs ca,a10/ap illegal 2 l h l l bs ca,a10/ap illegal 2 l l h x bs ra, pa illegal write with auto precharge l l l x x x illegal 2 h x x x x x nop idle after t rp l h h h x x nop idle after t rp l h h l x x illegal l h l x bs ca,a10/ap illegal 2 l l h h bs ra illegal 2 l l h l bs a10/ap nop idle after t rp 2 precharge l l l x x x illegal 4 h x x x x x nop row active after t rcd l h h h x x nop row active after t rcd l h h l x x illegal l h l x bs ca,a10/ap illegal 2 l l h h bs ra illegal 2 l l h l bs a10/ap illegal 2 row activating l l l x x x illegal 2 h x x x x x nop idle after t rc l h h x x x nop idle after t rc l h l x x x illegal l l h x x x illegal refreshing l l l x x x illegal h x x x x x nop idle after 2 clocks l h h h h x nop idle after 2 clocks l h h l x x illegal l h l x x x illegal mode register accessing l l x x x x illegal abbreviations ra = row address bs = bank address ap = auto precharge nop = no operation command ca = column address pa = precharge all note: 1. all entries assume that cke was active (high) during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state: function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. nop to bank precharging or in idle stat e. may precharge bank indicated by bs (and pa). 5. illegal if any banks is not idle.
a43p26161 preliminary (july, 2005, version 1.1) 40 amic technology, corp. function truth table for cke (table 2) current state cke n-1 cke n cs ra s cas we address action note h x x x x x x invalid l h h x x x x exit self refresh abi after t rc 6 l h l h h h x exit self refresh abi after t rc 6 l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal self refresh l l x x x x x nop(maintain self refresh) h x x x x x x invalid l h h x x x x exit power down abi 7 l h l h h h x exit power down abi 7 l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal both bank precharge power down l l x x x x x nop(maintain power down mode) h h x x x x x refer to table 1 h l h x x x x enter power down 8 h l l h h h x enter power down 8 h l l h h l x illegal h l l h l x x illegal h l l l h h ra row (& bank ) active h l l l l h x enter self refresh 8 h l l l l l opcode mrs all banks idle l l x x x x x nop h h x x x x x refer to operations in table 1 h l x x x x x begin clock suspend next cycle 9 l h x x x x x exit clock suspend next cycle 9 any state other than listed above l l x x x x x maintain clock suspend abbreviations : abi = all banks idle note: 6. after cke?s low to high transition to exit self refresh mode, a minimum of t rc (min) has to be elapse before issuing a new command. 7. cke low to high transition is asynchronous as if it restarts internal clock. a minimum setup time ?tss + one clock? must be satisfied before any command can be issued other than exit. 8. power-down and self refresh can be entered only when all the banks are in idle state. 9. must be a legal command.
a43p26161 preliminary (july, 2005, version 1.1) 41 amic technology, corp. ordering information part no. min. cycle time (ns) max. clock frequency (mhz) access time package A43P26161G-75 7.5 133 6 ns 54b csp A43P26161G-75f 7.5 133 6 ns 54b pb-free csp A43P26161G-75u 7.5 133 6 ns 54b csp A43P26161G-75uf 7.5 133 6 ns 54b pb-free csp a43p26161v-75 7.5 133 6 ns 54 tsop (ii) a43p26161v-75f 7.5 133 6 ns 54 pb-free tsop (ii) a43p26161v-75u 7.5 133 6 ns 54 tsop (ii) a43p26161v-75uf 7.5 133 6 ns 54 pb-free tsop (ii) a43p26161g-95 9.5 105 7 ns 54b csp a43p26161g-95f 9.5 105 7 ns 54b pb-free csp a43p26161g-95u 9.5 105 7 ns 54b csp a43p26161g-95uf 9.5 105 7 ns 54b pb-free csp a43p26161v-95 9.5 105 7 ns 54 tsop (ii) a43p26161v-95f 9.5 105 7 ns 54 pb-free tsop (ii) a43p26161v-95u 9.5 105 7 ns 54 tsop (ii) a43p26161v-95uf 9.5 105 7 ns 54 pb-free tsop (ii) note: -u is for industrial operating temperature range -40oc to +85oc.
a43p26161 preliminary (july, 2005, version 1.1) 42 amic technology, corp. package information 54 ball (8 x 8 mm) outline dimensions unit: mm 1 2 3 4 5 6 7 8 9 a b c d e f g h j d d/2 e e e/2 d 1 e 1 a a 1 z b encapsulant max. 0.20 dimensions in mm symbol min. nom. max. a - - 1.00 a 1 0.20 0.25 0.30 e 7.95 8.00 8.05 e 1 6.40 bsc d 7.95 8.00 8.05 d 1 6.40 bsc e 0.80 bsc b 0.30 0.35 0.40 z - - 0.10
a43p26161 preliminary (july, 2005, version 1.1) 43 amic technology, corp. package information tsop 54l (type ii) outline dimensions unit: inches/mm 1 e1 e c 54 a 1 a 2 a d 0.1 e d b l detail "a" detail "a" 27 28 seating plane r1 r2 l 1 -c- 0.21 ref 0.665 ref s dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 0.004 0.006 0.05 - 0.15 a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.012 - 0.018 0.30 - 0.45 c 0.005 - 0.008 0.12 - 0.21 d 0.875 bsc 22.22 bsc s 0.028 ref 0.71 ref e 0.463 bsc 11.76 bsc e 1 0.400 bsc 10.16 bsc e 0.031 bsc 0.80 bsc l 0.016 0.020 0.024 0.40 0.50 0.60 l 1 0.031 ref 0.80 ref r 1 0.005 - - 0.12 - - r 2 0.005 - 0.010 0.12 - 0.25 0 - 8 0 - 8 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension s includes end flash.

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