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1 lt c1090 1090fc single chip 10-bit data acquisition system software programmable features: unipolar/bipolar conversions 4 differential/8 single ended inputs msb or lsb first data sequence variable data word length built-in sample and hold single supply 5v, 10v or 5v operation direct 4 wire interface to most mpu serial ports and all mpu parallel ports 30khz maximum throughput rate resolution: 10 bits total unadjusted error (ltc1090a): 1/2lsb max conversion time: 22 s supply current: 2.5ma max, 1.0ma typ the ltc 1090 is a data acquisition component which contains a serial i/o successive approximation a/d con- verter. it uses ltcmos tm switched capacitor technology to perform either 10-bit unipolar, or 9-bit plus sign bipolar a/d conversions. the 8-channel input multiplexer can be configured for either single ended or differential inputs (or combinations thereof). an on-chip sample and hold is included for all single ended input channels. the serial i/o is designed to be compatible with industry standard full duplex serial interfaces. it allows either msb or lsb first data and automatically provides 2? complement output coding in the bipolar mode. the output data word can be programmed for a length of 8, 10, 12 or 16 bits. this allows easy interface to shift registers and a variety of processors. the ltc1090a is specified with total unadjusted error (including the effects of offset, linearity and gain errors) less than 0.5lsb. the ltc1090 is specified with offset and linearity less than 0.5lsb but with a gain error limit of 2lsb for applications where gain is adjustable or less critical. features descriptio u ltcmos is a trademark of linear technology corp. , ltc and lt are registered trademarks of linear technology corporation. key specificatio s u ltc1090 ?ta02 output code 0 512 1024 error (lsbs) 1.0 0.5 0.0 0.5 ?.0 linearity plot typical applicatio u 5v ltc1090 mpu (e.g., 8051) for 8051 code see applications information section differential input bipolar input ?v 5v ?v (+) (? t ltc1090 ?ta01 unipolar inputs p1.1 d out p1.2 d in p1.3 sclk p1.4 cs serial data link ?unipolar input
2 lt c1090 1090fc absolute axi u rati gs w ww u supply voltage (v cc ) to gnd or v ................................ 12v negative supply voltage (v ) ..................... 6v to gnd voltage: analog and reference inputs .................................... (v ) 0.3v to v cc 0.3v digital inputs ......................................... 0.3v to 12v digital outputs .............................. 0.3v to v cc 0.3v power dissipation .............................................. 500mw operating temperature range ltc1090ac/ltc1090c ........................40 c to 85 c ltc1090am/ltc1090m (obsolete) ...... 55 c to 125 c storage temperature range ................. 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c (notes 1 and 2) package/order i for atio uu w consult ltc marketing for parts specified with wider operating temperature ranges. reco e ded operati g co ditio s u u u uw w ltc1090/ltc1090a symbol parameter conditions min max units v cc positive supply voltage v = 0v 4.5 10 v v negative supply voltage v cc = 5v 5.5 0 v f sclk shift clock frequency v cc = 5v 0 1.0 mhz f aclk a/d clock frequency v cc = 5v 25 c 0.01 2.0 mhz 85 c 0.05 2.0 125 c 0.25 2.0 t cyc total cycle time see operating sequence 10 sclk + cycles 48 aclk t hcs hold time, cs low after last sclk v cc = 5v 0 ns t hdi hold time, d in after sclk v cc = 5v 150 ns t sucs setup time cs before clocking in first address bit (note 9) v cc = 5v 2 aclk cycles 1 s t sudi setup time, d in stable before sclk v cc = 5v 400 ns t whaclk aclk high time v cc = 5v 127 ns t wlaclk aclk low time v cc = 5v 200 ns t whcs cs high time during conversion v cc = 5v 44 aclk cycles obsolete package consider the sw or n package for alternate source 1 2 3 4 5 6 7 8 9 10 top view j package 20-lead cerdip t jmax = 150 c ja = 70 c/w sw package 20-lead plastic so wide n package 20-lead pdip 20 19 18 17 16 15 14 13 12 11 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc aclk sclk d in d out cs ref + ref v agnd ltc1090acn ltc1090cn ltc1090csw ltc1090amj LTC1090MJ ltc1090acj ltc1090cj order part number t jmax = 150 c, ja = 70 c/w t jmax = 110 c, ja = 90 c/w ltc1090 ?poi01
3 lt c1090 1090fc co verter a d ultiplexer characteristics u w u ltc1090a ltc1090 parameter conditions min typ max min typ max units offset error (note 4) 0.5 0.5 lsb linearity error (notes 4 and 5) 0.5 0.5 lsb gain error (note 4) 1.0 2.0 lsb total unadjusted error v ref = 5.000v 1.0 lsb (notes 4 and 6) reference input resistance 10 10 k ? analog and ref input range (note 7) (v ) ?0.05v to v cc 0.05v v on channel leakage current on channel = 5v 11 a (note 8) off channel = 0v on channel = 0v ? ? a off channel = 5v off channel leakage current on channel = 5v ? ? a (note 8) off channel = 0v on channel = 0v 11 a off channel = 5v the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. (note 3) ltc1090/ltc1090a symbol parameter conditions min typ max units t acc delay time from cs to d out data valid (note 9) 2 aclk cycles t smpl analog input sample time see operating sequence 5 sclk cycles t conv conversion time see operating sequence 44 aclk cycles t ddo delay time, sclk to d out data valid see test circuits 250 450 ns t dis delay time, cs to d out hi-z see test circuits 140 300 ns ns t en delay time, 2nd clk to d out enabled see test circuits 150 400 ns ns t hdo time output data remains valid after sclk 50 ns t f d out fall time see test circuits 90 300 ns ns t r d out rise time see test circuits 60 300 ns ns c in input capacitance analog inputs on channel 65 pf off channel 5 pf digital inputs 5 pf the denotes specifications which apply over the full operating temperature range, otherwise specification are t a = 25 c. (note 3) ac electrical characteristics
4 lt c1090 1090fc d igital a d dc electrical characteristics u ltc1090/ltc1090a symbol parameter conditions min typ max units v ih high level lnput voltage v cc = 5.25v 2.0 v v il low level input voltage v cc = 4.75v 0.8 v i ih high level lnput current v in = v cc 2.5 a i il low level input current v in = 0v ?.5 a v oh high level output voltage v cc = 4.75v, l o = 10 a 4.7 v v cc = 4.75v, l o = 360 a 2.4 4.0 v v ol low level output voltage v cc = 4.75v, l o = 1.6ma 0.4 v i oz hi-z output leakage v out = v cc , cs high 3 a v out = 0v, cs high ? a i source output source current v out = 0v 10 ma i sink output sink current v out = v cc 10 ma i cc positive supply current cs high, ref + open 1.0 2.5 ma i ref reference current v ref = 5v 0.5 1.0 ma i negative supply current cs high, v = 5v 150 a the denotes specifications which apply over the full operating temperature range, otherwise specification are t a = 25 c. (note 3) note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd, agnd and ref wired together (unless otherwise noted). note 3: v cc = 5v, v ref + = 5v, v ref ?= 0v, v = 0v for unipolar mode and ? v for bipolar mode, aclk = 2.0mhz, sclk = 0.5mhz unless otherwise specified. note 4: these specs apply for both unipolar and bipolar modes. in bipolar mode, one lsb is equal to the bipolar input span (2v ref ) divided by 1024. for example, when v ref = 5v, 1lsb (bipolar) = 2(5v)/1024 = 9.77mv. note 5: linearity error is specified between the actual end points of the a/d transfer curve. note 6: total unadjusted error includes offset, gain, linearity, multiplexer and hold step errors. note 7: two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below v or one diode drop above v cc . be careful during testing at low v cc levels (4.5v), as high level reference or analog inputs (5v) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for inputs near full-scale. this spec allows 50mv forward bias of either diode. this means that as long as the reference or analog input does not exceed the supply voltage by more than 50mv, the output code will be correct. to achieve an absolute 0v to 5v input voltage range will therefore require a minimum supply voltage of 4.950v over initial tolerance, temperature variations and loading. note 8: channel leakage current is measured after the channel selection. note 9: to minimize errors caused by noise at the chip select input, the internal circuitry waits for two aclk falling edges after a chip select falling edge is detected before responding to control input signals. therefore, no attempt should be made to clock an address in or data out until the minimum chip select setup time has elapsed.
5 lt c1090 1090fc on and off channel leakage current voltage waveforms for d out delay time, t ddo voltage waveforms for t en and t dis test circuits sclk 0.8v 2.4v 0.4v 2.4v t r t f 0.4v t ddo d out d out ltc1090 ?tc02 voltage waveforms for d out rise and fall times, t r , t f i on 5v off channels on channels polarity i off a a ltc1090 ?tc01 aclk cs d out waveform 1 (see note 1) d out waveform 2 (see note 2) 1 note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control 2 ltc1090 ?tc03 2.4v 90% 2.0v 0.4v 10% t en t dis load circuit for t dis and t en load circuit for t ddo , t r , and t f 3k 100pf d out 1.4v test point ltc1090 ?tc05 waveform 1 3k 100pf d out test point waveform 2 5v ltc1090 ?tc04
6 lt c1090 1090fc uu u pi fu ctio s # pin function description 1-8 ch0 to ch7 analog inputs the analog inputs must be free of noise with respect to agnd. 9 com common the common pin defines the zero reference point for all single ended inputs. it must be free of noise and is usually tied to the analog ground plane. 10 dgnd digital ground this is the ground for the internal logic. tie to the ground plane. 11 agnd analog ground agnd should be tied directly to the analog ground plane. 12 v negative supply tie v to most negative potential in the circuit. (ground in single supply applications.) 13,14 ref , ref + reference inputs the reference inputs must be kept free of noise with respect to agnd. 15 cs chip select input a logic low on this input enables data transfer. 16 d out digital data output the a/d conversion result is shifted out of this output. 17 d in data input the a/d configuration word is shifted into this input. 18 sclk shift clock this clock synchronizes the serial data transfer. 19 aclk a/d conversion clock this clock controls the a/d conversion process. 20 v cc positive supply this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. block diagra w d in 17 d out 16 sclk 18 ltc1090 ?bd01 ch0 1 ch1 2 ch2 3 ch3 4 ch4 5 ch5 6 ch6 7 ch7 8 com 9 v cc 20 input shift register output shift register cs 15 aclk 19 control and timing 10-bit sar sample and hold analog input mux comp ref 13 10-bit capacitive dac ref + v 12 agnd 11 dgnd 10 14
7 lt c1090 1090fc typical perfor a ce characteristics uw supply current vs supply voltage supply current vs temperature reference current vs temperature unadjusted offset error vs reference voltage linearity error vs reference voltage change in gain error vs reference voltage offset error vs supply voltage linearity error vs supply voltage change in gain error vs supply voltage supply voltage, v cc (v) 4 0 offset error (lsbs) 0.25 0.5 0.75 1.0 1.25 5 678 ltc1090 ?tpc07 910 v ref = 4v aclk = 2mhz v os = 1.25mv at v cc = 5v supply voltage, v cc (v) 4 0 linearity error (lsbs) 0.25 0.5 0.75 1.0 1.25 5 678 ltc1090 ?tpc08 910 v ref = 4v aclk = 2mhz supply voltage, v cc (v) 4 change in gain error (lsbs) 0.5 0.25 0 0.25 0.5 5 678 ltc1090 ?tpc09 910 v ref = 4v aclk = 2mhz supply voltage, v cc (v) 4 0 supply current, i cc (ma) 1 2 3 4 6 5 678 ltc1090 ?tpc01 910 5 ref + open aclk = 2mhz cs = v cc t a = 25 c ambient temperature, t a ( c) ?0 supply current, i cc (ma) 1.0 1.2 1.4 25 75 ltc1090 ?tpc02 0.8 0.6 ?5 0 50 100 125 0.4 0.2 ref + open aclk = 2mhz cs = 5v v cc = 5v ambient temperature, t a ( c) ?0 reference current, i ref (ma) 0.4 0.5 0.6 25 75 ltc1090 ?tpc03 0.3 0.2 ?5 0 50 100 125 0.1 0 v ref = 5v reference voltage, v ref (v) 0.2 0 offset error (lsbs = ?v ref ) 2 4 6 8 1.0 5.0 ltc1090 ?tpc04 10 1 3 5 7 9 1 1024 v os = 0.5mv v os = 1mv v cc = 5v 1 1024 reference voltage, v ref (v) 0 linearity error (lsbs = ?v ref ) 0.75 1.0 1.25 4 ltc1090 ?tpc05 0.5 0.25 0 1 2 3 5 v cc = 5v 1 1024 reference voltage, v ref (v) 0 change in gain error (lsbs = ?v ref ) 0.75 1.0 1.25 4 ltc1090 ?tpc06 0.5 0.25 0 1 2 3 5 v cc = 5v
8 lt c1090 1090fc typical perfor a ce characteristics uw change in offset error vs temperature change in linearity error vs temperature change in gain error vs temperature maximum conversion clock rate vs temperature maximum conversion clock rate vs reference voltage maximum conversion clock rate vs supply voltage maximum conversion clock rate vs source resistance maximum filter resistor vs cycle time sample-and-hold acquisition time vs source resistance *maximum aclk frequency represents the aclk frequency at which a 0.1lsb shift in the error at any code transition from its 2mhz valve is first detected. **maximum r filter represents the filter resistor valve at which a 0.1lsb shift change in full scale error from its value at r filter = 0 is first detected. ambient temperature, t a ( c) ?0 magnitude of offset change, ?? offset ? (lsbs) 0.4 0.5 0.6 25 75 ltc1090 ?tpc10 0.3 0.2 ?5 0 50 100 125 0.1 0 v cc = 5v v ref = 5v aclk = 2mhz ambient temperature, t a ( c) ?0 magnitude of linearity change, ?? linearity ? (lsbs) 0.4 0.5 0.6 25 75 ltc1090 ?tpc11 0.3 0.2 ?5 0 50 100 125 0.1 0 v cc = 5v v ref = 5v aclk = 2mhz ambient temperature, t a ( c) ?0 magnitude of gain change, ?? gain ? (lsbs) 0.4 0.5 0.6 25 75 ltc1090 ?tpc12 0.3 0.2 ?5 0 50 100 125 0.1 0 v cc = 5v v ref = 5v aclk = 2mhz ambient temperature, t a ( c) ?0 maximum aclk frequency* (mhz) 4 5 6 25 75 ltc1090 ?tpc13 3 2 ?5 0 50 100 125 1 0 v cc = 5v v ref = 5v reference voltage, v ref (v) 0 maximum aclk frequency* (mhz) 3 4 5 4 ltc1090 ?tpc14 2 1 0 1 2 3 5 v cc = 5v t a = 25 c supply voltage, v cc (v) 4 7 6 5 4 3 2 1 0 79 ltc1090 ?tpc15 56 810 maximum aclk frequency* (mhz) v ref = 4v t a = 25 c r source ( ? ) 10 0 maximum aclk frequency* (mhz) 3 4 5 100 1k 10k ltc1090 ?tpc16 2 1 + input input v in v cc = 5v v ref = 5v t a = 25 c r source cycle time, t cyc ( s) 100 maximum r filter ** ( ? ) 1k 10k 100k 100 1000 10k ltc1090 ?tpc17 10 10 + r filter c filter 1 f v in _ r source + ( ? ) 100 0.1 s & h acquisition time to 0.1% ( s) 1 10 1k 10k ltc1090 ?tpc18 + r source + v in _ v ref = 5v v cc = 5v t a = 25 c 0 to 5v input step
9 lt c1090 1090fc typical perfor a ce characteristics uw digital input logic threshold vs supply voltage input channel leakage current vs temperature noise error vs reference voltage the ltc1090 is a data acquisition component which contains the following functional blocks: 1. 10-bit successive approximation capacitive a/d converter 2. analog multiplexer (mux) 3. sample and hold (s/h) 4. synchronous, full duplex serial interface 5. control and timing logic digital considerations 1. serial interface the ltc1090 communicates with microprocessors and other external circuitry via a synchronous, full duplex, four wire serial interface (see operating sequence). the shift clock (sclk) synchronizes the data transfer with each bit being transmitted on the falling sclk edge and captured on the rising sclk edge in both transmit- ting and receiving systems. the data is transmitted and received simultaneously (full duplex). operating sequence (example: differential inputs (ch3 to ch2), bipolar, msb first and 10-bit word length) reference voltage, v ref (v) 0.2 peak-to-peak noise error (lsbs) 0.5 1.0 2.0 15 ltc1090 ?tpc21 1.5 0.25 0.75 1.75 1.25 ltc1090 noise = 200 v peak-to-peak applicatio s i for atio wu uu supply voltage, v cc (v) 4 0 logic threshold (v) 1 2 3 4 5678 ltc1090 ?tpc19 910 t a = 25 c ambient temperature, t a ( c) ?0 input channel leakage current (na) 100 300 400 500 1000 700 0 50 75 ltc1090 ?tpc20 200 800 900 600 ?5 25 100 125 guaranteed on channel off channels ltc1090 ?ai01 b9 (sb) shift a/d result out and new configuration word in b8 b7 b6 b5 b4 b3 b2 b1 b0 shift configuration word in odd/ sign sgl/ diff sel1 d in cs 15810 sclk d out sel0 uni msbf wl1 wl0 t cyc t smpl t conv don? care don? care
10 lt c1090 1090fc data transfer is initiated by a falling chip select (cs) signal. after the falling cs is recognized, an 8-bit input word is shifted into the d in input which configures the ltc1090 for the next conversion. simultaneously, the result of the previous conversion is output on the d out line. at the end of the data exchange the requested conversion begins and cs should be brought high. after t conv , the conversion is complete and the results will be available on the next data transfer cycle. as shown below, the result of a conversion is delayed by one cs cycle from the input word requesting it. 2. input data word the ltc1090 8-bit input data word is clocked into the d in input on the first eight rising sclk edges after chip select is recognized. further inputs on the d in pin are then ignored until the next cs cycle. the eight bits of the input word are defined as follows: multiplexer (mlix) address the first four bits of the input word assign the mux configuration for the requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and ?signs in the selected row of table 1. note that in differential mode (sgl/diff = o) measurements are limited to four adjacent input pairs with either polarity. in single ended mode, all input channels are measured with respect to com. figure 1 shows some examples of multiplexer assignments. table 1. multiplexer channel selection mux address differential channel selection sgl/ odd select diff sign 1 0 0 1 234567 0000+ 0001 + 0010 + 0011 + 0100+ 0101 + 0110 + 0111 + mux address single ended channel selection sgl/ odd/ select diff sign 1 0 0 1 2 3 4 5 6 7 com 1000+ 1001 + 1010 + 1011 + 1100 + 1101 + 1110 + 1111 + applicatio s i for atio wu uu ltc1090 ?ai02 data t ransfer t conv a/d conversion d out d in d in w ord 1 d out w ord 0 t conv a/d conversion data t ransfer d in w ord 2 d out w ord 1 d in w ord 3 d out w ord 2 ltc1090?ai03 data input (d in ) word: odd/ sign select 1 select 0 uni msbf wl1 w ord length mux address unipolar/ bipolar msb first/ lsb first wl0 sgl/ diff
11 lt c1090 1090fc 4 differential 8 single ended combinations of differential and single ended changing the mux assignment ?n the fly figure 1. examples of multiplexer options on the ltc1090 unipolar/bipolar (uni) the fifth input bit (uni) determines whether the conver- sion will be unipolar or bipolar. when uni is a logical one, a unipolar conversion will be performed on the selected input voltage. when uni is a logical zero, a bipolar conver- sion will result. the input span and code assignment for each conversion type are shown in the figures below. unipolar transfer curve (uni = 1) bipolar transfer curve (uni = 0) applicatio s i for atio wu uu ltc1090 ?ai04a 0,1 channel 2,3 4,5 6,7 +( ?) ? + ) +( ?) ? + ) +( ?) ? + ) +( ?) ? + ) ltc1090 ?ai04b channel 0 1 2 3 4 5 6 7 com ( ?) + + + + + + + + ltc1090 ?ai04c + + + + 0,1 channel 2,3 4 5 6 7 + + com ( ) ltc1090 ?ai04d 4,5 6,7 + + com (unused) 1st conversion ltc1090 ?ai04e 5,4 6 7 + + + com ( ) 2nd conversion ltc1090 ?ai05 1111111111 1111111110 0000000001 0000000000 ov 1lsb v ref ?2lsb v ref ?1lsb v ref v in ltc1090 ?ai06 0111111111 0111111110 1111111111 1111111110 0000000001 0000000000 1000000001 1000000000 v ref ?2lsb ? ref + 1lsb v ref ?1lsb v ref ? ref v in 2lsb 1lsb 1lsb
12 lt c1090 1090fc unipolar output code (uni = 1) input voltage output code input voltage (v ref = 5v) 1111111111 v ref ?1lsb 4.9951v 1111111110 v ref ?2lsb 4.9902v 0000000001 1lsb 0.0049v 0000000000 0v 0v bipolar output code (uni = 0) input voltage output code input voltage (v ref = 5v) 0111111111 v ref ?1lsb 4.9902v 0111111110 v ref ?2lsb 4.9805v 0000000001 1lsb 0.0098v 0000000000 0v 0v 1111111111 1lsb 0.0098v 1111111110 2lsb 0.0195v 1000000001 ?(v ref ) + 1lsb 4.9902v 1000000000 ?(v ref ) 5.000v msb first/lsb first format (msbf) the output data of the ltc1090 is programmed for msb first or lsb first sequence using the msbf bit. for msb first output data the input word clocked to the ltc1090 should always contain a logical one in the sixth bit location (msbf bit). likewise for lsb first output data, the input word clocked to the ltc1090 should always contain a zero in the msbf bit location. the msbf bit in a given d in word will control the order of the next d out word. the msbf bit affects only the order of the output data word. the order of the input word is unaffected by this bit. msbf output format 0l sb first 1 msb first word length (wl1, wl0) the last two bits of the input word (wl1 and wl0) program the output data word length of the ltc1090. word lengths of 8, 10, 12 or 16 bits can be selected according to the following table. the wl1 and wl0 bits in a given d in word control the length of the present, not the next, d out word. wl1 and wl0 are never ?on? cares and must be set for the correct d out word length even when a ?ummy?d in word is sent. on any transfer cycle, the word length should be made equal to the number of sclk cycles sent by the mpu. wl1 wl0 output word length 00 8 bits 01 10 bits 10 12 bits 11 16 bits figure 2 shows how the data output (d out ) timing can be controlled with word length selection and msb/lsb first format selection. 3. deglitcher a deglitching circuit has been added to the chip select input of the ltc1090 to minimize the effects of errors caused by noise on that input. this circuit ignores changes in state on the cs input that are shorter in duration than 1 aclk cycle. after a change of state on the cs input, the ltc1090 waits for two falling edges of the aclk before recognizing a valid chip select. one indication of cs low recognition is the d out line becoming active (leaving the hi-z state). note that the deglitching applies to both the rising and falling cs edges. applicatio s i for atio wu uu high z high z aclk aclk v alid output d out d out cs cs low cs recognized internally high cs recognized internally ltc1090 ?ai07
13 lt c1090 1090fc 8-bit word length 10-bit word length 12-bit word length 16-bit word length figure 2. data output (d out) timing with different word lengths applicatio s i for atio wu uu (sb) sclk d out msb first d out lsb first 18 b9 b8 b7 b6 b5 b4 b3 b0 b1 b2 b3 b4 b5 b6 b2 b7 cs t smpl t conv the last two bits are truncated ltc1090 ?ai08a (sb) (sb) sclk d out msb first d out lsb first 1 10 b9 b8 b7 b6 b5 b4 b3 b0 b1 b2 b3 b4 b5 b6 b2 b1 b0 b7 b8 b9 cs t smpl t conv ltc1090 ?ai08b (sb) (sb) sclk d out msb first d out lsb first 1 12 10 b9 b8 b7 b6 b5 b4 b3 b0 b1 b2 b3 b4 b5 b6 b2 b1 b0 b7 b8 b9 cs t smpl t conv fill zeroes ** ltc1090 ?ai08c (sb) (sb) sclk d out msb first d out lsb first 1 16 10 b9 b8 b7 b6 b5 b4 b3 b0 b1 b2 b3 b4 b5 b6 b2 b1 b0 b7 b8 b9 cs t smpl t conv fill zeroes ** * *** *in unipolar mode, these bits are filled with zeroes. in bipolar mode, the sign bit is extended into these locations ltc1090 ?ai08d
14 lt c1090 1090fc 4. cs low during conversion in the normal mode of operation, cs is brought high during the conversion time (see figure 3). the serial port ignores any sclk activity while cs is high. the ltc1090 will also operate with cs low during the conversion. in this mode, sclk must remain low during the conversion as shown in figure 4. after the conversion is complete, the d out line will become active with the first output bit. then the data transfer can begin as normal. 5. microprocessor interfaces the ltc1090 can interface directly (without external hard- ware) to most popular microprocessor (mpu) synchro nous figure 3. cs high during conversion figure 4. cs low during conversion applicatio s i for atio wu uu ltc1090 ?ai09 b9 shift result out and new address in b8 b7 b6 b5 b4 b3 b2 b1 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 odd/ sign sgl/ diff sel 1 d out sclk sel 0 uni msbf wl1 wl0 odd/ sign sgl/ diff sel 1 sel 0 uni msbf wl1 wl0 t smpl sample analog input 40 to 44 aclk cycles shift mux address in d in cs don? care ltc1090 ?ai10 b9 shift result out and new address in b8 b7 b6 b5 b4 b3 b2 b1 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 odd/ sign sgl/ diff sel 1 sclk d out sel 0 uni msbf wl1 wl0 odd/ sign sgl/ diff sel 1 sel 0 uni msbf wl1 wl0 t smpl sample analog input 40 to 44 aclk cycles sclk must remain low shift mux address in d in cs don? care
15 lt c1090 1090fc serial formats (see table 2). if an mpu without a serial interface is used, then 4 of the mpu? parallel port lines can be programmed to form the serial link to the ltc1090. included here are three serial interface examples and one example showing a parallel port programmed to form the serial interface. table 2. microprocessors with hardware serial interfaces compatible with the ltc1090** part number type of interface motorola mc6805s2, s3 spi mc68hc11 spi mc68hc05 spi rca cdp68hc05 spi hitachi hd6305 sci synchronous hd63705 sci synchronous hd6301 sci synchronous hd63701 sci synchronous hd6303 sci synchronous national semiconductor cop400 family microwire ? cop800 family microwire/plus ? ns8050u microwire/plus hpc16000 family microwire/plus texas instruments tms7002 serial port tms7042 serial port tms70c02 serial port tms70c42 serial port tms32011* serial port tms32020* serial port *requires external hardware **contact ltc marketing for interface information for processors not on this list ? microwire and mlcrowire/plus are trademarks of national semiconductor corp. serial port microprocessors most synchronous serial formats contain a shift clock (sclk) and two data lines, one for transmitting and one for receiving. in most cases data bits are transmitted on the falling edge of the clock (sclk) and captured on the rising edge. however, serial port formats vary among mpu manufacturers as to the smallest number of bits that can be sent in one group (e.g., 4-bit, 8-bit or 16-bit transfers). they also vary as to the order in which the bits are transmitted (lsb or msb first). the following examples show how the ltc1090 accommodates these differences. national microwire (cop420) the cop420 transfers data msb first and in 4-bit incre- ments (nibbles). this is easily accommodated by setting the ltc1090 to msb first format and 12-bit word length. the data output word is then received by the cop420 in three 4-bit blocks with the final two unused bits filled with zeroes by the ltc1090. hardware and software interface to national semiconductor cop420 processor applicatio s i for atio wu uu mnemonic description lei enable slo sc set carry flag ogi g0 is set to (cs goes low) ldd load first 4 bits of d in to acc xas swap acc with sio reg. starts sk clk ldd load 2nd 4 bits of d in to acc nop timing xas swap first 4 bits from a/d with acc. sk continues. xis put first 4 bits in ram (location a) nop timing xas swap 2nd 4 bits from a/d with acc. sk continues. xis put 2nd 4 bits in ram (location a + 1) rc clear carry nop timing xas swap 3rd 4 bits from a/d with acc. sk off xis put 3rd 4 bits in ram (location a + 2) ogi g0 is set to 1 (cs goes high) lei disable slo ltc1090 analog inputs d out d out from ltc1090 stored in cop420 ram d in sclk go sk so si cop420 cs b9 location a location a + 1 first 4 bits second 4 bits third 4 bits lsb msb* b8 b7 b6 b5 b4 b3 b2 location a + 2 b1 b0 b0 b0 ltc1090 ?ai11 *b9 is msb in unipolar or sign bit in bipolar
16 lt c1090 1090fc motorola spi (mc68hc05c4) the mc68hc05c4 transfers data msb first and in 8-bit increments. programming the ltc1090 for msb first format and 16-bit word length allows the 10-bit data output to be received by the mpu as two 8-bit bytes with the final 6 unused bits filled with zeroes by the ltc1090. hardware and software interface to motorola mc68hc05c4 processor hitachi synchronous sci (hd63705) the hd63705 transfers serial data in 8-bit increments, lsb first. to accommodate this, the ltc1090 is programmed for 16-bit word length and lsb first format. the 10-bit output data is received by the processor as two 8-bit bytes, lsb first. the ltc1090 fills the final 6 unused bits (after the msb) with zeroes in unipolar mode and with the sign bit in bipolar mode. hardware and software interface to hitachi hd63705 processor applicatio s i for atio wu uu mnemonic description bclr n c0 is cleared (cs goes low) lda load d in for ltc1090 into acc sta load d in from acc to spi data reg. start sck nop 8 nops for timing lda load contents of spi status reg. into acc lda load ltc1090 d out from spi data reg. into acc (byte 1) sta load ltc1090 d out into ram (location a) sta start next spl cycle nop 6 nops for timing bset n c0 is set (cs goes high) ld a load contents of spi status reg. into acc lda load ltc1090 d out from spi data reg. into acc (byte 2) sta load ltc1090 d out into ram (location a + 1) ltc1090 analog inputs d out d out from ltc1090 stored in mc68hco5c4 ram d in sclk co sck mosi miso mc68hco5c4 cs b9 location a location a + 1 byte 1 byte 2 *b9 is msb in unipolar or sign bit in bipolar msb* lsb b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 ltc1090 ?ai12 mnemonic description lda load d in word for ltc1090 into acc from ram bclr n c0 cleared (cs goes low) sta load d in word for ltc1090 into sci data reg. from acc and start clocking data (lsb first) nop 6 nops for timing lda load contents of sci data reg. into acc (byte 1) start next sci cycle sta load ltc1090 d out word into ram (location a) nop timing bset n c0 set (cs goes high) lda load contents of sci data reg. into acc (byte 2) sta load ltc1090 d out word into ram (location a + 1) ltc1090 analog inputs d out d out from ltc1090 stored in hd63705 ram d in sclk c0 ck t x r x hd63705 cs b7 location a location a + 1 bipolar sign byte 1 byte 2 lsb b6 b5 b4 b3 b2 b1 b0 b9 b9 b9 b9 b9 b9 b9 b8 ltc1090 ?ai13 b7 location a location a + 1 unipolar byte 1 byte 2 lsb msb b6 b5 b4 b3 b2 b1 b0 000000 b9 b8
17 lt c1090 1090fc parallel port microprocessors when interfacing the ltc1090 to an mpu which has a parallel port, the serial signals are created on the port with software. three mpu port lines are programmed to create the cs, sclk and d in signals for the ltc1090. a fourth port line reads the d out line. an example is made of the intel 8051/8052/80c252 family. intel 8051 to interface to the 8051, the ltc1090 is programmed for msb first format and 10-bit word length. the 8051 gener- ates cs, sclk and d in on three port lines and reads d out on the fourth. hardware and software interface to intel 8051 processor 8051 code mnemonic description mov pi,#02h initialize port 1 (bit 1 is made an input) clr p1.3 sclk goes low setb p1.4 cs goes high continue: mov a,#0dh d in word for the ltc1090 is placed in acc. clr p1.4 cs goes low mov r4,#08 load counter nop delay for deglitcher loop: mov c, p1.1 read data bit into carry rlc a rotate data bit into acc mov p1.2, c output d in bit to ltc1090 setb p1.3 sclk goes high clr p1.3 sclk goes low djnz r4, loop next bit mov r2, a store msbs in r2 mov c, p1.1 read data bit into carry clr a ciear acc rlc a rotate data bit into acc setb p1.3 sclk goes high clr p1.3 sclk goes low mov c, p1.1 read data bit into carry rrc a rotate right into acc rrc a rotate right into acc mov r3, a store lsbs in r3 setb p1.3 sclk goes high clr p1.3 sclk goes low setb p1.4 cs goes high mov r5,#07h load counter delay: djnz r5, delay delay for ltc1090 to perform conversion ajmp continue repeat program applicatio s i for atio wu uu figure 5. several ltc1090? sharing one 3-wire serial interface ltc1090 analog inputs d out d out from ltc1090 stored in 8051 ram d in sclk aclk cs p1.1 p1.2 p1.3 ale p1.4 8051 b9 r2 r3 *b9 is msb in unipolar or sign bit in bipolar msb* lsb b8 b7 b6 b5 b4 b3 b2 b1 b0 000000 ltc1090 ?ai14 ltc1090 3 3 210 cs 8 channels output port serial data 3-wire serial interface to other peripherals or ltc1090s mpu ltc1090 3 cs 8 channels ltc1090 3 cs 8 channels
18 lt c1090 1090fc 6. sharing the serial interface the ltc1090 can share the same 3-wire serial interface with other peripheral components or other ltc1090s (see figure 5). in this case, the cs signals decide which ltc1090 is being addressed by the mpu. analog considerations 1. grounding the ltc1090 should be used with an analog ground plane and single point grounding techniques. pin 11 (agnd) should be tied directly to this ground plane. pin 10 (dgnd) can also be tied directly to this ground plane because minimal digital noise is generated within the chip itself. pin 20 (v cc ) should be bypassed to the ground plane with a 4.7 f tantalum with leads as short as possible. pin 12 (v ) should be bypassed with a 0.1 f ceramic disk. for single supply applications, v can be tied to the ground plane. it is also recommended that pin 13 (ref ) and pin 9 (com) be tied directly to the ground plane. all analog inputs should be referenced directly to the single point ground. digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. figure 6 shows an example of an ideal ground plane design for a two sided board. of course this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. 2. bypassing for good performance, v cc must be free of noise and ripple. any changes in the v cc voltage with respect to analog ground during a conversion cycle can induce errors or noise in the output code. v cc noise and ripple can be kept below 1mv by bypassing the v cc pin directly to the analog ground plane with a 4.7 f tantalum with leads as short as possible. figures 7 and 8 show the effects of good and poor v cc bypassing. applicatio s i for atio wu uu figure 7. poor v cc bypassing. noise and ripple can cause a/d errors figure 6. example ground plane for the ltc1090 horizontal: 10 s/div vertical: 0.5mv/div figure 8. good v cc bypassing keeps noise and ripple on v cc below 1mv horizontal: 10 s/div vertical: 0.5mv/div 20 v cc v 10 11 ltc1090 ?ai15 analog ground plane 0.1 f ceramic disk 4.7 f tantalum 1
19 lt c1090 1090fc 3. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the ltc1090 have capacitive switching input current spikes. these current spikes settle quickly and do not cause a problem. however, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. source resistance the analog inputs of the ltc1090 look like a 60pf capaci- tor (c in ) in series with a 500 ? resistor (r on ) as shown in figure 9. c in gets switched between the selected ??and ?inputs once during each conversion cycle. large external source resistors and capacitances will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle within the allowed time. applicatio s i for atio wu uu figure 9. analog input equivalent circuit ??input settling this input capacitor is switched onto the ??input during the sample phase (t smpl , see figure 10). the sample phase starts at the 4th sclk cycle and lasts until the falling edge of the last sclk (the 8th, 10th, 12th or 16th sclk cycle depending on the selected word length). the voltage on the ??input must settle completely within this sample time. minimizing r source + and c1 will improve the input settling time. if large ??input source resistance must be used, the sample time can be increased by using a slower sclk frequency or selecting a longer word length. with the minimum possible sample time of 4 s, r source + < 2k and c1 < 20pf will provide adequate settling. ?input settling at the end of the sample phase the input capacitor switches to the ?input and the conversion starts (see figure 10). during the conversion, the ??input voltage is effectively ?eld?by the sample and hold and will not affect the conversion result. however, it is critical that the ?input voltage be free of noise and settle completely during the first four aclk cycles of the conversion time. minimizing r source and c2 will improve settling time. if large ?input source resistance must be used, the time allowed for settling can be extended by using a slower aclk frequency. at the maximum aclk rate of 2mhz, r source < 1k ? and c2 < 20pf will provide adequate settling. figure 10. ??and ?input settling windows ltc1090 ?ai17 cs sclk aclk t smpl hold 1 1st bit test last sclk (8th, 10th, 12th or 16th depending on work length) ???input must settle during this time ?+ ?input must settle during this time 234 123 4 sample mux address shifted in ???input ?+ ?input ltc1090 ?ai16 r source + r source v in v in + 4th sclk last sclk r on = 500 ? c in = 60pf l tc1090 ? input c1 c2 ? + input
20 lt c1090 1090fc input op amps when driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see figure 10). again, the ??and ?input sampling times can be extended as described above to accommo- date slower op amps. most op amps including the lt1006 and lt1013 single supply op amps can be made to settle well even with the minimum settling windows of 4 s (? input) and 2 s (?input) which occur at the maximum clock rates (aclk = 2mhz and sclk = 1mhz). figures 11 and 12 show examples of adequate and poor op amp settling. rc input filtering it is possible to filter the inputs with an rc network as shown in figure 13. for large values of c f (e.g., 1 f), the capacitive input switching currents are averaged into a net dc current. therefore, a filter should be chosen with a small resistor and large capacitor to prevent dc drops across the resistor. the magnitude of the dc current is approximately l dc = 60pf x v in /t cyc and is roughly propor- tional to v in . when running at the minimum cycle time of 33 s, the input current equals 9 a at v in = 5v. in this case, a filter resistor of 50 ? will cause 0.1lsb of full-scale error. if a larger filter resistor must be used, errors can be eliminated by increasing the cycle time as shown in the typical curve of maximum filter resistor vs cycle time. figure 11. adequate settling of op amp driving analog input figure 12. poor op amp settling can cause a/d errors figure 13. rc input filtering applicatio s i for atio wu uu horizontal: 1 s/div vertical: 5mv/div horizontal: 20 s/div vertical: 5mv/div ltc1090 ?ai18 v in r filter i dc c filter l tc1090 ?+ ? input leakage current input leakage currents can also create errors if the source resistance gets too large. for instance, the maximum input leakage specification of 1 a (at 125 c) flowing through a source resistance of 1k ? will cause a voltage drop of 1mv or 0.2lsb. this error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve of input channel leakage current vs temperature). noise coupling into inputs high source resistance input signals (>500 ? ) are more sensitive to coupling from external sources. it is preferable to use channels near the center of the package (i.e., ch2 to ch7) for signals which have the highest output resistance because they are essentially shielded by the pins on the package ends (dgnd and ch0). grounding any unused inputs (especially the end pin, ch0) will also reduce outside coupling into high source resistances. 4. sample-and-hold single ended inputs the ltc1090 provides a built-in sample and hold (s&h) function for all signals acquired in the single ended mode (com pin grounded). this sample and hold allows the ltc1090 to convert rapidly varying signals (see typical curve of s&h acquisition time vs source resistance). the input voltage is sampled during the t smpl time as shown in figure 10. the sampling interval begins after the fourth
21 lt c1090 1090fc mux address bit is shifted in and continues during the remainder of the data transfer. on the falling edge of the final sclk, the s&h goes into hold mode and the conver- sion begins. the voltage will be held on either the 8th, 10th, 12th or 16th falling edge of the sclk depending on the word length selected. differential inputs with differential inputs or when the com pin is not tied to ground, the a/d no longer converts just a single voltage but rather the difference between two voltages. in these cases, the voltage on the selected ?? input is still sampled and held and therefore may be rapidly time varying just as in single ended mode. however, the voltage on the se- lected ?input must remain constant and be free of noise and ripple throughout the conversion time. otherwise, the differencing operation may not be performed accurately. the conversion time is 44 aclk cycles. therefore, a change in the ?input voltage during this interval can ?input this error would be: v error (max) = v peak x 2 x x f(? x 44/f aclk where f(? is the frequency of the ?input voltage, v peak is its peak amplitude and f aclk is the frequency of the aclk. in most cases v error will not be significant. for a 60hz signal on the ?input to generate a 1/4lsb error (1.25mv) with the converter running at aclk = 2mhz, its peak value would have to be 150mv. 5. reference inputs the voltage between the reference inputs of the ltc1090 defines the voltage span of the a/d converter. the refer- ence inputs look primarily like a 10k ? resistor but will have transient capacitive switching currents due to the switched capacitor conversion technique (see figure 14). during each bit test of the conversion (every 4 aclk cycles), a capacitive current spike will be generated on the reference pins by the a/d. these current spikes settle quickly and do not cause a problem. however, if slow settling circuitry is used to drive the reference inputs, care must be taken to insure that transients caused by these current spikes settle completely during each bit test of the conversion. when driving the reference inputs, three things should be kept in mind: 1. the source resistance (r out ) driving the reference inputs should be low (less than 1 ? ) to prevent dc drops caused by the 1ma maximum reference current (i ref ). 2. transients on the reference inputs caused by the capacitive switching currents must settle completely during each bit test (each 4 aclk cycles). figures 15 and 16 show examples of both adequate and poor settling. using a slower aclk will allow more time for the reference to settle. however, even at the maximum aclk rate of 2mhz most references and op amps can be made to settle within the 2 s bit time. 3. it is recommended that the ref input be tied directly to the analog ground plane. if ref is biased at a voltage other than ground, the voltage must not change during a conversion cycle. this voltage must also be free of noise and ripple with respect to analog ground. figure 14. reference input equivalent circuit figure 15. adequate reference settling horizontal: 1 s/div vertical: 0.5mv/div applicatio s i for atio wu uu ltc1090 ?ai19 r out ref + ref v ref every 4 aclk cycles 10k typ r on 5pf ?30pf l tc1090 14 13
22 lt c1090 1090fc 6. reduced reference operation the effective resolution of the ltc1090 can be increased by reducing the input span of the converter. the ltc1090 exhibits good linearity and gain over a wide range of reference voltages (see typical curves of linearity and gain error vs reference voltage). however, care must be taken when operating at low values of v ref because of the reduced lsb step size and the resulting higher accuracy requirement placed on the converter. the following factors must be considered when operating at low v ref values: 1. conversion speed (aclk frequency) 2. offset 3. noise conversion speed with reduced v ref with reduced reference voltages, the lsb step size is reduced and the ltc1090 internal comparator overdrive is reduced. with less overdrive, more time is required to perform a conversion. therefore, the maximum aclk frequency should be reduced when low values of v ref are used. this is shown in the typical curve of maximum conversion clock rate vs reference voltage. offset with reduced v ref the offset of the ltc1090 has a larger effect on the output code when the a/d is operated with reduced reference voltage. the offset (which is typically a fixed voltage) becomes a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of unadjusted offset error vs reference voltage shows how offset in lsbs is related to reference voltage for a typical value of v os . for example, a v os of 0.5mv which is 0.1lsb with a 5v reference becomes 0.5lsb with a 1v reference and 2.5lsbs with a 0.2v reference. if this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the ?input to the ltc1090. noise with reduced v ref the total input referred noise of the ltc1090 can be reduced to approximately 200 v peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. this noise is insignificant with a 5v reference but will become a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of noise error vs reference voltage shows the lsb contribution of this 200 v of noise. for operation with a 5v reference, the 200 v noise is only 0.04lsb peak-to-peak. in this case, the ltc1090 noise will contribute virtually no uncertainty to the output code. however, for reduced references, the noise may become a significant fraction of an lsb and cause undesirable jitter in the output code. for example, with a 1v reference, this same 200 v noise is 0.2lsb peak-to-peak. this will reduce the range of input voltages over which a stable output code can be achieved by 0.2lsb. if the reference is further reduced to 200mv, the 200 v noise becomes equal to one lsb and a stable code may be difficult to achieve. in this case averaging readings may be necessary. this noise data was taken in a very clean setup. any setup induced noise (noise or ripple on v cc , v ref , v in or v ) will add to the internal noise. the lower the reference voltage to be used, the more critical it becomes to have a clean, noise-free setup. figure 16. poor reference settling can cause a/d errors horizontal: 1 s/div vertical: 0.5mv/div applicatio s i for atio wu uu
23 lt c1090 1090fc sneak-a-bit tm the ltc1090? unique ability to software select the polar- ity of the differential inputs and the output word length is used to achieve one more bit of resolution. using the circuit below with two conversions and some software, a 2? complement 10-bit + sign word is returned to memory inside the mpu. the mc68hc05c4 was chosen as an example; however, any processor could be used. two 10-bit unipolar conversions are performed: the first over a 0 to 5v span and the second over a 0 to 5v span (by reversing the polarity of the inputs). the sign of the input is determined by which of the two spans contained it. then the resulting number (ranging from 1023 to 1023 decimal) is converted to 2? complement notation and stored in ram. a ?uick look?circuit for the ltc1090 scope trace of ltc1090 ?uick look?circuit showing a/d output of 0101010101 (155 hex ) a ?uick look?circuit for the ltc1090 users can get a quick look at the function and timing of the ltc1090 by using the following simple circuit. ref + and d in are tied to v cc selecting a 5v input span, ch7 as a single ended input, unipolar mode, msb first format and 16-bit word length. aclk and sclk are tied together and driven by an external clock. cs is driven at 1/64 the clock rate by the cd4520 and d out outputs the data. all other pins are tied to a ground plane. the output data from the d out pin can be viewed on an oscilloscope which is set up to trigger on the falling edge of cs. u typical applicatio sneak-a-bit circuit sneak-a-bit is a trademark of linear technology corp. ltc1090 ?ta04 10 f 9v v in ?v to 5v other channels or sneak-a-bit inputs ch0 ch1 ch2 ch3 ch4 ch5 sck mosi miso co ch6 ch7 0.1 f ?v com dgnd v cc aclk sclk d in d out ref + ref v agnd l tc1090 mc68hc05c4 2mhz clock cs lt1 021-5 cs d out deglitcher time msb (b9) lsb (b0) fills zero ltc1090 ?ta03 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc aclk sclk d in d out ref + ref v agnd l tc1090 cs clk en f/64 5v 4.7 f f q1 q2 q3 q4 reset 0.1 reset q4 q3 v ss v in v dd q1 en clk l tc1090 q2 clock in 1mhz max to oscilloscope
24 lt c1090 1090fc u typical applicatio sneak-a-bit code for the ltc1090 using the mc68hc05c4 mnemonic description read/+: lda #$3f load d in word for ltc1090 into acc jsr transfer read ltc1090 routine lda $60 load msbs from ltc1090 into acc sta $71 store msbs in $71 lda $61 load lsbs from ltc1090 into acc sta $72 store lsbs in $72 rts return read+/? lda #$7f load d in word for ltc1090 into acc jsr transfer read ltc1090 routine lda $60 load msbs from ltc1090 into acc sta $73 store msbs in $73 lda $61 load lsbs from ltc1090 into acc sta $74 store lsbs in $74 rts return transfer: bclr 0, $02 cs goes low sta $0c load d in into spi. start transfer loop 1: tst $0b test status of splf bpl loop 1 loop to previous instruction if not done lda $0c load contents of spi data reg into acc sta $0c start next cycle sta $60 store msbs in $60 loop 2: tst $0b test status of splf bpl loop 2 loop to previous instruction if not done bset 0, $02 cs goes high lda $0c load contents of spi data reg into acc sta $61 store lsbs in $61 rts return chk sign: lda $73 load msbs of +/ read into acc ora $74 or acc (msbs) with lsbs of +/ read beq minus if result is 0 goto minus clc clear carry ror $73 rotate right $73 through carry ror $74 rotate right $74 through carry lda $73 load msbs of +/ read into acc sta $77 store msbs in ram location $77 lda $74 load lsbs of +/ read into acc sta $87 store lsbs in ram location $87 bra end goto end of routine minus: clc clear carry ror $71 shift msbs of /+ read right ror $72 shift lsbs of /+ read right com $71 1? complement of msbs com $72 1? complement of lsbs lda $72 load lsbs into acc add #$01 add 1 to lsbs sta $72 store acc in $72 clra clear acc adc $71 add with carry to msbs. result in acc sta $71 store acc in $71 sta $77 store msbs in ram location $77 lda $72 load lsbs in acc sta $87 store lsbs in ram location $87 end: rts return mnemonic description lda #$50 configuration data for spcr sta $0a load configuration data into $0a lda #$ff configuration data for port c ddr sta $06 load configuration data into port c ddr bset 0, $02 make sure cs is high jsr read /+ dummy read configures ltc1090 for next read jsr read+/ read ch6 with respect to ch7 jsr read /+ read ch7 with respect to ch6 jsr chk sign determines which reading has valid data, converts to 2? complement and stores in ram sneak-a-bit sneak-a-bit code for the ltc1090 using the mc68hc05c4 ltc1090 ?ta05 1st conversion 1st conversion 1024 steps 5v ?v 5v ?v 0v 0v 0v 2nd conversion 1024 steps software 2047 steps ( + ) ch6 ( ?) ch7 v in v in 2nd conversion sneak-a-bit code ( ?) ch6 ( + ) ch7 v in d out from ltc1090 in mc68hc05c4 ram d in words for ltc1090 location $77 sign lsb b2 b1 b0 b10 b9 b8 filled with 0s b7 b6 b5 b4 b3 location $87 (odd/sign) mux addr. word length uni msbf d in 1 001 1 1111 d in 2 011 1 1111 d in 3 001 1 1111
25 lt c1090 1090fc u package descriptio j20 1298 3 7 56 10 9 1 4 2 8 11 20 16 15 17 14 13 12 19 18 0.005 (0.127) min 0.025 (0.635) rad typ 0.220 ?0.310 (5.588 ?7.874) 1.060 (26.924) max 0 ?15 0.008 ?0.018 (0.203 ?0.457) 0.015 ?0.060 (0.381 ?1.524) 0.125 (3.175) min 0.014 ?0.026 (0.356 ?0.660) 0.045 ?0.065 (1.143 ?1.651) 0.100 (2.54) bsc 0.200 (5.080) max 0.300 bsc (0.762 bsc) 0.045 ?0.068 (1.143 ?1.727) full lead option 0.023 ?0.045 (0.584 ?1.143) half lead option corner leads option (4 plcs) note: lead dimensions apply to solder dip/plate or tin plate leads j package 20-lead cerdip (narrow .300 inch, hermetic) (reference ltc dwg # 05-08-1110) obsolete package
26 lt c1090 1090fc n package 20-lead pdip (narrow .300 inch) (reference ltc dwg # 05-08-1510) n20 1098 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.005 (0.127) min 0.100 (2.54) bsc 0.255 0.015* (6.477 0.381) 1.040* (26.416) max 12 3 4 5 6 7 8 910 19 11 12 13 14 16 15 17 18 20 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 + 0.035 0.015 + 0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) u package descriptio
27 lt c1090 1090fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio s20 (wide) 1098 note 1 0.496 ?0.512* (12.598 ?13.005) 20 19 18 17 16 15 14 13 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 11 12 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) bsc 0.014 ?0.019 (0.356 ?0.482) typ 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** sw package 20-lead plastic small outline (wide .300 inch) (reference ltc dwg # 05-08-1620)
28 lt c1090 1090fc linear technology corporation 1 630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com lw/tp 0902 1k rev c ?printed in usa ? l inear technology corporation 1990 part number description comments ltc1290 8-channel configurable, 5v, 12-bit adc pin-compatible with ltc1090 ltc1391 serial-controlled 8-to-1 analog multiplexer low r on , low power, 16-pin so and ssop package ltc1594l/ltc1598l 4-/8-channel, 3v micropower 12-bit adc low power, small size ltc1850/ltc1851 10-bit/12-bit, 8-channel, 1.25msps adcs 5v, p rogrammable mux and sequencer ltc1852/ltc1853 10-bit/12-bit, 8-channel, 400ksps adcs 3v or 5v, programmable mux and sequencer ltc2404/ltc2408 24-bit, 4-/8-channel, no latency ? tm adc 4ppm inl, 10ppm total unadjusted error, 200 a ltc2424/ltc2428 20-bit, 4-/8-channel, no latency ? adc 1.2ppm noise, 8ppm inl, pin compatible with ltc2404/ltc2408 related parts no latency ? is a trademark of linear technology corporation.

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