march 2008 revision: eb21_01.6 machxo standard evaluation board - revisions 001 & 002 user? guide
2 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide introduction the machxo standard evaluation board provides a convenient platform to evaluate electrical characteristics of the machxo device, and to evaluate, test and de-bug custom logic designs. the board features a machxo device in a 256-ball fpbga package. the machxo i/os are connected to a rich variety of interfaces, including an 8-bit input switch, leds, pcb test points, 0.10 general purpose headers and optional high-speed sma connectors. the board includes selectable power for mixed core i/o voltage operation. a 33mhz oscillator, as well as an ispclock pll synthesis device are also included on the board. features machxo in 256-ball ?e pitch ball grid array package (machxo640 or machxo2280) single printed circuit board solution eight leds for visual feedback 8-bit input switch general purpose push-button 1149.1 jtag programming/boundary-scan interface built-in power supply operating with an dc input between 5v and 20v selectable core voltage for the machxo selectable voltages for a portion of the i/o banks built-in adjustable oscillator for reference clocking source lattice ispclock5610 multiple output pll sma connector landing pads (sma connectors not populated) to machxo clock input/general purpose i/o pins rj-45 connector (not populated) lcd/gpio footprint 100mil center-center test point grid impedance controlled mictor (not populated) general description the heart of the board is the machxo programmable logic device in a 256-ball fpbga package. the board is designed to cover a broad range of core and i/o voltage requirements. the machxo ? grade devices require a core voltage supply between 1.5v to 3.3v and an auxiliary 3.3v supply. the ? grade devices require a core volt- age supply at 1.2v and an auxiliary i/o supply at 3.3v. the machxo standard evaluation board provides three supply voltages, all sourced from a 5v to 20v external source (or sourced individually via the banana jack inputs). the board provides ?ed 1.2v and 3.3v power rails and a single adjustable voltage that ranges from 1.2v to 3.3v. it is possible to use external power supplies to override the ?ed output levels if desired. the voltage supplied to the machxo core is selectable. the core voltage is changed by moving a single current sense resistor. once a correct set of supply voltages has been applied to the machxo, the device can be programmed. the machxo can be programmed and veri?d with a lattice jtag download cable, which should be connected to the 1x10 sip header on the board (1149.1 jtag interface). the ispvm system software controls the programming and veri?ation process. the ispvm system software is available for download from www .latticesemi.com/softw are .
3 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide the evaluation board also includes a lattice ispclock5610. this part is also programmed using the same jtag interface. the ispclock5610 can be used to generate synthesized clock inputs to the machxo device. the evaluation board includes additional components to aid in evaluating the machxo pld. these are described in the following sections in more detail. additional resources additional resources related to this board can be downloaded from the web at www .latticesemi.com/boards . click on the appropriate evaluation board, then see the blue ?esources box on the right of the screen for items such as: updated documentation, downloadable software, sample designs and more. getting started in order to use the machxo standard evaluation board, it must ?st be powered. follow the guidelines in the power supply section below for details. the machxo standard evaluation board is shipped from the factory pre-con?ured with a sample program loaded in both the machxo and ispclock devices. the source code and programming ?es are available for download from the lattice web site at: www .latticesemi.com/boards . the sample programs operate as follows. machxo: setting all of the 8-bit input switches to on causes the associated leds to count in one direction (8-bit binary counter). setting all of the 8-bit input switches to off reverses the direction of the count. if the switches are not all on or all off, the leds for the switches that are on will light up. additionally, other i/os on the machxo device are also toggled using the internal counter outputs. see the source code and preference ?e available on- line for more information. ispclock5610: the ispclock5610 sample program generates a 33mhz clock input to the machxo device. to reprogram the board, you will need the following items: isplever software: hdl design support for the machxo device is included in both isplever 5.0 sp1 and downloadable isplever-starter 5.0 sp1 (or later) software tools ispvm system: this is the lattice programming management tool which is used to download custom isplever designs from your pc to the machxo device via an ispdownload cable. the ispvm system software is avail- able for download from the lattice web site at: www .latticesemi.com/ispvm . ispdownload cable: an ispdownload cable is required to connect your pc to the machxo standard evaluation board. ispdownload cables are available for purchase separately from the lattice on-line store (www .latticesemi.com/store ) or any lattice distributor. for more information see: www .latticesemi.com/products/de vtools/hardw are/ispdo wnload/ machxo standard evaluation board functional description the machxo standard evaluation board is comprised of several primary functional blocks as shown in figure 1. in the descriptions below, locations of components and board features are described relative to a compass symbol placed adjacent to the lattice semiconductor logo. for example, the dip oscillator is on the southwest corner of the board, and the lattice logo is on the northeast corner of the board.
4 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 1. machxo standard evaluation board power supply the machxo standard evaluation board includes two locations to apply power. on the east side of the board are a pair of banana jacks (jp28 and jp29) and a coaxial dc connector (jp30), which receive power from either a bench power supply or a brick style power supply. a dc source between 5.0v and 28.0v must be applied in order to power the board. the coaxial dc connector uses a 2.5mm central pin, with a 6.3mm outer diameter barrel. the output from the dc system is controlled by switch s5. switch s5 is in the southeast corner of the board. this is a small surface mount switch that enables and disables the ltc1775 dc-dc conversion chip. the output voltages from the power supply are enabled when the switch is in the ?n position. the 5.0v to 28.0v dc input voltage is converted by dc-dc converters and switching power supplies to provide 3.3v, 1.2v, and an adjustable dc source on the board. the output from these supplies travels through surface mounted fuse holders. fuses are supplied and prevent over-current conditions from damaging the components on the board (vendor: littlefuse, make: nano smf very fast acting, 1.5a or 3a). due west of the fuse blocks are more banana plug connectors. these connectors provide an alternate means for applying dc voltage levels to the board. to apply voltages not supplied by the on-board power section, ?st remove the appropriate fuse from the fuse holder . then connect an alternate dc supply to the banana plug connector associated with that fuse. table 1. power supply fuses fuse number supply rail enabled/disabled banana connector input f1 v adj jp25 f2 1.2v jp26 f3 3.3v jp27 rj-45 connector area sma connector area ispclock5610 dip oscillator 8-bit input switch push-button switches prototype areas lcd display area dc power input jack power inputs north south east west prototype area jtag pro g rammin g interface
5 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide adjacent to jp25-27 are current sense resistors. these permit the measurement of the current ?wing from each of the power supplies. a single resistor can be moved to permit 1.2v, 3.3v, or v adj to supply v core to the machxo. table 2. machxo core voltage selection the remaining current sense resistors permit the measurement of the v ccio current draw. table 3. machxo i/o voltage rails four v ccio banks are available on the machxo standard evaluation board. three of the four i/o banks can be selected. v ccio2 is always powered at 3.3v. this forces the jtag interface to run at 3.3v. v ccio0 , v ccio1 , and v ccio3 can be altered using jumpers. table 4. machxo i/o voltage selection figure 2. machxo standard evaluation board programmability the programming interface for the machxo (and ispclock5610) is located in the northwest corner of the board. the 1x10 header, jp7, is the connection point for the jtag download cable. jumpers jp6 and jp8 determine how the tdi/tdo chain and tms pins behave. important note: the board must be un-powered when connecting, disconnecting, or reconnecting the ispdown- load cable. always connect the ispdownload cable's gnd pin (black wire), before connecting any other jtag pins. failure to follow these procedures can in result in damage to the machxo device and render the board inop- erable. resistor voltage supplied to the machxo core r141 v adj r142 1.2v r144 3.3v resistor i/o bank voltage r143 1.2v r145 3.3v r148 v adj jumper block v ccio controlled jp20 1-2: v ccio1 = 3.3v 3-4: v ccio1 = v adj 5-6: v ccio1 = 1.2v jp21 1-2: v ccio0 = 3.3v 3-4: v ccio0 = v adj 5-6: v ccio0 = 1.2v jp22 1-2: v ccio3 = 3.3v 3-4: v ccio3 = v adj 5-6: v ccio3 = 1.2v pin 1 pin 6
6 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide the default con?uration for jumper jp6 is to con?ure the tdi from jp7 to be routed to the machxo ?st. the tdo from the machxo is routed to the ispclock device. tdo from the ispclock is connected to the jtag header jp7. however figure 3 shows the board can be con?ured to only have the machxo accessible by the jtag header. it can also be con?ured to only have the ispclock accessible by the jtag header. jumper jp8 controls the tms routing to the machxo and the ispclock. the default con?uration connects tms to both the machxo and the ispclock. when the machxo is the only device in the jtag chain, the ispclock tms is pulled high, causing it to always go into test-logic-reset mode. the machxo has its tms pin pulled high when the ispclock is the only device in the jtag chain. figure 3. programming interface push buttons and status leds there are three push-buttons and three leds in the south portion of the machxo standard evaluation board. switch s2, the westernmost, asserts the global set/reset input on the machxo. when the button is pressed, led d9 (red), illuminates. this gives clear visual evidence the gsr input has toggled. in order for the gsr to operate, it is necessary to instantiate the gsr macro in the vhdl/verilog hdl source. immediately adjacent to the machxo reset switch is the ispclock reset switch (s3). pressing this button asserts reset to the ispclock chip. finally, there is a general use push-button (s4). s4 is routed to t11 on the machxo device. it is normally pulled high, and when pressed is asserted to ground. when pressed, led d10 (yellow) illuminates. adjacent, westward, to s2 is diode d11 (green). this is a led tied to a general purpose i/o on the machxo. this led signals that the machxo is done being programmed. however, it can be used to signal any status desired. evaluation bitstreams will tie output pin t6 to drive low, turning d11 on. global output enable the machxo device features a global output enable control. the goe is routed to jp18, and the factory default setting on jp18 is to enable the machxo outputs. the jumper on jp18 can be moved from the default setting to disable (tri-state) all of the machxo i/os. table 5. global output enable machxo and support interfaces the machxo standard evaluation board includes basic support features for evaluating the performance and func- tionality of the machxo device. this includes a prototyping area permitting arbitrary logic functions to be placed on jumper block jp1 8 output enable state 1-2 outputs disabled (tri-state) 2-3 outputs enabled jtag pin 1 tdi j u mpers machxo and ispclock machxo only ispclock only tdi ro u te tms ro u te tms j u mpers
7 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide board. there are also locations to insert connectors and resistors. these connections are useful for performing i/o characterization. the silk screen markings on the evaluation board are designed to make it easy to locate resources on the board and related connections to the machxo. parts are numbered in a consistent fashion. each part starts at reference designator ? in the northwest corner of the board (i.e. r1, c1, u1, l1?. the component number increases by one in a columnar fashion (i.e. south- ward). when the south edge of the board is reached, the count resumes slightly east, and at the north side of the board. thus the highest numbered components will always be in the southeast corner of the board. this same numbering sequence is applied to the reverse side of the evaluation board. the alphanumeric pin position of the machxo 256-ball fpbga is indicated adjacent to most of the switch inputs, led outputs, sma connectors, and test points on the board. for example, the designator (f3) is located next to the sma connector jp2. thus machxo pin f3 is connected to the center post of jp2. a solid white rectangle area near the sma connectors denotes the positive side of a matched pair. the negative side of the matched pair has a white outline rectangle area. prototype grids the board includes ?e 100-mil center-center prototype grid areas consisting of plated through holes with various connections. it is important to note the board conventions used to identify the through hole types: any through hole with a square-shaped plated area is not connected to any device on the board, and provided for your convenience. any round through-hole outlined with a thin white silkscreen rectangle is connected to ground. all other round through-holes are connected to the machxo pin as indicated by the silkscreen. note: some prototype grid test points may be connected to ?o-connect (nc) pin locations on the machxo device. consult the machxo device datasheet for further details regarding the machxo pinout. prototype grid 1 and 2: grid 1 is located in the northwest portion of the board. grid 2 is due south of the machxo device. both areas have an alphanumeric grid located in the silkscreen indicating which plated through hole is attached to which machxo pin. both grids are intermixed with through holes attached to the ground plane. these ground holes are marked with a white silkscreened rectangle. both grids are also intermixed with unconnected locations. these are indicated with a square-shaped plated area. for example, starting in the upper-left of grid 1; location a2 and a3 are unconnected, location a4 is connected to the machxo i/o pin a4, etc. both grids also have a series of pull-up/pull-down/inline resistors connected to the through holes. figure 4 shows how these resistors may be arrayed around the prototype area. (m12)
8 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 4. prototype grid 1 and 2 resistor pad con?uration the resistor pads are 0603 surface mount form factor. the 0603 resistor in the center has a short-circuit trace between the resistor pads. this permits the signal to be driven to the prototype area without the addition of a smt zero ohm resistor. if a series resistor with a non-zero value is needed, this short-circuit trace can be removed. the pull-up resistors within this grid can be con?ured to be pulled to one of the three available voltage rails on the board. table 6 shows how the voltage rails are assigned. refer to the schematic to determine which resistor pads connect to which machxo i/o. the schematic also indicates which jumper block controls the pull-up voltage on each resistor. the schematic is included in appendix a. table 6. pull-up voltage selection prototype grid 3: just west (left) of the machxo is a small array of nine test points. the machxo i/o pin connec- tions are indicated in the silkscreen marking. for example, the top-left location connects to machxo pin f5, etc. these test points are directly connected to the machxo without any series resistors, and do not have any pull- up/pull-down resistors attached. prototype grid 4: this grid is located in the south-east part of the board. this grid consists primarily of uncon- nected, square-plated through holes. the south edge of this grid has a row of through holes connected to ground. the north edge has a small quantity of through holes connected to the machxo. figure 5 indicates how these test points are connected to the machxo 256 fpbga. the lvds paired test points connect to a set of 0603 form factor resistors. these resistors permit series and parallel style terminations to be applied to the machxo i/o. note that some of these i/os may be no-connects on the machxo device depending on which machxo device is populated on the board. review the schematic and machxo family data sheet to determine which are available for use. jumper block pull-up voltage jp10 1-2: 1.2v 3-4: v adj 5-6: 3.3v jp19 1-2: 1.2v 3-4: v adj 5-6: 3.3v p u ll- u p from machxo p u ll-do w n short circ u it
9 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 5. prototype grid 4 prototype grid 5 : the last of the prototype grid is designed for use with an lcd display. u3 can be populated by a lumex lcd-s501c39tr ?e-element, seven-segement lcd display. when this display is populated, it is mounted on the rows between u3 and jp23/jp24. jp23 and jp24 can then be populated with general-purpose headers. jumpers can then be used to control connections between the machxo device pins and the lcd. when this lcd is not populated (default condition), the outer columns of jp23 and jp24 can be used as general- purpose i/o test points. l v ds paired direct to machxo short-circ u it
10 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide led displays on the south edge of the board is a set of eight green 0603 form factor leds. these leds are connected to i/o pins dedicated to driving the leds. table 7 shows which machxo i/o controls each led. the leds illuminate when the corresponding i/o is driven to v ol . table 7. led pin assignments switches the evaluation board includes an eight-bit input toggle switch at the south edge of the board. the machxo i/o location for each bit in the switch is indicated on the pcb silkscreen. when in the up position, the switch is pulled to 3.3v via a 10k resistor. when in the down position, the switch is tied to ground. table 8. switch assignments oscillator and clock inputs the machxo standard evaluation board provides the ability to supply selectable reference frequencies to the machxo device. the board provides a unique clock source distribution method. a lattice ispclock5610 is included on the board to provide a number of different clock frequencies to the machxo device. the ispclock5610 receives a reference clock from one of two sources on the board. the primary clock source for the ispclock5610 is the on-board dip oscillator. in the southwest corner of the board is xu1. this is a socket for installing 300mil wide 3.3v dip oscillators. figure 7 shows how each type of oscillator can be placed in the dip socket. led machxo i/o d0 r11 d1 r12 d2 p11 d3 p12 d4 t13 d5 t12 d6 r13 d7 r14 switch machxo i/o 1 t3 2 r4 3 r5 4 p5 5 p6 6 t4 7 t5 8 r6
11 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 6. oscillator positions note: xu2 pin 9 is routed to one of the two plls included on larger machxo devices. these machxo plls are not available on the machxo640 device. xu2 pin 9 provides input to the pll_t input pin m5. jp2 and jp3 are routed to the second set of pll input pins on the machxo device. on the machxo640, these input pins are general purpose i/o. for larger machxo devices, these same i/o pins are combination general pur- pose i/o and pll inputs. the traces from jp2/jp3 are 50 ohm impedance, and have the same resistor pad struc- ture described in figure 6. jp2/jp3 provide the ability to insert differential clock sources. review the schematic for the exact part reference numbers of the resistors. the second way to provide a clock to the ispclock5610 is to use jp4 and jp5 sma connectors. these sma con- nectors are not installed by default. also, by default the positive input from jp4 is disconnected from the ispclock5610. beneath the ispclock5610 on the reverse side of the board are two resistor sites: r158 and r159. r158 connects xu2 pin 10 to the ispclock5610 positive clock input. r159 connects jp4 to the ispclock positive clock input. by default, r158 has a zero ohm resistor installed and r159 is left empty. this is done to prevent unde- sirable artifacts from appearing on the input clock due to trace stubs. r158 and r159 are placed in a way to reduce the length of any stub traces to an absolute minimum. when supplying a clock from jp4/jp5, r158 should be moved to r159 in order to connect jp4 to the ispclock5610. table 9. ispclock5610 clock source once the clock source to the ispclock device has been de?ed, the ispclock can be programmed to generate clock frequencies for the machxo. the ispclock5610 has ?e outputs from the internal pll (0-4). the ?st four, 0-3, are applied directly to the machxo clock input pins. the ?th output is brought out to tp2 and tp3, adjacent to the isp- clock chip. table 10. clock connections resistor ispclock5610 positive source r158 xu2 pin 10 r159 jp4 ispclock5610 pin machxo pin clk_out0 d7 clk_out1 a9 clk_out2 n9 clk_out3 m9 f u ll-size to ispclock half-size to ispclock f u ll-size to machxo pll half-size to machxo pll osc osc osc osc jp9 pin 1 1-2: oscillator ena b led 2-3: oscillator disa b led
12 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide see the ispclock5610 family data sheet and the lattice pac-designer design software for information about pro- gramming the ispclock. more information and software downloads can be found on the lattice web site at www .lat- ticesemi.com/ispcloc k . ispclock con?uration the ispclock5610 has multiple con?uration pins. the evaluation board includes a number of headers on the board allowing these con?uration pins to be asserted, deasserted, or controlled from the machxo. the headers have a general format as shown in figure 7. figure 7. ispclock con?uration headers jp11 - jp17 con?ure all of the ispclock features. table 11 shows which jumper block controls which ispclock pin. refer to the ispclock5610 family data sheet to understand what function each pin performs. table 11. ispclock5610 clock source the ispclock has the ability to be programmed with four separate pro?es. the pro?es are selected using the ps1:0 input pins. the ispclock is programmed with a unique personality in pro?e 0. none of the remaining pro?es provide additional frequencies. pro?e 0 is con?ured to use the ispclock pll to generate several output frequencies from the base 33mhz input frequency. the outputs are: output 0: 4x input output 1: 2x input output 2: 1x input output 3: 0.5x input output 4: 0.25x input some applications may not require the ispclock to use the pll to generate higher frequency clocks. it is possible to turn the ispclock into a clock buffer chip. this is done by moving the pll bypass jumper from the default loca- tion. the pll will no longer be included in the clock frequency generation. if pro?e 0 is still selected the post pll clock dividers will still be active, causing the output frequencies to drop dramatically. if a 1:1 input to output fre- quency ratio is desired the ps1:0 jumpers can be used to select any pro?e other than pro?e 0. jumper block ispclock control factory default setting jp11 ps0 5-6 jp12 pll bypass 5-6 jp13 oex 5-6 jp14 goe 5-6 jp15 sgate 1-2 jp16 ps1 5-6 jp17 oey 5-6 pin 1 p u ll-do w np u ll- u p machxo
13 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide rj-45 connection the west edge of the board provides a place to insert an rj-45 connector. this connector is not installed at the fac- tory. the traces to the rj-45 connector have the same resistor network scheme as shown in figure 5, described above. the traces are 50 ohm impedance, and on larger machxo devices are connected to true lvds i/o. mictor header the left-side i/os on the machxo which are not used for the rj-45 and small prototype test points are routed to a amp/tyco mictor connector for additional off-board expansion. this connector can be mounted on the bottom side of the board. the connector is not populated by the manufacturer. review the schematic for the board to determine which i/o pins are routed to the mictor connector. ordering information technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal . all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. revision history description ordering part number china rohs environment- friendly use period (efup) machxo 2280c evaluation board - standard lcmxo2280c-l-ev machxo 640c evaluation board - standard LCMXO640C-L-EV isplever base with machxo 2280 standard development kit ls-x2280-base-pc-n date version change summary june 2006 01.0 initial release. september2006 01.1 updated schematic in appendix a. february 2007 01.2 updated switch assignments table. updated ispclock con?uration section. march 2007 01.3 added ordering information section. april 2007 01.4 added important information for proper connection of ispdownload (programming) cables. june 2007 01.5 updated features bullets and general description section to indicate the power supply will operate between 5v and 20v, instead of 5v to 28v. march 2008 01.6 changed document title from ?achxo standard evaluation board revision 001 user s guide to ?achxo standard evaluation board revision 001 & 002 user s guide? 10
14 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide appendix a. pcb schematic figure 8. machxo control and programming interfaces a a b b c c d d e e 4 4 3 3 2 2 1 1 tdo_clk ckin_pos ckin_neg tdi_clk vccio[3..0] tms_clk lock# ckin_pos ckin_neg clk_out[4..0] v3.3 gnd pllin_pos pllin_neg tck ck_ctrl[7..0] tdo_pld pb1 led[7..0] rj45[37..0] lcd[38..0] proto[99..0] gsr_n vaux tdi_pld switches[7..0] header[33..0] vcore goe_pld tms_pld done_n vcc_adj vcc_1.2v v3.3 gnd vcc_adj vcc_1.2v title size document number rev date: sheet of 0 machxo evaluation board c 112 title size document number rev date: sheet of 0 machxo evaluation board c 112 title size document number rev date: sheet of 0 machxo evaluation board c 112 page 2 page 3 page 4 page 5 page 6 page 7 page 12 b1 connectors tdi_pld tms_clk tck tdo_pld ckin_pos ckin_neg pllin_pos pllin_neg rj45_io[7..0] header[33..0] tdi_clk tdo_clk tms_pld gsr_n goe_pld done_n pb1 b2 power vccio[3..0] vcore vaux b3 machxo tdo tdi tms tck ck_ctrl[7..0] lock_n clk_in[4..0] proto[99..0] vcore vaux vccio[3..0] pllin_neg pllin_pos switches[7..0] lcd[38..0] led[7..0] header[33..0] rj45_io[7..0] goe_pld gsr_n done_n pb1 b4 prototype_area proto[99..0] vccio[3..0] b5 clock_control tdo tdi tms tck ck_ctrl[7..0] ckin_pos ckin_neg clk_out[4..0] lock_n b7 mechanical b6 input_output led[7..0] switches[7..0] lcd[38..0]
15 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 9. machxo i/o connections a a b b c c d d e e 4 4 3 3 2 2 1 1 vccio0 vccio0 vccio0 vccio0 vccio1 vccio1 vccio1 vccio1 vccio2 vccio2 vccio2 vccio2 vccio3 vccio3 vccio3 vccio3 vccio[3..0] clk_in[4..0] switches[7..0] lcd11 lcd27 rj45_io[7..0] proto10 header4 header5 header0 header1 proto1 proto0 proto3 proto2 proto5 proto4 proto[99..0] header[33..0] rj45_io6 vccio0 vccio1 vccio2 vccio3 rj45_io4 rj45_io5 rj45_io2 rj45_io3 rj45_io1 rj45_io0 proto11 proto16 proto17 proto12 proto15 proto13 proto14 header28 header24 header20 header18 proto50 header22 led[7..0] proto88 proto87 proto85 lcd26 lcd24 lcd25 lcd22 lcd18 lcd16 lcd[38..0] header26 header27 header17 header3 header2 proto6 proto7 header6 header14 header10 rj45_io7 header29 header15 header12 header11 proto49 header16 proto55 header30 proto52 header7 header8 proto56 proto46 proto57 proto54 header31 header32 header13 proto48 header9 header33 proto47 proto53 header25 header23 header19 proto51 proto45 proto86 proto93 proto94 done_n switches0 switches1 switches2 switches3 switches4 switches7 proto92 proto89 lcd7 lcd8 lcd9 lcd10 lcd12 lcd13 lcd14 lcd15 lcd17 lcd19 lcd20 lcd21 lcd23 proto73 proto72 proto74 proto71 proto64 proto65 proto70 lcd38 lcd37 lcd36 lcd35 lcd34 lcd33 lcd32 lcd31 lcd30 lcd29 lcd28 proto61 proto60 proto59 switches6 switches5 proto90 proto91 proto9 proto8 clk_in2 ck_ctrl3 ck_ctrl4 clk_in3 ck_ctrl6 ck_ctrl7 lock_n proto76 proto75 led0 led1 led2 led3 led4 led5 led6 led7 proto77 proto78 ck_ctrl2 proto79 proto80 proto81 proto82 proto84 proto83 ck_ctrl5 proto33 proto34 proto36 proto35 proto38 proto44 proto40 proto42 proto37 proto28 proto31 proto29 proto23 proto21 proto22 proto24 proto27 proto26 proto25 proto39 proto41 proto43 clk_in1 proto30 proto20 proto19 clk_in0 proto18 ck_ctrl0 ck_ctrl1 header21 proto69 proto63 proto62 proto68 proto67 proto66 lcd2 lcd3 lcd4 lcd5 lcd6 lcd1 clk_in4 proto58 lcd0 proto32 clk_in[4..0] proto[99..0] vcore vaux vccio[3..0] switches[7..0] lcd[38..0] header[33..0] rj45_io[7..0] pllin_neg pllin_pos gsr_n led[7..0] goe_pld done_n ck_ctrl[7..0] lock_n pb1 tdi tms tck tdo gnd gnd vcore vaux gnd title size document number rev date: sheet of 0 machxo evaluation board c 212 title size document number rev date: sheet of 0 machxo evaluation board c 212 title size document number rev date: sheet of 0 machxo evaluation board c 212 rj45_io traces are 50 ohm. resistors placed close to u2 place caps close to vcc pins they serve. pllin traces are 50 ohm. resistors placed close to u4 r42 100 cr0603 nopopulate r42 100 cr0603 nopopulate c43 0.1uf cc0402 populate c43 0.1uf cc0402 populate r41 100 cr0603 nopopulate r41 100 cr0603 nopopulate xo_640 common vccio vccj on vccio5 xo_640 common vccio xo_640 common vccio xo_640 common vccio u2e machxo_fpbga256 17mmx17mm populate xo_640 common vccio vccj on vccio5 xo_640 common vccio xo_640 common vccio xo_640 common vccio u2e machxo_fpbga256 17mmx17mm populate vccio0_0 f7 vccio0_1 f8 vccio1_0 f9 vccio1_1 f10 vccio2_0 g11 vccio2_1 h11 vccio3_0 j11 vccio3_1 k11 vccio4_0 l9 vccio4_1 l10 vccio5_0 l7 vccio5_1 l8 vccio6_0 j6 vccio6_1 k6 vccio7_0 g6 vccio7_1 h6 gnd_0 a16 gnd_1 t16 gnd_2 f11 gnd_3 h10 gnd_4 j10 gnd_5 g9 gnd_6 h9 gnd_7 j9 gnd_8 k9 gnd_9 g8 gnd_10 h8 gnd_11 j8 gnd_12 k8 gnd_13 h7 gnd_14 j7 gnd_15 l6 gnd_16 a1 gnd_17 t1 vcc_3 k7 vcc_2 g7 vcc_1 k10 vcc_0 g10 vccaux_0 a8 vccaux_1 t9 r60 100 cr0603 nopopulate r60 100 cr0603 nopopulate r63 100 cr0603 nopopulate r63 100 cr0603 nopopulate c41 0.1uf cc0402 populate c41 0.1uf cc0402 populate 4 o i c c v 5 o i c c v i/os in bank 5 for xo1200 i/os in bank 4 for xo2280 pin name sequence pb(640,1200,2280) u2c machxo_fpbga256 17mmx17mm populate 4 o i c c v 5 o i c c v i/os in bank 5 for xo1200 i/os in bank 4 for xo2280 pin name sequence pb(640,1200,2280) u2c machxo_fpbga256 17mmx17mm populate nc/pb2b/pb2b p3 nc/pb2d/pb2d n6 nc/pb2c/pb2c n5 pb2a/pb3a/pb3a t2 pb2b/pb3b/pb3b t3 pb2c/pb3c/pb3c r4 pb3d/pb4d/pb4d t4 pb3a/pb4a/pb4a p5 pb3b/pb4b/pb4b p6 pb3c/pb4c/pb4c t5 pb4a/pb5a/pb5a r6 pb2d/pb3d/pb3d r5 pb4b/pb5b/pb5b t6 pb4c/pb5c/pb6a t8 pb4d/pb5d/pb6b t7 nc/pb6a/pb7c m7 nc/pb6b/pb7d m8 pb4e/pb6c/pb8c r7 pb4f/pb6d/pb8d r8 pb5c/pb6e/pb9a p7 pb5d/pb6f/pb9b p8 pb5b/pb7b/pb10f/clk2 n9 pb5a/pb7a/pb10e n8 pb7a/pb7c/pb10c p9 pb7b/pb7d/pb10d p10 pb6b/pb7f/pb10b/clk3 m9 pb6a/pb7e/pb10a m10 pb6c/pb8a/pb11c r9 pb6d/pb8b/pb11d r10 pb7c/pb8c/pb12a t10 pb7d/pb8d/pb12b t11 nc/pb8e/pb12c n10 nc/pb8f/pb12d n11 pb7e/pb9a/pb13a r11 pb7f/pb9b/pb13b r12 pb8a/pb9c/pb13c p11 pb8b/pb9d/pb13d p12 pb8c/pb9e/pb14a t13 pb8d/pb9f/pb14b t12 pb9a/pb10a/pb14c r13 pb9b/pb10b/pb14d r14 pb9c/pb10c/pb15a t14 pb9d/pb10d/pb15b t15 nc/pb11a/pb16a r15 nc/pb11b/pb16b r16 sleepn p13 pb9f/pb10f/pb15d p14 nc/pb11c/pb16c p15 nc/pb11d/pb16d p16 tdi n7 tdo m6 tms p4 tck r3 nc/pb2a/pb2a p2 c39 10uf cc0805 populate c39 10uf cc0805 populate r57 100 cr0603 nopopulate r57 100 cr0603 nopopulate c44 10uf cc0805 populate c44 10uf cc0805 populate c16 0.1uf cc0402 populate c16 0.1uf cc0402 populate r61 100 cr0603 nopopulate r61 100 cr0603 nopopulate c17 10uf cc0805 populate c17 10uf cc0805 populate r45 100 cr0603 nopopulate r45 100 cr0603 nopopulate c14 0.1uf cc0402 populate c14 0.1uf cc0402 populate c15 10uf cc0805 populate c15 10uf cc0805 populate c21 0.1uf cc0402 populate c21 0.1uf cc0402 populate c20 10uf cc0805 populate c20 10uf cc0805 populate c19 0.1uf cc0402 populate c19 0.1uf cc0402 populate c42 10uf cc0805 populate c42 10uf cc0805 populate c38 0.1uf cc0402 populate c38 0.1uf cc0402 populate c40 0.1uf cc0402 populate c40 0.1uf cc0402 populate 1 o i c c v 0 o i c c v i/os in bank 0 for xo1200 i/os in bank 1 for xo2280 pin name sequence pt(640,1200,2280) u2a machxo_fpbga256 17mmx17mm populate 1 o i c c v 0 o i c c v i/os in bank 0 for xo1200 i/os in bank 1 for xo2280 pin name sequence pt(640,1200,2280) u2a machxo_fpbga256 17mmx17mm populate nc/pt2a/pt2c b2 nc/pt2b/pt2d b3 pt2a/pt3a/pt3a a2 pt2b/pt3b/pt3b a3 nc/pt2c/pt3c d3 nc/pt2d/pt3d d4 pt2f/pt4b/pt4b c5 pt2e/pt4a/pt4a c4 pt2c/pt3c/pt5a d6 pt2d/pt3d/pt5b d5 pt3a/pt3e/pt5c b4 pt3b/pt3f/pt5d b5 nc/pt4d/pt6f e6 nc/pt4c/pt6e e7 pt3f/pt5b/pt6d a4 pt3e/pt5a/pt6c a5 pt3c/pt5c/pt6a c6 pt3d/pt5d/pt6b c7 pt4a/pt5e/pt7a b6 pt4b/pt5f/pt7b b7 pt4c/pt6a/pt7c a6 pt4d/pt6b/pt7d a7 pt4e/pt6c/pt8c b8 pt4f/pt6d/pt8d c8 pt5b/pt6f/pt9b/clk0 d7 pt5a/pt6e/pt9a d8 pt9a/pt7a/pt9c e8 pt9b/pt7b/pt9d e9 pt6b/pt7d/pt10b/clk1 a9 pt6a/pt7c/pt10a a10 pt6c/pt7e/pt10c c9 pt6d/pt7f/pt10d c10 pt8c/pt8a/pt10e d9 pt8d/pt8b/pt10f d10 pt5c/pt8c/pt11a b9 pt5d/pt8d/pt11b b10 pt7c/pt8e/pt12a a11 pt7d/pt8f/pt12b a12 pt7a/pt9a/pt12c b11 pt7b/pt9b/pt12d b12 pt8a/pt9c/pt13c c11 pt8b/pt9d/pt13d c12 pt7f/pt9f/pt14b a14 pt7e/pt9e/pt14a a13 pt9c/pt10a/pt14c d11 pt9d/pt10b/pt14d d12 nc/pt10c/pt15a e10 nc/pt10d/pt15b e11 pt9e/pt10e/pt15c b13 pt9f/pt10f/pt15d c13 nc/pt11a/pt16a b14 nc/pt11b/pt16b c14 nc/pt11c/pt16c a15 nc/pt11d/pt16d b15 r56 100 cr0603 nopopulate r56 100 cr0603 nopopulate r44 100 cr0603 nopopulate r44 100 cr0603 nopopulate r65 100 cr0603 nopopulate r65 100 cr0603 nopopulate 3 o i c c v 2 o i c c v pin name sequence pr(640,1200,2280) u2d machxo_fpbga256 17mmx17mm populate 3 o i c c v 2 o i c c v pin name sequence pr(640,1200,2280) u2d machxo_fpbga256 17mmx17mm populate nc/pr2a/pr3a/lv_t d14 nc/pr2b/pr3b/lv_c d13 nc/pr3a/pr4a/lv_t e13 nc/pr3b/pr4b/lv_c e12 nc/pr3c/pr4c f13 nc/pr3d/pr4d f12 pr3c/pr4a/pr5a/lv_t e14 pr3d/pr4b/pr5b/lv_c f14 pr2a/pr4c/pr5c b16 pr2b/pr4d/pr5d c16 pr2c/pr5a/pr6a/lv_t c15 pr2d/pr5b/pr6b/lv_c d15 pr3a/pr5c/pr6c d16 pr3b/pr5d/pr6d e16 pr4a/pr6a/pr7a/lv_t e15 pr4b/pr6b/pr7b/lv_c f15 pr5a/pr6c/pr7c f16 pr5b/pr6d/pr7d g16 pr4c/pr7a/pr9a/lv_t g12 pr4d/pr7b/pr9b/lv_c g13 pr6c/pr7c/pr9c h12 pr6d/pr7d/pr9d h13 pr5c/pr8a/pr10a/lv_t g14 pr5d/pr8b/pr10b/lv_c h14 pr6a/pr8c/pr10c g15 pr6b/pr8d/pr10d h15 pr7a/pr9a/pr11a/lv_t h16 pr7b/pr9b/pr11b/lv_c j16 nc/pr9c/pr11c j12 nc/pr9d/pr11d k12 pr7c/pr10a/pr13a/lv_t j15 pr7d/pr10b/pr13b/lv_c k15 pr8a/pr10c/pr13c j14 pr8b/pr10d/pr13d k14 pr8c/pr11a/pr14a/lv_t j13 pr8d/pr11b/pr14b/lv_c k13 pr9a/pr11c/pr14c k16 pr9b/pr11d/pr14d l16 pr9c/pr12a/pr15a/lv_t l15 pr9d/pr12b/pr15b/lv_c m15 pr10c/pr12c/pr15c m16 pr10d/pr12d/pr15d n16 pr10a/pr13a/pr16a/lv_t l14 pr10b/pr13b/pr16b/lv_c m14 pr11b/pr13d/pr16d l13 pr11a/pr13c/pr16c l12 pr11c/pr14a/pr17a/lv_t n15 pr11d/pr14b/pr17b/lv_c n14 nc/pr14c/pr17c m12 nc/pr14d/pr17d m13 nc/pr15a/pr18a/lv_t n13 nc/pr15b/pr18b/lv_c n12 nc/pr16a/pr20a l11 nc/pr16b/pr20b m11 r58 100 cr0603 nopopulate r58 100 cr0603 nopopulate c18 10uf cc0805 populate c18 10uf cc0805 populate r59 100 cr0603 nopopulate r59 100 cr0603 nopopulate r43 100 cr0603 nopopulate r43 100 cr0603 nopopulate r62 100 cr0603 nopopulate r62 100 cr0603 nopopulate 6 o i c c v 7 o i c c v pin name sequence pl(640,1200,2280) u2b machxo_fpbga256 17mmx17mm populate 6 o i c c v 7 o i c c v pin name sequence pl(640,1200,2280) u2b machxo_fpbga256 17mmx17mm populate nc/pl2a/pl2a/pll1t_fb e4 nc/pl2b/pl2b/pll1c_fb e5 nc/pl3a/pl3a/lv_t f5 nc/pl3b/pl3b/lv_c f6 pl3a/pl3c/pl3c/pll1t_in f3 pl3b/pl3d/pl3d/pll1c_in f4 pl2c/pl4a/pl4a/lv_t e3 pl2d/pl4b/pl4b/lv_c e2 nc/pl4c/pl4c c3 nc/pl4d/pl4d c2 pl2a/pl5a/pl5a/lv_t b1 pl2b/pl5b/pl5b/lv_c c1 pl3c/pl5c/pl6c d2 pl3d/pl5d/pl6d d1 pl5a/pl6a/pl7a/lv_t f2 pl5b/pl6b/pl7b/gsr/lv_c g2 pl4a/pl6c/pl7c e1 pl4b/pl6d/pl7d f1 nc/pl7a/pl8a/lv_t g4 nc/pl7b/pl8b/lv_c g5 pl4c/pl7c/pl8c g3 pl4d/pl7d/pl8d h3 nc/pl8a/pl9a/lv_t h4 nc/pl8b/pl9b/lv_c h5 pl5c/pl8c/pl10c g1 pl5d/pl8d/pl10d h1 pl6a/pl9a/pl11a/lv_t h2 pl6b/pl9b/pl11b/lv_c j2 pl7c/pl9c/pl11c j3 pl7d/pl9d/pl11d k3 pl6c/pl10a/pl12a/lv_t j1 pl6d/pl10b/pl12b/lv_c k1 pl9a/pl10c/pl12c k2 pl9b/pl10d/pl12d l2 pl7a/pl11a/pl13a/lv_t l1 tsall/pl8c/pl11c/pl14c n1 pl8d/pl11d/pl14d p1 pl10a/pl12a/pl15a/lv_t l3 pl10b/pl12b/pl15b/lv_c m3 pl9c/pl12c/pl15c m2 pl9d/pl12d/pl15d n2 pl8a/pl13a/pl16a/lv_t j4 pl8b/pl13b/pl16b/lv_c j5 pl11a/pl13c/pl16c r1 pl11b/pl13d/pl16d r2 nc/pl14a/pl17a/lv_t/pll0_t_fb k5 nc/pl14b/pl17b/lv_c/pll0_c_fb k4 pl10c/pl14c/pl17c l5 pl10d/pl14d/pl17d l4 nc/pl15a/pl18a/lv_t/pll0_t_in m5 nc/pl15b/pl18b/lv_c/pll0_c_in m4 pl11c/pl16a/pl19a n4 pl11d/pl16b/pl19b n3 pl7b/pl11b/pl13b/lv_c m1 r64 100 cr0603 nopopulate r64 100 cr0603 nopopulate
16 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 10. power section a a b b c c d d e e 4 4 3 3 2 2 1 1 pwr_adj vcc_in v3.3 vcc_1.2v v3.3 pwr_3.3v vccio1 vccio3 vccio[3..0] vaux pwr_3.3v pwr_1.2v drain_1.2 pwr_3.3v drain_adj vccio2 vccio0 vcc_adj vaux vcc_adj vcc_adj vcc_1.2v v3.3 vcc_1.2v drain_adj drain_1.2 vccio[3..0] vaux vcore gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v3.3 vcc_adj vcc_1.2v title size document number rev date: sheet of 0 machxo evaluation board c 312 title size document number rev date: sheet of 0 machxo evaluation board c 312 title size document number rev date: sheet of 0 machxo evaluation board c 312 another p-channel mosfet option in sot23 package another p-channel mosfet option in sot23 package on off 3.3v on/off switch c2012x5roj475m select only one voltage for each vccio output voltage adjust current sense resistors voltage across resistor / .01 = current in amps 4.5vdc to 28vdc rapc712 2.5mm pin, (+) 5.5mm barrel, (-) dc-dc converter traces >= 10mil dc-dc converter traces >= 10mil dc-dc converter traces >= 10mil vccio0 vccio1 vccio3 3.3v adj 1.2v load only one current sense resistor for vcc_core use 1.2v for lfxpxxe devices use 1.8v, 2.5v, or 3.3v for lfxpxxc devices for 1.8v and 2.5v use vcc_adj 3.3v adj 1.2v 3.3v adj 1.2v vcore 1.2v v_adj 3.3v jp20 header 3x2 populate hdr_3x2_100mil jp20 header 3x2 populate hdr_3x2_100mil 2 4 6 1 3 5 q3 si5447dc populate 1206-8 q3 si5447dc populate 1206-8 d 1 d 2 d 3 g 4 s 5 d 6 d 7 d 8 j55 jblock populate j55 jblock populate q4 si5447dc populate 1206-8 q4 si5447dc populate 1206-8 d 1 d 2 d 3 g 4 s 5 d 6 d 7 d 8 r144 0.005 602sj nopopulate r144 0.005 602sj nopopulate c29 100uf sized populate c29 100uf sized populate 1 2 u4 ltc1775 populate u4 ltc1775 populate sgnd 6 run/ss 3 tg 13 sw 14 tk 15 extvcc 1 vosence 7 ith 5 vprog 8 fcb 4 pgnd 9 boost 12 intvcc 11 bg 10 vin 16 l10 6.2uh 7mmx7mm populate l10 6.2uh 7mmx7mm populate 1 2 jp25 conn_red cn_joh_111_0701_001 populate jp25 conn_red cn_joh_111_0701_001 populate s 1 r141 0.005 602sj nopopulate r141 0.005 602sj nopopulate c24 1uf sizea populate c24 1uf sizea populate 1 2 c34 4.7pf cc0402 populate c34 4.7pf cc0402 populate jp29 conn_red cn_joh_111_0701_001 populate jp29 conn_red cn_joh_111_0701_001 populate s 1 s5 sw spdt populate s5 sw spdt populate 2 1 3 c33 4.7pf cc0402 populate c33 4.7pf cc0402 populate c35 470uf sized populate c35 470uf sized populate 1 2 r147 10 cr0603 populate r147 10 cr0603 populate jp27 conn_red cn_joh_111_0701_001 populate jp27 conn_red cn_joh_111_0701_001 populate s 1 c31 2200pf cc0603 populate c31 2200pf cc0603 populate j56 jblock populate j56 jblock populate r153 10 cr0603 populate r153 10 cr0603 populate r145 0.005 602sj populate r145 0.005 602sj populate f1 3a 383milx198mil populate f1 3a 383milx198mil populate 1 2 c26 100uf sized populate c26 100uf sized populate 1 2 c23 0.47uf cc0603 populate c23 0.47uf cc0603 populate f2 3a 383milx198mil populate f2 3a 383milx198mil populate 1 2 c27 10uf sizec populate c27 10uf sizec populate 1 2 j57 jblock populate j57 jblock populate r143 0.005 602sj populate r143 0.005 602sj populate c25 1uf sizea populate c25 1uf sizea populate 1 2 jp28 conn_black cn_joh_111_0701_001 populate jp28 conn_black cn_joh_111_0701_001 populate s 1 d15 b320a sma populate d15 b320a sma populate r151 10k cr0603 populate r151 10k cr0603 populate c36 470uf sized populate c36 470uf sized populate 1 2 r154 500k pot 5.6mmx3.6mm populate r154 500k pot 5.6mmx3.6mm populate 1 3 2 d14 1n5819 populate d14 1n5819 populate jp22 header 3x2 populate hdr_3x2_100mil jp22 header 3x2 populate hdr_3x2_100mil 2 4 6 1 3 5 jp26 conn_red cn_joh_111_0701_001 populate jp26 conn_red cn_joh_111_0701_001 populate s 1 q6 si2323ds sot23 nopopulate q6 si2323ds sot23 nopopulate g d s r150 10k cr0603 populate r150 10k cr0603 populate u6 tps64203dvb sot23-6 populate u6 tps64203dvb sot23-6 populate /en 1 gnd 2 fb 3 isense 4 vin 5 sw 6 r157 10 cr0603 populate r157 10 cr0603 populate r142 0.005 602sj populate r142 0.005 602sj populate f3 3a 383milx198mil populate f3 3a 383milx198mil populate 1 2 d12 mbrs340 smc populate d12 mbrs340 smc populate r148 0.005 602sj populate r148 0.005 602sj populate l8 10uh 15.24mmx18.54mm populate l8 10uh 15.24mmx18.54mm populate 1 2 q2 si4840dy populate q2 si4840dy populate 5 4 1 6 2 3 7 8 q1 si4840dy populate q1 si4840dy populate 5 4 1 6 2 3 7 8 c30 4.7uf cr0805 populate c30 4.7uf cr0805 populate 1 2 r156 10k cr0402 populate r156 10k cr0402 populate c22 100uf sized populate c22 100uf sized populate 1 2 l9 6.2uh 7mmx7mm populate l9 6.2uh 7mmx7mm populate 1 2 u5 tps64203dvb sot23-6 populate u5 tps64203dvb sot23-6 populate /en 1 gnd 2 fb 3 isense 4 vin 5 sw 6 q5 si2323ds sot23 nopopulate q5 si2323ds sot23 nopopulate g d s d16 b320a sma populate d16 b320a sma populate c32 4.7pf cc0402 populate c32 4.7pf cc0402 populate d13 1n5820 267-05 populate d13 1n5820 267-05 populate c37 10uf sizec populate c37 10uf sizec populate 1 2 r146 10k cr0603 populate r146 10k cr0603 populate r155 10k cr0603 populate r155 10k cr0603 populate r149 10 cr0603 populate r149 10 cr0603 populate r152 10k cr0603 populate r152 10k cr0603 populate c28 0.001uf cc0603 populate c28 0.001uf cc0603 populate jp30 pwr jack populate jp30 pwr jack populate 3 2 1 jp21 header 3x2 populate hdr_3x2_100mil jp21 header 3x2 populate hdr_3x2_100mil 2 4 6 1 3 5
17 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 11. miscellaneous interfaces a a b b c c d d e e 4 4 3 3 2 2 1 1 rj45_io0 rj45_io2 rj45_io4 rj45_io6 rj45_io1 rj45_io3 rj45_io5 rj45_io7 rj45_io[7..0] pllin_pos clkin_neg clkin_pos pllin_neg tdi tdo header29 header17 header4 header3 header5 header25 header26 header6 header0 header13 header31 header15 header24 header2 header10 header9 header8 header14 header12 header22 header33 header21 header27 header16 header28 header1 header19 header32 header23 header7 header18 header30 header20 header11 tdi vjtag tdo tms tms tck rj45_io[7..0] header[33..0] pllin_pos ckin_pos pllin_neg ckin_neg tdi_pld tdo_clk tdo_pld tdi_clk tms_clk tms_pld goe_pld gsr_n done_n pb1 tck gnd gnd gnd gnd gnd v3.3 v3.3 gnd gnd v3.3 v3.3 gnd v3.3 gnd v3.3 gnd title size document number rev date: sheet of 0 machxo evaluation board c 412 title size document number rev date: sheet of 0 machxo evaluation board c 412 title size document number rev date: sheet of 0 machxo evaluation board c 412 2 3 4 8 9 10 rj45 footprint 1 5 6 7 pld and ispclk pld only ispclk only pld and ispclk pld only ispclk only init_n trst_n program_n/ispen done rj45_io traces are 50 ohm clkin traces are 50 ohm pllin traces are 50 ohm mount on secondary side silkscreen nomenclature bounded in yellow rectangles jtag header machxo reset global oe done 1 2 3 1 2 3 disable enable machxo reset user switch user switch (p14) jp11 jp16 vjtag tdo tdi tms gnd tck p (f3) 121212 121212 n (f4) p (18) n (19) jp1 rj45_cat5 635milx840mil nopopulate jp1 rj45_cat5 635milx840mil nopopulate 1 2 3 4 5 6 7 8 9 10 u7 mictor debug connector 1000milx343mil nopopulate u7 mictor debug connector 1000milx343mil nopopulate +5vdc 1 gnd dc 3 odd clk 5 odd d15 7 odd d14 9 odd d13 11 odd d12 13 odd d11 15 odd d10 17 odd d9 19 odd d8 21 odd d7 23 odd d6 25 odd d5 27 odd d4 29 odd d3 31 odd d2 33 odd d1 35 odd d0 37 scl 2 sda 4 even clk 6 even d15 8 even d14 10 even d13 12 even d12 14 even d11 16 even d10 18 even d9 20 even d8 22 even d7 24 even d6 26 even d5 28 even d4 30 even d3 32 even d2 34 even d1 36 even d0 38 gnd_0 39 gnd_1 40 gnd_2 41 gnd_3 42 gnd_4 43 m1 mounting hole populate 0_125_npth m1 mounting hole populate 0_125_npth 1 jp7 header 10 hdr10x1_100mil populate jp7 header 10 hdr10x1_100mil populate 1 2 3 4 5 6 7 8 9 10 jp18 header 3 hdr3x1_100mil nopopulate jp18 header 3 hdr3x1_100mil nopopulate 1 2 3 r85 10k cr0402 populate r85 10k cr0402 populate jp2 sma_th 275milx275mil nopopulate jp2 sma_th 275milx275mil nopopulate 1 2 3 4 5 jp3 sma_th 275milx275mil nopopulate jp3 sma_th 275milx275mil nopopulate 1 2 3 4 5 d10 yellow_led cr0603 populate d10 yellow_led cr0603 populate jp4 sma_th 275milx275mil nopopulate jp4 sma_th 275milx275mil nopopulate 1 2 3 4 5 r1 4.7k cr0402 populate r1 4.7k cr0402 populate m2 mounting hole populate 0_125_npth m2 mounting hole populate 0_125_npth 1 jp5 sma_th 275milx275mil nopopulate jp5 sma_th 275milx275mil nopopulate 1 2 3 4 5 r2 4.7k cr0402 populate r2 4.7k cr0402 populate c1 0.1uf cc0402 populate c1 0.1uf cc0402 populate d11 green_led cr0603 populate d11 green_led cr0603 populate r88 470 cr0402 populate r88 470 cr0402 populate s2 sw pushbutton populate 4.7mmx3.5mm s2 sw pushbutton populate 4.7mmx3.5mm 1 4 2 3 r122 10k cr0402 populate r122 10k cr0402 populate jp8 header 2x2 hdr_2x2_100mil populate jp8 header 2x2 hdr_2x2_100mil populate 1 2 3 4 d9 red_led cr0603 populate d9 red_led cr0603 populate j4 jblock populate j4 jblock populate r87 470 cr0402 populate r87 470 cr0402 populate r86 470 cr0402 populate r86 470 cr0402 populate j5 jblock populate j5 jblock populate j1 jblock populate j1 jblock populate r7 4.7k cr0402 populate r7 4.7k cr0402 populate j2 jblock populate j2 jblock populate m4 mounting hole populate 0_125_npth m4 mounting hole populate 0_125_npth 1 j3 jblock populate j3 jblock populate s4 sw pushbutton populate 4.7mmx3.5mm s4 sw pushbutton populate 4.7mmx3.5mm 1 4 2 3 r29 4.7k cr0402 populate r29 4.7k cr0402 populate m3 mounting hole populate 0_125_npth m3 mounting hole populate 0_125_npth 1 jp6 header 3x2 hdr_3x2_100mil populate jp6 header 3x2 hdr_3x2_100mil populate 2 4 6 1 3 5
18 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 12. ispclock5610 connections a a b b c c d d e e 4 4 3 3 2 2 1 1 clk_out[4..0] clk_out0 clk_out1 clk_out2 clk_out4 clk_out3 vclk_d vclk_d vclk_a vclk_a vcco_0 vcco_1 vcco_2 vcco_3 vcco_4 vcco_0 vcco_1 vcco_2 vcco_3 vcco_4 ck_ctrl[7..0] sgate oex oey ck_ctrl0 ck_ctrl2 ck_ctrl3 pulldown1 pullup1 pullup1 pullup1 pullup1 pulldown1 pulldown1 pulldown1 pulldown1 sgate goe_clk oex oey pll_bypass ps0 ps1 pullup0 ck_ctrl4 pulldown0 pullup0 ck_ctrl5 pulldown0 pullup0 ck_ctrl6 pulldown0 pulldown0 pullup0 ps1 ps0 pll_bypass pll_reset pll_reset ck_ctrl7 pullup1 ck_ctrl1 goe_clk tdo tdi tms tck ckin_pos clk_out[4..0] lock_n ckin_neg ck_ctrl[7..0] gnd v3.3 v3.3 gnd v3.3 gnd gnd gnd v3.3 v3.3 gnd gnd v3.3 gnd v3.3 gnd v3.3 gnd v3.3 gnd gnd title size document number rev date: sheet of 0 machxo evaluation board c 512 title size document number rev date: sheet of 0 machxo evaluation board c 512 title size document number rev date: sheet of 0 machxo evaluation board c 512 zero ohm resistors must be placed close to pin 18 of the ispclock_5510 device. ispclock reset oscillator input (m5) 1 5 2 pullup pulldown machxo jp1-7 (p10) (m10) (p7) (p8) (r9) (n8) (p9) ispclock pll bypass ispclock ps0 ispclock ps1 ispclock oex ispclock oey ispclock sgate ispclock goe osc enable 1 2 3 1 2 3 enable disable ispclock 4a (31) ispclock 4b (30) c6 0.1uf cc0402 populate c6 0.1uf cc0402 populate l6 ferrite_bead cr0603 populate l6 ferrite_bead cr0603 populate jp14 header 3x2 hdr_3x2_100mil populate jp14 header 3x2 hdr_3x2_100mil populate 2 4 6 1 3 5 jp17 header 3x2 hdr_3x2_100mil populate jp17 header 3x2 hdr_3x2_100mil populate 2 4 6 1 3 5 c11 0.1uf cc0402 populate c11 0.1uf cc0402 populate c12 10uf cc0805 populate c12 10uf cc0805 populate profile select phase lock loop output dividers output control and routing u1 ispclock_5610 9mmx9mm populate profile select phase lock loop output dividers output control and routing u1 ispclock_5610 9mmx9mm populate refa+ 18 refa- 19 refvtt 20 ps0 44 ps1 43 vcco_0 1 bank_0b 2 bank_0a 3 gndo_0 4 vcco_1 5 bank_1b 6 bank_1a 7 gndo_1 8 vcco_2 9 bank_2b 10 bank_2a 11 gndo_2 12 vcco_3 25 bank_3b 26 bank_3a 27 gndo_3 28 vcco_4 29 bank_4b 30 bank_4a 31 gndo_4 32 vcca 13 gnda 14 sgate 40 goe 42 oex 21 oey 22 lock 34 tdi 39 tdo 35 tms 37 tck 38 test1 46 test2 45 gndd_0 23 gndd_1 48 vccj 36 pll_bypass 47 reset 41 vccd_0 24 vccd_1 33 gndd_2 15 gndd_3 16 gndd_4 17 r5 4.7k cr0402 populate r5 4.7k cr0402 populate jp16 header 3x2 hdr_3x2_100mil populate jp16 header 3x2 hdr_3x2_100mil populate 2 4 6 1 3 5 r3 4.7k cr0402 populate r3 4.7k cr0402 populate s3 sw pushbutton populate 4.7mmx3.5mm s3 sw pushbutton populate 4.7mmx3.5mm 1 4 2 3 c2 0.1uf cc0402 populate c2 0.1uf cc0402 populate l7 ferrite_bead cr0603 populate l7 ferrite_bead cr0603 populate c13 10uf cc0805 populate c13 10uf cc0805 populate l5 ferrite_bead cr0603 populate l5 ferrite_bead cr0603 populate c8 0.1uf cc0402 populate c8 0.1uf cc0402 populate l4 ferrite_bead cr0603 populate l4 ferrite_bead cr0603 populate r158 0 cr0603 populate r158 0 cr0603 populate xu1 dip16 893milx395mil populate xu1 dip16 893milx395mil populate 1 2 3 4 5 6 7 8 9 10 14 16 15 13 12 11 c7 0.1uf cc0402 populate c7 0.1uf cc0402 populate r18 10k cr0402 populate r18 10k cr0402 populate l2 ferrite_bead cr0603 populate l2 ferrite_bead cr0603 populate r17 4.7k cr0402 populate r17 4.7k cr0402 populate tp2 test point tp2 test point 1 r4 4.7k cr0402 populate r4 4.7k cr0402 populate c4 0.1uf cc0402 populate c4 0.1uf cc0402 populate r159 0 cr0603 nopopulate r159 0 cr0603 nopopulate jp11 header 3x2 hdr_3x2_100mil populate jp11 header 3x2 hdr_3x2_100mil populate 2 4 6 1 3 5 l3 ferrite_bead cr0603 populate l3 ferrite_bead cr0603 populate r6 4.7k cr0402 populate r6 4.7k cr0402 populate y1 osc14a populate y1 osc14a populate en 1 gnd 7 out 8 vcc 14 jp9 header 3 hdr3x1_100mil nopopulate jp9 header 3 hdr3x1_100mil nopopulate 1 2 3 tp3 test point tp3 test point 1 tp1 test point tp1 test point 1 l1 ferrite_bead cr0603 populate l1 ferrite_bead cr0603 populate c9 0.1uf cc0402 populate c9 0.1uf cc0402 populate jp15 header 3x2 hdr_3x2_100mil populate jp15 header 3x2 hdr_3x2_100mil populate 2 4 6 1 3 5 jp12 header 3x2 hdr_3x2_100mil populate jp12 header 3x2 hdr_3x2_100mil populate 2 4 6 1 3 5 c3 0.1uf cc0402 populate c3 0.1uf cc0402 populate c5 10uf cc0805 populate c5 10uf cc0805 populate jp13 header 3x2 hdr_3x2_100mil populate jp13 header 3x2 hdr_3x2_100mil populate 2 4 6 1 3 5 c10 0.1uf cc0402 populate c10 0.1uf cc0402 populate
19 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 13. led and lcd connections a a b b c c d d e e 4 4 3 3 2 2 1 1 led_cl0 led_cl1 led_cl2 led_cl3 led_cl4 led_cl5 led_cl6 led_cl7 led0 led1 led2 led3 led4 led5 led6 led7 led[7..0] switches1 switches2 switches3 switches4 switches[7..0] switches0 switches5 switches6 switches7 lcd[38..0] lin35 lin34 lin33 lin32 lin27 lin26 lin25 lin24 lin19 lin18 lin17 lin16 lin10 lin9 lin8 lin3 lin36 lin37 lin38 lin28 lin20 lin31 lin30 lin29 lin11 lin23 lin21 lin22 lin12 lin14 lin15 lin13 lin5 lin4 lin7 lin6 lin0 lcd7 lcd6 lcd5 lcd4 lcd15 lcd14 lcd13 lcd12 lcd11 lcd23 lcd22 lcd21 lcd20 lcd31 lcd30 lcd29 lcd28 lcd38 lcd37 lcd36 lcd0 lcd1 lcd2 lcd3 lcd8 lcd9 lcd10 lcd16 lcd17 lcd18 lcd19 lcd24 lcd25 lcd26 lcd27 lcd32 lcd33 lcd34 lcd35 lin2 lin1 switches[7..0] lcd[38..0] led[7..0] v3.3 gnd gnd v3.3 title size document number rev date: sheet of 0 machxo evaluation board c 612 title size document number rev date: sheet of 0 machxo evaluation board c 612 title size document number rev date: sheet of 0 machxo evaluation board c 612 d0 (r11) d1 (r12) d2 (p11) d3 (p12) d4 (t13) d5 (t12) d6 (r13) d7 (r14) (t3) (r4) (r5) (p5) (p6) (t5) (r6) (g14) (c15) (d15) (d16) (e16) (l13) (n15) (n14) (e14) (e15) (h13) (h12) (g13) (k14) (j14) (j15) (m16) (m15) (l15) (k15) (l16) (k16) (k13) (j13) (h16) (g15) (h14) (g12) (g16) (h15) (c11) (l14) (m14) (l12) (f14) (c16) (f15) (f16) (b16) (t4) j38 jblock nopopulate j38 jblock nopopulate j6 jblock nopopulate j6 jblock nopopulate j43 jblock nopopulate j43 jblock nopopulate d7 green_led cr0603 populate d7 green_led cr0603 populate r30 470 cr0402 populate r30 470 cr0402 populate j54 jblock nopopulate j54 jblock nopopulate j15 jblock nopopulate j15 jblock nopopulate j44 jblock nopopulate j44 jblock nopopulate j49 jblock nopopulate j49 jblock nopopulate j39 jblock nopopulate j39 jblock nopopulate j18 jblock nopopulate j18 jblock nopopulate j34 jblock nopopulate j34 jblock nopopulate d3 green_led cr0603 populate d3 green_led cr0603 populate r37 470 cr0402 populate r37 470 cr0402 populate j40 jblock nopopulate j40 jblock nopopulate j7 jblock nopopulate j7 jblock nopopulate jp24 header 20x2 nopopulate jp24 header 20x2 nopopulate 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 j50 jblock nopopulate j50 jblock nopopulate r204 10k cr0402 populate r204 10k cr0402 populate j35 jblock nopopulate j35 jblock nopopulate j45 jblock nopopulate j45 jblock nopopulate r187 10k cr0402 populate r187 10k cr0402 populate r54 470 cr0402 populate r54 470 cr0402 populate j19 jblock nopopulate j19 jblock nopopulate u3 lcd_5char nopopulate u3 lcd_5char nopopulate com 1 1g 2 qe 3 1d 4 1c 5 2e 6 2d 7 2c 8 3e 9 3d 10 3c 11 dp3 12 4e 13 4d 14 4c 15 dp4 16 5e 17 5d 18 5c 19 5b 20 5a 21 5f 22 5g 23 4b 24 4a 25 f4 26 4g 27 3b 28 3a 29 3f 30 3g 31 dp2 32 2b 33 2a 34 2f 35 2g 36 dp1 37 1b 38 1a 39 1f 40 d6 green_led cr0603 populate d6 green_led cr0603 populate j21 jblock nopopulate j21 jblock nopopulate r28 470 cr0402 populate r28 470 cr0402 populate j26 jblock nopopulate j26 jblock nopopulate j8 jblock nopopulate j8 jblock nopopulate jp23 header 20x2 nopopulate jp23 header 20x2 nopopulate 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 j22 jblock nopopulate j22 jblock nopopulate j11 jblock nopopulate j11 jblock nopopulate d2 green_led cr0603 populate d2 green_led cr0603 populate j20 jblock nopopulate j20 jblock nopopulate j27 jblock nopopulate j27 jblock nopopulate r35 470 cr0402 populate r35 470 cr0402 populate r209 10k cr0402 populate r209 10k cr0402 populate r190 10k cr0402 populate r190 10k cr0402 populate j9 jblock nopopulate j9 jblock nopopulate j23 jblock nopopulate j23 jblock nopopulate j28 jblock nopopulate j28 jblock nopopulate r50 470 cr0402 populate r50 470 cr0402 populate j12 jblock nopopulate j12 jblock nopopulate d5 green_led cr0603 populate d5 green_led cr0603 populate j24 jblock nopopulate j24 jblock nopopulate j29 jblock nopopulate j29 jblock nopopulate j10 jblock nopopulate j10 jblock nopopulate r193 10k cr0402 populate r193 10k cr0402 populate d1 green_led cr0603 populate d1 green_led cr0603 populate j25 jblock nopopulate j25 jblock nopopulate r181 10k cr0402 populate r181 10k cr0402 populate j30 jblock nopopulate j30 jblock nopopulate j13 jblock nopopulate j13 jblock nopopulate r33 470 cr0402 populate r33 470 cr0402 populate j31 jblock nopopulate j31 jblock nopopulate d8 green_led cr0603 populate d8 green_led cr0603 populate j36 jblock nopopulate j36 jblock nopopulate j41 jblock nopopulate j41 jblock nopopulate j16 jblock nopopulate j16 jblock nopopulate j46 jblock nopopulate j46 jblock nopopulate s1 sw dip-8 populate s1 sw dip-8 populate 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 j51 jblock nopopulate j51 jblock nopopulate r39 470 cr0402 populate r39 470 cr0402 populate j37 jblock nopopulate j37 jblock nopopulate d4 green_led cr0603 populate d4 green_led cr0603 populate j47 jblock nopopulate j47 jblock nopopulate j42 jblock nopopulate j42 jblock nopopulate j14 jblock nopopulate j14 jblock nopopulate j52 jblock nopopulate j52 jblock nopopulate j32 jblock nopopulate j32 jblock nopopulate r199 10k cr0402 populate r199 10k cr0402 populate j48 jblock nopopulate j48 jblock nopopulate j17 jblock nopopulate j17 jblock nopopulate j53 jblock nopopulate j53 jblock nopopulate r184 10k cr0402 populate r184 10k cr0402 populate j33 jblock nopopulate j33 jblock nopopulate
20 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 14. miscellaneous a a b b c c d d e e 4 4 3 3 2 2 1 1 proto[99..0] proto[99..0] proto[99..0] proto[99..0] proto[99..0] vccio[3..0] v_pu_top v3.3 vcc_adj vcc_1.2v v3.3 proto[99..0] vccio[3..0] vcc_adj vcc_1.2v v3.3 title size document number rev date: sheet of 0 machxo evaluation board c 712 title size document number rev date: sheet of 0 machxo evaluation board c 712 title size document number rev date: sheet of 0 machxo evaluation board c 712 73..59 45..0 58..46 95..74 page 8 page 9 page 10 page 11 the series resistors with a short circuit should be placed on the pcb with a footprint similar to this: tpx rx machxo io 3.3v 1.2v adj 3.3v 1.2v adj b8 top_ios proto[99..0] v_pullup v_pullup1 b9 left_ios proto[99..0] b10 bottom_ios proto[99..0] v_pullup b11 right_ios proto[99..0] jp19 header 3x2 hdr_3x2_100mil populate jp19 header 3x2 hdr_3x2_100mil populate 2 4 6 1 3 5 jp10 header 3x2 hdr_3x2_100mil populate jp10 header 3x2 hdr_3x2_100mil populate 2 4 6 1 3 5 j59 jblock j59 jblock j58 jblock j58 jblock
21 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 15. prototype area a a b b c c d d e e 4 4 3 3 2 2 1 1 v_pullup proto[99..0] v_pullup proto0 v_pullup proto1 v_pullup proto2 v_pullup proto3 v_pullup proto4 v_pullup1 proto25 proto26 proto27 proto28 proto29 v_pullup proto5 v_pullup proto6 proto7 v_pullup v_pullup proto8 v_pullup proto9 proto31 proto32 proto30 proto33 proto34 v_pullup proto10 v_pullup proto11 proto12 v_pullup v_pullup proto13 v_pullup proto14 proto36 proto37 proto35 proto38 proto39 v_pullup proto15 v_pullup proto16 proto17 v_pullup v_pullup proto18 v_pullup proto19 proto41 proto42 proto40 proto43 proto44 v_pullup proto20 v_pullup proto21 proto22 v_pullup v_pullup proto23 v_pullup proto24 proto45 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 v_pullup1 proto[99..0] v_pullup v_pullup1 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd title size document number rev date: sheet of 0 machxo evaluation board c 812 title size document number rev date: sheet of 0 machxo evaluation board c 812 title size document number rev date: sheet of 0 machxo evaluation board c 812 tp102 test point tp102 test point 1 tp118 test point tp118 test point 1 r211 1k cr0603 nopopulate r211 1k cr0603 nopopulate tp77 test point tp77 test point 1 r246 1k cr0603 nopopulate r246 1k cr0603 nopopulate r226 1k cr0603 nopopulate r226 1k cr0603 nopopulate tp141 test point tp141 test point 1 tp122 test point tp122 test point 1 tp185 test point tp185 test point 1 r201 1k cr0603 nopopulate r201 1k cr0603 nopopulate tp71 test point tp71 test point 1 r252 1k cr0603 nopopulate r252 1k cr0603 nopopulate tp142 test point tp142 test point 1 r248 1k cr0603 nopopulate r248 1k cr0603 nopopulate tp160 test point tp160 test point 1 tp121 test point tp121 test point 1 r232 1k cr0603 nopopulate r232 1k cr0603 nopopulate r254 1k cr0603 nopopulate r254 1k cr0603 nopopulate tp192 test point tp192 test point 1 r14 1k cr0603 nopopulate r14 1k cr0603 nopopulate tp93 test point tp93 test point 1 r251 1k cr0603 nopopulate r251 1k cr0603 nopopulate tp32 test point tp32 test point 1 r206 1k cr0603 nopopulate r206 1k cr0603 nopopulate tp167 test point tp167 test point 1 tp60 test point tp60 test point 1 r16 1k cr0603 nopopulate r16 1k cr0603 nopopulate tp170 test point tp170 test point 1 tp17 test point tp17 test point 1 r229 1k cr0603 nopopulate r229 1k cr0603 nopopulate tp80 test point tp80 test point 1 tp67 test point tp67 test point 1 r249 1k cr0603 nopopulate r249 1k cr0603 nopopulate r196 1k cr0603 nopopulate r196 1k cr0603 nopopulate tp120 test point tp120 test point 1 r131 1k cr0603 nopopulate r131 1k cr0603 nopopulate r191 1k cr0603 nopopulate r191 1k cr0603 nopopulate r15 1k cr0603 nopopulate r15 1k cr0603 nopopulate tp62 test point tp62 test point 1 r194 1k cr0603 nopopulate r194 1k cr0603 nopopulate tp49 test point tp49 test point 1 r250 1k cr0603 nopopulate r250 1k cr0603 nopopulate tp191 test point tp191 test point 1 tp61 test point tp61 test point 1 tp51 test point tp51 test point 1 tp9 test point tp9 test point 1 r185 1k cr0603 nopopulate r185 1k cr0603 nopopulate tp166 test point tp166 test point 1 r130 1k cr0603 nopopulate r130 1k cr0603 nopopulate tp76 test point tp76 test point 1 tp83 test point tp83 test point 1 r113 1k cr0603 nopopulate r113 1k cr0603 nopopulate tp46 test point tp46 test point 1 tp168 test point tp168 test point 1 tp97 test point tp97 test point 1 tp144 test point tp144 test point 1 r132 1k cr0603 nopopulate r132 1k cr0603 nopopulate tp123 test point tp123 test point 1 r125 1k cr0603 nopopulate r125 1k cr0603 nopopulate tp159 test point tp159 test point 1 tp30 test point tp30 test point 1 r115 1k cr0603 nopopulate r115 1k cr0603 nopopulate r188 1k cr0603 nopopulate r188 1k cr0603 nopopulate tp90 test point tp90 test point 1 tp96 test point tp96 test point 1 r126 1k cr0603 nopopulate r126 1k cr0603 nopopulate tp98 test point tp98 test point 1 tp183 test point tp183 test point 1 tp161 test point tp161 test point 1 r31 1k cr0603 nopopulate r31 1k cr0603 nopopulate tp138 test point tp138 test point 1 r182 1k cr0603 nopopulate r182 1k cr0603 nopopulate tp33 test point tp33 test point 1 r114 1k cr0603 nopopulate r114 1k cr0603 nopopulate r34 1k cr0603 nopopulate r34 1k cr0603 nopopulate r124 1k cr0603 nopopulate r124 1k cr0603 nopopulate r192 1k cr0603 nopopulate r192 1k cr0603 nopopulate tp5 test point tp5 test point 1 r11 1k cr0603 nopopulate r11 1k cr0603 nopopulate tp357 test point tp357 test point 1 r110 1k cr0603 nopopulate r110 1k cr0603 nopopulate r103 1k cr0603 nopopulate r103 1k cr0603 nopopulate r197 1k cr0603 nopopulate r197 1k cr0603 nopopulate r13 1k cr0603 nopopulate r13 1k cr0603 nopopulate r32 1k cr0603 nopopulate r32 1k cr0603 nopopulate r112 1k cr0603 nopopulate r112 1k cr0603 nopopulate r38 1k cr0603 nopopulate r38 1k cr0603 nopopulate r99 1k cr0603 nopopulate r99 1k cr0603 nopopulate r111 1k cr0603 nopopulate r111 1k cr0603 nopopulate r169 1k cr0603 nopopulate r169 1k cr0603 nopopulate r195 1k cr0603 nopopulate r195 1k cr0603 nopopulate tp327 test point tp327 test point 1 r107 1k cr0603 nopopulate r107 1k cr0603 nopopulate tp53 test point tp53 test point 1 tp35 test point tp35 test point 1 r172 1k cr0603 nopopulate r172 1k cr0603 nopopulate tp12 test point tp12 test point 1 r179 1k cr0603 nopopulate r179 1k cr0603 nopopulate r12 1k cr0603 nopopulate r12 1k cr0603 nopopulate tp189 test point tp189 test point 1 tp162 test point tp162 test point 1 tp82 test point tp82 test point 1 tp6 test point tp6 test point 1 tp148 test point tp148 test point 1 tp86 test point tp86 test point 1 r165 1k cr0603 nopopulate r165 1k cr0603 nopopulate r260 1k cr0603 nopopulate r260 1k cr0603 nopopulate tp65 test point tp65 test point 1 r40 1k cr0603 nopopulate r40 1k cr0603 nopopulate tp219 test point tp219 test point 1 tp29 test point tp29 test point 1 tp34 test point tp34 test point 1 r163 1k cr0603 nopopulate r163 1k cr0603 nopopulate tp190 test point tp190 test point 1 tp220 test point tp220 test point 1 tp59 test point tp59 test point 1 r180 1k cr0603 nopopulate r180 1k cr0603 nopopulate r36 1k cr0603 nopopulate r36 1k cr0603 nopopulate tp208 test point tp208 test point 1 r171 1k cr0603 nopopulate r171 1k cr0603 nopopulate tp165 test point tp165 test point 1 tp137 test point tp137 test point 1 tp104 test point tp104 test point 1 r170 1k cr0603 nopopulate r170 1k cr0603 nopopulate tp78 test point tp78 test point 1 tp84 test point tp84 test point 1 r19 1k cr0603 nopopulate r19 1k cr0603 nopopulate r259 1k cr0603 nopopulate r259 1k cr0603 nopopulate tp87 test point tp87 test point 1 tp139 test point tp139 test point 1 tp50 test point tp50 test point 1 r164 1k cr0603 nopopulate r164 1k cr0603 nopopulate tp70 test point tp70 test point 1 r200 1k cr0603 nopopulate r200 1k cr0603 nopopulate r21 1k cr0603 nopopulate r21 1k cr0603 nopopulate r261 1k cr0603 nopopulate r261 1k cr0603 nopopulate r168 1k cr0603 nopopulate r168 1k cr0603 nopopulate r210 1k cr0603 nopopulate r210 1k cr0603 nopopulate r98 1k cr0603 nopopulate r98 1k cr0603 nopopulate r166 1k cr0603 nopopulate r166 1k cr0603 nopopulate r20 1k cr0603 nopopulate r20 1k cr0603 nopopulate r106 1k cr0603 nopopulate r106 1k cr0603 nopopulate r167 1k cr0603 nopopulate r167 1k cr0603 nopopulate tp37 test point tp37 test point 1 tp342 test point tp342 test point 1 r205 1k cr0603 nopopulate r205 1k cr0603 nopopulate tp63 test point tp63 test point 1 r24 1k cr0603 nopopulate r24 1k cr0603 nopopulate r117 1k cr0603 nopopulate r117 1k cr0603 nopopulate tp69 test point tp69 test point 1 r102 1k cr0603 nopopulate r102 1k cr0603 nopopulate tp4 test point tp4 test point 1 tp28 test point tp28 test point 1 r22 1k cr0603 nopopulate r22 1k cr0603 nopopulate tp115 test point tp115 test point 1 r128 1k cr0603 nopopulate r128 1k cr0603 nopopulate tp11 test point tp11 test point 1 r263 1k cr0603 nopopulate r263 1k cr0603 nopopulate r129 1k cr0603 nopopulate r129 1k cr0603 nopopulate r10 1k cr0603 nopopulate r10 1k cr0603 nopopulate tp36 test point tp36 test point 1 tp146 test point tp146 test point 1 r23 1k cr0603 nopopulate r23 1k cr0603 nopopulate tp207 test point tp207 test point 1 tp203 test point tp203 test point 1 tp206 test point tp206 test point 1 r127 1k cr0603 nopopulate r127 1k cr0603 nopopulate r8 1k cr0603 nopopulate r8 1k cr0603 nopopulate tp186 test point tp186 test point 1 tp204 test point tp204 test point 1 tp16 test point tp16 test point 1 tp14 test point tp14 test point 1 r116 1k cr0603 nopopulate r116 1k cr0603 nopopulate tp94 test point tp94 test point 1 tp143 test point tp143 test point 1 tp117 test point tp117 test point 1 tp100 test point tp100 test point 1 tp72 test point tp72 test point 1 tp27 test point tp27 test point 1 r118 1k cr0603 nopopulate r118 1k cr0603 nopopulate r175 1k cr0603 nopopulate r175 1k cr0603 nopopulate r262 1k cr0603 nopopulate r262 1k cr0603 nopopulate r68 1k cr0603 nopopulate r68 1k cr0603 nopopulate r91 1k cr0603 nopopulate r91 1k cr0603 nopopulate r173 1k cr0603 nopopulate r173 1k cr0603 nopopulate tp54 test point tp54 test point 1 r264 1k cr0603 nopopulate r264 1k cr0603 nopopulate r9 1k cr0603 nopopulate r9 1k cr0603 nopopulate r174 1k cr0603 nopopulate r174 1k cr0603 nopopulate tp312 test point tp312 test point 1 r176 1k cr0603 nopopulate r176 1k cr0603 nopopulate r78 1k cr0603 nopopulate r78 1k cr0603 nopopulate r83 1k cr0603 nopopulate r83 1k cr0603 nopopulate tp116 test point tp116 test point 1 r178 1k cr0603 nopopulate r178 1k cr0603 nopopulate tp187 test point tp187 test point 1 r95 1k cr0603 nopopulate r95 1k cr0603 nopopulate tp66 test point tp66 test point 1 r72 1k cr0603 nopopulate r72 1k cr0603 nopopulate tp92 test point tp92 test point 1 tp147 test point tp147 test point 1 r239 1k cr0603 nopopulate r239 1k cr0603 nopopulate tp81 test point tp81 test point 1 tp355 test point tp355 test point 1 r90 1k cr0603 nopopulate r90 1k cr0603 nopopulate tp74 test point tp74 test point 1 tp31 test point tp31 test point 1 tp47 test point tp47 test point 1 r236 1k cr0603 nopopulate r236 1k cr0603 nopopulate tp68 test point tp68 test point 1 r79 1k cr0603 nopopulate r79 1k cr0603 nopopulate tp15 test point tp15 test point 1 r177 1k cr0603 nopopulate r177 1k cr0603 nopopulate tp73 test point tp73 test point 1 r243 1k cr0603 nopopulate r243 1k cr0603 nopopulate r94 1k cr0603 nopopulate r94 1k cr0603 nopopulate r26 1k cr0603 nopopulate r26 1k cr0603 nopopulate tp8 test point tp8 test point 1 r183 1k cr0603 nopopulate r183 1k cr0603 nopopulate r69 1k cr0603 nopopulate r69 1k cr0603 nopopulate tp124 test point tp124 test point 1 tp140 test point tp140 test point 1 tp85 test point tp85 test point 1 tp205 test point tp205 test point 1 tp163 test point tp163 test point 1 tp58 test point tp58 test point 1 r189 1k cr0603 nopopulate r189 1k cr0603 nopopulate tp164 test point tp164 test point 1 r230 1k cr0603 nopopulate r230 1k cr0603 nopopulate tp182 test point tp182 test point 1 tp119 test point tp119 test point 1 tp48 test point tp48 test point 1 r73 1k cr0603 nopopulate r73 1k cr0603 nopopulate tp181 test point tp181 test point 1 r82 1k cr0603 nopopulate r82 1k cr0603 nopopulate tp95 test point tp95 test point 1 tp64 test point tp64 test point 1 r27 1k cr0603 nopopulate r27 1k cr0603 nopopulate r267 1k cr0603 nopopulate r267 1k cr0603 nopopulate r227 1k cr0603 nopopulate r227 1k cr0603 nopopulate r25 1k cr0603 nopopulate r25 1k cr0603 nopopulate r186 1k cr0603 nopopulate r186 1k cr0603 nopopulate r224 1k cr0603 nopopulate r224 1k cr0603 nopopulate r214 1k cr0603 nopopulate r214 1k cr0603 nopopulate r265 1k cr0603 nopopulate r265 1k cr0603 nopopulate tp75 test point tp75 test point 1 tp45 test point tp45 test point 1 r233 1k cr0603 nopopulate r233 1k cr0603 nopopulate r47 1k cr0603 nopopulate r47 1k cr0603 nopopulate r215 1k cr0603 nopopulate r215 1k cr0603 nopopulate r223 1k cr0603 nopopulate r223 1k cr0603 nopopulate r162 1k cr0603 nopopulate r162 1k cr0603 nopopulate r219 1k cr0603 nopopulate r219 1k cr0603 nopopulate tp57 test point tp57 test point 1 r240 1k cr0603 nopopulate r240 1k cr0603 nopopulate r160 1k cr0603 nopopulate r160 1k cr0603 nopopulate r266 1k cr0603 nopopulate r266 1k cr0603 nopopulate r55 1k cr0603 nopopulate r55 1k cr0603 nopopulate tp52 test point tp52 test point 1 r218 1k cr0603 nopopulate r218 1k cr0603 nopopulate tp125 test point tp125 test point 1 r247 1k cr0603 nopopulate r247 1k cr0603 nopopulate tp101 test point tp101 test point 1 tp103 test point tp103 test point 1 tp89 test point tp89 test point 1 tp7 test point tp7 test point 1 r244 1k cr0603 nopopulate r244 1k cr0603 nopopulate tp169 test point tp169 test point 1 r51 1k cr0603 nopopulate r51 1k cr0603 nopopulate r253 1k cr0603 nopopulate r253 1k cr0603 nopopulate tp184 test point tp184 test point 1 r161 1k cr0603 nopopulate r161 1k cr0603 nopopulate tp10 test point tp10 test point 1 tp13 test point tp13 test point 1 r237 1k cr0603 nopopulate r237 1k cr0603 nopopulate tp145 test point tp145 test point 1 tp88 test point tp88 test point 1 tp99 test point tp99 test point 1
22 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 16. prototype area (cont.) a a b b c c d d e e 4 4 3 3 2 2 1 1 proto[99..0] proto62 proto63 proto65 proto64 proto66 proto67 proto60 proto59 proto61 proto68 proto71 proto70 proto69 proto72 proto73 proto[99..0] gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd title size document number rev date: sheet of 0 machxo evaluation board c 912 title size document number rev date: sheet of 0 machxo evaluation board c 912 title size document number rev date: sheet of 0 machxo evaluation board c 912 the differential resistor network should be placed close to the machxo device. testpoint grid of unconnected plated through holes. arrange in the same pattern on the board as shown on this page. tp284 test point tp284 test point 1 tp397 test point tp397 test point 1 tp410 test point tp410 test point 1 tp343 test point tp343 test point 1 tp405 test point tp405 test point 1 tp345 test point tp345 test point 1 r100 100 cr0603 nopopulate r100 100 cr0603 nopopulate tp388 test point tp388 test point 1 tp390 test point tp390 test point 1 tp459 test point tp459 test point 1 tp302 test point tp302 test point 1 tp365 test point tp365 test point 1 tp445 test point tp445 test point 1 tp336 test point tp336 test point 1 tp319 test point tp319 test point 1 r119 100 cr0603 nopopulate r119 100 cr0603 nopopulate tp290 test point tp290 test point 1 tp408 test point tp408 test point 1 tp282 test point tp282 test point 1 tp418 test point tp418 test point 1 tp393 test point tp393 test point 1 tp396 test point tp396 test point 1 tp452 test point tp452 test point 1 tp368 test point tp368 test point 1 tp429 test point tp429 test point 1 tp339 test point tp339 test point 1 tp362 test point tp362 test point 1 tp415 test point tp415 test point 1 tp322 test point tp322 test point 1 tp333 test point tp333 test point 1 tp449 test point tp449 test point 1 tp293 test point tp293 test point 1 tp426 test point tp426 test point 1 tp412 test point tp412 test point 1 tp455 test point tp455 test point 1 tp432 test point tp432 test point 1 tp372 test point tp372 test point 1 tp299 test point tp299 test point 1 tp384 test point tp384 test point 1 tp422 test point tp422 test point 1 tp328 test point tp328 test point 1 tp383 test point tp383 test point 1 tp360 test point tp360 test point 1 r96 100 cr0603 nopopulate r96 100 cr0603 nopopulate tp389 test point tp389 test point 1 tp391 test point tp391 test point 1 tp285 test point tp285 test point 1 tp303 test point tp303 test point 1 tp374 test point tp374 test point 1 tp366 test point tp366 test point 1 tp411 test point tp411 test point 1 tp188 test point tp188 test point 1 tp286 test point tp286 test point 1 tp349 test point tp349 test point 1 tp340 test point tp340 test point 1 tp297 test point tp297 test point 1 tp320 test point tp320 test point 1 tp326 test point tp326 test point 1 tp291 test point tp291 test point 1 tp394 test point tp394 test point 1 tp453 test point tp453 test point 1 tp369 test point tp369 test point 1 r255 100 cr0603 nopopulate r255 100 cr0603 nopopulate tp439 test point tp439 test point 1 tp352 test point tp352 test point 1 tp363 test point tp363 test point 1 tp416 test point tp416 test point 1 tp323 test point tp323 test point 1 tp346 test point tp346 test point 1 tp450 test point tp450 test point 1 tp294 test point tp294 test point 1 tp436 test point tp436 test point 1 tp413 test point tp413 test point 1 tp456 test point tp456 test point 1 tp370 test point tp370 test point 1 tp442 test point tp442 test point 1 tp385 test point tp385 test point 1 tp419 test point tp419 test point 1 tp314 test point tp314 test point 1 tp434 test point tp434 test point 1 tp313 test point tp313 test point 1 tp373 test point tp373 test point 1 tp341 test point tp341 test point 1 tp421 test point tp421 test point 1 tp400 test point tp400 test point 1 tp392 test point tp392 test point 1 tp300 test point tp300 test point 1 tp316 test point tp316 test point 1 tp375 test point tp375 test point 1 tp377 test point tp377 test point 1 tp423 test point tp423 test point 1 tp287 test point tp287 test point 1 tp350 test point tp350 test point 1 tp310 test point tp310 test point 1 tp321 test point tp321 test point 1 tp281 test point tp281 test point 1 tp311 test point tp311 test point 1 tp304 test point tp304 test point 1 r241 100 cr0603 nopopulate r241 100 cr0603 nopopulate tp469 test point tp469 test point 1 tp395 test point tp395 test point 1 tp463 test point tp463 test point 1 tp380 test point tp380 test point 1 tp440 test point tp440 test point 1 tp353 test point tp353 test point 1 tp417 test point tp417 test point 1 tp324 test point tp324 test point 1 tp347 test point tp347 test point 1 tp460 test point tp460 test point 1 tp307 test point tp307 test point 1 tp437 test point tp437 test point 1 tp414 test point tp414 test point 1 tp466 test point tp466 test point 1 tp295 test point tp295 test point 1 tp443 test point tp443 test point 1 tp398 test point tp398 test point 1 tp420 test point tp420 test point 1 tp329 test point tp329 test point 1 tp358 test point tp358 test point 1 tp446 test point tp446 test point 1 tp283 test point tp283 test point 1 tp386 test point tp386 test point 1 tp401 test point tp401 test point 1 tp403 test point tp403 test point 1 tp315 test point tp315 test point 1 tp317 test point tp317 test point 1 tp376 test point tp376 test point 1 tp378 test point tp378 test point 1 tp435 test point tp435 test point 1 tp288 test point tp288 test point 1 tp351 test point tp351 test point 1 tp433 test point tp433 test point 1 tp334 test point tp334 test point 1 tp296 test point tp296 test point 1 tp305 test point tp305 test point 1 r234 100 cr0603 nopopulate r234 100 cr0603 nopopulate tp406 test point tp406 test point 1 tp464 test point tp464 test point 1 tp381 test point tp381 test point 1 tp441 test point tp441 test point 1 tp354 test point tp354 test point 1 tp427 test point tp427 test point 1 tp337 test point tp337 test point 1 tp348 test point tp348 test point 1 tp461 test point tp461 test point 1 tp308 test point tp308 test point 1 tp331 test point tp331 test point 1 tp438 test point tp438 test point 1 r104 100 cr0603 nopopulate r104 100 cr0603 nopopulate tp424 test point tp424 test point 1 tp467 test point tp467 test point 1 tp444 test point tp444 test point 1 tp430 test point tp430 test point 1 tp344 test point tp344 test point 1 tp298 test point tp298 test point 1 tp458 test point tp458 test point 1 r108 100 cr0603 nopopulate r108 100 cr0603 nopopulate tp371 test point tp371 test point 1 tp399 test point tp399 test point 1 tp402 test point tp402 test point 1 tp404 test point tp404 test point 1 tp330 test point tp330 test point 1 tp126 test point tp126 test point 1 tp318 test point tp318 test point 1 tp387 test point tp387 test point 1 tp379 test point tp379 test point 1 tp447 test point tp447 test point 1 tp301 test point tp301 test point 1 tp364 test point tp364 test point 1 tp325 test point tp325 test point 1 tp335 test point tp335 test point 1 tp306 test point tp306 test point 1 tp289 test point tp289 test point 1 tp407 test point tp407 test point 1 tp465 test point tp465 test point 1 tp382 test point tp382 test point 1 tp451 test point tp451 test point 1 tp367 test point tp367 test point 1 tp356 test point tp356 test point 1 tp428 test point tp428 test point 1 tp338 test point tp338 test point 1 tp361 test point tp361 test point 1 tp462 test point tp462 test point 1 tp309 test point tp309 test point 1 tp332 test point tp332 test point 1 tp448 test point tp448 test point 1 tp292 test point tp292 test point 1 r92 100 cr0603 nopopulate r92 100 cr0603 nopopulate tp457 test point tp457 test point 1 tp425 test point tp425 test point 1 tp468 test point tp468 test point 1 tp454 test point tp454 test point 1 tp409 test point tp409 test point 1 tp431 test point tp431 test point 1 tp359 test point tp359 test point 1
23 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 17. prototype area (cont.) a a b b c c d d e e 4 4 3 3 2 2 1 1 proto[99..0] v_pullup v_pullup proto74 v_pullup v_pullup proto77 proto76 v_pullup proto78 v_pullup proto75 proto80 v_pullup proto79 v_pullup proto81 v_pullup proto82 proto83 v_pullup v_pullup v_pullup v_pullup v_pullup proto84 v_pullup v_pullup proto85 proto87 proto88 proto86 v_pullup proto89 v_pullup v_pullup v_pullup v_pullup proto90 proto91 proto93 proto92 v_pullup proto94 proto[99..0] v_pullup gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd title size document number rev date: sheet of 0 machxo evaluation board c 10 12 title size document number rev date: sheet of 0 machxo evaluation board c 10 12 title size document number rev date: sheet of 0 machxo evaluation board c 10 12 tp128 test point tp128 test point 1 tp149 test point tp149 test point 1 tp248 test point tp248 test point 1 tp279 test point tp279 test point 1 tp153 test point tp153 test point 1 tp198 test point tp198 test point 1 r138 1k cr0603 nopopulate r138 1k cr0603 nopopulate tp133 test point tp133 test point 1 tp276 test point tp276 test point 1 tp129 test point tp129 test point 1 tp233 test point tp233 test point 1 tp230 test point tp230 test point 1 tp217 test point tp217 test point 1 r257 1k cr0603 nopopulate r257 1k cr0603 nopopulate tp227 test point tp227 test point 1 tp156 test point tp156 test point 1 tp267 test point tp267 test point 1 tp256 test point tp256 test point 1 tp264 test point tp264 test point 1 tp173 test point tp173 test point 1 tp210 test point tp210 test point 1 tp180 test point tp180 test point 1 tp134 test point tp134 test point 1 tp176 test point tp176 test point 1 tp218 test point tp218 test point 1 r123 1k cr0603 nopopulate r123 1k cr0603 nopopulate tp259 test point tp259 test point 1 tp130 test point tp130 test point 1 r139 1k cr0603 nopopulate r139 1k cr0603 nopopulate r49 1k cr0603 nopopulate r49 1k cr0603 nopopulate tp177 test point tp177 test point 1 tp196 test point tp196 test point 1 tp261 test point tp261 test point 1 r203 1k cr0603 nopopulate r203 1k cr0603 nopopulate r97 1k cr0603 nopopulate r97 1k cr0603 nopopulate tp253 test point tp253 test point 1 tp257 test point tp257 test point 1 tp151 test point tp151 test point 1 tp158 test point tp158 test point 1 r133 1k cr0603 nopopulate r133 1k cr0603 nopopulate r101 1k cr0603 nopopulate r101 1k cr0603 nopopulate r76 1k cr0603 nopopulate r76 1k cr0603 nopopulate tp232 test point tp232 test point 1 tp154 test point tp154 test point 1 tp107 test point tp107 test point 1 tp260 test point tp260 test point 1 r228 1k cr0603 nopopulate r228 1k cr0603 nopopulate tp269 test point tp269 test point 1 tp231 test point tp231 test point 1 tp152 test point tp152 test point 1 r89 1k cr0603 nopopulate r89 1k cr0603 nopopulate r77 1k cr0603 nopopulate r77 1k cr0603 nopopulate tp216 test point tp216 test point 1 r81 1k cr0603 nopopulate r81 1k cr0603 nopopulate tp277 test point tp277 test point 1 r66 1k cr0603 nopopulate r66 1k cr0603 nopopulate r105 1k cr0603 nopopulate r105 1k cr0603 nopopulate r67 1k cr0603 nopopulate r67 1k cr0603 nopopulate tp112 test point tp112 test point 1 r74 1k cr0603 nopopulate r74 1k cr0603 nopopulate r80 1k cr0603 nopopulate r80 1k cr0603 nopopulate r231 1k cr0603 nopopulate r231 1k cr0603 nopopulate tp238 test point tp238 test point 1 r221 1k cr0603 nopopulate r221 1k cr0603 nopopulate tp254 test point tp254 test point 1 tp113 test point tp113 test point 1 r217 1k cr0603 nopopulate r217 1k cr0603 nopopulate tp234 test point tp234 test point 1 r225 1k cr0603 nopopulate r225 1k cr0603 nopopulate r208 1k cr0603 nopopulate r208 1k cr0603 nopopulate r70 1k cr0603 nopopulate r70 1k cr0603 nopopulate tp108 test point tp108 test point 1 tp228 test point tp228 test point 1 r135 1k cr0603 nopopulate r135 1k cr0603 nopopulate tp197 test point tp197 test point 1 r202 1k cr0603 nopopulate r202 1k cr0603 nopopulate r235 1k cr0603 nopopulate r235 1k cr0603 nopopulate tp235 test point tp235 test point 1 tp268 test point tp268 test point 1 tp106 test point tp106 test point 1 tp109 test point tp109 test point 1 tp111 test point tp111 test point 1 tp245 test point tp245 test point 1 r84 1k cr0603 nopopulate r84 1k cr0603 nopopulate tp193 test point tp193 test point 1 tp135 test point tp135 test point 1 tp132 test point tp132 test point 1 tp194 test point tp194 test point 1 tp280 test point tp280 test point 1 tp209 test point tp209 test point 1 r213 1k cr0603 nopopulate r213 1k cr0603 nopopulate r121 1k cr0603 nopopulate r121 1k cr0603 nopopulate tp222 test point tp222 test point 1 r222 1k cr0603 nopopulate r222 1k cr0603 nopopulate tp244 test point tp244 test point 1 tp174 test point tp174 test point 1 r198 1k cr0603 nopopulate r198 1k cr0603 nopopulate r137 1k cr0603 nopopulate r137 1k cr0603 nopopulate tp242 test point tp242 test point 1 r207 1k cr0603 nopopulate r207 1k cr0603 nopopulate tp278 test point tp278 test point 1 tp250 test point tp250 test point 1 r271 1k cr0603 nopopulate r271 1k cr0603 nopopulate tp127 test point tp127 test point 1 tp171 test point tp171 test point 1 r93 1k cr0603 nopopulate r93 1k cr0603 nopopulate tp255 test point tp255 test point 1 tp212 test point tp212 test point 1 r273 1k cr0603 nopopulate r273 1k cr0603 nopopulate r270 1k cr0603 nopopulate r270 1k cr0603 nopopulate r71 1k cr0603 nopopulate r71 1k cr0603 nopopulate r275 1k cr0603 nopopulate r275 1k cr0603 nopopulate r238 1k cr0603 nopopulate r238 1k cr0603 nopopulate r53 1k cr0603 nopopulate r53 1k cr0603 nopopulate tp178 test point tp178 test point 1 tp211 test point tp211 test point 1 r268 1k cr0603 nopopulate r268 1k cr0603 nopopulate tp251 test point tp251 test point 1 tp155 test point tp155 test point 1 r274 1k cr0603 nopopulate r274 1k cr0603 nopopulate tp249 test point tp249 test point 1 tp195 test point tp195 test point 1 tp224 test point tp224 test point 1 tp240 test point tp240 test point 1 tp202 test point tp202 test point 1 tp271 test point tp271 test point 1 tp236 test point tp236 test point 1 r75 1k cr0603 nopopulate r75 1k cr0603 nopopulate tp265 test point tp265 test point 1 tp272 test point tp272 test point 1 tp131 test point tp131 test point 1 tp114 test point tp114 test point 1 r242 1k cr0603 nopopulate r242 1k cr0603 nopopulate r272 1k cr0603 nopopulate r272 1k cr0603 nopopulate tp199 test point tp199 test point 1 tp172 test point tp172 test point 1 tp226 test point tp226 test point 1 tp150 test point tp150 test point 1 r258 1k cr0603 nopopulate r258 1k cr0603 nopopulate r269 1k cr0603 nopopulate r269 1k cr0603 nopopulate tp179 test point tp179 test point 1 tp270 test point tp270 test point 1 tp136 test point tp136 test point 1 r212 1k cr0603 nopopulate r212 1k cr0603 nopopulate tp262 test point tp262 test point 1 r109 1k cr0603 nopopulate r109 1k cr0603 nopopulate r220 1k cr0603 nopopulate r220 1k cr0603 nopopulate r245 1k cr0603 nopopulate r245 1k cr0603 nopopulate r136 1k cr0603 nopopulate r136 1k cr0603 nopopulate tp241 test point tp241 test point 1 tp105 test point tp105 test point 1 tp258 test point tp258 test point 1 tp175 test point tp175 test point 1 tp221 test point tp221 test point 1 tp273 test point tp273 test point 1 r216 1k cr0603 nopopulate r216 1k cr0603 nopopulate tp215 test point tp215 test point 1 tp213 test point tp213 test point 1 r134 1k cr0603 nopopulate r134 1k cr0603 nopopulate r120 1k cr0603 nopopulate r120 1k cr0603 nopopulate tp110 test point tp110 test point 1 tp246 test point tp246 test point 1 tp275 test point tp275 test point 1 tp200 test point tp200 test point 1 tp247 test point tp247 test point 1 r46 1k cr0603 nopopulate r46 1k cr0603 nopopulate tp252 test point tp252 test point 1 r52 1k cr0603 nopopulate r52 1k cr0603 nopopulate tp266 test point tp266 test point 1 r140 1k cr0603 nopopulate r140 1k cr0603 nopopulate tp214 test point tp214 test point 1 tp223 test point tp223 test point 1 tp237 test point tp237 test point 1 tp201 test point tp201 test point 1 r256 1k cr0603 nopopulate r256 1k cr0603 nopopulate r48 1k cr0603 nopopulate r48 1k cr0603 nopopulate tp274 test point tp274 test point 1
24 machxo standard evaluation board lattice semiconductor revisions 001 & 002 user? guide figure 18. prototype area (cont.) a a b b c c d d e e 4 4 3 3 2 2 1 1 proto[99..0] proto52 proto53 proto54 proto55 proto56 proto51 proto46 proto47 proto48 proto49 proto50 proto58 proto57 proto[99..0] gnd gnd gnd title size document number rev date: sheet of 0 machxo evaluation board c 11 12 title size document number rev date: sheet of 0 machxo evaluation board c 11 12 title size document number rev date: sheet of 0 machxo evaluation board c 11 12 tp44 test point tp44 test point 1 tp21 test point tp21 test point 1 tp56 test point tp56 test point 1 tp41 test point tp41 test point 1 tp24 test point tp24 test point 1 tp19 test point tp19 test point 1 tp39 test point tp39 test point 1 tp40 test point tp40 test point 1 tp23 test point tp23 test point 1 tp20 test point tp20 test point 1 tp38 test point tp38 test point 1 tp43 test point tp43 test point 1 tp25 test point tp25 test point 1 tp26 test point tp26 test point 1 tp22 test point tp22 test point 1 tp42 test point tp42 test point 1
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