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publication# 20749 rev: a amendment/ 0 issue date: june 1997 this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. configuring the lan ? sc300 devices internal cga controller for a specific lcd panel application note this application note explains how to determine if a specific lcd panel is supported by the lan tm sc300 microcontroller, and in what modes (cga two-color or four-color graphics, cga text, hga graphics, hga text); how to configure the lansc300 microcontroller to work with the lcd panel in those modes; and which signals need to be connected to the lansc300 microcontroller to properly drive the panel. introduction there are a number of factors that need to be under- stood to accomplish the tasks mentioned above. the sections in the first part of this document provide you with the understanding and background needed to fol- low the procedures beginning on page 7. you are also encouraged to read and have available for reference chapter 3, video controller of the lan tm sc300 mi- crocontroller programmers reference manual , order #18470. definitions the following terms are used throughout this docu- ment. understanding these terms as they apply to the lansc300 microcontroller is essential for understand- ing how to configure the microcontrollers video index registers to work with various lcd panels. single-screen panels a single-screen lcd panel consists of the liquid crys- tal display (lcd) and a set of column drivers (also known as segment drivers) and row drivers (also called common drivers). these drivers supply the appropriate dc voltage to the liquid crystals in the display such that the crystals become aligned and block the light from passing through the display. an entire row of pixels is biased at one time. for this to occur, the pixel data for one row is loaded into the segment drivers. then, a dc voltage is applied to the segment drivers and to the common driver that is attached to the row being dis- played. this process is then repeated for each row of the display. figure 1 is a simplified illustration of an lcd panel that can be driven by the lansc300 microcontroller. not all signals are shown (e.g., frm and m), and not all con- nections of existing signals are shown. as depicted in figure 1, the lansc300 microcontroller drives 4 bits of pixel data at a time. the data is clocked into the seg- ment drivers using the shift clock. when all the data for a row of pixels is loaded into the segment drivers, the line clock will pulse, causing the common driver to ac- tivate the voltage to the common line for the row of pixels being displayed. dual-screen panels a dual-screen lcd panel is two single-screen panels glued so tightly together that they appear to be one panel. each panel has separate data bits but shares the same control signals: shift clock, line clock, and frame start (see the sections that follow). for example, a 640 x 200 dual-screen panel is actually two 640 x 100 single-screen panels glued together. the only dual-screen panel resolution the lansc300 microcontroller supports is 640 x 200. more specific in- formation as to how the lansc300 microcontroller handles a dual-screen panel is discussed later in this document. figure 1. simplified lcd panel configuration
2 configuring the lan?sc300 devices internal cga controller for a specific lcd panel pixel clock this is the standard unit of measure from which all of the lcd clocking signals can be derived. the pixel clock can be loosely defined as the rate at which pixels are displayed on the screen. on the lansc300 micro- controller, the pixel clock used is one of two fixed fre- quencies: 14.336 mhz for hga mode or 9.557 mhz (which is 2/3 of 14.336) for cga mode. on the lansc300 microcontroller, the pixel clock is internal to the video controller and is not available external to the chip. shift clock (cp2) the shift clock, known as the cp2 signal on the lansc300 microcontroller, tells the lcd panel when data is valid on the lcd data bus (the lansc300 mi- crocontroller pins lcdd0Clcdd3 and lcddl0C lcddl3). data is valid on the falling edge of shift clock. the frequency of the shift clock can be determined by the pixel clock frequency divided by the number of data bits per panel. for both single- and dual-screen panels with the lansc300 microcontroller, the number of bits per panel is four. therefore, the shift clock frequency will be either 14.336 mhz 4 data bits = 3.58 mhz, or 9.557 mhz 4 data bits = 2.389 mhz. line clock (cp1) the line clock, known as the cp1 signal on the lansc300 microcontroller, tells the lcd panel that a complete row (horizontal line) of pixel data has been sent to the lcd panel to be displayed. additional shift clocks indicate valid data for the next row of pixels (i.e., display the current row and prepare to receive pixel data for the next row). a line clock pulse will occur once for every row of pixel data sent to the lcd panel. for example, a 320 x 240 lcd screen has 240 rows; therefore, 240 line clocks will occur each time the panel is refreshed. when cp1 is asserted on the lansc300 microcontrol- lers lcd controller, there is a period of about 20 pixel clock cycles during which cp2 will not be asserted. this has a slight effect on the refresh rate as described later in this document. frame start (frm) frame start, known as frm on the lansc300 micro- controller, is asserted at the start of every frame (panel scan). this signal tells the lcd panel that the next data sent to it via the shift clock will be for the top row of the panel. this signal is sometimes referred to as the flm (first line marker) signal. on the lansc300 microcontrollers lcd controller, there is no dead time when frm is asserted. the frm assertion overlaps with the normal cp1 assertion at the end of the last line. refresh rate the refresh rate of the lcd panel is the number of times per second the screen is redrawn. this affects the crispness and brightness of the image on the dis- play. on the lansc300 microcontroller, the refresh rate is affected by the screen resolution programmed into the video controller, the number of bits per pixel (bpp) (in graphics mode only), and the pixel clock fre- quency. on the lansc300 microcontroller, the refresh rate for text mode or 2-color graphics mode can be calculated by dividing the pixel clock frequency by the screen res- olution programmed into the video controller, taking into account the 20 extra pixel clocks per line men- tioned in the previous section. the refresh rate for 4- color graphics mode will be half that amount. for ex- ample, if the controller is programmed for a 320 x 240 lcd screen and configured for cga 2-color mode (which means that the 9.557 mhz pixel clock is used), then each line consists of 320 + 20 = 340 pixel clocks, and the refresh rate would be 9.557 mhz (340 240) = 117.1 hz. if the refresh rate is marginal for the lcd size in cga graphics mode, a 50% increase in refresh rate can be achieved by using hga graphics mode. on the lansc300 microcontroller, the selection of cga or hga mode can remain independent of the resolution. (this is discussed later in this document.) dc voltage biasing dc voltage biasing is a condition of lcd panels when the liquid crystals in the display become permanently aligned. normally, the liquid crystals are nonaligned, al- lowing light to pass through the display. when a dc voltage is applied, the liquid crystals align themselves, blocking the light from passing through the display. the effect of this alignment causes a pixel to appear dark on the display. as a panel becomes dc voltage biased, the liquid crystals in the display become permanently aligned, eventually causing the entire display to appear black. ac modulation (defined in the next section) is used to prevent dc biasing. lcd panel ac modulation (m) all lcd panels implement what is known as ac modu- lation to prevent dc voltage biasing from damaging the display. ac modulation is accomplished by periodically reversing the polarity of the dc voltage that is applied to the liquid crystals. this prevents the crystals from becoming permanently aligned. some panels control the frequency at which the polarity is reversed inter- nally. other panels require an outside source to control this. for panels requiring an outside source to imple- ment this control, the lansc300 microcontroller sup- plies an ac modulation signal, m. this signal can be programmed to change state once per frame, once every 13 line clocks, or once every 61 line clocks.
configuring the lan?sc300 devices internal cga controller for a specific lcd panel 3 gray shading (gray scaling) gray shading is a way of representing colors on a monochrome lcd display using shades of gray. the irgb color information for each pixel is used to deter- mine which gray shading algorithm will be used to dis- play that pixel. the gray shading algorithm can be thought of as the duty cycle for displaying a particular pixel. for example, on the lansc300 microcontroller, an irgb value of 1011 corresponds to a 1/3 duty cycle. this means that, if a pixel is supposed to be displayed, it would be displayed once for every three times the screen is refreshed. refer to table 3 on page 6 for a list of the lansc300 microcontrollers irgb values and their corresponding gray shading duty cycles. lansc300 microcontroller extensions to the cga and hga standards cga standard the cga standard was defined for a color crt monitor with a resolution of 640 x 200 pixels. the cga stan- dard defines two graphic resolutions: 1. 640 x 200 pixels, with two colors, represented by 1bpp. 2. 320 x 200 pixels, with four colors, represented by 2 bpp. in 320 x 200 mode, each pixel in the x di- mension is displayed twice. for both 640 x 200 and 320 x 200 resolutions, the memory is divided into two 8-kbyte banks. pixel data for even-numbered display rows (starting with 0) are stored in bank 0, address range b8000Cb9fff. pixel data for odd-numbered display rows are stored in bank 1, address range ba000Cbbfff. the graphics mode section of chapter 3 in the lan tm sc300 microcontrol- ler programmers reference manual helps illustrate this. in text mode, 16 colors are available for characters. text mode is discussed in detail in chapter 3 of the lan tm sc300 microcontroller programmers reference manual and follows the cga standard implementation; therefore, it will not be discussed in detail in this docu- ment. how the lansc300 microcontroller deviates from the cga standard the lansc300 microcontroller can support any com- bination of resolutions at either 1 or 2 bpp (two or four colors), provided the video sram requirements do not exceed 32 kbyte. for memory requirements greater than 16 kbyte, the lansc300 microcontroller can be programmed to use three, or even all four, of the 8- kbyte banks of video sram. if all four banks are used: n the pixel data for display rows 0, 4, 8,... are in bank 1 (address range b8000Cb9fff). n the pixel data for display rows 1, 5, 9,... are in bank 2 (address range ba000Cbbfff). n the pixel data for display rows 2, 6, 10,... are in bank 3 (address range bc000Cbdfff). n the pixel data for display rows 3, 7, 11,... are in bank 4 (address range be000Cbffff). note that two banks are the minimum. thus, even if the pixel data for a small lcd screen could fit in 8 kbyte (for example, 320 x 200 in 2-color mode), two banks must still be used. in 4-color graphics mode (2 bpp), it is possible to se- lect whether or not pixels are doubled in the x dimen- sion. (in the cga standard, the pixel doubling is automatic in 4-color graphics mode.) if the lansc300 microcontroller graphics control is set to display 2-bpp graphics (port 3d8h bit 4 = 0), and if video index 20h bit 5 = 0, two pixels are displayed, effectively cutting the horizontal resolution in half. if video index 20h bit 5 = 1, only one pixel is displayed. in cga text mode, the lansc300 microcontroller gets its fonts from sram rather than rom and can support multiple font areas. the character width is fixed at eight pixels, but the character height is programmable. the way the font areas are addressed is discussed in detail in chapter 3 of the lan tm sc300 microcontroller pro- grammers reference manual . hga standard the hga standard was defined for a high-resolution, monochrome crt with a resolution of 720 x 348 pixels. in graphics mode, this allows two colors (black and white) represented by 1 bpp. the standard implemen- tation is to use four 8-kbyte banks of video sram in the same way the lansc300 microcontroller handles the four-bank cga configuration. in the case of hga, the standard address range for bank 1 is b0000C b1fff, for bank 2 it is b2000Cb3fff, for bank 3 it is b4000Cb5fff, and for bank 4 it is b6000Cb7fff. the hga standard also supports a second 32-kbyte dis- play page at b8000. in text mode, three character colors are available: black, light gray, and white. how the lansc300 microcontroller deviates from the hga standard the lansc300 microcontroller can support any com- bination of resolutions, provided the video sram re- quirements do not exceed 32 kbyte. for memory requirements of 16 kbyte or less, the lansc300 mi- crocontroller can be configured to use only two 8-kbyte banks of memory. for memory requirements of 16C 24 kbyte, the lansc300 microcontroller can be con- figured to use only three 8-kbyte banks of memory.
4 configuring the lan?sc300 devices internal cga controller for a specific lcd panel although the hga standard supports two 32-kbyte dis- play pages, only 32 kbyte of video sram are available on the lansc300 microcontroller. therefore, the lansc300 microcontroller will only allow access to b0000Cb7fff in hga mode. in hga text mode, the lansc300 microcontroller gets its fonts from sram rather than rom. the character width is fixed at nine pixels (the 9th column being auto- matically generated), but the character height is pro- grammable. chapter 3 of the lan tm sc300 microcontroller programmers reference manual de- tails the way the font areas are addressed. memory map organization for various display modes and panel sizes it is important to understand which settings affect the memory map of the video sram. this will enable you to properly display information on the screen. chapter 3 of the lan tm sc300 microcontroller programmers reference manual explains the memory map for text mode, how fonts should be set up, and how character and attribute bytes are organized. it also explains memory maps for a few different display sizes for graphics modes. this section expands on the informa- tion found in the lan tm sc300 microcontroller pro- grammers reference manual . it is meant to show how screen size and number of banks of video memory bits per pixel (graphics) and font size (text) affect the display data memory area. text mode in text mode, the display data area is 16 kbyte (for cga, b8000hCbbfffh and for hga, b0000hC b3fffh). some of the remaining 16 kbyte of the dis- play area are used for four different font areas, three of which are available in cga text mode and one of which is available in hga text mode. refer to section 3.4 text mode, in the lan tm sc300 micro- controller programmers reference manual , for text mode memory map examples. graphics mode in graphics mode, the video sram memory map is de- termined by the lcd resolution programmed into the lansc300 microcontroller, the number of banks of memory selected, and the number of bits per pixel re- quired. refer to section 3.3, graphics mode, in the lan tm sc300 microcontroller programmers refer- ence manual , for graphics mode memory map exam- ples. in graphics mode, the video sram memory is split into 8-kbyte banks. either two or four 8-kbyte banks are used. refer to "steps for determining if a single- screen lcd panel can be driven by the lansc300 microcontroller" on page 7 to determine how many banks are needed. the display rows are split evenly across the banks, as illustrated in the tables on the fol- lowing page. the number of bits per pixel and the programmed screen width determine how many bytes of data per row are needed. for example, a 128-pixel-wide screen, at 2 bpp needs 2 128 = 256 bits of data per row, and 256 8 = 32 bytes of data per row. at 2 bits per pixel, each pixel can be set to one of four colors. a 128-pixel- wide screen at 1 bpp needs 1 128 = 128 bits of data per row, and 128 8 = 16 bytes of data per row. at 1 bpp, each pixel can be set to only one of two colors. thus, more colors require more memory. note: with smaller panels, it may be necessary to pro- gram the lansc300 microcontrollers graphics con- troller with a logical screen width greater than the physical screen width of the lcd panel to meet the panels refresh rate requirements. reminder: if this is done, it is the logical screen width programmed into the graphics controller that determines the number of bytes per row. the following tables illustrate the memory map for a 128 x 128 pixel display set up for 2 bpp, in both a two-bank and four-bank configuration. as shown in the tables, a 128-pixel-wide display at 2 bpp re- quires 32 bytes of memory per row. if the width of the display were to increase or decrease, the change would cause the row ending address and subsequent starting addresses to increase or de- crease, respectively.
configuring the lan?sc300 devices internal cga controller for a specific lcd panel 5 table 1. memory map of 128 x 128 display using two banks in graphics mode table 2. memory map of 128 x 128 display using four banks in graphics mode row starting address display row row ending address bank 1 (b8000Cb9fff) b8000 0 b801f b8020 2 b803f b8040 4 b805f ... ... ... b87e0 126 b87ff bank 2 (ba000Cbbfff) ba000 1 ba01f ba020 3 ba03f ba040 5 ba05f ... ... ... ba7e0 127 ba7ff row starting address display row row ending address bank 1 (b8000Cb9fff) b8000 0 b801f b8020 4 b803f b8040 8 b805f ... ... ... b83e0 124 b83ff bank 2 (ba000Cbbfff) ba000 1 ba01f ba020 5 ba03f ba040 7 ba05f ... ... ... ba3e0 125 ba3ff bank 1 (bc000Cbcfff) bc000 2 bc01f bc020 6 bc03f bc040 10 bc05f ... ... ... bc3e0 126 bc3ff bank 2 (be000Cbefff) be000 3 be01f be020 7 be03f be040 11 be05f ... ... ... be3e0 127 be3ff
6 configuring the lan?sc300 devices internal cga controller for a specific lcd panel how the lansc300 microcontroller displays colors as gray shades the lansc300 microcontroller uses gray shading to represent colors on a monochrome lcd panel. it does this by associating a duty cycle with a particular irgb color value (see table 3). a duty cycle of x y indicates that for every y times the lcd display is refreshed, the pixel will be displayed x times. video index 19h, bit 4 enables color mapping for cga mode. this allows the mapping of one irgb/gray scale value to another irgb/gray scale value that looks bet- ter for a particular lcd. in this way, applications that use colors that do not look good on a particular display can still be used without having to change the applica- tion. single-screen lcd support a number of factors, including physical properties and mode of operation, determine whether or not the lansc300 microcontroller is capable of driving a spe- cific display. physical properties n 4-bit data interface the display to be driven must have 4 data lines to connect to the lansc300 microcontrollers lcdd3Clcdd0 n panel resolution the resolution, combined with the mode of opera- tion described in the next section, determines the rate at which the lansc300 microcontroller will re- fresh the display, as well as the amount of video sram used (the lansc300 microcontroller sup- ports a maximum of 32 kbyte of video sram). the video sram becomes a limiting factor for support- ing the display only when a graphics mode is used. n refresh rate the rate at which the lansc300 microcontroller re- freshes the display is affected by the mode of oper- ation as well as the panel resolution. if a panels refresh rate is not specifically stated, a maximum value can be approximated by taking: 4 ((shift clock period) (display resolution)) the 4 comes from the number of pixel data bits per shift clock. on the lansc300 microcontroller, this number must be 4. for example, a 320 x 240 display that has a minimum shift clock period of 125 ns, will have a maximum refresh rate of 4 (125 ns 320 240) = 416 hz. a typical refresh value is around 75 hz. a value less than 60 hz will probably yield unacceptable results (e.g., the screen will appear very dim or will blink). table 3. color codes mapped to pixel duty cycles color irgb/gray scale duty cycle common denominator black 0000 0 0/24 blue 0001 1/8 3/24 green 0010 1/2 12/24 cyan 0011 2/3 16/24 red 0100 1/3 8/24 magenta 0101 3/8 9/24 brown 0110 3/4 18/24 light gray 0111 7/8 21/24 dark gray 1000 1/6 4/24 light blue 1001 1/4 6/24 light green 1010 5/6 20/24 light cyan 1011 3/4 18/24 light red 1100 1/2 12/24 light magenta 1101 2/3 16/24 yellow 1110 7/8 21/24 white 1111 1 24/24
configuring the lan?sc300 devices internal cga controller for a specific lcd panel 7 mode of operation the mode of operation affects the refresh rate of the display, and when a graphics mode is selected, deter- mines the amount of video sram required. when the lansc300 microcontroller is configured for a graphics mode, the 32 kbyte of memory is divided into four 8- kbyte banks. video index register 09h controls whether the display information is divided between just two or all four of the memory banks. n cga mode when cga mode is selected, the lansc300 mi- crocontroller uses a pixel clock frequency of 9.557 mhz. the refresh rate for text mode, or 2- color graphics mode can be calculated by dividing the pixel clock frequency by the screen resolution programmed into the video controller, taking into ac- count the 20 extra pixel clocks per line mentioned earlier. the refresh rate for 4-color graphics mode will be half that value. n hga mode when hga mode is selected, the lansc300 mi- crocontroller uses a pixel clock frequency of 14.336 mhz. the refresh rate for text mode or 2- color graphics mode can be calculated by dividing the pixel clock frequency by the screen resolution programmed into the video controller, taking into ac- count the 20 extra pixel clocks per line mentioned earlier. steps for determining if a single-screen lcd panel can be driven by the lansc300 microcontroller 1. does the panel have a 4-bit data interface? C yes: go to step 2. C no: panel cannot be driven by the lansc300 microcontroller. 2. determine what rate the lansc300 microcontroller will refresh the lcd panel. refresh rate is a factor of the lcd panel resolution and pixel clock fre- quency, which is determined by the mode of opera- tion. for a panel size of w x h, and a bits-per-pixel value of bpp (1 or 2), the refresh rate will be as fol- lows: (pixel clock frequency) ((w + 20) bpp h) in cga mode, the pixel clock frequency is 9.557 mhz. in hga mode the pixel clock frequency is 14.336 mhz. therefore, when the lansc300 mi- crocontroller is configured for a 320 x 240, 1-bpp resolution lcd in cga mode, the refresh rate is 9.557 mhz (340 1 240) = 117 hz. when the lansc300 microcontroller is configured for the same size display in hga mode, the refresh rate is 14.336 mhz (340 1 240) = 175 hz. note that 2- color (1 bpp) mode can be supported by either cga or hga, but the hga refresh rate is approxi- mately 50% higher. 3. does the refresh rate fall in the range supported by the lcd panel? C yes: go to step 4. C no: panel cannot be driven by the lansc300 microcontroller. note: if the refresh rate driven by the lansc300 mi- crocontroller is too fast for the panel, it is possible to ef- fectively slow the refresh rate to the panel by programming the lansc300 microcontrollers graph- ics controller using a logical panel width that is greater than the physical lcd panel width. if this is done, the logical panel width must be used for all calculations, and it should first be tested on the same panel before making the design choice. this will determine if the panel can handle the additional shift clocks sent to it as a result of the larger panel width. 4. does the lansc300 microcontroller support the lcd panels video sram requirements? this is a concern only if the lcd will be operated in a graphics mode; therefore, text mode is not dis- cussed. 2 bits per pixel (four shades of gray) this mode consumes the most memory. each bank of memory is 8 kbyte (8192 bytes). in 2 bpp mode, each byte contains the equivalent of 4 pixels of in- formation. each bank can store information for 32,768 pixels. therefore, if configured for 4 banks of memory, the maximum number of pixels that the lansc300 microcontroller can support is 4 32,768 = 131,072 pixels. if configured for two banks of memory, the maximum number of pixels that the lansc300 microcontroller can support is 2 32,768 = 65,536 pixels. for example: a 320 x 240 lcd display has 320 240 = 76,800 pixels. therefore, the lansc300 microcontroller will support this resolu- tion lcd if configured for four banks of memory. 1 bit per pixel (2 shades of gray) each bank of memory is 8 kbyte (8192 bytes). in 1 bpp mode, each byte contains the equivalent of 8 pixels of information. each bank can store informa- tion for 65,536 pixels. therefore, if configured for four banks of memory, the maximum number of pix- els that the lansc300 microcontroller can support is 4 65,536 = 262,144 pixels. if configured for two banks of memory, the maximum number of pixels
8 configuring the lan?sc300 devices internal cga controller for a specific lcd panel that the lansc300 microcontroller can support is 2 65,536 = 131,072 pixels. for example: a 640 x 400 lcd display has 640 400 = 256,000 pixels. therefore the lansc300 microcontroller will support this resolu- tion lcd if configured for four banks of memory. 5. if the lcd panel meets the criteria listed in the pre- vious four steps, then the lansc300 microcontrol- ler is capable of driving the lcd panel. programming the lansc300 microcontroller to work with a single-screen lcd panel before programming the lansc300 microcontroller to work with a single-screen lcd panel, the following in- formation is needed: n display resolution in pixels, w x h (e.g., 640 x 200) n mode of operation (i.e., cga graphics-1 bpp, cga graphics-2 bpp, cga text, hga graphics-1 bpp, hga text) n if text mode, the font size (8 x fh for cga or 9 x fh for hga, where fh = font height; 8 x 8 is cga stan- dard, 9 x 14 is hga standard) n if graphics mode, the number of 8-kbyte banks of memory (see "steps for determining if a single- screen lcd panel can be driven by the lansc300 microcontroller" on page 7) determine the video index values to be programmed first determine the video index values for video in- dexes 00 C 0fh, based on the information listed in the four items above. cga & hga graphics mode values n (ht = w bpp 16) the horizontal total register (index 00h) and hor- izontal displayed register (index 01h) are pro- grammed with the number of 16-bit words per display row. in 2-color mode (1 bpp), this equals the width of the display in pixels divided by 16. in 4- color mode (2 bpp), this equals two times the width of the display in pixels divided by 16. for example, a 320 x 240 display is 320 pixels wide. therefore, in 2-color mode (1 bpp), ht = 320 16 = 20 (14h). n (vt = h banks) the vertical total register (index 04h), vertical display register (index 06h), and vertical sync po- sition register (index 07h) are programmed with the value of the height of the display in pixels, di- vided by the number of banks of memory. for exam- ple, a 320 x 240 display is 240 pixels high. if four banks of memory are going to be used, then vt = 240 4 = 60 (3ch). n (msl = banks C 1) the max scan line register (index 09h) is pro- grammed with the number of banks of memory to be used, minus 1. if four banks of memory are going to be used, then msl = 4 C 1 = 3. n (sah) (sal) the start address high (index 0ch) and start ad- dress low (index 0dh) video indexes together form a 14-bit offset (bits 7 and 6 of index 0ch are not used) that determines the location in video memory where the video controller will start fetching data to be displayed on the screen. typically, these indexes will be set to 0 so the display data starts being fetched from b8000h. scrolling can be imple- mented by changing the values in these registers. n all the other index registers (02, 03, 05, 08, 0ah, 0bh, 0eh, 0fh) will be programmed with 0h. cga & hga text mode values n ht = w bpp 16 the horizontal total register (index 00h) and hor- izontal displayed register (index 01h) are pro- grammed with the number of characters per row. the character width is hard coded to be 8 pixels wide. therefore, ht is the width of the display in pix- els divided by 8. for example, a 320 x 240 display is 320 pixels wide. therefore ht = 320 8 = 40 (28h). n (vt = h y) the vertical total register (index 04h), vertical displayed register (06h), and vertical sync posi- tion register (07h) are programmed with the value of the number of rows of characters. this is deter- mined by the height of the display in pixels, divided by the height of the character in pixels (y from the equation below). for example, a 320 x 240 display is 240 pixels high. if using an 8 x 10 font, then vt = 240 10 = 24 (18h). n (msl = y C1) the max scan line register (index 09h) is pro- grammed with the pixel height of the font C 1. for example, if using an 8 x 10 font, then msl = 10C1=9.
configuring the lan?sc300 devices internal cga controller for a specific lcd panel 9 n (cs = cursor start row C1) (ce = cursor end row C1) the cursor start register (index 0ah), and cursor end register (index 0bh) define the pixel rows within a font where the cursor will be displayed. typ- ically, the cursor is defined to be near the bottom of the character matrix. for example, an 8 x 10 font has 10 pixel rows. therefore, to have the cursor po- sitioned at rows 8 and 9, cs = 8 C 1 = 7, and ce = 9 C 1 = 8. note: bits 6 and 5 of the cursor start register (index 0ah) control the cursors behavior. see table 4. n (sah) (sal) the start address high (index 0ch) and start ad- dress low (index 0dh) video indexes together form a 14-bit offset (bits 7 and 6 of index 0ch are not used) that determines the location in video memory where the video controller will start fetching data to be displayed on the screen. typically, these indexes will be set to 0 so the display data starts being fetched from b8000h. scrolling can be imple- mented by changing the values in these registers. n (cah) (cal) cursor address high (index 0eh) and cursor ad- dress low (index 0fh) video indexes together form a 14-bit offset (bits 7 and 6 of index 0ch are not used) that determines the location in video memory where the video controller will display the cursor when the corresponding video data is displayed on the screen. for example, if sah = 0, sal = 0, cah = 0, and cal = 0, the cursor will be displayed in the upper left corner of the screen. n all the other index registers (02, 03, 05, 08, 0ah, 0bh, 0eh, 0fh) will be programmed with 0h. initializing the video controller the following sequences show the proper sequence for initializing the video controller. the following steps assume the video controller is set up to its default mode of cga and the video index registers are unlocked. (to unlock the video registers, write 12h to port 3d4h, and read port 3d5h with no i/o cycles between these.) note: only the minimum set of registers required to get the screen running are initialized. there are a num- ber of additional features such as auto screen blanking and text truncation that are discussed in the lan ? sc300 microcontroller programmers reference manual that are not reiterated in this document. cga graphics the video index registers are accessed by writing the register index to port 3d4h, and then writing or reading the register data to or from port 3d5h. 1. set video index 18h = 50h C sets up lcd panel type to single screen (bits 7 and 6) C sets display type to lcd (bit 4) 2. set video index 00h = ht 3. set video index 01h = ht 4. set video index 02h = 0 5. set video index 03h = 0 6. set video index 04h = vt 7. set video index 05h = 0 8. set video index 06h = vt 9. set video index 07h = vt 10.set video index 08h = 0 11. set video index 09h = msl 12.set video index 0ah = 0 13.set video index 0bh = 0 14.set video index 0ch = sah 15.set video index 0dh = sal 16.set video index 0eh = 0 17.set video index 0fh = 0 18.set video index 20h (bit 5 controls dot doubling) C if 2 bpp graphics mode is used, set bit 5 = 1 to disable dot doubling. note: this is the common setting. C if 2 bpp graphics mode is used, and dot dou- bling is desired (cga standard), then set bit 5 = 0. 19.if color mapping is going to be used: C set video indexs 14hC17h and 1chC1fh accordingly C set video index 19h = 10h 20.set video port 3d8h C if 2 bpp graphics mode, set to 0ah C if 1 bpp graphics mode, set to 1ah 21.set video port 3d9h C set colors accordingly (see the register descrip- tion in the lan tm sc300 microcontroller pro- grammers reference manual ) table 4. cursor control bits (index 0ah) bit 6 bit 5 cursor behavior 0 0 no blinking 0 1 cursor not displayed 1 0 blinking with 16 refresh rate 1 1 blinking with 32 refresh rate
10 configuring the lan?sc300 devices internal cga controller for a specific lcd panel cga text the video index registers are accessed by writing the register index to port 3d4h and then writing or reading the register data to or from port 3d5h. 1. set video index 18h = 50h C sets up lcd panel type to single screen (bits 7 and 6) C sets display type to lcd (bit 4) 2. set video index 00h = ht 3. set video index 01h = ht 4. set video index 02h = 0 5. set video index 03h = 0 6. set video index 04h = vt 7. set video index 05h = 0 8. set video index 06h = vt 9. set video index 07h = vt 10.set video index 08h = 0 11. set video index 09h = msl 12.set video index 0ah = cs 13.set video index 0bh = ce 14.set video index 0ch = sah 15.set video index 0dh = sal 16.set video index 0eh = cah 17.set video index 0fh = cal 18.if color mapping is going to be used: C set video indexes 14hC17h and 1chC1fh accordingly C set video index 19h = 10h 19.set video port 3d8h = 08h C enable text mode 20.set video port 3d9h C set colors accordingly (see the register descrip- tion in the lan tm sc300 microcontroller pro- grammers reference manual ) hga graphics initially, the video index registers are accessed by writ- ing the register index to port 3d4h, and then writing or reading the register data to or from port 3d5h. this oc- curs until the controller is switched to hga mode. after this occurs, port 3b4 is used for the index and port 3b5 is used for the data. 1. set video index 18h = 51h (use ports 3d4 and 3d5) C sets graphics mode to hga (from now on use ports 3b4 and 3b5) C sets up lcd panel type to single screen (bits 7 and 6) C sets display type to lcd (bit 4) 2. set video index 00h = ht 3. set video index 01h = ht 4. set video index 02h = 0 5. set video index 03h = 0 6. set video index 04h = vt 7. set video index 05h = 0 8. set video index 06h = vt 9. set video index 07h = vt 10.set video index 08h = 0 11. set video index 09h = msl 12.set video index 0ah = 0 13.set video index 0bh = 0 14.set video index 0ch = sah 15.set video index 0dh = sal 16.set video index 0eh = 0 17.set video index 0fh = 0 18.set video port 3bfh = 01h C master enable for graphics mode 19.set video port 3b8h = 0ah C enable graphics mode C enable video display
configuring the lan?sc300 devices internal cga controller for a specific lcd panel 11 hga text initially, the video index registers are accessed by writ- ing the register index to port 3d4h, and then writing or reading the register data to or from port 3d5h. this oc- curs until the controller is switched to hga mode. after this occurs, port 3b4 is used for the index and port 3b5 is used for the data. 1. set video index 18h = 51h (use ports 3d4 and 3d5) C sets graphics mode to hga (from now on use ports 3b4 and 3b5) C sets up lcd panel type to single screen (bits 7 and 6) C sets display type to lcd (bit 4) 2. set video index 00h = ht 3. set video index 01h = ht 4. set video index 02h = 0 5. set video index 03h = 0 6. set video index 04h = vt 7. set video index 05h = 0 8. set video index 06h = vt 9. set video index 07h = vt 10.set video index 08h = 0 11. set video index 09h = msl 12.set video index 0ah = cs 13.set video index 0bh = ce 14.set video index 0ch = sah 15.set video index 0dh = sal 16.set video index 0eh = cah 17.set video index 0fh = cal 18.set video port 3bfh = 00h C master disable for graphics mode 19.set video port 3b8h = 08h C enable video display dual-screen lcd support the lansc300 microcontroller supports only one type of dual-screen lcd display. the display must be 640 x 200 (640 x 100 per panel). the display must accept 8 data bits total (4 data bits per panel). the lansc300 microcontroller will support the panel in cga mode only and refresh the display at a rate of approximately 75 hz. the reason for the limited dual-screen support is that the lansc300 microcontroller does not have any dual-screen registers that, among other things, allow you to program where the fetching of data for the lower panel should begin. this was hard-wired in the lansc300 microcontroller. programming the lansc300 microcontroller for dual-screen lcd support the programming values for this dual-screen lcd are identical to the ones used for the single-screen panel with two exceptions. video index 18h bits 7 and 6 should be set to 00 instead of 01. the lansc300 mi- crocontroller configuration register b1h bit 1 must be set to 1 to enable the additional 4 lower-panel lcd data bits. the physical pin connections to the lansc300 microcontroller to connect an lcd panel to the lansc300 microcon- troller, the following pins need to be connected: lcdd3Clcdd0 : these are the panels data bits. lcdd3 is the msb; lcdd0 is the lsb. find out which data bit on the lcd is the msb, which is the lsb, and connect the pins accordingly. cp1 : also known as the line clock or latch (see defini- tion in "line clock (cp1)" on page 2). this should be connected to the equivalent line on the lcd panel. cp2 : also known as the shift clock or data shift (see definition in "shift clock (cp2)" on page 2). this should be connected to the equivalent line on the lcd panel. frm : also known as flm, or frame (see definition in "frame start (frm)" on page 2). this should be con- nected to the equivalent line on the lcd panel. m : ac modulation (see definition in "lcd panel ac modulation (m)" on page 2). some panels require this signal, others do not. connect this signal if appropriate. lcddl3Clcddl0 : these data bits are required only if a dual-screen lcd panel is being connected. these are the data bits for the lower panel. lcddl3 is the msb for the lower panel, and lcddl0 is the lsb for the lower panel. other lcd pin connections the other connections that need to be made to an lcd vary. for example: n contrast voltage : can be positive or negative, typ- ically about C22 volts. n +5 v n gnd n display enable : this is usually a simple 5-v enable signal that some panels require. this can easily be connected to one of the lansc300 microcontrol- lers pmc pins. n v ee : typically a voltage in the same range as the contrast voltage. refer to panel specifications.
12 configuring the lan?sc300 devices internal cga controller for a specific lcd panel using the lansc300 microcontroller evaluation board to test an lcd panel the lansc300 microcontroller evaluation board has a 20-pin header (p18) with all the lcd interface signals connected to it. the evaluation board provides a C14 v to C16 v contrast voltage (adjust using vr1) and a C17 v ee voltage. if the panel to be tested requires voltages other than these, a separate circuit will need to be bread boarded, or an external dc power supply used. the following evaluation board jumpers and resistor packs should also be set to configure the evaluation board for internal video mode: jp16 = 1C2; jp18 = open; install rp3 and rp4 (rp1, rp2, rp5, and rp6 must be empty). note that the evaluation board bios is set up to config- ure for a 640 x 200 single-panel display when the lansc300 microcontroller is in internal video mode. if a panel size other than this is used without modifying the bios, the screen may not display anything at boot- up. refer to "lcd development tips and tricks" for in- structions on how to use ctty for console activity while developing a screen application. also note that if a dual-screen lcd panel is used, the sbhe , irq14, mcs16, and ios16 isa signals are no longer available outside the chip. this means the stan- dard 16-bit ide interface cannot be used. table 5 shows how the pins on the 20-pin header should be connected to the pins of a hitachi lmg6272xnfr, 640 x 200 single-panel display. table 5. pin connections the lansc300 microcontroller evaluation board p18 header pins hitachi: lmg6272xnfr 640 x 200 single panel lcd pin # pin name function pin # pin name function 1 vcclcd5 +5 = 10 vdd power supply for logic circuit 2 gnd ground = 11 vss ground 3 lcdfrm frame start = 5 flm the flm signal indicates the start of each display cycle 4 lcdcp1 line clock = 7 cl1 data latch 5 lcdcp2 shift clock = 8 cl2 data shift 6 lcdm ac modulation x not used 7 lcdd0 data bit 0 (lsb) = 1 d0 data bit 0 (lsb) 8 lcdd1 data bit 1 = 2 d1 data bit 1 9 lcdd2 data bit 2 = 3 d2 data bit 2 10 lcdd3 data bit 3 (msb) = 4 d3 data bit 3 (msb) 11 lcddl0 dual-screen panel data bit 0 for lower panel x not used 12 lcddl1 dual-screen panel data bit 1 for lower panel x not used 13 lcddl2 dual-screen panel data bit 2 for lower panel x not used 14 lcddl3 dual-screen panel data bit 3 for lower panel x not used 15 contrast adjustable voltage between C14 v to C16 v = 9 vo lcd driving voltage 16 vee C17 v = 12 vee power supply for lc driving 17 20 nc not connected
configuring the lan?sc300 devices internal cga controller for a specific lcd panel 13 lcd development tips & tricks use ctty for console i/o when using an lcd as the console device under dos, there may be problems debugging the lcd because dos will also be attempting to write to the lcd through the bios. a way around this is by diverting the dos console i/o through the serial port. this allows use of debug or other application programs to access the lansc300 microcontrollers registers and view the re- sults on the lcd display. the following steps are rec- ommended: 1 connect a null modem cable between com1 on the lansc300 microcontroller and a pc running pro- comm or other terminal program. (a lap link serial cable is a null modem cable). 2. on the pc running procomm, set up for a direct connect to the serial port, running 9600 baud, 8 data, 1 stop bit, and no parity. set it up for a terminal type of either tty or ansi-bbs. 3. on the lansc300 microcontroller system, boot dos and have the following commands in the autoexec.bat file: C mode com1 9600,n,8,1 Cctty com1 4. after the system boots, the dos prompt will be vis- ible on the pc running procomm. 5. executing programs that use the console i/o such as debug should be possible. 6. programs that talk directly to video memory will dis- play the output on the lansc300 microcontroller system, but the keyboard input will come from the pc running procomm. 7. below are two things to keep in mind: C to debug an lcd, the lansc300 microcontrol- ler evaluation board should be configured for in- ternal video mode C if using phoenix bios, the bios will lock the video index registers. remember to unlock them by reading video index 12h. the bios will also lock the upper 16k of display memory, which is used for font storage in text mode. this can be unlocked by clearing bit 3 of video index 20h. the bios may also be updating the screen if using the lansc300 microcontroller evaluation board with an lcd standalone, (i.e., not option 1 above) and booting to dos, note that the bios is ac- cessing the video registers every time it is called to up- date the screen (i.e., typing in debug or from the dos prompt). if trying to use debug or other programs to modify the video registers, be aware that they may be modified by the bios as well, specifically ports 3d8h and 3d9h. using standard cga or hga drivers on a nonstandard display size it is possible to use standard cga or hga drivers on a nonstandard-sized screen. the method is to program the lansc300 microcontroller with values for the lcd width that match those that the driver expects. the lcd height can be set to the actual lcd height. this will cause the video sram to be organized as the stan- dard driver is expecting. the lcd panel will be display- ing the upper left of a virtual screen. trademarks copyright ? 1997 advanced micro devices, inc. all rights reserved. amd, the amd logo, combinations thereof, and lan are trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
publication# 20749 rev: a amendment/ 0 issue date: june 1997 this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. configuring the lan ? sc300 devices internal cga controller for a specific lcd panel application note this application note explains how to determine if a specific lcd panel is supported by the lan tm sc300 microcontroller, and in what modes (cga two-color or four-color graphics, cga text, hga graphics, hga text); how to configure the lansc300 microcontroller to work with the lcd panel in those modes; and which signals need to be connected to the lansc300 microcontroller to properly drive the panel. introduction there are a number of factors that need to be under- stood to accomplish the tasks mentioned above. the sections in the first part of this document provide you with the understanding and background needed to fol- low the procedures beginning on page 7. you are also encouraged to read and have available for reference chapter 3, video controller of the lan tm sc300 mi- crocontroller programmers reference manual , order #18470. definitions the following terms are used throughout this docu- ment. understanding these terms as they apply to the lansc300 microcontroller is essential for understand- ing how to configure the microcontrollers video index registers to work with various lcd panels. single-screen panels a single-screen lcd panel consists of the liquid crys- tal display (lcd) and a set of column drivers (also known as segment drivers) and row drivers (also called common drivers). these drivers supply the appropriate dc voltage to the liquid crystals in the display such that the crystals become aligned and block the light from passing through the display. an entire row of pixels is biased at one time. for this to occur, the pixel data for one row is loaded into the segment drivers. then, a dc voltage is applied to the segment drivers and to the common driver that is attached to the row being dis- played. this process is then repeated for each row of the display. figure 1 is a simplified illustration of an lcd panel that can be driven by the lansc300 microcontroller. not all signals are shown (e.g., frm and m), and not all con- nections of existing signals are shown. as depicted in figure 1, the lansc300 microcontroller drives 4 bits of pixel data at a time. the data is clocked into the seg- ment drivers using the shift clock. when all the data for a row of pixels is loaded into the segment drivers, the line clock will pulse, causing the common driver to ac- tivate the voltage to the common line for the row of pixels being displayed. dual-screen panels a dual-screen lcd panel is two single-screen panels glued so tightly together that they appear to be one panel. each panel has separate data bits but shares the same control signals: shift clock, line clock, and frame start (see the sections that follow). for example, a 640 x 200 dual-screen panel is actually two 640 x 100 single-screen panels glued together. the only dual-screen panel resolution the lansc300 microcontroller supports is 640 x 200. more specific in- formation as to how the lansc300 microcontroller handles a dual-screen panel is discussed later in this document. figure 1. simplified lcd panel configuration
2 configuring the lan?sc300 devices internal cga controller for a specific lcd panel pixel clock this is the standard unit of measure from which all of the lcd clocking signals can be derived. the pixel clock can be loosely defined as the rate at which pixels are displayed on the screen. on the lansc300 micro- controller, the pixel clock used is one of two fixed fre- quencies: 14.336 mhz for hga mode or 9.557 mhz (which is 2/3 of 14.336) for cga mode. on the lansc300 microcontroller, the pixel clock is internal to the video controller and is not available external to the chip. shift clock (cp2) the shift clock, known as the cp2 signal on the lansc300 microcontroller, tells the lcd panel when data is valid on the lcd data bus (the lansc300 mi- crocontroller pins lcdd0Clcdd3 and lcddl0C lcddl3). data is valid on the falling edge of shift clock. the frequency of the shift clock can be determined by the pixel clock frequency divided by the number of data bits per panel. for both single- and dual-screen panels with the lansc300 microcontroller, the number of bits per panel is four. therefore, the shift clock frequency will be either 14.336 mhz 4 data bits = 3.58 mhz, or 9.557 mhz 4 data bits = 2.389 mhz. line clock (cp1) the line clock, known as the cp1 signal on the lansc300 microcontroller, tells the lcd panel that a complete row (horizontal line) of pixel data has been sent to the lcd panel to be displayed. additional shift clocks indicate valid data for the next row of pixels (i.e., display the current row and prepare to receive pixel data for the next row). a line clock pulse will occur once for every row of pixel data sent to the lcd panel. for example, a 320 x 240 lcd screen has 240 rows; therefore, 240 line clocks will occur each time the panel is refreshed. when cp1 is asserted on the lansc300 microcontrol- lers lcd controller, there is a period of about 20 pixel clock cycles during which cp2 will not be asserted. this has a slight effect on the refresh rate as described later in this document. frame start (frm) frame start, known as frm on the lansc300 micro- controller, is asserted at the start of every frame (panel scan). this signal tells the lcd panel that the next data sent to it via the shift clock will be for the top row of the panel. this signal is sometimes referred to as the flm (first line marker) signal. on the lansc300 microcontrollers lcd controller, there is no dead time when frm is asserted. the frm assertion overlaps with the normal cp1 assertion at the end of the last line. refresh rate the refresh rate of the lcd panel is the number of times per second the screen is redrawn. this affects the crispness and brightness of the image on the dis- play. on the lansc300 microcontroller, the refresh rate is affected by the screen resolution programmed into the video controller, the number of bits per pixel (bpp) (in graphics mode only), and the pixel clock fre- quency. on the lansc300 microcontroller, the refresh rate for text mode or 2-color graphics mode can be calculated by dividing the pixel clock frequency by the screen res- olution programmed into the video controller, taking into account the 20 extra pixel clocks per line men- tioned in the previous section. the refresh rate for 4- color graphics mode will be half that amount. for ex- ample, if the controller is programmed for a 320 x 240 lcd screen and configured for cga 2-color mode (which means that the 9.557 mhz pixel clock is used), then each line consists of 320 + 20 = 340 pixel clocks, and the refresh rate would be 9.557 mhz (340 240) = 117.1 hz. if the refresh rate is marginal for the lcd size in cga graphics mode, a 50% increase in refresh rate can be achieved by using hga graphics mode. on the lansc300 microcontroller, the selection of cga or hga mode can remain independent of the resolution. (this is discussed later in this document.) dc voltage biasing dc voltage biasing is a condition of lcd panels when the liquid crystals in the display become permanently aligned. normally, the liquid crystals are nonaligned, al- lowing light to pass through the display. when a dc voltage is applied, the liquid crystals align themselves, blocking the light from passing through the display. the effect of this alignment causes a pixel to appear dark on the display. as a panel becomes dc voltage biased, the liquid crystals in the display become permanently aligned, eventually causing the entire display to appear black. ac modulation (defined in the next section) is used to prevent dc biasing. lcd panel ac modulation (m) all lcd panels implement what is known as ac modu- lation to prevent dc voltage biasing from damaging the display. ac modulation is accomplished by periodically reversing the polarity of the dc voltage that is applied to the liquid crystals. this prevents the crystals from becoming permanently aligned. some panels control the frequency at which the polarity is reversed inter- nally. other panels require an outside source to control this. for panels requiring an outside source to imple- ment this control, the lansc300 microcontroller sup- plies an ac modulation signal, m. this signal can be programmed to change state once per frame, once every 13 line clocks, or once every 61 line clocks.
configuring the lan?sc300 devices internal cga controller for a specific lcd panel 3 gray shading (gray scaling) gray shading is a way of representing colors on a monochrome lcd display using shades of gray. the irgb color information for each pixel is used to deter- mine which gray shading algorithm will be used to dis- play that pixel. the gray shading algorithm can be thought of as the duty cycle for displaying a particular pixel. for example, on the lansc300 microcontroller, an irgb value of 1011 corresponds to a 1/3 duty cycle. this means that, if a pixel is supposed to be displayed, it would be displayed once for every three times the screen is refreshed. refer to table 3 on page 6 for a list of the lansc300 microcontrollers irgb values and their corresponding gray shading duty cycles. lansc300 microcontroller extensions to the cga and hga standards cga standard the cga standard was defined for a color crt monitor with a resolution of 640 x 200 pixels. the cga stan- dard defines two graphic resolutions: 1. 640 x 200 pixels, with two colors, represented by 1bpp. 2. 320 x 200 pixels, with four colors, represented by 2 bpp. in 320 x 200 mode, each pixel in the x di- mension is displayed twice. for both 640 x 200 and 320 x 200 resolutions, the memory is divided into two 8-kbyte banks. pixel data for even-numbered display rows (starting with 0) are stored in bank 0, address range b8000Cb9fff. pixel data for odd-numbered display rows are stored in bank 1, address range ba000Cbbfff. the graphics mode section of chapter 3 in the lan tm sc300 microcontrol- ler programmers reference manual helps illustrate this. in text mode, 16 colors are available for characters. text mode is discussed in detail in chapter 3 of the lan tm sc300 microcontroller programmers reference manual and follows the cga standard implementation; therefore, it will not be discussed in detail in this docu- ment. how the lansc300 microcontroller deviates from the cga standard the lansc300 microcontroller can support any com- bination of resolutions at either 1 or 2 bpp (two or four colors), provided the video sram requirements do not exceed 32 kbyte. for memory requirements greater than 16 kbyte, the lansc300 microcontroller can be programmed to use three, or even all four, of the 8- kbyte banks of video sram. if all four banks are used: n the pixel data for display rows 0, 4, 8,... are in bank 1 (address range b8000Cb9fff). n the pixel data for display rows 1, 5, 9,... are in bank 2 (address range ba000Cbbfff). n the pixel data for display rows 2, 6, 10,... are in bank 3 (address range bc000Cbdfff). n the pixel data for display rows 3, 7, 11,... are in bank 4 (address range be000Cbffff). note that two banks are the minimum. thus, even if the pixel data for a small lcd screen could fit in 8 kbyte (for example, 320 x 200 in 2-color mode), two banks must still be used. in 4-color graphics mode (2 bpp), it is possible to se- lect whether or not pixels are doubled in the x dimen- sion. (in the cga standard, the pixel doubling is automatic in 4-color graphics mode.) if the lansc300 microcontroller graphics control is set to display 2-bpp graphics (port 3d8h bit 4 = 0), and if video index 20h bit 5 = 0, two pixels are displayed, effectively cutting the horizontal resolution in half. if video index 20h bit 5 = 1, only one pixel is displayed. in cga text mode, the lansc300 microcontroller gets its fonts from sram rather than rom and can support multiple font areas. the character width is fixed at eight pixels, but the character height is programmable. the way the font areas are addressed is discussed in detail in chapter 3 of the lan tm sc300 microcontroller pro- grammers reference manual . hga standard the hga standard was defined for a high-resolution, monochrome crt with a resolution of 720 x 348 pixels. in graphics mode, this allows two colors (black and white) represented by 1 bpp. the standard implemen- tation is to use four 8-kbyte banks of video sram in the same way the lansc300 microcontroller handles the four-bank cga configuration. in the case of hga, the standard address range for bank 1 is b0000C b1fff, for bank 2 it is b2000Cb3fff, for bank 3 it is b4000Cb5fff, and for bank 4 it is b6000Cb7fff. the hga standard also supports a second 32-kbyte dis- play page at b8000. in text mode, three character colors are available: black, light gray, and white. how the lansc300 microcontroller deviates from the hga standard the lansc300 microcontroller can support any com- bination of resolutions, provided the video sram re- quirements do not exceed 32 kbyte. for memory requirements of 16 kbyte or less, the lansc300 mi- crocontroller can be configured to use only two 8-kbyte banks of memory. for memory requirements of 16C 24 kbyte, the lansc300 microcontroller can be con- figured to use only three 8-kbyte banks of memory.
4 configuring the lan?sc300 devices internal cga controller for a specific lcd panel although the hga standard supports two 32-kbyte dis- play pages, only 32 kbyte of video sram are available on the lansc300 microcontroller. therefore, the lansc300 microcontroller will only allow access to b0000Cb7fff in hga mode. in hga text mode, the lansc300 microcontroller gets its fonts from sram rather than rom. the character width is fixed at nine pixels (the 9th column being auto- matically generated), but the character height is pro- grammable. chapter 3 of the lan tm sc300 microcontroller programmers reference manual de- tails the way the font areas are addressed. memory map organization for various display modes and panel sizes it is important to understand which settings affect the memory map of the video sram. this will enable you to properly display information on the screen. chapter 3 of the lan tm sc300 microcontroller programmers reference manual explains the memory map for text mode, how fonts should be set up, and how character and attribute bytes are organized. it also explains memory maps for a few different display sizes for graphics modes. this section expands on the informa- tion found in the lan tm sc300 microcontroller pro- grammers reference manual . it is meant to show how screen size and number of banks of video memory bits per pixel (graphics) and font size (text) affect the display data memory area. text mode in text mode, the display data area is 16 kbyte (for cga, b8000hCbbfffh and for hga, b0000hC b3fffh). some of the remaining 16 kbyte of the dis- play area are used for four different font areas, three of which are available in cga text mode and one of which is available in hga text mode. refer to section 3.4 text mode, in the lan tm sc300 micro- controller programmers reference manual , for text mode memory map examples. graphics mode in graphics mode, the video sram memory map is de- termined by the lcd resolution programmed into the lansc300 microcontroller, the number of banks of memory selected, and the number of bits per pixel re- quired. refer to section 3.3, graphics mode, in the lan tm sc300 microcontroller programmers refer- ence manual , for graphics mode memory map exam- ples. in graphics mode, the video sram memory is split into 8-kbyte banks. either two or four 8-kbyte banks are used. refer to "steps for determining if a single- screen lcd panel can be driven by the lansc300 microcontroller" on page 7 to determine how many banks are needed. the display rows are split evenly across the banks, as illustrated in the tables on the fol- lowing page. the number of bits per pixel and the programmed screen width determine how many bytes of data per row are needed. for example, a 128-pixel-wide screen, at 2 bpp needs 2 128 = 256 bits of data per row, and 256 8 = 32 bytes of data per row. at 2 bits per pixel, each pixel can be set to one of four colors. a 128-pixel- wide screen at 1 bpp needs 1 128 = 128 bits of data per row, and 128 8 = 16 bytes of data per row. at 1 bpp, each pixel can be set to only one of two colors. thus, more colors require more memory. note: with smaller panels, it may be necessary to pro- gram the lansc300 microcontrollers graphics con- troller with a logical screen width greater than the physical screen width of the lcd panel to meet the panels refresh rate requirements. reminder: if this is done, it is the logical screen width programmed into the graphics controller that determines the number of bytes per row. the following tables illustrate the memory map for a 128 x 128 pixel display set up for 2 bpp, in both a two-bank and four-bank configuration. as shown in the tables, a 128-pixel-wide display at 2 bpp re- quires 32 bytes of memory per row. if the width of the display were to increase or decrease, the change would cause the row ending address and subsequent starting addresses to increase or de- crease, respectively.
configuring the lan?sc300 devices internal cga controller for a specific lcd panel 5 table 1. memory map of 128 x 128 display using two banks in graphics mode table 2. memory map of 128 x 128 display using four banks in graphics mode row starting address display row row ending address bank 1 (b8000Cb9fff) b8000 0 b801f b8020 2 b803f b8040 4 b805f ... ... ... b87e0 126 b87ff bank 2 (ba000Cbbfff) ba000 1 ba01f ba020 3 ba03f ba040 5 ba05f ... ... ... ba7e0 127 ba7ff row starting address display row row ending address bank 1 (b8000Cb9fff) b8000 0 b801f b8020 4 b803f b8040 8 b805f ... ... ... b83e0 124 b83ff bank 2 (ba000Cbbfff) ba000 1 ba01f ba020 5 ba03f ba040 7 ba05f ... ... ... ba3e0 125 ba3ff bank 1 (bc000Cbcfff) bc000 2 bc01f bc020 6 bc03f bc040 10 bc05f ... ... ... bc3e0 126 bc3ff bank 2 (be000Cbefff) be000 3 be01f be020 7 be03f be040 11 be05f ... ... ... be3e0 127 be3ff
6 configuring the lan?sc300 devices internal cga controller for a specific lcd panel how the lansc300 microcontroller displays colors as gray shades the lansc300 microcontroller uses gray shading to represent colors on a monochrome lcd panel. it does this by associating a duty cycle with a particular irgb color value (see table 3). a duty cycle of x y indicates that for every y times the lcd display is refreshed, the pixel will be displayed x times. video index 19h, bit 4 enables color mapping for cga mode. this allows the mapping of one irgb/gray scale value to another irgb/gray scale value that looks bet- ter for a particular lcd. in this way, applications that use colors that do not look good on a particular display can still be used without having to change the applica- tion. single-screen lcd support a number of factors, including physical properties and mode of operation, determine whether or not the lansc300 microcontroller is capable of driving a spe- cific display. physical properties n 4-bit data interface the display to be driven must have 4 data lines to connect to the lansc300 microcontrollers lcdd3Clcdd0 n panel resolution the resolution, combined with the mode of opera- tion described in the next section, determines the rate at which the lansc300 microcontroller will re- fresh the display, as well as the amount of video sram used (the lansc300 microcontroller sup- ports a maximum of 32 kbyte of video sram). the video sram becomes a limiting factor for support- ing the display only when a graphics mode is used. n refresh rate the rate at which the lansc300 microcontroller re- freshes the display is affected by the mode of oper- ation as well as the panel resolution. if a panels refresh rate is not specifically stated, a maximum value can be approximated by taking: 4 ((shift clock period) (display resolution)) the 4 comes from the number of pixel data bits per shift clock. on the lansc300 microcontroller, this number must be 4. for example, a 320 x 240 display that has a minimum shift clock period of 125 ns, will have a maximum refresh rate of 4 (125 ns 320 240) = 416 hz. a typical refresh value is around 75 hz. a value less than 60 hz will probably yield unacceptable results (e.g., the screen will appear very dim or will blink). table 3. color codes mapped to pixel duty cycles color irgb/gray scale duty cycle common denominator black 0000 0 0/24 blue 0001 1/8 3/24 green 0010 1/2 12/24 cyan 0011 2/3 16/24 red 0100 1/3 8/24 magenta 0101 3/8 9/24 brown 0110 3/4 18/24 light gray 0111 7/8 21/24 dark gray 1000 1/6 4/24 light blue 1001 1/4 6/24 light green 1010 5/6 20/24 light cyan 1011 3/4 18/24 light red 1100 1/2 12/24 light magenta 1101 2/3 16/24 yellow 1110 7/8 21/24 white 1111 1 24/24
configuring the lan?sc300 devices internal cga controller for a specific lcd panel 7 mode of operation the mode of operation affects the refresh rate of the display, and when a graphics mode is selected, deter- mines the amount of video sram required. when the lansc300 microcontroller is configured for a graphics mode, the 32 kbyte of memory is divided into four 8- kbyte banks. video index register 09h controls whether the display information is divided between just two or all four of the memory banks. n cga mode when cga mode is selected, the lansc300 mi- crocontroller uses a pixel clock frequency of 9.557 mhz. the refresh rate for text mode, or 2- color graphics mode can be calculated by dividing the pixel clock frequency by the screen resolution programmed into the video controller, taking into ac- count the 20 extra pixel clocks per line mentioned earlier. the refresh rate for 4-color graphics mode will be half that value. n hga mode when hga mode is selected, the lansc300 mi- crocontroller uses a pixel clock frequency of 14.336 mhz. the refresh rate for text mode or 2- color graphics mode can be calculated by dividing the pixel clock frequency by the screen resolution programmed into the video controller, taking into ac- count the 20 extra pixel clocks per line mentioned earlier. steps for determining if a single-screen lcd panel can be driven by the lansc300 microcontroller 1. does the panel have a 4-bit data interface? C yes: go to step 2. C no: panel cannot be driven by the lansc300 microcontroller. 2. determine what rate the lansc300 microcontroller will refresh the lcd panel. refresh rate is a factor of the lcd panel resolution and pixel clock fre- quency, which is determined by the mode of opera- tion. for a panel size of w x h, and a bits-per-pixel value of bpp (1 or 2), the refresh rate will be as fol- lows: (pixel clock frequency) ((w + 20) bpp h) in cga mode, the pixel clock frequency is 9.557 mhz. in hga mode the pixel clock frequency is 14.336 mhz. therefore, when the lansc300 mi- crocontroller is configured for a 320 x 240, 1-bpp resolution lcd in cga mode, the refresh rate is 9.557 mhz (340 1 240) = 117 hz. when the lansc300 microcontroller is configured for the same size display in hga mode, the refresh rate is 14.336 mhz (340 1 240) = 175 hz. note that 2- color (1 bpp) mode can be supported by either cga or hga, but the hga refresh rate is approxi- mately 50% higher. 3. does the refresh rate fall in the range supported by the lcd panel? C yes: go to step 4. C no: panel cannot be driven by the lansc300 microcontroller. note: if the refresh rate driven by the lansc300 mi- crocontroller is too fast for the panel, it is possible to ef- fectively slow the refresh rate to the panel by programming the lansc300 microcontrollers graph- ics controller using a logical panel width that is greater than the physical lcd panel width. if this is done, the logical panel width must be used for all calculations, and it should first be tested on the same panel before making the design choice. this will determine if the panel can handle the additional shift clocks sent to it as a result of the larger panel width. 4. does the lansc300 microcontroller support the lcd panels video sram requirements? this is a concern only if the lcd will be operated in a graphics mode; therefore, text mode is not dis- cussed. 2 bits per pixel (four shades of gray) this mode consumes the most memory. each bank of memory is 8 kbyte (8192 bytes). in 2 bpp mode, each byte contains the equivalent of 4 pixels of in- formation. each bank can store information for 32,768 pixels. therefore, if configured for 4 banks of memory, the maximum number of pixels that the lansc300 microcontroller can support is 4 32,768 = 131,072 pixels. if configured for two banks of memory, the maximum number of pixels that the lansc300 microcontroller can support is 2 32,768 = 65,536 pixels. for example: a 320 x 240 lcd display has 320 240 = 76,800 pixels. therefore, the lansc300 microcontroller will support this resolu- tion lcd if configured for four banks of memory. 1 bit per pixel (2 shades of gray) each bank of memory is 8 kbyte (8192 bytes). in 1 bpp mode, each byte contains the equivalent of 8 pixels of information. each bank can store informa- tion for 65,536 pixels. therefore, if configured for four banks of memory, the maximum number of pix- els that the lansc300 microcontroller can support is 4 65,536 = 262,144 pixels. if configured for two banks of memory, the maximum number of pixels
8 configuring the lan?sc300 devices internal cga controller for a specific lcd panel that the lansc300 microcontroller can support is 2 65,536 = 131,072 pixels. for example: a 640 x 400 lcd display has 640 400 = 256,000 pixels. therefore the lansc300 microcontroller will support this resolu- tion lcd if configured for four banks of memory. 5. if the lcd panel meets the criteria listed in the pre- vious four steps, then the lansc300 microcontrol- ler is capable of driving the lcd panel. programming the lansc300 microcontroller to work with a single-screen lcd panel before programming the lansc300 microcontroller to work with a single-screen lcd panel, the following in- formation is needed: n display resolution in pixels, w x h (e.g., 640 x 200) n mode of operation (i.e., cga graphics-1 bpp, cga graphics-2 bpp, cga text, hga graphics-1 bpp, hga text) n if text mode, the font size (8 x fh for cga or 9 x fh for hga, where fh = font height; 8 x 8 is cga stan- dard, 9 x 14 is hga standard) n if graphics mode, the number of 8-kbyte banks of memory (see "steps for determining if a single- screen lcd panel can be driven by the lansc300 microcontroller" on page 7) determine the video index values to be programmed first determine the video index values for video in- dexes 00 C 0fh, based on the information listed in the four items above. cga & hga graphics mode values n (ht = w bpp 16) the horizontal total register (index 00h) and hor- izontal displayed register (index 01h) are pro- grammed with the number of 16-bit words per display row. in 2-color mode (1 bpp), this equals the width of the display in pixels divided by 16. in 4- color mode (2 bpp), this equals two times the width of the display in pixels divided by 16. for example, a 320 x 240 display is 320 pixels wide. therefore, in 2-color mode (1 bpp), ht = 320 16 = 20 (14h). n (vt = h banks) the vertical total register (index 04h), vertical display register (index 06h), and vertical sync po- sition register (index 07h) are programmed with the value of the height of the display in pixels, di- vided by the number of banks of memory. for exam- ple, a 320 x 240 display is 240 pixels high. if four banks of memory are going to be used, then vt = 240 4 = 60 (3ch). n (msl = banks C 1) the max scan line register (index 09h) is pro- grammed with the number of banks of memory to be used, minus 1. if four banks of memory are going to be used, then msl = 4 C 1 = 3. n (sah) (sal) the start address high (index 0ch) and start ad- dress low (index 0dh) video indexes together form a 14-bit offset (bits 7 and 6 of index 0ch are not used) that determines the location in video memory where the video controller will start fetching data to be displayed on the screen. typically, these indexes will be set to 0 so the display data starts being fetched from b8000h. scrolling can be imple- mented by changing the values in these registers. n all the other index registers (02, 03, 05, 08, 0ah, 0bh, 0eh, 0fh) will be programmed with 0h. cga & hga text mode values n ht = w bpp 16 the horizontal total register (index 00h) and hor- izontal displayed register (index 01h) are pro- grammed with the number of characters per row. the character width is hard coded to be 8 pixels wide. therefore, ht is the width of the display in pix- els divided by 8. for example, a 320 x 240 display is 320 pixels wide. therefore ht = 320 8 = 40 (28h). n (vt = h y) the vertical total register (index 04h), vertical displayed register (06h), and vertical sync posi- tion register (07h) are programmed with the value of the number of rows of characters. this is deter- mined by the height of the display in pixels, divided by the height of the character in pixels (y from the equation below). for example, a 320 x 240 display is 240 pixels high. if using an 8 x 10 font, then vt = 240 10 = 24 (18h). n (msl = y C1) the max scan line register (index 09h) is pro- grammed with the pixel height of the font C 1. for example, if using an 8 x 10 font, then msl = 10C1=9.
configuring the lan?sc300 devices internal cga controller for a specific lcd panel 9 n (cs = cursor start row C1) (ce = cursor end row C1) the cursor start register (index 0ah), and cursor end register (index 0bh) define the pixel rows within a font where the cursor will be displayed. typ- ically, the cursor is defined to be near the bottom of the character matrix. for example, an 8 x 10 font has 10 pixel rows. therefore, to have the cursor po- sitioned at rows 8 and 9, cs = 8 C 1 = 7, and ce = 9 C 1 = 8. note: bits 6 and 5 of the cursor start register (index 0ah) control the cursors behavior. see table 4. n (sah) (sal) the start address high (index 0ch) and start ad- dress low (index 0dh) video indexes together form a 14-bit offset (bits 7 and 6 of index 0ch are not used) that determines the location in video memory where the video controller will start fetching data to be displayed on the screen. typically, these indexes will be set to 0 so the display data starts being fetched from b8000h. scrolling can be imple- mented by changing the values in these registers. n (cah) (cal) cursor address high (index 0eh) and cursor ad- dress low (index 0fh) video indexes together form a 14-bit offset (bits 7 and 6 of index 0ch are not used) that determines the location in video memory where the video controller will display the cursor when the corresponding video data is displayed on the screen. for example, if sah = 0, sal = 0, cah = 0, and cal = 0, the cursor will be displayed in the upper left corner of the screen. n all the other index registers (02, 03, 05, 08, 0ah, 0bh, 0eh, 0fh) will be programmed with 0h. initializing the video controller the following sequences show the proper sequence for initializing the video controller. the following steps assume the video controller is set up to its default mode of cga and the video index registers are unlocked. (to unlock the video registers, write 12h to port 3d4h, and read port 3d5h with no i/o cycles between these.) note: only the minimum set of registers required to get the screen running are initialized. there are a num- ber of additional features such as auto screen blanking and text truncation that are discussed in the lan ? sc300 microcontroller programmers reference manual that are not reiterated in this document. cga graphics the video index registers are accessed by writing the register index to port 3d4h, and then writing or reading the register data to or from port 3d5h. 1. set video index 18h = 50h C sets up lcd panel type to single screen (bits 7 and 6) C sets display type to lcd (bit 4) 2. set video index 00h = ht 3. set video index 01h = ht 4. set video index 02h = 0 5. set video index 03h = 0 6. set video index 04h = vt 7. set video index 05h = 0 8. set video index 06h = vt 9. set video index 07h = vt 10.set video index 08h = 0 11. set video index 09h = msl 12.set video index 0ah = 0 13.set video index 0bh = 0 14.set video index 0ch = sah 15.set video index 0dh = sal 16.set video index 0eh = 0 17.set video index 0fh = 0 18.set video index 20h (bit 5 controls dot doubling) C if 2 bpp graphics mode is used, set bit 5 = 1 to disable dot doubling. note: this is the common setting. C if 2 bpp graphics mode is used, and dot dou- bling is desired (cga standard), then set bit 5 = 0. 19.if color mapping is going to be used: C set video indexs 14hC17h and 1chC1fh accordingly C set video index 19h = 10h 20.set video port 3d8h C if 2 bpp graphics mode, set to 0ah C if 1 bpp graphics mode, set to 1ah 21.set video port 3d9h C set colors accordingly (see the register descrip- tion in the lan tm sc300 microcontroller pro- grammers reference manual ) table 4. cursor control bits (index 0ah) bit 6 bit 5 cursor behavior 0 0 no blinking 0 1 cursor not displayed 1 0 blinking with 16 refresh rate 1 1 blinking with 32 refresh rate
10 configuring the lan?sc300 devices internal cga controller for a specific lcd panel cga text the video index registers are accessed by writing the register index to port 3d4h and then writing or reading the register data to or from port 3d5h. 1. set video index 18h = 50h C sets up lcd panel type to single screen (bits 7 and 6) C sets display type to lcd (bit 4) 2. set video index 00h = ht 3. set video index 01h = ht 4. set video index 02h = 0 5. set video index 03h = 0 6. set video index 04h = vt 7. set video index 05h = 0 8. set video index 06h = vt 9. set video index 07h = vt 10.set video index 08h = 0 11. set video index 09h = msl 12.set video index 0ah = cs 13.set video index 0bh = ce 14.set video index 0ch = sah 15.set video index 0dh = sal 16.set video index 0eh = cah 17.set video index 0fh = cal 18.if color mapping is going to be used: C set video indexes 14hC17h and 1chC1fh accordingly C set video index 19h = 10h 19.set video port 3d8h = 08h C enable text mode 20.set video port 3d9h C set colors accordingly (see the register descrip- tion in the lan tm sc300 microcontroller pro- grammers reference manual ) hga graphics initially, the video index registers are accessed by writ- ing the register index to port 3d4h, and then writing or reading the register data to or from port 3d5h. this oc- curs until the controller is switched to hga mode. after this occurs, port 3b4 is used for the index and port 3b5 is used for the data. 1. set video index 18h = 51h (use ports 3d4 and 3d5) C sets graphics mode to hga (from now on use ports 3b4 and 3b5) C sets up lcd panel type to single screen (bits 7 and 6) C sets display type to lcd (bit 4) 2. set video index 00h = ht 3. set video index 01h = ht 4. set video index 02h = 0 5. set video index 03h = 0 6. set video index 04h = vt 7. set video index 05h = 0 8. set video index 06h = vt 9. set video index 07h = vt 10.set video index 08h = 0 11. set video index 09h = msl 12.set video index 0ah = 0 13.set video index 0bh = 0 14.set video index 0ch = sah 15.set video index 0dh = sal 16.set video index 0eh = 0 17.set video index 0fh = 0 18.set video port 3bfh = 01h C master enable for graphics mode 19.set video port 3b8h = 0ah C enable graphics mode C enable video display
configuring the lan?sc300 devices internal cga controller for a specific lcd panel 11 hga text initially, the video index registers are accessed by writ- ing the register index to port 3d4h, and then writing or reading the register data to or from port 3d5h. this oc- curs until the controller is switched to hga mode. after this occurs, port 3b4 is used for the index and port 3b5 is used for the data. 1. set video index 18h = 51h (use ports 3d4 and 3d5) C sets graphics mode to hga (from now on use ports 3b4 and 3b5) C sets up lcd panel type to single screen (bits 7 and 6) C sets display type to lcd (bit 4) 2. set video index 00h = ht 3. set video index 01h = ht 4. set video index 02h = 0 5. set video index 03h = 0 6. set video index 04h = vt 7. set video index 05h = 0 8. set video index 06h = vt 9. set video index 07h = vt 10.set video index 08h = 0 11. set video index 09h = msl 12.set video index 0ah = cs 13.set video index 0bh = ce 14.set video index 0ch = sah 15.set video index 0dh = sal 16.set video index 0eh = cah 17.set video index 0fh = cal 18.set video port 3bfh = 00h C master disable for graphics mode 19.set video port 3b8h = 08h C enable video display dual-screen lcd support the lansc300 microcontroller supports only one type of dual-screen lcd display. the display must be 640 x 200 (640 x 100 per panel). the display must accept 8 data bits total (4 data bits per panel). the lansc300 microcontroller will support the panel in cga mode only and refresh the display at a rate of approximately 75 hz. the reason for the limited dual-screen support is that the lansc300 microcontroller does not have any dual-screen registers that, among other things, allow you to program where the fetching of data for the lower panel should begin. this was hard-wired in the lansc300 microcontroller. programming the lansc300 microcontroller for dual-screen lcd support the programming values for this dual-screen lcd are identical to the ones used for the single-screen panel with two exceptions. video index 18h bits 7 and 6 should be set to 00 instead of 01. the lansc300 mi- crocontroller configuration register b1h bit 1 must be set to 1 to enable the additional 4 lower-panel lcd data bits. the physical pin connections to the lansc300 microcontroller to connect an lcd panel to the lansc300 microcon- troller, the following pins need to be connected: lcdd3Clcdd0 : these are the panels data bits. lcdd3 is the msb; lcdd0 is the lsb. find out which data bit on the lcd is the msb, which is the lsb, and connect the pins accordingly. cp1 : also known as the line clock or latch (see defini- tion in "line clock (cp1)" on page 2). this should be connected to the equivalent line on the lcd panel. cp2 : also known as the shift clock or data shift (see definition in "shift clock (cp2)" on page 2). this should be connected to the equivalent line on the lcd panel. frm : also known as flm, or frame (see definition in "frame start (frm)" on page 2). this should be con- nected to the equivalent line on the lcd panel. m : ac modulation (see definition in "lcd panel ac modulation (m)" on page 2). some panels require this signal, others do not. connect this signal if appropriate. lcddl3Clcddl0 : these data bits are required only if a dual-screen lcd panel is being connected. these are the data bits for the lower panel. lcddl3 is the msb for the lower panel, and lcddl0 is the lsb for the lower panel. other lcd pin connections the other connections that need to be made to an lcd vary. for example: n contrast voltage : can be positive or negative, typ- ically about C22 volts. n +5 v n gnd n display enable : this is usually a simple 5-v enable signal that some panels require. this can easily be connected to one of the lansc300 microcontrol- lers pmc pins. n v ee : typically a voltage in the same range as the contrast voltage. refer to panel specifications.
12 configuring the lan?sc300 devices internal cga controller for a specific lcd panel using the lansc300 microcontroller evaluation board to test an lcd panel the lansc300 microcontroller evaluation board has a 20-pin header (p18) with all the lcd interface signals connected to it. the evaluation board provides a C14 v to C16 v contrast voltage (adjust using vr1) and a C17 v ee voltage. if the panel to be tested requires voltages other than these, a separate circuit will need to be bread boarded, or an external dc power supply used. the following evaluation board jumpers and resistor packs should also be set to configure the evaluation board for internal video mode: jp16 = 1C2; jp18 = open; install rp3 and rp4 (rp1, rp2, rp5, and rp6 must be empty). note that the evaluation board bios is set up to config- ure for a 640 x 200 single-panel display when the lansc300 microcontroller is in internal video mode. if a panel size other than this is used without modifying the bios, the screen may not display anything at boot- up. refer to "lcd development tips and tricks" for in- structions on how to use ctty for console activity while developing a screen application. also note that if a dual-screen lcd panel is used, the sbhe , irq14, mcs16, and ios16 isa signals are no longer available outside the chip. this means the stan- dard 16-bit ide interface cannot be used. table 5 shows how the pins on the 20-pin header should be connected to the pins of a hitachi lmg6272xnfr, 640 x 200 single-panel display. table 5. pin connections the lansc300 microcontroller evaluation board p18 header pins hitachi: lmg6272xnfr 640 x 200 single panel lcd pin # pin name function pin # pin name function 1 vcclcd5 +5 = 10 vdd power supply for logic circuit 2 gnd ground = 11 vss ground 3 lcdfrm frame start = 5 flm the flm signal indicates the start of each display cycle 4 lcdcp1 line clock = 7 cl1 data latch 5 lcdcp2 shift clock = 8 cl2 data shift 6 lcdm ac modulation x not used 7 lcdd0 data bit 0 (lsb) = 1 d0 data bit 0 (lsb) 8 lcdd1 data bit 1 = 2 d1 data bit 1 9 lcdd2 data bit 2 = 3 d2 data bit 2 10 lcdd3 data bit 3 (msb) = 4 d3 data bit 3 (msb) 11 lcddl0 dual-screen panel data bit 0 for lower panel x not used 12 lcddl1 dual-screen panel data bit 1 for lower panel x not used 13 lcddl2 dual-screen panel data bit 2 for lower panel x not used 14 lcddl3 dual-screen panel data bit 3 for lower panel x not used 15 contrast adjustable voltage between C14 v to C16 v = 9 vo lcd driving voltage 16 vee C17 v = 12 vee power supply for lc driving 17 20 nc not connected
configuring the lan?sc300 devices internal cga controller for a specific lcd panel 13 lcd development tips & tricks use ctty for console i/o when using an lcd as the console device under dos, there may be problems debugging the lcd because dos will also be attempting to write to the lcd through the bios. a way around this is by diverting the dos console i/o through the serial port. this allows use of debug or other application programs to access the lansc300 microcontrollers registers and view the re- sults on the lcd display. the following steps are rec- ommended: 1 connect a null modem cable between com1 on the lansc300 microcontroller and a pc running pro- comm or other terminal program. (a lap link serial cable is a null modem cable). 2. on the pc running procomm, set up for a direct connect to the serial port, running 9600 baud, 8 data, 1 stop bit, and no parity. set it up for a terminal type of either tty or ansi-bbs. 3. on the lansc300 microcontroller system, boot dos and have the following commands in the autoexec.bat file: C mode com1 9600,n,8,1 Cctty com1 4. after the system boots, the dos prompt will be vis- ible on the pc running procomm. 5. executing programs that use the console i/o such as debug should be possible. 6. programs that talk directly to video memory will dis- play the output on the lansc300 microcontroller system, but the keyboard input will come from the pc running procomm. 7. below are two things to keep in mind: C to debug an lcd, the lansc300 microcontrol- ler evaluation board should be configured for in- ternal video mode C if using phoenix bios, the bios will lock the video index registers. remember to unlock them by reading video index 12h. the bios will also lock the upper 16k of display memory, which is used for font storage in text mode. this can be unlocked by clearing bit 3 of video index 20h. the bios may also be updating the screen if using the lansc300 microcontroller evaluation board with an lcd standalone, (i.e., not option 1 above) and booting to dos, note that the bios is ac- cessing the video registers every time it is called to up- date the screen (i.e., typing in debug or from the dos prompt). if trying to use debug or other programs to modify the video registers, be aware that they may be modified by the bios as well, specifically ports 3d8h and 3d9h. using standard cga or hga drivers on a nonstandard display size it is possible to use standard cga or hga drivers on a nonstandard-sized screen. the method is to program the lansc300 microcontroller with values for the lcd width that match those that the driver expects. the lcd height can be set to the actual lcd height. this will cause the video sram to be organized as the stan- dard driver is expecting. the lcd panel will be display- ing the upper left of a virtual screen. trademarks copyright ? 1997 advanced micro devices, inc. all rights reserved. amd, the amd logo, combinations thereof, and lan are trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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