View KCD-A300-QB_1860189.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

kopin a300 display driver part number: KCD-A300-QB (august. 09, 2006) features ? support for 525 and 625 line monochrome systems ? integrated dc-dc conv erter provides all necessary voltages for the lcd display panel ? internal sync separator, pll, and logic provide all necessary timing signals to the lcd display panel ? gamma bias to adjust the video output characteristics ? hsync recovery ? battery voltage ; 2.5v ~ 3.6v ? power down mode ? 48lqfp general description the a300 is a driver for kopin?s cyberdisplay ? 300m lv monochrome display. it is designed to accept a standard monochrome video signal (525 or 625 lines), and convert it for the display. the a300 provides all necessary power supply voltages to the display panel by means of charge pump circuits. the input video signal is converted to appropriate differential video signals required by the lcd display panel. a separate on screen display (osd) input is provided. an on-chip sync separator, digital pll, and logic control section generate the appropriate horizontal an d vertical timing signals for the lcd panel. block diagram osd level detect dc restore sync seperator dpll q pump 3 (backlight) q pump 2 (display) timing control gamma & gain power down control osd mux internal white reference gen. + _ enb_qp3 clk_qp3 pre_qp3 fb_ref isink test_mode0 ref0 cka ckb fb5v test_mode1 pdb pal_sel skiplin fd0 fd1 inv0 inv1 v1x_sel extclk hs inv vs ck1 ck0 h v pdrb vid1 vid0 vgamma vgain vbat v33in osd_in wt_sel extwt bklvl vin vbg vssd vssa2 vssa3 vbba 1
pin descriptions pin symbol description 1 refo vref buffer output 2 osd_in input for the osd signals 3 extwt input for external white level 4 bklvl black level input 5 vin input for standard level monochrome video 6 vbg internally generated voltage reference 7 wt_sel input for external (low) or internal white level select 8 vssa1 analog ground 9 vbba substrate power 10 pdb power down (active low) 11 test_mode 1 test input pin 12 n.c no connection 13 vssd digital ground 14,15 fd0, fd1 field delay control, fd0: delay even field by one row fd1: delay odd field by one row 16 skiplin line skipping mode for pal vertical scaling 17 pal_mode ntsc / pal select, ntsc: low, pal: high 18 test_mode 0 test input pin 19,20 inv0 / inv1 inversion control, inv0 inv1 0 0 frame mode 0 1 pixel mode 1 0 column mode 1 1 row mode 21 v1x_sel vertical 1x at ?high? state, 2x inversion control at ?low? state 22 extclk clock input pin for test 23 inv inversion control output 24 hs horizontal output signal 25 vs vertical output signal 26,27 ck0 / ck1 pixel clock output 0/1 28 vssa2 analog ground 29 vid1 upper video drive signal to the lcd panel 30 vgamma gamma bias adjust 31 vgain gain bias adjust 32 vid0 lower video drive signal to the lcd panel 33 pdrb power down reset output to the lcd panel (active low) 34 isink led current control 35 vssa3 analog ground 36 fb_ref sink current control 37 pre_qp3 qpump3 clock buffer output 38 clk_qp3 qpump3 clock buffer output 39 v33in 3.3v regulated power supply 40 n.c no connection 41 n.c no connection 42 n.c no connection 43 enb_qp3 qpump3 enable input (active low) 44 vbat battery input 45 clkb qpump2 clock buffer output 46 clka qpump2 clock buffer output 47 n.c no connection 48 fb5v qpump2 voltage feedback 2
equivalent circuit for analog inputs dc gain control input, cmos gate input vgain 31 dc gamma control input, npn bipolar transistor input with beta=~45 vgam ma 30 dc black level input, cmos buffer input bklvl 4 dc white level input, cmos buffer input extwt 3 signal waveform function equivalent circuit symbol pin no. vssa1 v33in 3 5k 5k 5k 2k 2k vssa1 v33in vssa1 v33in 4 5k 2k 2k v33in 30 2k 2k vssa1 v33in vssa1 6k 20k v33in 31 2k 2k vssa1 v33in vssa1 vssa1 v33in 3
absolute maximum ratings symbol description min max unit vbat supply voltage -0.5 4.0 v v33in supply voltage -0.5 4.0 v vind digital input pin voltage vssd-0.3 v33in+0.3 v vina analog input pin voltage vssa-0.3 vbat+0.3 v tstorage storage temperature -40 125 c recommended operating conditions parameter conditions min typ max unit power supply voltage vbat 2.5 3.6 v power supply voltage v33in 2.7 3.6 v video signal input level (composite video-luma) - 1.0 - vp-p osd input level 0 - vbat v logic input level 0 - vbat v vgain bias range 1.2 - 2.0 v vgamma bias range 1.2 - 2.0 v external white level internal white level = 2*external white level 0 - 1.5 v operating temperature range -20 70 c electrical characteristics (all parameters are specified at ta=25 c, v33in=3.3v, unless otherwise noted.) dc characteristics parameter conditions min typ max unit supply current v33in=3.3v 13 ? shutdown current pdb=low 100 - ? pll/sync separator / video amplifier parameter conditions min typ max unit vbg bandgap reference(pin6) vbat=3.3v 1.15 1.23 1.3 v pixel clock output - 24 - mhz pll lock range 14.175 - 17.1875 khz power_down_reset (pdr) parameter conditions min typ max unit rst threshold 2.2 2.3 2.4 v hysterisis 0.1 v 4
display_pump (qpump 2) parameter conditions min typ max unit input voltage 2.5 3.6 v output voltage iout 5 a , 2.5v vin 3.6v -4.8 -5 -5.2 v output current 1 5 a oscillator frequency during active period 375 khz ripple voltage iout=1 a 60 mv quiescent current iout=0 a , vin=2.5v to 3.6v 70 120 shutdown current pdb=low 1 line regulation 2.5v vin 3.6v 40 50 a load regulation 0 a vload 1 a 40 50 a backlight_pump (qpump3) parameter conditions min typ max unit input voltage 2.5 3.6 v output voltage iout 30 a , 2.5v vin 3.6v - 3.6 - v output current 30 a oscillator frequency during active period 375 khz ripple voltage isink=10 a 60 a quiescent current isink=0 a , vin=2.5v to 3.6v 70 120 shutdown current pdb=low and/or enb_qp3=low 1 osd_detector parameter conditions min typ max unit input voltage 0 vbat v osdwt threshold 2/3 vbat v osdbk threshold 1/3 vbat v osdwt delay 20 30 ns osdbk delay 20 30 ns gain & gamma parameter conditions min typ max unit input voltage 1.15 2.05 v vgain bias range 1.2 2.0 v vgamma bias 1.2 2.0 v gain under breakpoint vin=1.15v,vgamma=1.5v 3.4 8.5 db gain upper breakpoint vin=1.85v,vgamma=1.5v 3.9 4.0 db 5
ac characteristics t nol t nol t cp t ch t cd ck0 ck1 symbol parameter min typ max unit t nol ck0 and ck1 non-overlap time 1 5 - ns t cp clock period - 333 - ns 2/t cp pixel rate - 6 - mhz t ch clock high pulse width 120 - - ns t cd ck0 to ck1 delay ( t cp /2)-5 t cp /2 ( t cp /2)+5 ns 0 2 4 326 1 3 5 327 t fd t bd t wh t ws white white white white vidh hs ck0 ck1 vidl symbol parameter min typ max unit t fd hs to 1 st ck0 delay 1.4 - s t bd 327 th ck0 to hs delay 1.4 - s t wh white hold after hs 500 - ns t ws white setup before hs 500 - ns 6
t is t ih t is t ih hs inv symbol parameter min typ max unit t is inv setup time 300 - ns t ih inv hold time 300 - ns 0 1 2 t v t hvd 240 t vhd t vsh 0 1 2 0 1 2 239 239 vs hs ck0 ck1 symbol parameter min typ max unit t v field period 16.7 ? 20.0 - ms (1/t v ) field rate 50 - 60 - hz t vsh vs high pulse width 10 - s t vhd vs to hs delay 10 - s t hvd hs to vs delay 10 s 7
a pplication information table 2: inversion control inversion control a liquid crystal display requires polarity inversion to maintain dc balance across the liquid crystal. the cyberdisplay 300m lv contains internal logic supporting four inversion modes: pixel, column, row, or frame (table 2). the inversion mode is selected by two bits inv0 and inv1. the cyberdisplay 300m lv inverts polarity with every pu lse of vs, normally once per field. this so-called ?2x rate? is preferable for most applications. however, 1x inversion may be accomplished when the v1x_sel pin is tied high. video input an ac coupled video signal is input to video in pin 5 via capacitor, normally 0.1uf. when using pal video signal, pin 17 tied to high. the standard horizontal video timing is shown fig. 1. inv0=low, inv1=low frame mode inv0=low, inv1=high pixel mode inv0=high, inv1=low column mode inv0=high, inv1=high row mode fig. 1: horizontal video timing 0 4 8 12 16 20 24 28 32 36 40 364 368 372 376 380 384 44 48 52 56 60 64 active active strating point horizontal sync back porch front porch time(t h /384) video hs inv ck0 ck1 white bkclamp 8
field delay control (fd0, fd1) the vertical start pulse can be delayed in even and/or odd field by 1 or 2 line. start position is shown below in figures 2 - 9. line 22 line 23 line 24 line 285 line 286 line 287 field 0 start position field 1 start position line 23 line 24 line 25 line 335 line 336 line 337 field 0 start position field 1 start position fig. 2 ntsc mode fd0 = 0 , fd1 = 0 fig. 6 pal mode fd0 = 0 , fd1 = 0 line 22 line 23 line 24 line 285 line 286 line 287 field 0 start position line 23 line 24 line 25 line 335 line 336 line 337 field 0 start position fig. 3 ntsc mode fd0 = 0 , fd1 = 1 fig. 7 pal mode fd0 = 0 , fd1 = 1 line 22 line 23 line 24 line 285 line 286 line 287 field 1 start position line 23 line 24 line 25 line 335 line 336 line 337 field 1 start position fig. 4 ntsc mode fd0 = 1 , fd1 = 0 fig. 8 pal mode fd0 = 1 , fd1 = 0 line 22 line 23 line 24 line 285 line 286 line 287 field 1 start position line 23 line 24 line 25 line 335 line 336 line 337 field 0 start position fig. 5 ntsc mode fd0 = 1 , fd1 = 1 fig. 9 pal mode fd0 = 1 , fd1 = 1 field 1 start position field 0 start position field 0 start position skiplin=0 skiplin=1 field 1 start position field 1 start position field 0 start position 9
vertical scaling in pal mode (skiplin) the pal video format has 625 lines per frame, of which 576 are active. vertical scaling must be performed to match 5762=288 lines per field to the display?s 240 physical rows. two 6:5 scaling modes may be selected by the lineskp pin. field 0 field 1 skiplin fd0 fd1 start line number skip line number start line number skip line number 0 0 0 23 28 + 6n (n=0,1,2,?) 335 337 + 6n (n=0,1,2,?) 0 0 1 23 28 + 6n (n=0,1,2,?) 336 338 + 6n (n=0,1,2,?) 0 1 0 24 29 + 6n (n=0,1,2,?) 335 337 + 6n (n=0,1,2,?) 0 1 1 23 28 + 6n (n=0,1,2,?) 337 339 + 6n (n=0,1,2,?) 1 0 0 23 28 + 6n (n=0,1,2,?) 335 340 + 6n (n=0,1,2,?) 1 0 1 23 28 + 6n (n=0,1,2,?) 336 341+ 6n (n=0,1,2,?) 1 1 0 24 29 + 6n (n=0,1,2,?) 336 340 + 6n (n=0,1,2,?) 1 1 1 23 28 + 6n (n=0,1,2,?) 337 342 + 6n (n=0,1,2,?) digital pll the digital pll will lock to the horizontal frequency of the incoming video so as to generate pixel clock. the timing generator provides all the timing signals to the display. when there is unstable horizontal frequency of the incoming video, the dpll will be reset and try to lock it again. the pll will be reset when the unstable condition persists for more than 2 frames (40 ms). 10
application example circuit 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 kcd-qk05-dc KCD-A300-QB 48 lqfp refo osd_in extwt bklvl vin vbg wt_sel vssa1 vbba pdb test_1 n.c vssd fdo fd1 skiplin pal test_0 inv0 inv1 v1x_sel ext_clk inv hs fb5v n.c clka clkb vbat enb_qp3 n.c n.c n.c v33in clk_qp3 pre_qp3 fb_ref vssa3 isink pdr vid0 vgain vgamma vid1 vssa2 ck1 ck0 vs 30.9k 200k 4.7u 10p 4.7u 4.7u -5v 0.22u 4.7u 0.22u 22uf 0.1uf pal/ntsc v33in 68k 33k 10k 10k 220k 0.1uf 0.1uf osd_in vin 3.9k 4.7k 0.1uf 4.7k vr10k 0.1uf 0.33uf 0.33uf vid0 vid1 ck1 ck0 vs hs inv 0.1uf 0.1uf v33in v33in v33in v33in v33in 40.2k 1 3 2 4 5 6 7 8 9 10 11 12 13 14 15 15flz-sm1-tb j3 hiros connector 15flz-sm1-tb or equivalent to cyber display 320 model 300 vee = 0v tp127 c52 0.33uf pdr* hs sleep* vss = -5v ck1 ck0 vdd = 3.3v vid1 c52 0.33uf vidh vidl vs rgt inv vid0 11

▲Up To Search▲

Price & Availability of KCD-A300-QB

	To Download KCD-A300-QB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .