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1 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver ace1202r data encryption standard (des) receiver ACE1202REM device pin-out preliminary august 2001 ?2001 fairchild semiconductor corporation general description the ace1202r is a custom receiver implementing the des algorithm. the receiver is used to decrypt a pulse-width modu- lated (pwm) encrypted signal transmitted by a radio frequency (rf) transmitter using the ace1202t 1 . together, the ace1202r and ace1202t form an encoder/decoder chip-set used in high security applications. remote keyless entry burglar alarms / garage door openers individualized recognition / transmission systems. game protection the ace1202r is a member of the ace1202 (arithmetic control- ler engine) family of microcontrollers. the ace1202 product family is a dedicated programmable monolithic integrated circuit for applications requiring high performance, low power, and small size. it is a fully static part fabricated using cmos technology. for additional information regarding the ace1202 family of microcontrollers please refer fairchild semiconductor? web site at www.fairchildsemi.com. features 32-bit des decoder receiver switched power mode up to 4 output channels pulsed outputs rf module switched v cc single supply operation (2.2 ?5.5v) low power halt mode (100na @ 3.3v) integrated power-on reset brown-out reset integrated rc oscillator integrated eeprom - 64 byte of data eeprom for data storage and options - 2k bytes of code eeprom - 40 years data retention - 1,000,000 data writes 14-pin soic package 1 see the ace1202t datasheet at www.fairchildsemi.com for details. 2 pin 14 must be de-coupled with a 100nf ceramic capacitor to gnd. v cc gnd rxin lrn o3 nc onr/txd rxd o4 o1 1 2 3 4 5 6 7 14 2 13 12 11 10 9 8 nc nc reset o2
2 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 2.0 pin description 2.1 lrn C pin1 the lrn pin is an active low input with an internal weak pull-up and is used to disable the learning code feature on the ace1202r. if the learning code feature is not needed, the lrn pin may be left unconnected avoiding the use of an external pull-up resister since it exists internally. the learning code feature is activated by applying a logic 0 to the lrn pin. this then disables the ace1202r from receiving the des and counter synchronization frames. the lrn pin can also used to enter the programming mode if the forceprogr flag in the option register is set. (see section 11.0) 2.2 o1 to o4 C pins 7, 8, 2 and 6 these output pins are activated, according with the value received in data field, upon reception of a valid normal frame (fix and des code must match internal memory). the outputs can be programmed to behave in three different modes: 1) stable output levels (direct or inverted) 2) pulsed (direct or inverted) with programmable pulse duration 3) output toggle: active output change state every valid frame received (direct or inverted) see section 8.4 and 8.8. 2.3 onr/txd C pin 4 the onr/txd pin is a multiplexed output used in both the pwm and nrz modes. in the pwm mode, the onr/txd pin assumes the onr (turn on receiver) function. the onr pin option is used to wakeup the external rf module in order to save current consumption in the entire system. (see section 9.0 for further information regarding the pwm mode.) in nrz mode, the onr/txd pin assumes the txd function. the txd pin option is used to transmit information to an external unit (pc or ace1202t) in the nrz format. (see section 11.0 for further information regarding the nrz mode.) 2.4 rxd C pin 5 in nrz mode, the rxd pin is an input accepting serial data transmitted by the pc or the ace1202t. the rxd pin is not used in the pwm mode and can be left floating. 2.5 rxin C pin 11 in pwm mode, the rxin pin is the receiving input line from the external rf module expecting only active high data. the rxin pin is not used while in the nrz mode and can be left floating. 2.6 reset C pin 9 the reset pin is an active low input and is used to externally reset the ace1202r. however, since the ace1202r has an internal power-on reset (por) circuit the reset pin may not be needed. in this case, the reset pin may be left floating or connected to v cc . before using the internal por, the v cc rise time condition must be met. (see section 15.0) 2.7 v cc and gnd C pins: 14 and 13 vcc and gnd are the power supply lines. the ace1202r is designed to work with a 3.3v or a 5.0v supply voltage. figure 2. receiver block diagram 1 2 3 4 14 13 12 11 lrn o3 onr/txd rxd o4 o1 v cc gnd rxin rxd reset o2 5 69 78 10 rf module progr. switch ace1202r voltage regul. v cc
3 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 3.0 electrical characteristics absolute maximum ratings ambient storage temperature -65 c to +150 c input voltage -0.3v to v cc +0.3v lead temperature (10s max) +300 c electrostatic discharge on all pins 2000v operating conditions ambient operating temperatures: ACE1202REM -40 c to +85 c operating supply voltage: from -40 c to +85 c 2.2v to 5.5v relative humidity (non-condensing) 95% eeprom write limits see dc electrical characteristics preliminary ACE1202REM dc electrical characteristics for v cc = 2.2 to 5.5v all measurements are valid for ambient operating temperature range unless otherwise stated. symbol parameter conditions min typ max unit i cc 3 supply current - no 2.2v 0.4 1.0 ma data eeprom write 2.7v 0.7 1.2 ma in progress 3.3v 1.3 1.5 ma 5.5v 3.6 4.5 ma i cch halt mode current 3.3v @ -40 c to 25 c 10 100 na 5.5v @ -40 c to 25 c 60 1000 na 3.3v @ +85 c 75 1000 na 5.5 @ +85 c 400 2500 na i ccl 4 idle mode current 3.3v 150 a 5.5v 200 a v ccw eeprom write voltage data eeprom in 2.4 5.5 v operating mode s vcc power supply slope 1 s/v 10ms/v v il input high with schmitt v cc = 2.2 - 5.5v 0.2v cc v trigger buffer v ih input high withi schmitt v cc = 2..2 - 5.5v 0.8v cc v trigger buffer i ip input pull-up current v cc = 5.5v, v in = 0v 30 65 350 a i tl tri-state leakage v cc = 5.5v 2 200 na v ol output low voltage: v cc = 2.2v o1, o2, o3, onr 2.0 ma sink 0.2v cc v o4 4.0 ma sink 0.2v cc v output low voltage: v cc = 2.7v o1, o2, o3, onr 3.0 ma sink 0.2v cc v o4 5.0 ma sink 0.2v cc v output low voltage: v cc = 3.3 - 5.5v o1, o2, o3, onr 5.0 ma sink 0.2v cc v o4 10.0 ma sink 0.2v cc v v oh output high voltage: v cc = 2.2v o1, o2, o3, onr 0.4 ma source 0.8v cc v o4 0.8 ma source 0.8v cc v output high voltage: v cc = 2.7v o1, o2, o3, onr 0.4 ma source 0.8v cc v o4 0.8 ma source 0.8v cc v output high voltage: v cc = 3.3 - 5.5v o1, o2, o3, onr 0.4 ma source 0.8v cc v o4 1.0 ma source 0.8v cc v 3 for i cc active data with eeprom writes see figure 5. 4 idle current is base on a continuous looping program. the true idle current is dependent on the specific application and the v alue stored in the rxawake register. see section 9.0 for details.
4 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver preliminary ACE1202REM ac electrical characteristics for v cc = 2.2 to 5.5v all measurements are valid for ambient operating temperature range unless otherwise stated. parameter conditions min typ max unit instruction cycle time from internal 5.0c at + 25 c 0.9 1.0 1.1 s clock - setpoint internal cycle voltage dependent 3.0v to 5.5v, constant 5% frequency variation temperature internal clock temperature dependent 3.0v to 5.5v, full 10 % frequency variation temperature range internal clock frequency deviation for 3.0v to 4.5v, constant 2% 0.5v drop temperature eeprom write time 310ms internal clock start up time (note 5) 2 ms oscillator start up time (note 5) 2400 cycles preliminary ACE1202REM low battery detect (lbd) characteristics, v cc = 2.2 to 5.5v parameter conditions min typ max unit lowbattlev addr. 0x67 -40 c 2.45 v 0 c 2.63 v +25 c 2.67 v +85 c 2.87 v preliminary ACE1202REM brown-out reset (bor) characteristics, v cc = 2.2 to 5.5v parameter conditions min typ max unit bor trigger threshold -40 c 1.98 v 0 c 2.06 v +25 c 2.12 v +85 c 2.27 v
5 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 3.1 preliminary ac & dc electrical characteristic graphs figure 3: internal oscillator frequency figure 4: power supply rise time t s min t s actual t s max time v cc v batt 1v name parameter unit v cc supply voltage [v] v batt battery voltage (nominal operating voltage) [v] t s min minimum time for v cc to rise by 1v [ms] t s actual actual time for v cc to rise by 1v [ms] t s max maximum time for v cc to rise by 1v [ms] s vcc power supply slope [ms/v] internal osc. frequency vs. temperature 1.60 1.70 1.80 1.90 2.00 2.10 2.20 -40 0 25 85 125 temperature (c) 2.2v 2.7v 3.3v 5.5v frequency (mhz)
6 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver figure 5: i cc active icc active (no data eeprom writes) vs. temperature 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 -40 0 25 85 125 temperature (c) 2.2v 2.7v 3.3v 5.5v icc active (data eeprom writes) vs. temperature 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000 -40 0 25 85 125 temperature (c) 2.7v 3.3v 5.5v icc active (ma) icc active (ma)
7 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver figure 6: halt current halt current vs. temperature 0 200 400 600 800 1000 1200 1400 1600 -40 0 25 85 125 temperature (c) 3.3v 5.5v icc halt (na)
8 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 4.0 general characteristics ace1202r is intended for use with the ace1202t product. this chip-set forms a secure and inexpensive system for a variety of applications that require a high level of security such as remote keyless entry or software protection. the basic function of the ace1202r is to receive a des coded message frame containing a fixed identifier (24-bit), data field (8- bit), des code (32-bit), a sequential counter (16-bit), and a parity field. this frame is received in a pwm coded format suitable for a rf system or a nrz format, used in a direct wire connection 5 . this frame will be compared with previously stored information in order to match the fixed and dynamic part of the code message. 4.1 mode of operations ace1202r can be programmed to work in three different modes as indicated in table 5 and is description in later sections. table 5 ace1202r operating modes operating modes description pwm mode indicated to work with a rf module nrz mode indicated to work with wired connection programming mode to select and program the user defined area 5 pwm coding is typically used in rf transmission, nrz coding can be used as well however the bit rate tolerance is a critical a spect to consider to extract correct information. we suggest to adopt nrz mode for wired direct connection.
9 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 5.0 des message description the des coded message is 12-bytes wide and is divided into fields transmitted in the following order: preamble sent only once as a continuous series of frames used to wake the receiver from halt mode. sync field 8 coded bits for the synchronization of the incoming data stream. data field contains information about the channel selected and special transmitting modes: des_key and des_counter. it is 8 bits wide. fixed field a unique 24-bit code that identifies the transmitter. des field the 32-bit des generated code. counter field the lower 16 bits of the des counter. parity field byte-wise exclusive-or from sync field to des field. the frame type selection bits of the data field configures the des field for one of three configurations. the three des frame configu- rations are the normal frame, the sync_des_key frame, and the sync_des_cnt frame. (see figure 7) 5.1 sync field the sync field is 8-bits wide and identifies the start of the des frame. 5.2 fixed field the fixed field is three bytes (24-bits) long and is used to identify the individual transmitter. if the fixed field is not found in the ace1202r memory, the frame will be rejected. the ace1202r must learn the fixed field while in a special operating mode. (see section 7.1.) 5.3 data field the data field contains the current configuration of the transmission. bits 7 to 4 decode the binary transmitter key configuration. the least significant nibble selects the frame type. see table 6 for details. table 6 data field bit definition bit value description bit 7 1 key1 has been pressed -> activate 01 bit 6 1 key2 has been pressed -> activate 02 bit 5 1 key3 has been pressed -> activate 03 bit 4 1 key4 has been pressed -> activate 04 bit 3-0 frame type selection: 0000 normal 0010 des key sync 0011 des counter sync 1111 low battery 5.4 des code field the des code field is the 32 most significant bits of the calculated des algorithm using the known des key and counter. (see section 6.0) this field is compared with the des code calculated internally by the receiver. this field is only sent in the normal frame. 5.5 counter field the counter field is the 16 least significant bits of the internal 64- bit des counter. the counter is used to synchronize the des operation on the receiver side. this field is transmitted only in the normal frame. this information helps track the current des progression held in the linear des counter. normally, only one calculation is needed to determine the current des code. 5.6 parity field the parity field is present in all the frames and contains the checksum for the frame transmitted. the checksum is the exclu- sive-or of all bytes received in the frames starting from sync field. 5.7 des key field the des key field is the security des key used in the algorithm to calculate the current des code. the four least significant bits in the data field indicate to the receiver that a sync_des_key frame (0x02) will be received. the receiver will store the des key in the internal register for future normal frame decoding. the true length of the des key is 56-bits wide. the des key field is 48 bits wide (addr. 0x45 to 0x4a duplicated in addr. 0x75 to 0x7a) and the remaining 8 bits of the des key is a user defined value, stored in memory (addr. 0x4b, duplicated in addr. 0x7b) during factory programming, otherwise it is defaulted to 0x00. if pin 1 of the ace1202r is set to logic 0 , the receiver will ignore any sync frame requests. 5.8 des counter field the des counter field is the 48-bit des counter used in the algorithm to calculate the current des code. the four least significant bits in the data field indicate to the receiver that a sync_des_cnt frame (0x03) will be received. the des counter will be stored in the internal registers for future normal frame decoding. the true length of the des counter is 64-bits long. the des counter field is 48-bits and the remaining 16 least significant bits are set to 0 every time a sync_des_cnt frame is transmit- ted. if pin 1 of ace1202r is set to logic 0 , the receiver will ignore any sync frame request. sync field 8 bit fixed field 24 bit data field xxxx0000 des code 32 bit counter 16 bit parity 8 bit normal frame sync field 8 bit fixed field 24 bit data field xx1x0010 des key 48 bit parity 8 bit sync_des_key frame sync field 8 bit fixed field 24 bit data field xxx10011 des counter 48 bit parity 8 bit sync_des_cnt frame figure 7. normal and sync frames
10 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 6.0 des algorithm with the help of the national security agency the national bureau of standards certified the data encryption standard (des) in the1977 to be used in electronic devices for the protection of coded data during transmission and storage in a computer system or network the des algorithm is different from other cryptography algorithms in that it is not kept in secret like the others. the des algorithm is public and the system security is based on a secret key (des key) of 56-bits plus 8-bits of parity known only by the transmitter and receiver. the des key must be transmitted or directly stored in the transmitter / receiver memory. the implementation of the des algorithm used in the ace1202r and ace1202t chip-set does not use the initial and final permu- tations normally used in des, as there is no benefit in implement- ing these permutations where des is used for authentication. figure 8 shows how the des algorithm encodes a 64-bit counter using a 56-bit des key to obtain the 64-bit des code. 64-bit des code 32 lsb bits of des code 16 lsb bits of des counter des algorithm sync field 8 bit fixed field 24 bit data field xxxx0000 des code 32 bit counter 16 bit parity 8 bit 56-bit des key 64-bit counter figure 8 des algorithm data flow
11 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 7.0 system operation to validate a normal frame received, the receiver must know the secret des key and the 64-bit counter. the receiver deter- mines these parameters either through the learning mode or by pre-programming. 7.1 learning mode to enter into the learning mode, the transmitter has to be enabled to send the sync frame 6 while pin 1 on ace1202r is at logic level 1.' as soon as a sync frame (key or counter) has been received, the information will be stored in the ace1202r eeprom (see section 8.3) replacing any previously stored information. if a sync_des_key frame is received and bit 0 ( autocntr ) in the options register is set, the des counter will be initialized as fixed. this saves an extra operation in sending a separate sync_des_cnt frame. 7.2 pre-programming if the transmitter is coupled with the receiver module after factory assembly, all the needed parameters (fixed code, des key, and des counter) can be stored directly into ace1202r user area using the 2/4 wire programming interface described in sections 8.0 and 11.0. if needed, the user area can be protected after programming to prevent external reading or writing of the user area. 6 see the ace1202t datasheet at www.fairchildsemi.com for details.
12 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 8.0 user area: it is possible to read, write, or protect the user-defined area using a 2- wire programming interface. the programming interface operates as a half duplex asynchronous protocol with txd (pin 4) and rxd (pin 5) dedicated lines with communications using the nrz format. the nrz format operates at a baud rate of 4800bps and a data frame format of 8 data bits, 1 start bit, and 1 stop bit. in order to enter programming mode, pins 4 and 5 must be at logic 1 level during power-up. after 500ms the part is ready to accept command from an external programmer. the first message must be a character corresponding to the hex value 0x55 needed to calibrate the internal baud-rate register. upon reception of the baud adjustment message, ace1202r will respond with an acknowledge message to inform the external programmer to be ready to receive new messages. the message structure is variable in length and follows the form: a) [0x55]: sent only from ace1202r to external ace1202t or programmer b) nbytes : the number of bytes to send 1 c) opcode : op-code field d) data : variable field from 1 to 15 bytes depending on op-code e) checksum : logical byte-wise exclusive-or of the previous fields b) to c) possible messages are: eeprom read (progr. to ace1202r) nbytes + read_usr_area + addr. + checksum (to read any location in user area) nbytes = 3 read_usr_area = 0x38 this message is valid only if the rd_protect bit is zero in options address (0x60). if the operation is executed correctly, the ace1202r will return the message: nbytes + read_usr_area + addr. + read_value + checksum , otherwise the message unknown will be returned. eeprom write (progr. to ace1202r) nbytes + write usr_area + addr.+ value + checksum (to write any location in user area) nbytes = 4 write_usr_area = 0x93 this message is valid only if the wr_protect bit is zero in options address (0x60). if the operation is executed correctly, the ace1202r will return the message: nbytes + write_usr_area + addr. + programmed_value + checksum , otherwise the message unknown will be returned. des frame (ace1202r to ace1202t) / des valid (ace1202t to ace1202r) [0x55] + nbytes + des_frame + fixedhigh + fixedmid + fixedlow + data + cnt0 + cnt1 + des3 + des2 + des1 + des0 + checksum (this is the des frame to be checked by the internal algorithm) nbytes = 12 des_frame = des_valid = 0x5a if the message has correct checksum and a valid des code, it will answer with the next des code generated by incrementing the des counter. if the message contains an invalid des code ace1202t will re-send the same message back to ace1202r (see section 12.0). the 0x55 preamble is sent only from ace1202r to ace1202t (des_frame) des key and counter info (ace1202r to ace1202t) 0x55 + nbytes + des_par + syncfield + fixedhigh + fixedmid + fixedlow + des_key0 + des_key1 + des_key2 + des_key3 + des_key4 + des_key5 + des_cnt2 + des_cnt3 + des_cnt4 + des_cnt5 + des_cnt6 + des_cnt7 + checksum (des information for ace1202t). nbytes = 18 des_par = 0x44 this frame is sent when the ace1202t is not in programmed state (blanked) and it is used to store the des parameters, des key, des counter and fix code into ace1202t user area. status request (ace1202r to ace1202t) 0x55 + nbytes + rx_stat_req + acerx_state + sw_revision + checksum (this message is only sent after pc connection, following the inquire (0x55) parameter.) nbytes = 4 rx_stat_req = 0x40 ace-r_state = 0x2a-> rx has no des information stored in memory ace-r_state = 0x33 -> rx has des information stored in memory sw_revision: bit0 to 3 = data eeprom revision bit4 to 7 = code revision exit (progr. to ace1202r) nbytes + exit + checksum (to exit from programming mode ) nbytes = 2 exit = 0x2b 8.1 message table table 7 nrz messages message byte sent 1 op-code meaning read_usr_area 3 0x38 progr to ace1202r - read one location at specified address write_usr_area 4 0x93 progr to ace1202r write data at specified address des_frame 12 0x5a ace1202r to ace1202t send current des code des_param 18 0x44 ace1202r to ace1202t send des parameter to store rx_stat 3 0x40 ace1202r to progr. actual ace1202r status exit 2 0x2b progr to ace1202r exit from progr connection unknown 2 0x55 ace1202r response to invalid messages des_valid 12 0x5a ace1202t to ace1202r next calculated des code
13 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 8.2 programming recommendations: ace1202r and ace1202t are delivered from the factory with default values loaded into user area allowing the designer to perform a test on the parts without data initialization. the programming interface is designed to allow easy in-circuit programming using the 4-wires interface. it is the responsibility of the user to load the appropriate value in the user area. it is recommended always to set the read and write protection bits prior to terminating the programming process. if further programming is needed, the read protection bit should be enabled to avoid external reading of the des information which need to remain secret to avoid system intrusion. 8.3 user area table table 8 user area registers addr. label description note 0x40 unused 0x41-0x71 sync field 8 bit synchronization field read/write 0x42-0x72 fixed high 24 bit fixed code high part read/write 0x43-0x73 fixed mid 24 bit fixed code mid part read/write 0x44-0x74 fixed low 24 bit fixed code low part read/write 0x45-0x75 des_key0 56 bit des key byte 0 read/write 0x46-0x76 des_key1 56 bit des key byte 1 read/write 0x47-0x77 des_key2 56 bit des key byte 2 read/write 0x48-0x78 des_key3 56 bit des key byte 3 read/write 0x49-0x79 des_key4 56 bit des key byte 4 read/write 0x4a-0x7a des_key5 56 bit des key byte 5 read/write 0x4b-0x7b des_key6 56 bit des key byte 6 user defined. read/write 0x4c-0x7c des_key_check des _k+ fixed checksum value read/write 0x4d des_cnt0_a 64 bit des counter byte 0 bank 0 - read/write 0x4e des_cnt1_a 64 bit des counter byte 1 bank 0 - read/write 0x4f des_cnt2_a 64 bit des counter byte 2 bank 0 - read/write 0x50 des_cnt3_a 64 bit des counter byte 3 bank 0 - read/write 0x51 des_cnt4_a 64 bit des counter byte 4 bank 0 - read/write 0x52 des_cnt5_a 64 bit des counter byte 5 bank 0 - read/write 0x53 des_cnt6_a 64 bit des counter byte 6 bank 0 - read/write 0x54 des_cnt7_a 64 bit des counter byte 7 bank 0 - read/write 0x55 des_cnta_check counter a checksum bank 0 - read/write 0x5f 0x60 options operation options read/write 0x61 rx_timeout active time waiting for messages to be received read/write step 8.2ms 0x62 rxawake - rf module power up cycle (pwm mode) step 8.2ms - read/write - in nrz mode is the ace1202t polling time step 50ms in nrz 0x63 pulse_out out1 4 pulse duration step 2.5ms - read/write 0x64 mask_port xor mask for portg read/write 0x65 baud_adj adjusted baud-rate value read only 0x66 acerx_state functional receiver state read/write 0x67 lowbattlev low battery level - 2.6v read/write 7 0x6d factory data1 free read/write 0x6e factory data2 free read/write 0x6f data eeprom revision eeprom data revision 0 to 0xf read/write 7 7 though it is possible to write in this location, it is recommended not to modify the factory defined values.
14 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 8.4 options register (addr. 0x60) bit 0 C autocntr if set to 1, the des counter will be set to a unique secret configuration once the sync_des_key frame is received. bit 1 C forcenrz when this bit is set to 1, the ace1202r enters the nrz mode regardless of the pin levels (after a power-on reset) on the rxd and txd pins. this option can be used only when the requested mode is nrz or to save external pull-ups on the rxd and txd pins. bit 2 C lowpowerm if set to 1, a special low power mode is enabled using the internal idle mode (see section 9.0.) the onr pin is used to switch an external power supply to the external rf receiver module. the onr timing is defined in the rx_timeout and rxawake registers. bit 3 C forceprogr if set to 1, a 0 on the lrn pin will force the ace1202r to enter into programming mode. programming mode is left as soon as the lrn pin returns to v cc . bit 4 C enalearn if the forceprogr bit of the options register is 1, the enalearn bit becomes active (set to 1 ) allowing the ace1202r to receive sync frames. the enalearn bit may be used to replace the external lrn pin feature with a programmable option through the forceprogr bit. bit 5 C despar if set to 0, the ace1202r is allowed to send the des parameters through the nrz connection to the ace1202t. if set to 1, the des parameters must be pre-programmed in both the ace1202r and ace1202t. bit 6 C rd_protect when programmed to 1, the user area registers can no longer be. once the rd_protect bit is set and the user area is read protected, no other writes to the rd_protect bit is possible. (the rd_protect bit is automatically write protected.) bit 7 C wr_protect if set to 1, it is no longer possible to write values into the user area. 8.5 rx_timeout register (addr. 0x61) the rx_timeout register determines the maximum length of time for a valid pwm bit. if a pwm bit period is valid, the timeout counter is reset allowing the ace1202r to receive the next bit of data. (the step size correction is 8.2ms.) if the lowpowerm bit of the options register is 0, once the ace1202r has timed out the receiver will enter into halt mode. however, if the lowpowerm bit is 1, the receiver will enter into a special low power mode using idle. (see section 9.0 for details.) 8.6 rxawake register (addr. 0x62) when ace1202r is connected in pwm mode, the rxawake register defines the number of cycles to power down the external rf module. the ace1202r s internal idle timer determines the timing (8192 us) for the power down cycles. (i.e. if a 10 decimal is written to the rxawake register the ace1202r resumes opera- tion after 81.92 ms.) this register is valid only if the lowpowerm bit of options register is programmed to 1. when ace1202r is connected in nrz mode, the rxawake register determines the ace1202t status inquire timing used to poll an external ace1202t on the communication lines. the step size in this mode is 50ms. 8.7 pulseout register (addr. 0x63) if the outstate bit of the mask_port register is 1, the pulse_out register defines the o1-o4 pulse duration that follows a valid received frame. the mask_port register also defines the polarity (active high or low) of this pulse (see section 8.8.) the timing step is 2.5ms. 8.8 mask_port register (addr. 0x64) the mask_port register defines the output pin polarity of the o1 through o4 and onr signals. if the respective bit is 0, the output pin is active high. if it is 1, the output pin is active low. bit 3 C outstate if the outstate bit is 0, the o1 through o4 output pins produce a stable binary level after the des frame is received. if the outstate bit is 1, the o1 through o4 output pins produce a pulse rather than a binary level with the pulse width defined by the pulse_out register. the mask_port register bits 0, 1, 4, and 5 define the polarity (active high or low) of each output. upon reception of the des frame, the data field (bit 7 to 4) information is decoded to determine which output(s) to apply the outstate condition to. bit 7 - out_toggle if out_toggle is 1, the outputs (o1 o4) selected by the data field, received in the des frame (bit 7 to 4), will change states every time a new frame is received. when no framed are received, the selected output(s) will maintain its state. however, if set to 0, the o1- o4 output behavior is dictated by the outstate selection. the out_toggle bit feature is valid only when the outstate is 0. 8.9 baud_adj register (addr. 0x65) the baud_adj register contains the auto-adjusted baud rate value. this value is automatically adjusted and should not be changed. 8.10 acerx_state register (addr. 0x66) the acerx_state register stores the current state of the receiver. it contains the value 0x33 if no des parameters are stored in the user area (blank from factory.) once the des information is transferred into the user area, the external programmer must take care to write the value 0x2a into this location. this information is used just to keep track of an external write access of the des user area. 8.11 factory data1 to 3 (0x6d to 0x6f) these unused locations could be programmed to hold user factory information such production date to track lot and testing information. 8.12 software revision (0x6f) contains the eeprom data version (0 to 0xf) and can be read through external programmer by asserting an inquire command (0x55.) figure 9 options register bit definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wr_protect rd_protect despar enalearn forceprogr lowpowerm forcenrz autocntr figure 10 mask_port register bit definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 out_toggle level_onr level o4 level o3 outstate x level o2 level o1
15 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 9.0 pwm mode the pwm mode is intended for use in rf transmissions. the bit coding is defined as 1/3 or 2/3 duty cycle to distinguish between coded 0 and 1 respectively. (see figure 11) a bit decoding algorithm will capture each single pulse transition (a rising to falling edge is ph and a falling to rising edge is pl .) the sum of the pulses will be compared to the min/max values. ph will then be subtracted from pl. the result is the bit to decode and will be shifted into a buffer: if (ph < pl) then bitdecode = 0 else bitdecode = 1 the decoding process is divided in two phases, sync decoding and message decoding. in sync decoding, the receiver is continuously shifting coded bit until a complete byte, which value corresponds to the sync field, is received. this condition is used to start the reception of the des message (2 nd phase) using a bit counter to determine the end of message. every time an out of range timing is found the process is restarted from phase 1 waiting for a new sync field. when the lowpowerm option is enabled, a special mode is used to minimize the total current consumption drawn by the receiving system. the pin onr is used to switch the rf-module power supply, as indicated in figure 14. the receiver active time is defined by register rx_timeout, while the power down phase is determined by register rxawake. in order to further reduce the current consumption, the ace1202r uses the idle mode. in this mode, the current drawn (ace1202r only) is typically 200 a @ 5.5v. the ace1202r exits idle mode every 8192 tcycles (whenever the idle timer underflows. 8 ) the value contained in rxawake is the number of idle cycles. before entering the active phase, the ace1202t has the possibil- ity to add a preamble field with programmable duration to consider the idle cycles in the active phase. (see figure 12) the example in figure 12 shows the waveform of the signals involved when rxwake = 4. the preamble has to be at least 5 idle cycles long to receive the message at the first frame. once exiting halt mode, the ace1202r waits at least rx_timeout * 2.5 ms before halt mode can be entered again. if a valid pwm bit is received before rx_timeout expires, the timeout will be set to the initial counting value. coded '0' coded '1' idle cycles onr rxin rx timeout * 8.2ms idle cycle = 8.2ms rxawake = 4 des frame preamble 4 1234 1 8 see the ace1202 product family datasheet at www.fairchildsemi.com for more details. figure 11 pwm encoding bits figure 12 receiver v cc switched mode
16 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 10.0 typical application circuit: the schematic in figure 13 shows a typical application where the ace1202r is used as a standalone module. the ace1202r takes care to switch the rf module power supply in order to minimize the power consumption. refer to the waveforms shown in figure 12 to see the relationship between received preamble and switching voltage. as described above, the preamble must be at least two vrf voltage cycles long, which allows the detection of an incoming signal at the very first frame. once a preamble is detected, the rf module is powered continuously. the incoming data stream is then decoded by the ace1202r. when the code has been completely received, the ace1202r will perform the following operations on the stored buffer: 1) checksum validation 2) fixed code presence 3) des validation 4) output result 5) auto-repetition control in cases where the current consumption is not an issue, the rf module can be powered directly from the vcc line. for this case, the ace1202r is in halt mode when there is no data detected on pin 11 (rxin), a rising edge on this pin will activate the ace1202r to decode an incoming message or return to sleep if no valid pwm bits are received. the lowpowerm bit in the options register must be 0 to disable the receiver switched mode. figure 13 low power receiver + 13 gnd 11 4 rxin onr 14 v cc +v r rf module ace1202r
17 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 11.0 nrz mode (bidirectional) the nrz mode is suited for wire operating applications such as software protection where the transmitter unit (ace1202t) can be connected through a dedicated connection to the receiver (ace1202r). to enable nrz mode, pin 4 and 5 must be high for at least 200ms following a power-on reset or an external reset (pin 10.) upon connection, the transmitter senses a polling message coming from the ace1202r txd line on pin 4 (rxd). the polling message contains two bytes. the transmitter uses the first byte (0x55) of the polling message to auto-calibrate its internal baud- rate. the second byte is a request from the receiver for the transmitter s status information. once the transmitter is cali- brated, the status information is sent. the status value can be: programmed (internal codes stored in ace1202t) blanked (not yet coupled with ace1202r) if ace1202r is connected to a blanked transmitter, it will automatically send a frame containing the fixed code, des key, and des counter. in order to send the des information, the bit despar in the options register must be set to 1 . the ace1202t will store this information in its user area and will reply to the ace1202r with a new status message informing the receiver of the change to programmed mode. once this information is received, the ace1202r will periodically transmit a status request message (0x55 + 0x55) to the transmitter. (the timing is defined in register rxawake with a 50ms step size.) the ace1202t will use the status request message to adjust the internal baud rate and answer with its internal status. at this point, the ace1202t responds with programmed. the ace1202r will then send the des coded message [des_frame] corresponding to the actual value of the des counter. the ace1202t will compare the information received with its internal des code. if a match is found, the next des code (obtained by incrementing the internal des counter) will be sent back to ace1202r for validation. if there is no match with the des code sent from the ace1202r, the same code will be sent back. once a validation cycle has completed, the value received in the data field (bit 7 to 5) is put onto the ace1202r output ports (o1 to o4). 7 8 5 4 wup/rxd onr/txd ace1202r ace1202t 6 4 txd rxd 2 6 o1 o2 o3 o4 figure 14 nrz connection
18 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 12.0 connection messages figure 15 shows the communication protocol between the ace1202t and the ace1202r. the ace1202r continuously sends an inquire message (0x55) to the ace1202t until the transmitter answer with its status information. when a blanked ace1202t is connected, the ace1202r provides the des infor- mation needed to perform the des algorithm 9 . the ace1202t will store the des key and counter and change its state to programmed. when the next inquire message is received by the ace1202t, it will inform the ace1202r that it is in the programmed state. the ace1202r will then send the next des code for validation by ace1202t. if the des code is acknowledge, the ace1202t will reply with the next des code (des counter is incremented by one) for validation by ace1202r. after the ace1202r des code is validated, the des counter is updated. otherwise, the old value is maintained and the data field contents will be placed on the outputs (o1-o4.) the data field is loaded with the contents of the datacode register (0x6c) defined in the ace1202t user area. figure 15. ace1202t (ace_t) with ace1202r (ace_r) connection 9 bit despar in the options register must be set to '1.' fixedhi fixedmid fixedlo key0 key1 key2 key3 key4 key5 cnt2 cnt3 cnt4 cnt5 cnt6 cnt7 chks 0x55 18 0x44 sync ace_t will store the des information changing the state to programmed 4 0x80 0x6d sw_rev chks 0x55 0x55 0x55 0x55 ace_t status inquire ace_t inquire ace_t ace_r ace_t blanked not connected connected fixedhi fixedmid fixedlo data cnt0 cnt1 roll2 roll3 chks 0x55 12 sync 4 0x80 0xe2 sw_rev chks 0x55 0x55 ace_t status inquire ace_t ace_r ace_t programmed connected des code @ counter fixedhi fixedmid fixedlo data cnt0 cnt1 roll2 roll3 chks 12 sync roll0 roll1 roll0 roll1 des code @ ++counter cycle is repeated sending another inquire tx command 0x55 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 5 ms stop bit start bit note: all the bytes transmitted or received must be spaced at least 5ms apart. a) communicating with a blanked ace_t b) communicating with a programmed ace_t c) serial data protocol
19 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 13.0 application circuits 13.1 stand alone receiver the stand alone receiver application circuit shows the possibility to synchronize an ace1202t without sending des information on rf that can compromise security if not done in a controlled environment. the ace1202t will be connected through programming interface driving the line e to ground. this will assert the ace1202r line lrn low forcing ace1202r to enter in programming mode. at this point, the ace1202r will send tx inquiry messages waiting for the ace1202t s status that must be blanked to allow des parameter downloading. (see section 11.0) when ace1202t is programmed, no further programming is possible and the only way to alter the des stored information is entering the program- ming mode with wr_protect option disabled and sending the eeprom write commands. once the ace1202r has transferred all the des information, it will continue to inquire the ace1202t checking the generation of the new des code. the process will continue as long as the pin 1 (lrn) is 0 . once the ace1202t is removed from programming connection, the pin 1 will go high and the programming routine is left waiting for a message on pin 11 (rf data). this mode is possible if bit forceprogr in options register is set. figure 16 receiver block with programming interface + 8 gnd 11 1 5 t+e - r 4 rxin lrn rxd onr/ txd 7 out1 14 v cc +v cc +v cc rf module +v cc 8 out2 2 out3 6 out4 9 o1 o2 o3 o4 rst reset
20 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 13.2 2-wire connection 10 the circuit in figure 17, shows how to implement a simple 2-wire connection between the ace1202t and the ace1202r. the line 'a' carries power supply and data information that is roughly one-volt modulation over the established dc voltage level. the power is delivered from the receiver unit while the transmitter acts as a passive key. if needed, the supply source can be inverted (the ace1202t is the source and the ace1202r is the passive element). capacitor c1 delivers current to ace1202t during the message modulation, on both ace1202t and ace1202r, and it is the key element to demodulate information sent. after connection, c1 is charged from r8 in a time faster than 50ms (this time required for the internal power-on reset circuit to operate correctly). after connection, both circuits (ace1202t and ace1202r) detect a nrz connection mode reading '1' on respec- tive rxd and txd lines. at this moment ace1202r starts to interrogate ace1202t with message 0x55 until it receives a status response from ace1202t. the process continues as indicated in section 11.0. the proposed circuit does not provide electrical protection in case the boards are connected to a non-compatible soure or extreme electrical noise. the led informs the user about the correct des algorithm acknowledge and des parameter stored. the use of this led is optional. figure 17. ace1202t/ace1202r 2-wire connection 10 component values and schematic not tested in a real application. + ace1202r gnd 7 gnd 5 4 rxd txd 7 14 v cc +5v r8 150 r6 270 t2 bc557 r7 10k r5 220k c3 100n c2 100n d3 1n414 decoded outputs 8 8 6 3 v cc led 2 6 o1 o2 o3 o4 d2 led a b d1 1n414 4 txd rxd r4 47k r3 2k2 r2 10k t1 bc557 ace1202t c1 10 r1 220
21 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 13.3 rf rke system with active/passive transmitter using the same 2-wire interface described in section 13.2, it is possible to build a rke system that allows the ace1202t to send information in pwm mode using the rf link or act as a passive key if connected through the 2-wire connection in nrz mode. the passive functionality could be employed as emergency enable/ disable of the system or to program des information into the ace1202t user area. in this case, the secret information is not sent through the rf channel.to enable this possibility, pin 1 (lrn) of the ace1202r must be connected to gnd. the system can work with or without a battery on the transmitter battery-holder. + + ace1202r module rf 13 7 gnd 5 11 4 rxd rxin txd 7 14 v cc gnd +5v r8 150 r6 270 t2 bc557 r7 10k +5v r5 220k c4 100n c3 100n c2 100n d5 1n4148 8 8 6 3 2 6 1 o1 o2 o3 o4 lrn d4 led a b d3 1n4148 4 txd k3/rxd r4 47k 5 2 1 v cc led k4 k2 k1 r3 2k2 to switches sw1, sw2, sw4 r2 10k t1 bc557 sw3 push-b ace1202t c1 10 d1 bar43 d2 bar43 3v lithium battery r1 220 rf tx stage figure 18. rke system with 2-wire interface
22 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 14.0 brown-out reset the brown-out reset (bor) function is a standard feature of the ace1202 product family used to hold the device in reset when vcc drops below a fixed threshold. (see bor electrical charac- teristics for threshold voltage.) while in reset, the device is held in its initial condition until v cc rises above the threshold value. shortly after v cc rises above the threshold value, an internal reset sequence is started. after the reset sequence, the core fetches the first instruction and starts normal operation. the bor should be used in situations when v cc rises and falls slowly and in situations when vcc does not fall to zero before rising back to operating range. the brown-out reset can be thought of as a supplement function to the power-on reset when v cc does not fall below ~1.5v. the power-on reset circuit works best when v cc starts from zero and rises sharply. so in applications where v cc is not constant, the bor will give added device stability. 76 1.8/2.2v ref. v cc bor comp to internal reset logic lbd control register + _ lbd comp + _ adj. reference voltage 543210 figure 19 bor/lbd block diagram
23 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver 15.0 power-on reset the power-on reset (por) circuit is guaranteed to work if the rate of rise of v cc is no slower than 10ms/1volt. the por circuit was designed to respond to fast low to high transitions between 0v and v cc . the circuit will not work if v cc does not drop to 0v before the next power-up sequence. in applications where 1) the vcc rise is slower than 10ms/1 volt or 2) v cc does not drop to 0v before the next power-up sequence the external reset option should be used. the external reset provides a way to properly reset the ace1202r if por cannot be used in the application. the external reset pin contains an internal pull-up resistor. therefore, to reset the device the reset pin should be held low for at least 2ms so that the internal clock has enough time to stabilize. figure 20 bor and por circuit relationship diagram v cc (pin 8) bor reset circuit output global reset to logic external reset pin (14-pin only) b a output por (pin 7) output v cc time bor output 1.75 0 v cc v cc 0 por output por output pulse 1.8v 0 v cc v cc 5.0v 0 the reset circuit will trigger when inputs a or b transition from high to low. at that time the global reset signal will go high which will reset all controller logic. the global reset will go high and stay high for around 1 s.
24 www.fairchildsemi.com ace1202r rev. a.6 ace1202r data encryption standard (des) receiver fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 physical dimensions inches (millimeters) unless otherwise noted molded small outline package (m) order number ACE1202REM package number m14a 123 4567 14 13 12 11 10 9 8 0.335 - 0.344 (8.509 - 8.788) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.014 (0.356) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ.

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