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| july 2007 rev 8 1/36 1 ST7LNB1Y0 diseqc? slave microcontroller for satcr based lnbs and switchers features clock, reset and supply management ? reduced power consumption ? safe power on/off management by low voltage detector (lvd) ? internal 8 mhz oscillator communication interface ? two diseqc tm communication interfaces ?four i 2 c communication interfaces i/o ports ? 4 output pins for control of a legacy matrix description the ST7LNB1Y0 is an 8-bit microcontroller dedicated to diseqc slave operation in satcr based lnbs (low-noise blocks) and switchers. figure 1. block diagram so16 narrow 8-bit core alu address and data bus reset drx2 8 mhz. rc osc internal clock control sda1 v ss power supply lvd/avd v dd i 2 c 1 scl1 drx1 sda2 i 2 c 2 scl2 sda3 / mat2 i 2 c 3 / scl3 / mat1 sda4 / mat4 i 2 c 4 / scl4 / mat3 13/18 v & 22 khz diseqc interface parameter dtx detector eeprom legacy matrix legacy matrix control control table 1. device summary features part number: ST7LNB1Y0m6 packages so16 narrow peripherals diseqc communication interface, 22 khz tone detector, 13/18 v detector operating voltage 4.5 to 5.5 v temperature range -40 to +85 c www.st.com
contents ST7LNB1Y0 2/36 contents 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 satcrs mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 ST7LNB1Y0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 diseqc-st commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2.1 command signalling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.2 look up tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 diseqc 1.0 command for legacy support . . . . . . . . . . . . . . . . . . . . . . . . 15 4 ST7LNB1Y0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 command 0fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 command 0dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4.1 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5.1 functional ems (ele ctromagnetic susceptib ility) . . . . . . . . . . . . . . . . . . 25 5.5.2 electromagnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.5.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 26 5.6 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ST7LNB1Y0 contents 3/36 5.6.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6.2 output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.7 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.7.1 asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 list of tables ST7LNB1Y0 4/36 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. satcrs implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. application types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. diseqc-st command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 table 6. odu_satcr_op (5ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. odu_satcr_inst(5bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. diseqc-st command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9. feeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 10. local oscillator frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 11. ST7LNB1Y0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 12. legacy commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 13. command 0fh format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 14. command 0dh format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 15. reply frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 16. ST7LNB1Y0 eeprom parame ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 17. truth table for support of 8 rf inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 18. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 19. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 20. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 21. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 22. operating conditions with low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 23. operating conditions with the diseqc? signalling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 24. supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 25. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 26. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 27. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 28. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 29. general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 30. output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 31. asynchronous reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 32. so16 16-pin plastic small outline-150mil width, package mechanical data . . . . . . . . . . . . 32 table 33. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 34. soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . . 33 table 35. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ST7LNB1Y0 list of figures 5/36 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. so16 narrow pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. ST7LNB1Y0 in the twin satcr and legacy (standard rf band) application . . . . . . . . . . . 8 figure 4. ST7LNB1Y0 in the twin satcr application with one input only . . . . . . . . . . . . . . . . . . . . . 9 figure 5. satcr control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. satcr control and legacy (standard rf band) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. satcr control and legacy (wide rf band) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. signalling of the diseqc-st command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. typical idd in run vs. fcpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12. two typical applications with unused i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. typical ipu vs. vdd with vin=vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14. typical vol at vdd=5 v (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 15. typical vol at vdd=5v (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 16. typical vdd-voh at vdd=5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 17. so16 16-pin plastic small outline -150mil width, package outline . . . . . . . . . . . . . . . . . . . 32 pin description ST7LNB1Y0 6/36 1 pin description figure 2. so16 narrow pinout 1. nc = not connected see ta bl e 2 for a description of the pin functions. table 2. pin functions pin number function name function description so16 1v ss ground 2v dd power supply (+5 volts) 3 reset reset (active low) input 4 dtx diseqc data transmit output 5drx1 (1) 1. if only one input is required by the applicat ion, drx1 must be used by default. diseqc-st (2) and legacy diseqc (3) 1.0 data receive input 2. diseqc-st: special diseqc command set for satcrs control (refer to section 3.2 for more details). 3. diseqc 1.0: refer to section 3.3 . 6 drx2 diseqc-st data receive input and diseqc- 1.0 with 13 to 18v transition (if a diseqc- command is sent before on drx1) 7,8 - not used (4) 4. unused pins must be tied to ground. 9sda4 / mat4i 2 c data line 4 / legacy matrix control line 4 10 scl4 / mat3 (5) 5. during normal operation this pin must not be pulled-down. i 2 c clock line 4 / legacy matrix control line 3 11 sda3 / mat2 i 2 c data line 3 / legacy matrix control line 2 12 scl3 / mat1 i 2 c clock line 3 / legacy matrix control line 1 13 sda2 i 2 c data line 2 14 scl2 i 2 c clock line 2 15 sda1 i 2 c data line 1 16 scl1 i 2 c clock line 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v ss v dd dtx nc nc drx2 drx1 reset scl1 sda1 sda4 / mat4 scl4 / mat3 sda3 / mat2 scl3 / mat1 sda2 scl2 ST7LNB1Y0 implementation 7/36 2 implementation 2.1 satcrs mapping the ST7LNB1Y0 could communicate through i 2 c with up to 8 satcrs (refer to ta bl e 3 ). the following hardware implementation of satcrs must be respected: table 3. satcrs implementation satcr number satcr (1) 1. as a convention, satcr1 must be associated to the bpf having the lowest center frequency of the application, satcr2 to the bpf having the next higher center frequency and so on. satcr address i 2 c line 0satcr 1 c8h i 2 c 1 1satcr 2 cah 2satcr 3 c8h i 2 c 2 3satcr 4 cah 4satcr 5 c8h i 2 c 3 5satcr 6 cah 6satcr 7 c8h i 2 c 4 7 satcr 8 / legacy satcr (for wide rf band applications) cah implementation ST7LNB1Y0 8/36 2.2 application example figure 3 and figure 4 show example application circuits for the ST7LNB1Y0 with and without legacy signal. figure 3. ST7LNB1Y0 in the twin satcr and legacy (standard rf band) application 1. the divider chain connected to the drx1 and drx2 pi ns must have the following resistance values: 330k ? and 100 k ? . 2. unused i 2 c lines (14,13) have to be linked to v cc through 12 k ? resistors. 3. rta-stb: remote tuning able set-top box (stb supporting satcr control). 4. the transistor is optional, it is used fo r eeprom parameters bytes reading using diseqc. 5. during normal operation this pin must not be pulled-down. 6. when the lvd is enabled (default state), it is mandatory not to connect a pull-up resi stor. a 10 nf pull-down capacitor is recommended to filter noise on the reset line. vss vdd reset dtx drx1 drx2 nc nc scl1 sda1 scl2 sda2 scl3 sda3 scl4 sda4 rta-stb input 100 k 330 k legacy or rta-stb input (3) 100 k 330 k 180 pf satcr 2 satcr 1 ST7LNB1Y0 v cc v cc 33 bc547 220 100 nf 180 f 100 nf legacy optional matrix control 12 k 12 k 12 k 12 k 0.01 f (6) (5) 100 nf ST7LNB1Y0 implementation 9/36 figure 4. ST7LNB1Y0 in the twin satcr application with one input only 1. nc = not connected. 2. the divider chain connected to the drx1 pins must have the following resistance values: 330 k ? and 100 k ? . 3. unused i 2 c lines (scl2,sda2) have to be linked to v cc through 12 k ? resistors. 4. rta-stb: remote tuning able set top box (stb supporting satcr control). 5. the transistor is optional, it is used fo r eeprom parameters bytes reading using diseqc. 6. during normal operation this pin must not be pulled-down. 7. when the lvd is enabled (default state), it is mandatory not to connect a pull-up resi stor. a 10 nf pull-down capacitor is recommended to filter noise on the reset line. rta-stb input (4) 100 k 330 k satcr 2 satcr 1 ST7LNB1Y0 v cc v cc 33 bc547 220 100 nf 180 pf optional 12 k 12 k 12 k 12 k 0.01 f (7) (6) 100 nf nc nc nc nc nc vss vdd reset dtx drx1 drx2 nc nc sda1 scl2 sda2 scl3 sda3 scl4 sda4 scl1 functional description ST7LNB1Y0 10/36 3 functional description 3.1 ST7LNB1Y0 applications the ST7LNB1Y0 is intended to be used in different lnb switcher applications supporting satcrs. three main types of applications could be distinguished (see ta b l e 4 ). an eeprom parameter will be used for config uring the ST7LNB1Y0 for a particular application type (refer to section 4 for more details on how to program the eeprom parameter). figure 5. satcr control block diagram figure 6. satcr control and legacy (standard rf band) table 4. application types num application type description 0 satcr control (1) (see figure 5 ) 1. this application could s upport up to 8 rf feeds. (applications 1 and 2 are limited to 4 rf feeds). ? control through i 2 c of up to 8 satcrs 1 satcr and legacy (standard rf band) (see figure 6 ) ? the ST7LNB1Y0 controls through i 2 c up to 4 satcrs ? control of a legacy matrix using up to 4 pins 2 satcr and legacy (wide rf band) (see figure 7 ) ? control though i 2 c of up to 6 satcrs + legacy ? control of a dedicated satcr for the legacy support satcr 1 matrix satcr 8 diseqc-st satcr x drx2 diseqc-st drx1 ST7LNB1Y0 ST7LNB1Y0 satcr 1 matrix satcr 4 diseqc 1.0 drx1 drx2 mat[1 to 4] diseqc-st ST7LNB1Y0 functional description 11/36 figure 7. satcr control and legacy (wide rf band) 3.2 diseqc-st commands to control satcr based lnbs and switchers, two new diseqc commands are used: odu_satcr_op (5ah): this command is used during lnb or switcher normal operation. odu_satcr_inst (5bh): this command is used only during the lnb or switcher installation. both commands frames must ha ve the following diseqc format: different subcommands are defined, depending on the data bytes which are sent (refer to ta bl e 6 and ta bl e 7 ). ST7LNB1Y0 satcr 1 matrix satcr 6 diseqc 1.0 drx1 diseqc-st drx2 legacy satcr table 5. diseqc-st command format e0h / e2h (1) diseqc slave address 5ah /5bh data1 data2 1. all commands accept e0h or e2h framin g. whatever the command, if e2h framin g is used, then the mcu sends at least the response e4h (refer to section 4.2 ). table 6. odu_satcr_op (5ah) sub-command data1 data2 command description 765 4:2 1 0 odu_changechannel satcr (1) feed (2) tu n [ 9 ] (3) tun[8] tun[7:0] this command is used for the channel selection. odu_poweroff satcr 0 00h this command is used to put a satcr in low power mode. 1. satcr: satcr number [0 to 7] (refer to table 3 ). 2. feed: matrix rf input [0 to 7] (refer to table 9 ). 3. tun[9:0]: tuning word. functional description ST7LNB1Y0 12/36 3.2.1 command signalling in order to be detected, the diseqc-st commands must be sent after a voltage change from 13 to 18 v. a delay time, t, between 4 ms and 24 ms must be respected before sending the diseqc-st commands (see figure 8 ). figure 8. signalling of the diseqc-st command table 7. odu_satcr_inst(5bh) sub-command data1 data2 command description 76543210 odu_config (1) satcr 00001 applinum (2) this command is sent by an rta-stb in order to determine the ST7LNB1Y0 application number. odu_lofreq (3) satcr 00010lofreqnum (4) this command is sent by the rta-stb in order to determine the l.o frequencies present in the lnb. odu_satcrxsignalon xx 00 xxh when receiving this command the ST7LNB1Y0 commands all the satcrs to send a tone in order to indicate their respective bpf center frequencies. 1. odu_config: when receiving this command the ST7LNB1Y0 che cks if the polonium indicated in data1 corresponds to the ST7LNB1Y0 application number, if it is the case the st 7lnb1y0 commands satcr indicated in data1 to send a tone having as frequency f = fbpf satcr else f = fbpf satcr + 20 mhz. 2. applinum: application number [1 to ffh] (refer to table 11 ). 3. odu_lofreq: when receiving this command the ST7LNB1Y0 chec ks if the lofreqnum indicated in data1 corresponds to the one of the l.os present in the application, if it is the case the ST7LNB1Y0 commands satcr indicated in data1 to send a tone having as frequency f = fbpf satcr else f = fbpf satcr + 20 mhz. 4. lofreqnum: local oscillat or table entry number [1 to ffh] (refer to table 10 ). table 8. diseqc-st command examples lnb diseqc frame description odu_config e0 00 5b 01 02 the stb asks if the application number is 2, the reply tone is expected from satcr 1 . odu_lofreq e0 10 5b 42 04 the stb asks if the lo frequency number 4 is present on the lnb, the reply tone is expected from satcr 3 . odu_change_channel e0 00 5a 24 55 the stb asks for a channel_change on satcr 2 with a tuning = 055h from matrix rf input = feed1. 13 v 18 v diseqc-st frame 24 ms t 4 ms ~ 1ms ST7LNB1Y0 functional description 13/36 3.2.2 look up tables table 9. feeds (1) 1. applications suppor ting legacy are limited to one satellite only (satellite a). feed rf input band polarization satellite 0lowverticala 1 high vertical a 2 low horizontal a 3 high horizontal a 4lowverticalb 5 high vertical b 6 low horizontal b 7 high horizontal b table 10. local oscillator frequencies lofreqnum (hex) local oscillator frequency standard rf band 00 none 01 not known 02 9.750 ghz 03 10.000 ghz 04 10.600 ghz 05 10.750 ghz 06 11.000 ghz 07 11.250 ghz 08 11.475 ghz 09 20.250 ghz 0a 5.150 ghz 0b 1.585 ghz 0c 13.850 ghz 0d not allocated 0e not allocated 0f not allocated functional description ST7LNB1Y0 14/36 wide rf band 10 none (switcher) 11 10.000 ghz 12 10.200 ghz 13 13.250 ghz 14 13.450 ghz 15 to 1f not allocated table 11. ST7LNB1Y0 applications application number (applinum) application 01 single satcr and legacy (standard rf band) 02 twin satcr (standard rf band) 03 twin satcr and legacy (standard rf band) 04 quad satcr (standard rf band) 05 double twin satcr (standard rf band) 06 twin satcr (wide rf band) 07 twin satcr and legacy (wide rf band) 08 quad satcr (wide rf band) 09 8 satcr (standard rf band) 0ah 6 satcr (standard rf band) 0bh quad satcr and legacy (standard rf band) 0ch to ffh tbd (1) 1. tbd stands for to be defined. table 10. local oscillator frequencies (continued) lofreqnum (hex) local oscillator frequency ST7LNB1Y0 functional description 15/36 3.3 diseqc 1.0 command for legacy support the diseqc 1.0 commands for the control of the legacy are the following: 00h : this command is used to rest ore the backwards compatibility. 38h : this command is used to write to port group command. for application supporting the legacy (except for application 1), th e backwards signalling (13/18 v, 22 khz tone) is recognized until a valid diseqc 1.0 command is detected. the following table presents the truth table for the legacy commands: table 12. legacy commands command 38h equivalent backwards signalling selected feed band polarity satellite e0 xx 38 f0 13v / 0 khz 0 low vertical a e0 xx 38 f1 13v / 22 khz 1 high vertical a e0 xx 38 f2 18v / 0 khz 2 low horizontal a e0 xx 38 f3 18v / 22 khz 3 high horizontal a ST7LNB1Y0 configuration ST7LNB1Y0 16/36 4 ST7LNB1Y0 configuration to configure the ST7LNB1Y0 for the required target application, a dedicated diseqc command is implemented. this configuration is stored in the ST7LNB1Y0 embedded eeprom location. 4.1 command 0fh ST7LNB1Y0 devices are shipped to customers with a default parameter value. these parameters can be updated using a dedicated 0fh diseqc command. this command has the following format where ?data? is the parameter value to be programmed at the ?index? location as shown in ta bl e 1 6 . note: the special command e0 xx 0f ff ff protects the eeprom data from any subsequent write access (where xx is the co rresponding diseqc slave address). 4.2 command 0dh for reading a parameter inside the eeprom a dedicated 0dh command has been added. the command format is described in ta b l e 1 4 , where ?index? is the address of the byte to be read from eeprom. the format of the reply frame is given in ta bl e 1 5 , format where ?data? is the byte read from eeprom. timings the time required to update a byte parameter (write and read operation) is 130 ms, while the time required to update all parameters is about 3.5 s. table 13. command 0fh format e0h diseqc slave address 0fh index data table 14. command 0dh format e2h (1) 1. e2h framing (and e4h resp onse) is supported from ve rsion 1.1 of the lnb1 software (previously, the command 0dh was implemented with e0h framing and the data response was without e4h framing). diseqc slave address 0dh (2) 2. after the command 0dh, there is a delay of 10ms before getting the reply frame. index table 15. reply frame format e4h data ST7LNB1Y0 ST7LNB1Y0 configuration 17/36 table 16. ST7LNB1Y0 eeprom parameters index parameter description default value 00 slave address diseqc slave address (1) 11h 01 satcr 1 bpf (lsb) (2) 5dh 02 satcr 1 bpf (msb) 02h 03 satcr 2 bpf (lsb) c6h 04 satcr 2 bpf (msb) 02h 05 satcr 3 bpf (lsb) 48h 06 satcr 3 bpf (msb) 03h 07 satcr 4 bpf (lsb) fch 08 satcr 4 bpf (msb) 03h 09 satcr 5 bpf (lsb) ffh 0a satcr 5 bpf (msb) ffh 0b satcr 6 bpf (lsb) ffh 0c satcr 6 bpf (msb) ffh 0d satcr 7 bpf(lsb) / legacy satcr low band (msb) (3) ffh 0e satcr 7 bpf(msb) / legacy satcr low band (lsb) ffh 0f satcr 8 bpf(lsb) / legacy satcr high band (msb) ffh 10 satcr 8 bpf(msb) / legacy satcr high band (lsb) ffh 11 applitype application type number (refer to ta bl e 4 ) 00h 12 applinum application number (refer to ta b l e 1 1 ) 04h 13 high l.o freq number refer to ta b l e 1 0 04h 14 low l.o freq number refer to ta b l e 1 0 02h ST7LNB1Y0 configuration ST7LNB1Y0 18/36 15 satcr 1 matrix truth table (4) ach 16 35h 17 satcr 2 matrix truth table 59h 18 6ah 19 satcr 3 matrix truth table 56h 1a 9ah 1b satcr 4 matrix truth table 95h 1c a6h 1d satcr 5 matrix truth table ffh 1e ffh 1f satcr 6 matrix truth table ffh 20 ffh 21 satcr 7 matrix truth table ffh 22 ffh 23 satcr 8 matrix truth table / legacy matrix ffh 24 ffh 25 satcrs gain (5) satcrs 1 to 4 gain ffh 26 satcrs 5 to 8 gain ffh 27 satcrs number (6) 04h 28 tuning step size (unit= 1mhz) 04h 29 software version number 14h 2a / 2b reserved (7) 1. besides the address defined in the eeprom at index 00h, addresses 10h and 00h are recognized also as valid addresses. 2. satcr x bpf = bpf x center frequency (mhz) / 2. 3. when an application supports the wide rf band only one local oscillat or with a frequency f lo is present in the lnb. in this case the selection of the high or the low band for t he legacy output is performed by a dedicated satcr. two parameters are needed for the band selection: - the tuning word for the low band selection = [(f lo (mhz) - f low (mhz) )/ 4] - 350: where f low corresponds to the low lo frequency. - the tuning word for the high band selection = [(f lo (mhz) - f high (mhz) )/4] - 350: where f high corresponds to the high band lo frequency. example: in a wide band application with f lo = 13250 mhz, for emulating a low band local oscillator at 9750 mhz, index 0dh and index 0eh must be loaded with the decimal value d = dec [0d:0e] = round ((13250-9750)/4) - 350 = 525. 4. matrix truth table for satcrx or legacy: - if 4 rf inputs are implemented then the matrix truth table has the follow ing coding on 2 bytes: ?aaaabbbb ccccdddd? where: aaaa= selection of feed1 on satcrx, aaaa = [mat4, mat3, mat2, mat1] bbbb= selection of feed0 on satcrx, bbbb = [mat4, mat3, mat2, mat1] cccc = selection of feed3 on satcrx , cccc = [mat4, mat3, mat2, mat1] dddd= selection of feed2 on satcrx,dddd = [mat4, mat3, mat2, mat1] - if 8rf inputs are implemented then the truth table given in table 17 is used. table 16. ST7LNB1Y0 eeprom parameters (continued) index parameter description default value ST7LNB1Y0 ST7LNB1Y0 configuration 19/36 5. in order to enable the support of 8 rf inputs: the value ? 0000h? has to be programmed in index 15h and 16h. satcrs gain value: it has the following format on two bytes: ?aabbccdd eeffgghh? where aa= gain for satcr 1 , bb = gain for satcr 2 , cc= gain for satcr 3 , dd=gain for satcr 4 , ee= gain for satcr 5 , ff= gain for satcr 6 , gg= gain for satcr 7 , hh=gain for satcr 8 or legacy satcr. upper case letters and upper case letters indicate lna and if gain, respectively. 6. satcrs number does not include the legac y satcr for the wide rf band applications. 7. reserved bytes: do not write to this location. table 17. truth table for support of 8 rf inputs feed mat1 mat2 mat3 mat4 0000 0 1100 0 2010 0 3110 0 4001 0 5101 0 6011 0 7111 0 electrical characteristics ST7LNB1Y0 20/36 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5 v for the 4.5 v v dd 5.5 v voltage range. they are given only as design guidelines and are not tested. 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 9 . figure 9. pin loading conditions c l st7 pin ST7LNB1Y0 electrical characteristics 21/36 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 10 . figure 10. pin input voltage 5.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in st7 pin table 18. voltage characteristics symbol ratings maximum value unit v dd - v ss supply voltage 7.0 v v in input voltage on any pin (1)(2) 1. directly connecting the i/o pins to v dd or v ss could damage the device if an unexpected change of the i/o configuration occurs (for example, due to a corrupt ed program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 10k ? for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics ST7LNB1Y0 24/36 5.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consumption, the two current values must be added. 5.4.1 supply current t a = ? 0 to +125 c unless otherwise specified figure 11. typical i dd in run vs. f cpu table 24. supply current characteristics symbol parameter conditions typ max unit i dd supply current in run mode (1) 1. 1. cpu running with memory access, all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by ex ternal square wave, lvd disabled. v dd = 5.5 v, f cpu =8 mhz 4.50 7 ma supply current for lnb or switcher applications (2) 2. 2. data based on typical st7lnb0 lnb or switcher application software running. 20 0.0 1.0 2.0 3.0 4.0 5.0 2.4 2.7 3.7 4.5 5 5.5 vdd (v) idd (ma) 8mhz 4mhz 1mhz ST7LNB1Y0 electrical characteristics 25/36 5.5 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. 5.5.1 functional ems (elect romagnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic ev ents until a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low st ate on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 25. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5 v, t a = +25 c, f osc = 8 mhz conforms to iec 1000-4-2 2b v fftb fast transient voltage burst limits to be applied through 100pf on v dd and v dd pins to induce a functional disturbance v dd = 5 v, t a = +25 c, f osc = 8 mhz conforms to iec 1000-4-4 3b electrical characteristics ST7LNB1Y0 26/36 5.5.2 electromagnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the board and the loading of each pin. 5.5.3 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22-a114a/a115a standard. table 26. emi characteristics (1) 1. data based on characterization results, not tested in production. symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit 1/4 mhz 1/8 mhz s emi peak level v dd = 5v, t a = +25c, so16 package, conforming to sae j 1752/3 0.1 mhz to 30 mhz 814 db v 30 mhz to 130 mhz 27 32 130 mhz to 1ghz 26 28 sae emi level 3.5 4 - table 27. absolute maximum ratings (1) 1. data based on characterization results, not tested in production. symbol ratings conditions maximum value 1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c 4000 v ST7LNB1Y0 electrical characteristics 27/36 static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. dlu : electrostatic discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the mi cro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards. for more details, refer to the application note an1181. table 28. electrical sensitivities (1) 1. 1. class description: a class is an stmicroelectronics internal specification. al l its limits are higher than the jedec specifications, that means when a device be longs to class a it exce eds the jedec standard. b class strictly covers all the je dec criteria (int ernational standard). symbol parameter conditions class 1) lu static latch-up class t a = +25c a dlu dynamic latch-up class v dd = 5.5 v, f osc = 4mhz, t a = +25 c a electrical characteristics ST7LNB1Y0 28/36 5.6 i/o port pin characteristics 5.6.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 12. two typical applications with unused i/o pin 1. only external pull-up allowed on iccclk pin. table 29. general characteristics symbol parameter conditions min typ max unit v il input low level voltage 0.3v dd v v ih input high level voltage 0.7v dd v hys schmitt trigger voltage hysteresis (1) 1. data based on characterization results, not tested in production. 400 mv i l input leakage current v ss v in v dd 1 a i s static current consumption (2) 2. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor (see figure 12 ). data based on design simulation and/or technology characte ristics, not tested in production. floating input mode 200 r pu weak pull-up equivalent resistor (3) 3. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics described in figure 13 ). v in = v ss , v dd =5 v 50 120 250 k ? c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time (1) c l =50 pf between 10% and 90% 25 ns t r(io)out output low to high level rise time (1) 25 10 k ? unused i/o port st7xxx 10 k ? unused i/o port st7xxx v dd ST7LNB1Y0 electrical characteristics 29/36 figure 13. typical i pu vs. v dd with v in =v ss 5.6.2 output driving current subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. 0 10 20 30 40 50 60 70 80 90 22.533.5 44.555.56 vdd(v) ip u (u a ) ta=140c ta=95c ta=25c ta=-45c table 30. output driving current characteristics symbol parameter conditions min max unit v ol (1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 14 ) v dd =5v i io =+5 ma 1.0 v i io =+2 ma 0.4 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 15 ) i io =+20 ma 1.3 i io =+8 ma 0.75 v oh (2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 16 ) i io =-5 ma v dd ? 1.5 i io =-2 ma v dd ? 0.8 1. the i io current sunk must always respect the absolute maximum rating specified in table 19 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect the absolute maximum rating specified in table 19 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . electrical characteristics ST7LNB1Y0 30/36 figure 14. typical v ol at v dd =5 v (standard) figure 15. typical v ol at v dd =5v (high sink) figure 16. typical v dd -v oh at v dd =5 v 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.0112345 lio (ma) vol at vdd=5v -45c 0c 25c 90c 130c 0.00 0.50 1.00 1.50 2.00 2.50 6 7 8 9 10152025303540 lio (ma) vol (v) at vdd=5v (hs) -45 0c 25c 90c 130c 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 -0.01-1-2-3-4-5 lio (ma) vdd-voh at vdd=5v -45c 0c 25c 90c 130c ST7LNB1Y0 electrical characteristics 31/36 5.7 control pin characteristics 5.7.1 asynchronous reset pin table 31. asynchronous reset pin characteristics (1)(2)(3) symbol parameter conditions min typ max unit v il input low level voltage 0.3v dd v v ih input high level voltage 0.7v dd v hys schmitt trigger voltage hysteresis (4) 1v v ol output low level voltage (5) v dd =5 v i io =+5ma 0.5 1.0 v i io =+2ma 0.2 0.4 r on pull-up equivalent resistor (4)(6) v dd =5v 20 40 80 k ? t w(rstl)out generated reset pulse duration internal reset sources 30 s t h(rstl)in external reset pulse hold time (7) 20 s t g(rstl)in filtered glitch duration (8) 200 ns 1. the output of the external reset circui t must have an open-drain output to drive t he st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). 2. whatever the reset source is (internal or external ), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 5.7.1 on page 31 . otherwise the reset will not be taken into account internally. 3. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin (by an external pull-up fo r example) is less than the abs olute maximum value specified for i inj(reset) in section table 19. on page 22 . 4. data based on characterization results, not tested in production. 5. the i io current sunk must always respect the absolute maximum rating specified in table 19 and the sum of i io (i/o ports and control pins) must not exceed i vss . 6. the r on pull-up equivalent resistor is based on a resi stive transistor. specified for voltage on reset pin between v ilmax and v dd . 7. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. 8. the reset network protects t he device against parasitic resets. package characteristics ST7LNB1Y0 32/36 6 package characteristics 6.1 package mechanical data figure 17. so16 16-pin plastic small outline -150mil width, package outline table 32. so16 16-pin plastic small outline-150mil width, package mechanical data dim. mm inches min typ max min typ max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 9.80 10.00 0.386 0.394 e 3.80 4.00 0.150 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n16 0016020 e h a1 c 45 a a1 b d e 16 9 1 8 l ST7LNB1Y0 package characteristics 33/36 6.2 thermal characteristics 6.3 soldering information in order to meet environmental requirements, st offers the ST7LNB1Y0 in ecopack ? package. the package have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at www.st.com , together with specific technical application note s covering the main technical aspects related to lead-free conversion (an2033, an2034, an2035, an2036). backward and forward compatibility the main difference between pb and pb-free soldering process is the temperature range. ecopack lqfp, sdip, so and qfn20 packages are fully compatible with lead (pb) containing soldering process (see application note an2034) tqfp, sdip and so pb-packages are compatible with lead-free soldering process, nevertheless it's the customer's duty to verify that the pb-packages maximum temperature (mentioned on the inner box label) is compatible with their lead-free soldering temperature. table 33. thermal characteristics symbol ratings value unit r thja package thermal resistance (junction to ambient) so16 85 c/w t jmax maximum junction temperature (1) 1. the maximum chip-junction temperature is based on technology characteristics. 150 c p dmax power dissipation (2) 2. the maximum power dissipation is obtained from the formula p d = (t j -t a ) / r thja . the power dissipation of an application can be defined by the user with the formula: p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation depending on the ports used in the application. so16 300 mw table 34. soldering compatibility (wave and reflow soldering process) package plating material devices pb solder paste pb-fr ee solder paste sdip & pdip sn (pure tin) yes yes (1) 1. assemblers must verify that the pb-package maxi mum temperature (mentioned on the inner box label) is compatible with their lead-free soldering process. qfn sn (pure tin) yes yes (1) lqfp and so nipdau (nickel-palladium-gold) yes yes (1) package characteristics ST7LNB1Y0 34/36 ST7LNB1Y0 diseqc? slave mi crocontroller option list (last update: july 2007) customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - package (tick one box) ST7LNB1Y0m6 - so16 narrow (16 pin) [ ] - eeprom parameters (any modified default settings [def] should be written in the custom boxes [cust]) index parameter def cust index parameter def cust 00 slave address 11h [ h] 11 applitype 00h [ h] 01 satcr1 bpf (lsb) 5dh [ h] 12 applinum 04h [ h] 02 satcr1 bpf (msb) 02h [ h] 13 high l.o freq number 04h [ h] 03 satcr2 bpf (lsb) c6h [ h] 14 low l.o freq number 02h [ h] 04 satcr2bpf (msb) 02h [ h] 15 satcr1 matrix truth table ach [ h] 16 35h [ h] 05 satcr3 bpf (lsb) 48h [ h] 17 satcr2 matrix truth table 59h [ h] 06 satcr3 bpf (msb) 03h [ h] 18 6ah [ h] 07 satcr4 bpf (lsb) fch [ h] 19 satcr3 matrix truth table 56h [ h] 1a 9ah [ h] 08 satcr4 bpf (msb) 03h [ h] 1b satcr4 matrix truth table 95h [ h] 09 satcr5 bpf (lsb) ffh [ h] 1c a6h [ h] 0a satcr5bpf (msb) ffh [ h] 1d satcr5 matrix truth table ffh [ h] 1e ffh [ h] 0b satcr6 bpf (lsb) ffh [ h] 1f satcr6 matrix truth table ffh [ h] 0c satcr6 bpf (msb) ffh [ h] 20 ffh [ h] 0d satcr7 bpf(lsb)/legacy 21 satcr7 matrix truth table ffh [ h] satcr low band(msb) ffh [ h] 22 ffh [ h] 0e satcr7 bpf(msb)/legacy 23 satcr8 matrix truth table/ ffh [ h] satcr low band (lsb) ffh [ h] 24 legacy matrix ffh [ h] 0f satcr8 bpf(lsb)/legacy 25 satcrs gain ffh [ h] satcr high band (msb)ffh [ h] 26 ffh [ h] 10 satcr8 bpf(msb)/legacy 27 satcrs number 04h [ h] satcr high band (lsb) ffh [ h] (please refer to ta b l e 1 6 in the datasheet for full descriptio ns and notes of eeprom parameters) customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . please download the latest version of this option list from: http://www.st.com/mcu > downloads > st7 microcontrollers > option list ST7LNB1Y0 revision history 35/36 7 revision history table 35. document revision history date revision description of changes 29-sep-2004 2.0 first release on st.com 10-nov-2004 3.0 note added, section 4.1: command 0fh e2h and e4h framing added for command 0dh, section 4.2: command 0dh 06-dec-2004 4.0 changed note 6 and figure 3 removed note on page 9. changed table 16: ST7LNB1Y0 eeprom parameters 28-jun-2005 5.0 changed note 4 in section 1: pin description changed note 5 in figure 3 added note 1 to section 3.2: diseqc-st commands changed timing in figure 8: signalling of the diseqc-st command changed table 11: ST7LNB1Y0 applications (added application for 0a and 0b) added frequencies in wide band part in table 10: local oscillator frequencies changed parameters in table 16: ST7LNB1Y0 eeprom parameters 12-oct-2005 6.0 changed package name to so16 narrow 31-jan-2006 7.0 modified notes for table 23: operating conditions with the diseqc? signalling related to diseqc signal detection levels capacitors changed from 100pf to 180pf in figure 3: ST7LNB1Y0 in the twin satcr and legacy (standard rf band) application 19-july-2007 8.0 document reformatted. qfn20 package removed root part number changed from st7lbn1 to ST7LNB1Y0. note 1 removed below table 30: output driving current characteristics . additional figure added for single-input application of twin satcr application, figure 4: ST7LNB1Y0 in the twin satcr application with one input only . thermal characteristics ( section 6.2 ) and soldering information ( section 6.3 ) updated option list updated and reformatted. ecopack package description updated in section 6.3: soldering information . ST7LNB1Y0 36/36 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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