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index of /ds/nm/ name last modified size description parent directory nm24c00.pdf 07-aug-98 00:00 83k nm24c02.pdf 09-feb-00 00:00 104k nm24c02u.pdf 22-dec-99 00:13 99k nm24c02u_nm24c03u.pdf 22-dec-99 00:13 99k nm24c02_03.pdf 09-feb-00 00:00 104k nm24c03.pdf 09-feb-00 00:00 104k nm24c03u.pdf 22-dec-99 00:13 99k nm24c04.pdf 09-feb-00 00:00 104k nm24c04u.pdf 22-dec-99 00:13 89k nm24c04u_nm24c05u.pdf 22-dec-99 00:13 89k nm24c04_05.pdf 09-feb-00 00:00 104k nm24c05.pdf 09-feb-00 00:00 104k nm24c05u.pdf 22-dec-99 00:13 89k nm24c08.pdf 09-feb-00 00:00 104k nm24c08u.pdf 22-dec-99 00:13 100k nm24c08u_nm24c09u.pdf 22-dec-99 00:13 100k nm24c08_09.pdf 09-feb-00 00:00 104k nm24c09.pdf 09-feb-00 00:00 104k nm24c09u.pdf 22-dec-99 00:13 100k nm24c16.pdf 09-feb-00 00:00 102k nm24c16u.pdf 22-dec-99 00:13 97k nm24c16u_nm24c17u.pdf 22-dec-99 00:13 97k nm24c16_17.pdf 09-feb-00 00:00 102k
nm24c17.pdf 09-feb-00 00:00 102k nm24c17u.pdf 22-dec-99 00:13 97k nm24c32.pdf 22-dec-99 00:13 87k nm24c32u.pdf 22-dec-99 00:13 89k nm24c65.pdf 22-dec-99 00:13 86k nm24c65u.pdf 22-dec-99 00:13 89k nm24w02.pdf 22-dec-99 00:13 104k nm24w04.pdf 22-dec-99 00:13 104k nm24w08.pdf 22-dec-99 00:13 104k nm24w16.pdf 22-dec-99 00:13 104k nm24wxx.pdf 22-dec-99 00:13 104k nm25c020.pdf 22-dec-99 00:13 108k nm25c040.pdf 22-dec-99 00:13 101k nm25c041.pdf 22-dec-99 00:13 79k nm25c160.pdf 22-dec-99 00:13 100k nm25c640.pdf 22-dec-99 00:13 93k nm25co20.pdf 07-aug-98 00:00 103k nm25co40.pdf 11-aug-98 00:00 103k nm27c010.pdf 22-dec-99 00:13 117k nm27c020.pdf 22-dec-99 00:13 119k nm27c040.pdf 22-dec-99 00:13 111k nm27c128.pdf 22-dec-99 00:13 112k nm27c210.pdf 22-dec-99 00:13 101k nm27c240.pdf 22-dec-99 00:13 96k nm27c256.pdf 22-dec-99 00:13 110k nm27c512.pdf 22-dec-99 00:13 105k NM27C520.pdf 22-dec-99 00:13 61k
NM27C520__524_288-bit+ 26-oct-98 00:00 61k nm27lv010.pdf 22-dec-99 00:13 100k nm27lv010b.pdf 22-dec-99 00:13 69k nm27lv210.pdf 22-dec-99 00:13 77k nm34c02.pdf 22-dec-99 00:13 90k nm34w02.pdf 22-dec-99 00:13 93k nm93c06.pdf 22-dec-99 00:13 88k nm93c46.pdf 22-dec-99 00:13 90k nm93c46a.pdf 22-dec-99 00:13 98k nm93c56.pdf 22-dec-99 00:13 89k nm93c56a.pdf 22-dec-99 00:13 104k nm93c66.pdf 22-dec-99 00:13 87k nm93c66a.pdf 22-dec-99 00:13 102k nm93c86a.pdf 22-dec-99 00:13 84k nm93c86au.pdf 15-may-99 00:00 83k nm93cs06.pdf 09-feb-00 00:00 164k nm93cs46.pdf 09-feb-00 00:01 163k nm93cs56.pdf 09-feb-00 00:01 163k nm93cs66.pdf 09-feb-00 00:01 163k nm95hs01.pdf 06-oct-98 16:47 144k nm95hs02.pdf 06-oct-98 16:47 144k nm95ms14.pdf 06-oct-98 16:47 112k nm95ms15.pdf 06-oct-98 16:47 117k nm95ms16.pdf 22-dec-99 00:13 138k nm95ms18.pdf 31-aug-98 10:58 140k nmc27c16b.pdf 22-dec-99 00:13 71k nmc27c32b.pdf 22-dec-99 00:13 70k
nmc27c64.pdf 22-dec-99 00:13 82k nmt2222.pdf 22-dec-99 00:13 160k nmt2907.pdf 22-dec-99 00:13 58k
1 www.fairchildsemi.com nm24c00 C 512-bit standard 2-wire bus interface serial eeprom preliminary july 1998 ? 1998 fairchild semiconductor corporation nm24c00 C 512-bit standard 2-wire bus interface serial eeprom general description the nm24c00 devices are 512 bits of cmos non-volatile electri- cally erasable memory. this device conforms to all specifications in the i 2 c? 2-wire protocol and is designed to minimize device pin count, and simplify pc board layout requirements. this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). fairchild eeproms are designed and tested for applications requiring high endurance, high reliability and low power consump- tion. block diagram features n extended operating voltage 2.7v C 5.5v n 400 khz clock frequency (f) n 500 m a active current typical 10 m a standby current typical 1 m a standby typical (l) 0.1 m a standby typical (lz) n i 2 c compatible interface C provides bidirectional data transfer protocol n self timed write cycle typical write cycle time of 6ms n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin so and 8-pin tssop n internal erase/write logic is disabled if v cc is below 3.8v (v cc = 5 10%). available on the 5v version nm24c00 (only). h.v. generation timing &control e 2 prom array ydec data register xdec control logic control logic word address counter d out ack slave address register & comparator start stop logic ck d in r/w sda scl v cc d out ds500068-1
2 www.fairchildsemi.com nm24c00 C 512-bit standard 2-wire bus interface serial eeprom connection diagrams so package (m8) and tssop package (mt8) top view see package number m08a and mtc8 pin names v ss ground sda data i/o scl clock input nc no internal connection v cc power supply nc nc nc v ss v cc nc scl sda 8 7 6 5 1 2 3 4 nm24c00 ds500068-2 ordering information nm 24 c xx f lz e xx letter description package m8 8-pin soic mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 m a standby current scl clock frequency blank 100khz f 400khz density 00 512bit c cmos technology interface 24 iic - 2 wire nm fairchild non-volatile memory
3 www.fairchildsemi.com nm24c00 C 512-bit standard 2-wire bus interface serial eeprom absolute maximum ratings ambient storage temperature C65 c to +150 c all input or output voltages with respect to ground 6.5v to C0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c00 0 c to +70 c nm24c00e -40 c to +85 c nm24c00v -40 c to +125 c positive power supply nm24c00 4.5v to 5.5v nm24c00l 2.7v to 5.5v nm24c00lz 2.7v to 5.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 100 khz 0.5 1.0 ma i sb standby current v in = gnd or v cc 10 50 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 100 khz 0.5 1.0 ma i sb standby current for l v in = gnd or v cc 110 m a (note 2) standby current for lz v in = gnd or v cc 0.1 1 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 1.0 mhz, v cc = 5v (note 1) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf note 1 : typical values are for t a = 25 c and nominal supply voltage (5v).
4 www.fairchildsemi.com nm24c00 C 512-bit standard 2-wire bus interface serial eeprom read and write cycle limits (standard and low v cc range - 2.7v-5.5v) symbol parameter 100 khz 400khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 m s t buf time the bus must be free before 4.7 1.3 m s a new transmission can start t hd:sta start condition hold time 4.0 0.6 m s t low clock low period 4.7 1.5 m s t high clock high period 4.0 0.6 m s t su:sta start condition setup time 4.7 0.6 m s (for a repeated start condition) t hd:dat data in hold time 0 0 m s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 m s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 m s t dh data out hold time 300 50 ns t wr write cycle time - nm24c00 10 10 ms (note 2) - nm24c00l, nm24c00lz 15 15 note 2 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c00 bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the device d oes not respond to its slave address. bus timing system layout sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc v cc ds500068-4 ds500068-5 note 3: due to open drain configuration of sda, a bus-level pull-up resistor is called for, (typical value = 4.7 k w ) scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto
5 www.fairchildsemi.com nm24c00 C 512-bit standard 2-wire bus interface serial eeprom definitions word 8 bits (byte) of data master any i 2 c device controlling the transfer of data (such as a microprocessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) pin descriptions scl serial clock this input is used to synchronize the data transfer from and to the device. sda serial data this is a bi-directional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal, therefore the sda bus requires a pull-up resistor to v cc . for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. noise protection the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. device operation the nm24c00 supports a bi-directional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions, while the nm24c00 works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. bus characteristics the following bus protocol has been defined: 1. data transfer may be initiated only when the bus is not busy. 2. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 1). bus not busy both data and clock lines remain high. start condition a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. stop condition a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. data valid the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one bit of data per clock pulse. each data transfer is initiated with a start condition and termi- nated with a stop condition. the number of the data bytes transferred between the start and stop conditions is deter- mined by the master device and is theoretically unlimited.
6 www.fairchildsemi.com nm24c00 C 512-bit standard 2-wire bus interface serial eeprom ds500068-7 start condition address or acknowledge valid data allowed to change stop condition scl sda (a) (b) (c) (d) (c) (a) bus characteristics (continued) acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. note: the nm24c00 does not generate any acknowledge bits if an internal programming cycle is in progress, the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that ha been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition (figure 2). 123456789123 data from transmitter data from transmitter acknowledge bit receiver must release the sda line at this point so the transmitter can continue sending data transmitter must release the sda line at this point allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data scl sda ds500068-8 device addressing after generating a start condition, the bus master transmits a control byte consisting of a slave address and an r/w bit that indicates what type of operation is to be performed. the slave address for the nm24c00 consists of a 4-bit device code (1010) followed by three "don't care" bits. data transfer sequence on the serial bus (figure 1) device select bits start bit acknowledge bit read/write bit slave address "don't care" bits 1 s 0 1 0xxx ack r/w ds500068-9 acknowledge timing (figure 2) control byte format (figure 3) the last bit of the control byte determines the operation to be performed. when set to a one a read operation is selected, and when set to a zero a write operation is selected (figure 3). the nm24c00 monitors the bus for its corresponding slave address all the time. it generates an acknowledge bit if the slave address was true and it is not in a programming mode.
7 www.fairchildsemi.com nm24c00 C 512-bit standard 2-wire bus interface serial eeprom write operations byte write following the start signal from the master, the device code (4 bits), the "don't care" bits (3 bits), and the r/w bit (which is a logic low) are placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after is has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the nm24c00. only the lower six address bits are used by the device, and the upper four bits are "don't cares." the nm24c00 will acknowledge the address byte and the master device will then transmit the data word to be written into the addressed memory location. the nm24c00 acknowledges again and the master generates a stop condition. this intiates the internal write cycle, and during this time the nm24c00 will not generate acknowledge signals (figure 4) . after a byte write command, the interal address counter will not be incremented and will point to the same address location that was just written. if a stop bit is transmitted to the device at any point in the write command sequence before the entire sequence is complete, then the command will abort and no data will be written. if more than 8 data bits are transmitted before the stop bit is sent, then the device will clear the previously loaded byte and begin loading the data buffer again. if more than one data byte is transmitted to the device and a stop bit is sent before a fill eight data bits have been transmitted, then the write command will abort and no data will be written. the nm24c00m8/mt8 employs a v cc threshold detector circuit which disables the internal pro- gramming circuit if v cc is below 3.8v. low v cc lockout nm24c00 provides data security against inadvertent writes that could potentially happen during the time the device is being powered on, powered down and brown out conditions by monitor- ing the v cc voltage during a write cycle. whenever a write cycle is started, the built-in circuitry starts to monitor the v cc level throughout the duration of the write command sequence until the master issues the required stop condition to start the actual internal write operation. if the sensed v cc voltage is below 3.8v at any point during this monitoring period, the device prohibits the write operation and does not generate the ack pulse. this low v cc lockout feature is only available for standard 5v device. acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack will be returned. if no ack is returned, then the start bit and control byte must be re-sent. if the cycle is complete,. then the device will return the ack and the master can then proceed with the next read or write command. see figure 5 for flow diagram. s t o p a c k p data a c k a c k s1010xxx0 xxxx s t a r t word address control byte bus activity: master sda line bus activity: nm24c00 x = "don't care" bit ds500068-10 byte write (figure 4) send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes acknowledge polling flow (figure 5) ds500068-11
8 www.fairchildsemi.com nm24c00 C 512-bit standard 2-wire bus interface serial eeprom read operations read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read, and sequential read. current address read the nm24c00 contains an address counter that maintains the address of the last word accessed, internally incremented by one. therefore, if the previous read operation was tp address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with the r/w bit set to one, the device issues an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the device discontinues transmission (figure 6). random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the device as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the control byte again but with the r/w bit set to a one. the nm24c00 will then issue an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the device discontinues transmission (figure 7). after this command, the internal address counter will point to the address location following the one that was just read. sequential read sequential reads are initiated in the same was as a random read except that after the device transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the device to transmit the next sequen- tially addressed 8-bit word (figure 8). to provide sequential reads the nm24c00 contains an internal address pointer which is incrmented by one at the completion of each read operation. this address pointer allows the entire memory to be serially read during one operation. current address read (figure 6) random read (figure 7) sequential read (figure 8) s t o p p data a c k no a c k s1010xxx1 s t a r t control byte bus activity: master sda line bus activity: nm24c00 x = "don't care" bit s t o p a c k no a c k control byte a c k a c k s t a r t s t a r t word address (n) control byte bus activity: master sda line bus activity: nm24c00 x = "don't care" bit s1 0 10xxx0 xxxx s1 01 0xxx1 p data n s t o p a c k no a c k bus activity: master sda line bus activity: nm24c00 p a c k data n + x a c k data n + 2 data n +1 data n a c k control byte ds500068-12 ds500068-13 ds500068-14
9 www.fairchildsemi.com nm24c00 C 512-bit standard 2-wire bus interface serial eeprom read operations (continued) random read (figure 9) sequential read (figure 10) s t o p a c k no a c k control byte a c k a c k s t a r t s t a r t word address (n) control byte bus activity: master sda line bus activity: nm24c00 x = "don't care" bit s1 0 10xxx0 xxxx s1 01 0xxx1 p data n s t o p a c k no a c k bus activity: master sda line bus activity: nm24c00 p a c k data n + x a c k data n + 2 data n +1 data n a c k control byte ds500068-18 ds500068-19
10 www.fairchildsemi.com nm24c00 C 512-bit standard 2-wire bus interface serial eeprom 8-pin molded small outline package (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
11 www.fairchildsemi.com nm24c00 C 512-bit standard 2-wire bus interface serial eeprom physical dimensions inches (millimeters) unless otherwise noted 8-pin molded tssop, jedec (mt8) package number mtc08 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
1 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom february 2000 ?1998 fairchild semiconductor corporation nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom general description the nm24c02/03 devices are 2048 bits of cmos non-volatile electrically erasable memory. these devices conform to all speci- fications in the standard iic 2-wire protocol and are designed to minimize device pin count, and simplify pc board layout require- ments. the upper half (upper 1kbit) of the memory of the nm24c03 can be write protected by connecting the wp pin to v cc . this section of memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by the fairchild family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. in order to implement higher eeprom memory densities on the iic bus, the extended iic protocol must be used. (refer to the nm24c32 or nm24c65 datasheets for more infor- mation.) fairchild eeproms are designed and tested for applications requir- ing high endurance, high reliability and low power consumption. block diagram features extended operating voltage 2.7v ?5.5v 400 khz clock frequency (f) at 2.7v - 5.5v 200 a active current typical 10 a standby current typical 1 a standby current typical (l) 0.1 a standby current typical (lz) iic compatible interface ?provides bi-directional data transfer protocol schmitt trigger inputs sixteen byte page write mode ?minimizes total write time per byte self timed write cycle typical write cycle time of 6ms hardware write protect for upper half (nm24c03 only) endurance: 1,000,000 data changes data retention greater than 40 years packages available: 8-pin dip, 8-pin so, and 8-pin tssop available in three temperature ranges - commercial: 0 to +70 c - extended (e): -40 to +85c - automotive (v): -40 to +125 c h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic ck d in r/w sda scl v ss wp v cc d out a2 a1 a0 ds500069-1
2 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom a0 a1 a2 v ss v cc nc scl sda 8 7 6 5 1 2 3 4 nm24c02 connection diagrams dual-in-line package (n), so package (m8) and tssop package (mt8) see package number n08e, m08a and mtc08 pin names a0,a1,a2 device address inputs v ss ground sda serial data i/o scl serial clock input nc no connection v cc power supply dual-in-line package (n), so package (m8) and tssop package (mt8) see package number n08e, m08a and mtc08 pin names a0,a1,a2 device address inputs v ss ground sda serial data i/o scl serial clock input wp write protect v cc power supply a0 a1 a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm24c03 ds500069-2 ds500069-3
3 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom ordering information nm 24 c xx f lz e xxx letter description package n 8-pin dip m8 8-pin soic mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current scl clock frequency blank 100khz f 400khz density 02 2k 03 2k with write protect c cmos technology interface 24 iic nm fairchild non-volatile memory
4 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom product specifications absolute maximum ratings ambient storage temperature 65 c to +150 c all input or output voltages with respect to ground 6.5v to 0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c02/03 0 c to +70 c nm24c02e/03e -40 c to +85 c nm24c02v/03v -40 c to +125 c positive power supply nm24c02/03 4.5v to 5.5v nm24c02l/03l 2.7v to 5.5v nm24c02lz/03lz 2.7v to 5.5v dc electrical characteristics (2.7v to 5.5v) symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd v cc = 2.7v - 5.5v 10 50 a or v cc v cc = 2.7v - 5.5v (l) 1 10 a v cc = 2.7v - 4.5v (lz) 0.1 1 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage of 5v for 4.5v-5.5v operation and at 3v for 2.7v-4.5v operation. note 2: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom ac test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.3 to v cc x 0.7 output load 1 ttl gate and c l = 100 pf bus timing ds500069-5 scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto 0.9v cc 0.1v cc 0.7v cc 0.3v cc read and write cycle limits (standard and low v cc range 2.7v - 5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before 4.7 1.3 s a new transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 1.5 s t high clock high period 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 20 20 ns t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 300 50 ns t wr write cycle time - nm24c02/03 10 10 ms (note 3) - nm24c02/03l, nm24c02/03lz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c02/03 bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the devic e does not respond to its slave address. refer "write cycle timing" diagram. ac testing input/output waveforms ds500069-4
6 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc v cc sda scl nm24c02/03 v cc v cc a0 a1 a2 v ss nm24c02/03 a0 a1 a2 v ss nm24c04/05 a1 a2 v ss nm24c08/09 a2 v ss v cc to v ss to v ss to v ss v cc v cc v cc to v cc to v ss to v ss to v cc to v ss to v cc typical system configuration note: due to open drain configuration of sda and scl, a bus-level pull-up resistor is called for, (typical value = 4.7k ? ) example of 16k of memory on 2-wire bus note: the sda pull-up resistor is required due to the open-drain/open collector output of iic bus devices. the scl pull-up resistor is recommended because of the normal scl line inactive 'high' state. it is recommended that the total line capacitance be less than 400pf device address pins present memory size # of page a0 a1 a2 blocks nm24c02/03 yes yes yes 2048 bits 1 nm24c04/05 no yes yes 4096 bits 2 nm24c08/09 no no yes 8192 bits 4 nm24c16/17 no no no 16,384 bits 8 ds500069-7 ds500069-8 ds500069-6 sda scl stop condition start condition word n 8th bit ack t wr write cycle timing note: the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
7 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom background information (iic bus) iic bus allows synchronous bi-directional communication be- tween a transmitter and a receiver using a clock signal (scl) and a data signal (sda). additionally there are up to three address signals (a2, a1 and a0) which collectively serve as "chip select signal" to a device (example eeprom) on the iic bus. all communication on the iic bus must be started with a valid start condition (by a master), followed by transmittal (by the master) of byte(s) of information (address/data). for every byte of information received, the addressed receiver provides a valid acknowledge pulse to further continue the communication unless the receiver intends to discontinue the communication. depending on the direction of transfer (write or read), the re- ceiver can be a slave or the master. a typical iic communi- cation concludes with a stop condition (by the master). addressing an eeprom memory location involves sending a command string with the following information: [device type] [device/page block selection] [r/w bit] {acknowledge pulse} [array address] slave address slave address is an 8-bit information consisting of a device type field (4bits), device/page block selection field (3bits) and read/ write bit (1bit). slave address format acknowledge acknowledge is an active low pulse on the sda line driven by an addressed receiver to the addressing transmitter to indicate receipt of 8-bits of data. the receiver provides an ack pulse for every 8-bits of data received. this handshake mechanism is done as follows: after transmitting 8-bits of data, the transmitter re- leases the sda line and waits for the ack pulse. the addressed receiver, if present, drives the ack pulse on the sda line during the 9th clock and releases the sda line back (to the transmitter). refer figure 3 . array address array address is an 8-bit information containing the address of a memory location to be selected within a page block of the device. 16k bit addressing limitation: standard iic specification limits the maximum size of eeprom memory on the bus to 16k bits. this limitation is due to the addressing protocol implemented which consists of the 8-bit slave address and an additional 8-bit field called array address. this array address selects 1 out of 256 locations (2 8 =256). since the data format of iic specification is 8-bit wide, a total of 256 x 8 = 2048 = 2k bit now becomes addressable by this 8-bit array address. this 2k bit is typically referred as a page block . combining this 8-bit array address with the 3-bit device/page address (part of slave address) allows a maximum of 8 pages (2 3 =8) of memory that can be addressed. since each page is 2k bit in size, 8 x 2k bit = 16k bit is the maximum size of memory that is addressable on the standard iic bus. this 16kb of memory can be in the form of a single 16kb eeprom device or multiple eeproms of varying density (in 2kb multiples) to a maximum total of 16kb. to address the needs of systems that require more than 16kb on the iic bus, a different specification called ex- tended iic specification is used. please refer to nm24c32xx datasheet for more information on extended iic specification. definitions word 8 bits (byte) of data page 16 sequential byte locations starting at a 16-byte address boundary, that may be pro- grammed during a "page write" programming cycle page block 2048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2048 bits master any iic device controlling the transfer of data (such as a microprocessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) device type identifier device/page block selection 1 0 1 0 a2 a1 a0 r/w (lsb) ds500069-9 device type iic bus is designed to support a variety of devices such as rams, eproms etc., along with eeproms. hence to properly identify various devices on the iic bus, a 4-bit device type identifier string is used. for eeproms, this 4-bit string is 1-0-1-0. every iic device on the bus internally compares this 4-bit string to its own device type string to ensure proper device selection. device/page block selection when multiple devices of the same type (e.g. multiple eeproms) are present on the iic bus, then the a2, a1 and a0 address information bits are also used as part of the slave address. every iic device on the bus internally compares this 3-bit string to its own physical configuration (a2, a1 and a0 pins) to ensure proper device selection. this comparison is in addition to the device type comparison. in addition to selecting an eeprom, these 3 bits are also used to select a page block within the selected eeprom. each page block is 2kbit (256bytes) in size. depend- ing on the density, an eeprom can contain from a minimum of 1 to a maximum of 8 page blocks (in multiples of 2) and selection of a page block within a device is by using a2, a1 and a0 bits. read/write bit last bit of the slave address indicates if the intended access is read or write. if the bit is "1," then the access is read, whereas if the bit is "0," then the access is write.
8 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom eeprom number of device selection inputs address bits density page blocks provided selecting page block 2k bit 1 a0 a1 a2 none 4k bit 2 a1 a2 a0 8k bit 4 a2 a0 and a1 16k bit 8 a0, a1 and a2 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bi-directional pin used to transfer data into and out of the device. it is an open drain output and may be wire ored with any number of open drain or open collector outputs. write protect (wp) (nm24c03 only) if tied to v cc , program operations onto the upper half (upper 1kbit) of the memory will not be executed. read operations are possible. if tied to v ss , normal operation is enabled, read/ write over the entire memory is possible. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. this pin has an internal pull-down circuit. however, on systems where write protection is not required it is recommended that this pin is tied to v ss . device selection inputs a2, a1 and a0 (as appropriate) these inputs collectively serve as chip select signal to an eeprom when multiple eeproms are present on the same iic bus. hence these inputs, if present, should be connected to v cc or v ss in a unique manner to allow proper selection of an eeprom amongst multiple eeproms. during a typical addressing se- quence, every eeprom on the iic bus compares the configura- tion of these inputs to the respective 3 bit device/page block selection information (part of slave address) to determine a valid selection. for e.g. if the 3 bit device/page block selection is 1- 0-1, then the eeprom whose device selection inputs (a2, a1 and a0) are connected to v cc -v ss -v cc respectively, is selected. depending on the density, only appropriate number of device selection inputs are provided on an eeprom. for every device selection input that is not present on the device, the correspond- ing bit in the device/page block selection field is used to select a page block within the device instead of the device itself. following table illustrates the above: note that even when just one eeprom present on the iic bus, these pins should be tied to v cc or v ss to ensure proper termina- tion. device operation the nm24c02/03 supports a bi-directional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm24c02/03 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figure 1 and figure 2 on next page. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24c02/ 03 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24c02/03 to place the device in the standby power mode, except when a write operation is being executed, in which case a second stop condition is required after t wr period, to place the device in standby mode.
9 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom data validity (figure 1) start and stop definition (figure 2) scl from master data output from transmitter data output from receiver 189 start condition acknowledge pulse t aa t dh sda scl start condition stop condition scl data stable data change sda ds500069-10 ds500069-11 ds500069-12 acknowledge response from receiver (figure 3)
10 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom acknowledge the nm24c02/03 device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm24c02/03 will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the nm24c02/03 slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected, nm24c02/03 will continue to transmit data. if an acknowledge is not detected,nm24c02/03 will terminate further data transmissions and await the stop condition to return to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier. this is fixed as 1010 for all eeprom devices. refer the following table for slave addresses string details: device a0 a1 a2 page page block blocks addresses nm24c02/03 a a a 1 (none) a: refers to a hardware configured device address pin. all iic eeproms use an internal protocol that defines a page block size of 2k bits (for word addresses 0x00 through 0xff). therefore, address bits a0, a1, or a2 (if designated 'p') are used to access a page block in conjunction with the word address used to access any individual data byte. the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the nm24c02/03 recognizes the start condition, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions. device type identifier device address 1 0 1 0 a2 a1 a0 r/w (lsb) nm24c02/03
11 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom write operations byte write for a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. upon receipt of the byte address the nm24c02/03 responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24c02/ 03 begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the nm24c02/03 inputs are disabled, and the device will not respond to any requests from the master for the duration of t wr . refer to figure 4 for the address, acknowledge and data transfer sequence. page write to minimize write cycle time, nm24c02/03 offer page write feature, by which, up to a maximum of 16 contiguous bytes locations can be programmed all at once (instead of 16 individual byte writes). to facilitate this feature, the memory array is orga- nized in terms of pages. a page consists of 16 contiguous byte locations starting at every 16-byte address boundary (for ex- ample, starting at array address 0x00, 0x10, 0x20 etc.). page write operation limits access to byte locations within a page. in other words a single page write operation will not cross over to locations on another page but will roll over to the beginning of the page whenever end of page is reached and additional locations are a continued to be accessed. a page write operation can be initiated to begin at any location within a page (starting address of the page write operation need not be the starting address of a page). s t o p bus activity: master sda line bus activity: eeprom data n + 15 data n + 1 data n word address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master sda line bus activity: eeprom ds500069-13 ds500069-14 page write is initiated in the same manner as the byte write operation; but instead of terminating the cycle after transmitting the first data byte, the master can further transmit up to 15 more bytes. after the receipt of each byte, nm24c02/03 will respond with an acknowledge pulse, increment the internal address counter to the next address and is ready to accept the next data. if the master should transmit more than sixteen bytes prior to generat- ing the stop condition, the address counter will roll over and previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 5 for the address, acknowledge and data transfer sequence. acknowledge polling once the stop condition is issued to indicate the end of the host s write operation the nm24c02/03 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24c02/03 is still busy with the write operation no ack will be returned. if the nm24c02/03 has completed the write operation an ack will be returned and the host can then proceed with the next read or write operation. write protection (nm24c03 only) programming of the upper half (upper 1kbit) of the memory will not take place if the wp pin of the nm24c03 is connected to v cc . the nm24c03 will respond to slave and byte addresses; but if the memory accessed is write protected by the wp pin, the nm24c03 will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. byte write (figure 4) page write (figure 5)
12 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom s t o p a c k no a c k slave address a c k a c k s t a r t s t a r t word address slave address bus activity: master sda line bus activity: eeprom data n s t o p a c k bus activity: master sda line bus activity: eeprom a c k data n + x a c k data n + 2 data n +1 data n +1 a c k no a c k slave address ds500069-16 ds500069-17 read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the nm24c02/03 contains an address counter that maintains the address of the last byte accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the nm24c02/03 issues an acknowledge and transmits the eight bit byte. the master will not acknowledge the transfer but does generate a stop condition, and therefore the nm24c02/03 discontinues transmission. refer to figure 6 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address with the r/w bit set to zero and then the byte address it is to read. after the byte address acknowledge, the master immediately issues another start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the nm24c02/03 and then by the eight bit byte. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24c02/03 discontinues transmission. refer to figure 7 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24c02/03 continues to output data for each ac- knowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" to the beginning of the memory. nm24c02/03 continues to output data for each acknowledge received. refer to figure 8 for the address, acknowledge, and data transfer sequence. current address read (figure 6) s t o p data a c k no a c k s t a r t slave address bus activity: master sda line bus activity: eeprom 1 0 1 0 1 ds500069-15 random read (figure 7) sequential read (figure 8)
13 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom 8-pin molded small outline package (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 8-pin molded thin shrink small outline package (mt8) package number mtc08 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
14 www.fairchildsemi.com nm24c02/03 rev. g nm24c02/03 C 2k-bit standard 2-wire bus interface serial eeprom physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident
1 www.fairchildsemi.com nm24c02u/nm24c03u rev. b.1 nm24c02u/nm24c03u C 2k-bit serial eeprom 2-wire bus interface august 1999 ?1998 fairchild semiconductor corporation nm24c02u/nm24c03u 2k-bit serial eeprom 2-wire bus interface general description the nm24c02u/nm24c03u are 2k (2,048) bit serial interface cmos eeproms (electrically erasable programmable read- only memory). these devices fully conform to the standard i 2 c 2-wire protocol which uses clock (scl) and data i/o (sda) pins to synchronously clock data between the "master" (for example a microprocessor) and the "slave" (the eeprom device). in addi- tion, the serial interface allows a minimal pin count packaging designed to simplify pc board layout requirements and offers the designer a variety of low voltage and low power options. nm24c03u incorporates a hardware "write protect" feature, by which, the upper half of the memory can be disabled against programming by connecting the wp pin to v cc . this section of memory then effectively becomes a rom (read-only memory) and can no longer be programmed as long as wp pin is connected to v cc . fairchild eeproms are designed and tested for applications requir- ing high endurance, high reliability and low power consumption for a continuously reliable non-volatile solution for all markets. block diagram functions i 2 c compatible interface 2,048 bits organized as 256 x 8 extended 2.7v ?5.5v operating voltage 100 khz or 400 khz operation self timed programming cycle (6ms typical) "programming complete" indicated by ack polling nm24c03u: memory "upper block" write protect pin features the i 2 c interface allows the smallest i/o pincount of any eeprom interface 16 byte page write mode to minimize total write time per byte typical 200 a active current (i cca ) typical 1 a standby current (i sb ) for "l" devices and 0.1 a standby current for "lz" devices endurance: up to 1,000,000 data changes data retention greater than 40 years h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic ck d in r/w sda scl v ss wp v cc d out a2 a1 a0 ds800007-1 i 2 c is a registered trademark of philips electronics n.v.
2 www.fairchildsemi.com nm24c02u/nm24c03u rev. b.1 nm24c02u/nm24c03u C 2k-bit serial eeprom 2-wire bus interface a0 a1 a2 v ss v cc nc scl sda 8 7 6 5 1 2 3 4 connection diagrams dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e, m08a, and mtc08 pin names a0,a1,a2 device address inputs v ss ground sda serial data i/o scl serial clock input nc no connection v cc power supply dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e, m08a, and mtc08 pin names a0,a1,a2 device address inputs v ss ground sda serial data i/o scl serial clock input wp write protect v cc power supply a0 a1 a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm24c02u nm24c03u ds800007-2 ds800007-3
3 www.fairchildsemi.com nm24c02u/nm24c03u rev. b.1 nm24c02u/nm24c03u C 2k-bit serial eeprom 2-wire bus interface ordering information nm 24 c xx u f lz e xx letter description package n 8-pin dip m8 8-pin soic mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current scl clock frequency blank 100khz f 400khz ultralite cs100ul process density 02 2k 03 2k with write protect c cmos technology w total array write protect interface 24 iic nm fairchild non-volatile memory
4 www.fairchildsemi.com nm24c02u/nm24c03u rev. b.1 nm24c02u/nm24c03u C 2k-bit serial eeprom 2-wire bus interface product specifications absolute maximum ratings ambient storage temperature 65 c to +150 c all input or output voltages with respect to ground 6.5v to 0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c02u/03u 0 c to +70 c nm24c02ue/03ue -40 c to +85 c nm24c02uv/03uv -40 c to +125 c positive power supply nm24c02u/03u 4.5v to 5.5v nm24c02ul/03ul 2.7v to 5.5v nm24c02ulz/03ulz 2.7v to 5.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd or v cc 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd v cc = 2.7v - 4.5v 1 10 a or v cc v cc = 2.7v - 4.5v 0.1 1 a v cc = 4.5v - 5.5v 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm24c02u/nm24c03u rev. b.1 nm24c02u/nm24c03u C 2k-bit serial eeprom 2-wire bus interface ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf read and write cycle limits (standard and low v cc range) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before 4.7 1.3 s a new transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 1.5 s t high clock high period 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 300 50 ns t wr write cycle time - nm24c02u/03u 10 10 ms (note 3) - nm24c02u/03ul, nm24c02u/03ulz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c02u/03u bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the dev ice does not respond to its slave address.
6 www.fairchildsemi.com nm24c02u/nm24c03u rev. b.1 nm24c02u/nm24c03u C 2k-bit serial eeprom 2-wire bus interface sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc v cc sda scl nm24c02u/03u v cc v cc a0 a1 a2 v ss nm24c02u/03u a0 a1 a2 v ss nm24c04u/05u a1 a2 v ss nm24c08u/09u a2 v ss v cc to v cc or v ss to v cc or v ss to v cc or v ss to v cc or v ss v cc v cc v cc bus timing system layout typical system configuration note: due to open drain configuration of sda, a bus-level pull-up resistor is called for, (typical value = 4.7k ? ) example of 16k of memory on 2-wire bus note: the sda pull-up resistor is required due to the open-drain/open collector output of iic bus devices. the scl pull-up resistor is recommended because of the normal scl line inactive 'high' state. it is recommended that the total line capacitance be less than 400pf device address pins memory size # of page a0 a1 a2 blocks nm24c02u/03u adr adr adr 2048 bits 1 ds800007-8 ds800007-20 ds800007-9 scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto
7 www.fairchildsemi.com nm24c02u/nm24c03u rev. b.1 nm24c02u/nm24c03u C 2k-bit serial eeprom 2-wire bus interface device operation inputs (a0, a1, a2) device address pins a0, a1, and a2 are connected to v cc or v ss to configure the eeprom chip address. table i shows the active pins. table 1. device a0 a1 a2 effects of addresses nm24c02u/03u adr adr adr 2 3 = 8; 8*x (1x2k)** = 16k * max # of devices on bus ** number of page blocks per density under the standard iic protocol, the maximum density address- able using the three pin configuration of the iic protocol is 16k. any combination of densities can be used up to this limit. background information (iic bus) as mentioned, the iic bus allows synchronous bidirectional com- munication between transmitter/receiver using the scl (clock) and sda (data i/o) lines. all communication must be started with a valid start condition, concluded with a stop condition and acknowledged by the receiver with an acknowledge condi- tion. hardware configuring the a0, a1, and a2 pins (device address pins) with pull-up or pull-down to v cc or v ss . all unused pins must be grounded (tied to v ss ). software addressing the required page block within the device memory array (as sent in the slave address string). for devices with densities greater than 16k, a different protocol, the extended iic protocol, is used. refer to nm24c32u datasheet (for example) for additional details. addressing an eeprom memory location involves sending a command string with the following information: [device type] [device address] [page block ad- dress] [byte address] definitions word 8 bits (byte) of data page 16 sequential addresses (one byte each) that may be programmed during a 'page write' programming cycle page block 2048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2048 bits master any iic device controlling the transfer of data (such as a microprocessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire ored with any number of open drain or open collector outputs. wp write protection (nm24c03u only) if tied to v cc , program operations onto the upper half of the memory will not be executed. read operations are possible. if tied to v ss , normal operation is enabled, read/write over the entire memory is possible. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. device operation the nm24c02u/03u supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm24c02u/03u will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figure 2 and figure 3 on next page. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24c02u/03u continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24c02u/03u to place the device in the standby power mode. write cycle timing acknowledge acknowledge is a hardware convention used to indicate success- ful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line to low to acknowledge that it received the eight bits of data. refer to figure 4.
8 www.fairchildsemi.com nm24c02u/nm24c03u rev. b.1 nm24c02u/nm24c03u C 2k-bit serial eeprom 2-wire bus interface ds800007-10 sda scl stop condition start condition word n 8th bit ack t wr write cycle timing (figure 1) note: the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. data validity (figure 2) start and stop definition (figure 3) acknowledge response from receiver (figure 4) scl from master data output from transmitter data output from receiver 189 start acknowledge sda scl start condition stop condition scl data stable data change sda ds800007-11 ds800007-12 ds800007-13
9 www.fairchildsemi.com nm24c02u/nm24c03u rev. b.1 nm24c02u/nm24c03u C 2k-bit serial eeprom 2-wire bus interface device type identifier device address 1 0 1 0 a2 a1 a0 r/w (lsb) nm24c02u/03u ds800007-14 write cycle timing (continued) the nm24c02u/03u device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm24c02u/03u will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the nm24c02u/03u slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier ( see figure 5) . this is fixed as 1010 for all eeprom devices. slave addresses (figure 5) refer to the following table for slave addresses string details: device a0 a1 a2 page page block blocks addresses nm24c02u/03u a a a 1 (none) a: refers to a hardware configured device address pin. all iic eeproms use an internal protocol that defines a page block size of 2k bits (for word addressess 0000 through 1111). therefore, address bits a0, a1, or a2 (if designated 'p') are used to access a page block in conjunction with the word address used to access any individual data byte (word). the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the nm24c02u/03u recognizes the start condition, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions.
10 www.fairchildsemi.com nm24c02u/nm24c03u rev. b.1 nm24c02u/nm24c03u C 2k-bit serial eeprom 2-wire bus interface write operations byte write for a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. upon receipt of the byte address the nm24c02u/03u responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24c02u/03u begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the nm24c02u/03u inputs are disabled, and the device will not respond to any requests from the master. refer to figure 6 for the address, acknowledge and data transfer sequence. page write the nm24c02u/03u is capable of a sixteen byte page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to fifteen more bytes. after the receipt of each byte, the nm24c02u/03u will respond with an acknowledge. after the receipt of each byte, the internal address counter increments to the next address and the next sda data is accepted. if the master should transmit more than sixteen bytes prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 7 for the address, acknowl- edge, and data transfer sequence. s t o p bus activity: master sda line bus activity: nm24c02u/03u data n + 15 data n + 1 data n word address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master sda line bus activity: nm24c02u/03u ds800007-15 ds800007-16 acknowledge polling once the stop condition is issued to indicate the end of the host s write operation the nm24c02u/03u initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24c02u/03u is still busy with the write operation no ack will be returned. if the nm24c02u/03u has completed the write operation an ack will be returned and the host can then proceed with the next read or write operation. write protection (nm24c03u only) programming of the upper half of the memory will not take place if the wp pin of the nm24c03u is connected to v cc . the nm24c03u will accept slave and byte addresses; but if the memory accessed is write protected by the wp pin, the nm24c03u will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. byte write (figure 6) page write (figure 7)
11 www.fairchildsemi.com nm24c02u/nm24c03u rev. b.1 nm24c02u/nm24c03u C 2k-bit serial eeprom 2-wire bus interface s t o p a c k no a c k slave address a c k a c k s t a r t s t a r t word address slave address bus activity: master sda line bus activity: nm24c02u/03u data n s t o p a c k bus activity: master sda line bus activity: nm24c02u/03u a c k data n + x a c k data n + 2 data n +1 data n +1 a c k no a c k slave address ds800007-18 ds800007-19 read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the nm24c02u/03u contains an address counter that maintains the address of the last byte accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the nm24c02u/03u issues an acknowledge and transmits the eight bit byte. the master will not acknowledge the transfer but does generate a stop condition, and therefore the nm24c02u/ 03u discontinues transmission. refer to figure 8 for the se- quence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address and then the byte address it is to read. after the byte address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the nm24c02u/03u and then by the eight bit data. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24c02u/03u discontinues transmission. refer to figure 9 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24c02u/03u continues to output data for each acknowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" and the nm24c02u/03u continues to output data for each acknowledge received. refer to figure 10 for the address, acknowledge, and data transfer sequence. current address read (figure 8) s t o p data a c k no a c k s t a r t slave address bus activity: master sda line bus activity: nm24c02u/03u ds800007-17 random read (figure 9) sequential read (figure 10)
12 www.fairchildsemi.com nm24c02u/nm24c03u rev. b.1 nm24c02u/nm24c03u C 2k-bit serial eeprom 2-wire bus interface 8-pin molded small outline package (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 8-pin molded thin shrink small outline package package number mtc08 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
13 www.fairchildsemi.com nm24c02u/nm24c03u rev. b.1 nm24c02u/nm24c03u C 2k-bit serial eeprom 2-wire bus interface physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident
1 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom february 2000 ?1998 fairchild semiconductor corporation nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom general description the nm24c04/05 devices are 4096 bits of cmos non-volatile electrically erasable memory. these devices conform to all speci- fications in the standard iic 2-wire protocol and are designed to minimize device pin count, and simplify pc board layout require- ments. the upper half (upper 2kbit) of the memory of the nm24c05 can be write protected by connecting the wp pin to v cc . this section of memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by the fairchild family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. in order to implement higher eeprom memory densities on the iic bus, the extended iic protocol must be used. (refer to the nm24c32 or nm24c65 datasheets for more infor- mation.) fairchild eeproms are designed and tested for applications requir- ing high endurance, high reliability and low power consumption. block diagram features extended operating voltage 2.7v ?5.5v 400 khz clock frequency (f) at 2.7v - 5.5v 200 a active current typical 10 a standby current typical 1 a standby current typical (l) 0.1 a standby current typical (lz) iic compatible interface ?provides bi-directional data transfer protocol schmitt trigger inputs sixteen byte page write mode ?minimizes total write time per byte self timed write cycle typical write cycle time of 6ms hardware write protect for upper half (nm24c05 only) endurance: 1,000,000 data changes data retention greater than 40 years packages available: 8-pin dip, 8-pin so, and 8-pin tssop available in three temperature ranges - commercial: 0 to +70 c - extended (e): -40 to +85c - automotive (v): -40 to +125 c h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic ck d in r/w sda scl v ss wp v cc d out a2 a1 ds500070-1
2 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom nc a1 a2 v ss v cc nc scl sda 8 7 6 5 1 2 3 4 nm24c04 connection diagrams dual-in-line package (n), so package (m8) and tssop package (mt8) see package number n08e, m08a and mtc08 pin names a1,a2 device address inputs v ss ground sda serial data i/o scl serial clock input nc no connection v cc power supply dual-in-line package (n), so package (m8) and tssop package (mt8) see package number n08e, m08a and mtc08 pin names a1,a2 device address inputs v ss ground sda serial data i/o scl serial clock input wp write protect v cc power supply nc no connection nc a1 a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm24c05 ds500070-2 ds500070-3
3 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom ordering information nm 24 c xx f lz e xxx letter description package n 8-pin dip m8 8-pin soic mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current scl clock frequency blank 100khz f 400khz density 04 4k 05 4k with write protect c cmos technology interface 24 iic nm fairchild non-volatile memory
4 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom product specifications absolute maximum ratings ambient storage temperature 65 c to +150 c all input or output voltages with respect to ground 6.5v to 0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c04/05 0 c to +70 c nm24c04e/05e -40 c to +85 c nm24c04v/05v -40 c to +125 c positive power supply nm24c04/05 4.5v to 5.5v nm24c04l/05l 2.7v to 5.5v nm24c04lz/05lz 2.7v to 5.5v dc electrical characteristics (2.7v to 5.5v) symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd v cc = 2.7v - 5.5v 10 50 a or v cc v cc = 2.7v - 5.5v (l) 1 10 a v cc = 2.7v - 4.5v (lz) 0.1 1 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage of 5v for 4.5v-5.5v operation and at 3v for 2.7v-4.5v operation. note 2: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom ac test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.3 to v cc x 0.7 output load 1 ttl gate and c l = 100 pf bus timing ds500070-5 scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto 0.9v cc 0.1v cc 0.7v cc 0.3v cc read and write cycle limits (standard and low v cc range 2.7v - 5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before 4.7 1.3 s a new transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 1.5 s t high clock high period 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 20 20 ns t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 300 50 ns t wr write cycle time - nm24c04/05 10 10 ms (note 3) - nm24c04/05l, nm24c04/05lz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c04/05 bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the devic e does not respond to its slave address. refer "write cycle timing" diagram. ac testing input/output waveforms ds500070-4
6 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc v cc sda scl nm24c02/03 v cc v cc a0 a1 a2 v ss nm24c02/03 a0 a1 a2 v ss nm24c04/05 a1 a2 v ss nm24c08/09 a2 v ss v cc to v ss to v ss to v ss v cc v cc v cc to v cc to v ss to v ss to v cc to v ss to v cc typical system configuration note: due to open drain configuration of sda and scl, a bus-level pull-up resistor is called for, (typical value = 4.7k ? ) example of 16k of memory on 2-wire bus note: the sda pull-up resistor is required due to the open-drain/open collector output of iic bus devices. the scl pull-up resistor is recommended because of the normal scl line inactive 'high' state. it is recommended that the total line capacitance be less than 400pf device address pins present memory size # of page a0 a1 a2 blocks nm24c02/03 yes yes yes 2048 bits 1 nm24c04/05 no yes yes 4096 bits 2 nm24c08/09 no no yes 8192 bits 4 nm24c16/17 no no no 16,384 bits 8 ds500070-7 ds500070-8 ds500070-6 sda scl stop condition start condition word n 8th bit ack t wr write cycle timing note: the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
7 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom background information (iic bus) iic bus allows synchronous bi-directional communication be- tween a transmitter and a receiver using a clock signal (scl) and a data signal (sda). additionally there are up to three address signals (a2, a1 and a0) which collectively serve as "chip select signal" to a device (example eeprom) on the iic bus. all communication on the iic bus must be started with a valid start condition (by a master), followed by transmittal (by the master) of byte(s) of information (address/data). for every byte of information received, the addressed receiver provides a valid acknowledge pulse to further continue the communication unless the receiver intends to discontinue the communication. depending on the direction of transfer (write or read), the re- ceiver can be a slave or the master. a typical iic communi- cation concludes with a stop condition (by the master). addressing an eeprom memory location involves sending a command string with the following information: [device type] [device/page block selection] [r/w bit] {acknowledge pulse} [array address] slave address slave address is an 8-bit information consisting of a device type field (4bits), device/page block selection field (3bits) and read/ write bit (1bit). slave address format acknowledge acknowledge is an active low pulse on the sda line driven by an addressed receiver to the addressing transmitter to indicate receipt of 8-bits of data. the receiver provides an ack pulse for every 8-bits of data received. this handshake mechanism is done as follows: after transmitting 8-bits of data, the transmitter re- leases the sda line and waits for the ack pulse. the addressed receiver, if present, drives the ack pulse on the sda line during the 9th clock and releases the sda line back (to the transmitter). refer figure 3 . array address array address is an 8-bit information containing the address of a memory location to be selected within a page block of the device. 16k bit addressing limitation: standard iic specification limits the maximum size of eeprom memory on the bus to 16k bits. this limitation is due to the addressing protocol implemented which consists of the 8-bit slave address and an additional 8-bit field called array address. this array address selects 1 out of 256 locations (2 8 =256). since the data format of iic specification is 8-bit wide, a total of 256 x 8 = 2048 = 2k bit now becomes addressable by this 8-bit array address. this 2k bit is typically referred as a page block . combining this 8-bit array address with the 3-bit device/page address (part of slave address) allows a maximum of 8 pages (2 3 =8) of memory that can be addressed. since each page is 2k bit in size, 8 x 2k bit = 16k bit is the maximum size of memory that is addressable on the standard iic bus. this 16kb of memory can be in the form of a single 16kb eeprom device or multiple eeproms of varying density (in 2kb multiples) to a maximum total of 16kb. to address the needs of systems that require more than 16kb on the iic bus, a different specification called ex- tended iic specification is used. please refer to nm24c32xx datasheet for more information on extended iic specification. definitions word 8 bits (byte) of data page 16 sequential byte locations starting at a 16-byte address boundary, that may be pro- grammed during a "page write" programming cycle page block 2048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2048 bits master any iic device controlling the transfer of data (such as a microprocessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) device type identifier device/page block selection 1 0 1 0 a2 a1 a0 r/w (lsb) ds500070-9 device type iic bus is designed to support a variety of devices such as rams, eproms etc., along with eeproms. hence to properly identify various devices on the iic bus, a 4-bit device type identifier string is used. for eeproms, this 4-bit string is 1-0-1-0. every iic device on the bus internally compares this 4-bit string to its own device type string to ensure proper device selection. device/page block selection when multiple devices of the same type (e.g. multiple eeproms) are present on the iic bus, then the a2, a1 and a0 address information bits are also used as part of the slave address. every iic device on the bus internally compares this 3-bit string to its own physical configuration (a2, a1 and a0 pins) to ensure proper device selection. this comparison is in addition to the device type comparison. in addition to selecting an eeprom, these 3 bits are also used to select a page block within the selected eeprom. each page block is 2kbit (256bytes) in size. depend- ing on the density, an eeprom can contain from a minimum of 1 to a maximum of 8 page blocks (in multiples of 2) and selection of a page block within a device is by using a2, a1 and a0 bits. read/write bit last bit of the slave address indicates if the intended access is read or write. if the bit is "1," then the access is read, whereas if the bit is "0," then the access is write.
8 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom eeprom number of device selection inputs address bits density page blocks provided selecting page block 2k bit 1 a0 a1 a2 none 4k bit 2 a1 a2 a0 8k bit 4 a2 a0 and a1 16k bit 8 a0, a1 and a2 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bi-directional pin used to transfer data into and out of the device. it is an open drain output and may be wire ored with any number of open drain or open collector outputs. write protect (wp) (nm24c05 only) if tied to v cc , program operations onto the upper half (upper 2kbit) of the memory will not be executed. read operations are possible. if tied to v ss , normal operation is enabled, read/ write over the entire memory is possible. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. this pin has an internal pull-down circuit. however, on systems where write protection is not required it is recommended that this pin is tied to v ss . device selection inputs a2, a1 and a0 (as appropriate) these inputs collectively serve as chip select signal to an eeprom when multiple eeproms are present on the same iic bus. hence these inputs, if present, should be connected to v cc or v ss in a unique manner to allow proper selection of an eeprom amongst multiple eeproms. during a typical addressing se- quence, every eeprom on the iic bus compares the configura- tion of these inputs to the respective 3 bit device/page block selection information (part of slave address) to determine a valid selection. for e.g. if the 3 bit device/page block selection is 1- 0-1, then the eeprom whose device selection inputs (a2, a1 and a0) are connected to v cc -v ss -v cc respectively, is selected. depending on the density, only appropriate number of device selection inputs are provided on an eeprom. for every device selection input that is not present on the device, the correspond- ing bit in the device/page block selection field is used to select a page block within the device instead of the device itself. following table illustrates the above: note that even when just one eeprom present on the iic bus, these pins should be tied to v cc or v ss to ensure proper termina- tion. device operation the nm24c04/05 supports a bi-directional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm24c04/05 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figure 1 and figure 2 on next page. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24c04/ 05 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24c04/05 to place the device in the standby power mode, except when a write operation is being executed, in which case a second stop condition is required after t wr period, to place the device in standby mode.
9 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom data validity (figure 1) start and stop definition (figure 2) scl from master data output from transmitter data output from receiver 189 start condition acknowledge pulse t aa t dh sda scl start condition stop condition scl data stable data change sda ds500070-10 ds500070-11 ds500070-12 acknowledge response from receiver (figure 3)
10 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom acknowledge the nm24c04/05 device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm24c04/05 will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the nm24c04/05 slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected, nm24c04/05 will continue to transmit data. if an acknowledge is not detected,nm24c04/05 will terminate further data transmissions and await the stop condition to return to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier. this is fixed as 1010 for all eeprom devices. refer the following table for slave addresses string details: device a0 a1 a2 page page block blocks addresses nm24c04/05 p a a 2 0, 1 a: refers to a hardware configured device address pin. p: refers to an internal page block. all iic eeproms use an internal protocol that defines a page block size of 2k bits (for word addresses 0x00 through 0xff). therefore, address bits a0, a1, or a2 (if designated 'p') are used to access a page block in conjunction with the word address used to access any individual data byte. the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the nm24c04/05 recognizes the start condition, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions. device type identifier device address 1 0 1 0 a2 a1 a0 r/w (lsb) nm24c04/05 page block address
11 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom write operations byte write for a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. upon receipt of the byte address the nm24c04/05 responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24c04/ 05 begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the nm24c04/05 inputs are disabled, and the device will not respond to any requests from the master for the duration of t wr . refer to figure 4 for the address, acknowledge and data transfer sequence. page write to minimize write cycle time, nm24c04/05 offer page write feature, by which, up to a maximum of 16 contiguous bytes locations can be programmed all at once (instead of 16 individual byte writes). to facilitate this feature, the memory array is orga- nized in terms of pages. a page consists of 16 contiguous byte locations starting at every 16-byte address boundary (for ex- ample, starting at array address 0x00, 0x10, 0x20 etc.). page write operation limits access to byte locations within a page. in other words a single page write operation will not cross over to locations on another page but will roll over to the beginning of the page whenever end of page is reached and additional locations are a continued to be accessed. a page write operation can be initiated to begin at any location within a page (starting address of the page write operation need not be the starting address of a page). s t o p bus activity: master sda line bus activity: eeprom data n + 15 data n + 1 data n word address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master sda line bus activity: eeprom ds500070-13 ds500070-14 page write is initiated in the same manner as the byte write operation; but instead of terminating the cycle after transmitting the first data byte, the master can further transmit up to 15 more bytes. after the receipt of each byte, nm24c04/05 will respond with an acknowledge pulse, increment the internal address counter to the next address and is ready to accept the next data. if the master should transmit more than sixteen bytes prior to generat- ing the stop condition, the address counter will roll over and previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 5 for the address, acknowledge and data transfer sequence. acknowledge polling once the stop condition is issued to indicate the end of the host s write operation the nm24c04/05 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24c04/05 is still busy with the write operation no ack will be returned. if the nm24c04/05 has completed the write operation an ack will be returned and the host can then proceed with the next read or write operation. write protection (nm24c05 only) programming of the upper half (upper 2kbit) of the memory will not take place if the wp pin of the nm24c05 is connected to v cc . the nm24c05 will respond to slave and byte addresses; but if the memory accessed is write protected by the wp pin, the nm24c05 will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. byte write (figure 4) page write (figure 5)
12 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom s t o p a c k no a c k slave address a c k a c k s t a r t s t a r t word address slave address bus activity: master sda line bus activity: eeprom data n s t o p a c k bus activity: master sda line bus activity: eeprom a c k data n + x a c k data n + 2 data n +1 data n +1 a c k no a c k slave address ds500070-16 ds500070-17 read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the nm24c04/05 contains an address counter that maintains the address of the last byte accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the nm24c04/05 issues an acknowledge and transmits the eight bit byte. the master will not acknowledge the transfer but does generate a stop condition, and therefore the nm24c04/05 discontinues transmission. refer to figure 6 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address with the r/w bit set to zero and then the byte address it is to read. after the byte address acknowledge, the master immediately issues another start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the nm24c04/05 and then by the eight bit byte. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24c04/05 discontinues transmission. refer to figure 7 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24c04/05 continues to output data for each ac- knowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" to the beginning of the memory. nm24c04/05 continues to output data for each acknowledge received. refer to figure 8 for the address, acknowledge, and data transfer sequence. current address read (figure 6) s t o p data a c k no a c k s t a r t slave address bus activity: master sda line bus activity: eeprom 1 0 1 0 1 ds500070-15 random read (figure 7) sequential read (figure 8)
13 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom 8-pin molded small outline package (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 8-pin molded thin shrink small outline package (mt8) package number mtc08 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
14 www.fairchildsemi.com nm24c04/05 rev. g nm24c04/05 C 4k-bit standard 2-wire bus interface serial eeprom physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident
1 www.fairchildsemi.com nm24c04u/nm24c05u rev. c.1 nm24c04u/nm24c05u C 4k-bit serial eeprom 2-wire bus interface august 1999 ?1999 fairchild semiconductor corporation nm24c04u/nm24c05u 4k-bit serial eeprom 2-wire bus interface general description the nm24c04u/05u devices are 4k (4,096) bit serial interface cmos eeproms (electrically erasable programmable read- only memory). these devices fully conform to the standard i 2 c 2-wire protocol which uses clock (scl) and data i/o (sda) pins to synchronously clock data between the "master" (for example a microprocessor) and the "slave" (the eeprom device). in addi- tion, the serial interface allows a minimal pin count packaging designed to simplify pc board layout requirements and offers the designer a variety of low voltage and low power options. nm24c05u incorporates a hardware "write protect" feature, by which, the upper half of the memory can be disabled against programming by connecting the wp pin to v cc . this section of memory then effectively becomes a rom (read-only memory) and can no longer be programmed as long as wp pin is connected to v cc . fairchild eeproms are designed and tested for applications requir- ing high endurance, high reliability and low power consumption for a continuously reliable non-volatile solution for all markets. block diagram functions i 2 c compatible interface 4,096 bits organized as 512 x 8 extended 2.7v ?5.5v operating voltage 100 khz or 400 khz operation self timed programming cycle (6ms typical) "programming complete" indicated by ack polling nm24c05u: memory "upper block" write protect pin features the i 2 c interface allows the smallest i/o pincount of any eeprom interface 16 byte page write mode to minimize total write time per byte typical 200 a active current (i cca ) typical 1 a standby current (i sb ) for "l" devices and 0.1 a standby current for "lz" devices endurance: up to 1,000,000 data changes data retention greater than 40 years h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic ck d in r/w sda scl v ss wp v cc d out a2 a1 ds800008-1 i 2 c is a registered trademark of philips electronics n.v.
2 www.fairchildsemi.com nm24c04u/nm24c05u rev. c.1 nm24c04u/nm24c05u C 4k-bit serial eeprom 2-wire bus interface nc a1 a2 v ss v cc nc scl sda 8 7 6 5 1 2 3 4 connection diagrams dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e, m08a, and mtc08 pin names a1,a2 device address inputs v ss ground sda serial data i/o scl serial clock input nc no connection v cc power supply dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e, m08a, and mtc08 pin names nc no connection a1,a2 device address inputs v ss ground sda serial data i/o scl serial clock input wp write protect v cc power supply nc a1 a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm24c04u nm24c05u ds800008-2 ds800008-3
3 www.fairchildsemi.com nm24c04u/nm24c05u rev. c.1 nm24c04u/nm24c05u C 4k-bit serial eeprom 2-wire bus interface ordering information nm 24 c xx u f lz e xx letter description package n 8-pin dip m8 8-pin soic mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current scl clock frequency blank 100khz f 400khz ultralite cs100ul process density 04 4k 05 4k with write protect c cmos technology w total array write protect interface 24 iic nm fairchild non-volatile memory
4 www.fairchildsemi.com nm24c04u/nm24c05u rev. c.1 nm24c04u/nm24c05u C 4k-bit serial eeprom 2-wire bus interface product specifications absolute maximum ratings ambient storage temperature 65 c to +150 c all input or output voltages with respect to ground 6.5v to 0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c04u/05u 0 c to +70 c nm24c04ue/05ue -40 c to +85 c nm24c04uv/05uv -40 c to +125 c positive power supply nm24c04u/05u 4.5v to 5.5v nm24c04ul/05ul 2.7v to 5.5v nm24c04ulz/05ulz 2.7v to 5.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd or v cc 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd v cc = 2.7v - 4.5v 1 10 a or v cc v cc = 2.7v - 4.5v 0.1 1 a v cc = 4.5v - 5.5v 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm24c04u/nm24c05u rev. c.1 nm24c04u/nm24c05u C 4k-bit serial eeprom 2-wire bus interface ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf read and write cycle limits (standard and low v cc range 2.7v - 5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before 4.7 1.3 s a new transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 1.5 s t high clock high period 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 300 50 ns t wr write cycle time - nm24c04u/05u 10 10 ms (note 3) - nm24c04u/05ul, nm24c04u/05ulz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c04u/05u bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the dev ice does not respond to its slave address.
6 www.fairchildsemi.com nm24c04u/nm24c05u rev. c.1 nm24c04u/nm24c05u C 4k-bit serial eeprom 2-wire bus interface sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc v cc sda scl nm24c02u/03u v cc v cc a0 a1 a2 v ss nm24c02u/03u a0 a1 a2 v ss nm24c04u/05u a1 a2 v ss nm24c08u/09u a2 v ss v cc to v cc or v ss to v cc or v ss to v cc or v ss to v cc or v ss v cc v cc v cc bus timing system layout typical system configuration note: due to open drain configuration of sda, a bus-level pull-up resistor is called for, (typical value = 4.7k ? ) example of 16k of memory on 2-wire bus note: the sda pull-up resistor is required due to the open-drain/open collector output of iic bus devices. the scl pull-up resistor is recommended because of the normal scl line inactive 'high' state. it is recommended that the total line capacitance be less than 400pf device address pins memory size # of page a0 a1 a2 blocks nm24c04u/05u no connect adr adr 4096 bits 2 ds800008-8 ds800008-20 ds800008-9 scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto
7 www.fairchildsemi.com nm24c04u/nm24c05u rev. c.1 nm24c04u/nm24c05u C 4k-bit serial eeprom 2-wire bus interface device operation inputs (a1, a2) device address pins a1 and a2 are connected to v cc or v ss to configure the eeprom chip address. table i shows the active pins. table 1. device a0 a1 a2 effects of addresses nm24c04u/05u x adr adr 2 2 = 4; 4*x (2x2k)** = 16k * max # of devices on bus ** number of page blocks per density under the standard iic protocol the maximum density address- able using the three pin configuration of the iic protocol is 16k. any combination of densities can be used up to this limit. background information (iic bus) as mentioned, the iic bus allows synchronous bidirectional com- munication between transmitter/receiver using the scl (clock) and sda (data i/o) lines. all communication must be started with a valid start condition, concluded with a stop condition and acknowledged by the receiver with an acknowledge condi- tion. as shown below, the eeproms on the iic bus may be configured in any manner required, the total memory addressed can not exceed 16k (16,384 bits). eeprom memory address program- ming is controlled by 2 methods: hardware configuring the a1 and a2 pins (device address pins) with pull-up or pull-down to v cc or v ss . all unused pins must be grounded (tied to v ss ). software addressing the required page block within the device memory array (as sent in the slave address string). for devices with densities greater than 16k, a different protocol, the extended iic protocol, is used. refer to nm24c32u datasheet (for example) for additional details. addressing an eeprom memory location involves sending a command string with the following information: [device type] [device address] [page block ad- dress] [byte address] definitions word 8 bits (byte) of data page 16 sequential addresses (one byte each) that may be programmed during a 'page write' programming cycle page block 2048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2048 bits master any iic device controlling the transfer of data (such as a microprocessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire ored with any number of open drain or open collector outputs. wp write protection (nm24c05u only) if tied to v cc , program operations onto the upper half of the memory will not be executed. read operations are possible. if tied to v ss , normal operation is enabled, read/write over the entire memory is possible. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. device operation the nm24c04u/05u supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm24c04u/05u will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figure 2 and figure 3 on next page. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24c04u/05u continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24c04u/05u to place the device in the standby power mode. write cycle timing acknowledge acknowledge is a hardware convention used to indicate success- ful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line to low to acknowledge that it received the eight bits of data. refer to figure 4.
8 www.fairchildsemi.com nm24c04u/nm24c05u rev. c.1 nm24c04u/nm24c05u C 4k-bit serial eeprom 2-wire bus interface ds800008-10 sda scl stop condition start condition word n 8th bit ack t wr write cycle timing (figure 1) note: the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. data validity (figure 2) start and stop definition (figure 3) acknowledge response from receiver (figure 4) scl from master data output from transmitter data output from receiver 189 start acknowledge sda scl start condition stop condition scl data stable data change sda ds800008-11 ds800008-12 ds800008-13
9 www.fairchildsemi.com nm24c04u/nm24c05u rev. c.1 nm24c04u/nm24c05u C 4k-bit serial eeprom 2-wire bus interface device type identifier device address 1 0 1 0 a2 a1 a0 r/w (lsb) nm24c04u/05u page block address ds800008-14 write cycle timing (continued) the nm24c04u/05u device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm24c04u/05u will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the nm24c04u/05u slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier ( see figure 5) . this is fixed as 1010 for all eeprom devices. slave addresses (figure 5) refer to the following table for slave addresses string details: device a0 a1 a2 page page block blocks addresses nm24c04u/05u p a a 2 00 01 a: refers to a hardware configured device address pin p: refers to an internal page block memory segment. all iic eeproms use an internal protocol that defines a page block size of 2k bits (for word addressess 0000 through 1111). therefore, address bits a0, a1, or a2 (if designated 'p') are used to access a page block in conjunction with the word address used to access any individual data byte (word). the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the nm24c04u/05u recognizes the start condition, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions.
10 www.fairchildsemi.com nm24c04u/nm24c05u rev. c.1 nm24c04u/nm24c05u C 4k-bit serial eeprom 2-wire bus interface write operations byte write for a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. upon receipt of the byte address the nm24c04u/05u responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24c04u/05u begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the nm24c04u/05u inputs are disabled, and the device will not respond to any requests from the master. refer to figure 6 for the address, acknowledge and data transfer sequence. page write the nm24c04u/05u is capable of a sixteen byte page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to fifteen more bytes. after the receipt of each byte, the nm24c04u/05u will respond with an acknowledge. after the receipt of each byte, the internal address counter increments to the next address and the next sda data is accepted. if the master should transmit more than sixteen bytes prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 7 for the address, acknowl- edge, and data transfer sequence. s t o p bus activity: master sda line bus activity: nm24c04u/05u data n + 15 data n + 1 data n word address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master sda line bus activity: nm24c04u/05u ds800008-15 ds800008-16 acknowledge polling once the stop condition is issued to indicate the end of the host s write operation the nm24c04u/05u initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24c04u/05u is still busy with the write operation no ack will be returned. if the nm24c04u/05u has completed the write operation an ack will be returned and the host can then proceed with the next read or write operation. write protection (nm24c05u only) programming of the upper half of the memory will not take place if the wp pin of the nm24c05u is connected to v cc . the nm24c05u will accept slave and byte addresses; but if the memory accessed is write protected by the wp pin, the nm24c05u will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. byte write (figure 6) page write (figure 7)
11 www.fairchildsemi.com nm24c04u/nm24c05u rev. c.1 nm24c04u/nm24c05u C 4k-bit serial eeprom 2-wire bus interface s t o p a c k no a c k slave address a c k a c k s t a r t s t a r t word address slave address bus activity: master sda line bus activity: nm24c04u/05u data n s t o p a c k bus activity: master sda line bus activity: nm24c04u/05u a c k data n + x a c k data n + 2 data n +1 data n +1 a c k no a c k slave address ds800008-18 ds800008-19 read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the nm24c04u/05u contains an address counter that maintains the address of the last byte accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the nm24c04u/05u issues an acknowledge and transmits the eight bit byte. the master will not acknowledge the transfer but does generate a stop condition, and therefore the nm24c04u/ 05u discontinues transmission. refer to figure 8 for the se- quence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address and then the byte address it is to read. after the byte address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the nm24c04u/05u and then by the eight bit data. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24c04u/05u discontinues transmission. refer to figure 9 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24c04u/05u continues to output data for each acknowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" and the nm24c04u/05u continues to output data for each acknowledge received. refer to figure 10 for the address, acknowledge, and data transfer sequence. current address read (figure 8) s t o p data a c k no a c k s t a r t slave address bus activity: master sda line bus activity: nm24c04u/05u ds800008-17 random read (figure 9) sequential read (figure 10)
12 www.fairchildsemi.com nm24c04u/nm24c05u rev. c.1 nm24c04u/nm24c05u C 4k-bit serial eeprom 2-wire bus interface 8-pin molded small outline package (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 8-pin molded thin shrink small outline package package number mtc08 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
13 www.fairchildsemi.com nm24c04u/nm24c05u rev. c.1 nm24c04u/nm24c05u C 4k-bit serial eeprom 2-wire bus interface physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom february 2000 ?1998 fairchild semiconductor corporation nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom general description the nm24c08/09 devices are 8192 bits of cmos non-volatile electrically erasable memory. these devices conform to all speci- fications in the standard iic 2-wire protocol and are designed to minimize device pin count, and simplify pc board layout require- ments. the upper half (upper 4kbit) of the memory of the nm24c09 can be write protected by connecting the wp pin to v cc . this section of memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by the fairchild family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. in order to implement higher eeprom memory densities on the iic bus, the extended iic protocol must be used. (refer to the nm24c32 or nm24c65 datasheets for more infor- mation.) fairchild eeproms are designed and tested for applications requir- ing high endurance, high reliability and low power consumption. block diagram features extended operating voltage 2.7v ?5.5v 400 khz clock frequency (f) at 2.7v - 5.5v 200 a active current typical 10 a standby current typical 1 a standby current typical (l) 0.1 a standby current typical (lz) iic compatible interface ?provides bi-directional data transfer protocol schmitt trigger inputs sixteen byte page write mode ?minimizes total write time per byte self timed write cycle typical write cycle time of 6ms hardware write protect for upper half (nm24c09 only) endurance: 1,000,000 data changes data retention greater than 40 years packages available: 8-pin dip, 8-pin so, and 8-pin tssop available in three temperature ranges - commercial: 0 to +70 c - extended (e): -40 to +85c - automotive (v): -40 to +125 c h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic ck d in r/w sda scl v ss wp v cc d out a2 ds500071-1
2 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom nc nc a2 v ss v cc nc scl sda 8 7 6 5 1 2 3 4 nm24c08 connection diagrams dual-in-line package (n), so package (m8) and tssop package (mt8) see package number n08e, m08a and mtc08 pin names a2 device address input v ss ground sda serial data i/o scl serial clock input nc no connection v cc power supply dual-in-line package (n), so package (m8) and tssop package (mt8) see package number n08e, m08a and mtc08 pin names a2 device address input v ss ground sda serial data i/o scl serial clock input wp write protect v cc power supply nc no connection nc nc a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm24c09 ds500071-2 ds500071-3 note: pins designated as "nc" are typically unbonded pins. however some of them are bonded for special testing purposes. hence if a s ignal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the v cc applied to the device. this will ensure proper operation.
3 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom ordering information nm 24 c xx f lz e xxx letter description package n 8-pin dip m8 8-pin soic mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current scl clock frequency blank 100khz f 400khz density 08 8k 09 8k with write protect c cmos technology interface 24 iic nm fairchild non-volatile memory
4 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom product specifications absolute maximum ratings ambient storage temperature 65 c to +150 c all input or output voltages with respect to ground 6.5v to 0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c08/09 0 c to +70 c nm24c08e/09e -40 c to +85 c nm24c08v/09v -40 c to +125 c positive power supply nm24c08/09 4.5v to 5.5v nm24c08l/09l 2.7v to 5.5v nm24c08lz/09lz 2.7v to 5.5v dc electrical characteristics (2.7v to 5.5v) symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd v cc = 2.7v - 5.5v 10 50 a or v cc v cc = 2.7v - 5.5v (l) 1 10 a v cc = 2.7v - 4.5v (lz) 0.1 1 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage of 5v for 4.5v-5.5v operation and at 3v for 2.7v-4.5v operation. note 2: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom ac test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.3 to v cc x 0.7 output load 1 ttl gate and c l = 100 pf bus timing ds500071-5 scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto 0.9v cc 0.1v cc 0.7v cc 0.3v cc read and write cycle limits (standard and low v cc range 2.7v - 5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before 4.7 1.3 s a new transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 1.5 s t high clock high period 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 20 20 ns t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 300 50 ns t wr write cycle time - nm24c08/09 10 10 ms (note 3) - nm24c08/09l, nm24c08/09lz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c08/09 bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the devic e does not respond to its slave address. refer "write cycle timing" diagram. ac testing input/output waveforms ds500071-4
6 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc v cc sda scl nm24c02/03 v cc v cc a0 a1 a2 v ss nm24c02/03 a0 a1 a2 v ss nm24c04/05 a1 a2 v ss nm24c08/09 a2 v ss v cc to v ss to v ss to v ss v cc v cc v cc to v cc to v ss to v ss to v cc to v ss to v cc typical system configuration note: due to open drain configuration of sda and scl, a bus-level pull-up resistor is called for, (typical value = 4.7k ? ) example of 16k of memory on 2-wire bus note: the sda pull-up resistor is required due to the open-drain/open collector output of iic bus devices. the scl pull-up resistor is recommended because of the normal scl line inactive 'high' state. it is recommended that the total line capacitance be less than 400pf device address pins present memory size # of page a0 a1 a2 blocks nm24c02/03 yes yes yes 2048 bits 1 nm24c04/05 no yes yes 4096 bits 2 nm24c08/09 no no yes 8192 bits 4 nm24c16/17 no no no 16,384 bits 8 ds500071-7 ds500071-8 ds500071-6 sda scl stop condition start condition word n 8th bit ack t wr write cycle timing note: the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
7 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom background information (iic bus) iic bus allows synchronous bi-directional communication be- tween a transmitter and a receiver using a clock signal (scl) and a data signal (sda). additionally there are up to three address signals (a2, a1 and a0) which collectively serve as "chip select signal" to a device (example eeprom) on the iic bus. all communication on the iic bus must be started with a valid start condition (by a master), followed by transmittal (by the master) of byte(s) of information (address/data). for every byte of information received, the addressed receiver provides a valid acknowledge pulse to further continue the communication unless the receiver intends to discontinue the communication. depending on the direction of transfer (write or read), the re- ceiver can be a slave or the master. a typical iic communi- cation concludes with a stop condition (by the master). addressing an eeprom memory location involves sending a command string with the following information: [device type] [device/page block selection] [r/w bit] {acknowledge pulse} [array address] slave address slave address is an 8-bit information consisting of a device type field (4bits), device/page block selection field (3bits) and read/ write bit (1bit). slave address format acknowledge acknowledge is an active low pulse on the sda line driven by an addressed receiver to the addressing transmitter to indicate receipt of 8-bits of data. the receiver provides an ack pulse for every 8-bits of data received. this handshake mechanism is done as follows: after transmitting 8-bits of data, the transmitter re- leases the sda line and waits for the ack pulse. the addressed receiver, if present, drives the ack pulse on the sda line during the 9th clock and releases the sda line back (to the transmitter). refer figure 3 . array address array address is an 8-bit information containing the address of a memory location to be selected within a page block of the device. 16k bit addressing limitation: standard iic specification limits the maximum size of eeprom memory on the bus to 16k bits. this limitation is due to the addressing protocol implemented which consists of the 8-bit slave address and an additional 8-bit field called array address. this array address selects 1 out of 256 locations (2 8 =256). since the data format of iic specification is 8-bit wide, a total of 256 x 8 = 2048 = 2k bit now becomes addressable by this 8-bit array address. this 2k bit is typically referred as a page block . combining this 8-bit array address with the 3-bit device/page address (part of slave address) allows a maximum of 8 pages (2 3 =8) of memory that can be addressed. since each page is 2k bit in size, 8 x 2k bit = 16k bit is the maximum size of memory that is addressable on the standard iic bus. this 16kb of memory can be in the form of a single 16kb eeprom device or multiple eeproms of varying density (in 2kb multiples) to a maximum total of 16kb. to address the needs of systems that require more than 16kb on the iic bus, a different specification called ex- tended iic specification is used. please refer to nm24c32xx datasheet for more information on extended iic specification. definitions word 8 bits (byte) of data page 16 sequential byte locations starting at a 16-byte address boundary, that may be pro- grammed during a "page write" programming cycle page block 2048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2048 bits master any iic device controlling the transfer of data (such as a microprocessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) device type identifier device/page block selection 1 0 1 0 a2 a1 a0 r/w (lsb) ds500071-9 device type iic bus is designed to support a variety of devices such as rams, eproms etc., along with eeproms. hence to properly identify various devices on the iic bus, a 4-bit device type identifier string is used. for eeproms, this 4-bit string is 1-0-1-0. every iic device on the bus internally compares this 4-bit string to its own device type string to ensure proper device selection. device/page block selection when multiple devices of the same type (e.g. multiple eeproms) are present on the iic bus, then the a2, a1 and a0 address information bits are also used as part of the slave address. every iic device on the bus internally compares this 3-bit string to its own physical configuration (a2, a1 and a0 pins) to ensure proper device selection. this comparison is in addition to the device type comparison. in addition to selecting an eeprom, these 3 bits are also used to select a page block within the selected eeprom. each page block is 2kbit (256bytes) in size. depend- ing on the density, an eeprom can contain from a minimum of 1 to a maximum of 8 page blocks (in multiples of 2) and selection of a page block within a device is by using a2, a1 and a0 bits. read/write bit last bit of the slave address indicates if the intended access is read or write. if the bit is "1," then the access is read, whereas if the bit is "0," then the access is write.
8 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom eeprom number of device selection inputs address bits density page blocks provided selecting page block 2k bit 1 a0 a1 a2 none 4k bit 2 a1 a2 a0 8k bit 4 a2 a0 and a1 16k bit 8 a0, a1 and a2 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bi-directional pin used to transfer data into and out of the device. it is an open drain output and may be wire ored with any number of open drain or open collector outputs. write protect (wp) (nm24c09 only) if tied to v cc , program operations onto the upper half (upper 4kbit) of the memory will not be executed. read operations are possible. if tied to v ss , normal operation is enabled, read/ write over the entire memory is possible. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. this pin has an internal pull-down circuit. however, on systems where write protection is not required it is recommended that this pin is tied to v ss . device selection inputs a2, a1 and a0 (as appropriate) these inputs collectively serve as chip select signal to an eeprom when multiple eeproms are present on the same iic bus. hence these inputs, if present, should be connected to v cc or v ss in a unique manner to allow proper selection of an eeprom amongst multiple eeproms. during a typical addressing se- quence, every eeprom on the iic bus compares the configura- tion of these inputs to the respective 3 bit device/page block selection information (part of slave address) to determine a valid selection. for e.g. if the 3 bit device/page block selection is 1- 0-1, then the eeprom whose device selection inputs (a2, a1 and a0) are connected to v cc -v ss -v cc respectively, is selected. depending on the density, only appropriate number of device selection inputs are provided on an eeprom. for every device selection input that is not present on the device, the correspond- ing bit in the device/page block selection field is used to select a page block within the device instead of the device itself. following table illustrates the above: note that even when just one eeprom present on the iic bus, these pins should be tied to v cc or v ss to ensure proper termina- tion. device operation the nm24c08/09 supports a bi-directional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm24c08/09 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figure 1 and figure 2 on next page. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24c08/ 09 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24c08/09 to place the device in the standby power mode, except when a write operation is being executed, in which case a second stop condition is required after t wr period, to place the device in standby mode.
9 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom data validity (figure 1) start and stop definition (figure 2) scl from master data output from transmitter data output from receiver 189 start condition acknowledge pulse t aa t dh sda scl start condition stop condition scl data stable data change sda ds500071-10 ds500071-11 ds500071-12 acknowledge response from receiver (figure 3)
10 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom acknowledge the nm24c08/09 device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm24c08/09 will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the nm24c08/09 slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected, nm24c08/09 will continue to transmit data. if an acknowledge is not detected,nm24c08/09 will terminate further data transmissions and await the stop condition to return to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier. this is fixed as 1010 for all eeprom devices. refer the following table for slave addresses string details: device a0 a1 a2 page page block blocks addresses nm24c08/09 p p a 4 00, 01, 10, 11 a: refers to a hardware configured device address pin. p: refers to an internal page block. all iic eeproms use an internal protocol that defines a page block size of 2k bits (for word addresses 0x00 through 0xff). therefore, address bits a0, a1, or a2 (if designated 'p') are used to access a page block in conjunction with the word address used to access any individual data byte. the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the nm24c08/09 recognizes the start condition, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions. device type identifier device address 1 0 1 0 a2 a1 a0 r/w (lsb) nm24c08/09 page block address
11 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom write operations byte write for a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. upon receipt of the byte address the nm24c08/09 responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24c08/ 09 begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the nm24c08/09 inputs are disabled, and the device will not respond to any requests from the master for the duration of t wr . refer to figure 4 for the address, acknowledge and data transfer sequence. page write to minimize write cycle time, nm24c08/09 offer page write feature, by which, up to a maximum of 16 contiguous bytes locations can be programmed all at once (instead of 16 individual byte writes). to facilitate this feature, the memory array is orga- nized in terms of pages. a page consists of 16 contiguous byte locations starting at every 16-byte address boundary (for ex- ample, starting at array address 0x00, 0x10, 0x20 etc.). page write operation limits access to byte locations within a page. in other words a single page write operation will not cross over to locations on another page but will roll over to the beginning of the page whenever end of page is reached and additional locations are a continued to be accessed. a page write operation can be initiated to begin at any location within a page (starting address of the page write operation need not be the starting address of a page). s t o p bus activity: master sda line bus activity: eeprom data n + 15 data n + 1 data n word address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master sda line bus activity: eeprom ds500071-13 ds500071-14 page write is initiated in the same manner as the byte write operation; but instead of terminating the cycle after transmitting the first data byte, the master can further transmit up to 15 more bytes. after the receipt of each byte, nm24c08/09 will respond with an acknowledge pulse, increment the internal address counter to the next address and is ready to accept the next data. if the master should transmit more than sixteen bytes prior to generat- ing the stop condition, the address counter will roll over and previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 5 for the address, acknowledge and data transfer sequence. acknowledge polling once the stop condition is issued to indicate the end of the host s write operation the nm24c08/09 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24c08/09 is still busy with the write operation no ack will be returned. if the nm24c08/09 has completed the write operation an ack will be returned and the host can then proceed with the next read or write operation. write protection (nm24c09 only) programming of the upper half (upper 4kbit) of the memory will not take place if the wp pin of the nm24c09 is connected to v cc . the nm24c09 will respond to slave and byte addresses; but if the memory accessed is write protected by the wp pin, the nm24c09 will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. byte write (figure 4) page write (figure 5)
12 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom s t o p a c k no a c k slave address a c k a c k s t a r t s t a r t word address slave address bus activity: master sda line bus activity: eeprom data n s t o p a c k bus activity: master sda line bus activity: eeprom a c k data n + x a c k data n + 2 data n +1 data n +1 a c k no a c k slave address ds500071-16 ds500071-17 read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the nm24c08/09 contains an address counter that maintains the address of the last byte accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the nm24c08/09 issues an acknowledge and transmits the eight bit byte. the master will not acknowledge the transfer but does generate a stop condition, and therefore the nm24c08/09 discontinues transmission. refer to figure 6 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address with the r/w bit set to zero and then the byte address it is to read. after the byte address acknowledge, the master immediately issues another start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the nm24c08/09 and then by the eight bit byte. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24c08/09 discontinues transmission. refer to figure 7 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24c08/09 continues to output data for each ac- knowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" to the beginning of the memory. nm24c08/09 continues to output data for each acknowledge received. refer to figure 8 for the address, acknowledge, and data transfer sequence. current address read (figure 6) s t o p data a c k no a c k s t a r t slave address bus activity: master sda line bus activity: eeprom 1 0 1 0 1 ds500071-15 random read (figure 7) sequential read (figure 8)
13 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom 8-pin molded small outline package (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 8-pin molded thin shrink small outline package (mt8) package number mtc08 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
14 www.fairchildsemi.com nm24c08/09 rev. g nm24c08/09 C 8k-bit standard 2-wire bus interface serial eeprom physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident
1 www.fairchildsemi.com nm24c08u/09u rev. b.1 nm24c08u/nm24c09u C 8k-bit serial eeprom 2-wire bus interface nm24c08u/nm24c09u 8k-bit serial eeprom 2-wire bus interface general description, the nm24c08u/09u devices are 8k (8,192) bit serial interface cmos eeproms (electrically erasable programmable read- only memory). these devices fully conform to the standard i 2 c 2-wire protocol which uses clock (scl) and data i/o (sda) pins to synchronously clock data between the "master" (for example a microprocessor) and the "slave" (the eeprom device). in addi- tion, the serial interface allows a minimal pin count packaging designed to simplify pc board layout requirements and offers the designer a variety of low voltage and low power options. nm24c09u incorporates a hardware "write protect" feature, by which, the upper half of the memory can be disabled against programming by connecting the wp pin to v cc . this section of memory then effectively becomes a rom (read-only memory) and can no longer be programmed as long as wp pin is connected to v cc . fairchild eeproms are designed and tested for applications requir- ing high endurance, high reliability and low power consumption for a continuously reliable non-volatile solution for all markets. block diagram august 1999 functions i 2 c compatible interface 8,192 bits organized as 1,024 x 8 extended 2.7v ?5.5v operating voltage 100 khz or 400 khz operation self timed programming cycle (6ms typical) "programming complete" indicated by ack polling nm24c09u: memory "upper block" write protect pin features the i 2 c interface allows the smallest i/o pincount of any eeprom interface 16 byte page write mode to minimize total write time per byte typical 200 a active current (i cca ) typical 1 a standby current (i sb ) for "l" devices and 0.1 a standby current for "lz" devices endurance: up to 1,000,000 data changes data retention greater than 40 years ?1999 fairchild semiconductor corporation h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic ck d in r/w sda scl v ss wp v cc d out a2 ds800009-1 i 2 c is a registered trademark of philips electronics n.v.
2 www.fairchildsemi.com nm24c08u/09u rev. b.1 nm24c08u/nm24c09u C 8k-bit serial eeprom 2-wire bus interface nc nc a2 v ss v cc nc scl sda 8 7 6 5 1 2 3 4 connection diagrams dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e, m08a, and mtc08 pin names a2 device address input v ss ground sda serial data i/o scl serial clock input nc no connection v cc power supply pin names nc no connection a2 device address input v ss ground sda serial data i/o scl serial clock input wp write protect v cc power supply nc nc a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm24c08u nm24c09u ds800009-2 ds800009-5 dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e, m08a, and mtc08
3 www.fairchildsemi.com nm24c08u/09u rev. b.1 nm24c08u/nm24c09u C 8k-bit serial eeprom 2-wire bus interface ordering information nm 24 c xx u f lz e xx letter description package n 8-pin dip m8 8-pin soic mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current scl clock frequency blank 100khz f 400khz ultralite cs100ul process density 08 8k 09 8k with write protect c cmos technology w total array write protect interface 24 iic nm fairchild non-volatile memory
4 www.fairchildsemi.com nm24c08u/09u rev. b.1 nm24c08u/nm24c09u C 8k-bit serial eeprom 2-wire bus interface product specifications absolute maximum ratings ambient storage temperature 65 c to +150 c all input or output voltages with respect to ground 6.5v to 0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c08u/09u 0 c to +70 c nm24c08ue/09ue -40 c to +85 c nm24c08uv/09uv -40 c to +125 c positive power supply nm24c08u/09u 4.5v to 5.5v nm24c08ul/09ul 2.7v to 5.5v nm24c08ulz/09ulz 2.7v to 5.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units mintyp max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd or v cc 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units mintyp max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd v cc = 2.7v - 4.5v 1 10 a or v cc v cc = 2.7v - 4.5v 0.1 1 a v cc = 4.5v - 5.5v 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm24c08u/09u rev. b.1 nm24c08u/nm24c09u C 8k-bit serial eeprom 2-wire bus interface ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf read and write cycle limits (standard and low v cc range 2.7v - 5.5v) symbol parameter 100 khz 400 khz units minmax minmax f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before 4.7 1.3 s a new transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 1.5 s t high clock high period 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 300 50 ns t wr write cycle time - nm24c08u/09u 10 10 ms (note 3) - nm24c08u/09ul, nm24c08u/09ulz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c08u/09u bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the dev ice does not respond to its slave address.
6 www.fairchildsemi.com nm24c08u/09u rev. b.1 nm24c08u/nm24c09u C 8k-bit serial eeprom 2-wire bus interface sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc v cc scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto sda scl nm24c02u/03u v cc v cc a0 a1 a2 v ss nm24c02u/03u a0 a1 a2 v ss nm24c04u/05u a1 a2 v ss nm24c08u/09u a2 v ss v cc to v cc or v ss to v cc or v ss to v cc or v ss to v cc or v ss v cc v cc v cc bus timing system layout typical system configuration note: due to open drain configuration of sda, a bus-level pull-up resistor is called for, (typical value = 4.7k ? ) example of 16k of memory on 2-wire bus note: the sda pull-up resistor is required due to the open-drain/open collector output of iic bus devices. the scl pull-up resistor is recommended because of the normal scl line inactive 'high' state. it is recommended that the total line capacitance be less than 400pf device address pins memory size # of page a0 a1 a2 blocks nm24c08u/09u no connect no connect adr 8192 bits 4 ds800009-8 ds800009-20 ds800009-9
7 www.fairchildsemi.com nm24c08u/09u rev. b.1 nm24c08u/nm24c09u C 8k-bit serial eeprom 2-wire bus interface device operation input (a2) device address pin a2 is connected to v cc or v ss to configure the eeprom chip address. table 1 shows the active pin. table 1. device a0 a1 a2 effects of addresses nm24c08u/09u x x adr 2 1 = 2; 2 x (4 x 2k) = 16k background information (iic bus) as mentioned, the iic bus allows synchronous bidirectional com- munication between transmitter/receiver using the scl (clock) and sda (data i/o) lines. all communication must be started with a valid start condition, concluded with a stop condition and acknowledged by the receiver with an acknowledge condi- tion. as shown below, the eeproms on the iic bus may be configured in any manner required, the total memory addressed can not exceed 16k (16,384 bits). eeprom memory address program- ming is controlled by 2 methods: hardware configuring the a2 pin (device address pin) with pull-up or pull-down to v cc or v ss . all unused pins must be grounded (tied to v ss ). software addressing the required page block within the device memory array (as sent in the slave address string). for devices with densities greater than 16k, a different protocol, the extended iic protocol, is used. refer to nm24c32u datasheet (for example) for additional details. addressing an eeprom memory location involves sending a command string with the following information: [device type] [device address] [page block ad- dress] [byte address] definitions byte 8 bits (byte) of data page 16 sequential addresses (one byte each) that may be programmed during a 'page write' programming cycle page block 2048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2048 bits master any iic device controlling the transfer of data (such as a microprocessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire ored with any number of open drain or open collector outputs. wp write protection (nm24c09u only) if tied to v cc , program operations onto the upper half of the memory will not be executed. read operations are possible. if tied to v ss , normal operation is enabled, read/write over the entire memory is possible. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. device operation the nm24c08u/09u supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm24c08u/09u will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figure 2 and figure 3 on next page. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24c08u/09u continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24c08u/09u to place the device in the standby power mode. write cycle timing acknowledge acknowledge is a hardware convention used to indicate success- ful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line to low to acknowledge that it received the eight bits of data. refer to figure 4.
8 www.fairchildsemi.com nm24c08u/09u rev. b.1 nm24c08u/nm24c09u C 8k-bit serial eeprom 2-wire bus interface ds800009-10 sda scl stop condition start condition word n 8th bit ack t wr write cycle timing note: the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. data validity (figure 2) start and stop definition (figure 3) acknowledge response from receiver (figure 4) scl from master data output from transmitter data output from receiver 189 start acknowledge sda scl start condition stop condition scl data stable data change sda ds800009-11 ds800009-12 ds800009-13
9 www.fairchildsemi.com nm24c08u/09u rev. b.1 nm24c08u/nm24c09u C 8k-bit serial eeprom 2-wire bus interface device type identifier device address 1 0 1 0 a2 a1 a0 r/w (lsb) nm24c08u/09u page block address ds800009-14 write cycle timing (continued) the nm24c08u/09u device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm24c08u/09u will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the nm24c08u/09u slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier ( see figure 5) . this is fixed as 1010 for all eeprom devices. slave addresses (figure 5) refer to the following table for slave addresses string details: device a0 a1 a2 page page block blocks addresses nm24c08u/09u p p a 4 00 01 10 11 a: refers to a hardware configured device address pin p: refers to an internal page block memory segment. all iic eeproms use an internal protocol that defines a page block size of 2k bits (for word addressess 0000 through 1111). therefore, address bits a0, a1, or a2 (if designated 'p') are used to access a page block in conjunction with the word address used to access any individual data byte (word). the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the nm24c08u/09u recognizes the start condition, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions.
10 www.fairchildsemi.com nm24c08u/09u rev. b.1 nm24c08u/nm24c09u C 8k-bit serial eeprom 2-wire bus interface write operations byte write for a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. upon receipt of the byte address the nm24c08u/09u responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24c08u/09u begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the nm24c08u/09u inputs are disabled, and the device will not respond to any requests from the master. refer to figure 6 for the address, acknowledge and data transfer sequence. page write the nm24c08u/09u is capable of a sixteen byte page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to fifteen more bytes. after the receipt of each byte, the nm24c08u/09u will respond with an acknowledge. after the receipt of each byte, the internal address counter increments to the next address and the next sda data is accepted. if the master should transmit more than sixteen bytes prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 7 for the address, acknowl- edge, and data transfer sequence. s t o p bus activity: master sda line bus activity: nm24c08u/09u data n + 15 data n + 1 data n word address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master sda line bus activity: nm24c08u/09u ds800009-15 ds800009-16 acknowledge polling once the stop condition is issued to indicate the end of the host s write operation the nm24c08u/09u initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24c08u/09u is still busy with the write operation no ack will be returned. if the nm24c08u/09u has completed the write operation an ack will be returned and the host can then proceed with the next read or write operation. write protection (nm24c09u only) programming of the upper half of the memory will not take place if the wp pin of the nm24c09u is connected to v cc . the nm24c09u will accept slave and byte addresses; but if the memory accessed is write protected by the wp pin, the nm24c09u will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. byte write (figure 6) page write (figure 7)
11 www.fairchildsemi.com nm24c08u/09u rev. b.1 nm24c08u/nm24c09u C 8k-bit serial eeprom 2-wire bus interface s t o p a c k no a c k slave address a c k a c k s t a r t s t a r t word address slave address bus activity: master sda line bus activity: nm24c08u/09u data n s t o p a c k bus activity: master sda line bus activity: nm24c08u/09u a c k data n + x a c k data n + 2 data n +1 data n +1 a c k no a c k slave address ds800009-18 ds800009-19 read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the nm24c08u/09u contains an address counter that maintains the address of the last byte accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the nm24c08u/09u issues an acknowledge and transmits the eight bit byte. the master will not acknowledge the transfer but does generate a stop condition, and therefore the nm24c08u/ 09u discontinues transmission. refer to figure 8 for the se- quence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address and then the byte address it is to read. after the byte address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the nm24c08u/09u and then by the eight bit data. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24c08u/09u discontinues transmission. refer to figure 9 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24c08u/09u continues to output data for each acknowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" and the nm24c08u/09u continues to output data for each acknowledge received. refer to figure 10 for the address, acknowledge, and data transfer sequence. current address read (figure 8) s t o p data a c k no a c k s t a r t slave address bus activity: master sda line bus activity: nm24c08u/09u ds800009-17 random read (figure 9) sequential read (figure 10)
12 www.fairchildsemi.com nm24c08u/09u rev. b.1 nm24c08u/nm24c09u C 8k-bit serial eeprom 2-wire bus interface 8-pin molded small outline package (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x 8-pin molded thin shrink small outline package package number mtc08
13 www.fairchildsemi.com nm24c08u/09u rev. b.1 nm24c08u/nm24c09u C 8k-bit serial eeprom 2-wire bus interface physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom february 2000 ?1998 fairchild semiconductor corporation nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom general description the nm24c16/17 devices are 16,384 bits of cmos non-volatile electrically erasable memory. these devices conform to all speci- fications in the standard iic 2-wire protocol and are designed to minimize device pin count, and simplify pc board layout require- ments. the upper half (upper 8kbit) of the memory of the nm24c17 can be write protected by connecting the wp pin to v cc . this section of memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by the fairchild family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. in order to implement higher eeprom memory densities on the iic bus, the extended iic protocol must be used. (refer to the nm24c32 or nm24c65 datasheets for more infor- mation.) fairchild eeproms are designed and tested for applications requir- ing high endurance, high reliability and low power consumption. block diagram features extended operating voltage 2.7v ?5.5v 400 khz clock frequency (f) at 2.7v - 5.5v 200 a active current typical 10 a standby current typical 1 a standby current typical (l) 0.1 a standby current typical (lz) iic compatible interface ?provides bi-directional data transfer protocol schmitt trigger inputs sixteen byte page write mode ?minimizes total write time per byte self timed write cycle typical write cycle time of 6ms hardware write protect for upper half (nm24c17 only) endurance: 1,000,000 data changes data retention greater than 40 years packages available: 8-pin dip, 8-pin so, and 8-pin tssop available in three temperature ranges - commercial: 0 to +70 c - extended (e): -40 to +85c - automotive (v): -40 to +125 c h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register start stop logic ck d in r/w sda scl v ss wp v cc d out ds500072-1
2 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom nc nc nc v ss v cc nc scl sda 8 7 6 5 1 2 3 4 nm24c16 connection diagrams dual-in-line package (n) and so package (m8) tssop package (mt8) see package number n08e, m08a and mtc08 pin names v ss ground sda serial data i/o scl serial clock input nc no connection v cc power supply dual-in-line package (n) and so package (m8) tssop package (mt8) see package number n08e, m08a and mtc08 pin names nc no connection v ss ground sda serial data i/o scl serial clock input wp write protect v cc power supply nc nc nc v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm24c17 ds500072-2 ds500072-4 nc v cc nc nc scl sda v ss nc 8 7 6 5 1 2 3 4 nm24c16 ds500072-3 wp v cc nc nc scl sda v ss nc 8 7 6 5 1 2 3 4 nm24c17 ds500072-5 note: pins designated as "nc" are typically unbonded pins. however some of them are bonded for special testing purposes. hence if a s ignal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the v cc applied to the device. this will ensure proper operation.
3 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom ordering information nm 24 c xx f t lz e xxx letter description package n 8-pin dip m8 8-pin soic mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current blank normal pin out t rotated die pin out scl clock frequency blank 100khz f 400khz density 16 16k 17 16k with write protect c cmos technology interface 24 iic nm fairchild non-volatile memory
4 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom product specifications absolute maximum ratings ambient storage temperature 65 c to +150 c all input or output voltages with respect to ground 6.5v to 0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c16/17 0 c to +70 c nm24c16e/17e -40 c to +85 c nm24c16v/17v -40 c to +125 c positive power supply nm24c16/17 4.5v to 5.5v nm24c16l/17l 2.7v to 5.5v nm24c16lz/17lz 2.7v to 5.5v dc electrical characteristics (2.7v to 5.5v) symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd v cc = 2.7v - 5.5v 10 50 a or v cc v cc = 2.7v - 5.5v (l) 1 10 a v cc = 2.7v - 4.5v (lz) 0.1 1 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage of 5v for 4.5v-5.5v operation and at 3v for 2.7v-4.5v operation. note 2: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom ac test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.3 to v cc x 0.7 output load 1 ttl gate and c l = 100 pf bus timing ds500072-7 scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto 0.9v cc 0.1v cc 0.7v cc 0.3v cc read and write cycle limits (standard and low v cc range 2.7v - 5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before 4.7 1.3 s a new transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 1.5 s t high clock high period 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 20 20 ns t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 300 50 ns t wr write cycle time - nm24c16/17 10 10 ms (note 3) - nm24c16/17l, nm24c16/17lz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c16/17 bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the devic e does not respond to its slave address. refer "write cycle timing" diagram. ac testing input/output waveforms ds500072-6
6 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc v cc typical system configuration note: due to open drain configuration of sda and scl, a bus-level pull-up resistor is called for, (typical value = 4.7k ? ) ds500072-9 ds500072-8 sda scl stop condition start condition word n 8th bit ack t wr write cycle timing note: the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
7 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom background information (iic bus) iic bus allows synchronous bi-directional communication be- tween a transmitter and a receiver using a clock signal (scl) and a data signal (sda). additionally there are up to three address signals (a2, a1 and a0) which collectively serve as "chip select signal" to a device (example eeprom) on the iic bus. all communication on the iic bus must be started with a valid start condition (by a master), followed by transmittal (by the master) of byte(s) of information (address/data). for every byte of information received, the addressed receiver provides a valid acknowledge pulse to further continue the communication unless the receiver intends to discontinue the communication. depending on the direction of transfer (write or read), the re- ceiver can be a slave or the master. a typical iic communi- cation concludes with a stop condition (by the master). addressing an eeprom memory location involves sending a command string with the following information: [device type] [device/page block selection] [r/w bit] {acknowledge pulse} [array address] slave address slave address is an 8-bit information consisting of a device type field (4bits), device/page block selection field (3bits) and read/ write bit (1bit). slave address format acknowledge acknowledge is an active low pulse on the sda line driven by an addressed receiver to the addressing transmitter to indicate receipt of 8-bits of data. the receiver provides an ack pulse for every 8-bits of data received. this handshake mechanism is done as follows: after transmitting 8-bits of data, the transmitter re- leases the sda line and waits for the ack pulse. the addressed receiver, if present, drives the ack pulse on the sda line during the 9th clock and releases the sda line back (to the transmitter). refer figure 3 . array address array address is an 8-bit information containing the address of a memory location to be selected within a page block of the device. 16k bit addressing limitation: standard iic specification limits the maximum size of eeprom memory on the bus to 16k bits. this limitation is due to the addressing protocol implemented which consists of the 8-bit slave address and an additional 8-bit field called array address. this array address selects 1 out of 256 locations (2 8 =256). since the data format of iic specification is 8-bit wide, a total of 256 x 8 = 2048 = 2k bit now becomes addressable by this 8-bit array address. this 2k bit is typically referred as a page block . combining this 8-bit array address with the 3-bit device/page address (part of slave address) allows a maximum of 8 pages (2 3 =8) of memory that can be addressed. since each page is 2k bit in size, 8 x 2k bit = 16k bit is the maximum size of memory that is addressable on the standard iic bus. this 16kb of memory can be in the form of a single 16kb eeprom device or multiple eeproms of varying density (in 2kb multiples) to a maximum total of 16kb. to address the needs of systems that require more than 16kb on the iic bus, a different specification called ex- tended iic specification is used. please refer to nm24c32xx datasheet for more information on extended iic specification. definitions word 8 bits (byte) of data page 16 sequential byte locations starting at a 16-byte address boundary, that may be pro- grammed during a "page write" programming cycle page block 2048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2048 bits master any iic device controlling the transfer of data (such as a microprocessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) device type identifier device/page block selection 1 0 1 0 a2 a1 a0 r/w (lsb) ds500072-10 device type iic bus is designed to support a variety of devices such as rams, eproms etc., along with eeproms. hence to properly identify various devices on the iic bus, a 4-bit device type identifier string is used. for eeproms, this 4-bit string is 1-0-1-0. every iic device on the bus internally compares this 4-bit string to its own device type string to ensure proper device selection. device/page block selection when multiple devices of the same type (e.g. multiple eeproms) are present on the iic bus, then the a2, a1 and a0 address information bits are also used as part of the slave address. every iic device on the bus internally compares this 3-bit string to its own physical configuration (a2, a1 and a0 pins) to ensure proper device selection. this comparison is in addition to the device type comparison. in addition to selecting an eeprom, these 3 bits are also used to select a page block within the selected eeprom. each page block is 2kbit (256bytes) in size. depend- ing on the density, an eeprom can contain from a minimum of 1 to a maximum of 8 page blocks (in multiples of 2) and selection of a page block within a device is by using a2, a1 and a0 bits. read/write bit last bit of the slave address indicates if the intended access is read or write. if the bit is "1," then the access is read, whereas if the bit is "0," then the access is write.
8 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom eeprom number of device selection inputs address bits density page blocks provided selecting page block 2k bit 1 a0 a1 a2 none 4k bit 2 a1 a2 a0 8k bit 4 a2 a0 and a1 16k bit 8 a0, a1 and a2 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bi-directional pin used to transfer data into and out of the device. it is an open drain output and may be wire ored with any number of open drain or open collector outputs. write protect (wp) (nm24c17 only) if tied to v cc , program operations onto the upper half (upper 8kbit) of the memory will not be executed. read operations are possible. if tied to v ss , normal operation is enabled, read/ write over the entire memory is possible. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. this pin has an internal pull-down circuit. however, on systems where write protection is not required it is recommended that this pin is tied to v ss . device selection inputs a2, a1 and a0 (as appropriate) these inputs collectively serve as chip select signal to an eeprom when multiple eeproms are present on the same iic bus. hence these inputs, if present, should be connected to v cc or v ss in a unique manner to allow proper selection of an eeprom amongst multiple eeproms. during a typical addressing se- quence, every eeprom on the iic bus compares the configura- tion of these inputs to the respective 3 bit device/page block selection information (part of slave address) to determine a valid selection. for e.g. if the 3 bit device/page block selection is 1- 0-1, then the eeprom whose device selection inputs (a2, a1 and a0) are connected to v cc -v ss -v cc respectively, is selected. depending on the density, only appropriate number of device selection inputs are provided on an eeprom. for every device selection input that is not present on the device, the correspond- ing bit in the device/page block selection field is used to select a page block within the device instead of the device itself. following table illustrates the above: note that even when just one eeprom present on the iic bus, these pins should be tied to v cc or v ss to ensure proper termina- tion. device operation the nm24c16/17 supports a bi-directional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm24c16/17 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figure 1 and figure 2 on next page. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24c16/ 17 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24c16/17 to place the device in the standby power mode, except when a write operation is being executed, in which case a second stop condition is required after t wr period, to place the device in standby mode.
9 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom data validity (figure 1) start and stop definition (figure 2) scl from master data output from transmitter data output from receiver 189 start condition acknowledge pulse t aa t dh sda scl start condition stop condition scl data stable data change sda ds500072-11 ds500072-12 ds500072-13 acknowledge response from receiver (figure 3)
10 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom acknowledge the nm24c16/17 device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm24c16/17 will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the nm24c16/17 slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected, nm24c16/17 will continue to transmit data. if an acknowledge is not detected,nm24c16/17 will terminate further data transmissions and await the stop condition to return to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier. this is fixed as 1010 for all eeprom devices. refer the following table for slave addresses string details: device a0 a1 a2 page page block blocks addresses nm24c16/17 p p p 8 000, 001, 010 ... 111 p: refers to an internal page block. all iic eeproms use an internal protocol that defines a page block size of 2k bits (for word addresses 0x00 through 0xff). therefore, address bits a0, a1, or a2 (if designated 'p') are used to access a page block in conjunction with the word address used to access any individual data byte. the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the nm24c16/17 recognizes the start condition, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions. device type identifier 1 0 1 0 a2 a1 a0 r/w (lsb) nm24c16/17 page block address
11 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom write operations byte write for a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. upon receipt of the byte address the nm24c16/17 responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24c16/ 17 begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the nm24c16/17 inputs are disabled, and the device will not respond to any requests from the master for the duration of t wr . refer to figure 4 for the address, acknowledge and data transfer sequence. page write to minimize write cycle time, nm24c16/17 offer page write feature, by which, up to a maximum of 16 contiguous bytes locations can be programmed all at once (instead of 16 individual byte writes). to facilitate this feature, the memory array is orga- nized in terms of pages. a page consists of 16 contiguous byte locations starting at every 16-byte address boundary (for ex- ample, starting at array address 0x00, 0x10, 0x20 etc.). page write operation limits access to byte locations within a page. in other words a single page write operation will not cross over to locations on another page but will roll over to the beginning of the page whenever end of page is reached and additional locations are a continued to be accessed. a page write operation can be initiated to begin at any location within a page (starting address of the page write operation need not be the starting address of a page). s t o p bus activity: master sda line bus activity: eeprom data n + 15 data n + 1 data n word address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master sda line bus activity: eeprom ds500072-14 ds500072-15 page write is initiated in the same manner as the byte write operation; but instead of terminating the cycle after transmitting the first data byte, the master can further transmit up to 15 more bytes. after the receipt of each byte, nm24c16/17 will respond with an acknowledge pulse, increment the internal address counter to the next address and is ready to accept the next data. if the master should transmit more than sixteen bytes prior to generat- ing the stop condition, the address counter will roll over and previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 5 for the address, acknowledge and data transfer sequence. acknowledge polling once the stop condition is issued to indicate the end of the host s write operation the nm24c16/17 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24c16/17 is still busy with the write operation no ack will be returned. if the nm24c16/17 has completed the write operation an ack will be returned and the host can then proceed with the next read or write operation. write protection (nm24c17 only) programming of the upper half (upper 8kbit) of the memory will not take place if the wp pin of the nm24c17 is connected to v cc . the nm24c17 will respond to slave and byte addresses; but if the memory accessed is write protected by the wp pin, the nm24c17 will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. byte write (figure 4) page write (figure 5)
12 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom s t o p a c k no a c k slave address a c k a c k s t a r t s t a r t word address slave address bus activity: master sda line bus activity: eeprom data n s t o p a c k bus activity: master sda line bus activity: eeprom a c k data n + x a c k data n + 2 data n +1 data n +1 a c k no a c k slave address ds500072-17 ds500072-18 read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the nm24c16/17 contains an address counter that maintains the address of the last byte accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the nm24c16/17 issues an acknowledge and transmits the eight bit byte. the master will not acknowledge the transfer but does generate a stop condition, and therefore the nm24c16/17 discontinues transmission. refer to figure 6 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address with the r/w bit set to zero and then the byte address it is to read. after the byte address acknowledge, the master immediately issues another start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the nm24c16/17 and then by the eight bit byte. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24c16/17 discontinues transmission. refer to figure 7 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24c16/17 continues to output data for each ac- knowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" to the beginning of the memory. nm24c16/17 continues to output data for each acknowledge received. refer to figure 8 for the address, acknowledge, and data transfer sequence. current address read (figure 6) s t o p data a c k no a c k s t a r t slave address bus activity: master sda line bus activity: eeprom 1 0 1 0 1 ds500072-16 random read (figure 7) sequential read (figure 8)
13 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom 8-pin molded small outline package (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 8-pin molded thin shrink small outline package (mt8) package number mtc08 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
14 www.fairchildsemi.com nm24c16/17 rev. g nm24c16/17 C 16k-bit standard 2-wire bus interface serial eeprom physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident
1 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface august 1999 ?1999 fairchild semiconductor corporation nm24c16u/nm24c17u 16k-bit serial eeprom 2-wire bus interface general description the nm24c16u/17u devices are 16k (16,384) bit serial interface cmos eeproms (electrically erasable programmable read- only memory). these devices fully conform to the standard i 2 c 2-wire protocol which uses clock (scl) and data i/o (sda) pins to synchronously clock data between the "master" (for example a microprocessor) and the "slave" (the eeprom device). in addi- tion, the serial interface allows a minimal pin count packaging designed to simplify pc board layout requirements and offers the designer a variety of low voltage and low power options. nm24c17u incorporates a hardware "write protect" feature, by which, the upper half of the memory can be disabled against programming by connecting the wp pin to v cc . this section of memory then effectively becomes a rom (read-only memory) and can no longer be programmed as long as wp pin is connected to v cc . fairchild eeproms are designed and tested for applications requir- ing high endurance, high reliability and low power consumption for a continuously reliable non-volatile solution for all markets. block diagram functions i 2 c compatible interface 4,096 bits organized as 512 x 8 extended 2.7v ?5.5v operating voltage 100 khz or 400 khz operation self timed programming cycle (6ms typical) "programming complete" indicated by ack polling nm24c17u: memory "upper block" write protect pin features the i 2 c interface allows the smallest i/o pincount of any eeprom interface 16 byte page write mode to minimize total write time per byte typical 200 a active current (i cca ) typical 1 a standby current (i sb ) for "l" devices and 0.1 a standby current for "lz" devices endurance: up to 1,000,000 data changes data retention greater than 40 years h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic ck d in r/w sda scl v ss wp v cc d out ds800010-1 i 2 c is a registered trademark of philips electronics n.v.
2 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface connection diagrams dual-in-line package (n), 8-pin so package (m8) top view see package number n08e, m08a and mtc08 pin names v ss ground sda serial data i/o scl serial clock input nc no connection v cc power supply dual-in-line package (n), 8-pin so package (m8) top view see package number n08e, m08a and mtc08 pin names v ss ground sda serial data i/o scl serial clock input wp write protect v cc power supply nc no connection nc nc nc v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nc nc nc v ss v cc nc scl sda 8 7 6 5 1 2 3 4 nm24c16u nm24c17u ds800010-2 ds800010-4 8-pin tssop package (mt8) rotated die (24c16ut) nc v cc nc nc scl sda v ss nc 8 7 6 5 1 2 3 4 ds800010-3 nm24c16ut 8-pin tssop package (mt8) rotated die (24c17ut) ds800010-5 wp v cc nc nc scl sda v ss nc 8 7 6 5 1 2 3 4 nm24c17ut
3 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface ordering information nm 24 c xx u f t lz e xx letter description package n 8-pin dip m8 8-pin soic mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current blank normal pin out t rotated die pin out scl clock frequency blank 100khz f 400khz ultralite cs100ul process density 16 16k 17 16k with write protect c cmos technology w total array write protect interface 24 iic nm fairchild non-volatile memory
4 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface product specifications absolute maximum ratings ambient storage temperature 65 c to +150 c all input or output voltages with respect to ground 6.5v to 0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c16u/17u 0 c to +70 c nm24c16ue/17ue -40 c to +85 c nm24c16uv/17uv -40 c to +125 c positive power supply nm24c16u/17u 4.5v to 5.5v nm24c16ul/17ul 2.7v to 5.5v nm24c16ulz/17ulz 2.7v to 5.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd or v cc 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd v cc = 2.7v - 4.5v 1 10 a or v cc v cc = 2.7v - 4.5v 0.1 1 a v cc = 4.5v - 5.5v 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf read and write cycle limits (standard and low v cc range 2.7v - 5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before 4.7 1.3 s a new transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 1.5 s t high clock high period 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 300 50 ns t wr write cycle time - nm24c16u/17u 10 10 ms (note 3) - nm24c16u/17ul, nm24c16u/17ulz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c16u/17u bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the dev ice does not respond to its slave address.
6 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc v cc bus timing system layout typical system configuration note: due to open drain configuration of sda, a bus-level pull-up resistor is called for, (typical value = 4.7k ? ) example of 16k of memory on 2-wire bus device address pins memory size # of page a0 a1 a2 blocks nm24c16u/17u no connect no connect no connect 16,384 bits 8 ds800010-8 ds800010-20 scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto
7 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface device operation background information (iic bus) as mentioned, the iic bus allows synchronous bidirectional com- munication between transmitter/receiver using the scl (clock) and sda (data i/o) lines. all communication must be started with a valid start condition, concluded with a stop condition and acknowledged by the receiver with an acknowledge condi- tion. as shown below, the eeproms on the iic bus may be configured in any manner required, the total memory addressed can not exceed 16k (16,384 bits). eeprom memory address program- ming is controlled by 2 methods: all unused pins must be grounded (tied to v ss ). software addressing the required page block within the device memory array (as sent in the slave address string). for devices with densities greater than 16k, a different protocol, the extended iic protocol, is used. refer to nm24c32u datasheet (for example) for additional details. addressing an eeprom memory location involves sending a command string with the following information: [device type] [device address] [page block ad- dress] [byte address] definitions word 8 bits (byte) of data page 16 sequential addresses (one byte each) that may be programmed during a 'page write' programming cycle page block 2048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 pages) = 2048 bits master any iic device controlling the transfer of data (such as a microprocessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire ored with any number of open drain or open collector outputs. wp write protection (nm24c17u only) if tied to v cc , program operations onto the upper half of the memory will not be executed. read operations are possible. if tied to v ss , normal operation is enabled, read/write over the entire memory is possible. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. device operation the nm24c16u/17u supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm24c16u/17u will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figure 2 and figure 3 on next page. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24c16u/17u continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24c16u/17u to place the device in the standby power mode. write cycle timing acknowledge acknowledge is a hardware convention used to indicate success- ful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line to low to acknowledge that it received the eight bits of data. refer to figure 4.
8 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface ds800010-10 sda scl stop condition start condition word n 8th bit ack t wr write cycle timing (figure 1) note: the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. data validity (figure 2) start and stop definition (figure 3) acknowledge response from receiver (figure 4) scl from master data output from transmitter data output from receiver 189 start acknowledge sda scl start condition stop condition scl data stable data change sda ds800010-11 ds800010-12 ds800010-13
9 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface device type identifier 1 0 1 0 a2 a1 a0 r/w (lsb) nm24c16u/17u page block address ds800010-14 write cycle timing (continued) the nm24c16u/17u device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm24c16u/17u will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the nm24c16u/17u slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier ( see figure 5) . this is fixed as 1010 for all eeprom devices. slave addresses (figure 5) refer to the following table for slave addresses string details: device a0 a1 a2 page page block blocks addresses nm24c16u/17u p p p 8 000 001 010 011 ... 111 p: refers to an internal page block memory segment. all iic eeproms use an internal protocol that defines a page block size of 2k bits (for word addressess 0000 through 1111). therefore, address bits a0, a1, or a2 (if designated 'p') are used to access a page block in conjunction with the word address used to access any individual data byte (word). the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the nm24c16u/17u recognizes the start condition, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions.
10 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface write operations byte write for a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. upon receipt of the byte address the nm24c16u/17u responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24c16u/17u begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the nm24c16u/17u inputs are disabled, and the device will not respond to any requests from the master. refer to figure 6 for the address, acknowledge and data transfer sequence. page write the nm24c16u/17u is capable of a sixteen byte page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to fifteen more bytes. after the receipt of each byte, the nm24c16u/17u will respond with an acknowledge. after the receipt of each byte, the internal address counter increments to the next address and the next sda data is accepted. if the master should transmit more than sixteen bytes prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 7 for the address, acknowl- edge, and data transfer sequence. s t o p bus activity: master sda line bus activity: nm24c16u/17u data n + 15 data n + 1 data n word address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master sda line bus activity: nm24c16u/17u ds800010-15 ds800010-16 acknowledge polling once the stop condition is issued to indicate the end of the host s write operation the nm24c16u/17u initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24c16u/17u is still busy with the write operation no ack will be returned. if the nm24c16u/17u has completed the write operation an ack will be returned and the host can then proceed with the next read or write operation. write protection (nm24c17u only) programming of the upper half of the memory will not take place if the wp pin of the nm24c17u is connected to v cc . the nm24c17u will accept slave and byte addresses; but if the memory accessed is write protected by the wp pin, the nm24c17u will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. byte write (figure 6) page write (figure 7)
11 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface s t o p a c k no a c k slave address a c k a c k s t a r t s t a r t word address slave address bus activity: master sda line bus activity: nm24c16u/17u data n s t o p a c k bus activity: master sda line bus activity: nm24c16u/17u a c k data n + x a c k data n + 2 data n +1 data n +1 a c k no a c k slave address ds800010-18 ds800010-19 read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the nm24c16u/17u contains an address counter that maintains the address of the last byte accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the nm24c16u/17u issues an acknowledge and transmits the eight bit byte. the master will not acknowledge the transfer but does generate a stop condition, and therefore the nm24c16u/ 17u discontinues transmission. refer to figure 8 for the se- quence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address and then the byte address it is to read. after the byte address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the nm24c16u/17u and then by the eight bit data. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24c16u/17u discontinues transmission. refer to figure 9 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24c16u/17u continues to output data for each acknowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" and the nm24c16u/17u continues to output data for each acknowledge received. refer to figure 10 for the address, acknowledge, and data transfer sequence. current address read (figure 8) s t o p data a c k no a c k s t a r t slave address bus activity: master sda line bus activity: nm24c16u/17u ds800010-17 random read (figure 9) sequential read (figure 10)
12 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface 8-pin molded small outline package (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 8-pin molded thin shrink small outline package package number mtc08 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
13 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm24c32 rev. c.2 nm24c32 32k-bit extended 2-wire bus interface serial eeprom with write protect preliminary march 1999 ? 1999 fairchild semiconductor corporation nm24c32 32k-bit extended 2-wire bus interface serial eeprom with write protect general description: the nm24c32 devices are 32,768 bits of cmos nonvolatile electrically erasable memory. these devices offer the designer different low voltage and low power options, and they conform to all specifications in the extended iic 2-wire protocol. furthermore, they are designed to minimize device pin count and simplify pc board layout requirements. the upper half of the memory can be disabled (write protection) by connecting the wp pin to v cc . this section of memory then becomes rom. this communication protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). fairchild eeproms are designed and tested for applications requiring high endurance, high reliability, and low power con- sumption. block diagram features: n extended operating voltage 2.7v C 5.5v n 400 khz clock frequency (f) at 2.7v - 5.5v n 200 m a active current typical 10 m a standby current typical 1 m a standby typical (l) 0.1 m a standby typical (lz) n iic compatible interface C provides bidirectional data transfer protocol n 32 byte page write mode C minimizes total write time per byte n self timed write cycle typical write cycle time of 6ms n hardware write protect for upper block n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin so, 8-pin dip n low v cc programming lockout (3.8v - on standard v cc devices only). ds500073-1 h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic write lockout start cycle ck d in r/w load inc sda scl wp v cc d out a2 a1 a0
2 www.fairchildsemi.com nm24c32 rev. c.2 nm24c32 32k-bit extended 2-wire bus interface serial eeprom with write protect connection diagram dual-in-line package (n) and 8-pin so package (m8) top view see package number n08e and m08a pin names a0, a1, a2 device address input v ss ground sda data i/o scl clock input wp write protect v cc power supply ordering information nm 24 c xx f lz e xx letter description package n 8-pin dip m8 8-pin soic temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current scl clock frequency blank 100khz f 400khz density 32 32k with write protect c cmos interface 24 iic nm fairchild non-volatile memory a0 a1 a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm24c32 ds500073-2
3 www.fairchildsemi.com nm24c32 rev. c.2 nm24c32 32k-bit extended 2-wire bus interface serial eeprom with write protect product specifications absolute maximum ratings ambient storage temperature C65 c to +150 c all input or output voltages with respect to ground 6.5v to C0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c32 0 c to +70 c nm24c32e -40 c to +85 c nm24c32v -40 c to +125 c positive power supply nm24c32 4.5v to 5.5v nm24c32l 2.7v to 4.5v nm24c32lz 2.7v to 4.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ (note 1) max i cca active power supply current f scl = 100 khz 0.2 1.0 ma i sb standby current v in = gnd or v cc 10 50 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 4.5v) dc electrical characteristics symbol parameter test conditions limits units min typ (note 1) max i cca active power supply current f scl = 100 khz 0.2 1.0 ma i sb standby current for l v in = gnd or v cc 110 m a (note 1) standby current for lz v in = gnd or v cc 0.1 1 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1 : typical values are for t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm24c32 rev. c.2 nm24c32 32k-bit extended 2-wire bus interface serial eeprom with write protect ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf read and write cycle limits (standard and low v cc range - 2.7v-5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 m s t buf time the bus must be free before 4.7 1.3 m s a new transmission can start t hd:sta start condition hold time 4.0 0.6 m s t low clock low period 4.7 1.5 m s t high clock high period 4.0 0.6 m s t su:sta start condition setup time 4.7 0.6 m s (for a repeated start condition) t hd:dat data in hold time 0 0 ns t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 m s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 m s t dh data out hold time 300 50 ns t wr write cycle time - nm24c32 10 10 ms (note 3) - nm24c32l, nm24c32lz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c32 bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the device d oes not respond to its slave address
5 www.fairchildsemi.com nm24c32 rev. c.2 nm24c32 32k-bit extended 2-wire bus interface serial eeprom with write protect background information (iic bus) as mentioned, the iic bus allows synchronous bidirectional commu- nication between transmitter/receiver using the scl (clock) and sda (data i/o) lines. all communication must be started with a valid start condition, concluded with a stop condition and acknowl- edged by the receiver with an acknowledge condition. in addition, since the iic bus is designed to support other devices such as ram, eprom, etc., the device type identifier string, or slave address, must follow the start condition. for eeproms, the first 4-bits of the slave address is '1010'. this is then followed by the device selection bits a2, a1 and a0.the final bit in the slave address determines the type of operation performed (read/ write). a "1" signifies a read while a "0" signifies a write. the slave address is then followed by two bytes that define the word address, which is then followed by the data byte. the eeproms on the iic bus may be configured in any manner required, providing the total memory addressed does not exceed 4m bits in the extended iic protocol. eeprom memory address- ing is controlled by hardware configuring the a2, a1, and a0 pins (device address pins) with pull-up or pull-down resistors. all unused pins must be grounded (tied to v ss ). addressing an eeprom memory location involves sending a command string with the following information: [device type]-[device address]-[page block ad- dress]-[byte address] definitions word 8 bits (byte) of data page 32 sequential addresses (one byte each) that may be programmed during a "page write" programming cycle. master any iic device controlling the transfer of data (such as a microcon- troller). slave device being controlled (eeproms are always considered slaves). transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave). pin description serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a biderectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto bus timing ds500073-3
6 www.fairchildsemi.com nm24c32 rev. c.2 nm24c32 32k-bit extended 2-wire bus interface serial eeprom with write protect device address inputs (a0, a1, a2) device address pins a0, a1, and a2 are connected to v cc or v ss to configure the eeprom address for multiple device configura- tion. a total of eight different devices can be attached to the same sda bus. write protection (wp ) if wp is tied to v cc , program write operations onto the upper half of the memory will not be executed. read operations are always available. if wp is tied to v ss , normal memory operation is enabled, read/ write over the entire memory array. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming writes. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. device operation the nm24c32xxx supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving devices as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm24c32xxx is considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high and reserved for indicating start and stop conditions. refer to figures 2 and 3. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24c32xxx continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24c32xxx to place the device in the standby power mode. write cycle timing acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 4 . the nm24c32xxx device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm24c32xxx will respond with an acknowledge after the receipt of each subsequent eight bit word. in the read mode the nm24c32xxx slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode.
7 www.fairchildsemi.com nm24c32 rev. c.2 nm24c32 32k-bit extended 2-wire bus interface serial eeprom with write protect write cycle timing (figure 1) sda scl stop condition start condition word n 8th bit ack t wr sda scl data stable data change sda scl start bit stop bit ds500073-4 ds500073-5 data validity (figure 2) ds500073-6 definition of start and stop (figure 3) scl from master data output from transmitter data output from receiver start acknowledge 189 acknowledge response from receiver (figure 4) ds500073-7
8 www.fairchildsemi.com nm24c32 rev. c.2 nm24c32 32k-bit extended 2-wire bus interface serial eeprom with write protect s t o p a c k bus activity: master sda line 1010 0000 bus activity a c k data a c k a c k word address (1) word address (0) slave address s t a r t device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier. this is fixed as 1010 for all eeprom devices. the next three bits identifies the device address. address from 000 to 111 are acceptable thus allowing up to eight devices to be connected to the iic bus. the last bit of the slave address defines whether a write or read condition is requested by the master. a "1" indicates that a read operation is to be executed and a "0" initiates the write mode. a simple review: after the nm24c32xxx recognizes the start condition, the devices interfaced to the iic bus waits for a slave address to be transmitted over the sda line. if the transitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge. signal and awaits further transmissions. write operations byte write for a write operation, two additional address bytes, with 12 active bits, are required after the slave acknowledge to address the full memory array. the first byte indicates the high-order byte of the word address. only the four least signicant bits can be changed, the other bits are pre-assigned the value "0". following the acknowledgement from the first word address, the next byte indicates the low-order byte of the word address. upon receipt of the word address, the nm24c32xxx responds with another ac- knowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24c32xxx begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress, the device's inputs are disabled and the device will not respond to any requests from the master. refer to figure 5 for the address, acknowledge and data transfer sequence. page write the nm24c32xxx is capable of thirty-two byte page write opera- tion. it is initiated in the same manner as the byte write operation; but instead of termination the write cycle after the first data word is transfered, the master can transmit up to thirty-one more words. after the receipt of each word, the device responds with an acknowledge. after the receipt of each word, the internal address counter increments to the next address and the next sda data is ac- cepted. if the master should transmit more than thirty-two words prior to generating the stop condition, the address counter will "roll over" and the previous written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 6 for the address, acknowl- edge and data transfer sequence. acknowledge polling once the stop condition is isssued to indicate the end of the host's write operation, the nm24c32xxx initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24c32xxx is still busy with the write operation, no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. ds500073-8 byte write (figure 5)
9 www.fairchildsemi.com nm24c32 rev. c.2 nm24c32 32k-bit extended 2-wire bus interface serial eeprom with write protect write protection programming of the upper half of memory will not take place if the wp pin is connected to v cc . the device will accept slave and word addresses; but if the memory accessed is write protected by the wp pin, the nm24c32xxx will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. low v cc lockout nm24c32xxx provides data security against inadvertent writes that could potentially happen during the time the device is being powered on, powered down and brown out conditions by monitor- ing the v cc voltage during a write cycle. whenever a write cycle is started, the built-in circuitry starts to monitor the v cc level throughout the duration of the write command sequence until the master issues the required stop condition to start the actual internal write operation. if the sensed v cc voltage is below 3.8v at any point during this monitoring period, the device prohibits the write operation and does not generate the ack pulse. this low v cc lockout feature is only available for standard 5v device. read operation read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to "1". there are three basic read operations: current address read, random read and sequential read. current address read internally the nm24c32xxx contains an address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n+1. upon receipt of the slave address with r/w set to one, the nm24c32xxx issues an acknowledge and transmits the eight bit word. the master will not acknowledge acknowledge the transfer but does generate a stop condition, and therefore discon- tinues transmission. refer to figure 7 for the sequence of ad- dress, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to "1", the master must first perform a "dummy" write operation. the master issues a start condition, slave address and then the word address it is to read. after the word address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to "1". this will be followed by an acknowledge from the nm24c32xxx and then by the eight bit word. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24c32xxx discontinues transmission. refer to figure 8 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24c32xxx continues to output data for each ac- knowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data n+1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" and the nm24c32xxx continues to output data for each acknowledge received. refer to figure 9 for the address, acknowledge and data transfer sequence. s t o p a c k a c k bus activity: master sda line 1010 0000 bus activity a c k data n data n+31 a c k word address (1) word address (0) slave address s t a r t ds500073-9 page write (figure 6)
10 www.fairchildsemi.com nm24c32 rev. c.2 nm24c32 32k-bit extended 2-wire bus interface serial eeprom with write protect current address read (figure 7) random read (figure 8) sequential read (figure 9) s t o p a c k no a c k bus activity: master sda line 1010 bus activity a c k data n + x a c k data n + 1 data n slave address a c k s t a r t s t o p a c k no a c k bus activity: master sda line 1010 10 10 10 0000 bus activity a c k a c k word address (1) word address (0) data n slave address slave address a c k s t a r t s t a r t s t o p a c k no a c k 10 10 data slave address s t a r t ds500073-10 ds500073-11 ds500073-12
11 www.fairchildsemi.com nm24c32 rev. c.2 nm24c32 32k-bit extended 2-wire bus interface serial eeprom with write protect molded small out-line package (m8) order number nm24c32xxxm8 or nm24c32xxxem8 package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
12 www.fairchildsemi.com nm24c32 rev. c.2 nm24c32 32k-bit extended 2-wire bus interface serial eeprom with write protect physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) order number nm24c32xxxn or nm24c32xxxen package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm24c32u rev. c.1 nm24c32u 32k-bit serial eeprom with write protect 2-wire bus interface preliminary august 1999 ?1999 fairchild semiconductor corporation nm24c32u 32k-bit serial eeprom with write protect 2-wire bus interface general description: the nm24c32u is a 32k (32,768) bit serial interface cmos eeprom (electrically erasable programmable read-only memory). this device fully conforms to the extended i 2 c 2-wire protocol which uses clock (scl) and data i/o (sda) pins to synchronously clock data between the "master" (for example a microprocessor) and the "slave" (the eeprom device). in addi- tion, the serial interface allows a minimal pin count packaging designed to simplify pc board layout requirements and offers the designer a variety of low voltage and low power options. nm24c32u incorporates a hardware "write protect" feature, by which, the upper half of the memory can be disabled against programming by connecting the wp pin to v cc . this section of memory then effectively becomes a rom (read-only memory) and can no longer be programmed as long as wp pin is connected to v cc . fairchild eeproms are designed and tested for applications requir- ing high endurance, high reliability and low power consumption for a continuously reliable non-volatile solution for all markets. block diagram functions i 2 c compatible interface 32,768 bits organized as 4,096 x 8 extended 2.7v ?5.5v operating voltage 100 khz or 400 khz operation self timed programming cycle (6ms typical) "programming complete" indicated by ack polling memory "upper block" write protect pin features the i 2 c interface allows the smallest i/o pincount of any eeprom interface 32 byte page write mode to minimize total write time per byte low v cc programming lockout (3.8v) ? "h" option (standard v cc range) parts only typical 200 a active current (i cca ) typical 1 a standby current (i sb ) for "l" devices and 0.1 a standby current for "lz" devices endurance: up to 1,000,000 data changes data retention greater than 40 years ds800011-1 h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic write lockout start cycle ck d in r/w load inc sda scl wp v cc d out a2 a1 a0 i 2 c is a registered trademark of philips electronics n.v.
2 www.fairchildsemi.com nm24c32u rev. c.1 nm24c32u 32k-bit serial eeprom with write protect 2-wire bus interface connection diagram dual-in-line package (n) and 8-pin so package (m8) top view see package number n08e and m08a pin names a0, a1, a2 device address input v ss ground sda data i/o scl clock input wp write protect v cc power supply ordering information nm 24 c xx u f lz e xx letter description package n 8-pin dip m8 8-pin soic temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current h 4.5v to 5.5v and v cc lockout scl clock frequency blank 100khz f 400khz ultralite cs100ul process density 32 32k with write protect c cmos interface 24 iic nm fairchild non-volatile memory a0 a1 a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm24c32u ds800011-2
3 www.fairchildsemi.com nm24c32u rev. c.1 nm24c32u 32k-bit serial eeprom with write protect 2-wire bus interface product specifications absolute maximum ratings ambient storage temperature 65 c to +150 c all input or output voltages with respect to ground 6.5v to 0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c32u 0 c to +70 c nm24c32ue -40 c to +85 c nm24c32uv -40 c to +125 c positive power supply nm24c32u/nm24c32uh 4.5v to 5.5v nm24c32ul 2.7v to 5.5v nm24c32ulz 2.7v to 5.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units mintyp max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd or v cc 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 5 .5v) dc electrical characteristics symbol parameter test conditions limits units mintyp max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd v cc = 2.7v - 4.5v 1 10 a or v cc v cc = 2.7v - 4.5v 0.1 1 a v cc = 4.5v - 5.5v 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm24c32u rev. c.1 nm24c32u 32k-bit serial eeprom with write protect 2-wire bus interface ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf read and write cycle limits (standard and low v cc range - 2.7v-5.5v) symbol parameter 100 khz 400 khz units minmax minmax f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before 4.7 1.3 s a new transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 1.5 s t high clock high period 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 300 50 ns t wr write cycle time - nm24c32u 10 10 ms (note 3) - nm24c32ul, nm24c32ulz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c32u bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address
5 www.fairchildsemi.com nm24c32u rev. c.1 nm24c32u 32k-bit serial eeprom with write protect 2-wire bus interface background information (iic bus) as mentioned, the iic bus allows synchronous bidirectional commu- nication between transmitter/receiver using the scl (clock) and sda (data i/o) lines. all communication must be started with a valid start condition, concluded with a stop condition and acknowl- edged by the receiver with an acknowledge condition. in addition, since the iic bus is designed to support other devices such as ram, eprom, etc., the device type identifier string, or slave address, must follow the start condition. for eeproms, the first 4-bits of the slave address is '1010'. this is then followed by the device selection bits a2, a1 and a0.the final bit in the slave address determines the type of operation performed (read/ write). a "1" signifies a read while a "0" signifies a write. the slave address is then followed by two bytes that define the word address, which is then followed by the data byte. the eeproms on the iic bus may be configured in any manner required, providing the total memory addressed does not exceed 4m bits in the extended iic protocol. eeprom memory address- ing is controlled by hardware configuring the a2, a1, and a0 pins (device address pins) with pull-up or pull-down resistors. all unused pins must be grounded (tied to v ss ). addressing an eeprom memory location involves sending a command string with the following information: [device type]-[device address]-[page block ad- dress]-[byte address] definitions word 8 bits (byte) of data page 32 sequential addresses (one byte each) that may be programmed during a "page write" programming cycle. master any iic device controlling the transfer of data (such as a microcon- troller). slave device being controlled (eeproms are always considered slaves). transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave). pin description serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a biderectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto bus timing ds800011-3
6 www.fairchildsemi.com nm24c32u rev. c.1 nm24c32u 32k-bit serial eeprom with write protect 2-wire bus interface device address inputs (a0, a1, a2) device address pins a0, a1, and a2 are connected to v cc or v ss to configure the eeprom address for multiple device configura- tion. a total of eight different devices can be attached to the same sda bus. write protection (wp ) if wp is tied to v cc , program write operations onto the upper half of the memory will not be executed. read operations are always available. if wp is tied to v ss , normal memory operation is enabled, read/ write over the entire memory array. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming writes. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. device operation the nm24c32uxxx supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter and the receiving devices as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm24c32uxxx is considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high and reserved for indicating start and stop conditions. refer to figures 2 and 3. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24c32uxxx continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24c32uxxx to place the device in the standby power mode. write cycle timing acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 4 . the nm24c32uxxx device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm24c32uxxx will respond with an acknowledge after the receipt of each subsequent eight bit word. in the read mode the nm24c32uxxx slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode.
7 www.fairchildsemi.com nm24c32u rev. c.1 nm24c32u 32k-bit serial eeprom with write protect 2-wire bus interface write cycle timing (figure 1) sda scl stop condition start condition word n 8th bit ack t wr scl data stable data change sda sda scl start condition stop condition ds800011-4 ds800011-5 data validity (figure 2) ds800011-6 definition of start and stop (figure 3) scl from master data output from transmitter data output from receiver start acknowledge 189 acknowledge response from receiver (figure 4) ds800011-7
8 www.fairchildsemi.com nm24c32u rev. c.1 nm24c32u 32k-bit serial eeprom with write protect 2-wire bus interface s t o p a c k bus activity: master sda line 1010 0000 bus activity a c k data a c k a c k word address (1) word address (0) slave address s t a r t device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier. this is fixed as 1010 for all eeprom devices. the next three bits identifies the device address. address from 000 to 111 are acceptable thus allowing up to eight devices to be connected to the iic bus. the last bit of the slave address defines whether a write or read condition is requested by the master. a "1" indicates that a read operation is to be executed and a "0" initiates the write mode. a simple review: after the nm24c32uxxx recognizes the start condition, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions. write operations byte write for a write operation, two additional address bytes, with 12 active bits, are required after the slave acknowledge to address the full memory array. the first byte indicates the high-order byte of the word address. only the four least signicant bits can be changed, the other bits are pre-assigned the value "0". following the acknowledgement from the first word address, the next byte indicates the low-order byte of the word address. upon receipt of the word address, the nm24c32uxxx responds with another acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24c32uxxx begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress, the device's inputs are disabled and the device will not respond to any requests from the master. refer figure 5 for the byte write sequence. page write the nm24c32uxxx is capable of thirty-two byte page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data word is transfered, the master can transmit up to thirty-one more words. after the receipt of each word, the device responds with an acknowledge. after the receipt of each word, the internal address counter increments to the next address and the next sda data is ac- cepted. if the master should transmit more than thirty-two words prior to generating the stop condition, the address counter will "roll over" and the previous written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer figure 6 for the page write sequence. acknowledge polling once the stop condition is isssued to indicate the end of the host's write operation, the nm24c32uxxx initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24c32uxxx is still busy with the write opera- tion, no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. byte write (figure 5) ds800011-8
9 www.fairchildsemi.com nm24c32u rev. c.1 nm24c32u 32k-bit serial eeprom with write protect 2-wire bus interface write protection programming of the upper half of memory will not take place if the wp pin is connected to v cc . the device will accept slave and word addresses; but if the memory accessed is write protected by the wp pin, the nm24c32uxxx will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. low v cc lockout nm24c32uxhx (h option) protects against data corruption during programming by preventing any programming operations if v cc drops below approximately 3.8v (v cc lockout trip level). this is accomplished by monitoring the "read/write" (r/w) bit in the slave address and if the r/w bit is "0," indicating a programming operation, the v cc lockout is activated. at that point, if the v cc drops below the trip level, programming is inhibited and the device does not issue an ack (the output stays high). to restate, the v cc lockout feature is active from the time a write bit is received up to the time that the master's stop condition is received (the stop condition turns on the v pp internal high voltage). once program- ming has begun, the programming cycle cannot be inter- rupted except by removal of v cc , which could result in data corruption. read operation read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to "1". there are three basic read operations: current address read, random read and sequential read. current address read internally the nm24c32uxxx contains an address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n+1. upon receipt of the slave address with r/w set to one, the nm24c32uxxx issues an acknowledge and transmits the eight bit word. the master will not acknowledge the transfer but does generate a stop condition, and therefore discontinues trans- mission. refer figure 7 for the current address read sequence. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to "1", the master must first perform a "dummy" write operation. the master issues a start condition, slave address with the r/w bit set to "0" and then the word address it is to read from. after the word address acknowledge, the master immedi- ately reissues the start condition and the slave address with the r/ w bit set to "1". this will be followed by an acknowledge from the nm24c32uxxx and then by the eight bit data. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24c32uxxx discontinues transmission. refer figure 8 for the random read sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24c32uxxx continues to output data for each acknowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data n+1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" and the nm24c32uxxx continues to output data for each acknowledge received. refer figure 9 for the sequential read sequence. s t o p a c k a c k bus activity: master sda line 1010 0000 bus activity a c k data n data n+31 a c k word address (1) word address (0) slave address s t a r t ds800011-9 page write (figure 6)
10 www.fairchildsemi.com nm24c32u rev. c.1 nm24c32u 32k-bit serial eeprom with write protect 2-wire bus interface current address read (figure 7) random read (figure 8) sequential read (figure 9) s t o p a c k no a c k bus activity: master sda line 1010 bus activity a c k data n + x a c k data n + 1 data n slave address a c k s t a r t s t o p a c k no a c k bus activity: master sda line 1010 0 1 10 10 0000 bus activity a c k a c k word address (1) word address (0) data n slave address slave address a c k s t a r t s t a r t s t o p a c k no a c k 10 10 data slave address s t a r t ds800011-10 ds800011-11 ds800011-12
11 www.fairchildsemi.com nm24c32u rev. c.1 nm24c32u 32k-bit serial eeprom with write protect 2-wire bus interface molded small out-line package (m8) order number nm24c32uxxxm8 or nm24c32uxxxem8 package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
12 www.fairchildsemi.com nm24c32u rev. c.1 nm24c32u 32k-bit serial eeprom with write protect 2-wire bus interface physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) order number nm24c32uxxxn or nm24c32uxxxen package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm24c65 rev. c.3 nm24c65 64k-bit extended 2-wire bus interface serial eeprom with write protect preliminary march 1999 ? 1999 fairchild semiconductor corporation nm24c65 64k-bit extended 2-wire bus interface serial eeprom with write protect general description: the nm24c65 devices are 65,536 bits of cmos nonvolatile electrically erasable memory. these devices offer the designer different low voltage and low power options, and they conform to all in the extended iic 2-wire protocol. furthermore, they are designed to minimize device pin count and simplify pc board layout requirements. the upper half of the memory can be disabled (write protection) by connecting the wp pin to v cc . this section of memory then becomes rom. this communication protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). fairchild eeproms are designed and tested for applications requiring high endurance, high reliability, and low power con- sumption. block diagram features: n extended operating voltage 2.7v C 5.5v n 400 khz clock frequency (f) at 2.7v - 5.5v n 200 m a active current typical 10 m a standby current typical 1 m a standby typical (l) 0.1 m a standby typical (lz) n iic compatible interface C provides bidirectional data transfer protocol n 32 byte page write mode C minimizes total write time per byte n self timed write cycle typical write cycle time of 6ms n hardware write protect for upper block n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin so, 8-pin dip n low v cc programming lockout (3.8v - on standard v cc devices only). ds500042-1 h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic write lockout start cycle ck d in r/w load inc sda scl wp v cc d out a2 a1 a0
2 www.fairchildsemi.com nm24c65 rev. c.3 nm24c65 64k-bit extended 2-wire bus interface serial eeprom with write protect connection diagram dual-in-line package (n) and 8-pin so package (m8) top view see package number n08e and m08a pin names a0, a1, a2 device address input v ss ground sda data i/o scl clock input wp write protect v cc power supply ordering information nm 24 c xx f lz e xx letter description package n 8-pin dip m8 8-pin so8 temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current scl clock frequency blank 100khz f 400khz density 65 64k with write protect c cmos interface 24 iic nm fairchild non-volatile memory a0 a1 a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm24c65 ds500042-2
3 www.fairchildsemi.com nm24c65 rev. c.3 nm24c65 64k-bit extended 2-wire bus interface serial eeprom with write protect product specifications absolute maximum ratings ambient storage temperature C65 c to +150 c all input or output voltages with respect to ground 6.5v to C0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c65 0 c to +70 c nm24c65e -40 c to +85 c nm24c65v -40 c to +125 c positive power supply nm24c65 4.5v to 5.5v nm24c65l 2.7v to 4.5v nm24c65lz 2.7v to 4.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ (note 1) max i cca active power supply current f scl = 100 khz 0.2 1.0 ma i sb standby current v in = gnd or v cc 10 50 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 4.5v) dc electrical characteristics symbol parameter test conditions limits units min typ (note 1) max i cca active power supply current f scl = 100 khz 0.2 1.0 ma i sb standby current for l v in = gnd or v cc 110 m a (note 1) standby current for lz v in = gnd or v cc 0.1 1 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1 : typical values are for t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm24c65 rev. c.3 nm24c65 64k-bit extended 2-wire bus interface serial eeprom with write protect ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf read and write cycle limits (standard and low v cc range - 2.7v-5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 m s t buf time the bus must be free before 4.7 1.3 m s a new transmission can start t hd:sta start condition hold time 4.0 0.6 m s t low clock low period 4.7 1.5 m s t high clock high period 4.0 0.6 m s t su:sta start condition setup time 4.7 0.6 m s (for a repeated start condition) t hd:dat data in hold time 0 0 ns t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 m s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 m s t dh data out hold time 300 50 ns t wr write cycle time - nm24c65 10 10 ms (note 3) - nm24c65l, nm24c65lz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c65 bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the device d oes not respond to its slave address
5 www.fairchildsemi.com nm24c65 rev. c.3 nm24c65 64k-bit extended 2-wire bus interface serial eeprom with write protect background information (iic bus) as mentioned, the iic bus allows synchronous bidirectional commu- nication between transmitter/receiver using the scl (clock) and sda (data i/o) lines. all communication must be started with a valid start condition, concluded with a stop condition and acknowl- edged by the receiver with an acknowledge condition. in addition, since the iic bus is designed to support other devices such as ram, eprom, etc., the device type identifier string, or slave address, must follow the start condition. for eeproms, the first 4-bits of the slave address is '1010'. this is then followed by the device selection bits a2, a1 and a0.the final bit in the slave address determines the type of operation performed (read/ write). a "1" signifies a read while a "0" signifies a write. the slave address is then followed by two bytes that define the word address, which is then followed by the data byte. the eeproms on the iic bus may be configured in any manner required, providing the total memory addressed does not exceed 4m bits in the extended iic protocol. eeprom memory address- ing is controlled by hardware configuring the a2, a1, and a0 pins (device address pins) with pull-up or pull-down resistors. all unused pins must be grounded (tied to v ss ). addressing an eeprom memory location involves sending a command string with the following information: [device type]-[device address]-[page block ad- dress]-[byte address] definitions word 8 bits (byte) of data page 32 sequential addresses (one byte each) that may be programmed during a "page write" programming cycle. master any iic device controlling the transfer of data (such as a microcontroller). slave device being controlled (eeproms are always considered slaves). transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave). pin description serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a biderectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. device address inputs (a0, a1, a2) device address pins a0, a1, and a2 are connected to v cc or v ss to configure the eeprom address for multiple device configuration. a total of eight different devices can be attached to the same sda bus. write protection (wp ) if wp is tied to v cc , program write operations onto the upper half of the memory will not be executed. read operations are always available. if wp is tied to v ss , normal memory operation is enabled, read/ write over the entire bit memory array. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming writes. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. device operation the nm24c65xxx supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving devices as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. there- fore, the nm24c65xxx is considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high and reserved for indicating start and stop conditions. refer to figures 2 and 3. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24c65xxx continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24c65xxx to place the device in the standby power mode. scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto ds500042-3 bus timing
6 www.fairchildsemi.com nm24c65 rev. c.3 nm24c65 64k-bit extended 2-wire bus interface serial eeprom with write protect write cycle timing acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 4 . the nm24c65xxx device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if write cycle timing (figure 1) sda scl stop condition start condition word n 8th bit ack t wr sda scl data stable data change sda scl start bit stop bit ds500042-4 ds500042-5 data validity (figure 2) definition of start and stop (figure 3) ds500042-6 both the device and a write operation have been selected, the nm24c65xxx will respond with an acknowledge after the receipt of each subsequent eight bit word. in the read mode the nm24c65xxx slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode. scl from master data output from transmitter data output from receiver start acknowledge 189 acknowledge response from receiver (figure 4) ds500042-7
7 www.fairchildsemi.com nm24c65 rev. c.3 nm24c65 64k-bit extended 2-wire bus interface serial eeprom with write protect s t o p a c k bus activity: master sda line 1010 000 bus activity a c k data a c k a c k word address (1) word address (0) slave address s t a r t device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier. this is fixed as 1010 for all eeprom devices. the next three bits identifies the device address. address from 000 to 111 are acceptable thus allowing up to eight devices to be connected to the iic bus. the last bit of the slave address defines whether a write or read condition is requested by the master. a "1" indicates that a read operation is to be executed and a "0" initiates the write mode. a simple review: after the nm24c65xxx recognizes the start condition, the devices interfaced to the iic bus waits for a slave address to be transmitted over the sda line. if the transitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge. signal and awaits further transmissions. write operations byte write for a write operation, two additional address bytes, with 13 active bits, are required after the slave acknowledge to address the full memory array. the first byte indicates the high-order byte of the word address. only the five least signicant bits can be changed, the other bits are pre-assigned the value "0". following the acknowledgement from the first word address, the next byte indicates the low-order byte of the word address. upon receipt of the word address, the nm24c65xxx responds with another ac- knowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24c65xxx begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress, the device's inputs are disabled and the device will not respond to any requests from the master. refer to figure 5 for the address, acknowledge and data transfer sequence. page write the nm24c65xxx is capable of thirty-two byte page write opera- tion. it is initiated in the same manner as the byte write operation; but instead of termination the write cycle after the first data word is transfered, the master can transmit up to thirty-one more words. after the receipt of each word, the device responds with an acknowledge. after the receipt of each word, the internal address counter increments to the next address and the next sda data is ac- cepted. if the master should transmit more than thirty-two words prior to generating the stop condition, the address counter will "roll over" and the previous written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 6 for the address, acknowl- edge and data transfer sequence. acknowledge polling once the stop condition is isssued to indicate the end of the host's write operation, the nm24c65xxx initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24c65xxx is still busy with the write operation, no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. ds500042-8 byte write (figure 5)
8 www.fairchildsemi.com nm24c65 rev. c.3 nm24c65 64k-bit extended 2-wire bus interface serial eeprom with write protect write protection programming of the upper half of memory will not take place if the wp pin is connected to v cc . the device will accept slave and word addresses; but if the memory accessed is write protected by the wp pin, the nm24c65xxx will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. low v cc lockout nm24c65xxx provides data security against inadvertent writes that could potentially happen during the time the device is being powered on, powered down and brown out conditions by monitor- ing the v cc voltage during a write cycle. whenever a write cycle is started, the built-in circuitry starts to monitor the v cc level throughout the duration of the write command sequence until the master issues the required stop condition to start the actual internal write operation. if the sensed v cc voltage is below 3.8v at any point during this monitoring period, the device prohibits the write operation and does not generate the ack pulse. this low v cc lockout feature is only available for standard 5v device. read operation read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to "1". there are three basic read operations: current address read, random read and sequential read. current address read internally the nm24c65xxx contains an address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n+1. upon receipt of the slave address with r/w set to one, the nm24c65xxx issues an acknowledge and transmits the eight bit word. the master will not acknowledge acknowledge the transfer but does generate a stop condition, and therefore discon- tinues transmission. refer to figure 7 for the sequence of ad- dress, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to "1", the master must first perform a "dummy" write operation. the master issues a start condition, slave address and then the word address it is to read. after the word address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to "1". this will be followed by an acknowledge from the nm24c65xxx and then by the eight bit word. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24c65xxx discontinues transmission. refer to figure 8 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24c65xxx continues to output data for each ac- knowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n, followed by the data n+1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" and the nm24c65xxx continues to output data for each acknowledge received. refer to figure 9 for the address, acknowledge and data transfer sequence. s t o p a c k a c k bus activity: master sda line 1010 000 bus activity a c k data n data n+31 a c k word address (1) word address (0) slave address s t a r t ds500042-9 page write (figure 6)
9 www.fairchildsemi.com nm24c65 rev. c.3 nm24c65 64k-bit extended 2-wire bus interface serial eeprom with write protect current address read (figure 7) random read (figure 8) sequential read (figure 9) s t o p a c k no a c k bus activity: master sda line 1010 bus activity a c k data n + x a c k data n + 1 data n slave address a c k s t a r t s t o p a c k no a c k bus activity: master sda line 1010 10 10 10 000 bus activity a c k a c k word address (1) word address (0) slave address slave address data n a c k s t a r t s t a r t s t o p a c k no a c k 10 10 data slave address s t a r t ds500042-10 ds500042-11 ds500042-12
10 www.fairchildsemi.com nm24c65 rev. c.3 nm24c65 64k-bit extended 2-wire bus interface serial eeprom with write protect molded small out-line package (m8) order number nm24c65xxxm8 or nm24c65xxxem8 package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
11 www.fairchildsemi.com nm24c65 rev. c.3 nm24c65 64k-bit extended 2-wire bus interface serial eeprom with write protect physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) order number nm24c65xxxn or nm24c65xxxen package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm24c65u rev. b.1 nm24c65u 64k-bit serial eeprom with write protect 2-wire bus interface preliminary august 1999 ?1999 fairchild semiconductor corporation nm24c65u 64k-bit serial eeprom with write protect 2-wire bus interface general description: the nm24c65u is a 64k (65,536) bit serial interface cmos eeprom (electrically erasable programmable read-only memory). this device fully conforms to the extended i 2 c 2-wire protocol which uses clock (scl) and data i/o (sda) pins to synchronously clock data between the "master" (for example a microprocessor) and the "slave" (the eeprom device). in addi- tion, the serial interface allows a minimal pin count packaging designed to simplify pc board layout requirements and offers the designer a variety of low voltage and low power options. nm24c65u incorporates a hardware "write protect" feature, by which the upper half of the memory can be disabled against programming by connecting the wp pin to v cc . this section of memory then effectively becomes a rom (read-only memory) and can no longer be programmed as long as wp pin is connected to v cc . fairchild eeproms are designed and tested for applications requir- ing high endurance, high reliability and low power consumption for a block diagram continuously reliable non-volatile solution for all markets. functions i 2 c compatible interface 65,536 bits organized as 8,192 x 8 100 khz or 400 khz operation extended 2.7v ?5.5v operating voltage self timed programming cycle (6ms typical) "programming complete" indicated by ack polling memory "upper block" write protect pin features the i 2 c interface allows the smallest i/o pincount of any eeprom interface 32 byte page write mode to minimize total write time per byte low v cc programming lockout (3.8v) ? "h" option (standard v cc range) parts only typical 200 a active current (i cca ) typical 1 a standby current (i sb ) for "l" devices and 0.1 a standby current for "lz" devices endurance: up to 1,000,000 data changes data retention greater than 40 years ds800012-1 h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic write lockout start cycle ck d in r/w load inc sda scl wp v cc d out a2 a1 a0 i 2 c is a registered trademark of philips electronics n.v.
2 www.fairchildsemi.com nm24c65u rev. b.1 nm24c65u 64k-bit serial eeprom with write protect 2-wire bus interface connection diagram dual-in-line package (n) and 8-pin so package (m8) top view see package number n08e and m08a pin names a0, a1, a2 device address input v ss ground sda data i/o scl clock input wp write protect v cc power supply ordering information nm 24 c xx u f lz e xx letter description package n 8-pin dip m8 8-pin soic temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current h 4.5v to 5.5v and v cc lockout scl clock frequency blank 100khz f 400khz ultralite cs100ul process density 65 64k with write protect c cmos interface 24 iic nm fairchild non-volatile memory a0 a1 a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm24c65u ds800012-2
3 www.fairchildsemi.com nm24c65u rev. b.1 nm24c65u 64k-bit serial eeprom with write protect 2-wire bus interface product specifications absolute maximum ratings ambient storage temperature 65 c to +150 c all input or output voltages with respect to ground 6.5v to 0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c65u 0 c to +70 c nm24c65ue -40 c to +85 c nm24c65uv -40 c to +125 c positive power supply nm24c65u/nm24c65uh 4.5v to 5.5v nm24c65ul 2.7v to 5.5v nm24c65ulz 2.7v to 5.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ (note 1) max i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd or v cc 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd v cc = 2.7v - 4.5v 1 10 a or v cc v cc = 2.7v - 4.5v 0.1 1 a v cc = 4.5v - 5.5v 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1 : typical values are for t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm24c65u rev. b.1 nm24c65u 64k-bit serial eeprom with write protect 2-wire bus interface ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf read and write cycle limits (standard and low v cc range - 2.7v-5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before 4.7 1.3 s a new transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 1.5 s t high clock high period 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 300 50 ns t wr write cycle time - nm24c65u 10 10 ms (note 3) - nm24c65ul, nm24c65ulz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c65u bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address
5 www.fairchildsemi.com nm24c65u rev. b.1 nm24c65u 64k-bit serial eeprom with write protect 2-wire bus interface background information (iic bus) as mentioned, the iic bus allows synchronous bidirectional commu- nication between transmitter/receiver using the scl (clock) and sda (data i/o) lines. all communication must be started with a valid start condition, concluded with a stop condition and acknowl- edged by the receiver with an acknowledge condition. in addition, since the iic bus is designed to support other devices such as ram, eprom, etc., the device type identifier string, or slave address, must follow the start condition. for eeproms, the first 4-bits of the slave address is '1010'. this is then followed by the device selection bits a2, a1 and a0.the final bit in the slave address determines the type of operation performed (read/ write). a "1" signifies a read while a "0" signifies a write. the slave address is then followed by two bytes that define the word address, which is then followed by the data byte. the eeproms on the iic bus may be configured in any manner required, providing the total memory addressed does not exceed 4m bits in the extended iic protocol. eeprom memory address- ing is controlled by hardware configuring the a2, a1, and a0 pins (device address pins) with pull-up or pull-down resistors. all unused pins must be grounded (tied to v ss ). addressing an eeprom memory location involves sending a command string with the following information: [device type]-[device address]-[page block ad- dress]-[byte address] definitions word 8 bits (byte) of data page 32 sequential addresses (one byte each) that may be programmed during a "page write" programming cycle. master any iic device controlling the transfer of data (such as a microcontroller). slave device being controlled (eeproms are always considered slaves). transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave). pin description serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a biderectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. device address inputs (a0, a1, a2) device address pins a0, a1, and a2 are connected to v cc or v ss to configure the eeprom address for multiple device configuration. a total of eight different devices can be attached to the same sda bus. write protection (wp ) if wp is tied to v cc , program write operations onto the upper half of the memory will not be executed. read operations are always available. if wp is tied to v ss , normal memory operation is enabled, read/ write over the entire bit memory array. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming writes. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. device operation the nm24c65uxxx supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving devices as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. there- fore, the nm24c65uxxx is considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high and reserved for indicating start and stop conditions. refer to figures 2 and 3. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24c65uxxx continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24c65uxxx to place the device in the standby power mode. scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto ds800012-3 bus timing
6 www.fairchildsemi.com nm24c65u rev. b.1 nm24c65u 64k-bit serial eeprom with write protect 2-wire bus interface write cycle timing acknowledge acknowledge is a hardware convention used to indicate success- ful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 4 . the nm24c65uxxx device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if write cycle timing (figure 1) sda scl stop condition start condition word n 8th bit ack t wr scl data stable data change sda sda scl start condition stop condition ds800012-4 ds800012-5 data validity (figure 2) definition of start and stop (figure 3) ds800012-6 both the device and a write operation have been selected, the nm24c65uxxx will respond with an acknowledge after the receipt of each subsequent eight bit word. in the read mode the nm24c65uxxx slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode. scl from master data output from transmitter data output from receiver 189 start acknowledge acknowledge response from receiver (figure 4) ds800012-7
7 www.fairchildsemi.com nm24c65u rev. b.1 nm24c65u 64k-bit serial eeprom with write protect 2-wire bus interface s t o p a c k bus activity: master sda line 1010 000 bus activity a c k data a c k a c k word address (1) word address (0) slave address s t a r t device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier. this is fixed as 1010 for all eeprom devices. the next three bits identifies the device address. address from 000 to 111 are acceptable thus allowing up to eight devices to be connected to the iic bus. the last bit of the slave address defines whether a write or read condition is requested by the master. a "1" indicates that a read operation is to be executed and a "0" initiates the write mode. a simple review: after the nm24c65uxxx recognizes the start condition, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions. write operations byte write for a write operation, two additional address bytes, with 13 active bits, are required after the slave acknowledge to address the full memory array. the first byte indicates the high-order byte of the word address. only the five least signicant bits can be changed, the other bits are pre-assigned the value "0". following the acknowledgement from the first word address, the next byte indicates the low-order byte of the word address. upon receipt of the word address, the nm24c65uxxx responds with another acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24c65uxxx begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress, the device's inputs are disabled and the device will not respond to any requests from the master. refer figure 5 for the byte write sequence. page write the nm24c65uxxx is capable of thirty-two byte page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data word is transfered, the master can transmit up to thirty-one more words. after the receipt of each word, the device responds with an acknowledge. after the receipt of each word, the internal address counter increments to the next address and the next sda data is ac- cepted. if the master should transmit more than thirty-two words prior to generating the stop condition, the address counter will "roll over" and the previous written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer figure 6 for the page write sequence. acknowledge polling once the stop condition is isssued to indicate the end of the host's write operation, the nm24c65uxxx initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24c65uxxx is still busy with the write opera- tion, no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. ds800012-8 byte write (figure 5)
8 www.fairchildsemi.com nm24c65u rev. b.1 nm24c65u 64k-bit serial eeprom with write protect 2-wire bus interface write protection programming of the upper half of memory will not take place if the wp pin is connected to v cc . the device will accept slave and word addresses; but if the memory accessed is write protected by the wp pin, the nm24c65uxxx will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. low v cc lockout nm24c65uxhx (h option) protects against data corruption during programming by preventing any programming operations if v cc drops below approximately 3.8v (v cc lockout trip level). this is accomplished by monitoring the "read/write" (r/w) bit in the slave address and if the r/w bit is "0," indicating a programming operation, the v cc lockout is activated. at that point, if the v cc drops below the trip level, programming is inhibited and the device does not issue an ack (the output stays high). to restate, the v cc lockout feature is active from the time a write bit is received up to the time that the master's stop condition is received (the stop condition turns on the v pp internal high voltage). once program- ming has begun, the programming cycle cannot be inter- rupted except by removal of v cc , which could result in data corruption. read operation read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to "1". there are three basic read operations: current address read, random read and sequential read. current address read internally the nm24c65uxxx contains an address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n+1. upon receipt of the slave address with r/w set to one, the nm24c65uxxx issues an acknowledge and transmits the eight bit word. the master will not acknowledge acknowledge the transfer but does generate a stop condition, and therefore discon- tinues transmission. refer figure 7 for the current address read sequence. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to "1", the master must first perform a "dummy" write operation. the master issues a start condition, slave address with the r/w bit set to "0" and then the word address it is to read from. after the word address acknowledge, the master immedi- ately reissues the start condition and the slave address with the r/w bit set to "1". this will be followed by an acknowledge from the nm24c65uxxx and then by the eight bit data. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24c65uxxx discontinues transmission. refer figure 8 for the random read sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24c65uxxx continues to output data for each acknowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n, followed by the data n+1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" and the nm24c65uxxx continues to output data for each acknowledge received. refer figure 9 for the sequential read sequence. s t o p a c k a c k bus activity: master sda line 1010 000 bus activity a c k data n data n+31 a c k word address (1) word address (0) slave address s t a r t ds800012-9 page write (figure 6)
9 www.fairchildsemi.com nm24c65u rev. b.1 nm24c65u 64k-bit serial eeprom with write protect 2-wire bus interface current address read (figure 7) random read (figure 8) sequential read (figure 9) s t o p a c k no a c k bus activity: master sda line 1010 bus activity a c k data n + x a c k data n + 1 data n slave address a c k s t a r t s t o p a c k no a c k bus activity: master sda line 1010 1 010 10 000 bus activity a c k a c k word address (1) word address (0) slave address slave address data n a c k s t a r t s t a r t s t o p a c k no a c k 10 10 data slave address s t a r t ds800012-10 ds800012-11 ds800012-12
10 www.fairchildsemi.com nm24c65u rev. b.1 nm24c65u 64k-bit serial eeprom with write protect 2-wire bus interface molded small out-line package (m8) order number nm24c65uxxxm8 or nm24c65uxxxem8 package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
11 www.fairchildsemi.com nm24c65u rev. b.1 nm24c65u 64k-bit serial eeprom with write protect 2-wire bus interface physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) order number nm24c65uxxxn or nm24c65uxxxen package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect preliminary march 1999 ? 1999 fairchild semiconductor corporation nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect general description the nm24wxx devices are 2048/4096/8192/16,384 bits, respec- tively, of cmos non-volatile electrically erasable memory. these devices conform to all specifications in the iic 2-wire protocol and are designed to minimize device pin count, and simplify pc board layout requirements. the entire ememory can be disabled (write protected) by con- necting the wp pin to v cc . the memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by fairchild's family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. fairchild eeproms are designed and tested for applications requiring high endurance, high reliability and low power consump- tion. block diagram ds500074-1 h.v. generation timing &control e 2 prom array 16 ydec 8 data register xdec control logic word address counter slave address register & comparator start stop logic start cycle 16/ 32/ 64/ 128/ 4 4 ck d in r/w load inc sda v ss v cc wp d out a2 a1 a0 device address bits 0/1/2/3 scl features n hardware write protect for entire memory n low power cmos 200 m a active current typical 10 m a standby current typical 1 m a standby typical (l) 0.1 m a standby typical (lz) n iic compatible interface provides bidirectional data transfer protocol n sixteen byte page write mode minimizes total write time per byte n self timed write cycle typical write cycle time of 6ms n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin dip, 8-pin so, and 8-pin tssop n available in three temperature ranges - commercial: 0 to +70 c - extended (e): -40 to +85c - automotive (v): -40 to +125 c
2 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect connection diagrams dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e (n), m08a (m8), and mtc08 (mt8) pin names a0,a1,a2 device address inputs v ss ground sda data i/o scl clock input wp write protect v cc power supply nc no connect ordering information nm 24 w xx lz e xx letter description package n 8-pin dip m8 8-pin so8 mt8 8-pin tssop temp. range none 0 to 70 c e -40 to +85 c v -40 c to +125 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current density 02 2k 04 4k 08 8k 16 16k w total array write protect interface 24 iic nm fairchild non-volatile memory a0 a1 a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 ds500074-3 nm24w02 nc a1 a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nc nc a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nc nc nc v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm24w04 nm24w08 nm24w16 ds500074-4 ds500074-18 ds500074-2
3 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect product specifications absolute maximum ratings ambient storage temperature C65 c to +150 c all input or output voltages with respect to ground 6.5v to C0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24wxx 0 c to +70 c nm24wxxe -40 c to +85 c nm24wxxv -40 c to +125 c positive power supply nm24wxx 4.5v to 5.5v nm24wxxl 2.7v to 4.5v nm24wxxlz 2.7v to 4.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 100 khz 0.2 1.0 ma i sb standby current v in = gnd or v cc 10 50 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 100 khz 0.2 1.0 ma i sb standby current for l v in = gnd or v cc 110 m a standby current for lz v in = gnd or v cc 0.1 1 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf read and write cycle limits (standard and low v cc range 2.7v - 4.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 m s t buf time the bus must be free before 4.7 1.3 m s a new transmission can start t hd:sta start condition hold time 4.0 0.6 m s t low clock low period 4.7 1.5 m s t high clock high period 4.0 0.6 m s t su:sta start condition setup time 4.7 0.6 m s (for a repeated start condition) t hd:dat data in hold time 0 0 ns t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 m s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 m s t dh data out hold time 300 50 ns t wr write cycle time - nm24wxx 10 10 ms (note 3) - nm24wxxl, nm24wxxlz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24wxx bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the device d oes not respond to its slave address.
5 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect bus timing background information (iic bus) as mentioned, the iic bus allows synchronous bidirectional com- munication between transmitter/receiver using the scl (clock) and sda (data i/o) lines. all communication must be started with a valid start condition, concluded with a stop condition and acknowledged by the receiver with an acknowledge condi- tion. in addition, since the iic bus is designed to support other devices such as ram, eproms, etc., a devce type identifier string must follow the start condition. for eeproms, this 4-bit string is 1010 and is the first 4 bits in the slave address. as shown below, the eeproms on the iic bus may be configured in any manner required, and for the standard iic protocol, the total memory addressed can not exceed 16k (16,384 bits). eeprom memory address programming is controlled by 2 methods: ? hardware configuring the a0, a1, and a2 pins (device address pins) with pull-up or pull-down to resistors. all unused pins must be grounded (tied to v ss ). ? software addressing the required page block within the device memory array (as sent in the slave address string). addressing an eeprom memory location involves sending a command string with the following information: [device type][device address][page block address][byte address] definitions word 8 bits of data page 16 sequential addresses (one byte each) that may be programmed during a 'page write' programming cycle page block 2,048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2,048 bits master any iic device controlling the transfer of data (such as a micropro- cessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) example of 16k of memory on 2-wire bus note: the sda pull-up resistor is required due to the open-drain/open collector output of iic bus devices. the scl pull-up resistor is recommended because of the normal scl line inactive 'high' state. it is recommended that the total line capacitance be less than 400pf. specific timing and addressing considerations are described in greater detail in the following sections. ds500074-5 ds500074-6 sda scl nm24w02 v cc v cc a0 a1 a2 v ss nm24w02 a0 a1 a2 v ss nm24w04 a0 a1 a2 v ss nm24w08 a0 a1 a2 v ss v cc to v cc or v ss to v cc or v ss to v cc or v ss to v cc or v ss v cc v cc v cc scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto
6 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect device address pins memory size number of a0 a1 a2 page blocks nm24w02 adr adr adr 2048 bits 1 nm24w04 nc adr adr 4096 bits 2 nm24w08 nc nc adr 8192 bits 4 nm24w16 nc nc nc 16,384 bits 8 adr is the hardware address (v cc /1 or v ss /0) of the device(s) used. pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wireCored with any number of open drain or open collector outputs. device operation inputs (a0, a1, a2) device address pins a0, a1, and a2 are connected to v cc or v ss to configure the eeprom chip address. table 1 shows the active pins across the nm24wxx device family. table 1. device a0 a1 a2 effects of addresses nm24w02 adr adr adr 2 3 = 8; 8*x(1x2k)**=16k nm24w04 x adr adr 2 2 = 4; 4*x(2x2k)**=16k nm24w08 x x adr 2 1 = 2; 2*x(4x2k)**=16k nm24w16 x x x 2 0 = 1; 1*x(8x2k)**=16k * max # of devices on bus ** number of page blocks per density wp write protection if tied to v cc , program operations onto memory will not be executed. (only read operations are possible.) if tied to v ss , normal operation is enabled (read/write over the entire memory is possible). device operation the nm24wxx supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm24wxx will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24wxx continuously monitors the sda and scl lines for the start condi- tion and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24wxx to place the device in the standby power mode. acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line to low to acknowledge that it received the eight bits of data. refer to figure 3. the nm24wxx device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm24wxx will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the nm24wxx slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode.
7 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect write cycle timing sda scl stop condition start condition word n 8th bit ack t wr ds500074-7 sda scl start condition stop condition sda scl data stable data change scl from master data output from transmitter data output from receiver 189 start acknowledge ds500074-8 ds500074-9 data validity (figure 1) start and stop definition (figure 2) acknowledge responses from receiver (figure 3) ds500074-10
8 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier ( see figure 4) . this is fixed as 1010 for all eeprom devices. slave addresses (figure 4) all standard iic protocol eeproms use an internal protocol that defines a page block size of 2k bits (for byte addresses 00 through ff). therefore, address bits a0, a1, or a2 (if designated 'p') are used to access a page block in conjuction with the byte address used to access any individual data byte. refer to the following table for slave address string details: device a0 a1 a2 page page block blks addresses nm24w02 a a a 1 (2k) (none) nm24w04 p a a 2 (4k) 0 1 nm24w08 p p a 4 (8k) 00 01 10 11 nm24w16 p p p 8 (16k) 000 001 010 011 100 101 110 111 note: a: refers to a hardware configured device address pin. p: refers to an internal page block memory segment the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the nm24wxx recognizes the start condi- tion, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions. device type identifier device address 1 0 1 0 a2 a1 a0 r/w (lsb) nm24w02 device type identifier device address page block address 1 0 1 0 a2 a1 a0 r/w (lsb) nm24w04 device type identifier device address page block address 1 0 1 0 a2 a1 a0 r/w (lsb) nm24w08 device type identifier page block address 1 0 1 0 a2 a1 a0 r/w (lsb) nm24w16 ds500074-11
9 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect write operations byte write for a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 words in the selected page of memory. upon receipt of the word address the nm24wxx responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24wxx begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the nm24wxx inputs are disabled, and the device will not respond to any requests from the master. refer to figure 5 for the address, acknowledge and data transfer sequence. page write the nm24wxx is capable of a sixteen byte page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to fifteen more words. after the receipt of each word, the nm24wxx will respond with an acknowledge. after the receipt of each word, the internal address counter increments to the next address and the next sda data is accepted. if the master should transmit more than sixteen words prior to generating the stop condition, the address counter will 'roll over' and the previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 6 for the address, acknowl- edge, and data transfer sequence. acknowledge polling once the stop condition is issued to indicate the end of the hosts write operation the nm24wxx initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24wxx is still busy with the write operation no ack will be returned. if the nm24wxx has completed the write operation an ack will be returned and the host can then proceed with the next read or write operation. write protection programming of the memory will not take place if the wp pin of the nm24wxx is connected to v cc . the nm24wxx will accept slave and word addresses; but if the memory accessed is write pro- tected by the wp pin, the nm24wxx will not generate an acknowl- edge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. s t o p bus activity: master bus activity: nm24wxx sda line data n + 15 data n + 1 data n byte address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master bus activity: nm24wxx sda line byte write (figure 5) page write (figure 6) ds500074-12 ds500074-13
10 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect ds500074-15 read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the nm24wxx contains an address counter that main- tains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the nm24wxx issues an acknowledge and transmits the eight bit word. the master will not acknowledge the transfer but does generate a stop condition, and therefore the nm24wxx discontin- ues transmission. refer to figure 7 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address, r/w bit set to zero, and then the word address it is to read. after the word address acknowledge, the master imme- diately reissues the start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the nm24wxx and then by the eight bit word. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24wxx discontinues transmission. refer to figure 8 for the address, acknowledge and data transfer se- quence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24wxx continues to output data for each acknowl- edge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter 'rolls over' and the nm24wxx continues to output data for each acknowledge re- ceived. refer to figure 9 for the address, acknowledge, and data transfer sequence. current address read (figure 7) s t o p a c k slave address a c k a c k s t a r t s t a r t byte address slave address bus activity: master sda line s data n s t o p a c k bus activity: master sda line a c k data n + x a c k data n + 2 data n +1 data n a c k slave address s t o p data a c k s t a r t slave address bus activity: master sda line random read (figure 8) sequential read (figure 9) ds500074-16 ds500074-14
11 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect ds500074-17 sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc read operations (continued) typical system configuration (figure 11) note: due to open drain configuration of sda, a bus-level resistor is called for (typical value = 4.7 w )
12 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect 8-pin molded small outline package (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
13 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect 8-pin molded tssop, jedec package number mtc08 physical dimensions inches (millimeters) unless otherwise noted 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
14 www.fairchildsemi.com nm24wxx rev. c.2 nm24wxx 2k/4k/8k/16k-bit standard 2-wire bus interface serial eeprom with full array write protect physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm25c020 rev. d.1 nm25c020 2k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) march 1999 ? 1999 fairchild semiconductor corporation nm25c020 2k-bit serial cmos eeprom (serial peripheral interface (spi) synchronous bus) general description the nm25c020 is a 2048-bit cmos eeprom with an spi compatible serial interface. the nm25c020 is designed for data storage in applications requiring both non-volatile memory and in- system data updates. this eeprom is well suited for applications using the 68hc11 series of microcontrollers that support the spi interface for high speed communication with peripheral devices via a serial bus to reduce pin count. the nm25c020 is imple- mented in fairchild semiconductors floating gate cmos process that provides superior endurance and data retention. the serial data transmission of this device requires four signal lines to control the device operation: chip select (cs), clock (sck), data in (si), and serial data out (so). all programming cycles are completely self-timed and do not require an erase before write. block write protection is provided by programming the sta- tus register with one of four levels of write protection. additionally, separate write enable and write disable instruc- tions are provided for data protection. hardware data protection is provided by the wp pin to protect against inadvertent programming. the hold pin allows the serial communication to be suspended without resetting the serial sequence. block diagram features n 2.1 mhz clock rate @ 2.7v to 5.5v n 2048 bits organized as 256 x 8 n multiple chips on the same 3-wire bus with separate chip select lines n self-timed programming cycle n simultaneous programming of 1 to 4 bytes at a time n status register can be polled during programming to monitor ready/busy n write protect (wp) pin and write disable instruction for both hardware and software write protection n block write protect feature to protect against accidental writes n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin dip, 8-pin so, or 8-pin tssop ds012400-1 instruction decoder control logic and clock generators high voltage generator and program timer instruction register program enable data in/out register 8 bits data out buffer non-volatile status register decoder 1 of 256 address counter/ register eeprom array 2048 bits (256 x 8) read/write amps cs hold sck v cc v ss v pp wp si so
2 www.fairchildsemi.com nm25c020 rev. d.1 nm25c020 2k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) connection diagram dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e (n), m08a (m8), and mtc08 (mt8) pin names cs chip select input so serial data output wp write protect v ss ground si serial data input sck serial clock input hold suspends serial data v cc power supply ordering information nm 25 c xx lz e xx letter description package n 8-pin dip m8 8-pin so mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current density/mode 020 2k, mode 0 c cmos technology interface 25 spi nm fairchild nonvolatile memory prefix cs so wp v ss v cc hold sck si 8 7 6 5 1 2 3 4 nm25c020 ds012400-2
3 www.fairchildsemi.com nm25c020 rev. d.1 nm25c020 2k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) standard voltage 4.5 v cc 5.5v specifications absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c020 0 c to +70 c nm25c020e -40 c to +85 c nm25c020v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v (unless otherwise specified) symbol parameter conditions min max units i cc operating current cs = v il 3ma i ccsb standby current cs = v cc 50 m a i il input leakage v in = 0 to v cc -1 +1 m a i ol output leakage v out = gnd to v cc -1 +1 m a v il cmos input low voltage -0.3 v cc * 0.3 v v ih cmos input high voltage 0.7 * v cc v cc + 0.3 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = -0.8 ma v cc - 0.8 v f op sck frequency 2.1 mhz t ri input rise time 2.0 m s t fi input fall time 2.0 m s t clh clock high time (note 2) 190 ns t cll clock low time (note 2) 190 ns t csh min cs high time (note 3) 240 ns t css cs setup time 240 ns t dis data setup time 100 ns t hds hold setup time 90 ns t csn cs hold time 240 ns t din data hold time 100 ns t hdn hold hold time 90 ns t pd output delay c l = 200 pf 240 ns t dh output hold time 0 ns t lz hold to output low z 100 ns t df output disable time c l = 200 pf 240 ns t hz hold to output high z 100 ns t wp write cycle time 1C4 bytes 10 ms capacitance t a = 25 c, f = 2.1/1 mhz (note 4) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load c l = 200 pf input pulse levels 0.1 * v cc C 0.9 * v cc timing measurement reference level 0.3 * v cc - .07 * v cc note 1: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, if the 2.1mhz period = 476ns and t clh = 190ns, t cll must be 286ns. note 3: cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 4: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm25c020 rev. d.1 nm25c020 2k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) low voltage 2.7v v cc 4.5v specifications absolute maximum ratings (note 5) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c020l/lz 0 c to +70 c nm25c020le/lze -40 c to +85 c nm25c020lv -40 c to +125 c power supply (v cc ) 2.7vC4.5v dc and ac electrical characteristics 2.7v v cc 4.5v (unless otherwise specified) 25c020l/le 25c020lv 25c020lz/lze symbol parameter part conditions min. max. min max units i cc operating current cs = v il 33ma i ccsb standby current l cs = v cc 10 10 m a lz 1 n/a m a i il input leakage v in = 0 to v cc -1 1 -1 1 m a i ol output leakage v out = gnd to v cc -1 1 -1 1 m a v il input low voltage -0.3 v cc * 0.3 -0.3 v cc * 0.3 v v ih input high voltage 0.7 * v cc v cc + 0.3 0.7 * v cc v cc + 0.3 v v ol output low voltage i ol = 0.8 ma 0.4 0.4 v v oh output high voltage i oh = C0.8 ma v cc - 0.8 v cc - 0.8 v f op sck frequency 1.0 1.0 mhz t ri input rise time 2.0 2.0 m s t fi input fall time 2.0 2.0 m s t clh clock high time (note 6) 410 410 ns t cll clock low time (note 6) 410 410 ns t csh min. cs high time (note 7) 500 500 ns t css cs setup time 500 500 ns t dis data setup time 100 100 ns t hds hold setup time 240 240 ns t csn cs hold time 500 500 ns t din data hold time 100 100 ns t hdn hold hold time 240 240 ns t pd output delay c l = 200 pf 500 500 ns t dh output hold time 0 0 ns t lz hold output low z 240 240 ns t df output disable time c l = 200 pf 500 500 ns t hz hold to output hi z 240 240 ns t wp write cycle time 1-4 bytes 15 15 ms capacitance t a = 25 c, f = 2.1/1 mhz (note 8) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load i ol = 10 m a, i oh = 10 m a input pulse levels 0.3v to 3.5v timing measurement reference level input 0.4v and 1.6v output 0.8v and 1.6v note 5: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 6: the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, if the 2.1mhz period = 476ns and t clh = 190ns, t cll must be 286ns. note 7: cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 8: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm25c020 rev. d.1 nm25c020 2k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) ac test conditions (continued) figure 1. synchronous data timing diagram figure 3. spi serial interface cs sck si so v ih v il v ih v il v ih v il v oh v ol t css t csh t csn t dis t pd t dh t df t din t clh t cll si so sck cs data out (mosi) data in (miso) serial clock (clk) ss0 ss1 ss2 ss3 si so sck cs si so sck cs si so sck cs spi chip selection master mcu nm25c020 ds012400-3 ds012400-4 sck hold so t hz t hdn t hds t hdn t hds t lz ds012400-6 figure 2. hold timing
6 www.fairchildsemi.com nm25c020 rev. d.1 nm25c020 2k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description table 1. instruction set instruction instruction operation name opcode wren 00000110 set write enable latch wrdi 00000100 reset write enable latch rdsr 00000101 read status register wrsr 00000001 write status register read 00000011 read data from memory array write 00000010 write data to memory array master : the device that generates the serial clock is desig- nated as the master. the nm25c020 can never function as a master. slave : the nm25c020 always operates as a slave as the serial clock pin is always an input. transmitter/receiver : the nm25c020 has separate pins for data transmission (so) and reception (si). msb : the most significant bit is the first bit transmitted and received. chip select : the chip is selected when pin cs is low. when the chip is not selected, data will not be accepted from pin si, and the output pin so is in high impedance. serial op-code : the first byte transmitted after the chip is selected with cs going low contains the op-code that defines the operation to be performed. protocol : when connected to the spi port of a 68hc11 microcontroller, the nm25c020 accepts a clock phase of 0 and a clock polarity of 0. the spi protocol for this device defines the byte transmitted on the si and so data lines for proper chip operation. see figure 4. cs si so invalid code ds012400-7 cs sck si so bit 7 bit 6 bit 0 bit 1 bit 7 bit 0 ds012400-5 figure 4. spi protocol data is clocked in on the positive sck edge and out on the negative sck edge. hold : the hold pin is used in conjunction with the cs to select the device. once the device is selected and a serial sequence is underway, hold may be forced low to suspend further serial communication with the device without resetting the serial se- quence. note that hold must be brought low while the sck pin is low. the device must remain selected during this sequence. to resume serial communication hold is brought high while the sck pin is low. the so pin is at a high impedance state during hold. invalid op-code : after an invalid code is received, no data is shifted into the nm25c020, and the so data output pin remains high impedance until a new cs falling edge reinitializes the serial communication. see figure 5. figure 5. invalid op-code
7 www.fairchildsemi.com nm25c020 rev. d.1 nm25c020 2k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description (continued) read sequence: reading the memory via the serial spi link requires the following sequence. the cs line is pulled low to select the device. the read op-code is transmitted on the si line followed by the byte address (a7Ca0) to be read. after this is done, data on the si line becomes dont care. the data (d7Cd0) at the address specified is then shifted out on the so line. if only one byte is to be read, the cs line can be pulled back to the high level. it is possible to continue the read sequence as the byte adress is automatically incremented and data will continue to be shifted out as clock pulses are continuously applied. when the highest address is reached (ff), the address counter rolls over to lowest address (000) allowing the entire memory to be read in one continuous read cycle. see figure 6. level status register bits array address bp1 bp0 protected 0 0 0 none 1 0 1 c0-ff 2 1 0 80-ff 3 1 1 00-ff write enable (wren) : when v cc is applied to the chip, it powers up in the write disable state. therefore, all programming modes must be preceded by a write enable (wren) instruc- tion. at the completion of a write or wrsr cycle the device is automatically returned to the write disable state. note that a write disable (wrdi) instruction will also return the device to the write disable state. see figure 8. figure 8. write enable cs si so wren op-code ds012400-10 write disable (wrdi) : to protect against accidental data disturbance the write disable (wrdi) instruction disables all programming modes. see figure 9. figure 9. write disable cs si so wrdi op-code ds012400-11 table 3. block write protection levels figure 6. read sequence figure 7. read status cs si so read op-code byte addr. data n data n+1 data n+2 data n+3 cs si so rdsr op-code sr data msb?sb ds012400-8 ds012400-9 read status register (rdsr) : the read status register (rdsr) instruction provides access to the status register and is used to interrogate the ready/busy and write enable status of the chip. (two non-volatile status register bits are used to select one of four levels of block write protection.) the status register format is shown in table 2. table 2. status register format bit bit bit bit bit bit bit bit 76543210 x x x x bp1 bp0 wen rdy x = don't care status register bit 0 = 0 (rdy) indicates that the device is ready; bit 0 = 1 indicates that a program cycle is in progress. bit 1 = 0 (wen) indicates that the device is not write enabled; bit 1 = 1 indicates that the device is write enabled. non-volatile status register bits 2 and 3 (bp0 and bp1) indicate the level of block write protection selected. the block write protec- tion levels and corresponding status register control bits are shown in table 3. note that if a rdsr instruction is executed during a programming cycle only the rdy bit is valid. all other bits are 1s. see figure 7. write sequence : to program the device, the write pro- tect (wp) pin must be held high and two separate instructions must be executed. the chip must first be write enabled via the write enable instruction and then a write instruction must be executed. moreover, the address of the memory location(s) to be programmed must be outside the protected address field selected by the block write protection level. see table 3. a write command requires the following sequence. the cs line is pulled low to select the device, then the write op-code is transmitted on the si line followed by the byte address(a7Ca0) and the corresponding data (d7-d0) to be written. programming will start after the cs pin is forced back to a high level. note that the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 data bit. see figure 10.
8 www.fairchildsemi.com nm25c020 rev. d.1 nm25c020 2k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description (continued) sck si so cs d0 d1 d2 cs si so write op-code byte addr (n) data (n) data (n + 1) data (n + 2) data (n + 3) ds012400-12 ds012400-13 figure 11. 4 byte page write figure 10. write sequence the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the write cycle is still in progress and bit 0 = 0 indicates that the write cycle has ended. during the write programming cycle (bit 0 = 1) only the read status regis- ter instruction is enabled. the nm25c020 is capable of a 4 byte page write operation. after receipt of each byte of data the two low order address bits are internally incremented by one. the seven high order bits of the address will remain constant. if the master should transmit more than 4 bytes of data, the address counter will roll over, and the previously loaded data will be reloaded. see figure 11. at the completion of a write cycle the device is automati- cally returned to the write disable state. if the device is not write enabled, the device will ignore the write instruction and return to the standby state when cs is forced high. a new cs falling edge is required to re-initialize the serial communication. write status register (wrsr): the write status register (wrsr) instruction is used to program the non- volatile status register bits 2 and 3 (bp0 and bp1). the write protect (wp) pin must be held high and two separate instruc- tions must be executed. the chip must first be write enabled via the write enable instruction and then a wrsr instruction must be executed. cs si so wrsr op-code sr data xxxxbp1bp0xx ds012400-14 figure 12. write status register bp0 sck si so cs ds012400-15 figure 13. start wrsr condition the wrsr command requires the following sequence. the cs line is pulled low to select the device and then the wrsr op-code is transmitted on the si line followed by the data to be pro- grammed. see figure 12. note that the first four bits are dont care bits followed by bp1 and bp0 then two additional dont care bits. programming will start after the cs pin is forced back to a high level. as in the write instruction the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the last dont care bit. see figure 13. the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the wrsr cycle is still in progress and bit 0 = 0 indicates that the wrsr cycle has ended. at the completion of a write cycle the device is automatically returned to the write disable state.
9 www.fairchildsemi.com nm25c020 rev. d.1 nm25c020 2k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) molded small out-line package (m8) package number m08a molded dual-in-line package (n) package number n08e physical dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
10 www.fairchildsemi.com nm25c020 rev. d.1 nm25c020 2k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) 8-pin molded tssop, jedec (mt8) package number mtc08 physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
1 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) nm25c040 4k-bit serial cmos eeprom (serial peripheral interface (spi) synchronous bus) general description the nm25c040 is a 4096-bit cmos eeprom with an spi compatible serial interface. the nm25c040 is designed for data storage in applications requiring both non-volatile memory and in- system data updates. this eeprom is well suited for applications using the 68hc11 series of microcontrollers that support the spi interface for high speed communication with peripheral devices via a serial bus to reduce pin count. the nm25c040 is imple- mented in fairchild semiconductors floating gate cmos process that provides superior endurance and data retention. the serial data transmission of this device requires four signal lines to control the device operation: chip select (cs), clock (sck), data in (si), and serial data out (so). all programming cycles are completely self-timed and do not require an erase before write. block write protection is provided by programming the sta- tus register with one of four levels of write protection. additionally, separate write enable and write disable instruc- tions are provided for data protection. hardware data protection is provided by the wp pin to protect against inadvertent programming. the hold pin allows the serial communication to be suspended without resetting the serial sequence. block diagram march 1999 features n 2.1 mhz clock rate @ 2.7v to 5.5v n 4096 bits organized as 512 x 8 n multiple chips on the same 3-wire bus with separate chip select lines n self-timed programming cycle n simultaneous programming of 1 to 4 bytes at a time n status register can be polled during programming to monitor ready/busy n write protect (wp) pin and write disable instruction for both hardware and software write protection n block write protect feature to protect against accidental writes n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin dip, 8-pin so, or 8-pin tssop ds012401-1 ? 1999 fairchild semiconductor corporation instruction decoder control logic and clock generators high voltage generator and program timer instruction register program enable data in/out register 8 bits data out buffer non-volatile status register decoder 1 of 512 address counter/ register eeprom array 4096 bits (512 x 8) read/write amps cs hold sck v cc v ss v pp wp si so
2 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) connection diagram dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e (n), m08a (m8), and mtc08 (mt8) pin names cs chip select input so serial data output wp write protect v ss ground si serial data input sck serial clock input hold suspends serial data v cc power supply ordering information nm 25 c xx lz e xx letter description package n 8-pin dip m8 8-pin so mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current density/mode 040 4k, mode 0 c cmos technology w total array write protect interface 25 spi nm fairchild nonvolatile memory prefix cs so wp v ss v cc hold sck si 8 7 6 5 1 2 3 4 nm25c040 ds012401-2
3 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) standard voltage 4.5 v cc 5.5v specifications absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c040 0 c to +70 c nm25c040e -40 c to +85 c nm25c040v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v (unless otherwise specified) symbol parameter conditions min max units i cc operating current cs = v il 3ma i ccsb standby current cs = v cc 50 m a i il input leakage v in = 0 to v cc -1 +1 m a i ol output leakage v out = gnd to v cc -1 +1 m a v il cmos input low voltage -0.3 v cc * 0.3 v v ih cmos input high voltage 0.7 * v cc v cc + 0.3 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = -0.8 ma v cc - 0.8 v f op sck frequency 2.1 mhz t ri input rise time 2.0 m s t fi input fall time 2.0 m s t clh clock high time (note 2) 190 ns t cll clock low time (note 2) 190 ns t csh min cs high time (note 3) 240 ns t css cs setup time 240 ns t dis data setup time 100 ns t hds hold setup time 90 ns t csn cs hold time 240 ns t din data hold time 100 ns t hdn hold hold time 90 ns t pd output delay c l = 200 pf 240 ns t dh output hold time 0 ns t lz hold to output low z 100 ns t df output disable time c l = 200 pf 240 ns t hz hold to output high z 100 ns t wp write cycle time 1C4 bytes 10 ms capacitance t a = 25 c, f = 2.1/1 mhz (note 4) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load c l = 200 pf input pulse levels 0.1 * v cc C 0.9 * v cc timing measurement reference level 0.3 * v cc - .07 * v cc note 1: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, if the 2.1mhz period = 476ns and t clh = 190ns, t cll must be 286ns. note 3: cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 4: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) low voltage 2.7v v cc 4.5v specifications absolute maximum ratings (note 5) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c040l/lz 0 c to +70 c nm25c040le/lze -40 c to +85 c nm25c040lv -40 c to +125 c power supply (v cc ) 2.7vC4.5v dc and ac electrical characteristics 2.7v v cc 4.5v (unless otherwise specified) 25c040l/le 25c040lv 25c040lz/ze symbol parameter part conditions min. max. min max units i cc operating current cs = v il 33ma i ccsb standby current l cs = v cc 10 10 m a lz 1 n/a m a i il input leakage v in = 0 to v cc -1 1 -1 1 m a i ol output leakage v out = gnd to v cc -1 1 -1 1 m a v il input low voltage -0.3 v cc * 0.3 -0.3 v cc * 0.3 v v ih input high voltage v cc * 0.7 v cc + 0.3 v cc * 0.7 v cc + 0.3 v v ol output low voltage i ol = 0.8 ma 0.4 0.4 v v oh output high voltage i oh = C0.8 ma v cc - 0.8 v cc - 0.8 v f op sck frequency 1.0 1.0 mhz t ri input rise time 2.0 2.0 m s t fi input fall time 2.0 2.0 m s t clh clock high time (note 6) 410 410 ns t cll clock low time (note 6) 410 410 ns t csh min. cs high time (note 7) 500 500 ns t css cs setup time 500 500 ns t dis data setup time 100 100 ns t hds hold setup time 240 240 ns t csn cs hold time 500 500 ns t din data hold time 100 100 ns t hdn hold hold time 240 240 ns t pd output delay c l = 200 pf 500 500 ns t dh output hold time 0 0 ns t lz hold output low z 240 240 ns t df output disable time c l = 200 pf 500 500 ns t hz hold to output hi z 240 240 ns t wp write cycle time 1-4 bytes 15 15 ms capacitance t a = 25 c, f = 2.1/1 mhz (note 8) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load c l = 200pf input pulse levels 0.1 * v cc - 0.9 * v cc timing measurement reference level 0.3 * v cc - 0.7 * v cc note 5: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposur e to absolute maximum rating conditions for extended periods may affect device reliability. note 6: the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, if the 2.1mhz period = 476ns and t clh = 190ns, t cll must be 286ns. note 7: cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 8: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) ac test conditions (continued) figure 1. synchronous data timing diagram si so sck cs data out (mosi) data in (miso) serial clock (clk) ss0 ss1 ss2 ss3 si so sck cs si so sck cs si so sck cs spi chip selection master mcu nm25c040 ds012401-3 ds012401-4 figure 3. spi serial interface cs sck si so v ih v il v ih v il v ih v il v oh v ol t css t csh t csn t dis t pd t dh t df t din t clh t cll sck hold so t hz t hdn t hds t hdn t hds t lz figure 2. hold timing ds012401-6
6 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description table 1. instruction set instruction instruction operation name opcode wren 00000110 set write enable latch wrdi 00000100 reset write enable latch rdsr 00000101 read status register wrsr 00000001 write status register read 0000a011 read data from memory array write 0000a010 write data to memory array note: as the nm25c040 requires 9 address bits (4,096 ? 8 = 512 bytes = 2 9 ), the 9th bit (for r/w instructions) is inputted in the instruction set byte in bit i 3 . this convention only applies to 4k spi protocol. master : the device that generates the serial clock is desig- nated as the master. the nm25c040 can never function as a master. slave : the nm25c040 always operates as a slave as the serial clock pin is always an input. transmitter/receiver : the nm25c040 has separate pins for data transmission (so) and reception (si). msb : the most significant bit is the first bit transmitted and received. chip select : the chip is selected when pin cs is low. when the chip is not selected, data will not be accepted from pin si, and the output pin so is in high impedance. serial op-code : the first byte transmitted after the chip is selected with cs going low contains the op-code that defines the operation to be performed. protocol : when connected to the spi port of a 68hc11 microcontroller, the nm25c040 accepts a clock phase of 0 and a clock polarity of 0. the spi protocol for this device defines the byte transmitted on the si and so data lines for proper chip operation. see figure 4. hold : the hold pin is used in conjunction with the cs to select the device. once the device is selected and a serial sequence is underway, hold may be forced low to suspend further serial communication with the device without resetting the serial se- quence. note that hold must be brought low while the sck pin is low. the device must remain selected during this sequence. to resume serial communication hold is brought high while the sck pin is low. the so pin is at a high impedance state during hold. invalid op-code : after an invalid code is received, no data is shifted into the nm25c040, and the so data output pin remains high impedance until a new cs falling edge reinitializes the serial communication. see figure 5. figure 5. invalid op-code cs si so invalid code ds012401-7 cs sck si so bit 7 bit 6 bit 0 bit 1 bit 7 bit 0 ds012401-5 figure 4. spi protocol data is clocked in on the positive sck edge and out on the negative sck edge.
7 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description (continued) read sequence: reading the memory via the serial spi link requires the following sequence. the cs line is pulled low to select the device. the read op-code (which includes a8) is transmitted on the si line followed by the byte address (a7Ca0) to be read. after this is done, data on the si line becomes dont care. the data (d7Cd0) at the address specified is then shifted out on the so line. if only one byte is to be read, the cs line can be pulled back to the high level. it is possible to continue the read sequence as the byte adress is automatically incremented and data will continue to be shifted out. when the highest address is reached (1ff), the address counter rolls over to lowest address (000) allowing the entire memory to be read in one continuous read cycle. see figure 6. level status register bits array address bp1 bp0 protected 0 0 0 none 1 0 1 180-1ff 2 1 0 100-1ff 3 1 1 000-1ff write enable (wren) : when v cc is applied to the chip, it powers up in the write disable state. therefore, all programming modes must be preceded by a write enable (wren) instruc- tion. at the completion of a write or wrsr cycle the device is automatically returned to the write disable state. note that a write disable (wrdi) instruction will also return the device to the write disable state. see figure 8. figure 8. write enable cs si so wren op-code ds012401-10 write disable (wrdi) : to protect against accidental data disturbance the write disable (wrdi) instruction disables all programming modes. see figure 9. figure 9. write disable cs si so wrdi op-code ds012401-11 table 3. block write protection levels figure 6. read sequence figure 7. read status cs si so read op-code byte addr. data n data n+1 data n+2 data n+3 cs si so rdsr op-code sr data msblsb ds012401-8 ds012401-9 read status register (rdsr) : the read status register (rdsr) instruction provides access to the status register is used to interrogate the ready/busy and write enable status of the chip. two non-volatile status register bits are used to select one of four levels of block write protection. the status register format is shown in table 2. table 2. status register format bit bit bit bit bit bit bit bit 76543210 x x x x bp1 bp0 wen rdy x = don't care. status register bit 0 = 0 (rdy) indicates that the device is ready; bit 0 = 1 indicates that a program cycle is in progress. bit 1 = 0 (wen) indicates that the device is not write enabled; bit 1 = 1 indicates that the device is write enabled. non-volatile status register bits 2 and 3 (bp0 and bp1) indicate the level of block write protection selected. the block write protec- tion levels and corresponding status register control bits are shown in table 3. note that if a rdsr instruction is executed during a programming cycle only the rdy bit is valid. all other bits are 1s. see figure 7. write sequence : to program the device, the write pro- tect (wp) pin must be held high and two separate instructions must be executed. the chip must first be write enabled via the write enable instruction and then a write instruction must be executed. moreover, the address of the memory location(s) to be programmed must be outside the protected address field selected by the block write protection level. see table 3. a write command requires the following sequence. the cs line is pulled low to select the device, then the write op-code (which includes a8) is transmitted on the si line followed by the high order address byte (a10-a8) and the byte address(a7Ca0) and the corresponding data (d7-d0) to be written. programming will start after the cs pin is forced back to a high level. note that the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 data bit. see figure 10.
8 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) sck si so cs d0 d1 d2 ds012401-12 functional description (continued) figure 10. write sequence the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the write cycle is still in progress and bit 0 = 0 indicates that the write cycle has ended. during the write programming cycle (bit 0 = 1) only the read status regis- ter instruction is enabled. the nm25c040 is capable of a 4 byte page write operation. after receipt of each byte of data the two low order address bits are internally incremented by one. the seven high order bits of the address will remain constant. if the master should transmit more than 4 bytes of data, the address counter will roll over, and the previously loaded data will be reloaded. see figure 11. the wrsr command requires the following sequence. the cs line is pulled low to select the device and then the wrsr op-code is transmitted on the si line followed by the data to be pro- grammed. see figure 12. cs si so write op-code byte addr (n) data (n) data (n + 1) data (n + 2) data (n + 3) cs si so wrsr op-code sr data xxxxbp1bp0xx ds012401-13 ds012401-14 figure 11. 4 byte page write figure 12. write status register bp0 sck si so cs ds012401-15 figure 13. start wrsr condition at the completion of a write cycle the device is automatically returned to the write disable state. if the device is not write enabled, the device will ignore the write instruction and return to the standby state when cs is forced high. a new cs falling edge is required to re-initialize the serial communication. write status register (wrsr): the write status register (wrsr) instruction is used to program the non- volatile status register bits 2 and 3 (bp0 and bp1). the write protect (wp) pin must be held high and two separate instruc- tions must be executed. the chip must first be write enabled via the write enable instruction and then a wrsr instruction must be executed. note that the first four bits are dont care bits followed by bp1 and bp0 then two additional dont care bits. programming will start after the cs pin is forced back to a high level. as in the write instruction the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the last dont care bit. see figure 13. the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the wrsr cycle is still in progress and bit 0 = 0 indicates that the wrsr cycle has ended. at the completion of a write cycle the device is automatically returned to the write disable state.
9 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) molded small out-line package (m8) package number m08a molded dual-in-line package (n) package number n08e 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ. physical dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident
10 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) 8-pin molded tssop, jedec (mt8) package number mtc08 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.50) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. max 0.0433 (1.1) 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 [0.50 - 0.70] 0.0075 - 0.0098 [0.19 - 0.25] seating plane gage plane see detail a land pattern recommendation detail a typ. scale: 40x physical dimensions inches (millimeters) unless otherwise noted note: metal mask option for 16-byte page size. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm25c041 rev. d.1 nm25c041 4k-bit serial interface cmos eeprom (serial peripheral interface (spi) synchronous bus) march 1999 ? 1999 fairchild semiconductor corporation nm25c041 4k-bit serial interface cmos eeprom (serial peripheral interface (spi?) synchronous bus) general description the nm25c041 is a 4096-bit mode 1 spi (serial peripheral interface) cmos eeprom which is designed for high-reliability non-volatile data storage applications. the spi interface features a byte-wide format (all data is transferred in 8-bit words) to interface with the motorola 68hc11 microprocessor, or equivalent, at a 2.1mhz clock transfer rate. (this interface is considered the fastest serial communication method.) this 4-wire spi interface allows the end user full eeprom functionality while keeping pin count and space requirements low for maximum pc board space utilization. the spi interface requires four i/o pins on each eeprom device: chip select (cs), clock (sck), serial data in (si), and serial data out (so), as well as 2 other control pins: write protect (wp) and hold (hold). the write protect pin can be used to disable the write operation and the hold pin is used to interrupt the si datastream and place the device in a hold state during micropro- cessor instruction generation. please refer to the following dia- grams and description for more details. all programming cycles are completely self-timed and do not require an erase, or similar setup, before programming any cells. programming can be performed in 3 modes, address (byte) write, page (4 addresses/bytes) write or partial page write. furthermore, the eeprom is provided with 4 levels of write protection wherein the data, once programmed, cannot be altered. this is controlled block diagram by the status register and is described in greater detail within this datasheet. in order to prevent spurious programming, the eeprom has both a write enable command, which is immediately disabled after each programming operation, and a write protect (wp) pin, which must be pulled high to program. features n 2.1 mhz clock rate @ 2.7v to 5.5v n 4096 bits organized as 512 x 8 n multiple chips on the same 3 wire bus with separate chip select lines n self-timed programming cycle n simultaneous programming of 1 to 4 bytes at a time n status register can be polled during programming to monitor rdy/busy n both the write protect (wp) pin and 'auto-write disable after programming' provides hardware and software write protection n block write protect feature to protect against accidental writes n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin dip and 8-pin so ds800002-1 spi? is a trademark of motorola corporation. instruction decoder control logic and clock generators high voltage generator and program timer instruction register program enable data in/out register 8 bits data out buffer non-volatile status register decoder 1 of 512 address counter/ register eeprom array 4096 bits (512 x 8) read/write amps cs hold sck v cc v ss v pp wp si so
2 www.fairchildsemi.com nm25c041 rev. d.1 nm25c041 4k-bit serial interface cmos eeprom (serial peripheral interface (spi) synchronous bus) connection diagram dual-in-line package (n) and so package (m8) top view pin names cs chip select input so serial data output wp write protect v ss ground si serial data input sck serial clock input hold suspends serial data v cc power supply ordering information nm 25 c xx lz e xx letter description package n 8-pin dip m8 8-pin so temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current density/mode 041 4k, mode 1 c cmos interface 25 spi nm fairchild non-volatile memory cs so wp v ss v cc hold sck si 8 7 6 5 1 2 3 4 ds800002-2
3 www.fairchildsemi.com nm25c041 rev. d.1 nm25c041 4k-bit serial interface cmos eeprom (serial peripheral interface (spi) synchronous bus) absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c041 0 c to +70 c nm25c041e -40 c to +85 c nm25c041v -40 c to +125 c power supply (v cc ) nm25c041 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v symbol parameter conditions min max units i cc operating current cs = v il 3ma i ccsb standby current cs = v cc 50 m a i il input leakage v in = 0 to v cc -1 1 m a i ol output leakage v out = gnd to v cc -1 1 m a v il input low voltage -0.3 v cc * 0.3 v v ih input high voltage 0.7 * v cc v cc + 0.3 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = -0.8 ma v cc - 0.8 v f op sck frequency 2.1 mhz t ri input rise time 2.0 m s t fi input fall time 2.0 m s t clh clock high time (note 2) 190 ns t cll clock low time (note 2) 190 ns t csh min cs high time (note 3) 240 ns t css cs setup time 240 ns t dis data setup time 100 ns t hds hold setup time 90 ns t csn cs hold time 240 ns t din data hold time 100 ns t hdn hold hold time 90 ns t pd output delay c l = 200 pf 240 ns t dh output hold time 0 ns t lz hold to output low z 100 ns t df output disable time c l = 200 pf 240 ns t hz hold to output high z 100 ns t wp write cycle time 1C4 bytes 10 ms capacitance (note 4) t a = 25 c, f = 2.1/1 mhz symbol test typ max units c out output capacitance 38pf c in input capacitance 2 6 pf ac test conditions output load c l = 200 pf input pulse levels 0.1 * v cc - 0.9 * v cc timing measurement reference level 0.3 * v cc - 0.7 * v cc note 1: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, if the 2.1mhz period = 476ns and t clh = 190ns, t cll must be 286ns. note 3: cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 4: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm25c041 rev. d.1 nm25c041 4k-bit serial interface cmos eeprom (serial peripheral interface (spi) synchronous bus) low voltage 2.7v v cc 4.5v specifications absolute maximum ratings (note 5) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c041l/lz 0 c to +70 c nm25c041le/lze -40 c to +85 c nm25c041lv -40 c to +125 c power supply (v cc ) 2.7v - 4.5v dc and ac electrical characteristics 2.7v v cc 4.5v 25c041l/le 25c041lv 25c041lz/lze symbol parameter conditions min. max. min max units i cc operating current cs = v il 33ma i ccsb standby current cs = v cc m a l 10 10 lz 1 n/a i il input leakage v in = 0 to v cc -1 1 -1 1 m a i ol output leakage v out = gnd to v cc -1 1 -1 1 m a v il input low voltage -0.3 v cc * 0.3 -0.3 v cc * 0.3 v v ih input high voltage 0.7 * v cc v cc + 0.3 0.7 * v cc v cc + 0.3 v v ol output low voltage i ol = 0.8 ma 0.4 0.4 v v oh output high voltage i oh = C0.8 ma v cc - 0.8 v cc - 0.8 v f op sck frequency 1.0 1.0 mhz t ri input rise time 2.0 2.0 m s t fi input fall time 2.0 2.0 m s t clh clock high time (note 6) 410 410 ns t cll clock low time (note 6) 410 410 ns t csh min. cs high time (note 7) 500 500 ns t css cs setup time 500 500 ns t dis data setup time 100 100 ns t hds hold setup time 240 240 ns t csn cs hold time 500 500 ns t din data hold time 100 100 ns t hdn hold hold time 240 240 ns t pd output delay 500 500 ns t dh output hold time 0 0 ns t lz hold output low z 240 240 ns t df output disable time 500 500 ns t hz hold to output hi z 240 240 ns t wp write cycle time 1-4 bytes 15 15 ms capacitance t a = 25 c, f = 2.1/1 mhz (note 8) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load c l = 200 pf input pulse levels 0.1 * v cc - 0.9 * v cc timing measurement reference level 0.3 * v cc - 0.7 * v cc note 5: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 6 : the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, if the 2.1mhz period = 476ns and t clh = 190ns, t cll must be 286ns. note 7: cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 8: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm25c041 rev. d.1 nm25c041 4k-bit serial interface cmos eeprom (serial peripheral interface (spi) synchronous bus) ac test conditions (continued) figure 1. synchronous data timing cs sck si so hi-z hi-z v ih v il v ih v il v ih v il v oh v ol t css t csh t csn t dis t din t df t pd t pd t clh t cll hold sck so t hz t lz t hdn t hds t hdn t hds ds800002-4 ds800002-6 figure 2. hold timing
6 www.fairchildsemi.com nm25c041 rev. d.1 nm25c041 4k-bit serial interface cmos eeprom (serial peripheral interface (spi) synchronous bus) functional description table 1. op codes table instruction instruction operation name opcode wren 0000 0110 set write enable latch wrdi 0000 0100 reset write enable latch rdsr 0000 0101 read status register wrsr 0000 0001 write status register read 0000 a011 read data from memory array write 0000 a010 write data to memory array note: as the nm25c040 requires 9 address bits (4,096 ? 8 = 512 bytes = 2 9 ), the 9th bit (for r/w instructions) is inputted in the instruction set byte in bit i 3 . this convention only applies to 4k spi protocol. the nm25c041 spi device uses a cs functionality, so the device is selected when cs is low (cs is to be held high during 'standby' periods and between instruction sets). as stated above, the spi protocol defines this as a mode 1 part, with a clock phase 1 and clock polarity 0. this means that the part is active with cs = 0 (v il ), all input data is latched into the device on the rising edge of sck and all output data is clocked out on the falling edge of sck. figure 3. spi protocol cs sck si so bit 7 bit 6 bit 6 bit 0 bit 1 bit 7 bit 0 bit 1 the hold pin operation is used when the device is selected (cs low) and the application requires that the si datastream be stopped and then restarted. the hold pin allows a fully 'static' operation, wherin the device may be put on hold by bringing the hold pin low (v il ). during the hold state, sck must be high and cs must remain low (device selected). in order to resume eeprom serial communication, hold must be again brought high and the sck/si signals resumed. during the hold state, so is tri-stated (high impedance). ds800002-5 as an additional protection against data corruption, the device is designed so that, if an invalid opcode is received, the device will not shift any further data into the si latches and so will remain tri- stated. in this case, cs must again be brought high to re-initialize the device and a new opcode re-entered. see figure 4. figure 4. invalid op-code cs si so invalid op-code ds800002-7 cs si so read op-code byte addr (n) data (n) data (n+1) data (n+2) data (n+3) ds800002-8 read status register (rdsr): the read status register (rdsr) instruction provides access to the status register which is used to interrogate the ready/busy and write enable status of the chip. two non-volatile status register bits are used to select one of four levels of block write protection. the status register format is shown in table 2. read sequence: reading the memory via the spi link re- quires the following sequence. the cs line is pulled low to select the device. the read op-code (which includes a8) is transmitted on the si line followed by the byte address (a7Ca0) to be read. after this is done, data on the si line becomes dont care. the data (d7Cd0) at the address specified is then shifted out on the so line. if only one byte is to be read, the cs line can be pulled back to the high level. it is possible to continue the read sequence as the byte address is automatically incremented and data will continue to be shifted out. when the highest address is reached (1ff), the address counter rolls over to lowest address (000) allowing the entire memory to be read in one continuous read cycle. see figure 5. figure 5. read sequence
7 www.fairchildsemi.com nm25c041 rev. d.1 nm25c041 4k-bit serial interface cmos eeprom (serial peripheral interface (spi) synchronous bus) functional description (continued) table 2. status register format bit bit bit bit bit bit bit bit 76543210 x x x x bp1 bp0 wen rdy x = don't care status register bit 0 = 0 (rdy) indicates that the device is ready; bit 0 = 1 indicates that a program cycle is in progress. bit 1 = 0 (wen) indicates that the device is not write enabled; bit 1 = 1 indicates that the device is write enabled. non-volatile status register bits 2 and 3 (bp0 and bp1) indicate the level of block write protection selected. the block write protec- tion levels and corresponding status register control bits are shown in table 3. note that if a rdsr instruction is executed during a programming cycle only the rdy bit is valid. all other bits are 1s. see figure 6. table 3. block write protection levels level status register bits array address bp1 bp0 protected 0 0 0 none 1 0 1 180C1ff 2 1 0 100C1ff 3 1 1 000C1ff figure 6. read status write enable (wren): when v cc is applied to the chip, it powers up in the write disable state. therefore, all modes must be preceded by a write enable (wren) instruction. addition- ally the wp pin must be held high during a write enable instruction. at the completion of a write or wrsr cycle the device is automatically turned to the write disable state. note that a write disable (wrdi) instruction or forcing the wp pin low will also return the device to the write disable state. see figure 7. figure 7. write enable write disable (wrdi): to protect against accidental data disturbance the write disable (wrdi) instruction disables all programming modes. the write disable instruction is inde- pendent of the status of the wp pin. see figure 8. figure 8. write disable cs sck si so d2 d1 d0 ds800002-12 cs si so rdsr op-code sr_data msb...lsb ds800002-9 cs si so wren op-code ds800002-10 cs si so wrdi op-code ds800002-11 write sequence: to program the device the write pro- tect (wp) pin must be held high and two separate instructions must be executed. the chip must first be write enabled via the write enable instruction and then a write instruction must be executed. moreover, the address of the memory location(s) to be programmed must be outside the protected address field selected by the block write protection level. see table 3. a write command requires the following sequence. the cs line is pulled low to select the device, then the write op-code (which includes a8) is transmitted on the si line followed by the byte address (a7Ca0) and the corresponding pro-data (d7Cd0) to be programmed. programming will start after the cs pin is forced back to a high level. note that the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 data bit. the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the write cycle is still in progress and bit 0 = 0 indicates that the write cycle has ended. during the write programming cycle (bit 0 = 1) only the read status register instruction is enabled. figure 9. start write condition
8 www.fairchildsemi.com nm25c041 rev. d.1 nm25c041 4k-bit serial interface cmos eeprom (serial peripheral interface (spi) synchronous bus) functional description (continued) the nm25c041 is capable of a four byte page write operation. after receipt of each byte of data the two low order address bits are internally incremented by one. the seven high order bits of the address will remain constant. if the master should transmit more than four bytes of data, the address counter will roll over, and the previously loaded data will be reloaded. see figure 10. figure 10. 4 page byte write at the completion of a write cycle the device is automatically returned to the write disable state. if the wp pin is forced low or the device is not write enabled, the device will ignore the write instruction and return to the standby state when cs is forced high. a new cs falling edge is required to re-initialize the serial communication. write status register (wrsr): the write status register (wrsr) instruction is used to program the non- volatile status register bits 2 and 3 (bp0 and bp1). as in the write mode the write protect (wp) pin must be held high and two separate instructions must be executed. the chip must first be write enabled via the write enable instruction and then a wrsr instruction must be executed. the wrsr command requires the following sequence. the cs line is pulled low to select the device and then the wrsr op-code is transmitted on the si line followed by the data to be programmed (see figure 11). figure 11. write status register note that the first four bits are dont care bits followed by bp1 and bp0 then two additional dont care bits. programming will start after the cs pin is forced back to a high level. as in the write instruction the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the last dont care bit. see figure 12. figure 12. start wrsr condition cs sck si so bp0 t din t csn t dis ds800002-15 cs si so data (n+3) data (n+2) data (n+1) data (n) byte addr(n) write op-code ds800002-13 cs si so wrsr op-code sr_data xxxxbp1bp0xx ds800002-14 the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the wrsr cycle is still in progress and bit 0 = 0 indicates that the wrsr cycle has ended. at the completion of a wrsr cycle the device is automatically returned to the write disable state.
9 www.fairchildsemi.com nm25c041 rev. d.1 nm25c041 4k-bit serial interface cmos eeprom (serial peripheral interface (spi) synchronous bus) molded small out-line package (m8) order number nm25c041m8 package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
10 www.fairchildsemi.com nm25c041 rev. d.1 nm25c041 4k-bit serial interface cmos eeprom (serial peripheral interface (spi) synchronous bus) physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) order number nm25c041n package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm25c160 rev. d.1 nm25c160 16k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) march 1999 ? 1999 fairchild semiconductor corporation nm25c160 16k-bit serial cmos eeprom (serial peripheral interface (spi) synchronous bus) general description the nm25c160 is a 16,384-bit cmos eeprom with an spi compatible serial interface. the nm25c160 is designed for data storage in applications requiring both non-volatile memory and in- system data updates. this eeprom is well suited for applications using the 68hc11 series of microcontrollers that support the spi interface for high speed communication with peripheral devices via a serial bus to reduce pin count. the nm25c160 is imple- mented in fairchild semiconductors floating gate cmos process that provides superior endurance and data retention. the serial data transmission of this device requires four signal lines to control the device operation: chip select (cs), clock (sck), data in (si), and serial data out (so). all programming cycles are completely self-timed and do not require an erase before write. block write protection is provided by programming the sta- tus register with one of four levels of write protection. additionally, separate write enable and write disable instruc- tions are provided for data protection. hardware data protection is provided by the wp pin to protect against inadvertent programming. the hold pin allows the serial communication to be suspended without resetting the serial sequence. block diagram features n 2.1 mhz clock rate @ 2.7v to 5.5v n 16,384 bits organized as 2,048 x 8 n multiple chips on the same 3-wire bus with separate chip select lines n self-timed programming cycle n simultaneous programming of 1 to 16 bytes at a time n status register can be polled during programming to monitor ready/busy n write protect (wp) pin and write disable instruction for both hardware and software write protection n block write protect feature to protect against accidental writes n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin dip, 8-pin so, or 8-pin tssop ds012402-1 instruction decoder control logic and clock generators high voltage generator and program timer instruction register program enable data in/out register 8 bits data out buffer non-volatile status register decoder 1 of 2048 address counter/ register eeprom array 16,384 bits (2048 x 8) read/write amps cs hold sck v cc v ss v pp wp si so
2 www.fairchildsemi.com nm25c160 rev. d.1 nm25c160 16k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) connection diagram dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e (n), m08a (m8), and mtc08 (mt8) pin names cs chip select input so serial data output wp write protect v ss ground si serial data input sck serial clock input hold suspends serial data v cc power supply ordering information nm 25 c xx lz e xx letter description package n 8-pin dip m8 8-pin so mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current density/mode 160 16k, mode 0 c cmos technology interface 25 spi nm fairchild nonvolatile memory prefix cs so wp v ss v cc hold sck si 8 7 6 5 1 2 3 4 nm25c160 ds012402-2
3 www.fairchildsemi.com nm25c160 rev. d.1 nm25c160 16k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) standard voltage 4.5 v cc 5.5v specifications absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c160 0 c to +70 c nm25c160e -40 c to +85 c nm25c160v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v (unless otherwise specified) symbol parameter conditions min max units i cc operating current cs = v il 3ma i ccsb standby current cs = v cc 50 m a i il input leakage v in = 0 to v cc -1 +1 m a i ol output leakage v out = gnd to v cc -1 +1 m a v il cmos input low voltage -0.3 v cc * 0.3 v v ih cmos input high voltage 0.7 * v cc v cc + 0.3 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = -0.8 ma v cc - 0.8 v f op sck frequency 2.1 mhz t ri input rise time 2.0 m s t fi input fall time 2.0 m s t clh clock high time (note 2) 190 ns t cll clock low time (note 2) 190 ns t csh min cs high time (note 3) 240 ns t css cs setup time 240 ns t dis data setup time 100 ns t hds hold setup time 90 ns t csn cs hold time 240 ns t din data hold time 100 ns t hdn hold hold time 90 ns t pd output delay c l = 200 pf 240 ns t dh output hold time 0 ns t lz hold to output low z 100 ns t df output disable time c l = 200 pf 240 ns t hz hold to output high z 100 ns t wp write cycle time 1C16 bytes 10 ms capacitance t a = 25 c, f = 2.1/1 mhz (note 4) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load c l = 200 pf input pulse levels 0.1 * v cc C 0.9 * v cc timing measurement reference level 0.3 * v cc - 0.7 * v cc note 1: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, if the 2.1mhz period = 476ns and t clh = 190ns, t cll must be 286ns. note 3: cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 4: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm25c160 rev. d.1 nm25c160 16k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) low voltage 2.7v v cc 4.5v specifications absolute maximum ratings (note 5) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c160l/lz 0 c to +70 c nm25c160lz/lze -40 c to +85 c nm25c160lv -40 c to +125 c power supply (v cc ) 2.7vC4.5v dc and ac electrical characteristics 2.7v v cc 4.5v (unless otherwise specified) 25c160l/le 25c160lv 25c160lz/lze symbol parameter part conditions min. max. min max units i cc operating current cs = v il 33ma i ccsb standby current l cs = v cc 10 10 m a lz 1 n/a m a i il input leakage v in = 0 to v cc -1 1 -1 1 m a i ol output leakage v out = gnd to v cc -1 1 -1 1 m a v il input low voltage -0.3 v cc * 0.3 -0.3 v cc * 0.3 v v ih input high voltage 0.7 * v cc v cc + 0.3 0.7 * v cc v cc + 0.3 v v ol output low voltage i ol = 0.8 ma 0.4 0.4 v v oh output high voltage i oh = C0.8 ma v cc - 0.8 v cc - 0.8 v f op sck frequency 1.0 1.0 mhz t ri input rise time 2.0 2.0 m s t fi input fall time 2.0 2.0 m s t clh clock high time (note 6) 410 410 ns t cll clock low time (note 6) 410 410 ns t csh min. cs high time (note 7) 500 500 ns t css cs setup time 500 500 ns t dis data setup time 100 100 ns t hds hold setup time 240 240 ns t csn cs hold time 500 500 ns t din data hold time 100 100 ns t hdn hold hold time 240 240 ns t pd output delay c l = 200 pf 500 500 ns t dh output hold time 0 0 ns t lz hold output low z 240 240 ns t df output disable time c l = 200 pf 500 500 ns t hz hold to output hi z 240 240 ns t wp write cycle time 1-16 bytes 15 15 ms capacitance t a = 25 c, f = 2.1/1 mhz (note 8) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load i ol = 10 m a, i oh = 10 m a input pulse levels 0.3v to 3.5v timing measurement reference level input 0.4v and 1.6v output 0.8v and 1.6v note 5: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposur e to absolute maximum rating conditions for extended periods may affect device reliability. note 6: the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, if the 2.1mhz period = 476ns and t clh = 190ns, t cll must be 286ns. note 7: cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 8: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm25c160 rev. d.1 nm25c160 16k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) ac test conditions (continued) figure 1. synchronous data timing diagram figure 3. spi serial interface si so sck cs data out (mosi) data in (miso) serial clock (clk) ss0 ss1 ss2 ss3 si so sck cs si so sck cs si so sck cs spi chip selection master mcu nm25c16 ds012402-3 ds012402-4 sck hold so t hz t hdn t hds t hdn t hds t lz ds012402-6 figure 2. hold timing cs sck si so v ih v il v ih v il v ih v il v oh v ol t css t csh t csn t dis t pd t dh t df t din t clh t cll
6 www.fairchildsemi.com nm25c160 rev. d.1 nm25c160 16k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description table 1. instruction set instruction instruction operation name opcode wren 00000110 set write enable latch wrdi 00000100 reset write enable latch rdsr 00000101 read status register wrsr 00000001 write status register read 00000011 read data from memory array write 00000010 write data to memory array master : the device that generates the serial clock is desig- nated as the master. the nm25c160 can never function as a master. slave : the nm25c160 always operates as a slave as the serial clock pin is always an input. transmitter/receiver : the nm25c160 has separate pins for data transmission (so) and reception (si). msb : the most significant bit is the first bit transmitted and received. chip select : the chip is selected when pin cs is low. when the chip is not selected, data will not be accepted from pin si, and the output pin so is in high impedance. serial op-code : the first byte transmitted after the chip is selected with cs going low contains the op-code that defines the operation to be performed. protocol : when connected to the spi port of a 68hc11 microcontroller, the nm25c160 accepts a clock phase of 0 and a clock polarity of 0. the spi protocol for this device defines the byte transmitted on the si and so data lines for proper chip operation. see figure 4. figure 4. spi protocol cs si so invalid code ds012402-7 cs sck si so bit 7 bit 6 bit 0 bit 1 bit 7 bit 0 ds012402-5 hold : the hold pin is used in conjunction with the cs to select the device. once the device is selected and a serial sequence is underway, hold may be forced low to suspend further serial communication with the device without resetting the serial se- quence. note that hold must be brought low while the sck pin is low. the device must remain selected during this sequence. to resume serial communication hold is brought high while the sck pin is low. the so pin is at a high impedance state during hold. invalid op-code : after an invalid code is received, no data is shifted into the nm25c160, and the so data output pin remains high impedance until a new cs falling edge reinitializes the serial communication. see figure 5. figure 5. invalid op-code data is clocked in on the positive sck edge and out on the negative sck edge.
7 www.fairchildsemi.com nm25c160 rev. d.1 nm25c160 16k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description (continued) read sequence: reading the memory via the serial spi link requires the following sequence. the cs line is pulled low to select the device. the read op-code is transmitted on the si line followed by the high order address byte (a10Ca8), and the low order address byte (a7Ca0). the leading three bits in the high order address byte will be ignored. after this is done, data on the si line becomes dont care. the data (d7Cd0) at the address specified is then shifted out on the so line. if only one byte is to be read, the cs line can be pulled back to the high level. it is possible to continue the read sequence as the byte adress is automatically incremented and data will continue to be shifted out. when the highest address is reached (7ff), the address counter rolls over to lowest address (000) allowing the entire memory to be read in one continuous read cycle. see figure 6. figure 6. read sequence table 3. block write protection levels level status register bits array address bp1 bp0 protected 0 0 0 none 1 0 1 600-7ff 2 1 0 400-7ff 3 1 1 000-7ff write enable (wren) : when v cc is applied to the chip, it powers up in the write disable state. therefore, all programming modes must be preceded by a write enable (wren) instruc- tion. at the completion of a write or wrsr cycle the device is automatically returned to the write disable state. note that a write disable (wrdi) instruction will also return the device to the write disable state. see figure 8. figure 8. write enable cs si so wren op-code ds012402-10 write disable (wrdi) : to protect against accidental data disturbance the write disable (wrdi) instruction disables all programming modes. see figure 9. figure 9. write disable cs si so wrdi op-code ds012402-11 cs si so read op-code byte h addr. n byte l addr. n data n data n+1 data n+2 data n+3 ds012402-8 cs si so rdsr op-code sr data msb?sb ds012402-9 read status register (rdsr) : the read status register (rdsr) instruction provides access to the status register is used to interrogate the ready/busy and write enable status of the chip. two non-volatile status register bits are used to select one of four levels of block write protection. the status register format is shown in table 2. table 2. status register format bit bit bit bit bit bit bit bit 76543210 x x x x bp1 bp0 wen rdy x = don't care status register bit 0 = 0 (rdy) indicates that the device is ready; bit 0 = 1 indicates that a program cycle is in progress. bit 1 = 0 (wen) indicates that the device is not write enabled; bit 1 = 1 indicates that the device is write enabled. non-volatile status register bits 2 and 3 (bp0 and bp1) indicate the level of block write protection selected. the block write protec- tion levels and corresponding status register control bits are shown in table 3. note that if a rdsr instruction is executed during a programming cycle only the rdy bit is valid. all other bits are 1s. see figure 7. figure 7. read status write sequence : to program the device, the write pro- tect (wp) pin must be held high and two separate instructions must be executed. the chip must first be write enabled via the write enable instruction and then a write instruction must be executed. moreover, the address of the memory location(s) to be programmed must be outside the protected address field selected by the block write protection level. see table 3.
8 www.fairchildsemi.com nm25c160 rev. d.1 nm25c160 16k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) sck si so cs d0 d1 d2 cs si so write op-code byte h addr (n) byte l addr (n) data (n) data (n+1) data (n+2) data (n+3) data (n+15) . . . cs si so wrsr op-code sr data xxxxbp1bp0xx ds012402-12 ds012402-13 ds012402-14 functional description (continued) a write command requires the following sequence. the cs line is pulled low to select the device, then the write op-code is transmitted on the si line followed by the high order address byte (a10-a8) and the low order address byte (a7Ca0). the leading five bits in the high order address byte will be ignored. the address is followed by the data (d7Cd0) to be written. programming will start after the cs pin is forced back to a high level. note that the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 data bit. see figure 10. figure 10. write sequence bp0 sck si so cs ds012402-15 the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the write cycle is still in progress and bit 0 = 0 indicates that the write cycle has ended. during the write programming cycle (bit 0 = 1) only the read status regis- ter instruction is enabled. the nm25c160 is capable of a 16 byte page write operation. after receipt of each byte of data the four low order address bits are internally incremented by one. the seven high order bits of the address will remain constant. if the master should transmit more than 16 bytes of data, the address counter will roll over, and the previously loaded data will be reloaded. see figure 11. figure 11. 16 byte page write at the completion of a write cycle the device is automatically returned to the write disable state. if the device is not write enabled, the device will ignore the write instruction and return to the standby state when cs is forced high. a new cs falling edge is required to re-initialize the serial communication. write status register (wrsr): the write status register (wrsr) instruction is used to program the non- volatile status register bits 2 and 3 (bp0 and bp1). the write protect (wp) pin must be held high and two separate instruc- tions must be executed. the chip must first be write enabled via the write enable instruction and then a wrsr instruction must be executed. the wrsr command requires the following sequence. the cs line is pulled low to select the device and then the wrsr op-code is transmitted on the si line followed by the data to be pro- grammed. see figure 12. figure 12. write status register note that the first four bits are dont care bits followed by bp1 and bp0 then two additional dont care bits. programming will start after the cs pin is forced back to a high level. as in the write instruction the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the last dont care bit. see figure 13. figure 13. start wrsr condition the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the wrsr cycle is still in progress and bit 0 = 0 indicates that the wrsr cycle has ended. at the completion of a write cycle the device is automatically returned to the write disable state.
9 www.fairchildsemi.com nm25c160 rev. d.1 nm25c160 16k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) molded small out-line package (m8) package number m08a molded dual-in-line package (n) package number n08e physical dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
10 www.fairchildsemi.com nm25c160 rev. d.1 nm25c160 16k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) 8-pin molded tssop, jedec (mt8) package number mtc08 physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
1 www.fairchildsemi.com nm25c640 rev. d.2 nm25c640 64k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) preliminary march 1999 ? 1999 fairchild semiconductor corporation nm25c640 64k-bit serial cmos eeprom (serial peripheral interface (spi) synchronous bus) general description the nm25c640 is a 65,536-bit cmos eeprom with an spi compatible serial interface. the nm25c640 is designed for data storage in applications requiring both non-volatile memory and in- system data updates. this eeprom is well suited for applications using the 68hc11 series of microcontrollers that support the spi interface for high speed communication with peripheral devices via a serial bus to reduce pin count. the nm25c640 is imple- mented in fairchild semiconductors floating gate cmos process that provides superior endurance and data retention. the serial data transmission of this device requires four signal lines to control the device operation: chip select (cs), clock (sck), data in (si), and serial data out (so). all programming cycles are completely self-timed and do not require an erase before write. block write protection is provided by programming the sta- tus register with one of four levels of write protection. additionally, separate write enable and write disable instruc- tions are provided for data protection. hardware data protection is provided by the wp pin to protect against inadvertent programming. the hold pin allows the serial communication to be suspended without resetting the serial sequence. block diagram features n 2.75 mhz clock rate @ 4.5v to 5.5v 2.1 mhz @ 2.7v to 4.5v n 65,536 bits organized as 8,192 x 8 n multiple chips on the same 3-wire bus with separate chip select lines n self-timed programming cycle n simultaneous programming of 1 to 32 bytes at a time n status register can be polled during programming to monitor ready/busy n write protect (wp) pin and write disable instruction for both hardware and software write protection n block write protect feature to protect against accidental writes n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin dip or 8-pin so ds500041-1 instruction decoder control logic and clock generators high voltage generator and program timer instruction register program enable data in/out register 8 bits data out buffer non-volatile status register decoder 1 of 8,192 address counter/ register eeprom array 65,536 bits (8,192 x 8) read/write amps cs hold sck v cc v ss v pp wp si so
2 www.fairchildsemi.com nm25c640 rev. d.2 nm25c640 64k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) connection diagram dual-in-line package (n) and so package (m8) top view pin names cs chip select input so serial data output wp write protect v ss ground si serial data input sck serial clock input hold suspends serial data v cc power supply ordering information nm 25 c xx lz e xx letter description package n 8-pin dip m8 8-pin so temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current density/mode 640 64k, mode 0 c cmos interface 25 spi nm fairchild nonvolatile memory cs so wp v ss v cc hold sck si 8 7 6 5 1 2 3 4 nm25c640 ds500041-2
3 www.fairchildsemi.com nm25c640 rev. d.2 nm25c640 64k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) standard voltage 4.5 v cc 5.5v specifications absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c640 0 c to +70 c nm25c640e -40 c to +85 c nm25c640v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v (unless otherwise specified) symbol parameter conditions min max units i cc operating current cs = v il 3ma i ccsb standby current cs = v cc 50 m a i il input leakage v in = 0 to v cc -1 +1 m a i ol output leakage v out = gnd to v cc -1 +1 m a v il cmos input low voltage -0.3 v cc * 0.3 v v ih cmos input high voltage v cc * 0.7 v cc + 0.3 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -0.8 ma v cc - 0.8 v f op sck frequency 2.75 mhz t ri input rise time 2.0 m s t fi input fall time 2.0 m s t clh clock high time (note 2) 155 ns t cll clock low time (note 2) 155 ns t csh min cs high time (note 3) 240 ns t css cs setup time 176 ns t dis data setup time 50 ns t hds hold setup time 90 ns t csn cs hold time 155 ns t din data hold time 50 ns t hdn hold hold time 90 ns t pd output delay c l = 200 pf 135 ns t dh output hold time 0 ns t lz hold to output low z 240 ns t df output disable time c l = 200 pf 290 ns t hz hold to output high z 240 ns t wp write cycle time 1C32 bytes 10 ms capacitance t a = 25 c, f = 2.1/1 mhz (note 4) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf note 1: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, if the 2.1mhz period = 476ns and t clh = 190ns, t cll must be 286ns. note 3: cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 4: this parameter is periodically sampled and not 100% tested. ac test conditions output load c l = 200 pf input pulse levels 0.1 * v cc C 0.9 * v cc timing measurement reference level 0.3 * v cc - 0.7 ? v cc
4 www.fairchildsemi.com nm25c640 rev. d.2 nm25c640 64k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) note 5: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 6: the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, if the 2.1mhz period = 476ns and t clh = 190ns, t cll must be 286ns. note 7: cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 8: this parameter is periodically sampled and not 100% tested. low voltage 2.7v v cc 4.5v specifications absolute maximum ratings (note 5) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c640l/lz 0 c to +70 c nm25c640lz/lze -40 c to +85 c nm25c640lv -40 c to +125 c power supply (v cc ) 2.7vC4.5v dc and ac electrical characteristics 2.7v v cc 4.5v (unless otherwise specified) 25c640l/le 25c640lv 25c640lz/lze symbol parameter part conditions min. max. min max units i cc operating current cs = v il 33ma i ccsb standby current l cs = v cc 10 10 m a lz 1 n/a m a i il input leakage v in = 0 to v cc -1 1 -1 1 m a i ol output leakage v out = gnd to v cc -1 1 -1 1 m a v il input low voltage -0.3 0.3 * v cc -0.3 0.3 * v cc v v ih input high voltage 0.7 * v cc v cc + 0.3 0.7 * v cc v cc + 0.3 v v ol output low voltage i ol = 1.6 ma 0.4 0.4 v v oh output high voltage i oh = C0.8 ma v cc - 0.8 v cc - 0.8 v f op sck frequency 2.1 1.0 mhz t ri input rise time 2.0 2.0 m s t fi input fall time 2.0 2.0 m s t clh clock high time (note 6) 190 410 ns t cll clock low time (note 6) 190 410 ns t csh min. cs high time (note 7) 240 500 ns t css cs setup time 240 500 ns t dis data setup time 100 100 ns t hds hold setup time 90 240 ns t csn cs hold time 240 500 ns t din data hold time 100 100 ns t hdn hold hold time 90 240 ns t pd output delay c l = 200 pf 240 500 ns t dh output hold time 0 0 ns t lz hold output low z 100 240 ns t df output disable time c l = 200 pf 240 500 ns t hz hold to output hi z 100 240 ns t wp write cycle time 1-32 bytes 15 15 ms capacitance t a = 25 c, f = 2.1/1 mhz (note 8) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load c l = 200pf input pulse levels 0.1 * v cc - 0.9 * v cc timing measurement reference level 0.3 * v cc - 0.7 * v cc
5 www.fairchildsemi.com nm25c640 rev. d.2 nm25c640 64k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) ac test conditions (continued) figure 1. synchronous data timing diagram figure 3. spi serial interface si so sck cs data out (mosi) data in (miso) serial clock (clk) ss0 ss1 ss2 ss3 si so sck cs si so sck cs si so sck cs spi chip selection master mcu nm25c640 ds500041-3 ds500041-4 sck hold so t hz t hdn t hds t hdn t hds t lz ds500041-6 figure 2. hold timing cs sck si so v ih v il v ih v il v ih v il v oh v ol t css t csh t csn t dis t pd t dh t df t din t clh t cll
6 www.fairchildsemi.com nm25c640 rev. d.2 nm25c640 64k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description table 1. instruction set instruction instruction operation name opcode wren 00000110 set write enable latch wrdi 00000100 reset write enable latch rdsr 00000101 read status register wrsr 00000001 write status register read 00000011 read data from memory array write 00000010 write data to memory array master : the device that generates the serial clock is desig- nated as the master. the nm25c640 can never function as a master. slave : the nm25c640 always operates as a slave as the serial clock pin is always an input. transmitter/receiver : the nm25c640 has separate pins for data transmission (so) and reception (si). msb : the most significant bit is the first bit transmitted and received. chip select : the chip is selected when pin cs is low. when the chip is not selected, data will not be accepted from pin si, and the output pin so is in high impedance. serial op-code : the first byte transmitted after the chip is selected with cs going low contains the op-code that defines the operation to be performed. protocol : when connected to the spi port of a 68hc11 microcontroller, the nm25c640 accepts a clock phase of 0 and a clock polarity of 0. the spi protocol for this device defines the byte transmitted on the si and so data lines for proper chip operation. see figure 4. figure 4. spi protocol cs sck si so bit 7 bit 6 bit 0 bit 1 bit 7 bit 0 cs si so invalid code ds500041-7 ds500041-5 hold : the hold pin is used in conjunction with the cs to select the device. once the device is selected and a serial sequence is underway, hold may be forced low to suspend further serial communication with the device without resetting the serial se- quence. note that hold must be brought low while the sck pin is low. the device must remain selected during this sequence. to resume serial communication hold is brought high while the sck pin is low. the so pin is at a high impedance state during hold. invalid op-code : after an invalid code is received, no data is shifted into the nm25c640, and the so data output pin remains high impedance until a new cs falling edge reinitializes the serial communication. see figure 5 . figure 5. invalid op-code data is clocked in on the positive sck edge and out on the negative sck edge.
7 www.fairchildsemi.com nm25c640 rev. d.2 nm25c640 64k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description (continued) cs si so read op-code byte h addr. n byte l addr. n data n data n+1 data n+2 data n+3 cs si so rdsr op-code sr data msblsb cs si so wren op-code ds500041-8 ds500041-9 ds500041-10 read sequence: reading the memory via the serial spi link requires the following sequence. the cs line is pulled low to select the device. the read op-code is transmitted on the si line followed by the high order address byte (a12Ca8), and the low order address byte (a7Ca0). the leading three bits in the high order address byte will be ignored. after this is done, data on the si line becomes dont care. the data (d7Cd0) at the address specified is then shifted out on the so line. if only one byte is to be read, the cs line can be pulled back to the high level. it is possible to continue the read sequence as the byte adress is automatically incremented and data will continue to be shifted out. when the highest address is reached (1fff), the address counter rolls over to lowest address (000) allowing the entire memory to be read in one continuous read cycle. see figure 6. figure 6. read sequence read status register (rdsr) : the read status register (rdsr) instruction provides access to the status register is used to interrogate the ready/busy and write enable status of the chip. two non-volatile status register bits are used to select one of four levels of block write protection. the status register format is shown in table 2. table 2. status register format bit bit bit bit bit bit bit bit 76543210 x x x x bp1 bp0 wen rdy x = don't care. status register bit 0 = 0 (rdy) indicates that the device is ready; bit 0 = 1 indicates that a program cycle is in progress. bit 1 = 0 (wen) indicates that the device is not write enabled; bit 1 = 1 indicates that the device is write enabled. non-volatile status register bits 2 and 3 (bp0 and bp1) indicate the level of block write protection selected. the block write protec- tion levels and corresponding status register control bits are shown in table 3. note that if a rdsr instruction is executed during a programming cycle only the rdy bit is valid. all other bits are 1s. see figure 7. figure 7. read status table 3. block write protection levels level status register bits array address bp1 bp0 protected 0 0 0 none 1 0 1 1800-1fff 2 1 0 1000-1fff 3 1 1 0000C1fff write enable (wren) : when v cc is applied to the chip, it powers up in the write disable state. therefore, all programming modes must be preceded by a write enable (wren) instruc- tion. additionally, the wp must be held high during a write engble instruction. at the completion of a write or wrsr cycle the device is automatically returned to the write disable state. note that a write disable (wrd) instruction will also return the device to the write disable state. see figure 8. figure 8. write enable write disable (wrdi) : to protect against accidental data disturbance the write disable (wrdi) instruction disables all programming modes. see figure 9. figure 9. write disable cs si so wrdi op-code ds500041-11
8 www.fairchildsemi.com nm25c640 rev. d.2 nm25c640 64k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description (continued) write sequence : to program the device, the write pro- tect (wp) pin must be held high and two separate instructions must be executed. the chip must first be write enabled via the write enable instruction and then a write instruction must be executed. moreover, the address of the memory location(s) to be programmed must be outside the protected address field selected by the block write protection level. see table 3. a write command requires the following sequence. the cs line is pulled low to select the device, then the write op-code is transmitted on the si line followed by the high order address byte (a12-a8) and the low order address byte (a7Ca0). the leading five bits in the high order address byte will be ignored. the address is followed by the data (d7Cd0) to be written. programming will start after the cs pin is forced back to a high level. note that the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 data bit. see figure 10. figure 10. end of write sequence sck si so cs d0 d1 d2 cs si so write op-code byte h addr (n) byte l addr (n) data (n) data (n+1) data (n+2) data (n+3) . . . data (n+31) cs si so wrsr op-code sr data xxxxbp1bp0xx ds500041-12 ds500041-13 the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the write cycle is still in progress and bit 0 = 0 indicates that the write cycle has ended. during the write programming cycle (bit 0 = 1) only the read status regis- ter instruction is enabled. the nm25c640 is capable of a 32 byte page write operation. after receipt of each byte of data the five low order address bits are internally incremented by one. the eight high order bits of the address will remain constant. if the master should transmit more than 32 bytes of data, the address counter will roll over, and the previously loaded data will be reloaded. see figure 11. figure 11. 32 byte page write at the completion of a write cycle the device is automatically returned to the write disable state. if the device is not write enabled, the device will ignore the write instruction and return to the standby state when cs is forced high. a new cs falling edge is required to re-initialize the serial communication. write status register (wrsr): the write status register (wrsr) instruction is used to program the non- volatile status register bits 2 and 3 (bp0 and bp1). the write protect (wp) pin must be held high and two separate instruc- tions must be executed. the chip must first be write enabled via the write enable instruction and then a wrsr instruction must be executed. the wrsr command requires the following sequence. the cs line is pulled low to select the device and then the wrsr op-code is transmitted on the si line followed by the data to be pro- grammed. see figure 12. figure 12. write status register ds500041-14 note that the first four bits are dont care bits followed by bp1 and bp0 then two additional dont care bits. programming will start after the cs pin is forced back to a high level. as in the write instruction the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the last dont care bit. see figure 13. figure 13. start wrsr condition the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the wrsr cycle is still in progress and bit 0 = 0 indicates that the wrsr cycle has ended. at the completion of a write cycle the device is automatically returned to the write disable state. bp0 sck si so cs ds500041-15
9 www.fairchildsemi.com nm25c640 rev. d.2 nm25c640 64k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) molded small out-line package (m8) package number m08a molded dual-in-line package (n) package number n08e physical dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
10 www.fairchildsemi.com nm25c640 rev. d.2 nm25c640 64k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm25c020 2048-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) july 1998 ? 1998 fairchild semiconductor corporation nm25c020 2048-bit serial cmos eeprom (serial peripheral interface (spi) synchronous bus) general description the nm25c020 is a 2048-bit cmos eeprom with an spi compatible serial interface. the nm25c020 is designed for data storage in applications requiring both non-volatile memory and in- system data updates. this eeprom is well suited for applications using the 68hc11 series of microcontrollers that support the spi interface for high speed communication with peripheral devices via a serial bus to reduce pin count. the nm25c020 is imple- mented in fairchild semiconductors floating gate cmos process that provides superior endurance and data retention. the serial data transmission of this device requires four signal lines to control the device operation: chip select (cs), clock (sck), data in (si), and serial data out (so). all programming cycles are completely self-timed and do not require an erase before write. block write protection is provided by programming the sta- tus register with one of four levels of write protection. additionally, separate write enable and write program dis- able instructions are provided for data protection. hardware data protection is provided by the wp pin to protect against accidental data changes. the hold pin allows the serial block diagram communication to be suspended without resetting the serial sequence. features n 2.1 mhz clock rate @ 2.7v to 5.5v n 2048 bits organized as 256 x 8 n multiple chips on the same 3-wire bus with separate chip select lines n self-timed programming cycle n simultaneous programming of 1 to 4 bytes at a time n status register can be polled during programming to monitor ready/busy n write protect (wp) pin and write disable instruction for both hardware and software write protection n block write protect feature to protect against accidental writes n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin dip, 8-pin so, or 8-pin tssop ds012400-1 instruction decoder control logic and clock generators high voltage generator and program timer instruction register program enable data in/out register 8 bits data out buffer non-volatile status register decoder 1 of 256 address counter/ register eeprom array 2048 bits (256 x 8) read/write amps cs hold sck v cc v ss v pp wp si so
2 www.fairchildsemi.com nm25c020 2048-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) connection diagram dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e (n), m08a (m8), and mtc08 (mt8) pin names cs chip select input so serial data output wp write protect v ss ground si serial data input sck serial clock input hold suspends serial data v cc power supply ordering information nm 25 c xx lz e xx letter description package n 8-pin dip m8 8-pin so mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 m a standby current density 020 2k, mode 0 c cmos technology interface 25 spi - 3 wire nm fairchild nonvolatile memory prefix cs so wp v ss v cc hold sck si 8 7 6 5 1 2 3 4 nm25c020 ds012400-2
3 www.fairchildsemi.com nm25c020 2048-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) standard voltage 4.5 v cc 5.5v specifications absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c020 0 c to +70 c nm25c020e -40 c to +85 c nm25c020v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v (unless otherwise specified) symbol parameter conditions min max units i cc operating current cs = v il 3ma i ccsb standby current cs = v cc 50 m a i il input leakage v in = 0v to v cc -1 +1 m a i ol output leakage v in = 0v to v cc -1 +1 m a v il cmos input low voltage -0.3 0.8 v v ih cmos input high voltage 2 v cc + 0.3 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -0.8 ma v cc - 0.8 v f op sck frequency 2.1 mhz t ri input rise time 2.0 m s t fi input fall time 2.0 m s t clh clock high time (note 2) 190 ns t cll clock low time (note 2) 190 v t csh min cs high time (note 3) 240 ns t css cs setup time 240 ns t dis data setup time 100 ns t hds hold setup time 90 ns t csn cs hold time 240 ns t din data hold time 100 ns t hdn hold hold time 90 ns t pd output delay from clock low c l = 200 pf 240 ns t dh output hold time 0 ns t lz hold to output low z 100 ns t df output disable time c l = 200 pf 240 ns t hz hold to output high z 100 ns t wp write cycle time 1C4 bytes 10 ms capacitance t a = 25 c, f = 1 mhz (note 4) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load c l = 200 pf input pulse levels 0.1 * v cc C 0.9 * v cc timing measurement reference level 0.3 * v cc - .07 * v cc note 1: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: the sck frequency specification specifies a minimum clock period of 476 ns; therefore, in an sck clock cycle, t clh +t cll must be greater than or equal to 476 ns. for example, if t cll = 190 ns, then the minimum t clh = 286 ns in order to meet the sck frequency specification. note 3: cs must be brought high for a minimum of 240 ns (t csh ) between consecutive instruction cycles. note 4: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm25c020 2048-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) low voltage 2.7v v cc 5.5v specifications absolute maximum ratings (note 5) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c020l/lz 0 c to +70 c nm25c020le/lze -40 c to +85 c nm25c020lv -40 c to +125 c power supply (v cc ) 2.7vC5.5v dc and ac electrical characteristics 2.7v v cc 5.5v (unless otherwise specified) 25c020e 25c020v symbol parameter part conditions min. max. min max units i cc operating current cs = v il 33ma i ccsb standby current l cs = v cc 10 10 m a lz 1 n/a m a i il input leakage v in = 0 to v cc -1 1 -1 1 m a i ol output leakage v out = gnd to v cc -1 1 -1 1 m a v il input low voltage -0.3 0.8 -0.3 0.8 v v ih input high voltage 2 v cc + 0.3 2 v cc + 0.3 v v ol output low voltage i ol = 2.1 ma 0.4 0.4 v v oh output high voltage i oh = C0.8 ma v cc - 0.8 v cc - 0.8 v f op sck frequency 2.1 2.1 mhz t ri input rise time 2.0 2.0 m s t fi input fall time 2.0 2.0 m s t clh clock high time (note 6) 190 190 ns t cll clock low time (note 6) 190 190 ns t csh min. cs high time (note 7) 240 240 ns t css cs setup time 240 240 ns t dis data setup time 100 100 ns t hds hold setup time 90 90 ns t csn cs hold time 240 240 ns t din data hold time 100 100 ns t hdn hold hold time 90 90 ns t pd output delay from c l = 200 pf 240 240 ns clock low t dh output hold time 0 0 ns t lz hold output low z 100 100 ns t df output disable time c l = 200 pf 240 240 ns t hz hold to output hi z 100 100 ns t wp write cycle time 1-4 bytes 10 10 ms capacitance t a = 25 c, f = 1 mhz (note 8) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load i ol = 10 m a, i oh = 10 m a input pulse levels 0.3v to 3.5v timing measurement reference level input 0.4v and 1.6v output 0.8v and 1.6v note 5: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 6: minimum clock period. specified minimum clock period for sck frequency varies with temperature range. extended temperature rang e (e), the minimum clock period is 476ns. in the automotive temperature range, the minimum clock period is 1000ns. for example, using the extended tempe rature range minimum, if t cll = 190ns, the minimum t clh is 286ns (190ns + 286ns = 476ns). note 7: cs must be brought high for a minimum of 250 ns (t csh ) between consecutive instruction cycles. note 8: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm25c020 2048-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) ac test conditions (continued) synchronous data timing diagram (figure 1) spi serial interface (figure 2) cs sck si so valid in valid out v ih v il v ih v il v ih v il v oh v ol t css t csh t csn t dis t pd t dh t df t din t clh t cll si so sck cs data out (mosi) data in (miso) serial clock (spick) ss0 ss1 ss2 ss3 si so sck cs si so sck cs si so sck cs spi chip selection master mcu nm25c020 ds012400-3 ds012400-4
6 www.fairchildsemi.com nm25c020 2048-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description master : the device that generates the serial clock is desig- nated as the master. the nm25c020 can never function as a master. slave : the nm25c020 always operates as a slave as the serial clock pin is always an input. transmitter/receiver : the nm25c020 has separate pins for data transmission (so) and reception (si). msb : the most significant bit is the first bit transmitted and received. chip select : the chip is selected when pin cs is low. when the chip is not selected, data will not be accepted from pin si, and the output pin so is in high impedance. serial op-code : the first byte transmitted after the chip is selected with cs going low contains the op-code that defines the operation to be performed. protocol : when connected to the spi port of a 68hc11 microcontroller, the nm25c020 accepts a clock phase of 0 and a clock polarity of 0. the spi protocol for this device defines the byte transmitted on the si and so data lines for proper chip operation. see figure 4. data is clocked in on the positive sck edge and out on the negative sck edge. hold : the hold pin is used in conjunction with the cs to select the device. once the device is selected and a serial sequence is underway, hold may be forced low to suspend further serial communication with the device without resetting the serial se- quence. note that hold must be brought low while the sck pin is low. the device must remain selected during this sequence. to resume serial communication hold is brought high while the sck pin is low. pins si, sck and so are at a high impedance state during hold. see figure 5. invalid op-code : after an invalid code is received, no data is shifted into the nm25c020, and the so data output pin remains high impedance until a new cs falling edge reinitializes the serial communication. see figure 3. invalid op-code (figure 3) instruction set (table 1) instruction instruction operation name format wren 00000110 set write enable latch wrdi 00000100 reset write enable latch rdsr 00000101 read status register wrsr 00000001 write status register read 00000011 read data from memory array write 00000010 write data to memory array cs si so invalid code ds012400-7
7 www.fairchildsemi.com nm25c020 2048-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description (continued) spi protocol (figure 4) cs sck si so bit 7 bit 6 bit 0 bit 1 bit 7 bit 0 sck hold so t hz t hdn t hds t hdn t hds t lz ds012400-5 ds012400-6 hold timing (figure 5) read sequence (figure 6) read status (figure 7) cs si so read op-code read op-code data n data n + 1 data n + 2 data n + 3 cs si so rdsr op-code sr data msb?sb ds012400-8 ds012400-9
8 www.fairchildsemi.com nm25c020 2048-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description (continued) read sequence: (one or more bytes): reading the memory via the serial spi link requires the following sequence. the cs line is pulled low to select the device. the read op-code is transmit- ted on the si line followed by the byte address (a7Ca0) to be read. after this is done, data on the si line becomes dont care. the data (d7Cd0) at the address specified is then shifted out on the so line. if only one byte is to be read, the cs line can be pulled back to the high level. it is possible to continue the read sequence as the byte adress is automatically incremented and data will continue to be shifted out. when the highest address is reached (ff), the address counter rolls over to lowest address (000) allowing the entire memory to be read in one continuous read cycle. see figure 6. read status register (rdsr) : the read status register (rdsr) instruction provides access to the status register is used to interrogate the ready/busy and write enable status of the chip. two non-volatile status register bits are used to select one of four levels of block write protection. the status register format is shown in table 2. status register format (table 2) bit bit bit bit bit bit bit bit 76543210 1 1 1 1 bp1 bp0 wen rdy status register bit 0 = 0 (rdy) indicates that the device is ready; bit 0 = 1 indicates that a program cycle is in progress. bit 1 = 0 (wen) indicates that the device is not write enabled; bit 1 = 1 indicates that the device is write enabled. non-volatile status register bits 2 and 3 (bp0 and bp1) indicate the level of block write protection selected. the block write protec- tion levels and corresponding status register control bits are shown in table 3. note that if a rdsr instruction is executed during a programming cycle only the rdy bit is valid. all other bits are 1s. see figure 7. block write protection levels (table 3) level status register bits array address bp1 bp0 protected 0 0 0 none 1 0 1 c0-ff 2 1 0 80-ff 3 1 1 00-ff write enable (wren) : when v cc is applied to the chip, it powers up in the write disable state. therefore, all programming modes must be preceded by a write enable (wren) instruc- tion. at the completion of a write or wrsr cycle the device is automatically returned to the write disable state. note that a write disable (wrdi) instruction will also return the device to the write disable state. see figure 8. write disable (wrdi) : to protect against accidental data disturbance the write disable (wrdi) instruction disables all programming modes. see figure 9. write disable (figure 9) cs si so wren op-code ds012400-10 write sequence : to program the device, the write pro- tect (wp) pin must be held high and two separate instructions must be executed. the chip must first be write enabled via the write enable instruction and then a write instruction must be executed. moreover, the address of the memory location(s) to be programmed must be outside the protected address field selected by the block write protection level. see table 3. a write command requires the following sequence. the cs line is pulled low to select the device, then the write op-code is transmitted on the si line followed by the byte address(a7Ca0) and the corresponding data (d7-d0) to be written. programming will start after the cs pin is forced back to a high level. note that the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 data bit. see figure 10. the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the write cycle is still in progress and bit 0 = 0 indicates that the write cycle has ended. during the write programming cycle (bit 0 = 1) only the read status regis- ter instruction is enabled. the nm25c020 is capable of a 4 byte page write operation. after receipt of each byte of data the two low order address bits are internally incremented by one. the seven high order bits of the address will remain constant. if the master should transmit more than 4 bytes of data, the address counter will roll over, and the previously loaded data will be reloaded. see figure 11. at the completion of a write cycle the device is automatically returned to the write disable state. if the device is not write enabled, the device will ignore the write instruction and return to the standby state when cs is forced high. a new cs falling edge is required to re-initialize the serial communication. cs si so wrdi op-code ds012400-11 write enable (figure 8)
9 www.fairchildsemi.com nm25c020 2048-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) sck si so cs t din t dis t csn d0 d1 d2 cs si so write op-code byte addr (n) data (n) data (n + 1) data (n + 2) data (n + 3) cs si so wrsr op-code sr data xxxxbp1bp0xx ds012400-12 ds012400-13 ds012400-14 functional description (continued) write sequence (figure 10) start write condition (figure 11) write status register (figure 12) bp0 sck si so cs t din t dis t csn ds012400-15 start wrsr condition (figure 13) write status register (wrsr): the write status register (wrsr) instruction is used to program the non- volatile status register bits 2 and 3 (bp0 and bp1). the write protect (wp) pin must be held high and two separate instruc- tions must be executed. the chip must first be write enabled via the write enable instruction and then a wrsr instruction must be executed. the wrsr command requires the following sequence. the cs line is pulled low to select the device and then the wrsr op-code is transmitted on the si line followed by the data to be pro- grammed. see figure 12. note that the first four bits are dont care bits followed by bp1 and bp0 then two additional dont care bits. programming will start after the cs pin is forced back to a high level. as in the write instruction the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the last dont care bit. see figure 13. the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the wrsr cycle is still in progress and bit 0 = 0 indicates that the wrsr cycle has ended. at the completion of a write cycle the device is automatically returned to the write disable state.
10 www.fairchildsemi.com nm25c020 2048-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) molded small out-line package (m8) package number m08a molded dual-in-line package (n) package number n08e physical dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
11 www.fairchildsemi.com nm25c020 2048-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) 8-pin molded tssop, jedec (mt8) package number mtc08 physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
1 www.fairchildsemi.com nm25c040 4096-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) july 1998 ? 1998 fairchild semiconductor corporation nm25c040 4096-bit serial cmos eeprom (serial peripheral interface (spi) synchronous bus) general description the nm25c040 is a 4096-bit cmos eeprom with an spi compatible serial interface. the nm25c040 is designed for data storage in applications requiring both non-volatile memory and in- system data updates. this eeprom is well suited for applications using the 68hc11 series of microcontrollers that support the spi interface for high speed communication with peripheral devices via a serial bus to reduce pin count. the nm25c040 is imple- mented in fairchild semiconductors floating gate cmos process that provides superior endurance and data retention. the serial data transmission of this device requires four signal lines to control the device operation: chip select (cs), clock (sck), data in (si), and serial data out (so). all programming cycles are completely self-timed and do not require an erase before write. block write protection is provided by programming the sta- tus register with one of four levels of write protection. additionally, separate write enable and write program dis- able instructions are provided for data protection. hardware data protection is provided by the wp pin to protect against accidental data changes. the hold pin allows the serial block diagram communication to be suspended without resetting the serial sequence. features n 2.1 mhz clock rate @ 2.7v to 5.5v n 4096 bits organized as 512 x 8 n multiple chips on the same 3-wire bus with separate chip select lines n self-timed programming cycle n simultaneous programming of 1 to 4 bytes at a time n status register can be polled during programming to monitor ready/busy n write protect (wp) pin and write disable instruction for both hardware and software write protection n block write protect feature to protect against accidental writes n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin dip, 8-pin so, or 8-pin tssop ds012401-1 instruction decoder control logic and clock generators high voltage generator and program timer instruction register program enable data in/out register 8 bits data out buffer non-volatile status register decoder 1 of 512 address counter/ register eeprom array 4096 bits (512 x 8) read/write amps cs hold sck v cc v ss v pp wp si so
2 www.fairchildsemi.com nm25c040 4096-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) connection diagram dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e (n), m08a (m8), and mtc08 (mt8) pin names cs chip select input so serial data output wp write protect v ss ground si serial data input sck serial clock input hold suspends serial data v cc power supply ordering information nm 25 c xx lz e xx letter description package n 8-pin dip m8 8-pin so mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 m a standby current density 040 4k, mode 0 c cmos technology interface 25 spi - 3 wire nm fairchild nonvolatile memory prefix cs so wp v ss v cc hold sck si 8 7 6 5 1 2 3 4 nm25c040 ds012401-2
3 www.fairchildsemi.com nm25c040 4096-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) standard voltage 4.5 v cc 5.5v specifications absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c040 0 c to +70 c nm25c040e -40 c to +85 c nm25c040v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v (unless otherwise specified) symbol parameter conditions min max units i cc operating current cs = v il 3ma i ccsb standby current cs = v cc 50 m a i il input leakage v in = 0v to v cc -1 +1 m a i ol output leakage v in = 0v to v cc -1 +1 m a v il cmos input low voltage -0.3 0.8 v v ih cmos input high voltage 2 v cc + 0.3 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -0.8 ma v cc - 0.8 v f op sck frequency 2.1 mhz t ri input rise time 2.0 m s t fi input fall time 2.0 m s t clh clock high time (note 2) 190 ns t cll clock low time (note 2) 190 v t csh min cs high time (note 3) 240 ns t css cs setup time 240 ns t dis data setup time 100 ns t hds hold setup time 90 ns t csn cs hold time 240 ns t din data hold time 100 ns t hdn hold hold time 90 ns t pd output delay from clock low c l = 200 pf 240 ns t dh output hold time 0 ns t lz hold to output low z 100 ns t df output disable time c l = 200 pf 240 ns t hz hold to output high z 100 ns t wp write cycle time 1C4 bytes 10 ms capacitance t a = 25 c, f = 1 mhz (note 4) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load c l = 200 pf input pulse levels 0.1 * v cc C 0.9 * v cc timing measurement reference level 0.3 * v cc - 0.7 * v cc note 1: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: the sck frequency specification specifies a minimum clock period of 476 ns; therefore, in an sck clock cycle, t clh +t cll must be greater than or equal to 476 ns. for example, if t cll = 190 ns, then the minimum t clh = 286 ns in order to meet the sck frequency specification. note 3: cs must be brought high for a minimum of 240 ns (t csh ) between consecutive instruction cycles. note 4: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm25c040 4096-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) low voltage 2.7v v cc 5.5v specifications absolute maximum ratings (note 5) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c040l/lz 0 c to +70 c nm25c040le/lze -40 c to +85 c nm25c040lv -40 c to +125 c power supply (v cc ) 2.7vC5.5v dc and ac electrical characteristics 2.7v v cc 5.5v (unless otherwise specified) 25c040le 25c040lv symbol parameter part conditions min. max. min max units i cc operating current cs = v il 33ma i ccsb standby current l cs = v cc 10 10 m a lz 1 m a i il input leakage v in = 0 to v cc -1 1 -1 1 m a i ol output leakage v out = gnd to v cc -1 1 -1 1 m a v il input low voltage -0.3 v cc * 0.3 -0.3 v cc * 0.3 v v ih input high voltage v cc * 0.7 v cc + 0.3 v cc * 0.7 v cc + 0.3 v v ol output low voltage i ol = 2.1 ma 0.4 0.4 v v oh output high voltage i oh = C0.8 ma v cc - 0.8 v cc - 0.8 v f op sck frequency 2.1 1.0 mhz t ri input rise time 2.0 2.0 m s t fi input fall time 2.0 2.0 m s t clh clock high time (note 6) 190 410 ns t cll clock low time (note 6) 190 410 ns t csh min. cs high time (note 7) 240 500 ns t css cs setup time 240 500 ns t dis data setup time 100 100 ns t hds hold setup time 90 500 ns t csn cs hold time 240 500 ns t din data hold time 100 100 ns t hdn hold hold time 90 240 ns t pd output delay from c l = 200 pf 240 240 ns clock low t dh output hold time 0 0 ns t lz hold output low z 100 240 ns t df output disable time c l = 200 pf 240 500 ns t hz hold to output hi z 100 240 ns t wp write cycle time 1-4 bytes 10 10 ms capacitance t a = 25 c, f = 1 mhz (note 8) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load c l = 200pf input pulse levels 0.1 * v cc - 0.9 * v cc timing measurement reference level 0.3 * v cc - 0.7 * v cc note 5: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 6: minimum clock period. specified minimum clock period for sck frequency varies with temperature range. extended temperature rang e (e), the minimum clock period is 476ns (2.1mhz). in the automotive temperature range, the minimum clock period is 1000ns (1mhz). for example, using th e extended temperature range minimum, if t cll = 190ns, the minimum t clh is 286ns (190ns + 286ns = 476ns). note 7: cs must be brought high for a minimum of 250 ns (t csh ) between consecutive instruction cycles. note 8: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm25c040 4096-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) ac test conditions (continued) synchronous data timing diagram (figure 1) spi serial interface (figure 2) cs sck si so valid in valid out v ih v il v ih v il v ih v il v oh v ol t css t csh t csn t dis t pd t dh t df t din t clh t cll si so sck cs data out (mosi) data in (miso) serial clock (spick) ss0 ss1 ss2 ss3 si so sck cs si so sck cs si so sck cs spi chip selection master mcu nm25c040 ds012401-3 ds012401-4
6 www.fairchildsemi.com nm25c040 4096-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description master : the device that generates the serial clock is desig- nated as the master. the nm25c040 can never function as a master. slave : the nm25c040 always operates as a slave as the serial clock pin is always an input. transmitter/receiver : the nm25c040 has separate pins for data transmission (so) and reception (si). msb : the most significant bit is the first bit transmitted and received. chip select : the chip is selected when pin cs is low. when the chip is not selected, data will not be accepted from pin si, and the output pin so is in high impedance. serial op-code : the first byte transmitted after the chip is selected with cs going low contains the op-code that defines the operation to be performed. protocol : when connected to the spi port of a 68hc11 microcontroller, the nm25c040 accepts a clock phase of 0 and a clock polarity of 0. the spi protocol for this device defines the byte transmitted on the si and so data lines for proper chip operation. see figure 4. data is clocked in on the positive sck edge and out on the negative sck edge. hold : the hold pin is used in conjunction with the cs to select the device. once the device is selected and a serial sequence is underway, hold may be forced low to suspend further serial communication with the device without resetting the serial se- quence. note that hold must be brought low while the sck pin is low. the device must remain selected during this sequence. to resume serial communication hold is brought high while the sck pin is low. pins si, sck and so are at a high impedance state during hold. see figure 5. invalid op-code : after an invalid code is received, no data is shifted into the nm25c040, and the so data output pin remains high impedance until a new cs falling edge reinitializes the serial communication. see figure 3. invalid op-code (figure 3) instruction set (table 1) instruction instruction operation name format wren 0000x110 set write enable latch wrdi 0000x100 reset write enable latch rdsr 0000x101 read status register wrsr 0000x001 write status register read 0000a011 read data from memory array write 0000a010 write data to memory array note: a represents msb address bit a8 x = dont care cs si so invalid code ds012401-7
7 www.fairchildsemi.com nm25c040 4096-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description (continued) spi protocol (figure 4) cs sck si so bit 7 bit 6 bit 0 bit 1 bit 7 bit 0 sck hold so t hz t hdn t hds t hdn t hds t lz ds012401-5 ds012401-6 hold timing (figure 5) read sequence (figure 6) read status (figure 7) cs si so read op-code read op-code data n data n + 1 data n + 2 data n + 3 cs si so rdsr op-code sr data msb?sb ds012401-8 ds012401-9
8 www.fairchildsemi.com nm25c040 4096-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description (continued) read sequence: (one or more bytes): reading the memory via the serial spi link requires the following sequence. the cs line is pulled low to select the device. the read op-code (which includes a8) is transmitted on the si line followed by the byte address (a7Ca0) to be read. after this is done, data on the si line becomes dont care. the data (d7Cd0) at the address specified is then shifted out on the so line. if only one byte is to be read, the cs line can be pulled back to the high level. it is possible to continue the read sequence as the byte adress is automatically incremented and data will continue to be shifted out. when the highest address is reached (1ff), the address counter rolls over to lowest address (000) allowing the entire memory to be read in one continuous read cycle. see figure 6. read status register (rdsr) : the read status register (rdsr) instruction provides access to the status register is used to interrogate the ready/busy and write enable status of the chip. two non-volatile status register bits are used to select one of four levels of block write protection. the status register format is shown in table 2. status register format (table 2) bit bit bit bit bit bit bit bit 76543210 1 1 1 1 bp1 bp0 wen rdy status register bit 0 = 0 (rdy) indicates that the device is ready; bit 0 = 1 indicates that a program cycle is in progress. bit 1 = 0 (wen) indicates that the device is not write enabled; bit 1 = 1 indicates that the device is write enabled. non-volatile status register bits 2 and 3 (bp0 and bp1) indicate the level of block write protection selected. the block write protec- tion levels and corresponding status register control bits are shown in table 3. note that if a rdsr instruction is executed during a programming cycle only the rdy bit is valid. all other bits are 1s. see figure 7. block write protection levels (table 3) level status register bits array address bp1 bp0 protected 0 0 0 none 1 0 1 180-1ff 2 1 0 100-1ff 3 1 1 000-1ff write enable (wren) : when v cc is applied to the chip, it powers up in the write disable state. therefore, all programming modes must be preceded by a write enable (wren) instruc- tion. at the completion of a write or wrsr cycle the device is automatically returned to the write disable state. note that a write disable (wrdi) instruction will also return the device to the write disable state. see figure 8. write disable (wrdi) : to protect against accidental data disturbance the write disable (wrdi) instruction disables all programming modes. see figure 9. write disable (figure 9) cs si so wren op-code ds012401-10 write sequence : to program the device, the write pro- tect (wp) pin must be held high and two separate instructions must be executed. the chip must first be write enabled via the write enable instruction and then a write instruction must be executed. moreover, the address of the memory location(s) to be programmed must be outside the protected address field selected by the block write protection level. see table 3. a write command requires the following sequence. the cs line is pulled low to select the device, then the write op-code (which includes a8) is transmitted on the si line followed by the byte address (a7-a0) and the corresponding data (d7-d0) to be written. programming will start after the cs pin is forced back to a high level. note that the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 data bit. see figure 10. the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the write cycle is still in progress and bit 0 = 0 indicates that the write cycle has ended. during the write programming cycle (bit 0 = 1) only the read status regis- ter instruction is enabled. the nm25c040 is capable of a 4 byte page write operation. after receipt of each byte of data the two low order address bits are internally incremented by one. the seven high order bits of the address will remain constant. if the master should transmit more than 4 bytes of data, the address counter will roll over, and the previously loaded data will be reloaded. see figure 11. at the completion of a write cycle the device is automatically returned to the write disable state. if the device is not write enabled, the device will ignore the write instruction and return to the standby state when cs is forced high. a new cs falling edge is required to re-initialize the serial communication. see figure 11. cs si so wrdi op-code ds012401-11 write enable (figure 8)
9 www.fairchildsemi.com nm25c040 4096-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) sck si so cs t din t dis t csn d0 d1 d2 cs si so write op-code byte addr (n) byte addr (n) data (n) data (n+1) data (n+2) data (n+3) hl cs si so wrsr op-code sr data xxxxbp1bp0xx ds012401-12 ds012401-13 ds012401-14 functional description (continued) write sequence (figure 10) start write condition (figure 11) write status register (figure 12) bp0 sck si so cs t din t dis t csn ds012401-15 start wrsr condition (figure 13) write status register (wrsr): the write status register (wrsr) instruction is used to program the non- volatile status register bits 2 and 3 (bp0 and bp1). the write protect (wp) pin must be held high and two separate instruc- tions must be executed. the chip must first be write enabled via the write enable instruction and then a wrsr instruction must be executed. the wrsr command requires the following sequence. the cs line is pulled low to select the device and then the wrsr op-code is transmitted on the si line followed by the data to be pro- grammed. see figure 12. note that the first four bits are dont care bits followed by bp1 and bp0 then two additional dont care bits. programming will start after the cs pin is forced back to a high level. as in the write instruction the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the last dont care bit. see figure 13. the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the wrsr cycle is still in progress and bit 0 = 0 indicates that the wrsr cycle has ended. at the completion of a write cycle the device is automatically returned to the write disable state.
10 www.fairchildsemi.com nm25c040 4096-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) molded small out-line package (m8) package number m08a molded dual-in-line package (n) package number n08e physical dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
11 www.fairchildsemi.com nm25c040 4096-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) 8-pin molded tssop, jedec (mt8) package number mtc08 physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
1 www.fairchildsemi.com nm27c010 1,048,576-bit (128k x 8) high performance cmos eprom nm27c010 1,048,576-bit (128k x 8) high performance cmos eprom general description the nm27c010 is a high performance, 1,048,576-bit electrically programmable uv erasable read only memory. it is organized as 128k-words of 8 bits each. its pin-compatibility with byte-wide jedec eproms enables upgrades through 8 mbit eproms. the dont care feature during read operations allows memory expansions from 1m to 8m bits with no printed circuit board changes. the nm27c010 can directly replace lower density 28-pin eproms by adding an a16 address line and v cc jumper. during the normal read operation pgm and v pp are in a dont care state which allows higher order addresses, such as a17, a18, and a19 to be connected without affecting the normal read operation. this allows memory upgrades to 8m bits without hardware changes. the nm27c010 is also offered in a 32-pin plastic dip with the same upgrade path. the nm27c010 provides microprocessor-based systems exten- sive storage capacity for large portions of operating system and application software. its 70 ns access time provides no-wait-state operation with high-performance cpus. the nm27c010 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. frequently-used software routines are quickly executed from eprom storage, greatly enhancing system utility. block diagram october 1998 the nm27c010 is manufactured using fairchilds advanced cmos amg? eprom technology. the nm27c010 is one member of a high density eprom family which range in densities up to 4 megabit. features n high performance cmos 70 ns access time n fast turn-off for microprocessor compatibility n simplified upgrade path v pp and pgm are dont care during normal read operation n manufacturers identification code n fast programming n jedec standard pin configurations 32-pin pdip package 32-pin plcc package 32-pin cerdip package ds010798-1 ? 1998 fairchild semiconductor corporation nm27c010 ver. 1.1 output enable, chip enable, and program logic y decoder x decoder . . . . . . . . . output buffers 1,048,576-bit cell matrix data outputs o 0 - o 7 v cc gnd v pp oe pgm ce a 0 - a 16 address inputs
2 www.fairchildsemi.com nm27c010 1,048,576-bit (128k x 8) high performance cmos eprom connection diagrams dip pin configurations note: compatible eprom pin configurations are shown in the blocks adjacent to the nm27c010 pins. commercial temperature range (0 c to +70 c) v cc = 5v 10% parameter/order number access time (ns) nm27c010 q, v, n 70 70 nm27c010 q, v, n 90 90 nm27c010 q, v, n 120 120 nm27c010 q, v, n 150 150 extended temperature range (-40 c to +85 c) v cc = 5v 10% parameter/order number access time (ns) nm27c010 qe, ve, ne 70 70 nm27c010 qe, ve, ne 90 90 nm27c010 qe, ve, ne 120 120 nm27c010 qe, ve, ne 150 150 package types: nm27c010 q, n, v xxx q = quartz-windowed ceramic dip package v = plcc package n = plastic dip package ? all packages conform to jedec standard. ? all versions are guaranteed to function at slower speeds. pin names a0Ca16 addresses ce chip enable oe output enable o0Co7 outputs pgm program xx dont care (during read) plcc pin configuration top view ds010798-10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 xx/v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd xx/v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c040 a 19 a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c080 27c020 xx/v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd dip nm27c010 v cc xx/pgm xx a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c256 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c512 27c020 27c040 v cc xx/pgm a 17 a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc a 18 a 17 a 14 a 13 a 8 a 9 a 11 oe a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 27c080 v cc a 18 a 17 a 14 a 13 a 8 a 9 a 11 oe/v pp a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 v cc a 14 a 13 a 8 a 9 a 11 oe/v pp a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 v cc a 14 a 13 a 8 a 9 a 11 oe a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 27c256 27c512 a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 a 12 a 15 a 16 xx/v pp v cc xx/pgm xx o 1 o 2 gnd o 3 o 4 o 5 o 6 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 32 31 30 ds010798-3
3 www.fairchildsemi.com nm27c010 1,048,576-bit (128k x 8) high performance cmos eprom absolute maximum ratings (note 1) storage temperature -65 c to +150 c all input voltages except a9 with respect to ground (note 10) -0.6v to +7v v pp and a9 with respect to ground -0.6v to +14v v cc supply voltage with respect to ground -0.6v to +7v esd protection >2000v all output voltages with respect to ground (note 10) v cc + 1.0v to gnd - 0.6v operating range range temperature v cc tolerance commercial 0 c to +70 c +5v 10% extended -40 c to +85 c +5v 10% dc read characteristics over operating range with v pp = v cc symbol parameter test conditions min max units v il input low level -0.5 0.8 v v ih input high level 2.0 v cc +1 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -2.5 ma 3.5 v i sb1 v cc standby current ce = v cc 0.3v 100 m a (cmos) i sb2 v cc standby current (ttl) ce = v ih 1ma i cc v cc active current ce = oe = v il f = 5 mhz 30 ma i/o = 0 ma i pp v pp supply current v pp = v cc 10 m a v pp v pp read voltage v cc - 0.7 v cc v i li input load current v in = 5.5 or gnd -1 1 m a i lo output leakage current v out = 5.5v or gnd -10 10 m a ac read characteristics over operating range with v pp = v cc symbol parameter 70 90 120 150 units min max min max min max min max t acc address to output delay 70 90 120 150 t ce ce to output delay 70 90 120 150 t oe oe to output delay 35 40 50 50 t df output disable to output 30 35 35 45 ns (note 2) float t oh output hold from (note 2) addresses, ce or oe , 0 0 0 0 whichever occurred first capacitance t a = +25 c, f = 1 mhz (note 2) symbol parameter conditions typ max units c in input capacitance v in = 0v 6 15 pf c out output capacitance v out = 0v 10 15 pf
4 www.fairchildsemi.com nm27c010 1,048,576-bit (128k x 8) high performance cmos eprom ac test conditions output load 1 ttl gate and c l = 100 pf (note 8) input rise and fall times 5 ns input pulse levels 0.45v to 2.4v timing measurement reference level inputs 0.8v and 2v outputs 0.8v and 2v ac waveforms (note 6), (note 7), and (note 9) note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: this parameter is only sampled and is not 100% tested. note 3: oe may be delayed up to t acc - t oe after the falling edge of ce without impacting t acc . note 4: the t df and t cf compare level is determined as follows: high to tri-state ? , the measured v oh1 (dc) - 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 5: tri-state may be attained using oe or ce. note 6: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. note 7: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 8: 1 ttl gate: i ol = 1.6 ma, i oh = -400 m a. c l : 100 pf includes fixture capacitance. note 9: v pp may be connected to v cc except during programming. note 10: inputs and outputs can undershoot to -2.0v for 20 ns max. programming characteristics (note 11), (note 12), (note 13), and (note 14) symbol parameter conditions min typ max units t as address setup time 1 m s t oes oe setup time 1 m s t ces ce setup time oe = v ih 1 m s t ds data setup time 1 m s t vps v pp setup time 1 m s t vcs v cc setup time 1 m s t ah address hold time 0 m s t dh data hold time 1 m s t df output enable to output float delay ce = v il 060ns t pw program pulse width 45 50 105 m s address valid valid output hi-z 2v 0.8v 2v 0.8v 2v 0.8v address output ce oe t ce 2v 0.8v (note 3) (note 3) t df (note 4, 5) (note 4, 5) t oh hi-z t oe t acc t cf ds010798-4
5 www.fairchildsemi.com nm27c010 1,048,576-bit (128k x 8) high performance cmos eprom programming characteristics (note 11), (note 12), (note 13), and (note 14) (continued) symbol parameter conditions min typ max units t oe data valid from oe ce = v il 100 ns i pp v pp supply current during ce = v il 15 ma programming pulse pgm = v il i cc v cc supply current 20 ma t a temperature ambient 20 25 30 c v cc power supply voltage 6.2 6.5 6.75 v v pp programming supply voltage 12.5 12.75 13.0 v t fr input rise, fall time 5 ns v il input low voltage 0.0 0.45 v v ih input high voltage 2.4 4.0 v t in input timing reference voltage 0.8 2.0 v t out output timing reference voltage 0.8 2.0 v programming waveforms (note 13) note 11: fairchilds standard product warranty applies only to devices programmed to specifications described herein. note 12: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 13: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v pp , v cc to gnd to suppress spurious voltage transients which may damage the device. note 14: during power up the pgm pin must be brought high ( 3 v ih ) either coincident with or before power is applied to v pp . t as t ah program program verify address n t df data out valid add n data in stable add n hi-z t ds t dh t vcs t vps t ces t pw t oes t oe 2v 0.8v 2v 0.8v 6.25v 12.75v 0.8v 2v 0.8v 2v 0.8v address data v cc ce pgm oe v pp ds010798-5
6 www.fairchildsemi.com nm27c010 1,048,576-bit (128k x 8) high performance cmos eprom turbo programming algorithm flow chart figure 1. ds010798-6 v cc = 6.5v v pp = 12.75v n = 0 address = first location check all bytes 1st: v cc = v pp = 6.0v 2nd: v cc = v pp = 4.3v program one 50 s pulse increment n address = first location verify byte n = 10? device failed last address ? increment address n = 0 program one 50 s pulse increment address verify byte last address ? pass no fail yes yes pass no fail no yes note: the standard national semiconductor algorithm may also be used but it will have longer programming time.
7 www.fairchildsemi.com nm27c010 1,048,576-bit (128k x 8) high performance cmos eprom functional description device operation the six modes of operation of the eprom are listed in table 1. it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and v pp . the v pp power supply must be at 12.75v during the three programming modes, and must be at 5v in the other three modes. the v cc power supply must be at 6.5v during the three programming modes, and at 5v in the other three modes. read mode the eprom has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that the addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs t oe after the falling edge of oe , assuming that ce has been low and addresses have been stable for at least t acc C t oe . standby mode the eprom has a standby mode which reduces the active power dissipation by over 99%, from 165 mw to 0.55 mw. the eprom is placed in the standby mode by applying a cmos high signal to the ce input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output disable the eprom is placed in output disable by applying a ttl high signal to the oe input. when in output disable all circuitry is enabled, except the outputs are in a high impedance state (tri- state). output or-tying because the eprom is usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ce be decoded and used as the primary device selecting function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on the v pp or a9 pin will damage the eprom. initially, and after each erasure, all bits of the eprom are in the 1s state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be pro- grammed, both 1s and 0s can be presented in the data word. the only way to change a 0 to a 1 is by ultraviolet light erasure. the eprom is in the programming mode when the v pp power supply is at 12.75v and oe is at v ih . it is required that at least a 0.1 m f capacitor be placed across v pp , v cc to ground to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 8 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. when the address and data are stable, an active low, ttl program pulse is applied to the pgm input. a program pulse must be applied at each address location to be programmed. the eprom is programmed with the turbo programming algorithm shown in figure 1. each address is programmed with a series of 50 m s pulses until it verifies good, up to a maximum of 10 pulses. most memory cells will program with a single 50 m s pulse. the eprom must not be programmed with a dc signal applied to the pgm input. programming multiple eprom in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. like inputs of the parallel eprom may be con- nected together when they are programmed with the same data. a low level ttl pulse applied to the pgm input programs the paralleled eprom. program inhibit programming multiple eproms in parallel with different data is also easily accomplished. except for ce all like inputs (including oe and pgm) of the parallel eprom may be common. a ttl low level program pulse applied to an eproms pgm input with ce at v il and v pp at 12.75v will program that eprom. a ttl high level ce input inhibits the other eproms from being programmed. program verify a verify should be performed on the programmed bits to determine whether they were correctly programmed. the verify may be performed with v pp at 12.75v. v pp must be at v cc , except during programming and program verify. after programming opaque labels should be placed over the eprom window to prevent unintentional erasure. covering the window will also prevent temporary functional failure due to the generation of photo currents. manufacturers identification code the eprom has a manufacturers indentification code to aid in programming. when the device is inserted in an eprom pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. the manufacturers identification code, shown in table 2, specifi- cally identifies the manufacturer and device type. the code for the nm27c010 is 8f86, where 8f designates that it is made by fairchild semiconductor, and 86 designates a 1 megabit (128k x 8) part. the code is accessed by applying 12v 0.5v to address pin a9. addresses a1Ca8, a10Ca16, and all control pins are held at v il . address pin a0 is held at v il for the manufacturers code, and held at v ih for the device code. the code is read on the eight data pins, o0C07. proper code access is only guaranteed at 25 c 5 c.
8 www.fairchildsemi.com nm27c010 1,048,576-bit (128k x 8) high performance cmos eprom functional description (continued) erasure characteristics the erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms (?). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000? C 4000? range. the recommended erasure procedure for the eprom is expo- sure to short wave ultraviolet light which has a wavelength of 2537?. the integrated dose (i.e., uv intensity x exposure time) for erasure should be a minimum of 15w-sec/cm 2 . the eprom should be placed within 1 inch of the lamp tubes during erasure. some lamps have a filter on their tubes which should be removed before erasure. an erasure system should be calibrated periodically. the distance from lamp to device should be maintained at one inch. the erasure time increases as the square of the distance from the lamp. (if distance is doubled the erasure time increases by factor of 4). lamps lose intensity as they age. when a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. incomplete erasure will cause symptoms that can be misleading. program- mers, components and even system designs have been errone- ously suspected when incomplete erasure was the problem. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc , has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. the associated v cc transient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces. mode selection the modes of operation of the nm27c010 are listed in table 1. a single 5v power supply is required in the read mode. all inputs are ttl levels except for v pp and a9 for device signature. table 1. modes selection pins ce oe pgm v pp v cc outputs mode read v il v il x x 5.0v d out (note 15) output disable x v ih x x 5.0v high z standby v ih x x x 5.0v high z programming v il v ih v il 12.75v 6.25v d in program verify v il v il v ih 12.75v 6.25v d out program inhibit v ih x x 12.75v 6.25v high z note 15: x can be v il or v ih . table 2. manufacturers identification code pins a0 a9 o7 o6 o5 o4 o3 o2 o1 o0 hex (12) (26) (21) (20) (19) (18) (17) (15) (14) (13) data manufacturer code v il 12v 1 0 0 0 1 1 1 1 8f device code v ih 12v 1 0 0 0 0 1 1 0 86
9 www.fairchildsemi.com nm27c010 1,048,576-bit (128k x 8) high performance cmos eprom 32-lead eprom ceramic dual-in-line package (q) order number nm27c010qxxx package number j32aq 32-lead molded dual-in-line package (n) order number nm27c010nxxx package number 1.660 (42.16) 32 1 17 16 0.025 (0.64) r 0.030-0.055 (0.76 - 1.40) typ uv window size and configuration determined by device size 0.175 (4.45) max 0.060-0.100 (1.52 - 2.54) typ 0.050-0.060 (1.27 - 1.52) typ 0.015-0.021 (0.38 - 0.53) typ 86 -94 typ glass sealant 0.150 (3.81) 0.015 -0.060 (0.25 - 1.52) typ 0.10 (2.54) max 0.090-0.110 (2.29 - 2.79) typ 0.005 (0.127) max typ 0.125 (3.18) 0.585 (14.86) max max r min typ min typ min typ 0.225 (5.72) 0.590-0.620 (15.03 - 15.79) 90 - 100 typ 0.685 (17.40) +0.025 (0.64) -0.060 (-1.523) 0.008-0.012 (0.20 - 0.30) typ 1.64 ?1.66 (41.66 ?42.164) 32 1 17 16 0.062 (1.575) rad pin no. 1 ident 0.580 (14.73) min 0.600 ?0.620 (15.240 ?15.748) 0.145 ?0.210 (3.683 ?5.334) 0.040 - 0.090 (1.016 ?2.286) 0.050 (1.270) typ typ 0.125 ?0.165 (3.175 ?4.191) 0.018 0.003 (0.457 0.078) 0.035 ?0.07 (0.889 ?1.778) 86 - 94 typ 0.120 ?0.150 (3.048 ?3.81) 0.015 (0.381) 0.100 0.010 (2.540 0.254) 90 ?05 0.008 - 0.015 (0.203 ?0.381) 0.490 ?0.550 (12.446 ?13.97) physical dimensions inches (millimeters) unless otherwise noted
10 www.fairchildsemi.com nm27c010 1,048,576-bit (128k x 8) high performance cmos eprom physical dimensions inches (millimeters) unless otherwise noted 32-lead plcc package order number nm27c010vxxx package number va32a 0.007[0.18] a s s f-g 0.007[0.18] b s d-e 0.449-0.453 [11.40-11.51] s 0.045 [1.143] 0.000-0.010 [0.00-0.25] polished optional 0.585-0.595 [14.86-15.11] 0.549-0.553 [13.94-14.05] -b- -f- -e- -g- 0.050 21 29 30 1 4 20 14 13 5 -d- 0.007[0.18] b s d-e s 0.002[0.05] b s -a- 0.485-0.495 [12.32-12.57] 0.007[0.18] a s s f-g a 0.002[0.05] s 0.007[0.18] h s s d-e, f-g 0.010[0.25] b a s d-e, f-g 0.118-0.129 [3.00-3.28] l b b 45 x 0.042-0.048 [1.07-1.22] 0.026-0.032 [0.66-0.81] typ 0.0100 [0.254] 0.030-0.040 [0.76-1.02] r 0.005 [0.13] max 0.020 [0.51] 0.045 [1.14] detail a typical rotated 90 0.027-0.033 [0.69-0.84] 0.025 [0.64] min 0.025 [0.64] min 0.031-0.037 [0.79-0.94] 0.053-0.059 [1.65-1.80] 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64] 0.065-0.071 [1.65-1.80] 0.021-0.027 [0.53-0.69] section b-b typical s 0.007[0.18] c m s d-e, f-g 0.015[0.38] c d-e, f-g 0.490-0530 [12.45-13.46] 0.078-0.095 [1.98-2.41] 0.013-0.021 [0.33-0.53] 0.004[0.10] 0.123-0.140 [3.12-3.56] see detail a -j- -c- 0.400 [10.16] ( ) typ 0.541-0.545 [13.74-13-84] 0.023-0.029 [0.58-0.74] 0.106-0.112 [2.69-2.84] 60 0.015 [0.38] base plane -h- min typ s fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom general description the nm27c020 is a high speed 2 megabit cmos uv-eprom manufactured on fairchilds advanced sub-micron technology. utilizing the amg architecture, this advanced cmos process delivers high speeds while consuming low power. the nm27c020 provides microprocessor-based systems exten- sive storage capacity for large portions of operating systems and application software. its 100ns access time provides no-wait-state operation with high-performance cpus. the nm27c020 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. frequently- used software routines are quickly executed from eprom stor- age, greatly enhancing system utility. the nm27c020 is manufactured using fairchilds advanced cmos amg eprom technology, and is one member of a high density fairchild eprom series family which range in densities up to 4mb. block diagram july 1998 features n high performance cmos 100 ns access time n simplified upgrade path v pp and pgm are dont care during normal read operation n manufacturers identification code n jedec standard pin configuration 32-pin cerdip package 32-pin plcc package 32-pin pdip package ? 1998 fairchild semiconductor corporation output enable, chip enable, and program logic y decoder x decoder . . . . . . . . . output buffers 2,097,152-bit cell matrix data outputs o 0 - o 7 v cc gnd v pp oe pgm ce a 0 - a 17 address inputs ds010835-1
2 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom connection diagrams commercial temperature range (0 c to +70 c) v cc = 5v 10% parameter/order number access time (ns) nm27c020 q, v, n 100 100 nm27c020 q, v, n 120 120 nm27c020 q, v, n 150 150 all versions are guaranteed to function at slower speeds. extended temperature range (-40 c to +85 c) v cc = 5v 10% parameter/order number access time (ns) nm27c020 qe, ve, te, ne 120 120 nm27c020 qe, ve, te, ne 150 150 plcc pin configuration top view pin names a0 Ca17 addresses ce chip enable oe output enable o0 Co7 outputs pgm program xx dont care (during read) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 xx/v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c512 27c256 v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c256 27c512 v cc xx/pgm a 17 a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc a 14 a 13 a 8 a 9 a 11 oe a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 v cc a 14 a 13 a 8 a 9 a 11 oe/v pp a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 xx/v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c040 xx/v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c010 a19 a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c080 27c040 27c080 v cc a 18 a 17 a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc a 18 a 17 a 14 a 13 a 8 a 9 a 11 oe/v pp a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 27c010 v cc xx/pgm xx a 14 a 13 a 8 a 9 a 11 oe a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 note: compatible eprom pin configurations are shown in the blocks adjacent to the nm27c020 pins. a14 a13 a8 a9 a11 oe a10 ce o7 a7 a6 a5 a4 a3 a2 a1 a0 o0 a12 a15 a16 vpp vcc pgm a17 o1 o2 gnd o3 o4 o5 o6 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 32 31 30 ds010835-10 ds010835-3
3 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom access time 100 = 100 ns 120 = 120 ns 150 = 150 ns operating temp blank = commercial temp. e = extended temp. packaging q = ceramic dip v = plcc n = pdip memory size 020 = 2 mbit fairchild memory eprom cmos q 150 e nm 27 c 020 connection diagrams (continued) ordering information ds010835-9
4 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom absolute maximum ratings (note 1) storage temperature -65 c to +125 c all input voltage except a9 with respect to ground (note 13) -0.6v to +7v v pp and a9 with respect to ground -0.6v to +14v v cc supply voltage with respect to ground -0.6v to +7v esd protection >2000v all output voltages with respect to ground (note 13) v cc + 10v to gnd -0.6v operating range range temperature v cc tolerance commercial 0 c to +70 c +5v 10 industrial -40 c to +85 c +5v 10% dc read characteristics over operating range with v pp = v cc symbol parameter test conditions min max units v il input low level -0.5 0.8 v v ih input high level 2.0 v cc +1 v v ol output low voltage i ol = 2.1 ma -0.4 v v oh output high voltage i oh = -400 m a 3.5 v i sb1 (note 4) v cc standby current (cmos) ce = v cc 0.3v 100 m a i sb2 v cc standby current (ttl) ce = v ih 1ma i cc (note 2) v cc active current ce, oe = v il commercial 30 i/o = 0 ma, f = 5 mhz industrial 30 ma inputs = v ih or v il i pp v pp supply current v pp = v cc 10 m a vpp v pp read voltage vcc - 0.4 v cc v i li input load current v in = 5.5 or gnd -1 1 m a i lo output leakage current v out = 5.5v or gnd -10 10 m a ac read characteristics over operating range with v pp = v cc symbol parameter 100 120 150 units min max min max min max t acc address to output delay 100 120 150 ns t ce ce to output delay 100 120 150 ns t oe oe to output delay 40 45 50 ns t df (note 3) output disable to output float 40 45 50 ns t oh output hold from addresses, ce 0 0 0 ns or oe , whichever occurred first note 1: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. note 2: the supply current is the sum of i cc and i pp . the maximum current value is with outputs o0 to o7 unloaded. note 3: this parameter is only sampled and is not 100% tested. output float is defined as the point where data is no longer driven-see timing diagram. note 4: cmos inputs: v il = gnd 10.3v, v ih = v cc 10.3v.
5 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom 40 30 20 10 0 012 345678 31 30 29 28 27 26 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 ac read characteristics (continued) i cc vs. frequency frequency (mhz) i cc vs. temperature temperature (ic) ds010835-7 ds010835-8
6 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom capacitance t a = +25 c, f = 1 mhz (note 5) symbol parameter conditions typ max units c in input capacitance v in = 0v 9 15 pf c out output capacitance v out = 0v 12 15 pf ac test conditions output load 1 ttl gate and c l = 100 pf (note 11) input rise and fall times 5 ns input pulse levels 0.45v to 2.4v timing measurement reference level (note 13) inputs 0.8v and 2v outputs 0.8v and 2v ac waveforms (notes 9, 10, 12) note 5: this parameter is only sampled and is not 100% tested. note 6: oe may be delayed up to t acc - t oe after the falling edge of ce without impacting t acc . note 7: the t df and t cf compare level is determined as follows: high to tri-state ? , the measured v oh1 (dc) - 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 8: tri-state may be attained using oe or ce . note 9: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.1 mf ceram ic capacitor be used on every device between v cc and gnd. note 10: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 11: 1 ttl gate: i ol = 1.6 ma, i oh = -400 m a. c l : 100 pf includes fixture capacitance. note 12: v pp may be connected to v cc except during programming. note 13: inputs and outputs can undershoot to -2.0v for 20 ns max. address valid valid output hi-z 2v 0.8v 2v 0.8v 2v 0.8v address output ce oe t ce 2v 0.8v (note 6) (note 6) t df (note 7, 8) (note 7, 8) t oh hi-z t oe acc t cf t ds010835-4
7 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom programming characteristics (notes 14, 15, 16, 17) symbol parameter condition min typ max units t as address setup time 1 m s t oes oe setup time 1 m s t ces ce setup time oe = v ih 1 m s t ds data setup time 1 m s t vps v pp setup time 1 m s t vcs v cc setup time 1 m s t ah address hold time 0 m s t dh data hold time 1 m s t df output enable to output ce = v il 060ns float delay t pw program pulse width 45 50 105 m s t oe data valid from oe ce = v il 100 ns i pp v pp supply current during ce = v il 15 ma programming pulse pgm = v il i cc v cc supply current 20 ma t a temperature ambient 20 25 30 c v cc power supply voltage 6.25 6.5 6.75 v v pp programming supply voltage 12.5 12.75 13.0 v t fr input rise, fall time 5 ns v il input low voltage 0.0 0.45 v v ih input high voltage 2.4 4.0 v t in input timing reference voltage 0.8 2.0 v t out output timing reference voltage 0.8 2.0 v note 14: fairchilds standard product warranty applies only to devices programmed to specifications described herein. note 15: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 16: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v pp , v cc to gnd to suppress spurious voltage transients which may damage the device. note 17: during power up the pgm pin must be brought high ( 3 v ih ) either coincident with or before power is applied to v pp .
8 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom t as t ah program program verify address n t df data out valid add n data in stable add n hi-z t ds t dh t vcs t vps t ces t pw t oes t oe 2v 0.8v 2v 0.8v 6.25v 12.75v 0.8v 2v 0.8v 2v 0.8v address data v cc ce pgm oe v pp programming waveforms (note 16) ds010835-5
9 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom turbo programming algorithm flow chart v cc = 6.5v v pp = 12.75v n = 0 address = first location check all bytes 1st: v cc = v pp = 6.0v 2nd: v cc = v pp = 4.3v program one 50 s pulse increment n address = first location verify byte n = 10? device failed last address ? increment address n = 0 program one 50 s pulse increment address verify byte last address ? pass no fail yes yes pass no fail no yes ds010835-6 figure 1. note: the standard national semiconductor algorithm may also be used but it will have longer programming time.
10 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom functional description device operation the six modes of operation of the device are listed in table 1. it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and v pp . the v pp power supply must be at 12.75v during the three programming modes, and must be at 5v in the other three modes. the v cc power supply must be at 6.5v during the three programming modes, and at 5v in the other three modes. read mode the part has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that the addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs t oe after the falling edge of oe, assuming that ce has been low and addresses have been stable for at least t acc Ct oe . standby mode the eprom has a standby mode which reduces the active power dissipation by over 99%, from 220 mw to 0.55 mw. the eprom is placed in the standby mode by applying a cmos high signal to the ce input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output or-tying because the part is usually used in larger memory arrays, fair- child has provided a 2-line control function that accommodates this use of multiple memory connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ce be decoded and used as the primary device selecting function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all selected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on pin 1 (v pp ) will damage the device. initially, and after each erasure, all bits of the device are in the 1s state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be programmed, both 1s and 0s can be presented in the data word. the only way to change a 0 to a 1 is by ultraviolet light erasure. the part is in the programming mode when the v pp power supply is at 12.75v and oe is at v ih . it is required that at least a 0.1 m f capacitor be placed across v pp , v cc to ground to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 8 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. when the address and data are stable, an active low, ttl program pulse is applied to the pgm input. a program pulse must be applied at each address location to be programmed. the eprom is programmed with the turbo programming algorithm shown in figure 1. each address is programmed with a series of 50 m s pulses until it verifies good, up to a maximum of 10 pulses. most memory cells will program with a single 50 m s pulse. (the standard national semiconductor algorithm may also be used but it will have longer programming time.) the eprom must not be pro- grammed with a dc signal applied to the pgm input. program- ming multiple eprom in parallel with the same data can be easily accomplished due to the simplicity of the programming require- ments. like inputs of the parallel eprom may be connected together when they are programmed with the same data. a low level ttl pulse applied to the pgm input programs the paralleled eprom. mode selection the modes of operation of the nm27c020 are listed in table 1. a single 5v power supply is required in the read mode. all inputs are ttl levels except for v pp and a9 for device signature. table 1. modes selection pins ce oe pgm v pp v cc outputs mode read v il v il x x 5.0v d out (note 18) output disable x v ih x x 5.0v h igh z standby v ih x x x 5.0v high z programming v il v ih v il 12.75v 6.25v d in program verify v il v il v ih 12.75v 6.25v d out program inhibit v ih x x 12.75v 6.25v high z note 18: x can be v il or v ih .
11 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom functional description (continued) program inhibit programming multiple eproms in parallel with different data is also easily accomplished. except for ce all like inputs (including oe) of the parallel eprom may be common. a ttl low level program pulse applied to an eproms ce with v pp at 12.75v will program that eprom. a ttl high level ce input inhibits the other eproms from being programmed. program verify a verify should be performed on the programmed bits to determine whether they were correctly programmed. the verify may be performed with v pp at 12.75v. v pp must be at v cc , except during programming and program verify. manufacturers identification code the part has a manufacturers indentification code to aid in programming. when the device is inserted in an eprom pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. the manufacturers identification code, shown in table 2, specifi- cally identifies the manufacturer and device type. the code for the nm27c020 is 8f8e, where 8f designates that it is made by fairchild semiconductor, and 8e designates a 2 megabit byte- wide part. the code is accessed by applying 12v 0.5v to address pin a9. addresses and control pins are held at v il , except a0. address pin a0 is held at v il for the manufacturers code, and held at v ih for the device code. the code is read on the eight data pins, o0 C07 . proper code access is only guaranteed at 25 c 5 c. erasure characteristics the erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms (?). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000? C 4000? range. after programming, opaque labels should be placed over the eprom window to prevent uninten- tional erasure. covering the window will also prevent temporary functional failure due to the generation of photo currents. the recommended erasure procedure for the eprom is expo- sure to short wave ultraviolet light which has a wavelength of 2537?. the integrated dose (i.e., uv intensity x exposure time) for erasure should be a minimum of 15w-sec/cm 2 . the device should be placed within 1 inch of the lamp tubes during erasure. the device should be placed within 1 inch of the lamp tubes during erasure. an erasure system should be calibrated periodically. the distance from lamp to device should be maintained at one inch. the erasure time increases as the square of the distance from the lamp. (if distance is doubled the erasure time increases by factor of 4). lamps lose intensity as they age. when a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. incomplete erasure will cause symptoms that can be misleading. program- mers, components and even system designs have been errone- ously suspected when incomplete erasure was the problem. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc , has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. the associated v cc transient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces. table 2. manufacturers identification code pins a0 a9 o7 o6 o5 o4 o3 o2 o1 o0 hex (12) (26) (21) (19) (18) (17) (16) (15) (14) (13) data manufacturer code v il 12v100011118f device code v ih 12v0000011107
12 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom 32-lead eprom ceramic dual-in-line package (q) order number nm27c020q package number j32aq physical dimensions inches (millimeters) unless otherwise noted 1.660 max 32 1 17 16 r 0.025 r 0.030-0.055 typ uv window size and configuration determined by device size 0.590-0.620 0.175 max 0.060-0.100 typ 0.050-0.060 typ 0.015-0.021 typ 86?94 typ 0.150 min typ 0.015 -0.060 typ 0.10 max 0.090-0.110 typ 0.005 min typ 0.225 max typ 0.125 min typ 90?- 100 typ 0.685 +0.025 -0.060 0.008-0.012 typ 0.585 max
13 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom 32-lead pdip package order number nm27c020n physical dimensions inches (millimeters) unless otherwise noted 1.64 ?1.66 (41.66 ?42.164) 32 1 17 16 0.062 (1.575) rad pin no. 1 ident 0.580 (14.73) min 0.600 ?0.620 (15.240 ?15.748) 0.145 ?0.210 (3.683 ?5.334) 0.040 - 0.090 (1.016 ?2.286) 0.050 (1.270) typ typ 0.125 ?0.165 (3.175 ?4.191) 0.018 0.003 (0.457 0.078) 0.035 ?0.07 (0.889 ?1.778) 86 - 94 typ 0.120 ?0.150 (3.048 ?3.81) 0.015 (0.381) 0.100 0.010 (2.540 0.254) 90 ?05 0.008 - 0.015 (0.203 ?0.381) 0.490 ?0.550 (12.446 ?13.97)
14 www.fairchildsemi.com nm27c020 2,097,152-bit (256k x 8) uv erasable cmos eprom physical dimensions inches (millimeters) unless otherwise noted 32-lead plcc package order number nm27c020v package number va32a 0.007[0.18] a s s f-g 0.007[0.18] b s d-e 0.449-0.453 [11.40-11.51] s 0.045 [1.143] 0.000-0.010 [0.00-0.25] polished optional 0.585-0.595 [14.86-15.11] 0.549-0.553 [13.94-14.05] -b- -f- -e- -g- 0.050 21 29 30 1 4 20 14 13 5 -d- 0.007[0.18] b s d-e s 0.002[0.05] b s -a- 0.485-0.495 [12.32-12.57] 0.007[0.18] a s s f-g a 0.002[0.05] s s 0.007[0.18] c m s d-e, f-g 0.015[0.38] c d-e, f-g 0.490-0530 [12.45-13.46] 0.078-0.095 [1.98-2.41] 0.013-0.021 [0.33-0.53] 0.004[0.10] 0.123-0.140 [3.12-3.56] see detail a -j- -c- 0.400 [10.16] ( ) typ 0.541-0.545 [13.74-13-84] 0.023-0.029 [0.58-0.74] 0.106-0.112 [2.69-2.84] 60 0.015 [0.38] base plane -h- min typ s 0.027-0.033 [0.69-0.84] 0.025 [0.64] min 0.025 [0.64] min 0.031-0.037 [0.79-0.94] 0.053-0.059 [1.65-1.80] 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64] 0.065-0.071 [1.65-1.80] 0.021-0.027 [0.53-0.69] section b-b typical 0.007[0.18] h s s d-e, f-g 0.010[0.25] b a s d-e, f-g 0.118-0.129 [3.00-3.28] l b b 45? 0.042-0.048 [1.07-1.22] 0.026-0.032 [0.66-0.81] typ 0.0100 [0.254] 0.030-0.040 [0.76-1.02] r 0.005 [0.13] max 0.020 [0.51] 0.045 [1.14] detail a typical rotated 90 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm27c040 rev. c.1 nm27c040 4,194,304-bit (512k x 8) high performance cmos eprom nm27c040 4,194,304-bit (512k x 8) high performance cmos eprom general description the nm27c040 is a high performance, 4,194,304-bit electrically programmable uv erasable read only memory. it is organized as 512k words of 8 bits each. its pin-compatibility with byte-wide jedec eproms enables upgrades through 8 mbit eproms. the dont care feature on v pp during read operations allows memory expansions from 1m to 8 mbits with no printed circuit board changes. the nm27c040 provides microprocessor-based systems exten- sive storage capacity for large portions of operating system and application software. its 120ns access time provides high speed operation with high-performance cpus. the nm27c040 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. frequently used software routines are quickly executed from eprom storage, greatly enhancing system utility. the nm27c040 is manufactured using fairchilds advanced cmos amg? eprom technology. block diagram february 1999 features n high performance cmos 120, 150ns access time* n simplified upgrade path v pp is a dont care during normal read operation n manufacturers identification code n jedec standard pin configuration 32-pin pdip 32-pin plcc 32-pin cerdip ds010836-1 amg? is a trademark of wsi, inc. ? 1999 fairchild semiconductor corporation output enable, chip enable, and program logic y decoder x decoder . . . . . . . . . output buffers y gating 4,194,304-bit cell matrix data outputs o 0 - o 7 v cc gnd v pp oe ce/pgm a 0 - a 18 address inputs *note: new revision meets 70ns. please check with factory for availability.
2 www.fairchildsemi.com nm27c040 rev. c.1 nm27c040 4,194,304-bit (512k x 8) high performance cmos eprom connection diagrams note: compatible eprom pin configurations are shown in the blocks adjacent to the nm27c040 pin. commercial temperature range (0 c to +70 c) v cc = 5v 10% parameter/order number access time (ns) nm27c040 q, n, v 120 120 nm27c040 q, n, v 150 150 extended temperature range (-40 c to +85 c) v cc = 5v 10% parameter/order number access time (ns) nm27c040 qe, ne, ve 150 150 package types: nm27c040 q, n,v xxx q = quartz-windowed ceramic dip n = plastic dip v = plcc ? all packages conform to the jedec standard. ? all versions are guaranteed to function for slower speeds. pin names a0Ca18 addresses ce/pgm chip enable/program oe output enable o0Co7 outputs xx dont care (during read) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 xx/v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd xx/v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd a 19 a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c020 27c010 xx/v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c010 27c020 nm27c040 v cc a 18 a 17 a 14 a 13 a 8 a 9 a 11 oe a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 v cc xx/pgm nc a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc xx/pgm a 17 a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 27c080 v cc a 18 a 17 a 14 a 13 a 8 a 9 a 11 oe/v pp a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 27c080 ds010836-2
3 www.fairchildsemi.com nm27c040 rev. c.1 nm27c040 4,194,304-bit (512k x 8) high performance cmos eprom absolute maximum ratings (note 1) storage temperature -65 c to +150 c all input voltages except a9 with respect to ground -0.6v to +7v v pp and a9 with respect to ground -0.6v to +14v v cc supply voltage with respect to ground -0.6v to +7v esd protection >2000v all output voltages with respect to ground v cc +1.0v to gnd - 0.6v operating range range temperature v cc tolerance commercial 0 c to +70 c +5v 10% industrial -40 c to +85 c +5v 10% read operation dc electrical characteristics over operating range with v pp = v cc symbol parameter test conditions min max units v il input low level -0.5 0.8 v v ih input high level 2.0 v cc +1 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -2.5 ma 3.5 v i sb1 v cc standby current (cmos) ce = v cc 0.3v 100 m a i sb2 v cc standby current ce = v ih 1ma i cc v cc active current ce = oe = v il , f=5 mhz 30 ma i/o = 0 ma i pp v pp supply current v pp = v cc 10 m a v pp v pp read voltage v cc - 0.4 v cc v i li input load current v in = 5.5v or gnd -1 1 m a i lo output leakage current v out = 5.5v or gnd -10 10 m a ac electrical characteristics over operating range with v pp = v cc symbol parameter 120 150 units min max min max t acc address to output delay 120 150 t ce ce to output delay 120 150 t oe oe to output delay 50 50 t df output disable to 45 55 ns (note 2) output float t oh output hold from addresses ce or oe , 0 0 (note 2) whichever occurred first capacitance t a = +25 c, f = 1 mhz (note 2) symbol parameter conditions typ max units c in input capacitance v in = 0v 9 15 pf c out output capacitance v out = 0v 12 15 pf
4 www.fairchildsemi.com nm27c040 rev. c.1 nm27c040 4,194,304-bit (512k x 8) high performance cmos eprom ac test conditions output load 1 ttl gate and c l = 100 pf (note 8) input rise and fall times 5 ns input pulse levels 0.45v to 2.4v timing measurement reference level (note 10) inputs 0.8v and 2v outputs` 0.8v and 2v ac waveforms (notes 6, 7, 9) note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: this parameter is only sampled and is not 100% tested. note 3: oe may be delayed up to t acc - t oe after the falling edge of ce without impacting t acc . note 4: the t df and t cf compare level is determined as follows: high to tri-state ? , the measured v oh1 (dc) - 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 5: tri-state may be attained using oe or ce . note 6: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. note 7: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 8: 1 ttl gate: i ol = 1.6 ma, i oh = -400 m a. c l : 100 pf includes fixture capacitance. note 9: v pp may be connected to v cc except during programming. note 10: inputs and outputs can undershoot to -2.0v for 20 ns max. addresses valid valid output hi-z 2v 0.8v 2v 0.8v 2v 0.8v addresses output ce oe t ce 2v 0.8v (note 3) (note 3) t df (note 4, 5) (note 4, 5) t oh hi-z t oe acc t cf t ds010836-4
5 www.fairchildsemi.com nm27c040 rev. c.1 nm27c040 4,194,304-bit (512k x 8) high performance cmos eprom programming waveform (note 13) programming characteristics (notes 11, 12, 13, 14) symbol parameter conditions min typ max units t as address setup time 1 m s t oes oe setup time 1 m s t ds data setup time 1 m s t vps v pp setup time 1 m s t vcs v cc setup time 1 m s t ah address hold time 0 m s t dh data hold time 1 m s t df output enable to output float delay ce/pgm = x 0 60 ns t pw program pulse width 45 50 105 m s t oe data valid from oe ce/pgm = x 100 ns i pp v pp supply current during ce/pgm = v il 30 ma programming pulse i cc v cc supply current 30 ma t a temperature ambient 20 25 30 c v cc power supply voltage 6.25 6.5 6.75 v v pp programming supply voltage 12.5 12.75 13.0 v t fr input rise, fall time 5 ns v il input low voltage -0.1 0.0 0.45 v v ih input high voltage 2.4 4.0 v t in input timing reference voltage 0.8 2.0 v t out output timing reference voltage 0.8 2.0 v note 11: fairchilds standard product warranty applies only to devices programmed to specifications described herein. note 12: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 13: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v pp , v cc to gnd to suppress spurious voltage transients which may damage the device. note 14: during power up the ce/pgm pin must be brought high ( 3 v ih ) either coincident with or before power is applied to v pp . t as t ah program program verify address n t df data out valid add n data in stable add n hi-z t ds t dh t vcs t vps t pw t oes t oe 2v 0.8v 2v 0.8v 6.25v 12.75v 2v 0.8v 2v 0.8v addresses data v pp ce/pgm oe v cc ds010836-5
6 www.fairchildsemi.com nm27c040 rev. c.1 nm27c040 4,194,304-bit (512k x 8) high performance cmos eprom turbo programming algorithm flow chart figure 1. v cc = 6.5v v pp = 12.75v n = 0 address = first location check all bytes 1st: v cc = v pp = 6.0v 2nd: v cc = v pp = 4.3v program one 50 s pulse increment n address = first location verify byte n = 10? device failed last address ? increment address n = 0 program one 50 s pulse increment address verify byte last address ? pass no fail yes yes pass no fail no yes ds010836-6 note: the standard national semiconductor algorithm may also be used with it will have longer programming time.
7 www.fairchildsemi.com nm27c040 rev. c.1 nm27c040 4,194,304-bit (512k x 8) high performance cmos eprom functional description device operation the six modes of operation of the eprom are listed in table 1. it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and v pp . the v pp power supply must be at 12.75v during the three programming modes, and must be at 5v in the other three modes. the v cc power supply must be at 6.25v during the three programming modes, and at 5v in the other three modes. read mode the eprom has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce/pgm) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs toe after the falling edge of oe, assuming that ce/pgm has been low and addresses have been stable for at least t acc -t oe . standby mode the eprom has a standby mode which reduces the active power dissipation by over 99%, from of 65 mw to 0.55 mw. the eprom is placed in the standby mode by applying a cmos high signal to the ce/pgm input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output disable the eprom is placed in output disable by applying a ttl high signal to the oe input. when in output disable all circuitry is enabled, except the outputs are in a high impedance state (tri- state). output or-typing because the eprom is usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ce/pgm be decoded and used as the primary device select- ing function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on pin 1 (v pp ) will damage the eprom. initially, and after each erasure, all bits of the eprom are in the 1s state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be pro- grammed, both 1s and 0s can be presented in the data word. the only way to change a 0 to a 1 is by ultraviolet light erasure. the eprom is in the programming mode when the v pp power supply is at 12.75v and oe is at v ih . it is required that at least a 0.1 m f capacitor be placed across v pp , v cc to ground to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 8 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. when the address and data are stable, an active low, ttl program pulse is applied to the ce/pgm input. a program pulse must be applied at each address location to be programmed. the eprom is programmed with the turbo programming algorithm shown in figure 1. each address is programmed with a series of 50 m s pulses until it verifies good, up to a maximum of 10 pulses. most memory cells will program with a single 50 m s pulse. (the standard national semiconductor algorithm may also be used but it will have longer programming time.) the eprom must not be programmed with a dc signal applied to the ce/pgm input. programming multiple eprom in parallel with the same data can be easily accomplished due to the simplicity of the pro-gramming requirements. like inputs of the parallel eprom may be con- nected together when they are programmed with the same data. a low level ttl pulse applied to the ce/pgm input programs the paralleled eprom. program inhibit programming multiple eproms in parallel with different data is also easily accomplished. except for ce/pgm all like in-puts (including oe) of the parallel eproms may be com-mon. a ttl low level program pulse applied to an eproms ce/pgm input with v pp at 12.75v will program that eprom. a ttl high level ce/ pgm input inhibits the other eproms from being programmed. program verify a verify should be performed on the programmed bits to determine whether they were correctly programmed. the verify may be performed with v pp at 12.75v. v pp must be at v cc , except during programming and program verify. after programming opaque labels should be placed over the eprom window to prevent unintentional erasure. covering the window will also prevent temporary functional failure due to the generation of photo currents. manufacturers identification code the eprom has a manufacturers identification code to aid in programming. when the device is inserted in an eprom pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. the manufacturers identification code, shown in table 2, specifi- cally identifies the manufacturer and device type. the code for nm27c040 is 8f08, where 8f designates that it is made by fairchild semiconductor, and 08 designates a 4 megabit (512k x 8) part. the code is accessed by applying 12v 0.5v to address pin a9. addresses a1Ca8, a10Ca18, and all control pins are held at v il . address pin a0 is held at v il for the manufacturers code, and held at v ih for the device code. the code is read on the eight data pins, o0 Co7 . proper code access is only guaranteed at 25 c 5 c.
8 www.fairchildsemi.com nm27c040 rev. c.1 nm27c040 4,194,304-bit (512k x 8) high performance cmos eprom functional description (continued) erasure characteristics the erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms (?). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000?C4000? range. the recommended erasure procedure for the eprom is expo- sure to short wave ultraviolet light which has a wavelength of 2537?. the integrated dose (i.e., uv intensity x exposure time) for erasure should be minimum of 15w-sec/cm 2 . the eprom should be placed within 1 inch of the lamp tubes during erasure. some lamps have a filter on their tubes which should be removed before erasure. an erasure system should be calibrated periodically. the distance from lamp to device should be maintained at one inch. the erasure time increase as the square of the distance from the lamp. (if distance is doubled the erasure time increases by factor of 4.) lamps lose intensity as they age. when a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. incomplete erasure will cause symptoms that can be misleading. program- mers, components, and even system designs have been errone- ously suspected when incomplete erasure was the problem. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc , has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent of the output capacitance loading of the device. the associated v cc transient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces. mode selection the modes of operation of the nm27c040 are listed in table 1. a single 5v power supply is required in the read mode. all inputs are ttl levels except for v pp and a9 for device signature. table 1. modes selection pins ce/pgm oe v pp v cc outputs mode read v il v il x 5.0v d out (note 15) output disable x v ih x 5.0v high z standby v ih x x 5.0v high z programming v il v ih 12.75v 6.25v d in program verify x v il 12.75v 6.25v d out program inhibit v ih v ih 12.75v 6.25v high z note 15: x can be v il or v ih table 2. manufacturers identification code pins a0 a9 o7 o6 o5 o4 o3 o2 o1 o0 hex (12) (26) (21) (20) (19) (18) (17) (15) (14) (13) data manufacturer code v il 12v100011118f device code v ih 12v0000100008
9 www.fairchildsemi.com nm27c040 rev. c.1 nm27c040 4,194,304-bit (512k x 8) high performance cmos eprom 32-lead eprom ceramic dual-in-line package (q) order number nm27c040qxxx package number j32aq physical dimensions inches (millimeters) unless otherwise noted 1.660 max 32 1 17 16 r 0.025 r 0.030-0.055 typ uv window size and configuration determined by device size 0.590-0.620 0.175 max 0.060-0.100 typ 0.050-0.060 typ 0.015-0.021 typ 86?94 typ glass sealant 0.150 min typ 0.015 -0.060 typ 0.10 max 0.090-0.110 typ 0.005 min typ 0.225 max typ 0.125 min typ 90?- 100 typ 0.685 +0.025 -0.060 0.008-0.012 typ 0.585 max
10 www.fairchildsemi.com nm27c040 rev. c.1 nm27c040 4,194,304-bit (512k x 8) high performance cmos eprom 32-lead plcc package (v) order number nm27c040vxxx package number va32a physical dimensions inches (millimeters) unless otherwise noted 0.007[0.18] a s s f-g 0.007[0.18] b s d-e 0.449-0.453 [11.40-11.51] s 0.045 [1.143] 0.000-0.010 [0.00-0.25] polished optional 0.585-0.595 [14.86-15.11] 0.549-0.553 [13.94-14.05] -b- -f- -e- -g- 0.050 21 29 30 1 4 20 14 13 5 -d- 0.007[0.18] b s d-e s 0.002[0.05] b s -a- 0.485-0.495 [12.32-12.57] 0.007[0.18] a s s f-g a 0.002[0.05] s 0.007[0.18] h s s d-e, f-g 0.010[0.25] b a s d-e, f-g 0.118-0.129 [3.00-3.28] l b b 45 x 0.042-0.048 [1.07-1.22] 0.026-0.032 [0.66-0.81] typ 0.0100 [0.254] 0.030-0.040 [0.76-1.02] r 0.005 [0.13] max 0.020 [0.51] 0.045 [1.14] detail a typical rotated 90 0.027-0.033 [0.69-0.84] 0.025 [0.64] min 0.025 [0.64] min 0.031-0.037 [0.79-0.94] 0.053-0.059 [1.65-1.80] 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64] 0.065-0.071 [1.65-1.80] 0.021-0.027 [0.53-0.69] section b-b typical s 0.007[0.18] c m s d-e, f-g 0.015[0.38] c d-e, f-g 0.490-0530 [12.45-13.46] 0.078-0.095 [1.98-2.41] 0.013-0.021 [0.33-0.53] 0.004[0.10] 0.123-0.140 [3.12-3.56] see detail a -j- -c- 0.400 [10.16] ( ) typ 0.541-0.545 [13.74-13-84] 0.023-0.029 [0.58-0.74] 0.106-0.112 [2.69-2.84] 60 0.015 [0.38] base plane -h- min typ s
11 www.fairchildsemi.com nm27c040 rev. c.1 nm27c040 4,194,304-bit (512k x 8) high performance cmos eprom physical dimensions inches (millimeters) unless otherwise noted 32-lead pdip package order number nm27c040nxxx 1.64 ?1.66 (41.66 ?42.164) 32 1 17 16 0.062 (1.575) rad pin no. 1 ident 0.580 (14.73) min 0.600 ?0.620 (15.240 ?15.748) 0.145 ?0.210 (3.683 ?5.334) 0.040 - 0.090 (1.016 ?2.286) 0.050 (1.270) typ typ 0.125 ?0.165 (3.175 ?4.191) 0.018 0.003 (0.457 0.078) 0.035 ?0.07 (0.889 ?1.778) 86 - 94 typ 0.120 ?0.150 (3.048 ?3.81) 0.015 (0.381) 0.100 0.010 (2.540 0.254) 90 ?05 0.008 - 0.015 (0.203 ?0.381) 0.490 ?0.550 (12.446 ?13.97) fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm27c128 131,072-bit (16k x 8) high performance cmos eprom nm27c128 131,072-bit (16k x 8) high performance cmos eprom general description the nm27c128 is a high performance 128k uv erasable electri- cally programmable read only memory. it is manufactured with fairchilds latest cmos split gate eprom technology which enables it to operate at speeds as fast as 90 ns access time over the full operating range. the nm27c128 provides microprocessor-based systems exten- sive storage capacity for large portions of operating system and application software. its 90 ns access time provides high speed operation with high-performance cpus. the nm27c128 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. frequently-used software routines are quickly executed from eprom storage, greatly enhancing system utility. the nm27c128 is configured in the standard eprom pinout which provides an easy upgrade path for systems which are currently using standard eproms. block diagram july 1998 the nm27c128 is one member of a high density eprom family which range in densities up to 4 mb. features n high performance cmos 90 ns access time n fast turn-off for microprocessor compatibility n jedec standard pin configuration 28-pin pdip package 32-pin chip carrier 28-pin cerdip package n drop-in replacement for 27c128 or 27128 n 40% faster programming time with fairchilds turbo algorithm ? 1998 fairchild semiconductor corporation output enable, and chip enable logic y decoder x decoder . . . . . . . . . output buffers y gating 131,072-bit cell matrix data outputs o 0 - o 7 v cc gnd v pp oe pgm ce a 0 - a 14 address inputs ds011329-1 ds011329-1
2 www.fairchildsemi.com nm27c128 131,072-bit (16k x 8) high performance cmos eprom connection diagrams note: compatible eprom pin configurations are shown in the blocks adjacent to the nm27c128 pins. commercial temp. range (0 c to +70 c) v cc = 5v 10% parameter/order number access time (ns) nm27c128 q, n, v 90 90 nm27c128 q, n, v 120 120 nm27c128 q, n, v 150 150 nm27c128 q, n, v 200 200 pin names symbol description a0Ca13 addresses ce chip enable oe output enable o0Co7 outputs pgm program nc no connect extended temp. range (-40 c to +85 c) v cc = 5v 10% parameter/order number access time (ns) nm27c128 qe, ne, ve 120 120 nm27c128 qe, ne, ve 150 150 nm27c128 qe, ne, ve 200 200 note: surface mount plcc package available for commercial and extended temperature ranges only. package types: nm27c128 q, n, v xxx q = quartz-windowed ceramic dip n = plastic otp dip v = surface-mount plcc ? all packages conform to the jedec standard. ? all versions are guaranteed to function for slower speeds. plcc top 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd a 19 a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c080 27c040 27c040 v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd dlp nm27c128 v cc pgm a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c512 27c512 v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c256 27c256 v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c010 v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c020 27c020 27c010 v cc pgm xx a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 27c080 v cc a 18 a 17 a 14 a 13 a 8 a 9 a 11 oe/v pp a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 v cc a 18 a 17 a 14 a 13 a 8 a 9 a 11 oe a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 v cc pgm xx a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc a 14 a 13 a8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc a 14 a 13 a 8 a 9 a 11 oe/v pp a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 ds011329-8 ds011329-3 a8 a9 a11 nc oe a10 ce o7 o6 a6 a5 a4 a3 a2 a1 a0 nc o0 a7 a12 vpp nc vcc pgm a13 o1 o2 gnd nc o3 o4 o5 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 32 31 30
3 www.fairchildsemi.com nm27c128 131,072-bit (16k x 8) high performance cmos eprom absolute maximum ratings (note 1) storage temperature -65 c to +150 c all input voltages except a9 with respect to ground -0.6v to +7v v pp and a9 with respect to ground -0.7v to +14v v cc supply voltage with respect to ground -0.6v to +7v esd protection > 2000v all output voltages with respect to ground v cc + 1.0v to gnd -0.6v operating range range temperature v cc comml 0 c to +70 c +5v 10% industrial -40 c to +85 c +5v 10% read operation dc electrical characteristics over operating range with v pp = v cc symbol parameter test conditions min max units v il input low level -0.5 0.8 v v ih input high level 2.0 v cc +1 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -2.5 ma 3.5 v i sb1 v cc standby current ce = v cc 0.3v 100 m a (cmos) v il = gnd 0.3v, v ih = v cc 0.3v i sb2 v cc standby current (t 2 l) ce = v ih 1ma i cc1 v cc active current, t 2 l inputs ce = oe = v il , f = 5 mhz 35 ma i/o = 0 ma i pp v pp supply current v pp = v cc 10 m a v pp v pp read voltage gnd v cc v i li input load current v in = 5.5v or gnd -1 1 m a i lo output leakage current v out = 5.5v or gnd -10 10 m a ac electrical characteristics over operating range with v pp = v cc symbol parameter 90 120 150 200 units min max min max min max min max t acc address to output delay 90 120 150 200 ns t ce ce to output delay 90 120 150 200 ns t oe oe to output delay 50 50 50 50 ns t cf ce high to output float 30 30 45 55 ns (note 2) t df oe high to output float 35 35 45 55 ns (note 2) t oh output hold from addresses, (note 2) ce or oe, 0000 ns whichever occurred first
4 www.fairchildsemi.com nm27c128 131,072-bit (16k x 8) high performance cmos eprom capacitance t a = +25 c, f = 1 mhz (note 2) symbol parameter conditions typ max units c in input capacitance v in = 0v 6 12 pf c out output capacitance v out = 0v 9 12 pf ac test conditions output load 1 ttl gate and c l = 100 pf (note 8) input rise and fall times 5 ns input pulse levels 0.45 to 2.4v timing measurement reference level (note 10) inputs 0.8v and 2.0v outputs 0.8v and 2.0v ac waveforms (notes 6, 7, 9) addresses valid valid output hi-z 2v 0.8v 2v 0.8v 2v 0.8v addresses output ce oe t ce 2v 0.8v (note 3) (note 3) t df t cf (notes 4, 5) (notes 4, 5) t oh hi-z t oe acc t note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating on ly and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: this parameter is only sampled and is not 100% tested. note 3: oe may be delayed up to t acc - t oe after the falling edge of ce without impacting t acc . note 4: the t df and t cf compare level is determined as follows: high to tri-state ? , the measured v oh1 (dc) - 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 5: tri-state may be attained using oe or ce . note 6: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. note 7: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 8: ttl gate: i ol = 1.6 ma, i oh = -400 m a. c l = 100 pf includes fixture capacitance. note 9: v pp may be connected to v cc except during programming. note 10: inputs and outputs can undershoot to -2.0v for 20 ns max. ds011329-4
5 www.fairchildsemi.com nm27c128 131,072-bit (16k x 8) high performance cmos eprom programming characteristics (notes 11, 12, 13, 14) symbol parameter conditions min typ max units t as address setup time 1 m s t oes oe setup time 1 m s t ces ce setup time oe = v ih 1 m s t vps v pp setup time 1 m s t vcs v cc setup time 1 m s t ds data setup time 1 m s t ah address hold time 0 m s t dh data hold time 1 m s t df output enable to output float delay ce = v il 060ns t pw program pulse width 45 50 105 m s t oe data valid from oe ce = v il 100 ns i pp v pp supply current ce = v il 30 ma during programming pulse i cc v cc supply current 50 ma t a temperature ambient 20 25 30 c v cc power supply voltage 6.25 6.5 6.75 v v pp programming supply voltage 12.5 12.75 13.0 v t fr input rise, fall time 5 ns v il input low voltage 0.0 0.45 v v ih input high voltage 2.4 4.0 v t in input timing reference voltage 0.8 2.0 v t out output timing reference voltage 0.8 2.0 v programming waveforms (note 13) note 11: fairchilds standard product warranty applies to devices programmed to specifications described herein. note 12: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 13: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v pp , v cc to gnd to suppress spurious voltage transients which may damage the device. note 14: during power up the pgm pin must be brought high ( 3 v ih ) either coincident with or before power is applied to v pp . t as t ah program program verify address n t df data out valid add n data in stable add n hi-z t ds t dh t vcs t vps t ces t pw t oes t oe 2v 0.8v 2v 0.8v 2v 0.8v 2v 0.8v 6.0v 13.0v 0.8v address data v cc ce oe v pp pgm ds011329-5
6 www.fairchildsemi.com nm27c128 131,072-bit (16k x 8) high performance cmos eprom turbo programming algorithm flow chart v cc = 6.5v v pp = 12.75v n = 0 address = first location check all bytes 1st: v cc = v pp = 6.0v 2nd: v cc = v pp = 4.3v program one 50 s pulse increment n address = first location verify byte n = 10? device failed last address ? increment address n = 0 program one 50 s pulse increment address verify byte last address ? pass no fail yes yes pass no fail no yes figure 1. ds011329-6 note: the standard national semiconductor algorithm may also be used but it will have longer programming time.
7 www.fairchildsemi.com nm27c128 131,072-bit (16k x 8) high performance cmos eprom functional description device operation the six modes of operation of the eprom are listed in table 1. it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and v pp . the v pp power supply must be at 12.75v during the three programming modes, and must be at 5v in the other three modes. the v cc power supply must be at 6.5v during the three programming modes, and at 5v in the other three modes. read mode the eprom has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs t oe after the falling edge of oe, assuming that ce has been low and addresses have been stable for at least t acc Ct oe . standby mode the eprom has a standby mode which reduces the active power dissipation by over 99%, from 220 mw to 0.55 mw. the eprom is placed in the standby mode by applying a cmos high signal to the ce input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output disable the eprom is placed in output disable by applying a ttl high signal to the oe input. when in output disable all circuitry is enabled, except the outputs are in a high impedance state (tri- state). output or-typing because the eprom is usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ce be decoded and used as the primary device selecting function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on pin 1 (v pp ) will damage the eprom. initially, and after each erasure, all bits of the eprom are in the 1s state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be pro- grammed, both 1s and 0s can be presented in the data word. the only way to change a 0 to a 1 is by ultraviolet light erasure. the eprom is in the programming mode when the v pp power supply is at 12.75v, ce is at v il , and oe is at v ih . it is required that at least a 0.1 m f capacitor be placed across v pp , v cc to ground to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 8 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. when the address and data are stable, an active low, ttl program pulse is applied to the pgm input. a program pulse must be applied at each address location to be programmed. the eprom is programmed with the turbo programming algorithm shown in figure 1. each address is programmed with a series of 50 m s pulses until it verifies good, up to a maximum of 10 pulses. most memory cells will program with a single 50 m s pulse. (the standard national semiconductor algorithm may also be used but it will have longer programming time.) the eprom must not be programmed with a dc signal applied to the pgm input. programming multiple eprom in parallel with the same data can be easily accomplished due to the simplicity of the programming requirments. like inputs of the parallel eprom may be connected together when they are programmed with the same data. a low level ttl pulse applied to the pgm input programs the paralleled eprom. program inhibit programming multiple eproms in parallel with different data is also easily accomplished. except for ce all like inputs (including oe) of the parallel eproms may be common. a ttl low level program pulse applied to an eproms ce input with v pp at 12.75v will program that eprom. a ttl high level ce input inhibits the other eproms from being programmed.
8 www.fairchildsemi.com nm27c128 131,072-bit (16k x 8) high performance cmos eprom functional description (continued) program verify a verify should be performed on the programmed bits to determine whether they were correctly programmed. the verify may be performed with v pp at 12.75v. v pp must be at v cc , except during programming and program verify. after programming opaque labels should be placed over the eprom window to prevent unintentional erasure. covering the window will also prevent temporary functional failure due to the generation of photo currents. manufacturers identification code the eprom has a manufacturers identification code to aid in programming. when the device is inserted in an eprom pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. the manufacturers identification code, shown in table 2, specifi- cally identifies the manufacture and device type. the code for nm27c128 is 8f83, where 8f designates that it is made by fairchild semiconductor, and 83 designates a 128k part. the code is accessed by applying 12v 0.5v to address pin a9. addresses a1Ca8, a10Ca13, and all control pins are held at v il . address pin a0 is held at v il for the manufacturers code, and held at v ih for the device code. the code is read on the eight data pins, o0 Co7 . proper code access is only guaranteed at 25 c to 5 c. erasure characteristics the erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms (?). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000? C 4000? range. the recommended erasure procedure for the eprom is expo- sure to short wave ultraviolet light which has a wavelength of 2537?. the integrated dose (i.e., uv intensity x exposure time) for erasure should be a minimum of 15w-sec/cm 2 . the eprom should be placed within 1 inch of the lamp tubes during erasure. some lamps have a filter on their tubes which should be removed before erasure. table 1 shows the minimum eprom erasure time for various light intensities. an erasure system should be calibrated periodically. the distance from lamp to device should be maintained at one inch. the erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4). lamps lose intensity as they age. when a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. incomplete erasure will cause symptoms that can be misleading. program- mers, components, and even system designs have been errone- ously suspected when incomplete erasure was the problem. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc , has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent of the output capacitance loading of the device. the associated v cc transient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces.
9 www.fairchildsemi.com nm27c128 131,072-bit (16k x 8) high performance cmos eprom mode selection the modes of operation of nm27c128 listed in table 1. a single 5v power supply is required in the read mode. all inputs are ttl levels except for v pp and a9 for device signature. table 1. modes selection pins ce oe pgm v pp v cc outputs mode read v il v il v ih v cc 5.0v d out output disable x v ih v ih v cc 5.0v high-z standby v ih xxv cc 5.0v high-z programming v il v ih v il 12.75v 6.5v d in program verify v il v il v ih 12.75v 6.5v d out program inhibit v ih x x 12.75v 6.5v high-z note 15: x can be v il or v ih . table 2. manufacturers identification code pins a0 a9 o7 o6 o5 o4 o3 o2 o1 o0 hex (10) (24) (19) (18) (17) (16) (15) (13) (12) (11) data manufacturer code v il 12v100011118f device code v ih 12v1000001183
10 www.fairchildsemi.com nm27c128 131,072-bit (16k x 8) high performance cmos eprom uv window cavity dual-in-line cerdip package (jq) order number nm27c128qxxx package number j28cq (c) 28-lead plastic one-time-programmable dual-in-line package order number nm27c128nxxx package number n28b physical dimensions inches (millimeters) unless otherwise noted 1.465 (37.08) max 28 1 15 14 r 0.025 (0.64) r 0.030-0.055 (0.76 - 1.40) typ 0.180 (4.57) max 0.060-0.100 (1.52 - 2.54) typ 0.050-0.060 (1.27 - 1.52) typ 0.015-0.021 (0.38 - 0.53) typ 0.035 - 0.045 (0.76 - 1.14) typ 86 -94 typ glass sealant 0.015 -0.060 (0.38 - 1.52) typ 0.10 (2.54) max 0.090-0.110 (2.29 - 2.79) typ 0.225 (5.72) 0.125 (3.18) min typ 0.590-0.620 (14.99 - (15.75) 90 - 100 typ 0.685 (17.40) +0.025 (0.64) -0.060 (-1.523) 0.008-0.012 (0.20 - 0.25) 0.280 0.010 (7.11 0.25) uv window 0.515 - 0.530 (13.08 - 13.46) max typ typ 0.008 ?0.015 (0.203 ?0.381) 0.580 (14.73) 90 ?05 0.583 ?0.640 (14.81 ?16.26) 0.030 (0.762) max 0.100 0.010 (2.54 ?.254) 0.018 0.003 (0.457 0.076) 0.015 (0.381) 0.120 ?0.150 (3.048 ?3.81) 0.125 ?0.165 (3.175-4.191) 0.035 ?0.070 (0.889 ?1.778) 0.050 (1.270) 0.145 - 0.210 (3.683 - 5.334) 0.065 0.025 (1.65 0.635) min 86 94 typ 12 34 28 27 26 25 1.360 - 1.470 (34.544 - 37.34) 0.490 ?0.550 (12.446 ?13.97) 0.062 (1.575) pin #1 ident 5 24 6 23 22 21 20 19 18 17 16 7 8 9 1011121314 15 typ rad typ min
11 www.fairchildsemi.com nm27c128 131,072-bit (16k x 8) high performance cmos eprom 32-lead plastic leaded chip carrier (plcc) order number nm27c128vxxx package number va32a physical dimensions inches (millimeters) unless otherwise noted 0.007[0.18] a s s f-g 0.007[0.18] b s d-e 0.449-0.453 [11.40-11.51] s 0.045 [1.143] 0.000-0.010 [0.00-0.25] polished optional 0.585-0.595 [14.86-15.11] 0.549-0.553 [13.94-14.05] -b- -f- -e- -g- 0.050 21 29 30 1 4 20 14 13 5 -d- 0.007[0.18] b s d-e s 0.002[0.05] b s -a- 0.485-0.495 [12.32-12.57] 0.007[0.18] a s s f-g a 0.002[0.05] s 0.007[0.18] h s s d-e, f-g 0.010[0.25] b a s d-e, f-g 0.118-0.129 [3.00-3.28] l b b 45 x 0.042-0.048 [1.07-1.22] 0.026-0.032 [0.66-0.81] typ 0.0100 [0.254] 0.030-0.040 [0.76-1.02] r 0.005 [0.13] max 0.020 [0.51] 0.045 [1.14] detail a typical rotated 90 0.027-0.033 [0.69-0.84] 0.025 [0.64] min 0.025 [0.64] min 0.031-0.037 [0.79-0.94] 0.053-0.059 [1.65-1.80] 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64] 0.065-0.071 [1.65-1.80] 0.021-0.027 [0.53-0.69] section b-b typical s 0.007[0.18] c m s d-e, f-g 0.015[0.38] c d-e, f-g 0.490-0530 [12.45-13.46] 0.078-0.095 [1.98-2.41] 0.013-0.021 [0.33-0.53] 0.004[0.10] 0.123-0.140 [3.12-3.56] see detail a -j- -c- 0.400 [10.16] ( ) typ 0.541-0.545 [13.74-13-84] 0.023-0.029 [0.58-0.74] 0.106-0.112 [2.69-2.84] 60 ? 0.015 [0.38] base plane -h- min typ s fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm27c210 1,048,576-bit (64k x 16) high performance cmos eprom nm27c210 1,048,576-bit (64k x 16) high performance cmos eprom general description the nm27c210 is a high performance electrically programmable uv erasable rom (eprom). it contains 1,048,576 bits config- ured as 64k x 16 bit. it is offered in both erasable versions for prototyping and early production applications as well as non- erasable, plastic packaged versions that are ideal for high volume and automated assembly applications. the nm27c210 operates from a single 5 volt 10% supply in the read mode. the nm27c210 is offered in both dip and surface mount pack- ages. the dip package is a 40-pin dual-in-line ceramic with a quartz window to allow erasing. the surface mount package is a 44-pin plcc that is offered in otp. this eprom is manufactured using fairchilds proprietary amg? eprom technology for an excellent combination of speed and economy while providing excellent reliability. block diagram july 1998 features n high performance cmos 90 ns access time n fast turn-off for microprocessor compatibility n simplified upgrade path v pp and pgm are dont care during normal read operation n compatible with 27210 and 27c210 eproms n manufacturers identification code n fast programming n jedec standard pin configuration 40-pin cdip package 40-pin pdip package 44-pin plcc package ds011093-1 amg? is a trademark of wsi, inc. ? 1998 fairchild semiconductor corporation v cc gnd v pp oe pgm ce output enable chip enable, and program logic y decoder x decoder output buffers 4,194,304-bit cell matrix a 0 - a 15 address inputs data outputs o 0 - o 15
2 www.fairchildsemi.com nm27c210 1,048,576-bit (64k x 16) high performance cmos eprom connection diagrams dip pin configurations note: compatible eprom pin configurations are shown in the blocks adjacent to the nm27c210 pins. commercial temperature range (0 c to +70 c) v cc = 5v 10% parameter/order number access time (ns) nm27c210 q, v, n 90 90 nm27c210 q, v, n 120 120 nm27c210 q, v, n 150 150 industrial temperature range (-40 c to +85 c) v cc = 5v 10% parameter/order number access time (ns) nm27c210 qe, ve, ne 120 120 nm27c210 qe, ve, ne 150 150 package types: nm27c210 q, v, n xxx q = quartz-windowed ceramic dip package n = plastic dip package v = plcc package ? all packages conform to jedec standard. ? all versions are guaranteed to function in slower applications. pin names a0Ca15 addresses ce chip enable oe output enable o0Co15 outputs pgm program xx dont care (during read) nc no connect plcc pin configuration 27c220 27c240 27c280 a 18 ce/pgm o 15 o 14 o 13 o 12 o 11 o 10 o 9 o 8 gnd o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 oe/v pp xxv pp ce/pgm o 15 o 14 o 13 o 12 o 11 o 10 o 9 o 8 gnd o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 oe xxv pp ce o 15 o 14 o 13 o 12 o 11 o 10 o 9 o 8 gnd o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 oe v cc a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 gnd a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v cc pgm a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 gnd a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v cc a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 gnd a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 xx/v pp ce o 15 o 14 o 13 o 12 o 11 o 10 o 9 o 8 gnd o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 oe v cc xx/pgm nc a 15 a 14 a 13 a 12 a 11 a 10 a 9 gnd a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 27c280 27c240 27c220 dip nm27c210 o 12 o 11 o 10 o 9 o 8 gnd nc o 7 o 6 o 5 o 4 a 13 a 12 a 11 a 10 a 9 gnd nc a 8 a 7 a 6 a 5 o 13 o 14 o 15 ce xx/v pp nc xx/pgm nc a 15 a 14 o 3 o 2 o 1 o 0 oe nc a 1 a 2 a 2 a 3 a 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 40 41 42 43 44 38 37 36 35 34 33 32 31 30 22 21 20 19 18 28 27 26 25 24 23 29 39 v cc ds011093-3 ds011093-7 top view
3 www.fairchildsemi.com nm27c210 1,048,576-bit (64k x 16) high performance cmos eprom absolute maximum ratings (note 1) storage temperature -65 c to +150 c all input voltages except a9 with respect to ground (note 10) -0.6v to +7v v pp and a9 with respect to ground -0.6v to +14v v cc supply voltage with respect to ground -0.6v to +7v esd protection >2000v all output voltages with respect to ground (note 10) v cc + 1.0v to gnd - 0.6v operating range range temperature v cc tolerance commercial 0 c to +70 c +5v 10% industrial -40 c to +85 c +5v 10% dc read characteristics over operating range with v pp = v cc symbol parameter test conditions min max units v il input low level -0.5 0.8 v v ih input high level 2.0 v cc +1 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -2.5 ma 3.5 v i sb1 v cc standby current ce = v cc 0.3v 100 m a (cmos) i sb2 v cc standby current ce = v ih 1ma i cc v cc active current ce = oe = v il f = 5 mhz 40 ma i/o = 0 ma i pp v pp supply current v pp = v cc 10 m a i li input load current v in = 5.5 or gnd -1 1 m a i lo output leakage current v out = 5.5v or gnd -10 10 m a ac read characteristics over operating range with v pp = v cc symbol parameter 90 120 150 units min max min max min max t acc address to output delay 90 120 150 t ce ce to output delay 90 120 150 t oe oe to output delay 50 50 50 t df output disable to output float 30 35 45 ns (note 2) t oh output hold from addresses, (note 2) ce or oe , whichever 0 0 0 occurred first capacitance (note 2) t a = +25 c, f = 1 mhz symbol parameter conditions typ max units c in input capacitance v in = 0v 12 20 pf c out output capacitance v out = 0v 13 20 pf
4 www.fairchildsemi.com nm27c210 1,048,576-bit (64k x 16) high performance cmos eprom ac test conditions output load 1 ttl gate and c l = 100 pf (note 8) input rise and fall times 5 ns input pulse levels 0.45v to 2.4v timing measurement reference level inputs 0.8v and 2v outputs 0.8v and 2v ac waveforms (note 6) , (note 7) , (note 9) note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: this parameter is only sampled and is not 100% tested. note 3: oe may be delayed up to t acc - t oe after the falling edge of ce without impacting t acc . note 4: the t df and t cf compare level is determined as follows: high to tri-state ? , the measured v oh1 (dc) - 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 5: tri-state may be attained using oe or ce . note 6: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. note 7: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 8: 1 ttl gate: i ol = 1.6 ma, i oh = -400 m a. c l : 100 pf includes fixture capacitance. note 9: v pp may be connected to v cc except during programming. note 10: inputs and outputs can undershoot to -2.0v for 20 ns max. t oh t df notes 4, 5 t cf notes 4, 5 t acc note 3 t oe note 3 high z 2.0v 0.8v output 2.0v 0.8v oe 2.0v 0.8v ce 2.0v 0.8v adresses high z addresses valid t ce ds011093-4
5 www.fairchildsemi.com nm27c210 1,048,576-bit (64k x 16) high performance cmos eprom programming characteristics (note 11), (note 12), (note 13), (note 14), and (note 15) symbol parameter conditions min typ max units t as address setup time 1 m s t oes oe setup time 1 m s t ces ce setup time oe = v ih 1 m s t ds data setup time 1 m s t vps v pp setup time 1 m s t vcs v cc setup time 1 m s t ah address hold time 0 m s t dh data hold time 1 m s t df output enable to output float delay ce = v il 060ns t pw program pulse width 45 50 105 m s t oe data valid from oe ce = v il 100 ns i pp v pp supply current during ce = v il 40 ma programming pulse pgm = v il i cc v cc supply current 50 ma t a temperature ambient 20 25 30 c v cc power supply voltage 6.25 6.5 6.75 v v pp programming supply voltage 12.5 12.75 13.0 v t fr input rise, fall time 5 ns v il input low voltage 0.0 0.45 v v ih input high voltage 2.4 4.0 v t in input timing reference voltage 0.8 2.0 v t out output timing reference voltage 0.8 2.0 v programming waveforms (note 13) note 11: fairchilds standard product warranty applies only to devices programmed to specifications described herein. note 12: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 13: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v pp , v cc to gnd to suppress spurious voltage transients which may damage the device. note 14: programming and program verify are tested with the turbo program algorithm, at typical power supply voltages and timings. note 15: during power up the pgm pin must be brought high ( v ih ) either coincident with or before power is applied to v pp . t pw 2.0v 0.8v 12.75v 6.25v 2.0v 0.8v adresses address n t df program program verify data in stable add n data out valid add n data v cc v pp t as t ah t oes t oe high z 2.0v 0.8v oe ce/pgm t ds 2.0v 0.8v t dh t vcs t vps ds011093-5
6 www.fairchildsemi.com nm27c210 1,048,576-bit (64k x 16) high performance cmos eprom turbo programming algorithm flow chart figure 1. v cc = 6.5v v pp = 12.75v n = 0 address = first location check all bytes 1st: v cc = v pp = 6.0v 2nd: v cc = v pp = 4.3v program one 50 s pulse increment n address = first location verify byte n = 10? device failed last address ? increment address n = 0 program one 50 s pulse increment address verify byte last address ? pass no fail yes yes pass no fail no yes ds011093-6 note: the standard national semiconductor algorithm may also be used but it will have longer programming time.
7 www.fairchildsemi.com nm27c210 1,048,576-bit (64k x 16) high performance cmos eprom functional description device operation the six modes of operation of the eprom are listed in table 1. it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and v pp . the v pp power supply must be at 12.75v during the three programming modes, and must be at 5v in the other three modes. the v cc power supply must be at 6.5v during the three programming modes, and at 5v in the other three modes. read mode the eprom has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that the addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs t oe after the falling edge of oe, assuming that ce has been low and addresses have been stable for at least t acc C t oe . standby mode the eprom has a standby mode which reduces the active power dissipation by over 99%, from 200 mw to 0.5 mw. the eprom is placed in the standby mode by applying a cmos high signal to the ce input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output disable the eprom is placed in output disable by applying a ttl high signal to the oe input. when in output disable all circuitry is enabled, except the outputs are in a high impedance state (tri- state). output or-tying because the eprom is usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ce be decoded and used as the primary device selecting function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on the v pp or a9 pin will damage the eprom. initially, and after each erasure, all bits of the eprom are in the 1s state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be pro- grammed, both 1s and 0s can be presented in the data word. the only way to change a 0 to a 1 is by ultraviolet light erasure. the eprom is in the programming mode when the v pp power supply is at 12.75v and oe is at v ih . it is required that at least a 0.1 m f capacitor be placed across v pp , v cc to ground to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 16 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. when the address and data are stable, an active low, ttl program pulse is applied to the pgm input. a program pulse must be applied at each address location to be programmed. the eprom is programmed with the turbo programming algorithm shown in figure 1. each address is programmed with a series of 50 m s pulses until it verifies good, up to a maximum of 10 pulses. most memory cells will program with a single 50 m s pulse. (the standard national semiconductor algorithm may also be used but it will have longer programming time). the eprom must not be programmed with a dc signal applied to the pgm input. programming multiple eprom in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. like inputs of the parallel eprom may be con- nected together when they are programmed with the same data. a low level ttl pulse applied to the pgm input programs the paralleled eprom. program inhibit programming multiple eproms in parallel with different data is also easily accomplished. except for ce all like inputs (including oe and pgm) of the parallel eprom may be common. a ttl low level program pulse applied to an eproms pgm input with ce at v il and v pp at 12.75v will program that eprom. a ttl high level ce input inhibits the other eproms from being programmed. program verify a verify should be performed on the programmed bits to determine whether they were correctly programmed. the verify may be performed with v pp at 12.75v. v pp must be at v cc , except during programming and program verify. after programming opaque labels should be placed over the eprom window to prevent unintentional erasure. covering the window will also prevent temporary functional failure due to the generation of photo currents. manufacturers identification code the eprom has a manufacturers identification code to aid in programming. when the device is inserted in an eprom pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. the manufacturers identification code, shown in table 2, specifi- cally identifies the manufacturer and device type. the code for the nm27c210 is 8fd6, where 8f designates that it is made by fairchild semiconductor, and d6 designates a 1 megabit (64k x 16) part. the code is accessed by applying 12v 0.5v to address pin a9 . addresses a1 Ca8, a10 Ca 15 , and all control pins are held at v il . address pin a0 is held at v il for the manufacturers code, and held
8 www.fairchildsemi.com nm27c210 1,048,576-bit (64k x 16) high performance cmos eprom functional description (continued) at v ih for the device code. the code is read on the lower eight data pins, o0 C07 . proper code access is only guaranteed at 25 c 5 c. erasure characteristics the erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms (?). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000? C 4000? range. the recommended erasure procedure for the eprom is expo- sure to short wave ultraviolet light which has a wavelength of 2537?. the integrated dose (i.e., uv intensity x exposure time) for erasure should be a minimum of 15w-sec/cm 2 . the eprom should be placed within 1 inch of the lamp tubes during erasure. some lamps have a filter on their tubes which should be removed before erasure. an erasure system should be calibrated periodically. the distance from lamp to device should be maintained at one inch. the erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4). lamps lose intensity as they age. when a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. incomplete erasure will cause symptoms that can be misleading. program- mers, components, and even system designs have been errone- ously suspected when incomplete erasure was the problem. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc , has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. the associated v cc transient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces. mode selection the modes of operation of the nm27c210 are listed in table 1. a single 5v power supply is required in the read mode. all inputs are ttl levels except for v pp and a9 for device signature. table 1. modes selection pins ce oe pgm v pp v cc outputs mode read v il v il x x 5.0v d out (note 16) output disable x v ih x x 5.0v high z standby v ih x x x 5.0v high z programming v il v ih v il 12.75v 6.25v d in program verify v il v il v ih 12.75v 6.25v d out program inhibit v ih x x 12.75v 6.25v high z note 16: x can be v il or v ih . table 2. manufacturers identification code pins a0 a9 o7 o6 o5 o4 o3 o2 o1 o0 hex (21) (31) (12) (13) (14) (15) (16) (17) (18) (19) data manufacturer code v il 12v100011118f device code v ih 12v11010110d6
9 www.fairchildsemi.com nm27c210 1,048,576-bit (64k x 16) high performance cmos eprom 40-lead eprom ceramic dual-in-line package (q) order number nm27c210qxxx package number j40bq 40-lead molded dual-in-line package (n) order number nm27c210nxxx package number n40a 0.590-0.620 (14.985-15.748) 0.08-0.012 (0.203-0.305) 0.180 (4.572) max 0.150 (3.810) min 0.090 (2.489) max (both ends) 86?94?typ 0.055-0.005 (1.397?.127) typ 0.125-0.200 (3.175-5.080) 0.005 (0.127) 95?? 0.100?.010 (2.540?.254) typ 0.020-0.070 (0.508-1.778) glass sealant 17.40 +0.635 -1.524 ( ( 2.080 (52.03) max 40 1 20 0.030-0.055 (0.762-1.397) rad typ 0.025 (0.036) 21 rad 0.280?.04 (7.112?.102) uv window 0.225 (5.715) max 0.018?.003 (.457?.076) typ min 0.530 (13.46) max ceramic 0.550 (13.97) max glass 0.685 +0.025 -0.060 physical dimensions inches (millimeters) unless otherwise noted 0.580 (14.73) min 86?94? typ 0.075?.015 (1.905?.381) 0.009-0.015 (0.229-0.381) 95??5 0.018?.003 (0.457?.076) 15.875 +0.635 -0.381 ( ( 2.043-2.070 (51.89-52.58) max 40 1 20 pin no. 1 ident 0.062 (1.575) 21 rad 0.225 (5.715) 0.100?.010 (2.540?.254) 0.550 ?.005 (13.970?.127) 0.625 +0.025 -0.015 0.600-0.620 (15.240-15.748) 0.050 (1.270) typ 0.020 (0.508) min 0.125-0.140 (3.175-3.556) 0.125-0.165 (3.175-4.191) 0.030 (0.762) max
10 www.fairchildsemi.com nm27c210 1,048,576-bit (64k x 16) high performance cmos eprom physical dimensions inches (millimeters) unless otherwise noted 44-lead plastic chip carrier (v) order number nm27c210vxxx package number v44a 6 1 44 40 39 29 17 17 18 28 0.050 [1.27] typ 0.500 [12.70] typ 0.650 +0.006 ?.000 16.51 +0.15 0 pin 1 ident 0.690 0.005 [17.53 ?.13] typ 0.045 [1.14] 45 x 0.026?.032 [0.66?.81] 0.017 0.021 [0.43 0.10] 0.045 [1.14] 0.020 [0.51] 0.610 0.020 [15.49 0.51] 0.105 0.015 [2.67 0.38] typ typ min typ seating plane typ 0.165?.180 [4.19?.57] typ typ 45 x 0.004 [0.10] fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm27c240 4,194,304-bit (256k x 16) high performance cmos eprom nm27c240 4,194,304-bit (256k x 16) high performance cmos eprom general description the nm27c240 is a high performance electrically programmable uv erasable rom (eprom). it contains 4,194,304 bits config- ured as 256k x 16 bits. it is offered in both erasable versions for prototyping and early production applications as well as non- erasable, plastic packaged versions that are ideal for high volume and automated assembly applications. the nm27c240 operates from a single 5v 10% supply in the read mode. the nm27c240 is offered in both dip and surface mount pack- ages. the dip package is a 40-pin dual-in-line ceramic with a quartz window to allow erasing. the surface mount package is a 44-pin plcc that is offered in otp. this eprom is manufactured using fairchilds proprietary amg? eprom technology for an excellent combination of speed and economy while providing excellent reliability. block diagram july 1998 features n high performance cmos 100 ns access time n fast turn-off for microprocessor compatibility n simplified upgrade path v pp and pgm are dont care during normal read operation n compatible with 27240 and 27c240 eproms n jedec standard pin configuration 40-pin dip package 44-pin plcc package n manufacturers identification code n fast programming algorithm amg? is a trademark of wsi, inc. ? 1998 fairchild semiconductor corporation v cc gnd v pp oe ce/pgm output enable chip enable, and program logic y decoder x decoder output buffers 4,194,304-bit cell matrix a 0 - a 17 address inputs data outputs o 0 - o 15 ds011949-1
2 www.fairchildsemi.com nm27c240 4,194,304-bit (256k x 16) high performance cmos eprom connection diagrams dip pin configurations note: compatible eprom pin configurations are shown in the blocks adjacent to the nm27c240 pins. commercial temperature range (0 c to +70 c) v cc = 5v 10% parameter/order number access time (ns) nm27c240 q, v, n 100 100 nm27c240 q, v, n 120 120 nm27c240 q, v, n 150 150 note: surface mount plcc package available for commercial and extended temperature ranges only. package types: nm27c240 q, v, n xxx q = quartz-windowed ceramic dip package v = plcc package n = plastic dip package ? all packages conform to jedec standard. ? all versions are guaranteed to function in slower applications. pin names a0Ca15 addresses ce/pgm chip enable/program oe output enable o0Co15 outputs xx dont care (during read) nc no connect extended temperature range (-40 to +85 c) v cc = 5v 10% parameter/order number access time (ns) nm27c240 qe, ve, ne 120 120 nm27c240 qe, ve, ne 150 150 plcc pin configuration 27c210 27c220 27c280 a 18 ce/pgm o 15 o 14 o 13 o 12 o 11 o 10 o 9 o 8 gnd o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 oe/v pp xxv pp ce o 15 o 14 o 13 o 12 o 11 o 10 o 9 o 8 gnd o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 oe xxv pp ce o 15 o 14 o 13 o 12 o 11 o 10 o 9 o 8 gnd o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 oe v cc a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 gnd a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v cc xx/pgm nc a 15 a 14 a 13 a 12 a 11 a 10 a 9 gnd a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v cc pgm a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 gnd a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 xx/v pp ce/pgm o 15 o 14 o 13 o 12 o 11 o 10 o 9 o 8 gnd o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 oe v cc a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 gnd a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 27c280 27c220 27c210 o 12 o 11 o 10 o 9 o 8 gnd nc o 7 o 6 o 5 o 4 a 13 a 12 a 11 a 10 a 9 gnd nc a 8 a 7 a 6 a 5 o 13 o 14 o 15 ce/pgm xx/v pp nc a 17 a 16 a 15 a 14 o 3 o 2 o 1 o 0 oe nc a 0 a 1 a 2 a 3 a 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 40 41 42 43 44 38 37 36 35 34 33 32 31 30 22 21 20 19 18 28 27 26 25 24 23 29 39 v cc dip nm27c240 ds011949-3 ds011949-2 top view
3 www.fairchildsemi.com nm27c240 4,194,304-bit (256k x 16) high performance cmos eprom absolute maximum ratings (note 1) storage temperature -65 c to +150 c all input voltages except a9 with respect to ground (note 10) -0.6v to +7v v pp and a9 with respect to ground -0.6v to +14v v cc supply voltage with respect to ground -0.6v to +7v esd protection >2000v all output voltages with respect to ground (note 10) v cc + 1.0v to gnd - 0.6v operating range range temperature v cc tolerance commercial 0 c to +70 c +5v 10% industrial -40v c to +85 c +5v 10% dc read characteristics over operating range with v pp = v cc symbol parameter conditions min max units v il input low level -0.5 0.8 v v ih input high level 2.0 v cc +1 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -2.5 ma 3.5 v i sb1 v cc standby current (cmos) ce = v cc 0.3v 100 m a i sb2 v cc standby current (ttl) ce = v ih 1ma i cc v cc active current ce = oe = v il , i/o = 0 ma f=5 mhz 40 ma i pp v pp supply current v pp = v cc 10 m a i li input load current v in = 5.5v or gnd -1 1 m a i lo output leakage current v out = 5.5v or gnd -10 10 m a ac read characteristics over operating range with v pp = v cc symbol parameter 100 120 150 units min max min max min max t acc address to output delay 100 120 150 ns t ce ce to output delay 100 120 150 t oe oe to output delay 50 50 50 t df (note 2) output disable to output float 35 35 45 t oh (note 2) output hold from addresses ce or 0 0 0 oe , whichever occurred first capacitance t a = +25?c, f = 1 mhz (note 2) symbol parameter conditions typ max units c in input capacitance v in = 0v 12 20 pf c out output capacitance v out = 0v 13 20 pf
4 www.fairchildsemi.com nm27c240 4,194,304-bit (256k x 16) high performance cmos eprom ac test conditions output load 1 ttl gate and c l = 100 pf (note 8) input rise and fall times 5 ns input pulse levels 0.45v to 2.4v timing measurement reference level inputs 0.8v and 2v outputs 0.8v and 2v ac waveforms (notes 6, 7) (note 9) note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: this parameter is only sampled and is not 100% tested. note 3: oe may be delayed up to t acc Ct oe after the falling edge of ce without impacting t acc . note 4: the t df and t cf compare level is determined as follows: high to tri-state ? , the measured v oh1 (dc) - 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 5: tri-state may be attained using oe or ce . note 6: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. note 7: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 8: 1 ttl gate: i ol = 1.6 ma, i oh = -400 m a. c l : 100 pf includes fixture capacitance. note 9: v pp may be connected to v cc except during programming. note 10: inputs and outputs can undershoot to -2.0v for 20 ns max. t oh t df notes 4, 5 t cf notes 4, 5 t acc note 3 t oe note 3 high z 2.0v 0.8v output 2.0v 0.8v oe 2.0v 0.8v ce 2.0v 0.8v adresses high z addresses valid t ce ds011949-4
5 www.fairchildsemi.com nm27c240 4,194,304-bit (256k x 16) high performance cmos eprom dc electrical characteristics (notes 11, 12, 13, 14) symbol parameter conditions min typ max units t as address setup time 1 m s t oes oe setup time 1 m s t ds data setup time 1 2.4 m s t vps v pp setup time 1 m s t vcs v cc setup time 1 m s t ah address hold time 0 m s t dh data hold time 1 m s t df output enable to output float delay ce = v il 060ns t pw program pulse width 45 50 105 m s t oe data valid from oe ce = v il 100 ns i pp v pp supply current during programming pulse ce = v il , pgm = v il 30 ma i cc v cc supply current 30 ma t a temperature ambient 20 25 30 c v cc power supply voltage 6.25 6.5 6.75 v v pp programming supply voltage 12.5 12.75 13.0 v t fr input rise, fall time 5 ns v il input low voltage 0.0 0.45 v v ih input high voltage 2.4 4.0 v t in input timing reference voltage 0.8 2.0 v t out output timing reference voltage 0.8 2.0 v programming waveforms (note 13) note 11: fairchilds standard product warranty applies only to devices programmed to specifications described herein. note 12: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 13: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v pp , v cc to gnd to suppress spurious voltage transients which may damage the device. note 14: during power up the ce/pgm pin must be brought high ( v ih ) either coincident with or before power is applied to v pp . t pw 2.0v 0.8v 12.75v 6.25v 2.0v 0.8v adresses address n t df program program verify data in stable add n data out valid add n data v cc v pp t as t ah t oes t oe high z 2.0v 0.8v oe ce/pgm t ds 2.0v 0.8v t dh t vcs t vps ds011949-5
6 www.fairchildsemi.com nm27c240 4,194,304-bit (256k x 16) high performance cmos eprom turbo programming algorithm flow chart figure 1. v cc = 6.5v v pp = 12.75v n = 0 address = first location check all bytes 1st: v cc = v pp = 6.0v 2nd: v cc = v pp = 4.2v program one 50 s pulse increment n address = first location verify byte n = 10? device failed last address ? increment address n = 0 program one 50 s pulse increment address verify byte last address ? pass no fail yes yes pass no fail no yes ds011949-6 note: the standard national semiconductor algorithm may also be used but it will have longer programming time.
7 www.fairchildsemi.com nm27c240 4,194,304-bit (256k x 16) high performance cmos eprom functional description device operation the six modes of operation of the eprom are listed in table 1. it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and v pp . v cc power supply must be at 12.75v during the three programming modes, and must be at 5v in the other three modes. the v cc power supply must be at 6.5v during the three programming modes, and at 5v in the other three modes. mode selection the modes of operation of the nm27c240 are listed in table 1. a single 5v power supply is required in the read mode. all inputs are ttl levels except for v pp and a9 for device signature. table 1. modes selection pins mode ce/ oe v pp v cc outputs pgm read v il v il x 5.0v d out output disable x v ih x 5.0v high z standby v ih x x 5.0v high z programming v il v ih 12.75v 6.25v d in program v il v il 12.75v 6.25v d out verify program v ih x 12.75v 6.25v high z inhibit note 15: x can be v il or v ih . read mode the eprom has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of the device selection. assuming that the addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs t oe after falling edge of oe, assuming that ce has been low and addresses have been stable for at least t acc - t oe . standby mode the eprom standby mode reduces the active power dissipation by over 99%, from 165 mw to 0.55 mw. the eprom is placed in the standby mode by applying a cmos high signal to the ce input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output disable the eprom is placed in output disable by applying a ttl high signal to the oe input. when in output disable all circuitry is enabled, except the outputs are in a high impedance state (tri- state). output or-tying because the eprom is usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. the complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ce be decoded and used as the primary device selecting function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on the v pp or a9 pin will damage the eprom. initially, and after erasure, all bits of the eprom are in the 1s state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be programmed, both 1s and 0s can be presented in the data word. the only way to change a 0 to a 1 is by ultraviolet light erasure. the eprom is in the programming mode when the v pp power supply is at 12.75v and oe is at v ih . it is required that at least a 0.1 m f capacitor be placed across v pp , v cc to ground to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 16 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. when the address and data are stable, and active low, ttl program pulse is applied to the pgm input. a program pulse must be applied at each address location to be programmed. the eprom is programmed with the turbo programming algorithm shown in figure 1. each address is programmed with a series of 50 m s pulses until it verifies good, up to a maximum of 10 pulses. most memory cells will program with a single 50 m s pulse. (the standard national semiconductor algorithm may also be used but it will have longer programming time.) the eprom must not be programmed with a dc signal applied to the pgm input. programming multiple eprom in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. like inputs of the parallel eprom may be con- nected together when they are programmed with the same data. a low level ttl pulse applied to the pgm input programs the paralleled eprom. program inhibit programming multiple eproms in parallel with different data is also easily accomplished. except for ce all like inputs (including oe and pgm) of the parallel eprom may be common. a ttl low level program pulse applied to an eproms pgm input with ce at v il and v pp at 12.75v will program that eprom. a ttl high level ce input inhibits the other eproms from being programmed. program verify a verify should be performed on the programmed bits to determine whether they were correctly programmed. the verify may be performed with v pp at 12.75v. v pp must be at v cc , except during programming and program verify.
8 www.fairchildsemi.com nm27c240 4,194,304-bit (256k x 16) high performance cmos eprom functional description (continued) after programming opaque labels should be placed over the eprom window to prevent unintentional erasure. covering the window will also prevent temporary functional failure due to the generation of photo currents. manufacturers identification code the eprom has a manufacturers identification code to aid in programming. when the device is inserted in an eprom pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. the manufacturers identification code, shown in table 2, specifi- cally identifies the manufacturer and device type. the code for the nm27c240 is 8fee, where 8f designates that it is made by fairchild semiconductor, and ee designates a 4 megabit (256k x 16) part. the code is accessed by applying 12v 0.5% to address pin a9. addresses a1Ca8, a10Ca15, and all control pins are held at v il . address pin a0 is held at v il for the manufacturers code, and held at v ih for the device code. the code is read on the lower eight data pins, o0Co7. proper code access is only guaranteed at 25 c 5 c. erasure characteristics the erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms (?). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000?C4000? range. the recommended erasure procedure for the eprom is expo- sure to short wave ultraviolet light which has a wavelength of 2537?. the integrated dose (i.e., uv intensity x exposure time) for erasure should be minimum of 15w-sec/cm 2 . the eprom should be placed within 1 inch of the lamp tubes during erasure. some lamps have a filter on their tubes which should be removed before erasure. an erasure system should be calibrated periodically. the distance from lamp to device should be maintained at one inch. the erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4). lamps lose intensity as they age. when a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make sure full erasure is occurring. incomplete erasure will cause symptoms that can be misleading. program- mers, components, and even system designs have been errone- ously suspected when incomplete erasure was the problem. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc , has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. the associated v cc transient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces. table 2. manufacturers identification code pins a0 a9 o7 o6 o5 o4 o3 o2 o1 o0 hex (21) (31) (12) (13) (14) (15) (16) (17) (18) (19) data manufacturer code v il 12v1 000 11 11 8f device code v ih 12v1 110 11 10 ee
9 www.fairchildsemi.com nm27c240 4,194,304-bit (256k x 16) high performance cmos eprom 40-lead ceramic dual-in-line package (q) order number nm27c240qxxx package number j40bq 44-lead plastic chip carrier (v) order number nm27c240vxxx package number v44a physical dimensions inches (millimeters) unless otherwise noted 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 uv window size and configuration determined by device size 0.90 ?0.110 [2.29 ?2.79] typ 86 94 typ 0.098 [2.49] max (both ends) 0.180 [4.57] max 0.040 [1.02] typ 0.005 [0.13] min glass sealant 0.030 - 0.055 (0.76 -1.40) rad typ 0.020 0.070 [0.51 ?.78] 0.125 ?0.200 [3.18 ?5.08] 0.150 [3.81] min 0.015 - 0.035 (0.38 - 0.89) rad 2.096 (53.24) max 0.180 [4.57] max 0.225 [5.72] max 0.610 (15.49) max glass 0.590 (14.99) max ceramic 0.010 [0.25] max 0.590 0.620 [14.99 ?15.75] 0.008 ?0.012 [0.20 ?0.30] 0.625 ?0.710 [15.88 ?18.03] 90 - 100 0.590-0630 [14.99-16.00] 0.013-0.021 [0.33-0.53] 0.165-0.180 [4.19-4.57] 0.020 [0.51] min typ typ typ 0.026-0.032 [0.66-0.81] typ 0.045 [1.14] 45?x 0.045 [1.14] 45? pin 1 indent 29 39 40 44 1 5 28 18 17 7 0.650-0.656 [16.51-16.66] 0.50 [1.27] typ 0.500 [12.70] typ typ 0.685-0.695 [17.40?7.65] typ 0.090-0.130 [2.29-3.30] typ
10 www.fairchildsemi.com nm27c240 4,194,304-bit (256k x 16) high performance cmos eprom physical dimensions inches (millimeters) unless otherwise noted 40-lead plastic molded dual-in-line (n) order number nm27c240nxxx 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0.0.18 0.003 (0.457 0.076) 86 94 typ 0.125?.150 (3.048?.81) 0.100 0.010 (2.540 0.254) 0.040 - 0.090 (1.016 - 2.286) 0.062 (1.575) rad 1.90 ?2.10 (48.26 ?53.34) 0.125?.165 (3.175?.191) 0.490 - 0.550 (12.446 - 13.97) 0.580 (14.73) min 0.008 0.015 (0.203 0.381) 95 5 pin #1 ident 0.145?.210 (3.683?.334) 0.015 (0.381) min 0.050 (1.270) 0.035 - 0.070 (0.889 - 1.778) 0.600?.620 (15.240?5.748) 0.030 (0.762) max fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm27c256 262,144-bit (32k x 8) high performance cmos eprom nm27c256 262,144-bit (32k x 8) high performance cmos eprom general description the nm27c256 is a 256k electrically programmable read only memory. it is manufactured in fairchilds latest cmos split gate eprom technology which enables it to operate at speeds as fast as 90 ns access time over the full operating range. the nm27c256 provides microprocessor-based systems exten- sive storage capacity for large portions of operating system and application software. its 90 ns access time provides high speed operation with high-performance cpus. the nm27c256 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. frequently-used software routines are quickly executed from eprom storage, greatly enhancing system utility. the nm27c256 is configured in the standard eprom pinout which provides an easy upgrade path for systems which are currently using standard eproms. block diagram july 1998 the nm27c256 is one member of a high density eprom family which range in densities up to 4 mb. features n high performance cmos 90 ns access time n jedec standard pin configuration 28-pin pdip package 32-pin chip carrier 28-pin cerdip package n drop-in replacement for 27c256 or 27256 n manufacturers identification code ds010833-1 output enable and chip enable logic y decoder x decoder . . . . . . . . . output buffers y gating data outputs o 0 - o 7 v cc gnd v pp oe ce/pgm a 0 - a 14 address inputs ? 1998 fairchild semiconductor corporation
2 www.fairchildsemi.com nm27c256 262,144-bit (32k x 8) high performance cmos eprom connection diagrams commercial temp. range (0 c to +70 c) v cc = 5v 10% parameter/order number access time (ns) nm27c256 q, n, v 90 90 nm27c256 q, n, v 100 100 nm27c256 q, n, v 120 120 nm27c256 q, n, v 150 150 nm27c256 q, n, v 200 200 extended temp. range (-40 c to +85 c) v cc = 5v 10% parameter/order number access time (ns) nm27c256 qe, ne, ve 120 120 nm27c256 qe, ne, ve 150 150 nm27c256 qe, ne, ve 200 200 note: surface mount plcc package available for commercial and extended temperature ranges only. package types: nm27c256 q, n, v xxx q = quartz-windowed ceramic dip n = plastic otp dip v = surface-mount plcc ? all packages conform to the jedec standard. ? all versions are guaranteed to function for slower speeds. pin names symbol description a0Ca14 addresses ce/pgm chip enable/program oe output enable o0Co7 outputs xx dont care (during read) plcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd a 19 a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c080 27c040 27c040 xx/v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd dlp nm27c256 v cc a 14 a 13 a 8 a 9 a 11 oe a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c512 27c512 xx/v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c010 xx/v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c020 27c020 27c010 v cc xx/pgm a 17 a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 27c080 v cc a 18 a 17 a 14 a 13 a 8 a 9 a 11 oe/v pp a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 v cc a 18 a 17 a 14 a 13 a 8 a 9 a 11 oe a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 v cc xx/pgm xx a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc a 14 a 13 a 8 a 9 a 11 oe/v pp a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 note: compatible eprom pin configurations are shown in the blocks adjacent to the nm27c256 pins. a 8 a 9 a 11 xx oe a 10 ce/pgm o 7 o 6 a 6 a 5 a 4 a 3 a 2 a 1 a 0 xx o 0 a 7 a 12 v pp xx v cc a 14 a 13 o 1 o 2 gnd xx o 3 o 4 o 5 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 32 31 30 ds010833-2 ds010833-3 top
3 www.fairchildsemi.com nm27c256 262,144-bit (32k x 8) high performance cmos eprom absolute maximum ratings (note 1) storage temperature -65 c to +150 c all input voltages except a9 with respect to ground -0.6v to +7v v pp and a9 with respect to ground -0.7v to +14v v cc supply voltage with respect to ground -0.6v to +7v esd protection > 2000v all output voltages with respect to ground v cc + 1.0v to gnd -0.6v operating range range temperature v cc comml 0 c to +70 c +5v 10% industrial -40 c to +85 c +5v 10% read operation dc electrical characteristics over operating range with v pp = v cc symbol parameter test conditions min max units v il input low level -0.5 0.8 v v ih input high level 2.0 v cc +1 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -2.5 ma 3.5 v i sb1 v cc standby current ce = v cc 0.3v 100 m a (note 11) (cmos) i sb2 v cc standby current (ttl) ce = v ih 1ma i cc1 v cc active current ce = oe = v il ,f=5 mhz 35 ma ttl inputs inputs = v ih or v il , i/o = 0 ma i pp v pp supply current v pp = v cc 10 m a v pp v pp read voltage v cc - 0.7 v cc v i li input load current v in = 5.5v or gnd -1 1 m a i lo output leakage current v out = 5.5v or gnd -10 10 m a ac electrical characteristics over operating range with v pp = v cc symbol parameter 90 100 120 150 200 units min max min max min max min max min max t acc address to output delay 90 100 120 150 200 ns t ce ce to output delay 90 100 120 150 200 t oe oe to output delay 35 50 50 50 50 t df output disable to 30 30 35 45 45 (note 2) output float t oh output hold from 00000 (note 2) addresses, ce or oe, whichever occurred first capacitance (note 2) t a = +25?c, f = 1 mhz symbol parameter conditions typ max units c in input capacitance v in = 0v 6 12 pf c out output capacitance v out = 0v 9 12 pf
4 www.fairchildsemi.com nm27c256 262,144-bit (32k x 8) high performance cmos eprom ac test conditions output load 1 ttl gate and cl = 100 pf (note 8) input rise and fall times 5 ns input pulse levels 0.45 to 2.4v timing measurement reference level (note 10) inputs 0.8v and 2.0v outputs 0.8v and 2.0v ac waveforms (note 6) (note 7) (note 9) note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating on ly and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: this parameter is only sampled and is not 100% tested. note 3: oe may be delayed up to t acc - t oe after the falling edge of ce without impacting t acc . note 4: the t df and t cf compare level is determined as follows: high to tri-state ? , the measured v oh1 (dc) - 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 5: tri-state may be attained using oe or ce. note 6: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. note 7: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 8: ttl gate: i ol = 1.6 ma, i oh = -400 m a. c l = 100 pf includes fixture capacitance. note 9: v pp may be connected to v cc except during programming. note 10: inputs and outputs can undershoot to -2.0v for 20 ns max. note 11: cmos inputs: v il = gnd 0.3v, v ih = v cc 0.3v. programming characteristics (note 12) (note 13) (note 14) (note 15) symbol parameter conditions min typ max units addresses valid valid output hi-z hi-z 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v addresses ce oe output t oe (note 3) t acc (note 3) t ce t ce (notes 4, 5) t oh t df (notes 4, 5) ds010833-4
5 www.fairchildsemi.com nm27c256 262,144-bit (32k x 8) high performance cmos eprom programming characteristics (note 12) (note 13) (note 14) (note 15) (continued) symbol parameter conditions min typ max units t as address setup time 1 m s t oes oe setup time 1 m s t vps v pp setup time 1 m s t vcs v cc setup time 1 m s t ds data setup time 1 m s t ah address hold time 0 m s t dh data hold time 1 m s t df output enable to output ce = v il 060ns float delay t pw program pulse width 45 50 105 m s t oe data valid from oe ce = v il 100 ns i pp v pp supply current ce = v il 30 ma during programming pulse i cc v cc supply current 50 ma t a temperature ambient 20 25 30 c v cc power supply voltage 6.25 6.5 6.75 v v pp programming supply voltage 12.5 12.75 13.0 v t fr input rise, fall time 5 ns v il input low voltage 0.0 0.45 v v ih input high voltage 2.4 4.0 v t in input timing reference voltage 0.8 2.0 v t out output timing reference voltage 0.8 2.0 v programming waveforms (note 14) note 12: fairchilds standard product warranty applies to devices programmed to specifications described herein. note 13: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 14: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v pp , v cc to gnd to suppress spurious voltage transients which may damage the device. note 15: during power up the pgm pin must be brought high ( 3 v ih ) either coincident with or before power is applied to v pp . address n data in stable add n data out valid add n 2.0v 0.8v 2.0v 0.8v 5.25v 12.75v 2.0v 0.8v 2.0v 0.8v addresses data ce v pp v cc oe t oe t oes t pw t vps t vcs t ds t as t ah t df t dh program program verify ds010833-5
6 www.fairchildsemi.com nm27c256 262,144-bit (32k x 8) high performance cmos eprom turbo programming algorithm flow chart v cc = 6.5v v pp = 12.75v n = 0 address = first location check all bytes 1st: v cc = v pp = 6.0v 2nd: v cc = v pp = 4.3v program one 50 s pulse increment n address = first location verify byte n = 10? device failed last address ? increment address n = 0 program one 50 s pulse increment address verify byte last address ? pass no fail yes yes pass no fail no yes ds010833-6 note: the standard national semiconductor algorithm may also be used but it will have longer programming time. figure 1.
7 www.fairchildsemi.com nm27c256 262,144-bit (32k x 8) high performance cmos eprom functional description device operation the six modes of operation of the eprom are listed in table 1. it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and v pp . the v pp power supply must be at 12.75v during the three programming modes, and must be at 5v in the other three modes. the v cc power supply must be at 6.5v during the three programming modes, and at 5v in the other three modes. read mode the eprom has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce/pgm) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs t oe after the falling edge of oe, assuming that ce/pgm has been low and addresses have been stable for at least t acc Ct oe . standby mode the eprom has a standby mode which reduces the active power dissipation by over 99%, from 385 mw to 0.55 mw. the eprom is placed in the standby mode by applying a cmos high signal to the ce/pgm input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output disable the eprom is placed in output disable by applying a ttl high signal to the oe input. when in output disable all circuitry is enabled, except the outputs are in a high impedance state (tri- state). output or-typing because the eprom is usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ce/pgm be decoded and used as the primary device select- ing function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on pin 1 (v pp ) will damage the eprom. initially, and after each erasure, all bits of the eprom are in the 1s state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be pro- grammed, both 1s and 0s can be presented in the data word. the only way to change a 0 to a 1 is by ultraviolet light erasure. the eprom is in the programming mode when the v pp power supply is at 12.75v and oe is at v ih . it is required that at least a 0.1 m f capacitor be placed across v pp , v cc to ground to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 8 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. when the address and data are stable, an active low, ttl program pulse is applied to the ce/pgm input. a program pulse must be applied at each address location to be programmed. the eprom is programmed with the turbo programming algorithm shown in figure 1. each address is programmed with a series of 50 m s pulses until it verifies good, up to a maximum of 10 pulses. most memory cells will program with a single 50 m s pulse. (the standard national semiconductor algorithm may also be used but it will have longer programming time.) the eprom must not be programmed with a dc signal applied to the ce/pgm input. programming multiple eprom in parallel with the same data can be easily accomplished due to the simplicity of the programming requirments. like inputs of the parallel eprom may be connected together when they are programmed with the same data. a low level ttl pulse applied to the ce/pgm input programs the paralleled eprom. program inhibit programming multiple eproms in parallel with different data is also easily accomplished. except for ce/pgm, all like inputs (including oe) of the parallel eproms may be common. a ttl low level program pulse applied to an eproms ce/pgm input with v pp at 12.75v will program that eprom. a ttl high level ce/ pgm input inhibits the other eproms from being programmed. program verify a verify should be performed on the programmed bits to determine whether they were correctly programmed. the verify may be performed with v pp at 12.75v. v pp must be at v cc , except during programming and program verify. after programming opaque labels should be placed over the eprom window to prevent unintentional erasure. covering the window will also prevent temporary functional failure due to the generation of photo currents. manufacturers identification code the eprom has a manufacturers identification code to aid in programming. when the device is inserted in an eprom pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. the manufacturers identification code, shown in table 2, specifi- cally identifies the manufacturer and device type. the code for nm27c256 is 8f04, where 8f designates that it is made by fairchild semiconductor, and 04 designates a 256k part. the code is accessed by applying 12v 0.5v to address pin a9. addresses a1Ca8, a10Ca16, and all control pins are held at v il . address pin a0 is held at v il for the manufacturers code, and held at v ih for the device code. the code is read on the eight data pins, o0 Co7. proper code access is only guaranteed at 25 c to 5 c.
8 www.fairchildsemi.com nm27c256 262,144-bit (32k x 8) high performance cmos eprom functional description (continued) erasure characteristics the erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms (?). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000?C4000? range. the recommended erasure procedure for the eprom is expo- sure to short wave ultraviolet light which has a wavelength of 2537?. the integrated dose (i.e., uv intensity x exposure time) for erasure should be a minimum of 15w-sec/cm 2 . the eprom should be placed within 1 inch of the lamp tubes during erasure. some lamps have a filter on their tubes which should be removed before erasure an erasure system should be calibrated periodically. the distance from lamp to device should be maintained at one inch. the erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4). lamps lose intensity as they age. when a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. incomplete erasure will cause symptoms that can be misleading. program- mers, components, and even system designs have been errone- ously suspected when incomplete erasure was the problem. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc, has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent of the output capacitance loading of the device. the associated v cc transient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces. mode selection the modes of operation of nm27c256 listed in table 1. a single 5v power supply is required in the read mode. all inputs are ttl levels except for v pp and a9 for device signature. table 1. modes selection pins ce/pgm oe v pp v cc outputs mode read v il v il v cc 5.0v d out output disable x v ih v cc 5.0v high-z (note 16) standby v ih xv cc 5.0v high-z programming v il vih 12.75v 6.25v d in program verify v ih v il 12.75v 6.25v d out program inhibit v ih v ih 12.75v 6.25v high-z note 16: x can be v il or v ih . table 2. manufacturers identification code pins a0 a9 o7 o6 o5 o4 o3 o2 o1 o0 hex (10) (24) (19) (18) (17) (16) (15) (13) (12) (11) data manufacturer code v il 12v100011118f device code v ih 12v0000010004
9 www.fairchildsemi.com nm27c256 262,144-bit (32k x 8) high performance cmos eprom physical dimensions inches (millimeters) unless otherwise noted 1.450 [36.83] max 28 1 15 14 r 0.025 [0.64] r 0.030-0.055 [0.76 - 1.40] typ 0.280 0.010 [7.11 0.25] uv window 0.600 [15.24] max glass 0.520 0.006 [13.21 0.15] 0.175 max 0.060-0.100 typ 0.050-0.060 typ 0.015-0.021 typ 86 -94 typ 0.150 min typ 0.015 -0.060 typ 0.090-0.110 typ 0.005 min typ 0.225 max typ 0.125 min typ 0.590-0.620 [14.99 - 15.75] glass sealant 95 5 typ 0.685 +0.025 -0.060 17.40 +0.64 -1.52 0.010 0.002 [0.25 0.05] typ 0.625 +0.025 -0.015 0.008-0.015 (0.229-0.381) 15.88 +0.635 -0.381 0.580 (14.73) 95 5 0.600 - 0.620 (15.24 - 15.75) 0.030 (0.762) max ( ( 0.108 0.010 (2.540 0.254) 0.018 0.003 (0.457 0.076) 0.20 (0.508) 0.125-0.145 (3.175-3.583) 0.125-0.165 (3.175-4.191) 0.050 (1.270) typ 0.053 - 0.069 (1.346 - 1.753) 0.050 0.015 (1.270 0.381) min 88 94 typ 12 34 28 27 26 25 1.393 - 1.420 (35.38 - 36.07) 0.510 0.005 (12.95 0.127) 0.062 (1.575) pin #1 ident 5 24 6 23 22 21 20 19 18 17 16 7 8 9 1011121314 15 rad 28-lead plastic one-time-programmable dual-in-line package order number nm27c256nxxx package number n28b uv window cavity dual-in-line cerdip package (q) order number nm27c256qxxx package number j28aq
10 www.fairchildsemi.com nm27c256 262,144-bit (32k x 8) high performance cmos eprom physical dimensions inches (millimeters) unless otherwise noted 0.007[0.18] a s s f-g 0.007[0.18] b s d-e 0.449-0.453 [11.40-11.51] s 0.045 [1.143] 0.000-0.010 [0.00-0.25] polished optional 0.585-0.595 [14.86-15.11] 0.549-0.553 [13.94-14.05] -b- -f- -e- -g- 0.050 21 29 30 1 4 20 14 13 5 -d- 0.007[0.18] b s d-e s 0.002[0.05] b s -a- 0.485-0.495 [12.32-12.57] 0.007[0.18] a s s f-g a 0.002[0.05] s 0.007[0.18] h s s d-e, f-g 0.010[0.25] b a s d-e, f-g 0.118-0.129 [3.00-3.28] l b b 45 x 0.042-0.048 [1.07-1.22] 0.026-0.032 [0.66-0.81] typ 0.0100 [0.254] 0.030-0.040 [0.76-1.02] r 0.005 [0.13] max 0.020 [0.51] 0.045 [1.14] detail a typical rotated 90 0.027-0.033 [0.69-0.84] 0.025 [0.64] min 0.025 [0.64] min 0.031-0.037 [0.79-0.94] 0.053-0.059 [1.65-1.80] 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64] 0.065-0.071 [1.65-1.80] 0.021-0.027 [0.53-0.69] section b-b typical s 0.007[0.18] c m s d-e, f-g 0.015[0.38] c d-e, f-g 0.490-0530 [12.45-13.46] 0.078-0.095 [1.98-2.41] 0.013-0.021 [0.33-0.53] 0.004[0.10] 0.123-0.140 [3.12-3.56] see detail a -j- -c- 0.400 [10.16] ( ) typ 0.541-0.545 [13.74-13-84] 0.023-0.029 [0.58-0.74] 0.106-0.112 [2.69-2.84] 60 ? 0.015 [0.38] base plane -h- min typ s 32-lead plastic leaded chip carrier (plcc) order number nm27c256vxxx package number va32a
11 www.fairchildsemi.com nm27c256 262,144-bit (32k x 8) high performance cmos eprom fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm27c512 524,288-bit (64k x 8) high performance cmos eprom nm27c512 524,288-bit (64k x 8) high performance cmos eprom general description the nm27c512 is a high performance 512k uv erasable electri- cally programmable read only memory (eprom). it is manufac- tured using fairchilds proprietary cmos amg? eprom tech- nology for an excellent combination of speed and economy while providing excellent reliability. the nm27c512 provides microprocessor-based systems storage capacity for portions of operating system and application soft- ware. its 90 ns access time provides no wait-state operation with high-performance cpus. the nm27c512 offers a single chip solution for the code storage requirements of 100% firmware- based equipment. frequently-used software routines are quickly executed from eprom storage, greatly enhancing system utility. the nm27c512 is configured in the standard jedec eprom pinout which provides an easy upgrade path for systems which are currently using standard eproms. block diagram july 1998 the nm27c512 is one member of a high density eprom family which range in densities up to 4 megabit. features n high performance cmos 90 ns access time n fast turn-off for microprocessor compatibility n manufacturers identification code n jedec standard pin configuration 28-pin pdip package 32-pin chip carrier 28-pin cerdip package ds010834-1 amg is a trademark of wsi, inc. ? 1998 fairchild semiconductor corporation output enable and chip enable logic y decoder x decoder . . . . . . . . . output buffers 524,288-bit cell matrix data outputs o 0 - o 7 v cc gnd v pp oe ce/pgm a 0 - a 15 address inputs
2 www.fairchildsemi.com nm27c512 524,288-bit (64k x 8) high performance cmos eprom connection diagrams compatible eprom pin configurations are shown in the blocks adjacement to the nm27c512 pins. commercial temp range (0 c to +70 c) parameter/order number access time (ns) nm27c512 q, n, v 90 90 nm27c512 q, n, v 120 120 nm27c512 q, n, v 150 150 industrial temp range (-40 c to +85 c) parameter/order number access time (ns) nm27c512 qe, ne, ve 120 120 nm27c512 qe, ne, ve 150 150 q = quartz-windowed ceramic dip package n = plastic dip package v = plcc package ? all packages conform to the jedec standard. ? all versions are guaranteed to function for slower speeds. pin names a0Ca15 addresses ce/pgm chip enable/program oe output enable o0Co7 outputs nc dont care (during read) plcc a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o0 o 1 o 2 gnd v cc a 14 a 13 a 8 a 9 a 11 oe/v pp a 10 ce/pgm o7 o 6 o 5 o4 o 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc xx/pgm xx a 14 a 13 a 8 a 9 a 11 oe a10 ce o7 o 6 o 5 o4 o 3 v cc xx/pgm a 17 a 14 a 13 a 8 a 9 a 11 oe a10 ce o7 o 6 o 5 o4 o 3 v cc a 14 a 13 a 8 a 9 a 11 oe a10 ce/pgm o7 o 6 o 5 o4 o 3 27c256 27c010 27c020 27c040 27c080 v cc a 18 a 17 a 14 a 13 a 8 a 9 a 11 oe a10 ce/pgm o7 o 6 o 5 o4 o 3 v cc a 18 a 17 a 14 a 13 a 8 a 9 a 11 oe/ v pp a10 ce/pgm o7 o 6 o 5 o4 o 3 27c080 27c040 27c020 27c010 27c256 a 19 a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd xx/ v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd xx/ v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd xx/ v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd dip nm27c512 a8 a9 a11 nc oe/vpp a10 ce/pgm o7 o8 a6 a5 a4 a3 a2 a1 a0 nc o0 a7 a12 a15 nc vcc a14 a13 o1 o2 gnd nc o3 o4 o5 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 32 31 30 ds010834-2 ds010834-3
3 www.fairchildsemi.com nm27c512 524,288-bit (64k x 8) high performance cmos eprom absolute maximum ratings (note 1) storage temperature -65 c to +150 c all input voltages except a9 with respect to ground -0.6v to +7v v pp and a9 with respect to ground -0.7v to +14v v cc supply voltage with respect to ground -0.6v to +7v esd protection (mil std. 883, method 3015.2) >2000v all output voltages with respect to ground v cc + 1.0v to gnd -0.6v operating range range temperature v cc tolerance commercial 0 c to +70 c +5v 10% industrial -40 c to +85 c +5v 10% read operation dc electrical characteristics symbol parameter test conditions min max units v il input low level -0.5 0.8 v v ih input high level 2.0 v cc +1 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -2.5 ma 3.5 v i sb1 v cc standby current (cmos) ce = v cc 0.3v 100 m a i sb2 v cc standby current ce = v ih 1ma i cc1 v cc active current ce = oe = v il f = 5 mhz 40 ma i cc2 v cc active current ce = gnd, f = 5 mhz cmos inputs inputs = v cc or gnd, i/o = 0 ma 35 ma c, e temp ranges i pp v pp supply current v pp = v cc 10 m a v pp v pp read voltage v cc - 0.7 v cc v i li input load current v in = 5.5v or gnd -1 1 m a i lo output leakage current v out = 5.5v or gnd -10 10 m a ac electrical characteristics symbol parameter 90 120 150 units min max min max min max t acc address to output delay 90 120 150 ns t ce ce to output delay 90 120 150 t oe oe to output delay 40 50 50 t df output disable to 35 25 45 output float t oh output hold from addresses, ce or oe, 0 0 0 whichever occurred first
4 www.fairchildsemi.com nm27c512 524,288-bit (64k x 8) high performance cmos eprom capacitance t a = +25 c, f = 1 mhz (note 2) symbol parameter conditions typ max units c in1 input capacitance v in = 0v 6 12 pf except oe/v pp c out output capacitance v out = 0v 9 12 pf c in2 oe/v pp input v in = 0v 20 25 pf capacitance ac test conditions output load 1 ttl gate and c l = 100 pf (note 8) input rise and fall times 5 ns input pulse levels 0.45v to 2.4v timing measurement reference level (note 9) inputs 0.8v and 2v outputs 0.8v and 2v ac waveforms (notes 6, 7) note 1: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: this parameter is only sampled and is not 100% tested. note 3: oe may be delayed up to t acc Ct oe after the falling edge of ce without impacting t acc . note 4: the t df and t cf compare level is determined as follows: high to tri-state, the measured v oh1 (dc) - 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 5: tri-state may be attained using oe or ce . note 6: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. note 7: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 8: 1 ttl gate: i ol = 1.6 ma, i oh = -400 m a. c l : 100 pf includes fixture capacitance. note 9: inputs and outputs can undershoot to -2.0v for 20 ns max. address valid valid output hi-z 2v 0.8v 2v 0.8v 2v 0.8v address output ce oe t ce 2v 0.8v (note 3) (note 3) t df (note 4, 5) (note 4, 5) t oh hi-z t oe acc t cf t ds010834-4
5 www.fairchildsemi.com nm27c512 524,288-bit (64k x 8) high performance cmos eprom programming characteristics (note 10) and (note 11) symbol parameter conditions min typ max units t as address setup time 1 m s t oes oe setup time 1 m s t ds data setup time 1 m s t vcs v cc setup time 1 m s t ah address hold time 0 m s t dh data hold time 1 m s t cf chip enable to output float delay oe = v il 060ns t pw program pulse width 45 50 105 m s t oeh oe hold time 1 m s t dv data valid from ce oe = v il 250 ns t prt oe pulse rise time 50 ns during programming t vr v pp recovery time 1 m s i pp v pp supply current during ce = v il 30 ma programming pulse oe = v pp i cc v cc supply current 50 ma t r temperature ambient 20 25 30 c v cc power supply voltage 6.25 6.5 6.75 v v pp programming supply voltage 12.5 12.75 13 v t fr input rise, fall time 5 ns v il input low voltage 0 0.45 v v ih input high voltage 2.4 4 v t in input timing reference voltage 0.8 2 v t out output timing reference voltage 0.8 2 v programming waveforms note 10: fairchilds standard product warranty applies to devices programmed to specifications described herein. note 11: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 12: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v cc to gnd to suppress spurious voltage transients which may damage the device. t as program program verify address n t cf hi-z t ds t dh t vps t pw t oeh t ah 2.0v 0.8v 2.0v 0.8v 6.25v addresses data oe/v pp v cc 0.8v t oes data out valid add n data in stable add n 2.0v 0.8v t dv t prt 12.75v t vcs t vr ce/pgm ds010834-5
6 www.fairchildsemi.com nm27c512 524,288-bit (64k x 8) high performance cmos eprom turbo programming algorithm flow chart figure 1. v cc = 6.5v v pp = 12.75v n = 0 address = first location check all bytes 1st: v cc = v pp = 6.0v 2nd: v cc = v pp = 4.3v program one 50 s pulse increment n address = first location verify byte n = 10? device failed last address ? increment address n = 0 program one 50 s pulse increment address verify byte last address ? pass no fail yes yes pass no fail no yes ds010834-6 note: the standard national semiconductor algorithm may also be used but it will take longer programming time.
7 www.fairchildsemi.com nm27c512 524,288-bit (64k x 8) high performance cmos eprom functional description device operation the six modes of operation of the eprom are listed in table1. it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and oe/v pp . the oe/v pp power supply must be at 12.75v during the three programming modes, and must be at 5v in the other three modes. the v cc power supply must be at 6.5v during the three programming modes, and at 5v in the other three modes. read mode the eprom has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce/pgm) is the power control and should be used for device selection. output enable (oe/v pp ) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs t oe after the falling edge of oe, assuming that ce has been low and addresses have been stable for at least t acc C t oe . standby mode the eprom has a standby mode which reduces the active power dissipation by over 99%, from 220 mw to 0.55 mw. the eprom is placed in the standby mode by applying a cmos high signal to the ce/pgm input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output disable the eprom is placed in output disable by applying a ttl high signal to the oe input. when in output disable all circuitry is enabled, except the outputs are in a high impedance state (tri- state). output or-typing because the eprom is usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ce/pgm be decoded and used as the primary device select- ing function, while oe/v pp be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on pin 22 (oe/v pp ) will damage the eprom. initially, and after each erasure, all bits of the eprom are in the 1s state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be pro- grammed, both 1s and 0s can be presented in the data word. the only way to change a 0 to a 1 is by ultraviolet light erasure. the eprom is in the programming mode when the oe/v pp is at 12.75v. it is required that at least a 0.1 m f capacitor be placed across v cc to ground to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 8 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. when the address and data are stable, an active low, ttl program pulse is applied to the ce/pgm input. a program pulse must be applied at each address location to be programmed. the eprom is programmed with the turbo programming algo- rithm shown in figure 1. each address is programmed with a series of 50 m s pulses until it verifies good, up to a maximum of 10 pulses. most memory cells will program with a single 50 m s pulse. (the standard national semiconductor algorithm may also be used but it will have longer programming time.) the eprom must not be programmed with a dc signal applied to the ce/pgm input. programming multiple eprom in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. like inputs of the parallel eprom may be con- nected together when they are programmed with the same data. a low level ttl pulse applied to the ce/pgm input programs the paralleled eprom. program inhibit programming multiple eproms in parallel with different data is also easily accomplished. except for ce/pgm all like inputs (including oe/v pp ) of the parallel eproms may be common. a ttl low level program pulse applied to an eproms ce/pgm input with oe/v pp at 12.75v will program that eprom. a ttl high level ce/pgm input inhibits the other eproms from being pro- grammed. program verify a verify should be performed on the programmed bits to determine whether they were correctly programmed. the verify is accom- plished with oe/v pp and ce at v il . data should be verified t dv after the falling edge of ce. after programming opaque labels should be placed over the eprom window to prevent unintentional erasure. covering the window will also prevent temporary functional failure due to the generation of photo currents. manufacturers identification code the eprom has a manufacturers identification code to aid in programming. when the device is inserted in an eprom pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. the manufacturers identification code, shown in table 2, specifi- cally identifies the manufacturer and device type. the code for nm27c512 is 8f85, where 8f designates that it is made by fairchild semiconductor, and 85 designates a 512k part. the code is accessed by applying 12v 0.5v to address pin a9. addresses a1Ca8, a10Ca16, and all control pins
8 www.fairchildsemi.com nm27c512 524,288-bit (64k x 8) high performance cmos eprom functional description (continued) are held at v il . address pin a0 is held at v il for the manufacturers code, and held at v ih for the device code. the code is read on the eight data pins, o0 Co 7 . proper code access is only guaranteed at 25 c 5 c. erasure characteristics the erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms (?). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000?C4000? range. the recommended erasure procedure for the eprom is expo- sure to short wave ultraviolet light which has a wavelength of 2537?. the integrated dose (i.e., uv intensity x exposure time) for erasure should be minimum of 15w-sec/cm 2 . the eprom should be placed within 1 inch of the lamp tubes during erasure. some lamps have a filter on their tubes which should be removed before erasure an erasure system should be calibrated periodically. the distance from lamp to device should be maintained at one inch. the erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4). lamps lose intensity as they age. when a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. incomplete erasure will cause symptoms that can be misleading. program- mers, components, and even system designs have been errone- ously suspected when incomplete erasure was the problem. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc , has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. the associated v cc transient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces. mode selection the modes of operation of the nm27c512 are listed in table 1. a single 5v power supply is required in the read mode. all inputs are ttl levels excepts for v pp and a9 for device signature. table 1. mode selection pins ce/pgm oe/v pp v cc outputs mode read v il v il 5.0v d out output disable x (note 13) v ih 5.0v high z standby v ih x 5.0v high z programming v il 12.75v 6.25v d in program verify v il v il 6.25v d out program inhibit v ih 12.75v 6.25v high z note 13: x can be v il or v ih . table 2. manufacturers identification code pins a0 a9 07 06 05 04 03 02 01 00 hex (10) (24) (19) (18) (17) (16) (15) (13) (12) (11) data manufacturer code v il 12v100011118f device code v ih 12v1000010185
9 www.fairchildsemi.com nm27c512 524,288-bit (64k x 8) high performance cmos eprom uv window cavity dual-in-line cerdip package (jq) order number nm27c512q package number j28cq physical dimensions inches (millimeters) unless otherwise noted 28-lead plastic one-time-programmable dual-in-line order number nm27c512n package number n28b 0.008-0.012 [0.203-0.305] typ 0.090-0.110 [2.286-2.794] typ 0.060-0.100 [1.524-2.540] typ 0.015-0.021 [0.381-0.533] typ 0.033-0.045 [0.838-1.143] typ 0.225 [5.715] max typ 0.125 [3.175] min typ glass sealant 15 14 28 1 r 0.025 [0.635] 0.290-0.310 [7.366-7.874] u.v. window r 0.030-0.055 [0.762-1.397] typ 0.515-0.530 [13.081-13.462] 1.465 max [37.211] 0.050-0.060 [1.270-1.524] typ 0.180 [4.572] max 0.010 [0.254] max 0.015-0.060 [0.381-1.524] typ 86 -94 typ 0.590-0.620 [14.99-15.75] 0.685 +0.025 -0.060 [17.399 ] +0.635 -1.524 90 -100 typ 0.625 +0.025 -0.015 0.008-0.015 (0.229-0.381) 15.88 +0.635 -0.381 0.580 (14.73) 95 5 0.600 - 0.620 (15.24 - 15.75) 0.030 (0.762) max ( ( 0.108 0.010 (2.540 0.254) 0.018 0.003 (0.457 0.076) 0.20 (0.508) 0.125-0.145 (3.175-3.583) 0.125-0.165 (3.175-4.191) 0.050 (1.270) typ 0.053 - 0.069 (1.346 - 1.753) 0.050 0.015 (1.270 0.381) min 88 94 typ 12 34 28 27 26 25 1.393 - 1.420 (35.38 - 36.07) 0.510 0.005 (12.95 0.127) 0.062 (1.575) pin #1 ident 5 24 6 23 22 21 20 19 18 17 16 7 8 9 1011121314 15 rad
10 www.fairchildsemi.com nm27c512 524,288-bit (64k x 8) high performance cmos eprom physical dimensions inches (millimeters) unless otherwise noted 32-lead plastic leaded chip carrier (plcc) order number nm27c512v package number va32a 0.007[0.18] a s s f-g 0.007[0.18] b s d-e 0.449-0.453 [11.40-11.51] s 0.045 [1.143] 0.000-0.010 [0.00-0.25] polished optional 0.585-0.595 [14.86-15.11] 0.549-0.553 [13.94-14.05] -b- -f- -e- -g- 0.050 21 29 30 1 4 20 14 13 5 -d- 0.007[0.18] b s d-e s 0.002[0.05] b s -a- 0.485-0.495 [12.32-12.57] 0.007[0.18] a s s f-g a 0.002[0.05] s 0.007[0.18] h s s d-e, f-g 0.010[0.25] b a s d-e, f-g 0.118-0.129 [3.00-3.28] l b b 45 x 0.042-0.048 [1.07-1.22] 0.026-0.032 [0.66-0.81] typ 0.0100 [0.254] 0.030-0.040 [0.76-1.02] r 0.005 [0.13] max 0.020 [0.51] 0.045 [1.14] detail a typical rotated 90 0.027-0.033 [0.69-0.84] 0.025 [0.64] min 0.025 [0.64] min 0.031-0.037 [0.79-0.94] 0.053-0.059 [1.65-1.80] 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64] 0.065-0.071 [1.65-1.80] 0.021-0.027 [0.53-0.69] section b-b typical s 0.007[0.18] c m s d-e, f-g 0.015[0.38] c d-e, f-g 0.490-0530 [12.45-13.46] 0.078-0.095 [1.98-2.41] 0.013-0.021 [0.33-0.53] 0.004[0.10] 0.123-0.140 [3.12-3.56] see detail a -j- -c- 0.400 [10.16] ( ) typ 0.541-0.545 [13.74-13-84] 0.023-0.029 [0.58-0.74] 0.106-0.112 [2.69-2.84] 60 0.015 [0.38] base plane -h- min typ s fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com NM27C520 524,288-bit (64k x 8) multiplexed addresses/outputs otp cmos eprom NM27C520 524,288-bit (64k x 8) multiplexed addresses/outputs otp cmos eprom general description the NM27C520 is a high performance 512k cmos one-time programmable read only memory (eprom) manufactured using fairchild's proprietary cmos amg? eprom technology for an excellent combination of speed and economy while providing excellent reliability. it incorporates latches for the 8 lower order address bits to multiplex with the 8 data bits. this minimizes chip count, reduces cost, and simplifies the design of multiplexed bus systems. the NM27C520 provides microprocessor-based systems storage capacity for portions of operating system and application soft- ware. its 90ns access time provides no wait-state operation with high-performance cpus. the NM27C520 offers a single chip solution for the code storage requirements of 100% firmware- based equipment. frequently-used software routines are quickly executed from eprom storage, greatly enhancing system utility. the NM27C520 is one member of a high density eprom family which range in densities up to 4 megabit. block diagram july 1998 features n 8-bit multiplexed addresses/outputs n high performance cmos - 90 ns access time n fast turn-off for microprocessor compatibility n manufacturers identification code n jedec standard pin configuration - 20-lead soic package ds800001-1 amg? is a trademark of wsi, inc. ? 1998 fairchild semiconductor corporation v cc gnd oe/v pp ale ad 0 - ad 7 a 8 - a 15 8 oe, ale and program logic y decoder output buffers cell matrix x decoder latches 8
2 www.fairchildsemi.com NM27C520 524,288-bit (64k x 8) multiplexed addresses/outputs otp cmos eprom connection diagram oe/v pp a 15 a 13 a 11 a 9 ad 0 ad 2 ad 4 ad 6 gnd v cc ale a 14 a 12 a 10 a 8 ad 1 ad 3 ad 5 ad 7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 soic top view commercial temp. range (0 c to + 70 c) v cc = 5v 10% parameter/order number access time (ns) (note 1) NM27C520m 90 90 industrial temp. range (-40 c to + 85 c) v cc = 5v 10% parameter/order number access time (ns) (note 1) NM27C520me 90 90 note 1: all versions are guaranteed to function for slower speeds. package type: m=wide bodied soic pin names addresses/outputs ad 0 -ad 7 address/data a 8 -a 15 address ale address latch enable oe/v pp output enable ds800001-2
3 www.fairchildsemi.com NM27C520 524,288-bit (64k x 8) multiplexed addresses/outputs otp cmos eprom absolute maximum ratings (note 2) storage temperature -65 c to +150 c all input voltage except a9 -2.0v to +7v with respect to ground v pp and a9 with respect to ground -2.0v to +14v v cc supply voltage with -0.6v to +7v respect to ground esd protection >2000v (mil std. 883, method 3015.2) all output voltages with v cc +1.0v to gnd -0.6v respect to ground operating range range temperature v cc tolerance commercial 0 c to +70 c +5v 10% industrial -40 c to +85 c +5v 10% read operation dc electrical characteristics symbol parameter test conditions min. max. units v il input low level -0.6 0.8 v v ih input high level 2.0 v cc + 0.5 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -400 m a 2.4 v i cc v cc active current i out = 0 ma, f = 5 mhz 20 ma i cc2 v cc standby current ale = v ih 2ma i pp v pp supply current v pp = v cc 10 m a v pp v pp read voltage v cc - 0.7 v cc v i li input load current v in = 5.5v or gnd -1 1 m a i li2 input load current a13 v in = 5.5v or gnd -100 100 m a i lo output leakage current v out = 5.5v or gnd -5 5 m a read operation ac electrical characteristics symbol parameter min max units t acc address to output delay 90 ns t ale address latch enable width 45 ns t oe oe to output delay 35 ns t df output disable to output float 25 ns t oh output hold from addresses, ce 0 ns or oe, whichever occurred first t as address setup time 15 ns t ah address hold time 15 ns
4 www.fairchildsemi.com NM27C520 524,288-bit (64k x 8) multiplexed addresses/outputs otp cmos eprom capacitance t a = +25 c, f = 1 mhz (note 3) symbol parameter conditions typ max units c in input capacitance v in = 0v 4 6 pf c out output capacitance v out = 0v 8 12 pf ac test conditions output load 1 ttl gate and cl = 100 pf (note 9) input rise and fall times 20 ns (10% to 90%) input pulse levels 0.45v to 2.4v timing measurement reference level (note 9) inputs 0.8v and 2.0v outputs 0.8v and 2.0v ac waveforms for read operation (notes 7 and 8) address in data out ale t ale a 8 - a 15 oe/v pp ad 0 - ad 7 (note 4) (note 4) t df (note 5, 6) t oh t oe t acc as t ah t note 2: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 3: this parameter is only sampled and is not 100% tested. note 4: oe may be delayed up to t acc - t oe after the falling edge of ale without impacting t acc . note 5: the t df and t cf compare level is determined as follows: high to tri-state, the measured v oh1 (dc) -0.10v; low to tri-state, the measured v ol1 (dc) +0.10v. note 6: tri-state may be attained using oe or ce. note 7: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. note 8: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 9: 1 ttl gate: i ol = 1.6 ma, i oh = -400 m a. c l : 100 pf includes fixture capacitance. note 10: inputs and outputs can undershoot to -2.0v for 20 ns max. ds800001-3
5 www.fairchildsemi.com NM27C520 524,288-bit (64k x 8) multiplexed addresses/outputs otp cmos eprom dc programming characteristics (notes 11 & 12) t a = 25 5 c, v cc = 6.5 2.5v, oe/v pp = 13.0 0.25v (note 13) symbol parameter test conditions min typ max units v il input low level -0.6 0.8 v v ih input high level 2.0 v cc + 1 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -400 m a 2.4 v i cc v cc supply current 25 ma i cc2 v cc standby current ale = v il 2.5 ma i pp oe/v pp current ale = v ih 25 ma i li input load current v in = v il or v ih -10 10 m a i li2 input load current a13 v in = v il or v ih -100 100 m a ac programming characteristics (notes 11 & 12) t a = 25 5 c, v cc = 6.5 2.5v, oe/v pp = 13.0 0.25v (note 13) symbol parameter test conditions min typ max units t ale address latch enable width 500 ns t las latched address setup time 100 ns t lah latched address hold time 100 ns t as address setup time 2 m s t ah address hold time 2 m s t ds data setup time 2 m s t dh data hold time 2 m s t oes oe/v pp setup time 2 m s t oeh oe/v pp hold time 2 m s t prt oe/v pp pulse rise time 50 ns during programming t vr oe/v pp recovery time 2 m s t pw program pulse width 45 50 105 m s t vcs v cc setup time 2 m s t lp ale low to oe/v pp high 2 m s voltage delay t oe data valid from oe/v pp 150 ns t dfp oe/v pp high to output float 0 130 ns delay (note 14) note 11 : fairchilds standard product warranty applies only to devices programmed to specifications described herein. note 12 : v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 13 : the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v cc to gnd to suppress spurious voltage transients which may damage the device. note 14 : this parameter is not 100% tested. output float is defined as the point where data is no longer driven. see timing diagram (p age 6).
6 www.fairchildsemi.com NM27C520 524,288-bit (64k x 8) multiplexed addresses/outputs otp cmos eprom programming waveforms t vcs program read (verify) t oes t oeh t las t lah t las t lah t ds 6.5v 5.0v 13.0v v ih v il v ih v il v ih v il v ih v il oe/v pp v cc t ale t prt t lp t pw t ale t vr t as t ah t dfp t oe t dh ale ad 0 - ad 7 a 8 - a 15 addr data in addr address stable data out note 15 : the input timing reference is 0.8v for v il and 2.0v for v ih . note 16 : t oe and t dfp are characteristics of the device but must be accommodated by the programmer. ds800001-4
7 www.fairchildsemi.com NM27C520 524,288-bit (64k x 8) multiplexed addresses/outputs otp cmos eprom turbo programming algorithm flow chart v cc = 6.5v v pp = 12.75v n = 0 address = first location check all bytes 1st: v cc = v pp = 6.0v 2nd: v cc = v pp = 4.3v program one 50 s pulse increment n address = first location verify byte n = 10? device failed last address ? increment address n = 0 program one 50 s pulse increment address verify byte last address ? pass no fail yes yes pass no fail no yes figure 1 ds800001-5
8 www.fairchildsemi.com NM27C520 524,288-bit (64k x 8) multiplexed addresses/outputs otp cmos eprom functional description device operation the six modes of operation of the eprom are listed in table 1. it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and oe/v pp . the oe/ v pp power supply must be at 12.75v during the two programming modes, and must be at 5v in the other four modes. the v cc power must be at 6.5v during the two programming modes, and at 5v in the other four modes. read mode the NM27C520 has two control pins which are used to read data on the output pins. address latch enable (ale) is pulsed to read address pins ad 0 - ad 7 . on the falling edge of this pulse, the data on these pins are latched into memory. when the address pins a 8 - a 15 are stable and output enable (oe) is low, the data contained in the desired address location is gated to pins ad 0 - ad 7 . address access time (t acc ) is either the time delay from address latch enable, or the time delay from when the address pins a 8 - a 15 are stable, which ever happens last. output enable (oe/v pp ) is the output control and should be used to drive data to the output pins. standby mode the eprom has a standby mode which reduces the active power dissipation by over 90%, from 110mw to less than 11mw. the eprom is placed in the standby mode by applying a cmos high signal to the ale input. output disable the eprom is placed in output disable by applying a ttl high signal to the oe input. when in output disable all circuitry is enabled, except the outputs are in a high impedance state (tri- state). output or-typing because the eprom is usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ale be decoded and used as the primary device selecting function, while oe/v pp be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on pin 1 (oe/v pp ) will damage the eprom. initially, all bits of the eprom are in the 1s state. data is introduced by selectively programming 0s into the desired bit locations. although only "0s" will be programmed, both 1s and 0s can be presented in the data word. it is not possible to change a 0 to a 1. the eprom is in the programming mode when the oe/v pp power supply is at 12.75v. it is required that at least a 0.1 m f capacitor be placed across v cc to ground to suppress spurious voltage transients which may damage the device. the data to be pro- grammed is applied 8 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. programming mode can be accomplished after a ttl high pulse is applied to the ale input latching in the addresses ad 0 - ad 7 by its falling edge. once addresses a 8 - a 15 are stable, the oe/v pp power supply is set to 12.75v and a ttl high pulse is again applied to the ale input. in order to program the entire memory array, a program pulse must be applied at each address location in this same manner. the eprom is programmed with the turbo programming algo- rithm shown in figure 1 . each address is programmed with a series of 50 m s pulses until it verifies good, up to a maximum of 10 pulses. most memory cells will program with a single 50 m s pulse. the eprom must not be programmed with a dc signal applied to the ale input. programming multiple eprom in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. like inputs of the parallel eprom may be con- nected together when they are programmed with the same data. a high level ttl pulse applied to the ale input programs the paralleled eprom. program inhibit programming multiple eprom's in parallel with different data is also easily accomplished. except for ale all like inputs (including oe/v pp ) of the parallel eprom may be common. a ttl high level program pulse applied to an eproms ale input with oe/v pp at 12.75v will program that eprom. a ttl low level ale input inhibits the other eproms from being programmed. manufacturer's identification code the eprom has a manufacturers identification code to aid in programming. when the device is inserted in an eprom pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. the manufacturers identification code, shown in table 2, specifi- cally identifies the manufacture and device type. the code for NM27C520 is '8f9d', where '8f' designates that it is made by fairchild semiconductor, and '9d' designates the 520 part. the code is accessed by applying 12v 0.5v to address pin a 9 . addresses ad 1 - a 8 , a 10 -a 16 , and all control pins are held at v il . address pin a 8 is held at v il for the manufacturers code, and held at v ih for the device code. the code is read on the eight data pins, ad 0 - ad 7 . proper code access is only guaranteed at 25 c 5 c.
9 www.fairchildsemi.com NM27C520 524,288-bit (64k x 8) multiplexed addresses/outputs otp cmos eprom mode selection the modes of operation of the NM27C520 are listed in table 1. a single 5v power supply is required in the read mode. all inputs are ttl levels except for v pp and a 9 for device signature. table 1. mode selection pins ale oe/v pp a 8 - a 15 ad 0 - ad 7 mode read v il v il a in d out output disable v il /v ih v ih a in high z/a in standby v ih xa in a in address latch enable v ih a in a in programming v ih 12.75v a in d in program inhibit v il 12.75v a in high z note 17 : = high to low transition, a in = address in, d out = data out, d in = data in table 2. manufacturer's identification code pins a 9 a 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 ad 1 ad 0 hex mode data manufacturer v pp 0100011118f code device code v pp 1100111019d
10 www.fairchildsemi.com NM27C520 524,288-bit (64k x 8) multiplexed addresses/outputs otp cmos eprom physical dimensions inches (millimeters) unless otherwise noted 20 lead no. 1 ident 11 10 1 0.394 - 0.419 [10.008 - 10.643] 0.496 - 05.12 [12.598 - 13.005] 0.50 [1.270] typ 0.008 [0.203] 0.014-0.020 [0.356-0.508] 30 typ 0.004-0.012 [0.102-0.305] typ seating plane 0.010 [0.254] max typ typ 0.093 - 0.104 [2.362 - 2.642] 0.014 [0.356] 0.291-0.299 [7.391- 7.595] 0.009-0.013 [0.229-0.330] typ all leads 0.010 - 0.029 [0.254 - 0.737] 8 max typ all leads x45 0.004 [0.102] all leads tips 0.016 - 0.050 [0.406 - 1.270] typ all leads 20-lead (0.300" wide) molded small outline package, jedec order number NM27C520 package number m20b fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm27lv010 1,048,576-bit (128k x 8) low voltage eprom nm27lv010 1,048,576-bit (128k x 8) low voltage eprom general description the nm27lv010 is a high performance low voltage electrically programmable read only memory. it is manufactured using fairchilds amg? eprom technology. this technology allows the part to operate at speeds as fast as 200 ns. this low voltage and low power eprom is designed with power sensitive hand held and portable battery products in mind. this allows for code storage of firmware for applications like notebook computers, palm top computers, cellular phones, and hdd. small outline packages are just as critical to portable applications as low voltage and low power. the nm27lv010 is one member of fairchilds growing low voltage product family. block diagram july 1998 features n 3.0v to 3.6v operation n 200 ns access time n low current operation 8 ma i cc active current @ 5 mhz (typ.) 20 m a i cc standby current @ 5 mhz (typ.) n ultra low power operation 66 m w standby power @ 3.3v 50 mw active power @ 3.3v n surface mount package options| 32-pin tsop 32-pin plcc ds011377-1 amg? is a trademark of wsi, incorporated. ? 1998 fairchild semiconductor corporation v cc gnd v pp oe output enable, chip enable & program logic y decoder x decoder output buffers 1,048,576-bit cell matrix a 0 - a 16 address inputs data outputs o 0 - o 7 ce pgm
2 www.fairchildsemi.com nm27lv010 1,048,576-bit (128k x 8) low voltage eprom connection diagrams plcc pin configuration top view tsop pin configuration top view commercial temperature range (0 c to +70 c) v cc = 3.3 0.3 parameter/order number access time (ns) nm27lv010 v, t 200 200 nm27lv010 v, t 250 250 pin names a0Ca16 addresses ce chip enable oe output enable o0Co7 outputs pgm program xx dont care (during read) v pp programming voltage industrial temperature range (-40 c to +85 c) v cc = 3.3 0.3 parameter/order number access time (ns) nm27lv010 ve, te 200 nm27lv010 ve, te 250 package types: nm27lv010 v, t v = plcc t = tsop ? all packages conform to the jedec standard. ? all versions are guaranteed to function for slower speeds. ? consult the fairchild sales office on new released products and packages. ? consult the fairchild representative for custom products for your specific application. a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 a 12 a 15 a 16 xx/v pp v cc xx/pgm xx o 1 o 2 gnd o 3 o 4 o 5 o 6 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 32 31 30 a 11 a 9 a 8 a 13 a 14 nc pgm v cc v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 oe a 10 ce o7 o 6 o 5 o4 o 3 v ss o 2 o1 o 0 a 0 a 1 a 2 a 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 8 x 20 mm tsop ds011377-2 ds011377-6
3 www.fairchildsemi.com nm27lv010 1,048,576-bit (128k x 8) low voltage eprom absolute maximum ratings (note 1) storage temperature -65 c to +150 c all input voltages except a9 with respect to ground (note 10) -0.6v to +7v v pp and a9 with respect to ground -0.6v to +14v v cc supply voltage with respect to ground -0.6v to +7v esd protection >2000v all output voltages with v cc + 1.0v respect to ground (note 10) to gnd - 0.6v operating range range temperature v cc tolerance commercial 0 c to +70 c 3.3v 0.3v industrial -40 c to +85 c 3.3v 0.3v dc electrical characteristics over operating range with v pp = v cc symbol parameter test conditions min max units v il input low level -0.3 0.7 v v ih input high level 2.0 v cc + 0.3 v v ol1 output low voltage (ttl) i ol = 2.0 ma 0.4 v v oh1 output high voltage (ttl) i oh = -2.0 ma 2.4 v v ol2 output low voltage i ol = 100 m a 0.2 v v oh2 output high voltage (cmos) i oh = -100 m av cc - 0.3 i sb1 v cc standby current ce = v cc 0.3v 50 m a (cmos) i sb2 v cc standby current (ttl) ce = v ih 100 m a i cc v cc active current ce = oe = v il , f = 5 mhz 15 ma i/o = 0 m a i pp v pp supply current v pp = v cc 10 m a v pp v pp read voltage v cc - 0.7 v cc v i li input load current v in = 3.0v or gnd 1 m a i lo output leakage current v out = 3.0v or gnd -1 10 m a ac electrical characteristics over operating range with v pp = v cc symbol parameter 200 250 units min max min max t acc address to output delay 200 250 ns t ce ce to output delay 200 250 t oe oe to output delay 70 75 t df output disable to output float 50 50 (note 2) t oh output hold from addresses, (note 2) ce or oe , whichever 0 0 occurred first
4 www.fairchildsemi.com nm27lv010 1,048,576-bit (128k x 8) low voltage eprom capacitance (note 2) t a = +25 c, 1 = 1 mhz symbol parameter conditions typ max units c in input capacitance v in = 0v 9 15 pf c out output capacitance v out = 0v 12 15 pf ac test conditions output load 1 ttl gate and c l = 100 pf (note 8) input rise and fall times 5 ns input pulse levels 0.45v to 2.4v timing measurement reference level inputs 0.8v and 2v outputs 0.8v and 2v ac waveforms (note 6) , (note 7) , and (note 9) note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operations sections of this specification is not impli ed. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: this parameter is only sampled and is not 100% tested. note 3: oe may be delayed up to t acc - t ce after the falling edge of ce without impacting t acc . note 4: the t df and t cf compare level is determined as follows: high to tri-state ? , the measured v oh1 (dc) - 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 5: tri-state may be attained using oe or ce . note 6: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.2 m f ceramic capacitor be used on every device between v cc and gnd. note 7: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 8: 1 ttl gate: i ol = 1.6 ma, i oh = -400 m a. c l : 100pf includes fixture capacitance. note 9: v pp may be connected to v cc except during programming. note 10: inputs and outputs can undershoot to -2.0v for 20 ns max. address valid valid output 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v address output ce oe t ce 2.0v 0.8v (note 3) (note 3) t df (note 2, 4, 5) (note 2, 4, 5) t oh hi-z t oe acc t cf t ds011377-3
5 www.fairchildsemi.com nm27lv010 1,048,576-bit (128k x 8) low voltage eprom programming characteristics (note 11), (note 12), (note 13) and (note 14) symbol parameter conditions min typ max units t as address setup time 1 m s t oes oe setup time 1 m s t ces ce setup time 1 m s t ds data setup time 1 m s t vps v pp setup time 1 m s t vcs v cc setup time 1 m s t ah address hold time 0 m s t dh data hold time 1 m s t df output enable to output ce/pgm = v il 060ns float delay t pw program pulse width 45 50 105 m s t oe data valid from oe ce/pgm = v il 100 ns i pp v pp supply current ce/pgm = v il 20 ma during programming pulse i cc v cc supply current 20 ma t a temperature ambient 20 25 30 c v cc power supply voltage 6.25 6.5 6.75 v v pp programming supply voltage 12.5 12.75 13.0 v t fr input rise, fall time 5 ns v il input low voltage 0.0 0.45 v v ih input high voltage 2.4 4.0 v t in input timing reference voltage 0.8 2.0 v t out output timing reference voltage 0.8 2.0 v programming waveform (note 13) note 11: fairchilds standard product warranty applies to devices programmed to specifications described herein. note 12: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removedfrom a board with voltage applied to v pp or v cc . note 13: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v pp , v cc to gnd to suppress spurious voltage transients which may damage the device. note 14: during power up the pgm pin must be brought high ( 3 v ih ) either coincident with or before power is applied to v pp . t as program program verify address n hi-z t ds t dh t vps t ah 2.0v 0.8v 2.0v 0.8v addresses data v pp t ces data out valid add n data in stable add n t pw 12.75v 6.25v v cc t vcs ce pgm t df t oes oe 2.0v 0.8v 2.0v 0.8v t oe ds011377-4
6 www.fairchildsemi.com nm27lv010 1,048,576-bit (128k x 8) low voltage eprom lv turbo programming algorithm flow chart figure 1. v cc = 6.5v v pp = 12.75v n = 0 address = first location check all bytes 1st: v cc = v pp = 5.0v 2nd: v cc = v pp = 3.0v program one 50 s pulse increment n address = first location verify byte n = 10? device failed last address ? increment address n = 0 program one 50 s pulse increment address verify byte last address ? pass no fail yes yes pass no fail no yes ds011377-5 note: the standard national semiconductor algorithm may also be used but it will have longer programming time.
7 www.fairchildsemi.com nm27lv010 1,048,576-bit (128k x 8) low voltage eprom functional description device operation the six modes of operation of the eprom are listed in table 1. it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and v pp . the v pp power supply must be at 12.75v during the three programming modes, and must be at 3.3v in the other three modes. the v cc power supply must be at 6.5v during the three programming modes, and at 3.3v in the other three modes. read mode the eprom has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs t oe after the falling edge of oe, assuming that ce has been low and addresses have been stable for at least t acc Ct oe . standby mode the eprom has a standby mode which reduces the active power dissipation by over 99%, from 50 mw to 0.17 mw. the eprom is placed in the standby mode by applying a cmos high signal to the ce input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output disable the eprom is placed in output disable by applying a ttl high signal to the oe input. when in output disable all circuitry is enabled, except the outputs are in a high impedance state (tri- state). output or-tying because the eprom is usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ce be decoded and used as the primary device selecting function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on pin 1 (v pp ) will damage the eprom. initially, and after each erasure, all bits of the eprom are in the 1s state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be pro- grammed, both 1s and 0s can be presented in the data word. the only way to change a 0 to a 1 is by ultraviolet light erasure. the eprom is in the programming mode when the v pp power supply is at 12.75v and oe is at v ih . it is required that at least a 0.1 m f capacitor be placed across v pp and v cc to ground to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 8 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. when the address and data are stable, an active low, ttl program pulse is applied to the pgm input. a program pulse must be applied at each address location to be programmed. the eprom is programmed with the lv turbo programming algorithm shown in figure 1. each address is programmed with a series of 50 m s pulses until it verifies good, up to a maximum of 10 pulses. most memory cells will program with a single 50 m s pulse. (the standard national semiconductor algorithm may also be used, but it will have longer programming time.) the eprom must not be programmed with a dc signal applied to the pgm input. programming multiple eprom in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. like inputs of the parallel eprom may be con- nected together when they are programmed with the same data. a low level ttl pulse applied to the pgm input programs the paralleled eprom. program inhibit programming multiple eproms in parallel with different data is also easily accomplished. except for ce, all like inputs (including oe and pgm) of the parallel eprom may be common. a ttl low level program pulse applied to an eproms pgm input with ce at v il and v pp at 12.75v will program that eprom. a ttl high level ce input inhibits the other eproms from being programmed. program verify a verify should be performed on the programmed bits to determine whether they were correctly programmed. the verify may be performed with v pp at 6.25v. v pp must be at v cc , except during programming and program verify. after programming opaque labels should be placed over the eprom window to prevent unintentional erasure. covering the window will also prevent temporary functional failure due to the generation of photo currents. manufacturers identification code the eprom has a manufacturers identification code to aid in programming. when the device is inserted in an eprom pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. the manufacturers identification code, shown in table 2, specifi- cally identifies the manufacturer and device type. the code for the nm27lv010 is 8f86, where 8f designates that it is made by fairchild semiconductor, and 86 designates a 1 megabit (128k x 8) part. the code is accessed by applying 12v 0.5v to address pin a9. addresses a1Ca8, a10Ca16, and all control pins are held at v il . address pin a0 is held at v il for the manufacturers code, and held at v ih for the device code. the code is read on the lower eight data pins, o0C07. proper code access is only guaranteed at 25 c 5 c.
8 www.fairchildsemi.com nm27lv010 1,048,576-bit (128k x 8) low voltage eprom functional description (continued) erasure characteristics the erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms (?). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000? C 4000? range. the recommended erasure procedure for the eprom is expo- sure to short wave ultraviolet light which has a wavelength of 2537?. the integrated dose (i.e., uv intensity x exposure time) for erasure should be a minimum of 30w-sec/cm 2 . the eprom should be placed within 1 inch of the lamp tubes during erasure. some lamps have a filter on their tubes which should be removed before erasure. an erasure system should be calibrated periodically. the distance from lamp to device should be maintained at one inch. the erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4). lamps lose intensity as they age. when a lamp has aged, the system should be checked to make certain full erasure is occur- ring. incomplete erasure will cause symptoms that can be mis- leading. programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc , has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. the associated v cc transient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces. mode selection the modes of operation of the nm27lv010 are listed in table 1. a single 3.3v power supply is required in the read mode. all inp uts are ttl levels except for v pp and a9 for device signature. table 1. modes selection pins ce oe pgm v pp v cc outputs mode read v il v il xv cc 3.3v d out output disable x (note 15) v ih xv cc 3.3v high z standby v ih xxv cc 3.3v high z programming v il v ih v il 12.75v 6.25v d in program verify v il v il v ih 12.75v 12.75v d out program inhibit v ih v ih x 12.75v 6.25v high z note 15: x can be v il or v ih . table 2. manufacturers identification code pins a0 a9 o7 o6 o5 o4 o3 o2 o1 o0 hex (12) (26) (21) (20) (19) (18) (17) (15) (14) (13) data manufacturer code v il 12v100011118f device code v ih 12v1000011086
9 www.fairchildsemi.com nm27lv010 1,048,576-bit (128k x 8) low voltage eprom 32-lead tsop package (t) order number nm27lv010txxx package number mbh32a physical dimensions inches (millimeters) unless otherwise noted 1 16 32 18.4 ?0.1 20.0 ?0.2 8.0 ?0.2 0.150?.08 (leadframe thickness) 0.5 0?5 17 0.15-0.25 typ 0.10 see detail a 1.27 max 0-0.25 0.4-0.6 detail a typical 0.96 - 1.06
10 www.fairchildsemi.com nm27lv010 1,048,576-bit (128k x 8) low voltage eprom physical dimensions inches (millimeters) unless otherwise noted 32-lead plcc package order number nm27lv010vxxx package number va32a 0.007[0.18] a s s f-g 0.007[0.18] b s d-e 0.449-0.453 [11.40-11.51] s 0.045 [1.143] 0.000-0.010 [0.00-0.25] polished optional 0.585-0.595 [14.86-15.11] 0.549-0.553 [13.94-14.05] -b- -f- -e- -g- 0.050 21 29 30 1 4 20 14 13 5 -d- 0.007[0.18] b s d-e s 0.002[0.05] b s -a- 0.485-0.495 [12.32-12.57] 0.007[0.18] a s s f-g a 0.002[0.05] s s 0.007[0.18] c m s d-e, f-g 0.015[0.38] c d-e, f-g 0.490-0530 [12.45-13.46] 0.078-0.095 [1.98-2.41] 0.013-0.021 [0.33-0.53] 0.004[0.10] 0.123-0.140 [3.12-3.56] see detail a -j- -c- 0.400 [10.16] ( ) typ 0.541-0.545 [13.74-13-84] 0.023-0.029 [0.58-0.74] 0.106-0.112 [2.69-2.84] 60 0.015 [0.38] base plane -h- min typ s 0.007[0.18] h s s d-e, f-g 0.010[0.25] b a s d-e, f-g 0.118-0.129 [3.00-3.28] l b b 45? 0.042-0.048 [1.07-1.22] 0.026-0.032 [0.66-0.81] typ 0.0100 [0.254] 0.030-0.040 [0.76-1.02] r 0.005 [0.13] max 0.020 [0.51] 0.045 [1.14] detail a typical rotated 90 0.027-0.033 [0.69-0.84] 0.025 [0.64] min 0.025 [0.64] min 0.031-0.037 [0.79-0.94] 0.053-0.059 [1.65-1.80] 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64] 0.065-0.071 [1.65-1.80] 0.021-0.027 [0.53-0.69] section b-b typical fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm27lv010b 1,048,576-bit (128k x 8) low voltage eprom nm27lv010b 1,048,576-bit (128k x 8) low voltage eprom general description the nm27lv010b is a high performance low voltage electrically programmable read only memory. it is manufactured using fairchilds split gate amg? eprom technology. this technology allows the part to operate at speeds as fast as 250 ns over industrial temperatures (-40 c to +85 c). this low voltage and low power eprom is designed with power sensitive hand held and portable battery products in mind. this allows for code storage of firmware for applications like notebook computers, palm top computers, cellular phones, and hdd. the nm27lv010b is one member of fairchilds growing low voltage product family. block diagram july 1998 features n 2.7v to 3.3v operation n 200 ns access time n low current operation 8 ma i cc active current @ 5 mhz (typ) 15 m a i cc standby current @ 5 mhz (typ) n ultra low power operation 50 m w standby power @ 3.3v (typ) 27 mw active power @ 3.3v (typ) n 32-pin tsop package ds012333-1 amg? is a trademark of wsi, incorporated. ? 1998 fairchild semiconductor corporation v cc gnd v pp oe output enable, chip enable & program logic y decoder x decoder output buffers 1,048,576-bit cell matrix a 0 - a 16 address inputs data outputs o 0 - o 7 ce pgm
2 www.fairchildsemi.com nm27lv010b 1,048,576-bit (128k x 8) low voltage eprom connection diagrams tsop pin configuration top view commercial temperature range (0 c to +70 c) v cc = 2.7v-3.6v parameter/order number access time (ns) nm27lv010bt 200 200 nm27lv010bt 250 250 pin names a0Ca16 addresses ce chip enable oe output enable o0Co7 outputs pgm program xx dont care (during read) v pp programming voltage industrial temperature range (-40 c to +85 c) v cc = 2.7vC3.6v parameter/order number access time (ns) nm27lv010bte 250 package type: nm27lv010b t t = tsop package ? all packages conform to jedec standard. ? all versions are guaranteed to function at slower speeds. ? consult your fairchild semiconductor sales office for new released products and packages. ? consult your fairchild semiconductor representative for custom products for your specific application. a 11 a 9 a 8 a 13 a 14 nc pgm v cc v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 oe a 10 ce o7 o 6 o 5 o4 o 3 v ss o 2 o1 o 0 a 0 a 1 a 2 a 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 8 x 20 mm tsop ds012333-3
3 www.fairchildsemi.com nm27lv010b 1,048,576-bit (128k x 8) low voltage eprom absolute maximum ratings (note 1) storage temperature -65 c to +150 c all input voltage except a9 with respect to ground -0.6v to +7v v pp and a9 with respect to ground -0.7v to +14v v cc supply voltage with respect to ground -0.6v to +7v esd protection >2000v all output voltages with respect to ground v cc + 1.0v (note 10) to gnd - 0.6v operating range range temperature v cc tolerance commercial 0 c to +70 c 2.7vC3.3v industrial -40 c to +85 c 2.7vC3.3v dc read characteristics (over operating range with v pp = v cc ) symbol parameter conditions min max units v il input low level -0.3 0.6 v v ih input high level 2.0 v cc + 0.3 v v ol1 output low voltage (ttl) i ol = 2.1 ma 0.4 v v oh1 output high voltage (ttl) i oh = -400 m a 2.2 v v ol2 output low voltage i ol = 100 m a 0.2 v v oh2 output high voltage (cmos) i oh = 100 m av cc - 0.3 v i sb1 v cc standby current ce = 2.7vC3.6v 50 m a (cmos) i sb2 v cc standby current (ttl) ce = v ih 100 m a i cc v cc active current ce = oe = v il , f = 5 mhz 15 ma i/o = 0 m a i pp v pp supply current v pp = v cc 10 m a i li input load current v in = 3.0v or gnd 1 m a i lo output leakage current v out = 3.3v or gnd -1 10 m a ac read characteristics (over operating range with v pp = v cc ) symbol parameter 200 250 units min max min max t acc address to output delay 200 250 ns t ce ce to output delay 200 250 ns t oe oe to output delay 70 75 ns t df output disable to output float 50 50 ns (note 2) t oh output hold from addresses, ce or oe , 0 0 ns whichever occurred first (note 2)
4 www.fairchildsemi.com nm27lv010b 1,048,576-bit (128k x 8) low voltage eprom capacitance t a = +25 c, f = 1 mhz (note 2) symbol parameter conditions typ max units c in1 input capacitance v in = 0v 9 15 pf c out output capacitance v out = 0v 12 15 pf ac test conditions output load: 1 ttl gate and c l = 100 pf (note 8) input rise and fall times: 5 ns input pulse levels: 0.45v to 2.4v timing measurement reference level inputs: 0.8v and 2v outputs: 0.8v and 2v ac waveforms (note 6) (note 7) (note 9) *after power-up (stable v cc ), a high-to-low transition of ce is required before the first byte of data is read. note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not impli ed. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: this parameter is only sampled and is not 100% tested. note 3: oe may be delayed up to t acc - t oe after the falling edge of ce without impacting t acc . note 4: the t df and t cf compare level is determined as follows: high to tri-state ? , the measured v oh1 (dc) - 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 5: tri-state may be attained using oe or ce. note 6: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. note 7: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 8: 1 ttl gate: i ol = 1.6 ma, i oh = -400 m a. c l : 100 pf includes fixture capacitance. note 9: v pp may be connected to v cc except during programming. note 10: inputs and outputs can undershoot to -2.0v for 20 ns max. address valid valid output 2.0v 0.8v 2.0v 0.8v ce high-to-low transition must occur after v cc > 2.7v 2.0v 0.8v address output ce oe t ce 2.0v 0.8v (note 3) (note 3) t df (note 2, 4, 5) (note 2, 4, 5) t oh hi-z t oe acc t cf t ds012333-4
5 www.fairchildsemi.com nm27lv010b 1,048,576-bit (128k x 8) low voltage eprom programming characteristics (note 11) (note 12) (note 13) (note 14) symbol parameter conditions min typ max units t as address setup time 1 m s t oes oe setup time 1 m s t ces ce setup time 1 t ds data setup time 1 m s t vps v pp setup time 1 t vcs v cc setup time 1 m s t ah address hold time 0 m s t dh data hold time 1 m s t df output enable to output float delay ce/pgm = v il 060ns t pw program pulse width 45 50 55 m s t oe data valid from oe ce/pgm = v il 100 m s i pp v pp supply current during programming pulse ce/pgm = v il 20 ma i cc v cc supply current 20 ma t a temperature ambient 20 25 30 c v cc power supply voltage 6.25 6.5 6.75 v v pp programming supply voltage 12.5 12.75 13 v t fr input rise, fall time 5 ns v il input low voltage 0 0.45 v v ih input high voltage 2.4 4 v t in input timing reference voltage 0.8 2 v t out output timing reference voltage 0.8 2 v programming waveform (note 13) note 11: fairchilds standard product warranty applies only to devices programmed to specifications described herein. note 12: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 13: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v cc to gnd to suppress spurious voltage transients which may damage the device. note 14: during power up, the pgm pin must be brought high (v ih ) either coincident with or before power is applied to v pp . t as program program verify address n hi-z t ds t dh t vps t ah 2.0v 0.8v 2.0v 0.8v addresses data v pp t ces data out valid add n data in stable add n t pw 12.75v 6.25v v cc t vcs ce pgm t df t oes oe 2.0v 0.8v 2.0v 0.8v t oe ds012333-5
6 www.fairchildsemi.com nm27lv010b 1,048,576-bit (128k x 8) low voltage eprom lv turbo programming algorithm flow chart figure 1. v cc = 6.5v v pp = 12.75v n = 0 address = first location check all bytes 1st: v cc = v pp = 5.0v 2nd: v cc = v pp = 3.0v program one 50 s pulse increment n address = first location verify byte n = 10? device failed last address ? increment address n = 0 program one 50 s pulse increment address verify byte last address ? pass no fail yes yes pass no fail no yes ds012333-6 note: the standard national semiconductor algorithm may also be used but it will have longer programming time.
7 www.fairchildsemi.com nm27lv010b 1,048,576-bit (128k x 8) low voltage eprom functional description device operation the six modes of operation of the eprom are listed in table 1. it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and v pp . the v pp power supply must be at 12.75v during the three programming modes, and must be at 3.3v in the other three modes. the v cc power must be at 6.5v during the three programming modes, and at 3.3v in the other three modes. read mode the eprom has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs t oe after the falling edge of oe, assuming that ce has been low and addresses have been stable for at least t acc - t oe . standby mode the eprom has a standby mode which reduces the active power dissipation by over 99%, from 45 mw to 0.15 mw. the eprom is placed in the standby mode by applying a cmos high signal to the ce input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output disable the eprom is placed in output disable by applying a ttl high signal to the oe input. when in output disable all circuitry is enabled, except the outputs are in a high impedance state (tri- state). output or-tying because the eprom is usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ce be decoded and used as the primary device selecting function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all selected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on pin 22 (v pp ) will damage the eprom. initially, and after each erasure, all bits of the eprom are in the 1s state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be pro- grammed, both 1s and 0s can be presented in the data word. the only way to change a 0 to a 1 is by ultraviolet light erasure. the eprom is in the programming mode when the v pp power supply is at 12.75v and oe is at v ih . it is required that at least a 0.1 m f capacitor be placed across v cc to gnd to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 8 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. when the address and data are stable, an active low, ttl program pulse is applied to the pgm input. a program pulse must be applied at each address location to be programmed. the eprom is programmed with the lv turbo programming algorithm shown in figure 1. each address is programmed with a series of 50 m s pulses until it verifies good, up to a maximum of 10 pulses. most memory cells will program with a single 50 m s pulse. (the standard national semiconductor algorithm may also be used, but it will have longer programming time.) the eprom must not be programmed with a dc signal applied to the pgm input. programming multiple eproms in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. like inputs of the parallel eprom may be con- nected together when they are programmed with the same data. a low level ttl pulse applied to the pgm input programs the paralleled eprom. program inhibit programming multiple eproms in parallel with different data is also easily accomplished. except for ce, all like inputs (including oe and pgm) of the parallel eprom may be common. a tll low level program pulse applied to an eproms pgm input with ce at v il and v pp at 12.75v will program that eprom. a ttl high level ce input inhibits the other eproms from being programmed. program verify a verify should be performed on the programmed bits to determine whether they were correctly programmed. the verify may be performed with v pp at 6.25v. v pp must be at v cc except during programming and program verify. after programming opaque labels should be placed over the eprom window to prevent unintentional erasure. covering the window will also prevent temporary functional failure due to the generation of photo currents. manufacturers identification code the eprom has a manufacturers identification code to aid in programming. when the device is inserted in an eprom pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. the manufacturers identification code, shown in table 2, specifi- cally identifies the manufacture and device type. the code for nm27lv010b is 8f86, where 8f designates that it is made by fairchild semiconductor, and 86 designates a 1 mbit (128k x 8) part. the code is accessed by applying 12v 0.5v to address pin a9. addresses a1Ca8, a10Ca16 and all control pins are held at v il . address pin a0 is held at v il for the manufacturers code and held at v ih for the device code. the code is read on the eight data pins, o0Co7. proper code access is only guaranteed at 25 c 5 c.
8 www.fairchildsemi.com nm27lv010b 1,048,576-bit (128k x 8) low voltage eprom functional description (continued) erasure characteristics the erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms (?). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000? C 4000? range. the recommended erasure procedure for the eprom is expo- sure to short wave ultraviolet light which has a wavelength of 2537?. the integrated dose (i.e., uv intensity x exposure time) for erasure should be a minimum of 30 wsec/cm 2 . the eprom should be placed within one inch of the lamp tubes during erasure. some lamps have a filter on their tubes which should be removed before erasure. an erasure system should be calibrated periodically. the distance from lamp to device should be maintained at one inch. the erasure time increases at the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of four). lamps lose intensity as they age. when a lamp is changed, the distance has changed or the lamp has aged, the system should be checked to make certain full erasure is occurring. incomplete erasure will cause symptoms that can be misleading. program- mers, components, and even system designs have been errone- ously suspected when incomplete erasure was the problem. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc , has three segments that are of interest to the system designer: the standby current level, the active current level and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. the associated v cc transient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces. mode selection the modes of operation of the nm27lv010b are listed below. all inputs are ttl levels except for v pp and a9 for device signature. modes selection pins ce oe pgm v pp v cc outputs mode read v il v il xv cc 3.3v d out output disable x v ih xv cc 3.3v high z standby v ih xxv cc 3.3v high z programming v il v ih v il 12.75v 6.25v d in program verify v il v il v ih 12.75v 12.75v d out program inhibit v ih v ih x 12.75v 6.25v high z x can be v il or v ih manufacturers identification code pins a0 a9 o7 o6 o5 o4 o3 o2 o1 o0 hex (12) (26) (21) (20) (19) (18) (17) (15) (14) (13) data manufacturer code v il 12v100011118f device code v ih 12v1000011086
9 www.fairchildsemi.com nm27lv010b 1,048,576-bit (128k x 8) low voltage eprom physical dimensions inches (millimeters) unless otherwise noted 32-lead tsop package (t) order number nm27lv010btxxx package number mbh32a 1 16 32 18.4 ?0.1 20.0 ?0.2 8.0 ?0.2 0.150?.08 (leadframe thickness) 0.5 0?5 17 0.15-0.25 typ 0.10 see detail a 1.27 max 0-0.25 0.4-0.6 detail a typical 0.96 - 1.06 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm27lv210 1,048,576-bit (64k x 16) low voltage eprom nm27lv210 1,048,576-bit (64k x 16) low voltage eprom general description the nm27lv210 is a high performance low voltage electrical programmable read only memory. it is manufactured using fairchilds latest eprom technology. this technology allows the part to operate at high speeds. this low voltage and low power eprom is designed with power sensitive hand held and portable battery products in mind. this allows for code storage of firmware for applications like notebook computers, palm top computers, cellular phones, and hdd. the nm27lv210 is one member of fairchilds growing low voltage product family. block diagram july 1998 features n 3.0v to 3.6v operation n 200 ns, 250 ns maximum access time n low current operation 20ma i cc active current @ 5 mhz 50 m a i cc standby current @ 5 mhz n ultra low power operation 60 m a standby power @ 3.3v 50 mw active power @ 3.3v n surface mount package option 44-pin plcc ds011376-1 ? 1998 fairchild semiconductor corporation v cc gnd v pp oe pgm output enable chip enable, and program logic y decoder x decoder output buffers 1,048,576-bit cell matrix a 0 - a 15 address inputs data outputs o 0 - o 15 ce
2 www.fairchildsemi.com nm27lv210 1,048,576-bit (64k x 16) low voltage eprom connection diagrams plcc pin configuration top view commercial temperature range (0 c to +70 c) v cc = 3.3v 0.3 parameter/order number access time (ns) nm27lv210 v 200 200 nm27lv210 v 250 250 pin names a0Ca15 addresses ce chip enable oe output enable o0Co15 outputs pgm program xx dont care (during read) nc no connect v pp programming voltage extended temperature range (-40 c to +85 c) v cc = 3.3v 0.3 parameter/order number access time (ns) nm27lv210 ve 250 250 ? all packages conform to jedec standard. ? all versions are guaranteed to function in slower applica- tions. ? consult the fsc representative for newly released products/ packages. o 12 o 11 o 10 o 9 o 8 gnd nc o 7 o 6 o 5 o 4 a 13 a 12 a 11 a 10 a 9 gnd nc a 8 a 7 a 6 a 5 o 13 o 14 o 15 xx/v pp nc nc a 15 a 14 o 3 o 2 o 1 o 0 oe nc a 0 a 1 a 2 a 3 a 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 40 41 42 43 44 38 37 36 35 34 33 32 31 30 22 21 20 19 18 28 27 26 25 24 23 29 39 ce v cc xx/pgm o 12 o 11 o 10 o 9 o 8 gnd nc o 7 o 6 o 5 o 4 a 13 a 12 a 11 a 10 a 9 gnd nc a 8 a 7 a 6 a 5 o 13 o 14 o 15 xx/v pp nc nc a 15 a 14 o 3 o 2 o 1 o 0 oe nc a 0 a 1 a 2 a 3 a 4 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 34 35 36 37 38 32 31 30 29 28 27 26 25 24 16 15 14 13 12 22 21 20 19 18 17 23 33 ce v cc xx/pgm ds011376-7 ds011376-3
3 www.fairchildsemi.com nm27lv210 1,048,576-bit (64k x 16) low voltage eprom absolute maximum ratings (note 2) storage temperature -65 c to +150 c all input voltages except a9 with respect to ground (note 12) -0.6v to +7v v pp and a9 with respect to ground -0.6v to +14v v cc supply voltage with respect to ground -0.6v to +7v esd protection >2000v all output voltages with respect to ground (note 11) v cc + 1.0v to gnd - 0.6v operating range range temperature v cc tolerance commercial 0 c to +70 c 3.3 0.3 extended -40 c to +85 c 3.3 0.3 dc read characteristics over operating range with v pp = v cc symbol parameter test conditions min max units v il input low level -0.3 0.7 v v ih input high level 2.0 v cc + 0.3 v v ol1 output low voltage (ttl) 0.4 v v oh1 output high voltage (ttl) 2.4 v v ol2 output low voltage (cmos) 0.2 v v oh2 output high voltage (cmos) v cc - 0.3 v i sb1 v cc standby current (ttl) ce = v ih 150 m a i sb2 v cc standby current (cmos) ce = v cc 0.3v 50 m a i cc v cc active current ce = oe = v il , f = 5 mhz 20 ma i/o = 0 m a i pp v pp supply current v pp = v cc 10 m a i li input load current v in = 3.3 or gnd -1 1 m a i lo output leakage current v out = 3.3v or gnd -1 10 m a ac read characteristics over operating range with v pp = v cc symbol parameter 200 250 units min max min max t acc address to output delay 200 250 t ce ce to output delay 200 250 t oe oe to output delay 70 75 t df output disable to output float 0 50 0 60 ns (note 3) t oh output hold from addresses, (note 3) ce or oe , whichever 0 0 occurred first capacitance (note 3) t a = +25?c, f = 1 mhz symbol parameter conditions typ max units c in input capacitance v in = 0v 12 20 pf c out output capacitance v out = 0v 13 20 pf
4 www.fairchildsemi.com nm27lv210 1,048,576-bit (64k x 16) low voltage eprom ac test conditions output load 1 ttl gate and c l = 100 pf (note 9) input rise and fall times 5 ns input pulse levels 0.45v to 2.4v timing measurement reference level inputs 0.8v and 2v outputs 0.8v and 2v ac waveforms (note 7) (note 8) (note 10) note 2: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 3: this parameter is only sampled and is not 100% tested. note 4: oe may be delayed up to t acc - t oe after the falling edge of ce without impacting t acc . note 5: the t df and t cf compare level is determined as follows: high to tri-state ? , the measured v oh1 (dc) - 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 6: tri-state may be attained using oe or ce. note 7: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. note 8: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 9: 1 ttl gate: i ol = 1.6 ma, i oh = -400 m a. c l : 100 pf includes fixture capacitance. note 10: v pp may be connected to v cc except during programming. note 11: inputs and outputs can undershoot to -2.0v for 20 ns max. programming characteristics (note 12) (note 13) (note 14) (note 15) symbol parameter conditions min typ max units t as address setup time 1 m s t oes oe setup time 1 m s t ces ce setup time oe = v ih 1 m s t ds data setup time 1 m s t vps v pp setup time 1 m s t vcs v cc setup time 1 m s t ah address hold time 0 m s t dh data hold time 1 m s t df output enable to output float delay ce = v il 060ns address valid valid output 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v address output ce oe t ce 2.0v 0.8v (note 3) (note 3) t df (note 4, 5) (note 4, 5) t dh hi-z t oe acc t cf t hi-z ds011376-4
5 www.fairchildsemi.com nm27lv210 1,048,576-bit (64k x 16) low voltage eprom programming characteristics (note 12) (note 13) (note 14) (note 15) (continued) symbol parameter conditions min typ max units t pw program pulse width 45 50 105 m s t oe data valid from oe ce = v il 100 ns i pp v pp supply current during ce = v il 40 ma programming pulse pgm = v il i cc v cc supply current 50 ma t a temperature ambient 20 25 30 c v cc power supply voltage 6.25 6.5 6.75 v v pp programming supply voltage 12.5 12.75 13.0 v t fr input rise, fall time 5 ns v il input low voltage 0.0 0.45 v v ih input high voltage 2.4 4.0 v t in input timing reference voltage 0.8 2.0 v t out output timing reference voltage 0.8 2.0 v programming waveforms (note 14) note 12: fairchilds standard product warranty applies only to devices programmed to specifications described herein. note 13: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 14: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v pp , v cc to gnd to suppress spurious voltage transients which may damage the device. note 15: during power up the pgm pin must be brought high ( 3 v ih ) either coincident with or before power is applied to v pp . t as program program verify address n t df hi-z t ds t dh t vcs t vps t pw t oes t oe 2.0v 0.8v 2.0v 0.8v 6.25v 12.75v 2.0v 0.8v 2.0v 0.8v addresses data oe ce v cc v pp 0.8v pgm t ces data out valid add n data in stable add n ds011376-5
6 www.fairchildsemi.com nm27lv210 1,048,576-bit (64k x 16) low voltage eprom turbo lv programming algorithm flow chart figure 1. v cc = 6.5v v pp = 12.75v n = 0 address = first location check all bytes 1st: v cc = v pp = 5.0v 2nd: v cc = v pp = 3.0v program one 50 s pulse increment n address = first location verify byte n = 10? device failed last address ? increment address n = 0 program one 50 s pulse increment address verify byte last address ? pass no fail yes yes pass no fail no yes ds011376-6 note: the standard national semiconductor algorithm may also be used but it will have longer programming time.
7 www.fairchildsemi.com nm27lv210 1,048,576-bit (64k x 16) low voltage eprom functional description device operation the six modes of operation of the eprom are listed in . it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and v pp . the v pp power supply must be at 12.75v during the three programming modes, and must be at 3.3v in the other three modes. the v cc power supply must be at 6.5v during the three programming modes, and at 3.3v in the other three modes. read mode the eprom has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that the addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs t oe after the falling edge of oe, assuming that ce has been low and addresses have been stable for at least t acc C t oe . standby mode the eprom has a standby mode which reduces the active power dissipation by over 99%, from 66 mw to 66 m w. the eprom is placed in the standby mode by applying a cmos high signal to the ce input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output disable the eprom is placed in output disable by applying a ttl high signal to the oe input. when in output disable all circuitry is enabled, except the outputs are in a high impedance state (tri- state). output or-tying because the eprom is usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ce be decoded and used as the primary device selecting function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on the v pp or a9 pin will damage the eprom. initially, and after each erasure, all bits of the eprom are in the 1s state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be pro- grammed, both 1s and 0s can be presented in the data word. the only way to change a 0 to a 1 is by ultraviolet light erasure. the eprom is in the programming mode when the v pp power supply is at 12.75v and oe is at v ih . it is required that at least a 0.1 m f capacitor be placed across v pp , v cc to ground to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 16 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. when the address and data are stable, an active low, ttl program pulse is applied to the pgm input. a program pulse must be applied at each address location to be programmed. the eprom is programmed with the turbo programming algorithm shown in figure 1. each address is programmed with a series of 50 m s pulses until it verifies good, up to a maximum of 10 pulses. most memory cells will program with a single 50 m s pulse. (the standard national semiconductor algorithm may also be used but it will have longer programming time.) the eprom must not be programmed with a dc signal applied to the pgm input. programming multiple eprom in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. like inputs of the parallel eprom may be con- nected together when they are programmed with the same data. a low level ttl pulse applied to the pgm input programs the paralleled eprom.
8 www.fairchildsemi.com nm27lv210 1,048,576-bit (64k x 16) low voltage eprom functional description (continued) mode selection the modes of operation of the nm27lv210 are listed in table 1. a single power supply is required in the read mode. all inputs a re ttl levels except for v pp and a9 for device signature. table 1. modes selection pins ce oe pgm v pp v cc outputs mode read v il v il x x 3.3v d out (note 16) output disable x v ih x x 3.3v high z standby v ih x x x 3.3v high z programming v il v ih v il 12.75v 6.25v d in program verify v il v il v ih 12.75v 6.25v d out program inhibit v ih x x 12.75v 6.25v high z note 16: x can be v il or v ih . program inhibit programming multiple eproms in parallel with different data is also easily accomplished. except for ce all like inputs (including oe and pgm) of the parallel eprom may be common. a ttl low level program pulse applied to an eproms pgm input with ce at v il and v pp at 12.75v will program that eprom. a ttl high level ce input inhibits the other eproms from being programmed. program verify a verify should be performed on the programmed bits to determine whether they were correctly programmed. the verify may be performed with v pp at 6.25v. v pp must be at v cc , except during programming and program verify. manufacturers identification code the eprom has a manufacturers identification code to aid in programming. when the device is inserted in an eprom pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. the manufacturers identification code, shown in table 2, specifi- cally identifies the manufacturer and device type. the code for the nm27lv210 is 8fd6, where 8f designates that it is made by fairchild semiconductor, and d6 designates a 1 megabit (64k x 16) part. the code is accessed by applying 12v 0.5v to address pin a9 . addresses a1 Ca8 ,a10 Ca15 , and all control pins are held at v il . address pin a0 is held at v il for the manufacturers code, and held at v ih for the device code. the code is read on the lower eight data pins, o0 C07 . proper code access is only guaranteed at 25 c 5 c. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc , has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. the associated v cc transient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces. table 2. manufacturers identification code pins a0 a9 o7 o6 o5 o4 o3 o2 o1 o0 hex (21) (31) (12) (13) (14) (15) (16) (17) (18) (19) data manufacturer code v il 12v1 00 011 118f device code v ih 12v1 10 101 10d6
9 www.fairchildsemi.com nm27lv210 1,048,576-bit (64k x 16) low voltage eprom 44-lead plastic chip carrier (v) order number nm27lv210xxx package number v44a 6 1 44 40 39 29 17 17 18 28 0.050 [1.27] typ 0.500 [12.70] typ 0.650 +0.006 ?.000 16.51 +0.15 0 pin 1 ident 0.690 0.005 [17.53 ?.13] typ 0.045 [1.14] 45 x 0.026?.032 [0.66?.81] 0.017 0.021 [0.43 0.10] 0.045 [1.14] 0.020 [0.51] 0.610 0.020 [15.49 0.51] 0.105 0.015 [2.67 0.38] typ typ min typ seating plane typ 0.165?.180 [4.19?.57] typ typ 45 x 0.004 [0.10] physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm34c02 rev. d.2 nm34c02 2k-bit standard 2-wire bus interface ? 1999 fairchild semiconductor corporation march 1999 nm34c02 2k-bit standard 2-wire bus interface designed with permanent write-protection for first 128 bytes for serial presence detect application on memory modules general description the nm34c02 is 2048 bits of cmos non-volatile electrically erasable memory. it is designed to support serial presence detect circuitry in memory modules. this communications proto- col uses clock (scl) and data i/o (sda) lines to synchro- nously clock data between the master (for example a micropro- cessor) and the slave eeprom device(s). the contents of the non-volatile memory allows the cpu to determine the capacity of the module and the electrical character- istics of the memory devices it contains. this will enable "plug and play" capability as the module is read and pc main memory resources utilized through the memory controller. the first 128 bytes of the memory of the nm34c02 can be permanently write protected by writing to the "write protect" register. write protect implementation details are described under the section titled addressing the wp register . the nm34c02 is available in a jedec standard tssop package for low profile memory modules for systems requiring efficient space utilization such as in a notebook computer. two options are available: l - low voltage and lz - low power, allowing the part to be used in systems where battery life is of primary importance. block diagram features n extended operating voltage: 2.7v-5.5v n write-protection for first 128 bytes n 200 m a active current typical C 10 m a standby current typical C 1.0 m a standby current typical (l) C 0.1 m a standby current typical (lz) n iic compatible interface C provides bidirectional data transfer protocol n sixteen byte page write mode C minimizes total write time per byte n self timed write cycle - typical write cycle time of 6ms n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin tssop and 8-pin so ds012821-1 h.v. generation timing &control e 2 prom array 16 x 16 x 8 16 ydec 8 data register xdec control logic word address counter slave address register & comparator start stop logic start cycle 16 4 4 ck d in r/w load inc sda v ss v cc d out a2 a1 a0 device address bits 0/1/2/3 scl write protect register
2 www.fairchildsemi.com nm34c02 rev. d.2 nm34c02 2k-bit standard 2-wire bus interface a0 a1 a2 v ss v cc nc scl sda 8 7 6 5 1 2 3 4 nm34c02 ds012821-2 connection diagram so (m8) and tssop (mt8) package top view see package number m08a and mtc08 pin names a0,a1,a2 device address inputs v ss ground sda data i/o scl clock input nc no connection v cc power supply ordering information nm34c02 xx x x package m8 = 8 pin soic mt8 = 8 pin tssop temperature range blank = 0 c to +70 c e = -40 c to +85 c voltage range blank = 4.5v to 5.5v l = 2.7v to 4.5v lz = 2.7v to 4.5v and < 1 m a standby current device 2k iic serial eeprom ds012821-21
3 www.fairchildsemi.com nm34c02 rev. d.2 nm34c02 2k-bit standard 2-wire bus interface product specifications absolute maximum ratings ambient storage temperature C65 c to +150 c all input or output voltages with respect to ground 6.5v to C0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm34c02 0 c to +70 c nm34c02e -40 c to +85 c positive power supply nm34c02 4.5v to 5.5v nm34c02l 2.7v to 4.5v nm34c02lz 2.7v to 4.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 100 khz 0.2 1.0 ma i sb standby current v in = gnd or v cc 10 50 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 100 khz 0.2 1.0 ma i sb standby current for l v in = gnd or v cc 110 m a standby current for lz v in = gnd or v cc 0.1 1 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm34c02 rev. d.2 nm34c02 2k-bit standard 2-wire bus interface ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf read and write cycle limits (standard and low v cc range 2.7v - 4.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 m s t buf time the bus must be free before 4.7 1.3 m s a new transmission can start t hd:sta start condition hold time 4.0 0.6 m s t low clock low period 4.7 1.5 m s t high clock high period 4.0 0.6 m s t su:sta start condition setup time 4.7 0.6 m s (for a repeated start condition) t hd:dat data in hold time 0 0 m s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 m s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 m s t dh data out hold time 300 50 ns t wr write cycle time - nm34c02 10 10 ms (note 3) - nm34c02l, nm34c02lz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm34c02 bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the device d oes not respond to its slave address.
5 www.fairchildsemi.com nm34c02 rev. d.2 nm34c02 2k-bit standard 2-wire bus interface bus timing background information (iic bus) as mentioned, the iic bus allows synchronous bidirectional com- munication between transmitter/receiver using the scl (clock) and sda (data i/o) lines. all communication must be started with a valid start condition, concluded with a stop condition and acknowledged by the receiver with an acknowledge condi- tion. in addition, since the iic bus is designed to support other devices such as ram, eproms, etc., a device type identifier string must follow the start condition. for eeproms, this 4-bit string is 1010. also refer the addressing the wp register section. as shown below, although the eeproms on the iic bus may be configured in any manner required, the total memory addressed can not exceed 16k (16,384 bits) on the standard iic protocol. ee- prom memory address programming is controlled by 2 methods: ? hardware configuring the a0, a1, and a2 pins (device address pins) with pull-up or pull-down resistors. all unused pins must be grounded (tied to v ss ). ? software addressing the required page block within the device memory array (as sent in the slave address string). addressing an eeprom memory location involves sending a command string with the following information: [device type][device address][page block address][byte address] definitions byte 8 bits of data page 16 sequential addresses (one byte each) that may be programmed during a 'page write' programming cycle page block 2,048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2,048 bits master any iic device controlling the transfer of data (such as a micropro- cessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) example of 16k of memory on 2-wire bus note: the sda pull-up resistor is required due to the open-drain/open collector output of iic bus devices the scl pull-up resistor is recommended because of the normal scl line inactive 'high' state. it is recommended that the total line capacitance be less than 400pf. specific timing and addressing considerations are described in greater detail in the following sections. scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto ds012821-4 ds012821-5 sda scl nm34c02l v cc a0 a1 a2 v ss nm24c02 a0 a1 a2 v ss nm24c04 a0 a1 a2 v ss nm24c08 a0 a1 a2 v ss v cc to v cc or v ss to v cc or v ss to v cc or v ss to v cc or v ss v cc v cc v cc
6 www.fairchildsemi.com nm34c02 rev. d.2 nm34c02 2k-bit standard 2-wire bus interface device address pins memory size number of a0 a1 a2 page blocks nm34c02 adr adr adr 2048 bits 1 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wireCored with any number of open drain or open collector outputs. device operation inputs (a0, a1, a2) device address pins a0, a1, and a2 are connected to v cc or v ss to configure the eeprom chip address. table a shows the active pins across the nm34c02 device family. table 1. device a0 a1 a2 effects of addresses nm34c02l adr adr adr 8 devices max. device operation the nm34c02 supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm34c02 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm34c02 continuously monitors the sda and scl lines for the start condi- tion and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm34c02 to place the device in the standby power mode. acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line to low to acknowledge that it received the eight bits of data. refer to figure 3. the nm34c02 device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm34c02 will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the nm34c02 slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode.
7 www.fairchildsemi.com nm34c02 rev. d.2 nm34c02 2k-bit standard 2-wire bus interface device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier ( see figure 4) . this is fixed as 1010 for all eeprom devices. write cycle timing sda scl stop condition start condition word n 8th bit ack t wr ds012821-6 sda scl start condition stop condition sda scl data stable data change scl from master data output from transmitter data output from receiver 189 start acknowledge ds012821-7 ds012821-8 ds012821-9 data validity (figure 1). start and stop definition (figure 2). all iic eeproms use an internal protocol that defines a page block size of 2k bits (for byte addresses 00 through ff). acknowledge responses from receiver (figure 3).
8 www.fairchildsemi.com nm34c02 rev. d.2 nm34c02 2k-bit standard 2-wire bus interface device addressing (continued) slave addresses (figure 4). refer to the following table for slave address string details: device a0 a1 a2 page page block blocks addresses nm34c02 a a a 1 (2k) (none) write operations the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the nm34c02 recognizes the start condi- tion, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions. byte write for a write operation a second address field is required which is a byte address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page block of memory. upon receipt of the byte address the nm34c02 responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm34c02 begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the nm34c02 inputs are disabled, and the device will not respond to any requests from the master. refer to figure 5 for the address, acknowledge and data transfer sequence. page write the nm34c02 is capable of a sixteen byte page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to fifteen more bytes. after the receipt of each byte, the nm34c02 will respond with an acknowledge. after the receipt of each byte, the internal address counter increments to the next address and the next sda data is accepted. if the master should transmit more than sixteen bytes prior to generating the stop condition, the address counter will 'roll over' and the previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 6 for the address, acknowl- edge, and data transfer sequence. acknowledge polling once the stop condition is issued to indicate the end of the hosts write operation the nm34c02 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm34c02 is still busy with the write operation no ack will be returned. if the nm34c02 has completed the write operation an ack will be returned and the host can then proceed with the next read or write operation. software write protect write protection on the nm34c02 protects the first 128 bytes of the eeprom memory. write protection is implemented through a seperate register called the write protect (wp) register and writing to this wp register permanently write protects the memory. this wp register is a "one-time-only-write" register. once this register is written, it cannot be erased. after the first write to this register, all future access' to this register are ignored as if an invalid iic cycle occured. to write protect, the user must perform a byte write to the wp register. this will permanently disable programming to the first 128 bytes of memory. addressing the wp register addressing the wp register is very similar to accessing any memory array with the following difference: instead of the conventional "1010" iic device address, the unused iic device address "0110" is used to access just the wp register. device address "1010" will be used for all the typical memory array access. with this difference in place, accessing the wp register is same as a typical iic byte write cycle as described under "write operations" section. all timing information and waveform details remain the same. the "byte address" and the "data" fields of the byte write cycle serve as place holders and can be of any value (don't care). refer to figure 7 . device type identifier device address 1 0 1 0 a2 a1 a0 r/w (lsb) nm34c02 ds012821-10
9 www.fairchildsemi.com nm34c02 rev. d.2 nm34c02 2k-bit standard 2-wire bus interface s t o p bus activity: master sda line data n + 15 data n + 1 data n byte address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master sda line s t o p bus activity: master sda line bus activity: device address data don't care don't care byte address a c k s t a r t slave address a c k a c k ds012821-14 ds012821-15 ds012821-16 write protect scheme (continued) byte write (figure 5). page write (figure 6). wp register write (figure 7). read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the nm34c02 contains an address counter that main- tains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the nm34c02 issues an acknowledge and transmits the data byte. the master will not acknowledge the transfer but does generate a stop condition, and therefore the nm34c02 discontinues trans- mission. refer to figure 8 for the sequence of address, acknowl- edge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address, r/w bit set to zero, and then the word address to be read. after the slave word address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to one. this will be followed by an acknowl- edge from the nm34c02 and then by the eight bit word. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm34c02 discontinues trans- mission. refer to figure 9 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm34c02 continues to output data for each acknowl- edge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condi- tion. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read
10 www.fairchildsemi.com nm34c02 rev. d.2 nm34c02 2k-bit standard 2-wire bus interface read operations (continued) operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter 'rolls over' and the nm34c02 continues to output data for each acknowledge re- ceived. refer to figure 10 for the address, acknowledge, and data transfer sequence. s t o p a c k slave address a c k a c k s t a r t s t a r t byte address slave address bus activity: master sda line s data n s t o p a c k bus activity: master sda line a c k data n + x a c k data n + 2 data n +1 data n a c k slave address s t o p data a c k s t a r t slave address bus activity: master sda line ds012821-17 ds012821-18 ds012821-19 current address read (figure 8). random read (figure 9). sequential read (figure 10). note: due to open drain configuration of sda, a bus-level resistor is called for (typical value = 4.7 w ) typical system configuration (figure 11). sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc ds012821-20
11 www.fairchildsemi.com nm34c02 rev. d.2 nm34c02 2k-bit standard 2-wire bus interface 8-pin molded small outline package (m8) order number nm34c02lm8/lzm8 package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
12 www.fairchildsemi.com nm34c02 rev. d.2 nm34c02 2k-bit standard 2-wire bus interface physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 8-pin molded tssop, jedec (mt8) order number nm34c02lmt8/lzmt8 package number mtc08 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
1 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect ? 1999 fairchild semiconductor corporation nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect designed with permanent write-protection for first 128 bytes for serial presence detect application on memory modules (pc100 compliant) general description the nm34w02 is 2048 bits of cmos non-volatile electrically erasable memory. this device is specifically designed to support serial presence detect circuitry in memory modules. this com- munications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for ex- ample a microprocessor) and the slave eeprom device(s). the contents of the non-volatile memory allows the cpu to determine the capacity of the module and the electrical character- istics of the memory devices it contains. this will enable "plug and play" capability as the module is read and pc main memory resources utilized through the memory controller. the first 128 bytes of the memory of the nm34w02 can be permanently write protected by writing to the "write protect" register. write protect implementation details are described under the section titled addressing the wp register . in addition, like the nm24wxx product family, the entire memory array can be write-protected through "wp" pin. the nm34w02 is available in a jedec standard tssop package for low profile memory modules for systems requiring efficient space utilization such as in a notebook computer. two options are available: l - low voltage and lz - low power, allowing the part to be used in systems where battery life is of primary importance. block diagram features n pc100 compliant n extended operating voltage: 2.7v-5.5v n software write-protection for first 128 bytes n hardware write-protection for entire memory array n 200 m a active current typical C 1.0 m a standby current typical (l) C 0.1 m a standby current typical (lz) n iic compatible interface C provides bidirectional data transfer protocol n sixteen byte page write mode C minimizes total write time per byte n self timed write cycle - typical write cycle time of 6ms n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin tssop and 8-pin so n temperature ranges: commercial and extended ds500078-1 h.v. generation timing &control e 2 prom array 16 x 16 x 8 16 ydec 8 data register xdec control logic word address counter slave address register & comparator start stop logic start cycle 16 4 4 ck d in r/w load inc sda v ss v cc wp d out a2 a1 a0 device address bits 0/1/2/3 scl write protect register march 1999
2 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect a0 a1 a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm34w02 ds500078-2 so (m8) and tssop (mt8) package connection diagram top view see package number m08a and mtc08 pin names a0,a1,a2 device address inputs v ss ground sda data i/o scl clock input wp write protect v cc power supply ordering information nm 34 w 02 lz e xx letter description package m8 8-pin so8 mt8 8-pin tssop temp. range none 0 to 70 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current density 02 2k w full array write protect interface 34 iic nm fairchild non-volatile memory
3 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect product specifications absolute maximum ratings ambient storage temperature C65 c to +150 c all input or output voltages with respect to ground 6.5v to C0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm34w02 0 c to +70 c nm34w02e -40 c to +85 c positive power supply nm34w02 4.5v to 5.5v nm34w02l 2.7v to 4.5v nm34w02lz 2.7v to 4.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 100 khz 0.2 1.0 ma i sb standby current v in = gnd or v cc 10 50 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 100 khz 0.2 1.0 ma i sb standby current for l v in = gnd or v cc 110 m a standby current for lz v in = gnd or v cc 0.1 1 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf read and write cycle limits (standard and low v cc range 2.7v - 5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 m s t buf time the bus must be free before 4.7 1.3 m s a new transmission can start t hd:sta start condition hold time 4.0 0.6 m s t low clock low period 4.7 1.5 m s t high clock high period 4.0 0.6 m s t su:sta start condition setup time 4.7 0.6 m s (for a repeated start condition) t hd:dat data in hold time 0 0 ns t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 m s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 m s t dh data out hold time 300 50 ns t wr write cycle time - nm34w02 10 10 ms (note 3) - nm34w02l, nm34w02lz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm34w02 bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the device d oes not respond to its slave address.
5 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect bus timing background information (iic bus) as mentioned, the iic bus allows synchronous bidirectional com- munication between transmitter/receiver using the scl (clock) and sda (data i/o) lines. all communication must be started with a valid start condition, concluded with a stop condition and acknowledged by the receiver with an acknowledge condi- tion. in addition, since the iic bus is designed to support other devices such as ram, eproms, etc., a device type identifier string must follow the start condition. for eeproms, this 4-bit string is 1010. also refer the addressing the wp register section. as shown below, although the eeproms on the iic bus may be configured in any manner required, the total memory addressed can not exceed 16k (16,384 bits) on the standard iic. eeprom memory address programming is controlled by 2 methods: ? hardware configuring the a0, a1, and a2 pins (device address pins) with pull-up or pull-down to v cc or v ss . all unused pins must be grounded (tied to v ss ). ? software addressing the required page block within the device memory array (as sent in the slave address string). addressing an eeprom memory location involves sending a command string with the following information: [device type][device address][page block address][byte address] definitions byte 8 bits of data page 16 sequential addresses (one byte each) that may be programmed during a 'page write' programming cycle page block 2,048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2,048 bits master any iic device controlling the transfer of data (such as a micropro- cessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) example of 16k of memory on 2-wire bus note: the sda pull-up resistor is required due to the open-drain/open collector output of iic bus devices. the scl pull-up resistor is recommended because of the normal scl line inactive 'high' state. it is recommended that the total line capacitance be less than 400pf. specific timing and addressing considerations are described in greater detail in the following sections. scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto ds500078-5 ds500078-6 sda scl nm34c02l v cc v cc a0 a1 a2 v ss nm24c02 a0 a1 a2 v ss nm24c04 a0 a1 a2 v ss nm24c08 a0 a1 a2 v ss v cc to v cc or v ss to v cc or v ss to v cc or v ss to v cc or v ss v cc v cc v cc
6 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect device address pins memory size number of a0 a1 a2 page blocks nm34w02 adr adr adr 2048 bits 1 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wireCored with any number of open drain or open collector outputs. device operation inputs (a0, a1, a2) device address pins a0, a1, and a2 are connected to v cc or v ss to configure the eeprom chip address. table a shows the active pins across the nm34w02 device family. table 1. device a0 a1 a2 effects of addresses nm34w02 adr adr adr 8 devices max. device operation the nm34w02 supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm34w02 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm34w02 continuously monitors the sda and scl lines for the start condi- tion and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm34w02 to place the device in the standby power mode. acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line to low to acknowledge that it received the eight bits of data. refer to figure 3. the nm34w02 device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm34w02 will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the nm34w02 slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode.
7 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier ( see figure 4) . this is fixed as 1010 for all eeprom devices. write cycle timing sda scl stop condition start condition word n 8th bit ack t wr ds500078-7 sda scl start condition stop condition sda scl data stable data change scl from master data output from transmitter data output from receiver 189 start acknowledge ds500078-8 ds500078-9 data validity (figure 1). start and stop definition (figure 2). all iic eeproms use an internal protocol that defines a page block size of 2k bits (for byte addresses 00 through ff). acknowledge responses from receiver (figure 3). ds500078-10
8 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect device addressing (continued) slave addresses (figure 4). refer to the following table for slave address string details: device a0 a1 a2 page page block blocks addresses nm34w02 a a a 1 (2k) (none) write operations the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the nm34w02 recognizes the start condi- tion, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions. byte write for a write operation a second address field is required which is a byte address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page block of memory. upon receipt of the byte address the nm34w02 responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm34w02 begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the nm34w02 inputs are disabled, and the device will not respond to any requests from the master. refer to figure 5 for the address, acknowledge and data transfer sequence. page write the nm34w02 is capable of a sixteen byte page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to fifteen more bytes. after the receipt of each byte, the nm34w02 will respond with an acknowledge. after the receipt of each byte, the internal address counter increments to the next address and the next sda data is accepted. if the master should transmit more than sixteen bytes prior to generating the stop condition, the address counter will 'roll over' and the previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 6 for the address, acknowl- edge, and data transfer sequence. acknowledge polling once the stop condition is issued to indicate the end of the hosts write operation the nm34w02 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm34w02 is still busy with the write operation no ack will be returned. if the nm34w02 has completed the write operation an ack will be returned and the host can then proceed with the next read or write operation. software write protect software write protection on the nm34w02 protects the first 128 bytes of the eeprom memory. software write protection is implemented through a seperate register called the write pro- tect (wp) register and writing to this wp register permanently write protects the memory. this wp register is a "one-time- only-write" register. once this register is written, it cannot be erased. after the first write to this register, all future access' to this register are ignored as if an invalid iic cycle occured. to write protect, the user must perform a byte write to the wp register. this will permanently disable programming to the first 128 bytes of memory. addressing the wp register addressing the wp register is very similar to accessing any memory array with the following difference: instead of the conventional "1010" iic device address, the unused iic device address "0110" is used to access just the wp register. device address "1010" will be used for all the typical memory array access. with this difference in place, accessing the wp register is same as a typical iic byte write cycle as described under "write operations" section. all timing information and waveform details remain the same. the "byte address" and the "data" fields of the byte write cycle serve as place holders and can be of any value (don't care). refer to figure 7 . hardware write protect programming of the memory will not take place if the wp pin of the nm34w02 is connected to v cc , regardless of whether the soft- ware write protect register has been implemented or not. the nm34w02 will accept slave and word addresses; but if the memory accessed is write protected by the wp pin, the nm34w02 will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. (note: if the wp pin is set to v cc , it will prevent the software write protect register from being written.) device type identifier device address 1 0 1 0 a2 a1 a0 r/w (lsb) nm34w02 ds500078-11
9 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect s t o p bus activity: master sda line data n + 15 data n + 1 data n byte address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master sda line s t o p bus activity: master sda line bus activity: device address data don't care don't care byte address a c k s t a r t slave address a c k a c k ds500078-15 ds500078-16 ds500078-17 write protect scheme (continued) byte write (figure 5). page write (figure 6). wp register write (figure 7). read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the nm34w02 contains an address counter that main- tains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the nm34w02 issues an acknowledge and transmits the data byte. the master will not acknowledge the transfer but does generate a stop condition, and therefore the nm34w02 discontinues trans- mission. refer to figure 8 for the sequence of address, acknowl- edge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address, r/w bit set to zero, and then the word address to be read. after the slave word address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to one. this will be followed by an acknowl- edge from the nm34w02 and then by the eight bit word. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm34w02 discontinues trans- mission. refer to figure 9 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm34w02 continues to output data for each acknowl- edge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter 'rolls over' and the nm34w02 continues to output data for each acknowledge re- ceived. refer to figure 10 for the address, acknowledge, and data transfer sequence.
10 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect s t o p a c k slave address a c k a c k s t a r t s t a r t byte address slave address bus activity: master sda line data n s t o p a c k bus activity: master sda line a c k data n + x a c k data n + 2 data n +1 data n a c k slave address s t o p data a c k s t a r t slave address bus activity: master sda line ds500078-18 ds500078-19 ds500078-20 sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc ds500078-21 current address read (figure 8) random read (figure 9) sequential read (figure 10) note: due to open drain configuration of sda, a bus-level resistor is called for (typical value = 4.7 w ) typical system configuration (figure 11)
11 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect 8-pin molded small outline package (m8) order number nm34w02lm8/lzm8 package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
12 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect physical dimensions inches (millimeters) unless otherwise noted 8-pin molded tssop, jedec (mt8) order number nm34w02lmt8/lzmt8 package number mtc08 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
1 www.fairchildsemi.com nm93c06 rev. c.1 nm93c06 256-bit serial cmos eeprom (microwire? bus interface) march 1999 ? 1999 fairchild semiconductor corporation nm93c06 256-bit serial cmos eeprom (microwire? bus interface) general description the nm93c06 devices are 256 bits of cmos non-volatile electri- cally erasable memory divided into 16 16-bit registers. they are fabricated using fairchild semiconductor's floating-gate cmos process for high reliability, high endurance and low power con- sumption. these memory devices are available in an 8-pin soic or 8-pin tssop package for small space considerations. the serial interface that operates these eeproms is microwire compatible for simple interface to standard microcontrollers and microprocessors. there are 7 instructions which control this device: read, write enable, erase, erase all, write, write all, and write disable. the ready/busy status is available on the do pin to indicate the completion of a programming cycle. block diagram features n device status during programming mode n typical active current of 200 m a 10 m a standby current typical 1 m a standby current typical (l) 0.1 m a standby current typical (lz) n no erase required before write n reliable cmos floating gate technology n 2.7v to 5.5v operation in all modes n microwire compatible serial l/o n self-timed programming cycle n 40 years data retention n endurance: 1,000,000 data changes n packages available: 8-pin so, 8-pin dip, 8-pin tssop ds500079-1 instruction decoder control logic, and clock generators high voltage generator and program timer instruction register address register eeprom array read/write amps data in/out register 16 bits decoder 1 of 16 16 16 data out buffer v pp v cc cs sk di do v ss
2 www.fairchildsemi.com nm93c06 rev. c.1 nm93c06 256-bit serial cmos eeprom (microwire? bus interface) connection diagrams v cc nc gnd cs sk di do 1 2 3 4 8 7 6 5 nc ds500079-2 dual-in-line package (n), 8-pin so (m8) and 8-pin tssop (mt8) top view see package number n08e, m08a and mtc08 pin names cs chip select sk serial data clock di serial data input do serial data output gnd ground v cc power supply ordering information nm 93 c xx lz e xx letter description package n 8-pin dip m8 8-pin so8 mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current density 06 256 bit c cmos cs data protect and sequential read interface 93 microwire nm fairchild non-volatile memory
3 www.fairchildsemi.com nm93c06 rev. c.1 nm93c06 256-bit serial cmos eeprom (microwire? bus interface) absolute maximum ratings (note 1) ambient storage temperature C65 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v standard v cc (4.5v to 5.5v) dc and ac electrical characteristics symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 1mhz 1 ma i ccs standby current cs = v il 50 m a i il input leakage v in = 0v to v cc 1 m a i ol output leakage (note 2) v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v ol1 output low voltage i ol = 2.1ma 0.4 v v oh1 output high voltage i oh = -400 m a 2.4 v v ol2 output low voltage i ol = 10 m a 0.2 v v oh2 output high voltage i oh = -10 m av cc -0.2 v f sk sk clock frequency (note 3) 0 1 mhz t skh sk high time nm93c06 250 ns nm93c06e/v 300 t skl sk low time 250 ns t sks sk setup time sk must be at v il for 50 ns t sks before cs goes high t cs minimum cs (note 4) 250 ns low time t css cs setup time 50 ns t dh do hold time 70 ns t dis di setup time nm93c06 100 ns nm93c06e/v 200 t csh cs hold time 0 ns t dih di hold time 20 ns t pd1 output delay to "1" 500 ns t pd0 output delay to "0" 500 ns t sv cs to status valid 500 ns t df cs to do in cs = v il 100 ns tri-state t wp write cycle time 10 ms operating range ambient operating temperature nm93c06 0 c to +70 c nm93c06e -40 c to +85 c nm93c06v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v
4 www.fairchildsemi.com nm93c06 rev. c.1 nm93c06 256-bit serial cmos eeprom (microwire? bus interface) absolute maximum ratings (note 1) ambient storage temperature C65 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v low v cc (2.7v to 4.5v) dc and ac electrical characteristics symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 250khz 1ma i ccs standby current cs = v il l 10 m a lz 1 m a i il input leakage v in = 0v to v cc 1 m a i ol output leakage (note 2) v il input low voltage -0.1 0.15 v cc v v ih input high voltage 0.8 v cc v cc +1 v ol output low voltage i ol = 10 m a 0.1 v cc v v oh output high voltage i oh = -10 m a 0.9 v cc v f sk sk clock frequency (note 3) 0 250 khz t skh sk high time 1 m s t skl sk low time 1 m s t sks sk setup time sk must be at v il for 0.2 m s t sks before cs goes high t cs minimum cs (note 4) 1 m s low time t css cs setup time 0.2 m s t dh do hold time 70 ns t dis di setup time 0.4 m s t csh cs hold time 0 ns t dih di hold time 0.4 m s t pd1 output delay to "1" 2 m s t pd0 output delay to "0" 2 m s t sv cs to status valid 1 m s t df cs to do in cs = v il 0.4 m s tri-state t wp write cycle time 15 ms operating range ambient operating temperature nm93c06l/lz 0 c to +70 c nm93c06le/lze -40 c to +85 c nm93c06lv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 4.5v capacitance t a = 25 c, f = 1 mhz (note 5) symbol test typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20na range. note 3 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 4 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagram on the following page.) note 5 : this parameter is periodically sampled and not 100% tested. ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v .03v/1.8v 1.0v 0.8v/1.5v 10 m a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v -2.1ma/0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf)
5 www.fairchildsemi.com nm93c06 rev. c.1 nm93c06 256-bit serial cmos eeprom (microwire? bus interface) functional description the nm93c06 device has 7 instructions as described below. note that the msb of any instruction is a 1 and is viewed as a start bit in the interface sequence. the next 8 bits carry the op code and the 6-bit address for register selection. read (read): the read instruction outputs serial data on the d0 pin. after a read instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a 16-bit serial-out shift register. a dummy bit (logical 0) precedes the 16-bit data output string. output data changes are initiated by a low to high transition of the sk clock. write enable (wen): when v cc is applied to the part, it 'powers-up' in the write disable (wds) state. therefore, all programming modes must be pre- ceded by a write enable (wen) instruction. once a write enable instruction is executed, programming remains enabled until awrite disable (wds) instruction is executed or v cc is removed from the part. erase (erase): the erase instruction will program all bits in the specified register to the logical 1 state. cs is brought low following the loading of the last address bit. this falling edge of the cs pin initiates the self-timed programming cycle. the do pin indicates the ready/busy status of the chip if cs is brought high after a minimum time of t cs . do = logical 0 indicates that the register, at the address specified in the instruction, has been erased, and the part is ready for another instruction. write (write): the write instruction is followed by the address and 16 bits of data to be written into the specified address. after the last bit of data is put in the data-in (di) pin, cs must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. the d0 pin indicates the ready/ busy status of the chip if cs is brought high after a minimum of t cs . d0 = logical 1 indicates that the register at the address specified in the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction. erase all (eral): the eral instruction will simultaneously program all registers in the memory array and set each bit to the logical 1 state. the erase all cycle is identical to the erase cycle except for the different op- code. as in the erase mode, the do pin indicates the ready/ busy status of the chip if cs is brought high after the t cs interval. write all (wrall): the wrall instruction will simultaneously program all registers with the data pattern specified in the instruction. as in the write mode, the do pin indicates the ready/busy status of the chip if cs is brought high after the t cs interval. write disable (wds): to protect against accidental data disturb, the wds instruction disables all programming modes and should follow all program- ming operations. execution of a read instruction is independent of both the wen and wds instructions. note: the fairchild cmos eeproms do not require an "erase" or "erase all" operation prior to the "write" and "write all" instructions. the "erase" and "erase all" instructions are included to maintain compatibility with earlier technology eeproms. instruction set for the nm93c06 instruction sb op. code address data comments read 1 10 00 a3 a2 a1 a0 reads data stored in memory, at specified address. wen 1 00 11xxxx write enable must precede all programming modes. erase 1 11 00 a3 a2 a1 a0 erase selected register. write 1 01 00 a3 a2 a1 a0 d15-d0 writes selected register. eral 1 00 10xxxx erases all registers. wrall 1 00 01xxxx d15-d0 writes all registers. wds 1 00 00xxxx disables all programming instructions. note: address bits a5 and a4 should be set to '0' for read, erase and write instructions.
6 www.fairchildsemi.com nm93c06 rev. c.1 nm93c06 256-bit serial cmos eeprom (microwire? bus interface) 0 1 cs sk di do 10 0 d15 . . . d0 0 . . . a3 a0 t cs read 1 cs sk di 00 1 1 . . . xx t cs wen 1 cs sk di 00 0 0 . . . xx t cs wds ds500079-5 ds500079-6 ds500079-7 status valid synchronous data timing v ih v il cs v ih v il sk v ih v il di v oh v ol do (read) v oh v ol do (program) t css t sks t dis t dih t pd0 t pd1 t dh t df t df t dh t sv t skh t skl t csh ds500079-4 timing diagrams synchronous data timing read wen wds
7 www.fairchildsemi.com nm93c06 rev. c.1 nm93c06 256-bit serial cmos eeprom (microwire? bus interface) 1 cs sk di do 01 busy ready 00 . . . a3 a0 d15 d0 . . . t cs t wp 1 cs sk di do 0001 busy ready don't care (4 bits) . . . d15 d0 t cs wrall t wp 111 cs sk di do 00 busy ready standby tri-state tri-state a3 . . . a0 erase t wp t cs ds500079-8 ds500079-9 ds500079-10 100 cs sk di do 10 busy ready standby check status don't care bits (4 bits) tri-state tri-state eral t wp t cs ds500079-11 eral erase wrall timing diagrams (continued) write
8 www.fairchildsemi.com nm93c06 rev. c.1 nm93c06 256-bit serial cmos eeprom (microwire? bus interface) physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ. 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x molded small out-line package (m8) package number m08a 8-pin molded tssop, jedec (mt8) package number mtc08
9 www.fairchildsemi.com nm93c06 rev. c.1 nm93c06 256-bit serial cmos eeprom (microwire? bus interface) physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) min + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 ident option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 (7.112) dia 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max. 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm93c46 rev. c.2 nm93c46 1k-bit serial cmos eeprom (microwire? bus interface) march 1999 ? 1999 fairchild semiconductor corporation nm93c46 1k-bit serial cmos eeprom (microwire? bus interface) general description the nm93c46 devices are 1024 bits of cmos non-volatile electrically erasable memory divided into 64 16-bit registers. they are fabricated using fairchild semiconductor's floating-gate cmos process for high reliability, high endurance and low power con- sumption. these memory devices are available in an 8-pin soic or 8-pin tssop package for small space considerations. the serial interface that operates these eeproms is microwire compatible for simple interface to standard microcontrollers and microprocessors. there are 7 instructions which control this device: read, write enable, erase, erase all, write, write all, and write disable. the ready/busy status is available on the do pin to indicate the completion of a programming cycle. block diagram features n device status during programming mode n typical active current of 200 m a 10 m a standby current typical 1 m a standby current typical (l) 0.1 m a standby current typical (lz) n no erase required before write n reliable cmos floating gate technology n 2.7v to 5.5v operation in all modes n microwire compatible serial l/o n self-timed programming cycle n 40 years data retention n endurance: 1,000,000 data changes n packages available: 8-pin so, 8-pin dip, 8-pin tssop ds500080-1 instruction decoder control logic, and clock generators high voltage generator and program timer instruction register address register eeprom array read/write amps data in/out register 16 bits decoder 1 of 16 data out buffer v pp v cc cs sk di do v ss
2 www.fairchildsemi.com nm93c46 rev. c.2 nm93c46 1k-bit serial cmos eeprom (microwire? bus interface) connection diagrams v cc nc gnd cs sk di do 1 2 3 4 8 7 6 5 nc ds500080-2 dual-in-line package (n), 8-pin so (m8) and 8-pin tssop (mt8) top view see package number n08e, m08a and mtc08 pin names cs chip select sk serial data clock di serial data input do serial data output gnd ground v cc power supply ordering information nm 93 c xx t lz e xx letter description package n 8-pin dip m8 8-pin so8 mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current blank normal pin out t rotated die pin out density 46 1k c cmos cs data protect and sequential read interface 93 microwire nm fairchild non-volatile memory nc do di nc v cc cs sk 1 2 3 4 8 7 6 5 gnd ds500080-12 rotated die (93c46t)
3 www.fairchildsemi.com nm93c46 rev. c.2 nm93c46 1k-bit serial cmos eeprom (microwire? bus interface) absolute maximum ratings (note 1) ambient storage temperature C65 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v standard v cc (4.5v to 5.5v) dc and ac electrical characteristics symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 1mhz 1 ma i ccs standby current cs = v il 50 m a i il input leakage v in = 0v to v cc 1 m a i ol output leakage (note 2) v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v ol1 output low voltage i ol = 2.1ma 0.4 v v oh1 output high voltage i oh = -400 m a 2.4 v v ol2 output low voltage i ol = 10 m a 0.2 v v oh2 output high voltage i oh = -10 m av cc -0.2 v f sk sk clock frequency (note 3) 0 1 mhz t skh sk high time nm93c46 250 ns nm93c46e/v 300 t skl sk low time 250 ns t sks sk setup time sk must be at v il for 50 ns t sks before cs goes high t cs minimum cs (note 4) 250 ns low time t css cs setup time 50 ns t dh do hold time 70 ns t dis di setup time nm93c46 100 ns nm93c46e/v 200 t csh cs hold time 0 ns t dih di hold time 20 ns t pd1 output delay to "1" 500 ns t pd0 output delay to "0" 500 ns t sv cs to status valid 500 ns t df cs to do in cs = v il 100 ns tri-state t wp write cycle time 10 ms operating range ambient operating temperature nm93c46 0 c to +70 c nm93c46e -40 c to +85 c nm93c46v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v
4 www.fairchildsemi.com nm93c46 rev. c.2 nm93c46 1k-bit serial cmos eeprom (microwire? bus interface) absolute maximum ratings (note 1) ambient storage temperature C65 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v low v cc (2.7v to 4.5v) dc and ac electrical characteristics symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 250khz 1ma i ccs standby current cs = v il l 10 m a lz 1 m a i il input leakage v in = 0v to v cc 1 m a i ol output leakage (note 2) v il input low voltage -0.1 0.15 v cc v v ih input high voltage 0.8 v cc v cc +1 v ol output low voltage i ol = 10 m a 0.1 v cc v v oh output high voltage i oh = -10 m a 0.9 v cc v f sk sk clock frequency (note 3) 0 250 khz t skh sk high time 1 m s t skl sk low time 1 m s t sks sk setup time sk must be at v il for 0.2 m s t sks before cs goes high t cs minimum cs (note 4) 1 m s low time t css cs setup time 0.2 m s t dh do hold time 70 ns t dis di setup time 0.4 m s t csh cs hold time 0 ns t dih di hold time 0.4 m s t pd1 output delay to "1" 2 m s t pd0 output delay to "0" 2 m s t sv cs to status valid 1 m s t df cs to do in cs = v il 0.4 m s tri-state t wp write cycle time 15 ms operating range ambient operating temperature nm93c46l/lz 0 c to +70 c nm93c46le/lze -40 c to +85 c nm93c46lv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 4.5v capacitance t a = 25 c, f = 1 mhz (note 5) symbol test typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20na range. note 3 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 4 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagram on the following page.) note 5 : this parameter is periodically sampled and not 100% tested. ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v .03v/1.8v 1.0v 0.8v/1.5v 10 m a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v -2.1ma/0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf)
5 www.fairchildsemi.com nm93c46 rev. c.2 nm93c46 1k-bit serial cmos eeprom (microwire? bus interface) functional description the nm93c46 device has 7 instructions as described below. note that the msb of any instruction is a 1 and is viewed as a start bit in the interface sequence. the next 8 bits carry the op code and the 6-bit address for register selection. read (read): the read instruction outputs serial data on the d0 pin. after a read instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a 16-bit serial-out shift register. a dummy bit (logical 0) precedes the 16-bit data output string. output data changes are initiated by a low to high transition of the sk clock. write enable (wen): when v cc is applied to the part, it 'powers-up' in the write disable (wds) state. therefore, all programming modes must be pre- ceded by a write enable (wen) instruction. once a write enable instruction is executed, programming remains enabled until awrite disable (wds) instruction is executed or v cc is removed from the part. erase (erase): the erase instruction will program all bits in the specified register to the logical 1 state. cs is brought low following the loading of the last address bit. this falling edge of the cs pin initiates the self-timed programming cycle. the do pin indicates the ready/busy status of the chip if cs is brought high after a minimum time of t cs . do = logical 0 indicates that the register, at the address specified in the instruction, has been erased, and the part is ready for another instruction. write (write): the write instruction is followed by the address and 16 bits of data to be written into the specified address. after the last bit of data is put in the data-in (di) pin, cs must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. the d0 pin indicates the ready/ busy status of the chip if cs is brought high after a minimum of t cs . d0 = logical 1 indicates that the register at the address specified in the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction. erase all (eral): the eral instruction will simultaneously program all registers in the memory array and set each bit to the logical 1 state. the erase all cycle is identical to the erase cycle except for the different op- code. as in the erase mode, the do pin indicates the ready/ busy status of the chip if cs is brought high after the t cs interval. write all (wrall): the wrall instruction will simultaneously program all registers with the data pattern specified in the instruction. as in the write mode, the do pin indicates the ready/busy status of the chip if cs is brought high after the t cs interval. write disable (wds): to protect against accidental data disturb, the wds instruction disables all programming modes and should follow all program- ming operations. execution of a read instruction is independent of both the wen and wds instructions. note: the fairchild cmos eeproms do not require an "erase" or "erase all" operation prior to the "write" and "write all" instructions. the "erase" and "erase all" instructions are included to maintain compatibility with earlier technology eeproms. instruction set for the nm93c46 instruction sb op. code address data comments read 1 10 a5-a0 reads data stored in memory, at specified address. wen 1 00 11xxxx write enable must precede all programming modes. erase 1 11 a5-a0 erase selected register. write 1 01 a5-a0 d15-d0 writes selected register. eral 1 00 10xxxx erases all registers. wrall 1 00 01xxxx d15-d0 writes all registers. wds 1 00 00xxxx disables all programming instructions.
6 www.fairchildsemi.com nm93c46 rev. c.2 nm93c46 1k-bit serial cmos eeprom (microwire? bus interface) 1 cs sk di do 10 0 d15 . . . d0 a5 . . . a0 t cs read 1 cs sk di 00 1 1 . . . xx t cs wen 1 cs sk di 00 0 0 . . . xx t cs wds ds500080-5 ds500080-6 ds500080-7 status valid synchronous data timing v ih v il cs v ih v il sk v ih v il di v oh v ol do (read) v oh v ol do (program) t css t sks t dis t dih t pd0 t pd1 t dh t df t df t dh t sv t skh t skl t csh ds500080-4 timing diagrams synchronous data timing read wen wds
7 www.fairchildsemi.com nm93c46 rev. c.2 nm93c46 1k-bit serial cmos eeprom (microwire? bus interface) 1 cs sk di do 01 busy ready a5 . . . a0 d15 d0 t cs write t wp 1 cs sk di do 0001 busy ready don't care (4 bits) . . . d15 d0 t cs wrall t wp 111 cs sk di do a5 a4 busy ready standby tri-state tri-state a3 . . . a0 erase t wp t cs ds500080-8 ds500080-9 ds500080-10 100 cs sk di do 10 busy ready standby check status don't care bits (4 bits) tri-state tri-state eral t wp t cs ds500080-11 eral erase wrall timing diagrams (continued) write
8 www.fairchildsemi.com nm93c46 rev. c.2 nm93c46 1k-bit serial cmos eeprom (microwire? bus interface) physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ. 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x molded small out-line package (m8) package number m08a 8-pin molded tssop, jedec (mt8) package number mtc08
9 www.fairchildsemi.com nm93c46 rev. c.2 nm93c46 1k-bit serial cmos eeprom (microwire? bus interface) physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm93c46a rev. d.2 nm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) nm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) general description the nm93c46a is 1,024 bits of cmos nonvolatile, electrically erasable memory available as either 64 16-bit registers or 128 8- bit registers. (the organization is determined by the status of the org input.) this is fabricated using fairchild semiconductors floating gate cmos process for high reliability, high endurance, and low power consumption. the nm93c46a is available in 8-pin dip, so and tssop packages for space considerations. the eeprom is microwire compatible for simple interfacing to a wide variety of microcontrollers and microprocessors. there are 7 instructions that operate the nm93c46a: read, erase/write enable, erase, write, erase/write disable, write all, and erase all. the nm93c46a defaults to the 64 x 16 configuration if the org pin (pin 6) is left floating, as it is internally pulled up to v cc . march 1999 features n 2.7v to 5.5v operation in all modes n typical active current 200 m a 10 m a standby current typical 1 m a standby current typical (l) 0.1 m a standby current typical (lz) n self-timed programming cycle n device status indication during programming mode n no erase required before write n reliable cmos floating gate technology n microwire compatible serial i/o n 40 years data retention n endurance: 1,000,000 data changes n packages available: 8-pin tssop, 8-pin so, 8-pin dip ds011042-1 instruction decoder control logic, and clock generators high voltage generator and program timer instruction register address register eeprom array 1024 bits (64x16) or (128x8) read/write amps data in/out register 16 (or 8) bits decoder 1 of 64 (or 128) data out buffer v pp v cc cs sk di do gnd org ? 1999 fairchild semiconductor corporation block diagram
2 www.fairchildsemi.com nm93c46a rev. d.2 nm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) connection diagrams pin names cs chip select sk serial data clock di serial data input do serial data output v ss ground org memory organizational select nc no connect v cc positive power supply ordering information nm 93 c xx a t lz e xx letter description package n 8-pin dip m8 8-pin so8 mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current blank normal pin out t rotated die pin out a x8 or x16 configuration density 46 1k c cmos cs data protect and sequential read interface 93 microwire nm fairchild non-volatile memory dual-in-line package (n), 8-pin so package (m8) and 8-pin tssop package (mt8) top view see package number n08e, m08a and mtc08 v cc org v ss cs sk di do 1 2 3 4 8 7 6 5 nc ds011042-2 nm93c46a rotated die (93c46at) org do di nc v cc cs sk 1 2 3 4 8 7 6 5 v ss nm93c46a
3 www.fairchildsemi.com nm93c46a rev. d.2 nm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages: with respect to ground v cc +1 to -0.3v lead temperature (soldering, 10 seconds) +300 c eds rating 2000v operating range ambient operating temperature nm93c46a 0 c to +70 c nm93c46ae -40 c to +85 c nm93c46av -40 c to +125 c power supply (v cc ) 4.5v to 5.5v standard v cc (4.5v to .5v) dc and ac electrical characteristics symbol parameter part number conditions min max units i cca operating current cs = v ih ,sk=1 mhz 1 ma i ccs standby current cs = 0v, org = v cc or nc 50 m a i il input leakage v in = 0v to v cc (note 2) -1 1 m a i ilo input leakage org tied to v cc -1 1 m a org pin org tied to v ss (note 3) -2.5 2.5 i ol output leakage v in = 0v to v cc -1 1 m a v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v v ol1 output low voltage i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = -400 m a 2.4 v v ol2 output low voltage i ol = 10 m a 0.2 v v oh2 output high voltage i ol = -10 m av cc - 0.2 v f sk sk clock frequency (note 4) 0 1 mhz t skh sk high time nm93c46a 250 ns nm93c46ae/v 300 t skl sk low time 250 ns t sks sk setup time sk must be at v il for 50 ns t sks before cs goes high t cs minimum cs (note 5) 250 ns t css cs setup time 50 ns t dh do hold time 70 ns t dis di setup time nm93c46a 100 ns nm93c46ae/v 200 t csh cs hold time 0 ns t dih di hold time 20 ns t pd1 output delay to 1 500 ns t pd0 output delay to 0 500 ns t sv cs to status valid 500 ns t df cs to do in cs = v il 100 ns tri-state ? t wp write cycle time 10 ms
4 www.fairchildsemi.com nm93c46a rev. d.2 nm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v .03v/1.8v 1.0v 0.8v/1.5v 10 m a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v -2.1ma/0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf) absolute maximum ratings (note 1) ambient storage temperature C65 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v low v cc (2.7v to 4.5v) dc and ac electrical characteristics symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 250khz 1ma i ccs standby current cs = v il l 10 m a lz 1 m a i il input leakage v in = 0v to v cc (note 2) 1 m a i ilo input leakage org tied to v cc -1 1 m a org pin org tied to v ss (note 3) -2.5 2.5 i ol output leakage v in = 0v to v cc 1 m a v il input low voltage -0.1 0.15 v cc v v ih input high voltage 0.8 v cc v cc +1 v ol output low voltage i ol = 10 m a 0.1 v cc v v oh output high voltage i oh = -10 m a 0.9 v cc v f sk sk clock frequency (note 4) 0 250 khz t skh sk high time 1 m s t skl sk low time 1 m s t sks sk setup time sk must be at v il for 0.2 m s t sks before cs goes high t cs minimum cs (note 5) 1 m s low time t css cs setup time 0.2 m s t dh do hold time 70 ns t dis di setup time 0.4 m s t csh cs hold time 0 ns t dih di hold time 0.4 m s t pd1 output delay to "1" 2 m s t pd0 output delay to "0" 2 m s t sv cs to status valid 1 m s t df cs to do in cs = v il 0.4 m s tri-state t wp write cycle time 15 ms operating range ambient operating temperature nm93c46al/lz 0 c to +70 c nm93c46ale/lze -40 c to +85 c nm93c46a lv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 4.5v capacitance t a = 25 c, f = 1 mhz symbol test typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20 na range. note 3 : the org pin may draw > 1 m a when in the x8 mode ude to an internal pull-up transistor. note 4 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 5 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagrams in the following pages.)
5 www.fairchildsemi.com nm93c46a rev. d.2 nm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) microwire i/o pin description chip select (cs): this pin enables and disables the microwire device and performs 3 general functions: 1. when in the low state, the microwire device is disabled and the output tri-stated (high impedance). if this pin is brought high (rising edge active), all internal registers are reset and the device is enabled, allowing microwire communication via di/do pins. to restate, the cs pin must be held high during all device communication and opcode functions. if the cs pin is brought low, all functions will be disabled and reset when cs is brought high again. the exception to this is when a programming cycle is initiated (see 2 and 3). again, all activity on the cs, di and do pins is ignored until cs is brought high. 2. after entering all required opcode and address data, bringing cs low initiates the (asynchronous) programming cycle. 3. when programming is in progress, the data-out pin will display the programming status as either busy (do low) or ready (do high) when cs is brought high. (again, the output will be tri-stated when cs is low.) to restate, during programming, the cs pin may be brought high and low any number of times to view the programming status without affect the programming operation. once programming is completed (output in ready state), the output is 'cleared' (returned to normal tri-state condition) by clocking in a start bit. after the start bit is clocked in, the output will return to a tri-stated condition. when clocked in, this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. serial clock (sk): this pin is the clock input (rising edge active) for clocking in all opcodes and data on the di pin and clocking out all data on the do pin.however, this pin has no effect on the asynchronous program- ming cycle (see the cs pin section) as the busy/ready status is a function of the cs pin only. data-in (di): all serial communication into the device is performed using this input pin (rising edge active). in order to avoid false start bits, or related issues, it is advised to keep the di pin in the low state unless actually clocking in data bits (start bit, opcode, address or incoming data bits to be programmed). please note that the first '1' clocked into the device (after cs is brought high) is seen as a start bit and the beginning of a serial command string, so caution must be observed when bringing cs high. data-out (do): all serial communication out of the device (read opcode) is performed using this output pin (rising edge active) as well as indicating the ready/busy status duting the asynchronous programming cycle. note that, during read operations, the output data is clocked out after the last address bit (a0) is clocked in. if a 3-wire application is required (where di and do are tied together), sections in an-758, or related application notes, must be followed for correct operation. organization (org): this pin controls the device architecture (8-bit data word vs. 16-bit data word). if the org pin is brought to v cc , the device is configured with a 16-bit data word and if the org pin is brought to v ss (ground), the device is configured with an 8-bit data word (refer to other sections for details of both configurations). if the org pin is left floating, the device will default to a 16-bit data word. instruction set for the nm93c46a org memory pin configuration # of address bits logic 0 128 x 8 7 bits 1 64 x 16 6 bits
6 www.fairchildsemi.com nm93c46a rev. d.2 nm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) 64 by 16-bit organization (nm93c46a when org = v cc or nc) instruction sb op-code address data comments 2 bits 6 bits 16 bits read 1 10 a5Ca0 read data stored in selected registers. ewen 1 00 11xxxx enables programming modes. ewds 1 00 00xxxx disables all programming modes. erase 1 11 a5Ca0 erases selected register. write 1 01 a5Ca0 d15Cd0 writes data pattern d15Cd0 into selected register. eral 1 00 10xxxx erases all registers. wral 1 00 01xxxx d15Cd0 writes data pattern d15Cd0 into all registers. 128 by 8-bit organization (nm93c46a when org = gnd) instruction sb op-code address data comments 2 bits 7 bits 8 bits read 1 10 a6Ca0 read data stored in selected registers. ewen 1 00 11xxxxx enables programming modes. ewds 1 00 00xxxxx disables all programming modes. erase 1 11 a6Ca0 erases selected register. write 1 01 a6Ca0 d7Cd0 writes data pattern d7Cd0 into selected register. eral 1 00 10xxxxx erases all registers. wral 1 00 01xxxxx d7Cd0 writes data pattern d7Cd0 into all registers. functional description programming: 1. programming is initiated by clocking in the start bit, opcode bits, address bits and the 8/16 data bits (refer to the org pin section). 2. programming is started by bringing the cs pin low. once the programming cycle is started, it cannot be stopped. (bringing v cc low will stop any programming, but will also result in data corruption.) 3. the status of the programming cycle (busy or ready) is observed by bringing the cs pin high and observing the output state. if the output is low, the device is still program- ming (busy). if the output is high, the programming cycle has been completed and the device is ready for the next operation. note that the output will be tri-stated each time cs is brought low and the r/b status will be shown each time cs is brought high. 4. after programming, the ready state (output high) can be reset and the output tri-stated by clocking in a single start bit. this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. in any case, clocking in a '1' bit will tri-state the output. read (read): the read instruction outputs serial data on the do pin. after a read instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a serial-out shift register. a dummy bit (logical 0) precedes the serial data output string. output data changes are initiated by a low to high transition of sk after the last address bit (a0) is clocked in. erase/write enable (ewen): when v cc is applied to the part, it powers up in the erase/write disable (ewds) state. therefore, all programming modes must be preceded by an erase/write enable (ewen) instruction. once an erase/write enable instruction is executed, programming remains enabled until an erase/write disable (ewds) instruction is executed or v cc is removed from the part.
7 www.fairchildsemi.com nm93c46a rev. d.2 nm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) status valid synchronous data timing v ih v il cs v ih v il sk v ih v il di v oh v ol do (read) v oh v ol do (program) t css t sks t dis t dih t pd0 t pd1 t dh t df t df t dh t sv t skh t skl t csh ds011042-4 functional description (continued) erase/write disable (ewds): to protect against accidental data overwrites, the erase/write disable (ewds) instruction disables all programming modes and should follow all programming operations. execution of a read instruction is independent of both the even and ewds instruc- tions. erase (erase): the erase instruction will program all bits in the specified register to the logical 1 state. please refer to the programming section for details. write (write): the write instruction is followed by 16 bits of data (or 8 bits of data when using the nm93c46a in the x8 organization) to be written into the specified address. please refer to the program- ming section for details. erase all (eral): the eral instruction will simultaneously program all registers in the memory array to the logical 1 state. write all (wral): the wral instruction will simultaneously program all registers with the data pattern specified in the instruction. timing diagrams for the nm93c46a
8 www.fairchildsemi.com nm93c46a rev. d.2 nm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) cs sk di 1 . . . org = v cc , 4 x's org = v ss , 5 x's t cs ewen do = tri-state 0011 xx cs sk di 1 . . . org = v cc , 4 x's org = v ss , 5 x's t cs ewds do = tri-state 0000 xx timing diagrams for the nm93c46a (continued) ds011042-6 ds011042-7 1 cs sk di do 10 0d n . . . d 0 a n . . . a 0 t cs read ds011042-5 key for timing diagrams organization of address and data fields for nm93c46a org pin organization a n d n v cc or nc 64 x 16 a5 d15 v ss 128 x 8 a6 d7 erase 111 a n . . . a 0 cs busy ready tri-state tri-state standby do sk di t cs t wp ds011042-8
9 www.fairchildsemi.com nm93c46a rev. d.2 nm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) eral 00 110xx . . . cs busy ready standby do sk di t wp t cs org = v cc , 4 x's org = v ss , 5 x's ready status signal resets to tri-state after clocking in one sk cycle with di = 1 wral 000 11xxd n d 0 . . . . . . cs busy ready standby do sk di t wp t cs org = v cc , 4 x's org = v ss , 5 x's ready status signal resets to tri-state after clocking in one sk cycle with di = 1 timing diagrams for the nm93c46a (continued) ds011042-10 ds011042-11 write 1 . . . . . . t cs 0 1 a n a 0 d 0 d n cs busy ready do sk di t wp ds011042-9
10 www.fairchildsemi.com nm93c46a rev. d.2 nm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ. physical dimensions inches (millimeters) unless otherwise noted molded small outline package (m8) package number m08a
11 www.fairchildsemi.com nm93c46a rev. d.2 nm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.50) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. max 0.0433 (1.1) 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 [0.50 - 0.70] 0.0075 - 0.0098 [0.19 - 0.25] seating plane gage plane see detail a land pattern recommendation detail a typ. scale: 40x physical dimensions inches (millimeters) unless otherwise noted 8-pin molded tssop, jedec (mt8) package number mtc08
12 www.fairchildsemi.com nm93c46a rev. d.2 nm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) physical dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident molded dual-in-line package (n) package number n08e life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm93c56 rev. c.2 nm93c56 2k-bit serial cmos eeprom (microwire? bus interface) march 1999 ? 1999 fairchild semiconductor corporation nm93c56 2k-bit serial cmos eeprom (microwire? bus interface) general description the nm93c56 devices are 2048 bits of cmos non-volatile electrically erasable memory divided into 128 16-bit registers. they are fabricated using fairchild semiconductor's floating-gate cmos process for high reliability, high endurance and low power consumption. these memory devices are available in an 8-pin soic or 8-pin tssop package for small space considerations. the serial interface that operates this eeprom is microwire compatible for simple interface to standard microcontrollers and microprocessors. there are 7 instructions which control this device: read, write enable, erase, erase all, write, write all, and write disable. the ready/busy status is available on the do pin to indicate the completion of a programming cycle. block diagram features n device status during programming mode n typical active current of 200 m a 10 m a standby current typical 1 m a standby current typical (l) 0.1 m a standby current typical (lz) n no erase required before write n reliable cmos floating gate technology n 2.7v to 5.5v operation in all modes n microwire compatible serial l/o n self-timed programming cycle n 40 years data retention n endurance: 1,000,000 data changes n packages available: 8-pin so, 8-pin dip, 8-pin tssop ds500081-1 instruction decoder control logic, and clock generators high voltage generator and program timer instruction register address register eeprom array read/write amps data in/out register 16 bits decoder 1 of 16 16 16 data out buffer v pp v cc cs sk di do v ss
2 www.fairchildsemi.com nm93c56 rev. c.2 nm93c56 2k-bit serial cmos eeprom (microwire? bus interface) connection diagrams v cc nc gnd cs sk di do 1 2 3 4 8 7 6 5 nc ds500081-2 dual-in-line package (n), 8-pin so (m8) and 8-pin tssop (mt8) top view see package number n08e, m08a and mtc08 pin names cs chip select sk serial data clock di serial data input do serial data output gnd ground v cc power supply ordering information nm 93 c xx t lz e xx letter description package n 8-pin dip m8 8-pin so8 mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current blank normal pin out t rotated die pin out density 56 2k c cmos cs data protect and sequential read interface 93 microwire nm fairchild non-volatile memory nc do di nc v cc cs sk 1 2 3 4 8 7 6 5 gnd ds500081-12 rotated die (93c56t)
3 www.fairchildsemi.com nm93c56 rev. c.2 nm93c56 2k-bit serial cmos eeprom (microwire? bus interface) absolute maximum ratings (note 1) ambient storage temperature C65 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v standard v cc (4.5v to 5.5v) dc and ac electrical characteristics symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 1mhz 1 ma i ccs standby current cs = v il 50 m a i il input leakage v in = 0v to v cc 1 m a i ol output leakage (note 2) v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v ol1 output low voltage i ol = 2.1ma 0.4 v v oh1 output high voltage i oh = -400 m a 2.4 v v ol2 output low voltage i ol = 10 m a 0.2 v v oh2 output high voltage i oh = -10 m av cc -0.2 v f sk sk clock frequency (note 3) 0 1 mhz t skh sk high time nm93c56 250 ns nm93c56e/v 300 t skl sk low time 250 ns t sks sk setup time sk must be at v il for 50 ns t sks before cs goes high t cs minimum cs (note 4) 250 ns low time t css cs setup time 50 ns t dh do hold time 70 ns t dis di setup time nm93c56 100 ns nm93c56e/v 200 t csh cs hold time 0 ns t dih di hold time 20 ns t pd1 output delay to "1" 500 ns t pd0 output delay to "0" 500 ns t sv cs to status valid 500 ns t df cs to do in cs = v il 100 ns tri-state t wp write cycle time 10 ms operating range ambient operating temperature nm93c56 0 c to +70 c nm93c56e -40 c to +85 c nm93c56v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v
4 www.fairchildsemi.com nm93c56 rev. c.2 nm93c56 2k-bit serial cmos eeprom (microwire? bus interface) absolute maximum ratings (note 1) ambient storage temperature C65 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v low v cc (2.7v to 4.5v) dc and ac electrical characteristics symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 250khz 1ma i ccs standby current cs = v il l 10 m a lz 1 m a i il input leakage v in = 0v to v cc 1 m a i ol output leakage (note 2) v il input low voltage -0.1 0.15 v cc v v ih input high voltage 0.8 v cc v cc +1 v ol output low voltage i ol = 10 m a 0.1 v cc v v oh output high voltage i oh = -10 m a 0.9 v cc v f sk sk clock frequency (note 3) 0 250 khz t skh sk high time 1 m s t skl sk low time 1 m s t sks sk setup time sk must be at v il for 0.2 m s t sks before cs goes high t cs minimum cs (note 4) 1 m s low time t css cs setup time 0.2 m s t dh do hold time 70 ns t dis di setup time 0.4 m s t csh cs hold time 0 ns t dih di hold time 0.4 m s t pd1 output delay to "1" 2 m s t pd0 output delay to "0" 2 m s t sv cs to status valid 1 m s t df cs to do in cs = v il 0.4 m s tri-state t wp write cycle time 15 ms operating range ambient operating temperature nm93c56l/lz 0 c to +70 c nm93c56le/lze -40 c to +85 c nm93c56lv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 4.5v capacitance t a = 25 c, f = 1 mhz (note 5) symbol test typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20na range. note 3 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 4 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagram on the following page.) note 5 : this parameter is periodically sampled and not 100% tested. ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v .03v/1.8v 1.0v 0.8v/1.5v 10 m a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v -2.1ma/0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf)
5 www.fairchildsemi.com nm93c56 rev. c.2 nm93c56 2k-bit serial cmos eeprom (microwire? bus interface) functional description the nm93c56 device has 7 instructions as described below. note that the msb of any instruction is a 1 and is viewed as a start bit in the interface sequence. the next 10 bits carry the op code and the 8-bit address for register selection. read (read): the read instruction outputs serial data on the d0 pin. after a read instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a 16-bit serial-out shift register. a dummy bit (logical 0) precedes the 16-bit data output string. output data changes are initiated by a low to high transition of the sk clock. write enable (wen): when v cc is applied to the part, it 'powers-up' in the write disable (wds) state. therefore, all programming modes must be pre- ceded by a write enable (wen) instruction. once a write enable instruction is executed, programming remains enabled until awrite disable (wds) instruction is executed or v cc is removed from the part. erase (erase): the erase instruction will program all bits in the specified register to the logical 1 state. cs is brought low following the loading of the last address bit. this falling edge of the cs pin initiates the self-timed programming cycle. the do pin indicates the ready/busy status of the chip if cs is brought high after a minimum time of t cs . do = logical 0 indicates that the register, at the address specified in the instruction, has been erased, and the part is ready for another instruction. write (write): the write instruction is followed by the address and 16 bits of data to be written into the specified address. after the last bit of data is put in the data-in (di) pin, cs must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. the d0 pin indicates the ready/ busy status of the chip if cs is brought high after a minimum of t cs . d0 = logical 1 indicates that the register at the address specified in the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction. erase all (eral): the eral instruction will simultaneously program all registers in the memory array and set each bit to the logical 1 state. the erase all cycle is identical to the erase cycle except for the different op- code. as in the erase mode, the do pin indicates the ready/ busy status of the chip if cs is brought high after the t cs interval. write all (wrall): the wrall instruction will simultaneously program all registers with the data pattern specified in the instruction. as in the write mode, the do pin indicates the ready/busy status of the chip if cs is brought high after the t cs interval. write disable (wds): to protect against accidental data disturb, the wds instruction disables all programming modes and should follow all program- ming operations. execution of a read instruction is independent of both the wen and wds instructions. note: the fairchild cmos eeproms do not require an "erase" or "erase all" operation prior to the "write" and "write all" instructions. the "erase" and "erase all" instructions are included to maintain compatibility with earlier technology eeproms. instruction set for the nm93c56 instruction sb op. code address data comments read 1 10 a7-a0 reads data stored in memory, at specified address. wen 1 00 11xxxxxx write enable must precede all programming modes. erase 1 11 a7-a0 erase selected register. write 1 01 a7-a0 d15-d0 writes selected register. eral 1 00 10xxxxxx erases all registers. wrall 1 00 01xxxxxx d15-d0 writes all registers. wds 1 00 00xxxxxx disables all programming instructions. note: a7 is "don't care" bit, but must be included in the address string.
6 www.fairchildsemi.com nm93c56 rev. c.2 nm93c56 2k-bit serial cmos eeprom (microwire? bus interface) 1 cs sk di do 10 0 d15 . . . d0 a7 . . . a0 t cs read 1 cs sk di 00 1 1 . . . xx t cs wen 1 cs sk di 00 0 0 . . . xx t cs wds ds500081-5 ds500081-6 ds500081-7 status valid synchronous data timing v ih v il cs v ih v il sk v ih v il di v oh v ol do (read) v oh v ol do (program) t css t sks t dis t dih t pd0 t pd1 t dh t df t df t dh t sv t skh t skl t csh ds500081-4 timing diagrams synchronous data timing read wen wds
7 www.fairchildsemi.com nm93c56 rev. c.2 nm93c56 2k-bit serial cmos eeprom (microwire? bus interface) 1 cs sk di do 01 busy ready a7 . . . a0 d15 d0 t cs write t wp 1 cs sk di do 0001 busy ready don't care (6 bits) . . . d15 d0 t cs wrall t wp 111 cs sk di do a7 a6 busy ready standby tri-state tri-state a5 . . . a0 erase t wp t cs ds500081-8 ds500081-9 ds500081-10 100 cs sk di do 10 busy ready standby check status don't care bits (6 bits) tri-state tri-state eral t wp t cs ds500081-11 eral erase wrall timing diagrams (continued) write
8 www.fairchildsemi.com nm93c56 rev. c.2 nm93c56 2k-bit serial cmos eeprom (microwire? bus interface) physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x molded small out-line package (m8) package number m08a 8-pin molded tssop, jedec (mt8) package number mtc08
9 www.fairchildsemi.com nm93c56 rev. c.2 nm93c56 2k-bit serial cmos eeprom (microwire? bus interface) physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm93c56a rev. d.2 nm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) nm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) general description the nm93c56a is 2,048 bits of cmos non-volatile, electrically erasable memory user organized as either 128 16-bit registers or 256 8-bit registers. the user organization is determined by the status of the org input. the memory device is fabricated using fairchild semiconductors floating gate cmos process for high reliability, high endurance and low power consumption. the nm93c56a is available in both 8-pin so and tssop packages for space considerations. the eeprom is microwire compatible for simple interfacing to a wide variety of microcontrollers and microprocessors. there are 7 instructions that operate the nm93c56a: read, erase/write enable, erase, write, erase/write disable, write all, and erase all. the nm93c56a defaults to the 128 x 16 configuration if the org pin (pin 6) is left floating, as it is internally pulled up to v cc . march 1999 features n 2.7v to 5.5v operation in all modes n typical active current 200 m a 10 m a standby current typical 1 m a standby current typical (l) 0.1 m a standby current typical (lz) n self-timed programming cycle n device status indication during programming mode n no erase required before write n reliable cmos floating gate technology n microwire compatible serial i/o n 40 years data retention n endurance: 1,000,000 data changes n packages available: 8-pin tssop, 8-pin so, 8-pin dip ds012509-1 block diagram instruction decoder control logic, and clock generators high voltage generator and program timer instruction register address register eeprom array 2048 bits (128x16) or (256x8) read/write amps data in/out register 16 (or 8) bits decoder 1 of 128 (or 256) data out buffer v pp v cc cs sk di do gnd org ? 1999 fairchild semiconductor corporation
2 www.fairchildsemi.com nm93c56a rev. d.2 nm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) connection diagram dual-in-line package (n) 8-pin so package (m8) and 8-pin tssop package (mt8) v cc org v ss cs sk di do 1 2 3 4 8 7 6 5 nc top view see package number n08e, m08a and mtc08 nm93c56a ds012509-2 pin names pin description cs chip select sk serial data clock di serial data input do serial data output v ss ground org memory organization select nc no connect v cc positive power supply ordering information nm 93 c xx a t lz e xx letter description package n 8-pin dip m8 8-pin so8 mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current blank normal pin out t rotated die pin out a x8 or x16 configuration density 56 2k c cmos cs data protect and sequential read interface 93 microwire nm fairchild non-volatile memory rotated die (93c56at) org do di nc v cc cs sk 1 2 3 4 8 7 6 5 v ss nm93c56a
3 www.fairchildsemi.com nm93c56a rev. d.2 nm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages with respect to ground v cc +1 to -0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v operating conditions ambient operating temperature nm93c56a 0 c to +70 c nm93c56ae -40 c to +85 c nm93c56av -40 c to +125 c power supply (v cc ) range 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v symbol parameter part number conditions min max units i cca operating current cs = v ih sk = 1 mhz 1 ma i ccs standby current cs = 0v org = v cc or nc 50 m a i il input leakage v in = 0v to v cc (note 2) -1 1 m a i ilo input leakage org tied to v cc -1 1 m a org pin org tied to v ss (note 3) -2.5 2.5 i ol output leakage v in = 0v to v cc -1 1 m a v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v v ol1 output low voltage i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = -400 m a 2.4 v v ol2 output low voltage i ol = 10 m a 0.2 v v oh2 output high voltage i ol = -10 m av cc -0.2 v f sk sk clock frequency (note 4) 0 1 mhz t skh sk high time nm93c56a 250 ns nm93c56ae 300 t skl sk low time 250 ns t sks sk setup time sk must be at v il for 50 ns t sks before cs goes high t cs minimum cs (note 5) 250 ns low time t css cs set-up time 50 ns t dh d0 hold time 70 ns t dis di set-up time nm93c56a 100 ns nm93c56ae/v 200 t csh cs hold time 0 ns t dih di hold time 20 ns t pd1 output delay to 1 500 ns t pd0 output delay to 0 500 ns t sv cs to status valid 500 ns t df cs to do in 100 ns tri-state ? t wp write cycle time 10 ms
4 www.fairchildsemi.com nm93c56a rev. d.2 nm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v .03v/1.8v 1.0v 0.8v/1.5v 10 m a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v -2.1ma/0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf) absolute maximum ratings (note 1) ambient storage temperature C65 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v low v cc (2.7v to 4.5v) dc and ac electrical characteristics symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 250khz 1ma i ccs standby current cs = v il l 10 m a lz 1 m a i il input leakage v in = 0v to v cc (note 2) 1 m a i ilo input leakage org tied to v cc -1 1 m a org pin org tied to v ss (note 3) -2.5 2.5 i ol output leakage v in = 0v to v cc 1 m a v il input low voltage -0.1 0.15 v cc v v ih input high voltage 0.8 v cc v cc +1 v ol output low voltage i ol = 10 m a 0.1 v cc v v oh output high voltage i oh = -10 m a 0.9 v cc v f sk sk clock frequency (note 4) 0 250 khz t skh sk high time 1 m s t skl sk low time 1 m s t sks sk setup time sk must be at v il for 0.2 m s t sks before cs goes high t cs minimum cs (note 5) 1 m s low time t css cs setup time 0.2 m s t dh do hold time 70 ns t dis di setup time 0.4 m s t csh cs hold time 0 ns t dih di hold time 0.4 m s t pd1 output delay to "1" 2 m s t pd0 output delay to "0" 2 m s t sv cs to status valid 1 m s t df cs to do in cs = v il 0.4 m s tri-state t wp write cycle time 15 ms operating range ambient operating temperature nm93c56al/lz 0 c to +70 c nm93c56ale/lze -40 c to +85 c nm93c56a lv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 4.5v capacitance t a = 25 c, f = 1 mhz symbol test typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20 na range. note 3 : the org pin may draw > 1 m a when in the x8 mode ude to an internal pull-up transistor. note 4 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 5 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagrams in the following pages.)
5 www.fairchildsemi.com nm93c56a rev. d.2 nm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) microwire i/o pin description chip select (cs): this pin enables and disables the microwire device and performs 3 general functions: 1. when in the low state, the microwire device is disabled and the output tri-stated (high impedance). if this pin is brought high (rising edge active), all internal registers are reset and the device is enabled, allowing microwire communication via di/do pins. to restate, the cs pin must be held high during all device communication and opcode functions. if the cs pin is brought low, all functions will be disabled and reset when cs is brought high again. the exception to this is when a programming cycle is initiated (see 2 and 3). again, all activity on the cs, di and do pins is ignored until cs is brought high. 2. after entering all required opcode and address data, bringing cs low initiates the (asynchronous) programming cycle. 3. when programming is in progress, the data-out pin will display the programming status as either busy (do low) or ready (do high) when cs is brought high. (again, the output will be tri-stated when cs is low.) to restate, during programming, the cs pin may be brought high and low any number of times to view the programming status without affect the programming operation. once programming is completed (output in ready state), the output is 'cleared' (returned to normal tri-state condition) by clocking in a start bit. after the start bit is clocked in, the output will return to a tri-stated condition. when clocked in, this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. serial clock (sk): this pin is the clock input (rising edge active) for clocking in all opcodes and data on the di pin and clocking out all data on the do pin.however, this pin has no effect on the asynchronous program- ming cycle (see the cs pin section) as the busy/ready status is a function of the cs pin only. data-in (di): all serial communication into the device is performed using this input pin (rising edge active). in order to avoid false start bits, or related issues, it is advised to keep the di pin in the low state unless actually clocking in data bits (start bit, opcode, address or incoming data bits to be programmed). please note that the first '1' clocked into the device (after cs is brought high) is seen as a start bit and the beginning of a serial command string, so caution must be observed when bringing cs high. data-out (do): all serial communication out of the device (read opcode) is performed using this output pin (rising edge active) as well as indicating the ready/busy status duting the asynchronous programming cycle. note that, during read operations, the output data is clocked out after the last address bit (a0) is clocked in. if a 3-wire application is required (where di and do are tied together), sections in an-758, or related application notes, must be followed for correct operation. organization (org): this pin controls the device architecture (8-bit data word vs. 16-bit data word). if the org pin is brought to v cc , the device is configured wiht a 16-bit data word and if the org pin is brought to v ss (ground), the device is configured with an 8-bit data word (refer to other sections for details of both configurations). if the org pin is left floating, the device will default to a 16-bit data word. instruction set for the nm93c56a org memory pin configuration # of address bits logic 0 256 x 8 9 bits 1 128 x 16 8 bits note: the leading (msb) bit is a "don't care," but must be included in the address string.
6 www.fairchildsemi.com nm93c56a rev. d.2 nm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) 128 by 16-bit organization (nm93c56a when org = v cc or nc) instruction sb op-code address data comments 2 bits 8 bits 16 bits read 1 10 a7Ca0 read data stored in selected registers. ewen 1 00 11xxxxxx enables programming modes. ewds 1 00 00xxxxxx disables all programming modes. erase 1 11 a7Ca0 erase selected register. write 1 01 a7Ca0 d15Cd0 writes data pattern d15Cd0 into selected register. eral 1 00 10xxxxxx erases all registers. wral 1 00 01xxxxxx d15Cd0 writes data pattern d15Cd0 into all registers. note: the a7 bit is a "don't care" bit, but must be entered in the address string. 256 by 8-bit organization (nm93c56a when org = gnd) instruction sb op-code address data comments 2 bits 9 bits 8 bits read 1 10 a8Ca0 read data stored in selected registers. ewen 1 00 11xxxxxxx enables programming modes. ewds 1 00 00xxxxxxx disables all programming modes. erase 1 11 a8Ca0 erase selected register. write 1 01 a8Ca0 d7Cd0 writes data pattern d7Cd0 into selected registers. eral 1 00 10xxxxxxx erases all registers. wral 1 00 01xxxxxxx d7Cd0 writes data pattern d7Cd0 into all registers. note: the a8 bit is a "don't care" bit, but must be entered in the address string. functional description programming: 1. programming is initiated by clocking in the start bit, opcode bits, address bits and the 8/16 data bits (refer to the org pin section). 2. programming is started by bringing the cs pin low. once the programming cycle is started, it cannot be stopped. (bringing v cc low will stop any programming, but will also result in data corruption.) 3. the status of the programming cycle (busy or ready) is observed by bringing the cs pin high and observing the output state. if the output is low, the device is still program- ming (busy). if the output is high, the programming cycle has been completed and the device is ready for the next operation. note that the output will be tri-stated each time cs is brought low and the r/b status will be shown each time cs is brought high. 4. after programming, the ready state (output high) can be reset and the output tri-stated by clocking in a single start bit. this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. in any case, clocking in a '1' bit will tri-state the output. read (read) the read instruction outputs serial data on the do pin. after a read instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a serial-out shift register. a dummy bit (logical 0) precedes the serial data output string. output data changes are initiated by a low to high transition of sk after the last address bit (a0) is clocked in. erase/write enable (ewen) when v cc is applied to the part, it powers up in the erase/write disable (ewds) state. therefore, all programming modes must be preceded by an erase/write enable (ewen) instruction. once an erase/write enable instruction is executed, programming remains enabled until an erase/write disable (ewds) instruction is executed or v cc is removed from the part.
7 www.fairchildsemi.com nm93c56a rev. d.2 nm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) functional description (continued) erase/write disable (ewds): to protect against accidental data overwrites, the erase/write disable (ewds) instruction disables all programming modes and should follow all programming operations. execution of a read instruction is independent of both the ewen and ewds instruc- tions. erase (erase): the erase instruction will program all bits in the specified register to the logical 1 state. please refer to the programming section for details. write (write): the write instruction is followed by 16 bits of data (or 8 bits of data when using the nm93c56a in the x8 organization) to be written into the specified address. please refer to the program- ming section for details. erase all (eral): the eral instruction will simultaneously program all registers in the memory array to the logical 1 state. write all (wral): the wral instruction will simultaneously program all registers with the data pattern specified in the instruction. status valid synchronous data timing v ih v il cs v ih v il sk v ih v il di v oh v ol do (read) v oh v ol do (program) t css t sks t dis t dih t pd0 t pd1 t dh t df t df t dh t sv t skh t skl t csh ds012509-4 timing diagrams for the nm93c56a
8 www.fairchildsemi.com nm93c56a rev. d.2 nm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) cs sk di 1 . . . org = v cc , 6 x's org = v ss , 7 x's t cs ewen do = tri-state 0011 xx cs sk di 1 . . . org = v cc , 6 x's org = v ss , 7 x's t cs ewds do = tri-state 0000 xx erase 111 a n . . . a 0 cs busy ready tri-state tri-state standby do sk di t cs t wp ds012509-6 ds012509-7 ds012509-8 timing diagrams for the nm93c56a (continued) 1 cs sk di do 10 0d n . . . d 0 a n . . . a 0 t cs read ds012509-5 key for timing diagrams organization of address and data fields for nm93c56a org pin organization a n d n v cc or nc 128 x 16 a7 d15 v ss 256 x 8 a8 d7 note: the msb is "don't care."
9 www.fairchildsemi.com nm93c56a rev. d.2 nm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) eral 1 001 0 cs busy ready tri-state tri-state standby check status do sk di t wp t cs wral 1 . . . . . . 000 1 x xd 0 d n cs busy ready do sk di t wp ds012509-10 ds012509-11 timing diagrams for the nm93c56a (continued) write 1 . . . . . . t cs 0 1 a n a 0 d 0 d n cs busy ready do sk di t wp ds012509-9
10 www.fairchildsemi.com nm93c56a rev. d.2 nm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ. physical dimensions inches (millimeters) unless otherwise noted molded small outline package (m8) package number m08a
11 www.fairchildsemi.com nm93c56a rev. d.2 nm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.50) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. max 0.0433 (1.1) 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 [0.50 - 0.70] 0.0075 - 0.0098 [0.19 - 0.25] seating plane gage plane see detail a land pattern recommendation detail a typ. scale: 40x physical dimensions inches (millimeters) unless otherwise noted 8-pin molded tssop, jedec (mt8) package number mtc08
12 www.fairchildsemi.com nm93c56a rev. d.2 nm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) physical dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident molded dual-in-line package (n) package number n08e life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm93c66 rev. c.2 nm93c66 4k-bit serial cmos eeprom (microwire? bus interface) march 1999 ? 1999 fairchild semiconductor corporation nm93c66 4k-bit serial cmos eeprom (microwire? bus interface) general description the nm93c66 devices are 4096 bits of cmos non-volatile electrically erasable memory divided into 256 16-bit registers. they are fabricated using fairchild semiconductor's floating-gate cmos process for high reliability, high endurance and low power consumption. these memory devices are available in an 8-pin soic or 8-pin tssop package for small space considerations. the serial interface that operates this eeprom is microwire compatible for simple interface to standard microcontrollers and microprocessors. there are 7 instructions which control this device: read, write enable, erase, erase all, write, write all, and write disable. the ready/busy status is available on the do pin to indicate the completion of a programming cycle. block diagram features n device status during programming mode n typical active current of 200 m a 10 m a standby current typical 1 m a standby current typical (l) 0.1 m a standby current typical (lz) n no erase required before write n reliable cmos floating gate technology n 2.7v to 5.5v operation in all modes n microwire compatible serial l/o n self-timed programming cycle n 40 years data retention n endurance: 1,000,000 data changes n packages available: 8-pin so, 8-pin dip, 8-pin tssop ds500082-1 instruction decoder control logic, and clock generators high voltage generator and program timer instruction register address register eeprom array read/write amps data in/out register 16 bits decoder 1 of 16 16 16 data out buffer v pp v cc cs sk di do v ss
2 www.fairchildsemi.com nm93c66 rev. c.2 nm93c66 4k-bit serial cmos eeprom (microwire? bus interface) connection diagrams v cc nc gnd cs sk di do 1 2 3 4 8 7 6 5 nc ds500082-2 dual-in-line package (n), 8-pin so (m8) and 8-pin tssop (mt8) top view see package number n08e, m08a and mtc08 pin names cs chip select sk serial data clock di serial data input do serial data output gnd ground v cc power supply ordering information nm 93 c xx lz e xx letter description package n 8-pin dip m8 8-pin so8 mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current density 66 4k c cmos interface 93 microwire nm fairchild non-volatile memory
3 www.fairchildsemi.com nm93c66 rev. c.2 nm93c66 4k-bit serial cmos eeprom (microwire? bus interface) absolute maximum ratings (note 1) ambient storage temperature C65 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v standard v cc (4.5v to 5.5v) dc and ac electrical characteristics symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 1mhz 1 ma i ccs standby current cs = v il 50 m a i il input leakage v in = 0v to v cc 1 m a i ol output leakage (note 2) v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v ol1 output low voltage i ol = 2.1ma 0.4 v v oh1 output high voltage i oh = -400 m a 2.4 v v ol2 output low voltage i ol = 10 m a 0.2 v v oh2 output high voltage i oh = -10 m av cc -0.2 v f sk sk clock frequency (note 3) 0 1 mhz t skh sk high time nm93c66 250 ns nm93c66e/v 300 t skl sk low time 250 ns t sks sk setup time sk must be at v il for 50 ns t sks before cs goes high t cs minimum cs (note 4) 250 ns low time t css cs setup time 50 ns t dh do hold time 70 ns t dis di setup time nm93c66 100 ns nm93c66e/v 200 t csh cs hold time 0 ns t dih di hold time 20 ns t pd1 output delay to "1" 500 ns t pd0 output delay to "0" 500 ns t sv cs to status valid 500 ns t df cs to do in cs = v il 100 ns tri-state t wp write cycle time 10 ms operating range ambient operating temperature nm93c66 0 c to +70 c nm93c66e -40 c to +85 c nm93c66v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v
4 www.fairchildsemi.com nm93c66 rev. c.2 nm93c66 4k-bit serial cmos eeprom (microwire? bus interface) ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v .03v/1.8v 1.0v 0.8v/1.5v 10 m a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v -2.1ma/0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf) absolute maximum ratings (note 1) ambient storage temperature C65 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v low v cc (2.7v to 4.5v) dc and ac electrical characteristics symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 250khz 1ma i ccs standby current cs = v il l 10 m a lz 1 m a i il input leakage v in = 0v to v cc 1 m a i ol output leakage v il input low voltage -0.1 0.15 v cc v v ih input high voltage 0.8 v cc v cc +1 v ol output low voltage i ol = 10 m a 0.1 v cc v v oh output high voltage i oh = -10 m a 0.9 v cc v f sk sk clock frequency (note 3) 0 250 khz t skh sk high time 1 m s t skl sk low time 1 m s t sks sk setup time sk must be at v il for 0.2 m s t sks before cs goes high t cs minimum cs (note 4) 1 m s low time t css cs setup time 0.2 m s t dh do hold time 70 ns t dis di setup time 0.4 m s t csh cs hold time 0 ns t dih di hold time 0.4 m s t pd1 output delay to "1" 2 m s t pd0 output delay to "0" 2 m s t sv cs to status valid 1 m s t df cs to do in cs = v il 0.4 m s tri-state t wp write cycle time 15 ms operating range ambient operating temperature nm93c66l/lz 0 c to +70 c nm93c66le/lze -40 c to +85 c nm93c66lv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 4.5v capacitance t a = 25 c, f = 1 mhz (note 5) symbol test typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20na range. note 3 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 4 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagram on the following page.) note 5 : this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm93c66 rev. c.2 nm93c66 4k-bit serial cmos eeprom (microwire? bus interface) functional description the nm93c66 device has 7 instructions as described below. note that the msb of any instruction is a 1 and is viewed as a start bit in the interface sequence. the next 10 bits carry the op code and the 8-bit address for register selection. read (read): the read instruction outputs serial data on the d0 pin. after a read instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a 16-bit serial-out shift register. a dummy bit (logical 0) precedes the 16-bit data output string. output data changes are initiated by a low to high transition of the sk clock. write enable (wen): when v cc is applied to the part, it 'powers-up' in the write disable (wds) state. therefore, all programming modes must be pre- ceded by a write enable (wen) instruction. once a write enable instruction is executed, programming remains enabled until awrite disable (wds) instruction is executed or v cc is removed from the part. erase (erase): the erase instruction will program all bits in the specified register to the logical 1 state. cs is brought low following the loading of the last address bit. this falling edge of the cs pin initiates the self-timed programming cycle. the do pin indicates the ready/busy status of the chip if cs is brought high after a minimum time of t cs . do = logical 0 indicates that the register, at the address specified in the instruction, has been erased, and the part is ready for another instruction. write (write): the write instruction is followed by the address and 16 bits of data to be written into the specified address. after the last bit of data is put in the data-in (di) pin, cs must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. the d0 pin indicates the ready/ busy status of the chip if cs is brought high after a minimum of t cs . d0 = logical 1 indicates that the register at the address specified in the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction. erase all (eral): the eral instruction will simultaneously program all registers in the memory array and set each bit to the logical 1 state. the erase all cycle is identical to the erase cycle except for the different op- code. as in the erase mode, the do pin indicates the ready/ busy status of the chip if cs is brought high after the t cs interval. write all (wrall): the wrall instruction will simultaneously program all registers with the data pattern specified in the instruction. as in the write mode, the do pin indicates the ready/busy status of the chip if cs is brought high after the t cs interval. write disable (wds): to protect against accidental data disturb, the wds instruction disables all programming modes and should follow all program- ming operations. execution of a read instruction is independent of both the wen and wds instructions. note: the fairchild cmos eeproms do not require an "erase" or "erase all" operation prior to the "write" and "write all" instructions. the "erase" and "erase all" instructions are included to maintain compatibility with earlier technology eeproms. instruction set for the nm93c66 instruction sb op. code address data comments read 1 10 a7-a0 reads data stored in memory, at specified address. wen 1 00 11xxxxxx write enable must precede all programming modes. erase 1 11 a7-a0 erase selected register. write 1 01 a7-a0 d15-d0 writes selected register. eral 1 00 10xxxxxx erases all registers. wrall 1 00 01xxxxxx d15-d0 writes all registers. wds 1 00 00xxxxxx disables all programming instructions.
6 www.fairchildsemi.com nm93c66 rev. c.2 nm93c66 4k-bit serial cmos eeprom (microwire? bus interface) 1 cs sk di do 10 0 d15 . . . d0 a7 . . . a0 t cs read 1 cs sk di 00 1 1 . . . xx t cs wen 1 cs sk di 00 0 0 . . . xx t cs wds ds500082-5 ds500082-6 ds500082-7 status valid synchronous data timing v ih v il cs v ih v il sk v ih v il di v oh v ol do (read) v oh v ol do (program) t css t sks t dis t dih t pd0 t pd1 t dh t df t df t dh t sv t skh t skl t csh ds500082-4 timing diagrams synchronous data timing read wen wds
7 www.fairchildsemi.com nm93c66 rev. c.2 nm93c66 4k-bit serial cmos eeprom (microwire? bus interface) 1 cs sk di do 01 busy ready a7 . . . a0 d15 d0 t cs write t wp 1 cs sk di do 0001 busy ready don't care (6 bits) . . . d15 d0 t cs wrall t wp 111 cs sk di do a7 a6 busy ready standby tri-state tri-state a5 . . . a0 erase t wp t cs ds500082-8 ds500082-9 ds500082-10 100 cs sk di do 10 busy ready standby check status don't care bits (6 bits) tri-state tri-state eral t wp t cs ds500082-11 eral erase wrall timing diagrams (continued) write
8 www.fairchildsemi.com nm93c66 rev. c.2 nm93c66 4k-bit serial cmos eeprom (microwire? bus interface) physical dimensions inches (millimeters) unless otherwise noted molded small out-line package (m8) package number m08a 8-pin molded tssop, jedec (mt8) package number mtc08 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
9 www.fairchildsemi.com nm93c66 rev. c.2 nm93c66 4k-bit serial cmos eeprom (microwire? bus interface) physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm93c66a rev. d.2 nm93c66a 4k-bit serial cmos eeprom (microwire? bus interface) march 1999 ? 1999 fairchild semiconductor corporation nm93c66a 4k-bit serial cmos eeprom (microwire? bus interface) general description the nm93c66a is 4,096 bits of cmos non-volatile, electrically erasable memory available user organized as either 256 16-bit registers or 512 8-bit registers. the user organization is deter- mined by the status of the org input. the memory device is fabricated using fairchild semiconductors floating gate cmos process for high reliability, high endurance and low power con- sumption. the nm93c66a is available in both 8-pin so and tssop packages for space considerations. the eeprom is microwire compatible for simple interfacing to a wide variety of microcontrollers and microprocessors. there are 7 instructions that operate the nm93c66a: read, erase/write enable, erase, write, erase/write disable, write all, and erase all. the nm93c66a defaults to the 256 x 16 configuration if the org pin (pin 6) is left floating, as it is internally pulled up to v cc . block diagram features n 2.7v to 5.5v operation in all modes n typical active current of 200 m a 10 m a standby current typical 1 m a standby current typical (l) 0.1 m a standby current typical (lz) n self-timed programming cycle n device status indication during programming mode n no erase required before write n reliable cmos floating gate technology n microwire compatible serial i/o n 40 years data retention n endurance: 1,000,000 data changes n packages available: 8-pin tssop, 8-pin so, 8-pin dip ds012510-1 instruction decoder control logic, and clock generators high voltage generator and program timer instruction register address register eeprom array 2048 bits (256 x16) or (512 x8) read/write amps data in/out register 16 (or 8) bits decoder 1 of 256 (or 512) data out buffer v pp v cc cs sk di do gnd org
2 www.fairchildsemi.com nm93c66a rev. d.2 nm93c66a 4k-bit serial cmos eeprom (microwire? bus interface) v cc org v ss cs sk di do 1 2 3 4 8 7 6 5 nc connection diagram dual-in-line package (n) 8-pin so package (m8) and 8-pin tssop package (mt8) top view see package number n08e, m08a and mtc08 pin names pin description cs chip select sk serial data clock di serial data input do serial data output v ss ground org memory organization select nc no connect v cc positive power supply ordering information nm 93 c xx a lz e xx letter description package n 8-pin dip m8 8-pin so8 mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current a x8 or x16 configuration density 66 4k c cmos interface 93 microwire nm fairchild non-volatile memory ds012510-2 nm93c66a
3 www.fairchildsemi.com nm93c66a rev. d.2 nm93c66a 4k-bit serial cmos eeprom (microwire? bus interface) absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages with respect to ground v cc +1 to -0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v operating conditions ambient operating temperature nm93c66a 0 c to +70 c nm93c66ae -40 c to +85 c nm93c66av -40 c to +125 c power supply (v cc ) range 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v symbol parameter part number conditions min max units i cca operating current cs = v ih ,sk=1 mhz 1 ma i ccs standby current cs = 0v org = v cc or nc 50 m a i il input leakage v in = 0v to v cc (note 2) -1 1 m a i ilo input leakage org tied to v cc -1 1 m a org pin org tied to v ss -2.5 2.5 (note 3) i ol output leakage v in = 0v to v cc -1 1 m a v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v v ol1 output low voltage i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = -400 m a 2.4 v v ol2 output low voltage i ol = 10 m a 0.2 v v oh2 output high voltage i ol = -10 m av cc - 0.2 v f sk sk clock frequency (note 4) 0 1 mhz t skh sk high time nm93c66a 250 ns nm93c66ae 300 t skl sk low time 250 ns t sks sk setup time sk must be at v il for 50 ns t sks before cs goes high t cs minimum cs (note 5) 250 ns low time t css cs set-up time 50 ns t dh do hold time 70 ns t dis di set-up time nm93c66a 100 ns nm93c66ae/v 200 t csh cs hold time 0 ns t dih di hold time 20 ns t pd1 output delay to 1 500 ns t pd0 output delay to 0 500 ns t sv cs to status valid 500 ns t df cs to do in 100 ns tri-state ? t wp write cycle time 10 ms
4 www.fairchildsemi.com nm93c66a rev. d.2 nm93c66a 4k-bit serial cmos eeprom (microwire? bus interface) absolute maximum ratings (note 1) ambient storage temperature C65 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating range ambient operating temperature nm93c66al/lz 0 c to +70 c nm93c66ale/lze -40 c to +85 c nm93c66alv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 4.5v ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v .03v/1.8v 1.0v 0.8v/1.5v 10 m a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v -2.1ma/0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf) capacitance t a = 25 c, f = 1 mhz symbol test typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20 na range. note 3 : the org pin may draw > 1 m a when in the x8 mode ude to an internal pull-up transistor. note 4 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 5 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagrams in the following pages.) low v cc (2.7v to 4.5v) dc and ac electrical characteristics symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 250khz 1ma i ccs standby current cs = v il l 10 m a lz 1 m a i il input leakage v in = 0v to v cc (note 2) 1 m a i ilo input leakage org tied to v cc -1 1 m a org pin org tied to v ss (note 3) -2.5 2.5 i ol output leakage v in = 0v to v cc 1 m a v il input low voltage -0.1 0.15 v cc v v ih input high voltage 0.8 v cc v cc +1 v ol output low voltage i ol = 10 m a 0.1 v cc v v oh output high voltage i oh = -10 m a 0.9 v cc v f sk sk clock frequency (note 4) 0 250 khz t skh sk high time 1 m s t skl sk low time 1 m s t sks sk setup time sk must be at v il for 0.2 m s t sks before cs goes high t cs minimum cs (note 5) 1 m s low time t css cs setup time 0.2 m s t dh do hold time 70 ns t dis di setup time 0.4 m s t csh cs hold time 0 ns t dih di hold time 0.4 m s t pd1 output delay to "1" 2 m s t pd0 output delay to "0" 2 m s t sv cs to status valid 1 m s t df cs to do in cs = v il 0.4 m s tri-state t wp write cycle time 15 ms
5 www.fairchildsemi.com nm93c66a rev. d.2 nm93c66a 4k-bit serial cmos eeprom (microwire? bus interface) microwire i/o pin description chip select (cs): this pin enables and disables the microwire device and performs 3 general functions: 1. when in the low state, the microwire device is disabled and the output tri-stated (high impedance). if this pin is brought high (rising edge active), all internal registers are reset and the device is enabled, allowing microwire communication via di/do pins. to restate, the cs pin must be held high during all device communication and opcode functions. if the cs pin is brought low, all functions will be disabled and reset when cs is brought high again. the exception to this is when a programming cycle is initiated (see 2 and 3). again, all activity on the cs, di and do pins is ignored until cs is brought high. 2. after entering all required opcode and address data, bringing cs low initiates the (asynchronous) programming cycle. 3. when programming is in progress, the data-out pin will display the programming status as either busy (do low) or ready (do high) when cs is brought high. (again, the output will be tri-stated when cs is low.) to restate, during programming, the cs pin may be brought high and low any number of times to view the programming status without affect the programming operation. once programming is completed (output in ready state), the output is 'cleared' (returned to normal tri-state condition) by clocking in a start bit. after the start bit is clocked in, the output will return to a tri-stated condition. when clocked in, this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. serial clock (sk): this pin is the clock input (rising edge active) for clocking in all opcodes and data on the di pin and clocking out all data on the do pin.however, this pin has no effect on the asynchronous program- ming cycle (see the cs pin section) as the ready/busy status is a function of the cs pin only. data-in (di): all serial communication into the device is performed using this input pin (rising edge active). in order to avoid false start bits, or related issues, it is advised to keep the di pin in the low state unless actually clocking in data bits (start bit, opcode, address or incoming data bits to be programmed). please note that the first '1' clocked into the device (after cs is brought high) is seen as a start bit and the beginning of a serial command string, so caution must be observed when bringing cs high. data-out (do): all serial communication out of the device (read opcode) is performed using this output pin (rising edge active) as well as indicating the ready/busy status duting the asynchronous programming cycle. note that, during read operations, the output data is clocked out after the last address bit (a0) is clocked in. if a 3-wire application is required (where di and do are tied together), sections in an-758, or related application notes, must be followed for correct operation. organization (org): this pin controls the device architecture (8-bit data word vs. 16-bit data word). if the org pin is brought to v cc , the device is configured with a 16-bit data word and if the org pin is brought to v ss (ground), the device is configured with an 8-bit data word (refer to other sections for details of both configurations). if the org pin is left floating, the device will default to a 16-bit data word. instruction set for nm93c66a org memory pin configuration # of address bits logic 0 512 x 8 9 bits 1 256 x 16 8 bits
6 www.fairchildsemi.com nm93c66a rev. d.2 nm93c66a 4k-bit serial cmos eeprom (microwire? bus interface) 256 by 16-bit organization (nm93c66a when org = v cc or nc) instruction sb op-code address data comments 2 bits 8 bits 16 bits read 1 10 a7Ca0 read data stored in selected registers. ewen 1 00 11xxxxxx enables programming modes. ewds 1 00 00xxxxxx disables all programming modes. erase 1 11 a7Ca0 erase selected register. write 1 01 a7Ca0 d15Cd0 writes data pattern d15Cd0 into selected register. eral 1 00 10xxxxxx erases all registers. wral 1 00 01xxxxxx d15Cd0 writes data pattern d15Cd0 into all registers. 512 by 8-bit organization (nm93c66a when org = gnd) instruction sb op-code address data comments 2 bits 9 bits 8 bits read 1 10 a8Ca0 read data stored in selected registers. ewen 1 00 11xxxxxxx enables programming modes. ewds 1 00 00xxxxxxx disables all programming modes. erase 1 11 a8Ca0 erase selected register. write 1 01 a8Ca0 d7Cd0 writes data pattern d7Cd0 into selected register. eral 1 00 10xxxxxxx erases all registers. wral 1 00 01xxxxxxx d7Cd0 writes data pattern d7Cd0 into all registers. functional description programming: 1. programming is initiated by clocking in the start bit, opcode bits, address bits and the 8/16 data bits (refer to the org pin section). 2. programming is started by bringing the cs pin low. once the programming cycle is started, it cannot be stopped. (bringing v cc low will stop any programming, but will also result in data corruption.) 3. the status of the programming cycle (busy or ready) is observed by bringing the cs pin high and observing the output state. if the output is low, the device is still program- ming (busy). if the output is high, the programming cycle has been completed and the device is ready for the next operation. note that the output will be tri-stated each time cs is brought low and the r/b status will be shown each time cs is brought high. 4. after programming, the ready state (output high) can be reset and the output tri-stated by clocking in a single start bit. this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. in any case, clocking in a '1' bit will tri-state the output. read (read): the read instruction outputs serial data on the do pin. after a read instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a serial-out shift register. a dummy bit (logical 0) precedes the serial data output string. output data changes are initiated by a low to high transition of sk after the last address bit (a0) is clocked in. erase/write enable (ewen): when v cc is applied to the part, it powers up in the erase/write disable (ewds) state. therefore, all programming modes must be preceded by an erase/write enable (ewen) instruction. once an erase/write enable instruction is executed, programming remains enabled until an erase/write disable (ewds) instruction is executed or v cc is removed from the part.
7 www.fairchildsemi.com nm93c66a rev. d.2 nm93c66a 4k-bit serial cmos eeprom (microwire? bus interface) functional description (continued) erase/write disable (ewds): to protect against accidental data overwrites, the erase/write disable (ewds) instruction disables all programming modes and should follow all programming operations. execution of a read instruction is independent of both the ewen and ewds instruc- tions. erase (erase): the erase instruction will program all bits in the specified register to the logical 1 state. please refer to the programming section for details. write (write): the write instruction is followed by 16 bits of data (or 8 bits of data when using the nm93c66a in the x8 organization) to be written into the specified address. please refer to the program- ming section for details. erase all (eral): the eral instruction will simultaneously program all registers in the memory array to the logical 1 state. write all (wral): the wral instruction will simultaneously program all registers with the data pattern specified in the instruction. timing diagrams for the nm93c66a status valid synchronous data timing v ih v il cs v ih v il sk v ih v il di v oh v ol do (read) v oh v ol do (program) t css t sks t dis t dih t pd0 t pd1 t dh t df t df t dh t sv t skh t skl t csh ds012510-4
8 www.fairchildsemi.com nm93c66a rev. d.2 nm93c66a 4k-bit serial cmos eeprom (microwire? bus interface) timing diagrams for the nm93c66a (continued) cs sk di 1 . . . org = v cc , 6 x's org = v ss , 7 x's t cs ewen do = tri-state 0011 xx cs sk di 1 . . . org = v cc , 6 x's org = v ss , 7 x's t cs ewds do = tri-state 0000 xx ds012510-6 ds012510-7 1 cs sk di do 10 0d n . . . d 0 a n . . . a 0 t cs read ds012510-5 key for timing diagrams organization of address and data fields for the nm93c66a org pin organization a n d n v cc or nc 256 x 16 a7 d15 v ss 512 x 8 a8 d7
9 www.fairchildsemi.com nm93c66a rev. d.2 nm93c66a 4k-bit serial cmos eeprom (microwire? bus interface) timing diagrams for the nm93c66a (continued) eral 1 001 0 cs busy ready tri-state tri-state standby check status do sk di t wp t cs wral 1 . . . . . . 000 1 x xd 0 d n cs busy ready do sk di t wp ds012510-10 ds012510-11 write 1 . . . . . . t cs 0 1 a n a 0 d n d 0 cs busy ready do sk di t wp ds012510-9 erase 111 . . . a 0 a n cs busy ready tri-state tri-state standby check status do sk di t wp t cs ds012510-8
10 www.fairchildsemi.com nm93c66a rev. d.2 nm93c66a 4k-bit serial cmos eeprom (microwire? bus interface) physical dimensions inches (millimeters) unless otherwise noted molded small outline package (m8) package number m08a 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
11 www.fairchildsemi.com nm93c66a rev. d.2 nm93c66a 4k-bit serial cmos eeprom (microwire? bus interface) physical dimensions inches (millimeters) unless otherwise noted 8-pin molded tssop, jedec (mt8) package number mtc08 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
12 www.fairchildsemi.com nm93c66a rev. d.2 nm93c66a 4k-bit serial cmos eeprom (microwire? bus interface) physical dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident molded dual-in-line package (n) package number n08e fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
nm93c86a 16k-bit serial cmos eeprom (microwire? bus interface) 1 www.fairchildsemi.com nm93c86a rev. e.2 march 1999 nm93c86a 16k-bit serial eeprom (microwire? bus interface) general description the nm93c86a is 16,384 bits of cmos nonvolatile, electrically erasable memory available in user organized as either 1024 16- bit registers or 2048 8-bit registers. the user organization is determined by the status of the org input. the memory device is fabricated using fairchild semiconductors floating gate cmos process for high reliability, high endurance and low power con- sumption. the nm93c86a is available in 8-pin so and tssop packages for space considerations. the eeprom is microwire? compatible for simple interfac- ing to a wide variety of microcontrollers and microprocessors. there are 7 instructions that operate the nm93c86a: read, erase/write enable, erase, write, erase/write disable, write all, and erase all. the nm93c86a defaults to the 1024 x 16 configuration if the org pin (pin 6) is left floating, as it is internally pulled up to v cc . block diagram features n 2.7v to 5.5v operation in all modes n typical active current of 200 m a 10 m a standby current typical 1 m a standby current typical (l) 0.1 m a standby current typical (lz) n device status indication during programming mode n no erase required before write n reliable cmos floating gate technology n microwire? compatible serial i/o n self-timed programming cycle n 40 years data retention n endurance: 1,000,000 data changes n packages available: 8-pin so, 8-pin dip ds011254-12 instruction decoder control logic, and clock generators high voltage generator and program timer instruction register address register eeprom array 16384 bits (1024x16) or (2048x8) read/write amps data in/out register 16 (or 8) bits decoder 1 of 1024 (or 2048) data out buffer v pp v cc cs sk di do gnd org ? 1999 fairchild semiconductor corporation
nm93c86a 16k-bit serial cmos eeprom (microwire? bus interface) 2 www.fairchildsemi.com nm93c86a rev. e.2 connection diagram dual-in-line package (n) and 8-pin so package (m8) top view see package number n08e and m08a pin names pin description cs chip select sk serial data clock di serial data input do serial data output v ss ground org memory organization select nc no connect v cc positive power supply ordering information nm 93 c xx a lz e xx letter description package n 8-pin dip m8 8-pin so8 temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current a x8 or x16 configuration density 86 16k c cmos interface 93 microwire nm fairchild non-volatile memory v cc org v ss cs sk di do 1 2 3 4 8 7 6 5 nc nm93c86a ds011254-14
nm93c86a 16k-bit serial cmos eeprom (microwire? bus interface) 3 www.fairchildsemi.com nm93c86a rev. e.2 absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground v cc + 1 to -0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v operating range ambient operating temperature nm93c86a 0 c to +70 c nm93c86ae -40 c to +85 c nm93c86av -40 c to +125 c power supply (v cc ) range 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v symbol parameter part number conditions min max units i cca operating current cs = v ih , sk=1 mhz 1 ma i ccs standby current cs = 0v org = v cc or nc 50 m a i il input leakage v in = 0v to v cc (note 2) -1 1 m a i ilo input leakage org pin org tied to v cc -1 1 org tied to v ss -2.5 2.5 m a (note 3) i ol output leakage v in = 0v to v cc -1 1 m a v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v v ol1 output low voltage i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = -400 m a 2.4 v v ol2 output low voltage i ol = 10 m a 0.2 v v oh2 output high voltage i ol = -10 m av cc - 0.2 v f sk sk clock frequency (note 4) 0 1 mhz t skh sk high time nm93c86a 250 ns nm93c86ae/v 300 t skl sk low time 250 ns t sks sk setup time sk must be at v il for 50 ns t sks before cs goes high t cs minimum cs low time (note 5) 250 ns t css cs set-up time 50 ns t dh do hold time 70 ns t dis di set-up time nm93c86a 100 ns nm93c86ae/v 200 t csh cs hold time 0 ns t dih di hold time 20 ns t pd1 output delay to 1 500 ns t pd0 output delay to 0 500 ns t sv cs to status valid 500 ns t df cs to do in tri-state ? 100 ns t wp write cycle time 10 ms
nm93c86a 16k-bit serial cmos eeprom (microwire? bus interface) 4 www.fairchildsemi.com nm93c86a rev. e.2 absolute maximum ratings (note 1) ambient storage temperature C65 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating range ambient operating temperature nm93c86al/lz 0 c to +70 c nm93c86ale/lze -40 c to +85 c nm93c86alv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 4.5v ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v .03v/1.8v 1.0v 0.8v/1.5v 10 m a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v -2.1ma/0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf) capacitance t a = 25 c, f = 1 mhz symbol test typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20 na range. note 3 : the org pin may draw > 1 m a when in the x8 mode ude to an internal pull-up transistor. note 4 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 5 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagrams in the following pages.) low v cc (2.7v to 4.5v) dc and ac electrical characteristics symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 250khz 1ma i ccs standby current cs = v il l 10 m a lz 1 m a i il input leakage v in = 0v to v cc (note 2) 1 m a i ilo input leakage org tied to v cc -1 1 m a org pin org tied to v ss (note 3) -2.5 2.5 i ol output leakage v in = 0v to v cc 1 m a v il input low voltage -0.1 0.15 v cc v v ih input high voltage 0.8 v cc v cc +1 v ol output low voltage i ol = 10 m a 0.1 v cc v v oh output high voltage i oh = -10 m a 0.9 v cc v f sk sk clock frequency (note 4) 0 250 khz t skh sk high time 1 m s t skl sk low time 1 m s t sks sk setup time sk must be at v il for 0.2 m s t sks before cs goes high t cs minimum cs (note 5) 1 m s low time t css cs setup time 0.2 m s t dh do hold time 70 ns t dis di setup time 0.4 m s t csh cs hold time 0 ns t dih di hold time 0.4 m s t pd1 output delay to "1" 2 m s t pd0 output delay to "0" 2 m s t sv cs to status valid 1 m s t df cs to do in cs = v il 0.4 m s tri-state t wp write cycle time 15 ms
nm93c86a 16k-bit serial cmos eeprom (microwire? bus interface) 5 www.fairchildsemi.com nm93c86a rev. e.2 instruction set for the nm93c86a org memory pin configuration # of address bits logic 0 2048 x 8 11 bits 1 1024 x 16 10 bits microwire i/o pin description chip select (cs): this pin enables and disables the microwire device and performs 2 general functions: 1. when in the low state, the microwire device is disabled and the output tri-stated (high impedance). if this pin is brought high (rising edge active), all internal registers are reset and the device is enabled, allowing microwire communication via di/do pins. to restate, the cs pin must be held high during all device communication and opcode functions. if the cs pin is brought low, all functions will be disabled and reset when cs is brought high again. the exception to this is when a programming cycle is initiated. again, all activity on the cs, di and do pins is ignored until cs is brought high. 2. when programming is in progress, the data-out pin will display the programming status as either busy (do low) or ready (do high) when cs is brought high. (again, the output will be tri-stated when cs is low.) to restate, during programming, the cs pin may be brought high and low any number of times to view the programming status without affect the programming operation. once programming is completed (output in ready state), the output is 'cleared' (returned to normal tri-state condition) by clocking in a start bit. after the start bit is clocked in, the output will return to a tri-stated condition. when clocked in, this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. unlike the lower density members of the microwire product family (nm93c06, nm93c46, nm93c56, nm93c66) programming is not initiated by bringing cs low. serial clock (sk): this pin is the clock input (rising edge active) for clocking in all opcodes and data on the di pin and clocking out all data on the do pin. however, this pin has no effect on the asynchronous program- ming cycle (see the cd pin section) as the busy/ready status is a function of the cd pin only. data-in (di): all serial communication into the device is performed using this input pin (rising edge active). in order to avoid false start bits, or related issues, it is advised to keep the di pin in the low state unless actually clocking in data bits (start bit, opcode, address or incoming data bits to be programmed). please note that the first '1' clocked into the device (after cs is brought high) is seen as a start bit and the beginning of a serial command string, so caution must be observed when bringing cs high. data-out (do): all serial communication out of the device (read opcode) is performed using this output pin (rising edge active) as well as indicating the ready/busy status duting the asynchronous programming cycle. note that, during read operations, the output data is clocked out after the last address bit (a0) is clocked in. if a 3-wire application is required (where di and do are tied together), sections in an-758, or related application notes, must be followed for correct operation. organization (org): this pin controls the device architecture (8-bit data word vs. 16-bit data word). if the org pin is brought to v cc , the device is configured with a 16-bit data word and if the org pin is brought to v ss (ground), the device is configured with an 8-bit data word (refer to other sections for details of both configurations). if the org pin is left floating, the device will default to a 16-bit data word.
nm93c86a 16k-bit serial cmos eeprom (microwire? bus interface) 6 www.fairchildsemi.com nm93c86a rev. e.2 1024 by 16-bit organization (nm93c86a when org = v cc or nc) instruction sb op code address data function 2 bits 10 bits 16 bits read 1 10 a9Ca0 read data stored in selected registers. ewen 1 00 11xxxxxxxx enables programming modes. ewds 1 00 00xxxxxxxx disables all programming modes. erase 1 11 a9Ca0 erases selected register. write 1 01 a9Ca0 d15Cd0 writes data pattern d15Cd0 into selected register. eral 1 00 10xxxxxxxx erases all registers. wral 1 00 01xxxxxxxx d15Cd0 writes data pattern d15Cd0 into all registers. 2048 by 8-bit organization (nm93c86a when org = gnd) instruction sb op code address data function 2 bits 11 bits 8 bits read 1 10 a10Ca0 read data stored in selected registers. ewen 1 00 11xxxxxxxxx enables programming modes. ewds 1 00 00xxxxxxxxx disables all programming modes. erase 1 11 a10Ca0 erases selected register. write 1 01 a10Ca0 d7Cd0 writes data pattern d7Cd0 into selected register. eral 1 00 10xxxxxxxxx erases all registers. wral 1 00 01xxxxxxxxx d7Cd0 writes data pattern d7Cd0 into all registers. functional description programming the programming cycle is automatically started after entering the last bit of the programming instruction string (unlike other microwire family members which use cs to initiate programming). this feature, counting the number of instruction bits, decreases the likelihood of inadvertent programming and allows the pro- gramming to be cancelled before sending out the last bit in the string (be bringing cs low). programming instruction last bit in string write d0 wral d0 erase a0 eral a0 note that, in the erase/eral instructions, the a0 bit is the last bit in the string and clocking in that bit will initiate programming. in order to maintain compatibility, cs may be brought low after clocking in the last bit, but it is not necessary. in all programming modes the ready/busy status of the device can be determined by polling the do pin. after clocking in the last bit of the instruction sequence and with the cs held high, the do pin will exit the high impedance state and indicate the ready/ busy status of the device. do = logical 0 indicates that program- ming is still in progress and no other instruction can be executed. do = logical 1 indicates that the device is ready for another instruction. if cs is forced low the do pin will return to the high impedance state. after the programming cycle has been com- pleted and do = logical 1, the do pin can be reset back to the high impedance state by clocking a logical 1 into the di pin. (this is also performed with the start bit on all op codes, thus clocking an instruction has the same effect.) read (read) the read instruction outputs serial data on the do pin. after a read instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a serial-out shift register. a dummy bit (logical 0) precedes the serial data output string. output data changes are initiated by a low to high transition of sk clock after the last address bit (a0) is clocked in. erase/write enable (ewen) when v cc is applied to the part, it powers up in the erase/write disable (ewds) state. therefore, all programming modes must be preceded by an erase/write enable (ewen) instruction. once an erase/write enable instruction is executed, programming remains enabled until an erase/write disable (ewds) instruction is executed or v cc is removed from the part.
nm93c86a 16k-bit serial cmos eeprom (microwire? bus interface) 7 www.fairchildsemi.com nm93c86a rev. e.2 functional description (continued) erase/write disable (ewds) to protect against accidental data overwrites, the erase/write disable (ewds) instruction disables all programming modes and should follow all programming operations. execution of a read instruction is independent of both the ewen and ewds instruc- tions. erase (erase) the erase instruction will program all bits in the specified register to the logical 1 state. the self-timed programming cycle is initiated on the rising edge of the sk clock as the last address bit (a0) is clocked in. at this point cs, sk and di become dont care states. after starting an erase cycle the do pin indicates the ready/busy status of the chip if cs is held high. do = logical 0 indicates that programming is still in progress. do = logical 1 indicates that the register, at the address specified in the instruc- tion, has been erased. write (write) the write instruction is followed by 16 bits of data (or 8 bits of data when using the nm93c86a in the x8 organization) to be written into the specified address. note that if the cs is brought low before clocking in all of the data bits, then the write instruction will be aborted. the self-timed programming cycle is initiated on the rising edge of the sk clock as the last data bit (d0) is clocked in. at this point, cs, sk and di become dont care states. no separate erase cycle is required before a write instruction. as in the erase instruction, after starting a write cycle, the do pin indicates the ready/busy status of the chip if cs is held high. do = logical 0 indicates that programming is still in progress. do = logical 1 indicates that the register, at the address specified in the instruction, has been written and that the part is ready for another instruction. erase all (eral) the eral instruction will simultaneously program all registers in the memory array to the logical 1 state. write all (wral) the wral instruction will simultaneously program all registers with the data pattern specified in the instruction. timing diagrams for the nm93c86a synchronous data timing status valid v ih v il cs v ih v il sk v ih v il di v oh v ol do (read) v oh v ol do (program) t css t sks t dis t dih t pd0 t pd1 t dh t df t df t dh t sv t skh t skl t csh ds011254-3
nm93c86a 16k-bit serial cmos eeprom (microwire? bus interface) 8 www.fairchildsemi.com nm93c86a rev. e.2 timing diagrams for the nm93c86a (continued) ewds do = tri-state erase cs sk di 1 t cs 001 1 . . . xx org = v cc , 8 x's org = v ss , 9 x's cs sk di 1 t cs 00 00x . . . x org = v cc , 8 x's org = v ss , 9 x's cs sk di do 1 11a n . . . a 0 ready status signal resets to tri-state after clocking in one sk cycle with di = 1 t wp busy ready ds011254-5 ds011254-6 ds011254-7 ewen do = tri-state key for timing diagrams organization of address and data fields for the nm93c86a 1 cs sk di do 10 0d n . . . d 0 a n . . . a 0 t cs ds011254-4 org organization a n d n v cc or nc 1024 x 16 a9 d15 v ss 2048 x 8 a10 d7 read
nm93c86a 16k-bit serial cmos eeprom (microwire? bus interface) 9 www.fairchildsemi.com nm93c86a rev. e.2 timing diagrams for the nm93c86a (continued) cs sk di do 1 00 10x . . . x ready status signal resets to tri-state after clocking in one sk cycle with di = 1 t wp busy ready org = v cc , 8 x's org = v ss , 9 x's cs sk di do 1 0 001xx . . . . . . d n d 0 ready status signal resets to tri-state after clocking in one sk cycle with di = 1 t wp busy ready org = v cc , 8 x's org = v ss , 9 x's ds011254-9 ds011254-10 eral wral write cs sk di do 1 01a n a 0 d n . . . . . . d 0 ready status signal resets to tri-state after clocking in one sk cycle with di = 1 t wp busy ready ds011254-8
nm93c86a 16k-bit serial cmos eeprom (microwire? bus interface) 10 www.fairchildsemi.com nm93c86a rev. e.2 physical dimensions inches (millimeters) unless otherwise noted molded small outline package (m8) package number m08a 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ.
nm93c86a 16k-bit serial cmos eeprom (microwire? bus interface) 11 www.fairchildsemi.com nm93c86a rev. e.2 molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
nm93c86au 16k-bit microwire interface serial eeprom 1 www.fairchildsemi.com nm93c86au rev. a.2 may 1999 nm93c86au 16k-bit microwire interface serial eeprom general description the nm93c86au is a 16k (16,384) bit serial interface cmos eeprom (electrically erasable programmable read-only memory). this device fully conforms to the microwire 4-wire protocol which uses chip select (cs), clock (sk). data-in (di) and data-out (do) pins to synchronously control the eeprom data transfer and the org pin, which allows configuring the part for an 8-bit or 16-bit data format. in addition, the serial interface allows a minimal pin count, packaging designed to simplify pc board layout requirements and offers the designer a variety of low voltage and low power options. the nm93c86au microwire eeprom offers the user the ability to configure the eeprom as a 16-bit dataword (org pin = v cc ; 16 bits x 1,024 addresses) or an 8-bit data byte (org pin = v ss ; 8 bits x 2,048 addresses). fairchild eeproms are designed and tested for applications requiring high endurance, high reliability, and low power con- sumption for a continuously reliable non-volatile solution for all markets. block diagram functions microwire 4-wire interface 16k bits organized as 8 x 2,048 or 16 x 1,024 organization (org pin control) extended 2.7v to 5.5v operating voltage 1mhz operation self-timed programming cycle (6ms typical) "programming complete" indicated by do ready/busy polling features the microwire interface offers the greatest ease of use vs. clock rate of serial data transfer methods bulk mode programming to allow simultaneous programming of all addresses low v cc programming lockout (3.8v) ?"h" option (standard v cc range) parts only schmitt trigger (hysteresis) on all inputs typical 200 a active current (i cca ) typical 1 a standby current (i sb ) for "l" devices and 0.1 a standby current for "lz" devices endurance: up to 1,000,000 data changes data retention greater than 40 years ds800021-12 instruction decoder control logic, and clock generators high voltage generator and program timer instruction register address register eeprom array 16384 bits (1024x16) or (2048x8) read/write amps data in/out register 16 (or 8) bits decoder 1 of 1024 (or 2048) data out buffer v pp v cc cs sk di do gnd org ? 1999 fairchild semiconductor corporation
nm93c86au 16k-bit microwire interface serial eeprom 2 www.fairchildsemi.com nm93c86au rev. a.2 connection diagram dual-in-line package (n) and 8-pin so package (m8) top view see package number n08e and m08a pin names pin description cs chip select sk serial data clock di serial data input do serial data output v ss ground org memory organization select nc no connect v cc positive power supply ordering information nm 93 c xx a u lz e xx letter description package n 8-pin dip m8 8-pin so8 temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 a standby current h 4.5 to 5.5v and v cc lockout ultralite cs100ul process a x8 or x16 configuration density 86 16k c cmos interface 93 microwire nm fairchild non-volatile memory v cc org v ss cs sk di do 1 2 3 4 8 7 6 5 nc nm93c86au ds800021-14
nm93c86au 16k-bit microwire interface serial eeprom 3 www.fairchildsemi.com nm93c86au rev. a.2 absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground v cc + 1 to -0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v operating range ambient operating temperature nm93c86au 0 c to +70 c nm93c86aue -40 c to +85 c nm93c86auv -40 c to +125 c power supply (v cc ) range nm93c86au/nm93c86auh 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v symbol parameter part number conditions min max units i cca operating current cs = v ih , sk=1 mhz 1 ma i ccs standby current cs = 0v org = v cc or nc 50 a i il input leakage v in = 0v to v cc (note 2) -1 1 a i ilo input leakage org pin org tied to v cc -1 1 org tied to v ss -2.5 2.5 a (note 3) i ol output leakage v in = 0v to v cc -1 1 a v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v v ol1 output low voltage i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = -400 a 2.4 v v ol2 output low voltage i ol = 10 a 0.2 v v oh2 output high voltage i ol = -10 av cc - 0.2 v f sk sk clock frequency (note 4) 0 1 mhz t skh sk high time nm93c86au 250 ns nm93c86aue/v 300 t skl sk low time 250 ns t sks sk setup time sk must be at v il for 50 ns t sks before cs goes high t cs minimum cs low time (note 5) 250 ns t css cs set-up time 50 ns t dh do hold time 70 ns t dis di set-up time nm93c86au 100 ns nm93c86aue/v 200 t csh cs hold time 0 ns t dih di hold time 20 ns t pd1 output delay to 1 500 ns t pd0 output delay to 0 500 ns t sv cs to status valid 500 ns t df cs to do in tri-state 100 ns t wp write cycle time 10 ms
nm93c86au 16k-bit microwire interface serial eeprom 4 www.fairchildsemi.com nm93c86au rev. a.2 absolute maximum ratings (note 1) ambient storage temperature 65 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating range ambient operating temperature nm93c86aul/lz 0 c to +70 c nm93c86aule/lze -40 c to +85 c nm93c86aulv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 4.5v ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v .03v/1.8v 1.0v 0.8v/1.5v 10 a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v -2.1ma/0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf) capacitance t a = 25 c, f = 1 mhz symbol test typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20 na range. note 3 : the org pin may draw > 1 a when in the x8 mode ude to an internal pull-up transistor. note 4 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 5 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagrams in the following pages.) low v cc (2.7v to 4.5v) dc and ac electrical characteristics symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 250khz 1ma i ccs standby current cs = v il l 10 a lz 1 a i il input leakage v in = 0v to v cc (note 2) 1 a i ilo input leakage org tied to v cc -1 1 a org pin org tied to v ss (note 3) -2.5 2.5 i ol output leakage v in = 0v to v cc 1 a v il input low voltage -0.1 0.15 v cc v v ih input high voltage 0.8 v cc v cc +1 v ol output low voltage i ol = 10 a 0.1 v cc v v oh output high voltage i oh = -10 a 0.9 v cc v f sk sk clock frequency (note 4) 0 250 khz t skh sk high time 1 s t skl sk low time 1 s t sks sk setup time sk must be at v il for 0.2 s t sks before cs goes high t cs minimum cs (note 5) 1 s low time t css cs setup time 0.2 s t dh do hold time 70 ns t dis di setup time 0.4 s t csh cs hold time 0 ns t dih di hold time 0.4 s t pd1 output delay to "1" 2 s t pd0 output delay to "0" 2 s t sv cs to status valid 1 s t df cs to do in cs = v il 0.4 s tri-state t wp write cycle time 15 ms
nm93c86au 16k-bit microwire interface serial eeprom 5 www.fairchildsemi.com nm93c86au rev. a.2 instruction set for the nm93c86au org memory pin configuration # of address bits logic 0 2048 x 8 11 bits 1 1024 x 16 10 bits microwire i/o pin description chip select (cs): this pin enables and disables the microwire device and performs 2 general functions: 1. when in the low state, the microwire device is disabled and the output tri-stated (high impedance). if this pin is brought high (rising edge active), all internal registers are reset and the device is enabled, allowing microwire communication via di/do pins. to restate, the cs pin must be held high during all device communication and opcode functions. if the cs pin is brought low, all functions will be disabled and reset when cs is brought high again. the exception to this is when a programming cycle is initiated. again, all activity on the cs, di and do pins is ignored until cs is brought high. 2. when programming is in progress, the data-out pin will display the programming status as either busy (do low) or ready (do high) when cs is brought high. (again, the output will be tri-stated when cs is low.) to restate, during programming, the cs pin may be brought high and low any number of times to view the programming status without affect the programming operation. once programming is completed (output in ready state), the output is 'cleared' (returned to normal tri-state condition) by clocking in a start bit. after the start bit is clocked in, the output will return to a tri-stated condition. when clocked in, this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. unlike the lower density members of the microwire product family (nm93c06, nm93c46, nm93c56, nm93c66) programming is not initiated by bringing cs low. serial clock (sk): this pin is the clock input (rising edge active) for clocking in all opcodes and data on the di pin and clocking out all data on the do pin. however, this pin has no effect on the asynchronous program- ming cycle (see the cd pin section) as the busy/ready status is a function of the cd pin only. data-in (di): all serial communication into the device is performed using this input pin (rising edge active). in order to avoid false start bits, or related issues, it is advised to keep the di pin in the low state unless actually clocking in data bits (start bit, opcode, address or incoming data bits to be programmed). please note that the first '1' clocked into the device (after cs is brought high) is seen as a start bit and the beginning of a serial command string, so caution must be observed when bringing cs high. data-out (do): all serial communication out of the device (read opcode) is performed using this output pin (rising edge active) as well as indicating the ready/busy status duting the asynchronous programming cycle. note that, during read operations, the output data is clocked out after the last address bit (a0) is clocked in. if a 3-wire application is required (where di and do are tied together), sections in an-758, or related application notes, must be followed for correct operation. organization (org): this pin controls the device architecture (8-bit data word vs. 16-bit data word). if the org pin is brought to v cc , the device is configured with a 16-bit data word and if the org pin is brought to v ss (ground), the device is configured with an 8-bit data word (refer to other sections for details of both configurations). if the org pin is left floating, the device will default to a 16-bit data word.
nm93c86au 16k-bit microwire interface serial eeprom 6 www.fairchildsemi.com nm93c86au rev. a.2 1024 by 16-bit organization (nm93c86au when org = v cc or nc) instruction sb op code address data function 2 bits 10 bits 16 bits read 1 10 a9 a0 read data stored in selected registers. ewen 1 00 11xxxxxxxx enables programming modes. ewds 1 00 00xxxxxxxx disables all programming modes. erase 1 11 a9 a0 erases selected register. write 1 01 a9 a0 d15 d0 writes data pattern d15 d0 into selected register. eral 1 00 10xxxxxxxx erases all registers. wral 1 00 01xxxxxxxx d15 d0 writes data pattern d15 d0 into all registers. 2048 by 8-bit organization (nm93c86au when org = gnd) instruction sb op code address data function 2 bits 11 bits 8 bits read 1 10 a10 a0 read data stored in selected registers. ewen 1 00 11xxxxxxxxx enables programming modes. ewds 1 00 00xxxxxxxxx disables all programming modes. erase 1 11 a10 a0 erases selected register. write 1 01 a10 a0 d7 d0 writes data pattern d7 d0 into selected register. eral 1 00 10xxxxxxxxx erases all registers. wral 1 00 01xxxxxxxxx d7 d0 writes data pattern d7 d0 into all registers. functional description programming the programming cycle is automatically started after entering the last bit of the programming instruction string (unlike other microwire family members which use cs to initiate programming). this feature, counting the number of instruction bits, decreases the likelihood of inadvertent programming and allows the pro- gramming to be cancelled before sending out the last bit in the string (be bringing cs low). programming instruction last bit in string write d0 wral d0 erase a0 eral a0 note that, in the erase/eral instructions, the a0 bit is the last bit in the string and clocking in that bit will initiate programming. in order to maintain compatibility, cs may be brought low after clocking in the last bit, but it is not necessary. in all programming modes the ready/busy status of the device can be determined by polling the do pin. after clocking in the last bit of the instruction sequence and with the cs held high , the do pin will exit the high impedance state and indicate the ready/ busy status of the device. do = logical 0 indicates that program- ming is still in progress and no other instruction can be executed. do = logical 1 indicates that the device is ready for another instruction. if cs is forced low the do pin will return to the high impedance state. after the programming cycle has been com- pleted and do = logical 1 , the do pin can be reset back to the high impedance state by clocking a logical 1 into the di pin. (this is also performed with the start bit on all op codes, thus clocking an instruction has the same effect.) read (read) the read instruction outputs serial data on the do pin. after a read instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a serial-out shift register. a dummy bit (logical 0) precedes the serial data output string. output data changes are initiated by a low to high transition of sk clock after the last address bit (a0) is clocked in. erase/write enable (ewen) when v cc is applied to the part, it powers up in the erase/write disable (ewds) state. therefore, all programming modes must be preceded by an erase/write enable (ewen) instruction. once an erase/write enable instruction is executed, programming remains enabled until an erase/write disable (ewds) instruction is executed or v cc is removed from the part.
nm93c86au 16k-bit microwire interface serial eeprom 7 www.fairchildsemi.com nm93c86au rev. a.2 functional description (continued) erase/write disable (ewds) to protect against accidental data overwrites, the erase/write disable (ewds) instruction disables all programming modes and should follow all programming operations. execution of a read instruction is independent of both the ewen and ewds instruc- tions. erase (erase) the erase instruction will program all bits in the specified register to the logical 1 state. the self-timed programming cycle is initiated on the rising edge of the sk clock as the last address bit (a0) is clocked in. at this point cs, sk and di become don t care states. after starting an erase cycle the do pin indicates the ready/busy status of the chip if cs is held high . do = logical 0 indicates that programming is still in progress. do = logical 1 indicates that the register, at the address specified in the instruc- tion, has been erased. write (write) the write instruction is followed by 16 bits of data (or 8 bits of data when using the nm93c86au in the x8 organization) to be written into the specified address. note that if the cs is brought low before clocking in all of the data bits, then the write instruction will be aborted. the self-timed programming cycle is initiated on the rising edge of the sk clock as the last data bit (d0) is clocked in. at this point, cs, sk and di become don t care states. no separate erase cycle is required before a write instruction. as in the erase instruction, after starting a write cycle, the do pin indicates the ready/busy status of the chip if cs is held high . do = logical 0 indicates that programming is still in progress. do = logical 1 indicates that the register, at the address specified in the instruction, has been written and that the part is ready for another instruction. erase all (eral) the eral instruction will simultaneously program all registers in the memory array to the logical 1 state. write all (wral) the wral instruction will simultaneously program all registers with the data pattern specified in the instruction. low v cc lockout the nm93c86axhx ( h option) protects against data corruption during programming by preventing any programming operations if v cc drops below approximately 3.8v (v cc lockout trip level). this is accomplished by continually monitoring the cs (chip select) pin and, when active (high), preventing programming if the v cc drops below the lockout trip level. after any programming opcode is fully clocked in and the v pp internal high voltage has been turned on, the lockout is disabled. the lockout is inactive if any opcode is entered except a programming opcode. disabled programming is indicated by no busy signal appearing at the output (the output remains tri-stated). to restate, the v cc lockout feature is active from the time cs goes high up to the time that the v pp internal high voltage is turned on. (the low v cc lockout feature is not enabled for any non-programming opcodes.) once programming has begun, the programming cycle can- not be interrupted except by removal of v cc , which could result in data corruption. timing diagrams for the nm93c86au synchronous data timing status valid v ih v il cs v ih v il sk v ih v il di v oh v ol do (read) v oh v ol do (program) t css t sks t dis t dih t pd0 t pd1 t dh t df t df t dh t sv t skh t skl t csh ds800021-3
nm93c86au 16k-bit microwire interface serial eeprom 8 www.fairchildsemi.com nm93c86au rev. a.2 timing diagrams for the nm93c86au (continued) ewds do = tri-state erase cs sk di 1 t cs 001 1 . . . xx org = v cc , 8 x's org = v ss , 9 x's cs sk di 1 t cs 00 00x . . . x org = v cc , 8 x's org = v ss , 9 x's cs sk di do 1 11a n . . . a 0 ready status signal resets to tri-state after clocking in one sk cycle with di = 1 t wp busy ready ds800021-5 ds800021-6 ds800021-7 ewen do = tri-state key for timing diagrams organization of address and data fields for the nm93c86au 1 cs sk di do 10 0d n . . . d 0 a n . . . a 0 t cs ds800021-4 org organization a n d n v cc or nc 1024 x 16 a9 d15 v ss 2048 x 8 a10 d7 read
nm93c86au 16k-bit microwire interface serial eeprom 9 www.fairchildsemi.com nm93c86au rev. a.2 timing diagrams for the nm93c86au (continued) cs sk di do 1 00 10x . . . x ready status signal resets to tri-state after clocking in one sk cycle with di = 1 t wp busy ready org = v cc , 8 x's org = v ss , 9 x's cs sk di do 1 0 001xx . . . . . . d n d 0 ready status signal resets to tri-state after clocking in one sk cycle with di = 1 t wp busy ready org = v cc , 8 x's org = v ss , 9 x's ds800021-9 ds800021-10 eral wral write cs sk di do 1 01a n a 0 d n . . . . . . d 0 ready status signal resets to tri-state after clocking in one sk cycle with di = 1 t wp busy ready ds800021-8
nm93c86au 16k-bit microwire interface serial eeprom 10 www.fairchildsemi.com nm93c86au rev. a.2 physical dimensions inches (millimeters) unless otherwise noted molded small outline package (m8) package number m08a 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ.
nm93c86au 16k-bit microwire interface serial eeprom 11 www.fairchildsemi.com nm93c86au rev. a.2 molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 physical dimensions inches (millimeters) unless otherwise noted
1 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read february 2000 ?1999 fairchild semiconductor corporation nm93cs06 (microwire? bus interface) 256-bit serial eeprom with data protect and sequential read general description nm93cs06 is a 256-bit cmos non-volatile eeprom organized as 16 x 16-bit array. this device features microwire interface which is a 4-wire serial bus with chipselect (cs), clock (sk), data input (di) and data output (do) signals. this interface is compat- ible to many of standard microcontrollers and microprocessors. nm93cs06 offers programmable write protection to the memory array using a special register called protect register. selected memory locations can be protected against write by programming this protect register with the address of the first memory location to be protected (all locations greater than or equal to this first address are then protected from further change). additionally, this address can be ?ermanently locked?into the device, making all future attempts to change data impossible. in addition this device features ?equential read? by which, entire memory can be read in one cycle instead of multiple single byte read cycles. there are 10 instructions implemented on the nm93cs06, 5 of which are for memory operations and the remaining 5 are for protect register operations. this device is fabricated using fairchild semiconduc- tor floating-gate cmos process for high reliability, high endurance and low power consumption. ?z?and ??versions of nm93cs06 offer very low standby current making them suitable for low power applications. this device is offered in both so and tssop packages for small space considerations. functional diagram features wide v cc 2.7v - 5.5v programmable write protection sequential register read typical active current of 200 a 10 a standby current typical 1 a standby current typical (l) 0.1 a standby current typical (lz) no erase instruction required before write instruction self timed write cycle device status during programming cycles 40 year data retention endurance: 1,000,000 data changes packages available: 8-pin so, 8-pin dip, 8-pin tssop instruction decoder control logic and clock generators comparator and write enable high voltage generator and program timer instruction register address register protect register eeprom array read/write amps data in/out register 16 bits decoder 16 16 data out buffer pre pe cs sk di do v ss v cc
2 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read connection diagram dual-in-line package (n) 8Cpin so (m8) and 8Cpin tssop (mt8) top view package number n08e, m08a and mtc08 pin names cs chip select sk serial data clock di serial data input do serial data output gnd ground pe program enable pre protect register enable v cc power supply ordering information nm 93 cs xx lz e xxx letter description package n 8-pin dip m8 8-pin so mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current density 06 256 bits c cmos cs data protect and sequential read interface 93 microwire fairchild memory prefix v cc pe gnd cs sk di do 1 2 3 4 8 7 6 5 pre
3 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm93cs06 0 c to +70 c nm93cs06e -40 c to +85 c nm93cs06v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics v cc = 4.5v to 5.5v unless otherwise specified symbolparameter conditions min max units i cca operating current cs = v ih , sk=1.0 mhz 1 ma i ccs standby current cs = v il 50 a i il input leakage v in = 0v to v cc -1 a i ol output leakage (note 2) v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v ol1 output low voltage i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = -400 a 2.4 v ol2 output low voltage i ol = 10 a 0.2 v v oh2 output high voltage i oh = -10 av cc - 0.2 f sk sk clock frequency (note 3) 1 mhz t skh sk high time 0 c to +70 c 250 ns -40 c to +125 c 300 t skl sk low time 250 ns t sks sk setup time 50 ns t cs minimum cs low time (note 4) 250 ns t css cs setup time 100 ns t pres pre setup time 50 ns t dh do hold time 70 ns t pes pe setup time 50 ns t dis di setup time 100 ns t csh cs hold time 0 ns t peh pe hold time 250 ns t preh pre hold time 50 ns t dih di hold time 20 ns t pd output delay 500 ns t sv cs to status valid 500 ns t df cs to do in hi-z cs = v il 100 ns t wp write cycle time 10 ms
4 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm93cs06l/lz 0 c to +70 c nm93cs06le/lze -40 c to +85 c nm93cs06lv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 5.5v dc and ac electrical characteristics v cc = 2.7v to 5.5v unless otherwise specified symbolparameter conditions min max units i cca operating current cs = v ih , sk=1.0 mhz 1 ma i ccs standby current cs = v il l 10 a lz (2.7v to 4.5v) 1 a i il input leakage v in = 0v to v cc 1 a i ol output leakage (note 2) v il input low voltage -0.1 0.15v cc v v ih input high voltage 0.8v cc v cc +1 v ol output low voltage i ol = 10 a 0.1v cc v v oh output high voltage i oh = -10 a 0.9v cc f sk sk clock frequency (note 3) 0 250 khz t skh sk high time 1 s t skl sk low time 1 s t sks sk setup time 0.2 s t cs minimum cs low time (note 4) 1 s t css cs setup time 0.2 s t pres pre setup time 50 ns t dh do hold time 70 ns t pes pe setup time 50 ns t dis di setup time 0.4 s t csh cs hold time 0 ns t peh pe hold time 250 ns t preh pre hold time 50 ns t dih di hold time 0.4 s t pd output delay 2 s t sv cs to status valid 1 s t df cs to do in hi-z cs = v il 0.4 s t wp write cycle time 15 ms capacitance t a = 25 c, f = 1 mhz (note 5) symboltest typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20na range. note 3 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 4 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagram on the following page.) note 5 : this parameter is periodically sampled and not 100% tested. ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v 0.3v/1.8v 1.0v 0.8v/1.5v 10 a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v 2.1ma/-0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf)
5 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read pin description chip select (cs) this is an active high input pin to nm93cs06 eeprom (the device) and is generated by a master that is controlling the device. a high level on this pin selects the device and a low level deselects the device. all serial communications with the device is enabled only when this pin is held high. however this pin cannot be permanently tied high, as a rising edge on this signal is required to reset the internal state-machine to accept a new cycle and a falling edge to initiate an internal programming after a write cycle. all activity on the sk, di and do pins are ignored while cs is held low. serial clock (sk) this is an input pin to the device and is generated by the master that is controlling the device. this is a clock signal that synchronizes the communication between a master and the device. all input informa- tion (di) to the device is latched on the rising edge of this clock input, while output data (do) from the device is driven from the rising edge of this clock input. this pin is gated by cs signal. serial input (di) this is an input pin to the device and is generated by the master that is controlling the device. the master transfers input informa- tion (start bit, opcode bits, array addresses and data) serially via this pin into the device. this input information is latched on the rising edge of the sck. this pin is gated by cs signal. serial output (do) this is an output pin from the device and is used to transfer output data via this pin to the controlling master. output data is serially shifted out on this pin from the rising edge of the sck. this pin is active only when the device is selected. protect register enable (pre) this is an active high input pin to the device and is used to distinguish operations to memory array and operations to protect register. when this pin is held low, operations to the memory array are enabled. when this pin is held high, operations to the protect register are enabled. this pin operates in conjunction with pe pin. refer table1 for functional matrix of this pin for various operations. program enable (pe) this is an active high input pin to the device and is used to enable operations, that are write in nature, to the memory array and to the protect register. when this pin is held high, operations that are write in nature are enabled. when this pin is held low, operations that are write in nature are disabled. this pin operates in conjunction with pre pin. refer table1 for functional matrix of this pin for various operations. microwire interface a typical communication on the microwire bus is made through the cs, sk, di and do signals. to facilitate various operations on the memory array and on the protect register, a set of 10 instructions are implemented on nm93cs06. the format of each instruction is listed in table 1. instruction each of the above 10 instructions is explained under individual instruction descriptions. start bit this is a 1-bit field and is the first bit that is clocked into the device when a microwire cycle starts. this bit has to be 1 for a valid cycle to begin. any number of preceding 0 can be clocked into the device before clocking a 1 . opcode this is a 2-bit field and should immediately follow the start bit. these two bits (along with pre, pe signals and 2 msb of address field) select a particular instruction to be executed. address field this is a 6-bit field and should immediately follow the opcode bits. in nm93cs06, only the lsb 4 bits are used for address decoding during read, write and prwrite instructions. during these instructions (read, write and prwrite), the msb 2 bits are "don't care" (can be 0 or 1). during all other instructions (with the exception of prread), the msb 2 bits are used to decode instruction (along with opcode bits, pre and pe signals). data field this is a 16-bit field and should immediately follow the address bits. only the write and wrall instructions require this field. d15 (msb) is clocked first and d0 (lsb) is clocked last (both during writes as well as reads). table 1. instruction set instruction start bit opcode field address field data field pre pin pe pin read 1 10 x x a3 a2 a1 a0 0 x wen 1 00 1 1xxxx 0 1 write 1 01 x x a3 a2 a1 a0 d15-d0 0 1 wrall 1 00 0 1 xxxx d15-d0 0 1 wds 1 00 0 0xxxx 0 x prread 1 10 x x xxxx 1 x pren 1 00 1 1 xxxx 1 1 prclear 1 11 111111 1 1 prwrite 1 01 x x a3 a2 a1 a0 1 1 prds 1 00 000000 1 1
6 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read functional description a typical microwire cycle starts by first selecting the device (bringing the cs signal high). once the device is selected, a valid start bit ( 1 ) should be issued to properly recognize the cycle. following this, the 2-bit opcode of appropriate instruction should be issued. after the opcode bits, the 6-bit address information should be issued. for certain instructions, some (or all) of these 6 bits are don t care values (can be 0 or 1 ), but they should still be issued. following the address information, depending on the instruction (write and wrall), 16-bit data is issued. other- wise, depending on the instruction (read and prread), the device starts to drive the output data on the do line. other instructions perform certain control functions and do not deal with data bits. the microwire cycle ends when the cs signal is brought low. however during certain instructions, falling edge of the cs signal initiates an internal cycle (programming), and the device remains busy till the completion of the internal cycle. each of the 10 instructions is explained in detail in the following sections. memory instructions following five instructions, read, wen, write, wrall and wds are specific to operations intended for memory array. the pre pin should be held low during these instructions. 1) read and sequential read (read) read instruction allows data to be read from a selected location in the memory array. input information (start bit, opcode and address) for this instruction should be issued as listed under table1. upon receiving a valid input information, decoding of the opcode and the address is made, followed by data transfer from the selected memory location into a 16-bit serial-out shift register. this 16-bit data is then shifted out on the do pin. d15 bit (msb) is shifted out first and d0 bit (lsb) is shifted out last. a dummy-bit (logical 0) precedes this 16-bit data output string. output data changes are initiated on the rising edge of the sk clock. after reading the 16-bit data, the cs signal can be brought low to end the read cycle. the pre pin should be held low during this cycle. refer read cycle diagram . this device also offers sequential memory read operation to allow reading of data from the additional memory locations instead of just one location. it is started in the same manner as normal read but the cycle is continued to read further data (instead of terminat- ing after reading the first 16-bit data). after providing 16-bit data, the device automatically increments the address pointer to the next location and continues to provide the data from that location. any number of locations can be read out in this manner, however, after reading out from the last location, the address pointer points back to the first location. if the cycle is continued further, data will be read from this first location onward. in this mode of read, the dummy-bit is present only when the very first data is read (like normal read cycle) and is not present on subsequent data reads. the pre pin should be held low during this cycle. refer sequen- tial read cycle diagram . 2) write enable (wen) when v cc is applied to the part, it powers up in the write disable (wds) state. therefore, all programming operations (for both memory array and protect register) must be preceded by a write enable (wen) instruction. once a write enable instruction is executed, programming remains enabled until a write disable (wds) instruction is executed or v cc is completely removed from the part. input information (start bit, opcode and address) for this wen instruction should be issued as listed under table1. the device becomes write-enabled at the end of this cycle when the cs signal is brought low. the pre pin should be held low during this cycle. execution of a read instruction is independent of wen instruction. refer write enable cycle diagram. 3) write (write) write instruction allows write operation to a specified location in the memory with a specified data. this instruction is valid only when the following are true: device is write-enabled (refer wen instruction) address of the write location is not write-protected pe pin is held high during this cycle pre pin should be held low during this cycle input information (start bit, opcode, address and data) for this write instruction should be issued as listed under table1. after inputting the last bit of data (d0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. the status of the internal programming cycle can be polled at any time by bringing the cs signal high again, after t cs interval. when cs signal is high, the do pin indicates the ready/busy status of the chip. do = logical 0 indicates that the programming is still in progress. do = logical 1 indicates that the programming is finished and the device is ready for another instruction. it is not required to provide the sk clock during this status polling. while the device is busy, it is recommended that no new instruction be issued. refer write cycle diagram. it is also recommended to follow this instruction (after the device becomes ready) with a write disable (wds) instruction to safeguard data against corruption due to spurious noise, inadvert- ent writes etc. 4) write all (wrall) write all (wrall) instruction is similar to the write instruction except that wrall instruction will simultaneously program all memory locations with the data pattern specified in the instruction. this instruction is valid only when the following are true: protect register has been cleared (refer prclear instruction) device is write-enabled (refer wen instruction) pe pin is held high during this cycle pre pin should be held low during this cycle input information (start bit, opcode, address and data) for this wrall instruction should be issued as listed under table1. after inputting the last bit of data (d0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer write all cycle diagram.
7 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read 5) write disable (wds) write disable (wds) instruction disables all programming opera- tions and is recommended to follow all programming operations. executing this instruction after a valid write instruction would protect against accidental data disturb due to spurious noise, glitches, inadvertent writes etc. input information (start bit, opcode and address) for this wds instruction should be issued as listed under table1. the device becomes write-disabled at the end of this cycle when the cs signal is brought low. execution of a read instruction is independent of wds instruction. refer write disable cycle diagram. protect register instructions following five instructions, prread, pren, prclear, prwrite and prds are specific to operations intended for protect register. the pre pin should be held high during these instructions. 1) protect register read (prread) this instruction reads the content of the internal protect register. content of this register is 6-bit wide and is the starting address of the write-protected section of the memory array. all memory locations greater than or equal to this address are write-protected. input information (start bit, opcode and address) for this prread instruction should be issued as listed under table1. upon receiv- ing a valid input information, decoding of the opcode and the address is made, followed by data transfer (address information) from the protect register. this 6-bit data is then shifted out on the do pin with the msb first and the lsb last. like the read instruction a dummy-bit (logical 0) precedes this 6-bit data output string. output data changes are initiated on the rising edge of the sk clock. after reading the 6-bit data, the cs signal can be brought low to end the prread cycle. the pre pin should be held high during this cycle. refer protect register read cycle diagram. though the content of this register is 6-bit wide, only the last 4 bits (lsb) are valid for nm93cs06 device. 2) protect register enable (pren) this instruction is required to enable prclear, prwrite and prds instructions and should be executed prior to executing prclear, prwrite and prds instructions. however, this pren instruction is enabled (valid) only the following are true device is write-enabled (refer wen instruction) pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this pren instruction should be issued as listed under table1. the protect register becomes enabled for prclear, prwrite and prds instructions at the end of this cycle when the cs signal is brought low. note that this pren instruction must immediately precede a prclear, prwrite or prds instruction. in other words, no other instruction should be executed between a pren instruction and a prclear, prwrite or prds instruction. refer protect register enable cycle diagram. 3) protect register clear (prclear) this instruction clears the content of the protect register and therefore enables write operations (write or wrall) to all memory locations. executing this instruction will program the content of the protect register with a pattern of all 1s. however, in this case, write operation to the last memory address (0x001111) is still enabled. prclear instruction is enabled (valid) only when the following are true: pren instruction was executed immediately prior to prclear instruction pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this prclear instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed clear cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal clear cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer protect register clear cycle diagram. 4) protect register write (prwrite) this instruction is used to write the starting address of the memory section to be write-protected into the protect register. after the execution of prwrite instruction, all memory locations greater than or equal to this address are write-protected. prwrite instruction is enabled (valid) only the following are true: prclear instruction was executed first (to clear the protect register) pren instruction was executed immediately prior to prwrite instruction pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this prwrite instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer protect register write cycle diagram. 5) protect register disable (prds) unlike all other instructions, this instruction is a one-time-only instruction which when executed permanently write-protects the protect register and renders it unalterable in the future. this instruction is useful to safeguard vital data (typically read only data) in the memory against any possible corruption. prds instruction is enabled (valid) only the following are true: pren instruction was executed immediately prior to prds instruction pe pin is held high during this cycle pre pin is held high during this cycle
8 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read input information (start bit, opcode and address) for this prds instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. the protect register is permanently write-protected at the end of this cycle. refer protect register disable cycle diagram. clearing of ready/busy status when programming is in progress, the data-out pin will display the programming status as either busy (low) or ready (high) when cs is brought high (do output will be tri-stated when cs is low). to restate, during programming, the cs pin may be brought high and low any number of times to view the programming status without affecting the programming operation. once programming is completed (output in ready state), the output is cleared (returned to normal tri-state condition) by clocking in a start bit. after the start bit is clocked in, the output will return to a tri-stated condition. when clocked in, this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. refer clearing ready status diagram. related document application note: an758 - using fairchild s microwire ee- prom.
9 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read t css synchronous data timing cs sk pre pe di do (data read) do (status read) valid status t pres t pes t dis t dih t pd t dh t sv t skh t skl t csh t preh t peh t df t df t pd valid input valid input valid output valid output t sks cs sk di do high - z dummy bit 1 1 0 a5 a4 a1 a0 pre 0 d15 d1 d0 t cs normal read cycle (read) address bits(6) start bit opcode bits(2) 93cs06: address bits pattern -> x-x-a3-a2-a1-a0; (x -> don't care, can be 0 or 1); (a3-a0 -> user defined) pe timing diagrams cs sk di do high - z dummy bit data(n) 1 1 0 a5 a0 pre 0 d15 d0 d15 d0 d15 d0 t cs sequential read cycle (pre = 0; pe = x) data(n+1) data(n+2) address bits(6) start bit opcode bits(2) 93cs06: address bits pattern -> x-x-a3-a2-a1-a0; (x -> don't care, can be 0 or 1); (a3-a0 -> user defined)
10 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read timing diagrams (continued) address bits(6) cs pe sk di do high - z write disable cycle (wds) start bit 93cs06: address bits pattern -> 0-0-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a5 a4 a1 a0 pre t cs address bits(6) data bits(16) cs pe sk di do high - z t cs write cycle (write) start bit 93cs06: address bits pattern -> x-x-a3-a2-a1-a0; (x -> don't care, can be 0 or 1); (a3-a0 -> user defined) data bits pattern -> user defined opcode bits(2) 1 0 1 a5 a4 a1 a0 d15 d14 d1 d0 pre busy ready t wp address bits(6) cs pe sk di do high - z write enable cycle (wen) start bit 93cs06: address bits pattern -> 1-1-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a5 a4 a1 a0 pre t cs
11 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read timing diagrams (continued) cs sk di do high - z dummy bit 1 1 0 a5 a4 a1 a0 pre pe 0 d5 d1 d0 t cs protect register read cycle (prread) address bits(6) start bit opcode bits(2) 93cs06: address bits pattern -> x-x-x-x-x-x; (x -> don't care, can be 0 or 1) of the 6-bit output data(d5-d0), only d3 to d0 are valid and they correspond to a3 to a0 respectively. address bits(6) cs pe sk di do high - z protect register enable cycle (pren) start bit 93cs06: address bits pattern -> 1-1-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a5 a4 a1 a0 pre t cs address bits(6) data bits(16) cs pe sk di do high - z t cs write all cycle (wrall) start bit 93cs06: address bits pattern -> 0-1-x-x-x-x; (x -> don't care, can be 0 or 1) data bits pattern -> user defined opcode bits(2) 1 0 0 a5 a4 a1 a0 d15 d14 d1 d0 pre busy ready t wp
12 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read timing diagrams (continued) address bits(6) cs pe sk di do high - z t cs protect register write cycle (prwrite) start bit 93cs06: address bits pattern -> x-x-a3-a2-a1-a0; (x -> don't care, can be 0 or 1); (a3-a0 -> user defined) opcode bits(2) 1 0 1 a5 a4 a1 a0 pre busy ready t wp address bits(6) cs pe sk di do high - z t cs protect register disable cycle (prds) start bit 93cs06: address bits pattern -> 0-0-0-0-0-0 opcode bits(2) 1 0 0 a5 a4 a1 a0 pre busy ready t wp address bits(6) cs pe sk di do high - z t cs protect register clear cycle (prclear) start bit 93cs06: address bits pattern -> 1-1-1-1-1-1 opcode bits(2) 1 1 1 a5 a4 a1 a0 pre busy ready t wp
13 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read timing diagrams (continued) cs pe sk di do high - z high - z clearing ready status start bit note: this start bit can also be part of a next instruction. hence the cycle can be continued(instead of getting terminated, as shown) as if a new instruction is being issued. pre busy ready
14 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read molded package, small outline, 0.15 wide, 8-lead (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
15 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read 8-pin molded tssop, jedec (mt8) package number mtc08 physical dimensions inches (millimeters) unless otherwise noted 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
16 www.fairchildsemi.com nm93cs06 rev. f.2 nm93cs06 (microwire bus interface) 256-bit serial eeprom with data protect and sequential read physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read february 2000 ?1999 fairchild semiconductor corporation nm93cs46 (microwire? bus interface) 1024-bit serial eeprom with data protect and sequential read general description nm93cs46 is a 1024-bit cmos non-volatile eeprom organized as 64 x 16-bit array. this device features microwire interface which is a 4-wire serial bus with chipselect (cs), clock (sk), data input (di) and data output (do) signals. this interface is compat- ible to many of standard microcontrollers and microprocessors. nm93cs46 offers programmable write protection to the memory array using a special register called protect register. selected memory locations can be protected against write by programming this protect register with the address of the first memory location to be protected (all locations greater than or equal to this first address are then protected from further change). additionally, this address can be ?ermanently locked?into the device, making all future attempts to change data impossible. in addition this device features ?equential read? by which, entire memory can be read in one cycle instead of multiple single byte read cycles. there are 10 instructions implemented on the nm93cs46, 5 of which are for memory operations and the remaining 5 are for protect register operations. this device is fabricated using fairchild semiconduc- tor floating-gate cmos process for high reliability, high endurance and low power consumption. ?z?and ??versions of nm93cs46 offer very low standby current making them suitable for low power applications. this device is offered in both so and tssop packages for small space considerations. functional diagram features wide v cc 2.7v - 5.5v programmable write protection sequential register read typical active current of 200 a 10 a standby current typical 1 a standby current typical (l) 0.1 a standby current typical (lz) no erase instruction required before write instruction self timed write cycle device status during programming cycles 40 year data retention endurance: 1,000,000 data changes packages available: 8-pin so, 8-pin dip, 8-pin tssop instruction decoder control logic and clock generators comparator and write enable high voltage generator and program timer instruction register address register protect register eeprom array read/write amps data in/out register 16 bits decoder 16 16 data out buffer pre pe cs sk di do v ss v cc
2 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read connection diagram dual-in-line package (n) 8Cpin so (m8) and 8Cpin tssop (mt8) top view package number n08e, m08a and mtc08 pin names cs chip select sk serial data clock di serial data input do serial data output gnd ground pe program enable pre protect register enable v cc power supply ordering information nm 93 cs xx t lz e xxx letter description package n 8-pin dip m8 8-pin so mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current blank normal pin out t rotated pin out density 46 1024 bits c cmos cs data protect and sequential read interface 93 microwire fairchild memory prefix v cc pe gnd cs sk di do 1 2 3 4 8 7 6 5 pre pe do di pre v cc cs sk 1 2 3 4 8 7 6 5 gnd normal pinout rotated pinout
3 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm93cs46 0 c to +70 c nm93cs46e -40 c to +85 c nm93cs46v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics v cc = 4.5v to 5.5v unless otherwise specified symbolparameter conditions min max units i cca operating current cs = v ih , sk=1.0 mhz 1 ma i ccs standby current cs = v il 50 a i il input leakage v in = 0v to v cc -1 a i ol output leakage (note 2) v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v ol1 output low voltage i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = -400 a 2.4 v ol2 output low voltage i ol = 10 a 0.2 v v oh2 output high voltage i oh = -10 av cc - 0.2 f sk sk clock frequency (note 3) 1 mhz t skh sk high time 0 c to +70 c 250 ns -40 c to +125 c 300 t skl sk low time 250 ns t sks sk setup time 50 ns t cs minimum cs low time (note 4) 250 ns t css cs setup time 100 ns t pres pre setup time 50 ns t dh do hold time 70 ns t pes pe setup time 50 ns t dis di setup time 100 ns t csh cs hold time 0 ns t peh pe hold time 250 ns t preh pre hold time 50 ns t dih di hold time 20 ns t pd output delay 500 ns t sv cs to status valid 500 ns t df cs to do in hi-z cs = v il 100 ns t wp write cycle time 10 ms
4 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm93cs46l/lz 0 c to +70 c nm93cs46le/lze -40 c to +85 c nm93cs46lv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 5.5v dc and ac electrical characteristics v cc = 2.7v to 5.5v unless otherwise specified symbolparameter conditions min max units i cca operating current cs = v ih , sk=1.0 mhz 1 ma i ccs standby current cs = v il l 10 a lz (2.7v to 4.5v) 1 a i il input leakage v in = 0v to v cc 1 a i ol output leakage (note 2) v il input low voltage -0.1 0.15v cc v v ih input high voltage 0.8v cc v cc +1 v ol output low voltage i ol = 10 a 0.1v cc v v oh output high voltage i oh = -10 a 0.9v cc f sk sk clock frequency (note 3) 0 250 khz t skh sk high time 1 s t skl sk low time 1 s t sks sk setup time 0.2 s t cs minimum cs low time (note 4) 1 s t css cs setup time 0.2 s t pres pre setup time 50 ns t dh do hold time 70 ns t pes pe setup time 50 ns t dis di setup time 0.4 s t csh cs hold time 0 ns t peh pe hold time 250 ns t preh pre hold time 50 ns t dih di hold time 0.4 s t pd output delay 2 s t sv cs to status valid 1 s t df cs to do in hi-z cs = v il 0.4 s t wp write cycle time 15 ms capacitance t a = 25 c, f = 1 mhz (note 5) symboltest typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20na range. note 3 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 4 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagram on the following page.) note 5 : this parameter is periodically sampled and not 100% tested. ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v 0.3v/1.8v 1.0v 0.8v/1.5v 10 a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v 2.1ma/-0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf)
5 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read pin description chip select (cs) this is an active high input pin to nm93cs46 eeprom (the device) and is generated by a master that is controlling the device. a high level on this pin selects the device and a low level deselects the device. all serial communications with the device is enabled only when this pin is held high. however this pin cannot be permanently tied high, as a rising edge on this signal is required to reset the internal state-machine to accept a new cycle and a falling edge to initiate an internal programming after a write cycle. all activity on the sk, di and do pins are ignored while cs is held low. serial clock (sk) this is an input pin to the device and is generated by the master that is controlling the device. this is a clock signal that synchronizes the communication between a master and the device. all input informa- tion (di) to the device is latched on the rising edge of this clock input, while output data (do) from the device is driven from the rising edge of this clock input. this pin is gated by cs signal. serial input (di) this is an input pin to the device and is generated by the master that is controlling the device. the master transfers input informa- tion (start bit, opcode bits, array addresses and data) serially via this pin into the device. this input information is latched on the rising edge of the sck. this pin is gated by cs signal. serial output (do) this is an output pin from the device and is used to transfer output data via this pin to the controlling master. output data is serially shifted out on this pin from the rising edge of the sck. this pin is active only when the device is selected. protect register enable (pre) this is an active high input pin to the device and is used to distinguish operations to memory array and operations to protect register. when this pin is held low, operations to the memory array are enabled. when this pin is held high, operations to the protect register are enabled. this pin operates in conjunction with pe pin. refer table1 for functional matrix of this pin for various operations. program enable (pe) this is an active high input pin to the device and is used to enable operations, that are write in nature, to the memory array and to the protect register. when this pin is held high, operations that are write in nature are enabled. when this pin is held low, operations that are write in nature are disabled. this pin operates in conjunction with pre pin. refer table1 for functional matrix of this pin for various operations. microwire interface a typical communication on the microwire bus is made through the cs, sk, di and do signals. to facilitate various operations on the memory array and on the protect register, a set of 10 instructions are implemented on nm93cs46. the format of each instruction is listed in table 1. instruction each of the above 10 instructions is explained under individual instruction descriptions. start bit this is a 1-bit field and is the first bit that is clocked into the device when a microwire cycle starts. this bit has to be 1 for a valid cycle to begin. any number of preceding 0 can be clocked into the device before clocking a 1 . opcode this is a 2-bit field and should immediately follow the start bit. these two bits (along with pre, pe signals and 2 msb of address field) select a particular instruction to be executed. address field this is a 6-bit field and should immediately follow the opcode bits. in nm93cs46, all 6 bits are used for address decoding during read, write and prwrite instructions. during all other in- structions (with the exception of prread), the msb 2 bits are used to decode instruction (along with opcode bits, pre and pe signals). data field this is a 16-bit field and should immediately follow the address bits. only the write and wrall instructions require this field. d15 (msb) is clocked first and d0 (lsb) is clocked last (both during writes as well as reads). table 1. instruction set instruction start bit opcode field address field data field pre pin pe pin read 1 10 a5 a4 a3 a2 a1 a0 0 x wen 1 00 1 1xxxx 0 1 write 1 01 a5 a4 a3 a2 a1 a0 d15-d0 0 1 wrall 1 00 0 1 xxxx d15-d0 0 1 wds 1 00 0 0xxxx 0 x prread 1 10 x x xxxx 1 x pren 1 00 1 1 xxxx 1 1 prclear 1 11 111111 1 1 prwrite 1 01 a5 a4 a3 a2 a1 a0 1 1 prds 1 00 000000 1 1
6 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read functional description a typical microwire cycle starts by first selecting the device (bringing the cs signal high). once the device is selected, a valid start bit ( 1 ) should be issued to properly recognize the cycle. following this, the 2-bit opcode of appropriate instruction should be issued. after the opcode bits, the 6-bit address information should be issued. for certain instructions, some (or all) of these 6 bits are don t care values (can be 0 or 1 ), but they should still be issued. following the address information, depending on the instruction (write and wrall), 16-bit data is issued. other- wise, depending on the instruction (read and prread), the device starts to drive the output data on the do line. other instructions perform certain control functions and do not deal with data bits. the microwire cycle ends when the cs signal is brought low. however during certain instructions, falling edge of the cs signal initiates an internal cycle (programming), and the device remains busy till the completion of the internal cycle. each of the 10 instructions is explained in detail in the following sections. memory instructions following five instructions, read, wen, write, wrall and wds are specific to operations intended for memory array. the pre pin should be held low during these instructions. 1) read and sequential read (read) read instruction allows data to be read from a selected location in the memory array. input information (start bit, opcode and address) for this instruction should be issued as listed under table1. upon receiving a valid input information, decoding of the opcode and the address is made, followed by data transfer from the selected memory location into a 16-bit serial-out shift register. this 16-bit data is then shifted out on the do pin. d15 bit (msb) is shifted out first and d0 bit (lsb) is shifted out last. a dummy-bit (logical 0) precedes this 16-bit data output string. output data changes are initiated on the rising edge of the sk clock. after reading the 16-bit data, the cs signal can be brought low to end the read cycle. the pre pin should be held low during this cycle. refer read cycle diagram . this device also offers sequential memory read operation to allow reading of data from the additional memory locations instead of just one location. it is started in the same manner as normal read but the cycle is continued to read further data (instead of terminat- ing after reading the first 16-bit data). after providing 16-bit data, the device automatically increments the address pointer to the next location and continues to provide the data from that location. any number of locations can be read out in this manner, however, after reading out from the last location, the address pointer points back to the first location. if the cycle is continued further, data will be read from this first location onward. in this mode of read, the dummy-bit is present only when the very first data is read (like normal read cycle) and is not present on subsequent data reads. the pre pin should be held low during this cycle. refer sequen- tial read cycle diagram . 2) write enable (wen) when v cc is applied to the part, it powers up in the write disable (wds) state. therefore, all programming operations (for both memory array and protect register) must be preceded by a write enable (wen) instruction. once a write enable instruction is executed, programming remains enabled until a write disable (wds) instruction is executed or v cc is completely removed from the part. input information (start bit, opcode and address) for this wen instruction should be issued as listed under table1. the device becomes write-enabled at the end of this cycle when the cs signal is brought low. the pre pin should be held low during this cycle. execution of a read instruction is independent of wen instruction. refer write enable cycle diagram. 3) write (write) write instruction allows write operation to a specified location in the memory with a specified data. this instruction is valid only when the following are true: device is write-enabled (refer wen instruction) address of the write location is not write-protected pe pin is held high during this cycle pre pin should be held low during this cycle input information (start bit, opcode, address and data) for this write instruction should be issued as listed under table1. after inputting the last bit of data (d0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. the status of the internal programming cycle can be polled at any time by bringing the cs signal high again, after t cs interval. when cs signal is high, the do pin indicates the ready/busy status of the chip. do = logical 0 indicates that the programming is still in progress. do = logical 1 indicates that the programming is finished and the device is ready for another instruction. it is not required to provide the sk clock during this status polling. while the device is busy, it is recommended that no new instruction be issued. refer write cycle diagram. it is also recommended to follow this instruction (after the device becomes ready) with a write disable (wds) instruction to safeguard data against corruption due to spurious noise, inadvert- ent writes etc. 4) write all (wrall) write all (wrall) instruction is similar to the write instruction except that wrall instruction will simultaneously program all memory locations with the data pattern specified in the instruction. this instruction is valid only when the following are true: protect register has been cleared (refer prclear instruction) device is write-enabled (refer wen instruction) pe pin is held high during this cycle pre pin should be held low during this cycle input information (start bit, opcode, address and data) for this wrall instruction should be issued as listed under table1. after inputting the last bit of data (d0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer write all cycle diagram.
7 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read 5) write disable (wds) write disable (wds) instruction disables all programming opera- tions and is recommended to follow all programming operations. executing this instruction after a valid write instruction would protect against accidental data disturb due to spurious noise, glitches, inadvertent writes etc. input information (start bit, opcode and address) for this wds instruction should be issued as listed under table1. the device becomes write-disabled at the end of this cycle when the cs signal is brought low. execution of a read instruction is independent of wds instruction. refer write disable cycle diagram. protect register instructions following five instructions, prread, pren, prclear, prwrite and prds are specific to operations intended for protect register. the pre pin should be held high during these instructions. 1) protect register read (prread) this instruction reads the content of the internal protect register. content of this register is 6-bit wide and is the starting address of the write-protected section of the memory array. all memory locations greater than or equal to this address are write-protected. input information (start bit, opcode and address) for this prread instruction should be issued as listed under table1. upon receiv- ing a valid input information, decoding of the opcode and the address is made, followed by data transfer (address information) from the protect register. this 6-bit data is then shifted out on the do pin with the msb first and the lsb last. like the read instruction a dummy-bit (logical 0) precedes this 6-bit data output string. output data changes are initiated on the rising edge of the sk clock. after reading the 6-bit data, the cs signal can be brought low to end the prread cycle. the pre pin should be held high during this cycle. refer protect register read cycle diagram. 2) protect register enable (pren) this instruction is required to enable prclear, prwrite and prds instructions and should be executed prior to executing prclear, prwrite and prds instructions. however, this pren instruction is enabled (valid) only the following are true device is write-enabled (refer wen instruction) pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this pren instruction should be issued as listed under table1. the protect register becomes enabled for prclear, prwrite and prds instructions at the end of this cycle when the cs signal is brought low. note that this pren instruction must immediately precede a prclear, prwrite or prds instruction. in other words, no other instruction should be executed between a pren instruction and a prclear, prwrite or prds instruction. refer protect register enable cycle diagram. 3) protect register clear (prclear) this instruction clears the content of the protect register and therefore enables write operations (write or wrall) to all memory locations. executing this instruction will program the content of the protect register with a pattern of all 1s. however, in this case, write operation to the last memory address (0x111111) is still enabled. prclear instruction is enabled (valid) only when the following are true: pren instruction was executed immediately prior to prclear instruction pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this prclear instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed clear cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal clear cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer protect register clear cycle diagram. 4) protect register write (prwrite) this instruction is used to write the starting address of the memory section to be write-protected into the protect register. after the execution of prwrite instruction, all memory locations greater than or equal to this address are write-protected. prwrite instruction is enabled (valid) only the following are true: prclear instruction was executed first (to clear the protect register) pren instruction was executed immediately prior to prwrite instruction pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this prwrite instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer protect register write cycle diagram. 5) protect register disable (prds) unlike all other instructions, this instruction is a one-time-only instruction which when executed permanently write-protects the protect register and renders it unalterable in the future. this instruction is useful to safeguard vital data (typically read only data) in the memory against any possible corruption. prds instruction is enabled (valid) only the following are true: pren instruction was executed immediately prior to prds instruction pe pin is held high during this cycle pre pin is held high during this cycle
8 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read input information (start bit, opcode and address) for this prds instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. the protect register is permanently write-protected at the end of this cycle. refer protect register disable cycle diagram. clearing of ready/busy status when programming is in progress, the data-out pin will display the programming status as either busy (low) or ready (high) when cs is brought high (do output will be tri-stated when cs is low). to restate, during programming, the cs pin may be brought high and low any number of times to view the programming status without affecting the programming operation. once programming is completed (output in ready state), the output is cleared (returned to normal tri-state condition) by clocking in a start bit. after the start bit is clocked in, the output will return to a tri-stated condition. when clocked in, this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. refer clearing ready status diagram. related document application note: an758 - using fairchild s microwire ee- prom.
9 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read t css synchronous data timing cs sk pre pe di do (data read) do (status read) valid status t pres t pes t dis t dih t pd t dh t sv t skh t skl t csh t preh t peh t df t df t pd valid input valid input valid output valid output t sks cs sk di do high - z dummy bit 1 1 0 a5 a4 a1 a0 pre 0 d15 d1 d0 t cs normal read cycle (read) address bits(6) start bit opcode bits(2) 93cs46: address bits pattern -> user defined pe timing diagrams cs sk di do high - z dummy bit data(n) 1 1 0 a5 a0 pre 0 d15 d0 d15 d0 d15 d0 t cs sequential read cycle (pre = 0; pe = x) data(n+1) data(n+2) address bits(6) start bit opcode bits(2) 93cs46: address bits pattern -> user defined
10 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read timing diagrams (continued) address bits(6) cs pe sk di do high - z write disable cycle (wds) start bit 93cs46: address bits pattern -> 0-0-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a5 a4 a1 a0 pre t cs address bits(6) data bits(16) cs pe sk di do high - z t cs write cycle (write) start bit 93cs46: address bits pattern -> user defined data bits pattern -> user defined opcode bits(2) 1 0 1 a5 a4 a1 a0 d15 d14 d1 d0 pre busy ready t wp address bits(6) cs pe sk di do high - z write enable cycle (wen) start bit 93cs46: address bits pattern -> 1-1-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a5 a4 a1 a0 pre t cs
11 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read timing diagrams (continued) cs sk di do high - z dummy bit 1 1 0 a5 a4 a1 a0 pre pe 0 d5 d1 d0 t cs protect register read cycle (prread) address bits(6) start bit opcode bits(2) 93cs46: address bits pattern -> x-x-x-x-x-x; (x -> don't care, can be 0 or 1) address bits(6) cs pe sk di do high - z protect register enable cycle (pren) start bit 93cs46: address bits pattern -> 1-1-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a5 a4 a1 a0 pre t cs address bits(6) data bits(16) cs pe sk di do high - z t cs write all cycle (wrall) start bit 93cs46: address bits pattern -> 0-1-x-x-x-x; (x -> don't care, can be 0 or 1) data bits pattern -> user defined opcode bits(2) 1 0 0 a5 a4 a1 a0 d15 d14 d1 d0 pre busy ready t wp
12 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read timing diagrams (continued) address bits(6) cs pe sk di do high - z t cs protect register write cycle (prwrite) start bit 93cs46: address bits pattern -> user defined opcode bits(2) 1 0 1 a5 a4 a1 a0 pre busy ready t wp address bits(6) cs pe sk di do high - z t cs protect register disable cycle (prds) start bit 93cs46: address bits pattern -> 0-0-0-0-0-0 opcode bits(2) 1 0 0 a5 a4 a1 a0 pre busy ready t wp address bits(6) cs pe sk di do high - z t cs protect register clear cycle (prclear) start bit 93cs46: address bits pattern -> 1-1-1-1-1-1 opcode bits(2) 1 1 1 a5 a4 a1 a0 pre busy ready t wp
13 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read timing diagrams (continued) cs pe sk di do high - z high - z clearing ready status start bit note: this start bit can also be part of a next instruction. hence the cycle can be continued(instead of getting terminated, as shown) as if a new instruction is being issued. pre busy ready
14 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read molded package, small outline, 0.15 wide, 8-lead (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
15 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read 8-pin molded tssop, jedec (mt8) package number mtc08 physical dimensions inches (millimeters) unless otherwise noted 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
16 www.fairchildsemi.com nm93cs46 rev. f.2 nm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read february 2000 ?1999 fairchild semiconductor corporation nm93cs56 (microwire? bus interface) 2048-bit serial eeprom with data protect and sequential read general description nm93cs56 is a 2048-bit cmos non-volatile eeprom organized as 128 x 16-bit array. this device features microwire interface which is a 4-wire serial bus with chipselect (cs), clock (sk), data input (di) and data output (do) signals. this interface is compat- ible to many of standard microcontrollers and microprocessors. nm93cs56 offers programmable write protection to the memory array using a special register called protect register. selected memory locations can be protected against write by programming this protect register with the address of the first memory location to be protected (all locations greater than or equal to this first address are then protected from further change). additionally, this address can be ?ermanently locked?into the device, making all future attempts to change data impossible. in addition this device features ?equential read? by which, entire memory can be read in one cycle instead of multiple single byte read cycles. there are 10 instructions implemented on the nm93cs56, 5 of which are for memory operations and the remaining 5 are for protect register operations. this device is fabricated using fairchild semiconduc- tor floating-gate cmos process for high reliability, high endurance and low power consumption. ?z?and ??versions of nm93cs56 offer very low standby current making them suitable for low power applications. this device is offered in both so and tssop packages for small space considerations. functional diagram features wide v cc 2.7v - 5.5v programmable write protection sequential register read typical active current of 200 a 10 a standby current typical 1 a standby current typical (l) 0.1 a standby current typical (lz) no erase instruction required before write instruction self timed write cycle device status during programming cycles 40 year data retention endurance: 1,000,000 data changes packages available: 8-pin so, 8-pin dip, 8-pin tssop instruction decoder control logic and clock generators comparator and write enable high voltage generator and program timer instruction register address register protect register eeprom array read/write amps data in/out register 16 bits decoder 16 16 data out buffer pre pe cs sk di do v ss v cc
2 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read connection diagram dual-in-line package (n) 8Cpin so (m8) and 8Cpin tssop (mt8) top view package number n08e, m08a and mtc08 pin names cs chip select sk serial data clock di serial data input do serial data output gnd ground pe program enable pre protect register enable v cc power supply ordering information nm 93 cs xx lz e xxx letter description package n 8-pin dip m8 8-pin so mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current density 56 2048 bits c cmos cs data protect and sequential read interface 93 microwire fairchild memory prefix v cc pe gnd cs sk di do 1 2 3 4 8 7 6 5 pre
3 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm93cs56 0 c to +70 c nm93cs56e -40 c to +85 c nm93cs56v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics v cc = 4.5v to 5.5v unless otherwise specified symbol parameter conditions min max units i cca operating current cs = v ih , sk=1.0 mhz 1 ma i ccs standby current cs = v il 50 a i il input leakage v in = 0v to v cc -1 a i ol output leakage (note 2) v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v ol1 output low voltage i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = -400 a 2.4 v ol2 output low voltage i ol = 10 a 0.2 v v oh2 output high voltage i oh = -10 av cc - 0.2 f sk sk clock frequency (note 3) 1 mhz t skh sk high time 0 c to +70 c 250 ns -40 c to +125 c 300 t skl sk low time 250 ns t sks sk setup time 50 ns t cs minimum cs low time (note 4) 250 ns t css cs setup time 100 ns t pres pre setup time 50 ns t dh do hold time 70 ns t pes pe setup time 50 ns t dis di setup time 100 ns t csh cs hold time 0 ns t peh pe hold time 250 ns t preh pre hold time 50 ns t dih di hold time 20 ns t pd output delay 500 ns t sv cs to status valid 500 ns t df cs to do in hi-z cs = v il 100 ns t wp write cycle time 10 ms
4 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm93cs56l/lz 0 c to +70 c nm93cs56le/lze -40 c to +85 c nm93cs56lv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 5.5v dc and ac electrical characteristics v cc = 2.7v to 5.5v unless otherwise specified symbol parameter conditions min max units i cca operating current cs = v ih , sk=1.0 mhz 1 ma i ccs standby current cs = v il l 10 a lz (2.7v to 4.5v) 1 a i il input leakage v in = 0v to v cc 1 a i ol output leakage (note 2) v il input low voltage -0.1 0.15v cc v v ih input high voltage 0.8v cc v cc +1 v ol output low voltage i ol = 10 a 0.1v cc v v oh output high voltage i oh = -10 a 0.9v cc f sk sk clock frequency (note 3) 0 250 khz t skh sk high time 1 s t skl sk low time 1 s t sks sk setup time 0.2 s t cs minimum cs low time (note 4) 1 s t css cs setup time 0.2 s t pres pre setup time 50 ns t dh do hold time 70 ns t pes pe setup time 50 ns t dis di setup time 0.4 s t csh cs hold time 0 ns t peh pe hold time 250 ns t preh pre hold time 50 ns t dih di hold time 0.4 s t pd output delay 2 s t sv cs to status valid 1 s t df cs to do in hi-z cs = v il 0.4 s t wp write cycle time 15 ms capacitance t a = 25 c, f = 1 mhz (note 5) symbol test typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20na range. note 3 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 4 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagram on the following page.) note 5 : this parameter is periodically sampled and not 100% tested. ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v 0.3v/1.8v 1.0v 0.8v/1.5v 10 a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v 2.1ma/-0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf)
5 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read pin description chip select (cs) this is an active high input pin to nm93cs56 eeprom (the device) and is generated by a master that is controlling the device. a high level on this pin selects the device and a low level deselects the device. all serial communications with the device is enabled only when this pin is held high. however this pin cannot be permanently tied high, as a rising edge on this signal is required to reset the internal state-machine to accept a new cycle and a falling edge to initiate an internal programming after a write cycle. all activity on the sk, di and do pins are ignored while cs is held low. serial clock (sk) this is an input pin to the device and is generated by the master that is controlling the device. this is a clock signal that synchronizes the communication between a master and the device. all input informa- tion (di) to the device is latched on the rising edge of this clock input, while output data (do) from the device is driven from the rising edge of this clock input. this pin is gated by cs signal. serial input (di) this is an input pin to the device and is generated by the master that is controlling the device. the master transfers input informa- tion (start bit, opcode bits, array addresses and data) serially via this pin into the device. this input information is latched on the rising edge of the sck. this pin is gated by cs signal. serial output (do) this is an output pin from the device and is used to transfer output data via this pin to the controlling master. output data is serially shifted out on this pin from the rising edge of the sck. this pin is active only when the device is selected. protect register enable (pre) this is an active high input pin to the device and is used to distinguish operations to memory array and operations to protect register. when this pin is held low, operations to the memory array are enabled. when this pin is held high, operations to the protect register are enabled. this pin operates in conjunction with pe pin. refer table1 for functional matrix of this pin for various operations. program enable (pe) this is an active high input pin to the device and is used to enable operations, that are write in nature, to the memory array and to the protect register. when this pin is held high, operations that are write in nature are enabled. when this pin is held low, operations that are write in nature are disabled. this pin operates in conjunction with pre pin. refer table1 for functional matrix of this pin for various operations. microwire interface a typical communication on the microwire bus is made through the cs, sk, di and do signals. to facilitate various operations on the memory array and on the protect register, a set of 10 instructions are implemented on nm93cs56. the format of each instruction is listed in table 1. instruction each of the above 10 instructions is explained under individual instruction descriptions. start bit this is a 1-bit field and is the first bit that is clocked into the device when a microwire cycle starts. this bit has to be 1 for a valid cycle to begin. any number of preceding 0 can be clocked into the device before clocking a 1 . opcode this is a 2-bit field and should immediately follow the start bit. these two bits (along with pre, pe signals and 2 msb of address field) select a particular instruction to be executed. address field this is a 8-bit field and should immediately follow the opcode bits. in nm93cs56, only the lsb 7 bits are used for address decoding during read, write and prwrite instructions. during these three instructions (read, write and prwrite), the msb is don t care (can be 0 or 1). during all other instructions (with the exception of prread), the msb 2 bits are used to decode instruction (along with opcode bits, pre and pe signals). data field this is a 16-bit field and should immediately follow the address bits. only the write and wrall instructions require this field. d15 (msb) is clocked first and d0 (lsb) is clocked last (both during writes as well as reads). table 1. instruction set instruction start bit opcode field address field data field pre pin pe pin read 1 10 x a6 a5 a4 a3 a2 a1 a0 0 x wen 1 00 1 1xxxxxx 0 1 write 1 01 x a6 a5 a4 a3 a2 a1 a0 d15-d0 0 1 wrall 1 00 0 1 x x xxxx d15-d0 0 1 wds 1 00 0 0xxxxxx 0 x prread 1 10 xxxxxxxx 1 x pren 1 00 1 1 x x xxxx 1 1 prclear 1 11 11111111 1 1 prwrite 1 01 x a6 a5 a4 a3 a2 a1 a0 1 1 prds 1 00 00000000 1 1
6 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read functional description a typical microwire cycle starts by first selecting the device (bringing the cs signal high). once the device is selected, a valid start bit ( 1 ) should be issued to properly recognize the cycle. following this, the 2-bit opcode of appropriate instruction should be issued. after the opcode bits, the 8-bit address information should be issued. for certain instructions, some (or all) of these 8 bits are don t care values (can be 0 or 1 ), but they should still be issued. following the address information, depending on the instruction (write and wrall), 16-bit data is issued. other- wise, depending on the instruction (read and prread), the device starts to drive the output data on the do line. other instructions perform certain control functions and do not deal with data bits. the microwire cycle ends when the cs signal is brought low. however during certain instructions, falling edge of the cs signal initiates an internal cycle (programming), and the device remains busy till the completion of the internal cycle. each of the 10 instructions is explained in detail in the following sections. memory instructions following five instructions, read, wen, write, wrall and wds are specific to operations intended for memory array. the pre pin should be held low during these instructions. 1) read and sequential read (read) read instruction allows data to be read from a selected location in the memory array. input information (start bit, opcode and address) for this instruction should be issued as listed under table1. upon receiving a valid input information, decoding of the opcode and the address is made, followed by data transfer from the selected memory location into a 16-bit serial-out shift register. this 16-bit data is then shifted out on the do pin. d15 bit (msb) is shifted out first and d0 bit (lsb) is shifted out last. a dummy-bit (logical 0) precedes this 16-bit data output string. output data changes are initiated on the rising edge of the sk clock. after reading the 16-bit data, the cs signal can be brought low to end the read cycle. the pre pin should be held low during this cycle. refer read cycle diagram . this device also offers sequential memory read operation to allow reading of data from the additional memory locations instead of just one location. it is started in the same manner as normal read but the cycle is continued to read further data (instead of terminat- ing after reading the first 16-bit data). after providing 16-bit data, the device automatically increments the address pointer to the next location and continues to provide the data from that location. any number of locations can be read out in this manner, however, after reading out from the last location, the address pointer points back to the first location. if the cycle is continued further, data will be read from this first location onward. in this mode of read, the dummy-bit is present only when the very first data is read (like normal read cycle) and is not present on subsequent data reads. the pre pin should be held low during this cycle. refer sequen- tial read cycle diagram . 2) write enable (wen) when v cc is applied to the part, it powers up in the write disable (wds) state. therefore, all programming operations (for both memory array and protect register) must be preceded by a write enable (wen) instruction. once a write enable instruction is executed, programming remains enabled until a write disable (wds) instruction is executed or v cc is completely removed from the part. input information (start bit, opcode and address) for this wen instruction should be issued as listed under table1. the device becomes write-enabled at the end of this cycle when the cs signal is brought low. the pre pin should be held low during this cycle. execution of a read instruction is independent of wen instruction. refer write enable cycle diagram. 3) write (write) write instruction allows write operation to a specified location in the memory with a specified data. this instruction is valid only when the following are true: device is write-enabled (refer wen instruction) address of the write location is not write-protected pe pin is held high during this cycle pre pin should be held low during this cycle input information (start bit, opcode, address and data) for this write instruction should be issued as listed under table1. after inputting the last bit of data (d0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. the status of the internal programming cycle can be polled at any time by bringing the cs signal high again, after t cs interval. when cs signal is high, the do pin indicates the ready/busy status of the chip. do = logical 0 indicates that the programming is still in progress. do = logical 1 indicates that the programming is finished and the device is ready for another instruction. it is not required to provide the sk clock during this status polling. while the device is busy, it is recommended that no new instruction be issued. refer write cycle diagram. it is also recommended to follow this instruction (after the device becomes ready) with a write disable (wds) instruction to safeguard data against corruption due to spurious noise, inadvert- ent writes etc. 4) write all (wrall) write all (wrall) instruction is similar to the write instruction except that wrall instruction will simultaneously program all memory locations with the data pattern specified in the instruction. this instruction is valid only when the following are true: protect register has been cleared (refer prclear instruction) device is write-enabled (refer wen instruction) pe pin is held high during this cycle pre pin should be held low during this cycle input information (start bit, opcode, address and data) for this wrall instruction should be issued as listed under table1. after inputting the last bit of data (d0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer write all cycle diagram.
7 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read 5) write disable (wds) write disable (wds) instruction disables all programming opera- tions and is recommended to follow all programming operations. executing this instruction after a valid write instruction would protect against accidental data disturb due to spurious noise, glitches, inadvertent writes etc. input information (start bit, opcode and address) for this wds instruction should be issued as listed under table1. the device becomes write-disabled at the end of this cycle when the cs signal is brought low. execution of a read instruction is independent of wds instruction. refer write disable cycle diagram. protect register instructions following five instructions, prread, pren, prclear, prwrite and prds are specific to operations intended for protect register. the pre pin should be held high during these instructions. 1) protect register read (prread) this instruction reads the content of the internal protect register. content of this register is 8-bit wide and is the starting address of the write-protected section of the memory array. all memory locations greater than or equal to this address are write-protected. input information (start bit, opcode and address) for this prread instruction should be issued as listed under table 1. upon receiving a valid input information, decoding of the opcode and the address is made, followed by data transfer (address information) from the protect register. this 8-bit data is then shifted out on the do pin with the msb first and the lsb last. like the read instruction a dummy-bit (logical 0) precedes this 8-bit data output string. output data changes are initiated on the rising edge of the sk clock. after reading the 8-bit data, the cs signal can be brought low to end the prread cycle. the pre pin should be held high during this cycle. refer protect register read cycle diagram. though the content of this register is 8-bit wide, only the last 7 bits (lsb) are valid for nm93cs56 device. 2) protect register enable (pren) this instruction is required to enable prclear, prwrite and prds instructions and should be executed prior to executing prclear, prwrite and prds instructions. however, this pren instruction is enabled (valid) only the following are true device is write-enabled (refer wen instruction) pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this pren instruction should be issued as listed under table1. the protect register becomes enabled for prclear, prwrite and prds instructions at the end of this cycle when the cs signal is brought low. note that this pren instruction must immediately precede a prclear, prwrite or prds instruction. in other words, no other instruction should be executed between a pren instruction and a prclear, prwrite or prds instruction. refer protect register enable cycle diagram. 3) protect register clear (prclear) this instruction clears the content of the protect register and therefore enables write operations (write or wrall) to all memory locations. executing this instruction will program the content of the protect register with a pattern of all 1s. however, in this case, write operation to the last memory address (0x01111111) is still enabled. prclear instruction is enabled (valid) only when the following are true: pren instruction was executed immediately prior to prclear instruction pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this prclear instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed clear cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal clear cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer protect register clear cycle diagram. 4) protect register write (prwrite) this instruction is used to write the starting address of the memory section to be write-protected into the protect register. after the execution of prwrite instruction, all memory locations greater than or equal to this address are write-protected. prwrite instruction is enabled (valid) only the following are true: prclear instruction was executed first (to clear the protect register) pren instruction was executed immediately prior to prwrite instruction pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this prwrite instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer protect register write cycle diagram. 5) protect register disable (prds) unlike all other instructions, this instruction is a one-time-only instruction which when executed permanently write-protects the protect register and renders it unalterable in the future. this instruction is useful to safeguard vital data (typically read only data) in the memory against any possible corruption. prds instruction is enabled (valid) only the following are true: pren instruction was executed immediately prior to prds instruction pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this prds
8 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. the protect register is permanently write-protected at the end of this cycle. refer protect register disable cycle diagram. clearing of ready/busy status when programming is in progress, the data-out pin will display the programming status as either busy (low) or ready (high) when cs is brought high (do output will be tri-stated when cs is low). to restate, during programming, the cs pin may be brought high and low any number of times to view the programming status without affecting the programming operation. once programming is completed (output in ready state), the output is cleared (returned to normal tri-state condition) by clocking in a start bit. after the start bit is clocked in, the output will return to a tri-stated condition. when clocked in, this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. refer clearing ready status diagram. related document application note: an758 - using fairchild s microwire ee- prom.
9 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read t css synchronous data timing cs sk pre pe di do (data read) do (status read) valid status t pres t pes t dis t dih t pd t dh t sv t skh t skl t csh t preh t peh t df t df t pd valid input valid input valid output valid output t sks cs sk di do high - z dummy bit 1 1 0 a7 a6 a1 a0 pre 0 d15 d1 d0 t cs normal read cycle (read) address bits(8) start bit opcode bits(2) 93cs56: address bits pattern -> x-a6-a5-a4-a3-a2-a1-a0; (x -> don't care, can be 0 or 1); ( a6-a0 -> user defined ) pe timing diagrams cs sk di do high - z dummy bit data(n) 1 1 0 a7 a0 pre 0 d15 d0 d15 d0 d15 d0 t cs sequential read cycle (pre = 0; pe = x) data(n+1) data(n+2) address bits(8) start bit opcode bits(2) 93cs56: address bits pattern ->x-a6-a5-a4-a3-a2-a1-a0; (x -> don't care, can be 0 or 1); ( a6-a0 -> user defined )
10 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read timing diagrams (continued) address bits(8) cs pe sk di do high - z write disable cycle (wds) start bit 93cs56: address bits pattern -> 0-0-x-x-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a7 a6 a1 a0 pre t cs address bits(8) data bits(16) cs pe sk di do high - z t cs write cycle (write) start bit 93cs56: address bits pattern -> x-a6-a5-a4-a3-a2-a1-a0; (x -> don't care, can be 0 or 1); ( a6-a0 -> user defined ) data bits pattern -> user defined opcode bits(2) 1 0 1 a7 a6 a1 a0 d15 d14 d1 d0 pre busy ready t wp address bits(8) cs pe sk di do high - z write enable cycle (wen) start bit 93cs56: address bits pattern -> 1-1-x-x-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a7 a6 a1 a0 pre t cs
11 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read timing diagrams (continued) cs sk di do high - z dummy bit 1 1 0 a7 a6 a1 a0 pre pe 0 d7 d1 d0 t cs protect register read cycle (prread) address bits(8) start bit opcode bits(2) 93cs56: address bits pattern -> x-x-x-x-x-x-x-x; (x -> don't care, can be 0 or 1) address bits(8) cs pe sk di do high - z protect register enable cycle (pren) start bit 93cs56: address bits pattern -> 1-1-x-x-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a7 a6 a1 a0 pre t cs address bits(8) data bits(16) cs pe sk di do high - z t cs write all cycle (wrall) start bit 93cs56: address bits pattern -> 0-1-x-x-x-x-x-x; (x -> don't care, can be 0 or 1) data bits pattern -> user defined opcode bits(2) 1 0 0 a7 a6 a1 a0 d15 d14 d1 d0 pre busy ready t wp
12 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read timing diagrams (continued) address bits(8) cs pe sk di do high - z t cs protect register write cycle (prwrite) start bit 93cs56: address bits pattern -> x-a6-a5-a4-a3-a2-a1-a0; (x -> don't care, can be 0 or 1); ( a6-a0 -> user defined ) opcode bits(2) 1 0 1 a7 a6 a1 a0 pre busy ready t wp address bits(8) cs pe sk di do high - z t cs protect register disable cycle (prds) start bit 93cs56: address bits pattern -> 0-0-0-0-0-0-0-0 opcode bits(2) 1 0 0 a7 a6 a1 a0 pre busy ready t wp address bits(8) cs pe sk di do high - z t cs protect register clear cycle (prclear) start bit 93cs56: address bits pattern -> 1-1-1-1-1-1-1-1 opcode bits(2) 1 1 1 a7 a6 a1 a0 pre busy ready t wp
13 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read timing diagrams (continued) cs pe sk di do high - z high - z clearing ready status start bit note: this start bit can also be part of a next instruction. hence the cycle can be continued(instead of getting terminated, as shown) as if a new instruction is being issued. pre busy ready
14 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read molded package, small outline, 0.15 wide, 8-lead (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
15 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read 8-pin molded tssop, jedec (mt8) package number mtc08 physical dimensions inches (millimeters) unless otherwise noted 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
16 www.fairchildsemi.com nm93cs56 rev. f.2 nm93cs56 (microwire bus interface) 2048-bit serial eeprom with data protect and sequential read physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read february 2000 ?1999 fairchild semiconductor corporation nm93cs66 (microwire? bus interface) 4096-bit serial eeprom with data protect and sequential read general description nm93cs66 is a 4096-bit cmos non-volatile eeprom organized as 256 x 16-bit array. this device features microwire interface which is a 4-wire serial bus with chipselect (cs), clock (sk), data input (di) and data output (do) signals. this interface is compat- ible to many of standard microcontrollers and microprocessors. nm93cs66 offers programmable write protection to the memory array using a special register called protect register. selected memory locations can be protected against write by programming this protect register with the address of the first memory location to be protected (all locations greater than or equal to this first address are then protected from further change). additionally, this address can be ?ermanently locked?into the device, making all future attempts to change data impossible. in addition this device features ?equential read? by which, entire memory can be read in one cycle instead of multiple single byte read cycles. there are 10 instructions implemented on the nm93cs66, 5 of which are for memory operations and the remaining 5 are for protect register operations. this device is fabricated using fairchild semiconduc- tor floating-gate cmos process for high reliability, high endurance and low power consumption. ?z?and ??versions of nm93cs66 offer very low standby current making them suitable for low power applications. this device is offered in both so and tssop packages for small space considerations. functional diagram features wide v cc 2.7v - 5.5v programmable write protection sequential register read typical active current of 200 a 10 a standby current typical 1 a standby current typical (l) 0.1 a standby current typical (lz) no erase instruction required before write instruction self timed write cycle device status during programming cycles 40 year data retention endurance: 1,000,000 data changes packages available: 8-pin so, 8-pin dip, 8-pin tssop instruction decoder control logic and clock generators comparator and write enable high voltage generator and program timer instruction register address register protect register eeprom array read/write amps data in/out register 16 bits decoder 16 16 data out buffer pre pe cs sk di do v ss v cc
2 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read connection diagram dual-in-line package (n) 8Cpin so (m8) and 8Cpin tssop (mt8) top view package number n08e, m08a and mtc08 pin names cs chip select sk serial data clock di serial data input do serial data output gnd ground pe program enable pre protect register enable v cc power supply ordering information nm 93 cs xx lz e xxx letter description package n 8-pin dip m8 8-pin so mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current density 66 4096 bits c cmos cs data protect and sequential read interface 93 microwire fairchild memory prefix v cc pe gnd cs sk di do 1 2 3 4 8 7 6 5 pre
3 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm93cs66 0 c to +70 c nm93cs66e -40 c to +85 c nm93cs66v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics v cc = 4.5v to 5.5v unless otherwise specified symbol parameter conditions min max units i cca operating current cs = v ih , sk=1.0 mhz 1 ma i ccs standby current cs = v il 50 a i il input leakage v in = 0v to v cc -1 a i ol output leakage (note 2) v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v ol1 output low voltage i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = -400 a 2.4 v ol2 output low voltage i ol = 10 a 0.2 v v oh2 output high voltage i oh = -10 av cc - 0.2 f sk sk clock frequency (note 3) 1 mhz t skh sk high time 0 c to +70 c 250 ns -40 c to +125 c 300 t skl sk low time 250 ns t sks sk setup time 50 ns t cs minimum cs low time (note 4) 250 ns t css cs setup time 100 ns t pres pre setup time 50 ns t dh do hold time 70 ns t pes pe setup time 50 ns t dis di setup time 100 ns t csh cs hold time 0 ns t peh pe hold time 250 ns t preh pre hold time 50 ns t dih di hold time 20 ns t pd output delay 500 ns t sv cs to status valid 500 ns t df cs to do in hi-z cs = v il 100 ns t wp write cycle time 10 ms
4 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm93cs66l/lz 0 c to +70 c nm93cs66le/lze -40 c to +85 c nm93cs66lv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 5.5v dc and ac electrical characteristics v cc = 2.7v to 5.5v unless otherwise specified symbol parameter conditions min max units i cca operating current cs = v ih , sk=1.0 mhz 1 ma i ccs standby current cs = v il l 10 a lz (2.7v to 4.5v) 1 a i il input leakage v in = 0v to v cc 1 a i ol output leakage (note 2) v il input low voltage -0.1 0.15v cc v v ih input high voltage 0.8v cc v cc +1 v ol output low voltage i ol = 10 a 0.1v cc v v oh output high voltage i oh = -10 a 0.9v cc f sk sk clock frequency (note 3) 0 250 khz t skh sk high time 1 s t skl sk low time 1 s t sks sk setup time 0.2 s t cs minimum cs low time (note 4) 1 s t css cs setup time 0.2 s t pres pre setup time 50 ns t dh do hold time 70 ns t pes pe setup time 50 ns t dis di setup time 0.4 s t csh cs hold time 0 ns t peh pe hold time 250 ns t preh pre hold time 50 ns t dih di hold time 0.4 s t pd output delay 2 s t sv cs to status valid 1 s t df cs to do in hi-z cs = v il 0.4 s t wp write cycle time 15 ms capacitance t a = 25 c, f = 1 mhz (note 5) symbol test typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20na range. note 3 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 4 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagram on the following page.) note 5 : this parameter is periodically sampled and not 100% tested. ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v 0.3v/1.8v 1.0v 0.8v/1.5v 10 a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v 2.1ma/-0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf)
5 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read pin description chip select (cs) this is an active high input pin to nm93cs66 eeprom (the device) and is generated by a master that is controlling the device. a high level on this pin selects the device and a low level deselects the device. all serial communications with the device is enabled only when this pin is held high. however this pin cannot be permanently tied high, as a rising edge on this signal is required to reset the internal state-machine to accept a new cycle and a falling edge to initiate an internal programming after a write cycle. all activity on the sk, di and do pins are ignored while cs is held low. serial clock (sk) this is an input pin to the device and is generated by the master that is controlling the device. this is a clock signal that synchronizes the communication between a master and the device. all input informa- tion (di) to the device is latched on the rising edge of this clock input, while output data (do) from the device is driven from the rising edge of this clock input. this pin is gated by cs signal. serial input (di) this is an input pin to the device and is generated by the master that is controlling the device. the master transfers input informa- tion (start bit, opcode bits, array addresses and data) serially via this pin into the device. this input information is latched on the rising edge of the sck. this pin is gated by cs signal. serial output (do) this is an output pin from the device and is used to transfer output data via this pin to the controlling master. output data is serially shifted out on this pin from the rising edge of the sck. this pin is active only when the device is selected. protect register enable (pre) this is an active high input pin to the device and is used to distinguish operations to memory array and operations to protect register. when this pin is held low, operations to the memory array are enabled. when this pin is held high, operations to the protect register are enabled. this pin operates in conjunction with pe pin. refer table1 for functional matrix of this pin for various operations. program enable (pe) this is an active high input pin to the device and is used to enable operations, that are write in nature, to the memory array and to the protect register. when this pin is held high, operations that are write in nature are enabled. when this pin is held low, operations that are write in nature are disabled. this pin operates in conjunction with pre pin. refer table1 for functional matrix of this pin for various operations. microwire interface a typical communication on the microwire bus is made through the cs, sk, di and do signals. to facilitate various operations on the memory array and on the protect register, a set of 10 instructions are implemented on nm93cs66. the format of each instruction is listed in table 1. instruction each of the above 10 instructions is explained under individual instruction descriptions. start bit this is a 1-bit field and is the first bit that is clocked into the device when a microwire cycle starts. this bit has to be 1 for a valid cycle to begin. any number of preceding 0 can be clocked into the device before clocking a 1 . opcode this is a 2-bit field and should immediately follow the start bit. these two bits (along with pre, pe signals and 2 msb of address field) select a particular instruction to be executed. address field this is a 8-bit field and should immediately follow the opcode bits. in nm93cs66, all 8 bits are used for address decoding during read, write and prwrite instructions.during all other in- structions (with the exception of prread), the msb 2 bits are used to decode instruction (along with opcode bits, pre and pe signals). data field this is a 16-bit field and should immediately follow the address bits. only the write and wrall instructions require this field. d15 (msb) is clocked first and d0 (lsb) is clocked last (both during writes as well as reads). table 1. instruction set instruction start bit opcode field address field data field pre pin pe pin read 1 10 a7 a6 a5 a4 a3 a2 a1 a0 0 x wen 1 00 1 1xxxxxx 0 1 write 1 01 a7 a6 a5 a4 a3 a2 a1 a0 d15-d0 0 1 wrall 1 00 0 1 x x xxxx d15-d0 0 1 wds 1 00 0 0xxxxxx 0 x prread 1 10 xxxxxxxx 1 x pren 1 00 1 1 x x xxxx 1 1 prclear 1 11 11111111 1 1 prwrite 1 01 a7 a6 a5 a4 a3 a2 a1 a0 1 1 prds 1 00 00000000 1 1
6 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read functional description a typical microwire cycle starts by first selecting the device (bringing the cs signal high). once the device is selected, a valid start bit ( 1 ) should be issued to properly recognize the cycle. following this, the 2-bit opcode of appropriate instruction should be issued. after the opcode bits, the 8-bit address information should be issued. for certain instructions, some (or all) of these 8 bits are don t care values (can be 0 or 1 ), but they should still be issued. following the address information, depending on the instruction (write and wrall), 16-bit data is issued. other- wise, depending on the instruction (read and prread), the device starts to drive the output data on the do line. other instructions perform certain control functions and do not deal with data bits. the microwire cycle ends when the cs signal is brought low. however during certain instructions, falling edge of the cs signal initiates an internal cycle (programming), and the device remains busy till the completion of the internal cycle. each of the 10 instructions is explained in detail in the following sections. memory instructions following five instructions, read, wen, write, wrall and wds are specific to operations intended for memory array. the pre pin should be held low during these instructions. 1) read and sequential read (read) read instruction allows data to be read from a selected location in the memory array. input information (start bit, opcode and address) for this instruction should be issued as listed under table1. upon receiving a valid input information, decoding of the opcode and the address is made, followed by data transfer from the selected memory location into a 16-bit serial-out shift register. this 16-bit data is then shifted out on the do pin. d15 bit (msb) is shifted out first and d0 bit (lsb) is shifted out last. a dummy-bit (logical 0) precedes this 16-bit data output string. output data changes are initiated on the rising edge of the sk clock. after reading the 16-bit data, the cs signal can be brought low to end the read cycle. the pre pin should be held low during this cycle. refer read cycle diagram . this device also offers sequential memory read operation to allow reading of data from the additional memory locations instead of just one location. it is started in the same manner as normal read but the cycle is continued to read further data (instead of terminat- ing after reading the first 16-bit data). after providing 16-bit data, the device automatically increments the address pointer to the next location and continues to provide the data from that location. any number of locations can be read out in this manner, however, after reading out from the last location, the address pointer points back to the first location. if the cycle is continued further, data will be read from this first location onward. in this mode of read, the dummy-bit is present only when the very first data is read (like normal read cycle) and is not present on subsequent data reads. the pre pin should be held low during this cycle. refer sequen- tial read cycle diagram . 2) write enable (wen) when v cc is applied to the part, it powers up in the write disable (wds) state. therefore, all programming operations (for both memory array and protect register) must be preceded by a write enable (wen) instruction. once a write enable instruction is executed, programming remains enabled until a write disable (wds) instruction is executed or v cc is completely removed from the part. input information (start bit, opcode and address) for this wen instruction should be issued as listed under table1. the device becomes write-enabled at the end of this cycle when the cs signal is brought low. the pre pin should be held low during this cycle. execution of a read instruction is independent of wen instruction. refer write enable cycle diagram. 3) write (write) write instruction allows write operation to a specified location in the memory with a specified data. this instruction is valid only when the following are true: device is write-enabled (refer wen instruction) address of the write location is not write-protected pe pin is held high during this cycle pre pin should be held low during this cycle input information (start bit, opcode, address and data) for this write instruction should be issued as listed under table1. after inputting the last bit of data (d0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. the status of the internal programming cycle can be polled at any time by bringing the cs signal high again, after t cs interval. when cs signal is high, the do pin indicates the ready/busy status of the chip. do = logical 0 indicates that the programming is still in progress. do = logical 1 indicates that the programming is finished and the device is ready for another instruction. it is not required to provide the sk clock during this status polling. while the device is busy, it is recommended that no new instruction be issued. refer write cycle diagram. it is also recommended to follow this instruction (after the device becomes ready) with a write disable (wds) instruction to safeguard data against corruption due to spurious noise, inadvert- ent writes etc. 4) write all (wrall) write all (wrall) instruction is similar to the write instruction except that wrall instruction will simultaneously program all memory locations with the data pattern specified in the instruction. this instruction is valid only when the following are true: protect register has been cleared (refer prclear instruction) device is write-enabled (refer wen instruction) pe pin is held high during this cycle pre pin should be held low during this cycle input information (start bit, opcode, address and data) for this wrall instruction should be issued as listed under table1. after inputting the last bit of data (d0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer write all cycle diagram.
7 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read 5) write disable (wds) write disable (wds) instruction disables all programming opera- tions and is recommended to follow all programming operations. executing this instruction after a valid write instruction would protect against accidental data disturb due to spurious noise, glitches, inadvertent writes etc. input information (start bit, opcode and address) for this wds instruction should be issued as listed under table1. the device becomes write-disabled at the end of this cycle when the cs signal is brought low. execution of a read instruction is independent of wds instruction. refer write disable cycle diagram. protect register instructions following five instructions, prread, pren, prclear, prwrite and prds are specific to operations intended for protect register. the pre pin should be held high during these instructions. 1) protect register read (prread) this instruction reads the content of the internal protect register. content of this register is 8-bit wide and is the starting address of the write-protected section of the memory array. all memory locations greater than or equal to this address are write-protected. input information (start bit, opcode and address) for this prread instruction should be issued as listed under table 1. upon receiving a valid input information, decoding of the opcode and the address is made, followed by data transfer (address information) from the protect register. this 8-bit data is then shifted out on the do pin with the msb first and the lsb last. like the read instruction a dummy-bit (logical 0) precedes this 8-bit data output string. output data changes are initiated on the rising edge of the sk clock. after reading the 8-bit data, the cs signal can be brought low to end the prread cycle. the pre pin should be held high during this cycle. refer protect register read cycle diagram. 2) protect register enable (pren) this instruction is required to enable prclear, prwrite and prds instructions and should be executed prior to executing prclear, prwrite and prds instructions. however, this pren instruction is enabled (valid) only the following are true device is write-enabled (refer wen instruction) pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this pren instruction should be issued as listed under table1. the protect register becomes enabled for prclear, prwrite and prds instructions at the end of this cycle when the cs signal is brought low. note that this pren instruction must immediately precede a prclear, prwrite or prds instruction. in other words, no other instruction should be executed between a pren instruction and a prclear, prwrite or prds instruction. refer protect register enable cycle diagram. 3) protect register clear (prclear) this instruction clears the content of the protect register and therefore enables write operations (write or wrall) to all memory locations. executing this instruction will program the content of the protect register with a pattern of all 1s. however, in this case, write operation to the last memory address (0x11111111) is still enabled. prclear instruction is enabled (valid) only when the following are true: pren instruction was executed immediately prior to prclear instruction pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this prclear instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed clear cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal clear cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer protect register clear cycle diagram. 4) protect register write (prwrite) this instruction is used to write the starting address of the memory section to be write-protected into the protect register. after the execution of prwrite instruction, all memory locations greater than or equal to this address are write-protected. prwrite instruction is enabled (valid) only the following are true: prclear instruction was executed first (to clear the protect register) pren instruction was executed immediately prior to prwrite instruction pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this prwrite instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer protect register write cycle diagram. 5) protect register disable (prds) unlike all other instructions, this instruction is a one-time-only instruction which when executed permanently write-protects the protect register and renders it unalterable in the future. this instruction is useful to safeguard vital data (typically read only data) in the memory against any possible corruption. prds instruction is enabled (valid) only the following are true: pren instruction was executed immediately prior to prds instruction pe pin is held high during this cycle pre pin is held high during this cycle
8 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read input information (start bit, opcode and address) for this prds instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. the protect register is permanently write-protected at the end of this cycle. refer protect register disable cycle diagram. clearing of ready/busy status when programming is in progress, the data-out pin will display the programming status as either busy (low) or ready (high) when cs is brought high (do output will be tri-stated when cs is low). to restate, during programming, the cs pin may be brought high and low any number of times to view the programming status without affecting the programming operation. once programming is completed (output in ready state), the output is cleared (returned to normal tri-state condition) by clocking in a start bit. after the start bit is clocked in, the output will return to a tri-stated condition. when clocked in, this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. refer clearing ready status diagram. related document application note: an758 - using fairchild s microwire ee- prom.
9 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read t css synchronous data timing cs sk pre pe di do (data read) do (status read) valid status t pres t pes t dis t dih t pd t dh t sv t skh t skl t csh t preh t peh t df t df t pd valid input valid input valid output valid output t sks cs sk di do high - z dummy bit 1 1 0 a7 a6 a1 a0 pre 0 d15 d1 d0 t cs normal read cycle (read) address bits(8) start bit opcode bits(2) 93cs66: address bits pattern -> user defined pe timing diagrams cs sk di do high - z dummy bit data(n) 1 1 0 a7 a0 pre 0 d15 d0 d15 d0 d15 d0 t cs sequential read cycle (pre = 0; pe = x) data(n+1) data(n+2) address bits(8) start bit opcode bits(2) 93cs66: address bits pattern -> user defined
10 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read timing diagrams (continued) address bits(8) cs pe sk di do high - z write disable cycle (wds) start bit 93cs66: address bits pattern -> 0-0-x-x-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a7 a6 a1 a0 pre t cs address bits(8) data bits(16) cs pe sk di do high - z t cs write cycle (write) start bit 93cs66: address bits pattern -> user defined data bits pattern -> user defined opcode bits(2) 1 0 1 a7 a6 a1 a0 d15 d14 d1 d0 pre busy ready t wp address bits(8) cs pe sk di do high - z write enable cycle (wen) start bit 93cs66: address bits pattern -> 1-1-x-x-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a7 a6 a1 a0 pre t cs
11 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read timing diagrams (continued) cs sk di do high - z dummy bit 1 1 0 a7 a6 a1 a0 pre pe 0 d7 d1 d0 t cs protect register read cycle (prread) address bits(8) start bit opcode bits(2) 93cs66: address bits pattern -> x-x-x-x-x-x-x-x; (x -> don't care, can be 0 or 1) address bits(8) cs pe sk di do high - z protect register enable cycle (pren) start bit 93cs66: address bits pattern -> 1-1-x-x-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a7 a6 a1 a0 pre t cs address bits(8) data bits(16) cs pe sk di do high - z t cs write all cycle (wrall) start bit 93cs66: address bits pattern -> 0-1-x-x-x-x-x-x; (x -> don't care, can be 0 or 1) data bits pattern -> user defined opcode bits(2) 1 0 0 a7 a6 a1 a0 d15 d14 d1 d0 pre busy ready t wp
12 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read timing diagrams (continued) address bits(8) cs pe sk di do high - z t cs protect register write cycle (prwrite) start bit 93cs66: address bits pattern -> user defined opcode bits(2) 1 0 1 a7 a6 a1 a0 pre busy ready t wp address bits(8) cs pe sk di do high - z t cs protect register disable cycle (prds) start bit 93cs66: address bits pattern -> 0-0-0-0-0-0-0-0 opcode bits(2) 1 0 0 a7 a6 a1 a0 pre busy ready t wp address bits(8) cs pe sk di do high - z t cs protect register clear cycle (prclear) start bit 93cs66: address bits pattern -> 1-1-1-1-1-1-1-1 opcode bits(2) 1 1 1 a7 a6 a1 a0 pre busy ready t wp
13 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read timing diagrams (continued) cs pe sk di do high - z high - z clearing ready status start bit note: this start bit can also be part of a next instruction. hence the cycle can be continued(instead of getting terminated, as shown) as if a new instruction is being issued. pre busy ready
14 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read molded package, small outline, 0.15 wide, 8-lead (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
15 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read 8-pin molded tssop, jedec (mt8) package number mtc08 physical dimensions inches (millimeters) unless otherwise noted 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
16 www.fairchildsemi.com nm93cs66 rev. f.2 nm93cs66 (microwire bus interface) 4096-bit serial eeprom with data protect and sequential read physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 nm95hs01/nm95hs02 hisec high security rolling code generator july 1998 ? 1998 fairchild semiconductor corporation nm95hs01/nm95hs02 hisec? high security rolling code generator general description the nm95hs01/02 hisec rolling code generator is a small footprint, monolithic cmos device designed to provide a com- plete, low-cost, high security solution to the problem of generating encrypted signals for remote keyless entry (rke) applications. the nm95hs01/02 generates a fully encoded bit stream each time one of (up to) 4 switch inputs is activated. the patented* coding scheme utilizes 2 48 possible user-programmable coding combinations, and features high linear complexity and correlation immunity. high security is guaranteed by generating a unique (rolling) code for each transmission, and can be further enhanced by creating customized algorithms for individual customers. with this product, each key can be designed to be both unique and highly secure. the nm95hs01/02 supports either an ir or rf signal transmitter, and can be clocked with either an rc clock (nm95hs01) or a crystal oscillator (nm95hs02). the device operates over a volt- age range of 2.2v to 6.5v, and offers a low power standby mode (<1 m a) for battery applications. the product is available in both 8- pin and 14-pin so packages with 2 or 4 key switch inputs that can be used for customer presets such as seat positions, and vehicle operating functions such as car door locking/unlocking. functional block diagram features n high security coding scheme with 2 48 combinations n high linear complexity and correlation immunity n 2.2v to 6.5v operation n less than 1 m a standby current n full resynchronization capability n unique customized algorithm option n 13 bytes on-chip non-volatile configuration memory n rc or xtal clock options for to 4.1 mhz operation n supports both ir and rf signal transmission n selection of bit coding and transmission frame formats n space saving narrow body so8 or so14 packages n up to 4 key switch inputs on so14 package applications n remote keyless entry (rke) applications n burglar alarms/garage door openers n individualized recognition/transmission systems n personalized consumer automotive applications relevant documents n designing and programming a complete hisec? -based rke system: an-985 ds012302-1 enkey init data output transmit and timing block code generator block tx data key application decoder enpre init enb en24 enbuf preamble generator 8-bit sync field reg. 24-bit key 10 reg. parity generator 24/36-bit buffer reg. note: signals shown are internal logic signals. figure 1. note: *patents pending
2 nm95hs01/nm95hs02 hisec high security rolling code generator general characteristics the nm95hs01/02hisec generator was developed to meet existing standards for rolling code-based security systems. theft prevention systems typically involve user identification and transmission of information at various distances from the vehicle. these remote keyless entry (rke) systems are generally imple- mented with ir transmitters for short distances, or rf transmitters for longer distances. rf transmission has become state of the art; however the longer distances involved require a much higher degree of security, since the possibility of signal interception is greatly increased. these applications are ideally served by the nm95hs01/02. this generator is a small footprint, low current solution that supports both ir and rf transmission. the device is available in an 8-pin so package with 2 key switch inputs, or a 14-pin so package with 4 key switch inputs. the proprietary coding scheme used generates a rolling code based on 2 48 possible user combinations, and ensures a high level of coding security for any rke application. the nm95hs01 can be clocked with an rc circuit, while the nm95hs02 can be clocked with a crystal oscillator. general device operation the functional block diagram ( figure 1) shows the internal elements of the code generating logic and program registers. the nm95hs01/02 hisec generator achieves its high security level by combining the contents of several dynamic data registers in a non-linear manner to generate an encoded output. data in the registers is comprised of a mixture of user programmable data, factory programmable data, and randomized data. this inherently random and separate data is encrypted by clocking it through a non-linear logic block, and feeding part of the output back to produce a final coded output with a high degree of linear complex- ity and correlation immunity. the nm95hs01/02 incorporates 13 bytes of non-volatile eeprom memory which can be used to configure the device registers. this memory is accessible to the user, and can be configured to the desired configuration, then write-disabled to prevent tampering. user programmable data includes 24 bits of the code block, a 24- bit key id register, and an 8-bit sync field register. the 24-bit key id register can be used to configure a large number of unique keys, each of which will produce a unique encoded output bit stream. the 24 bits in the code generator block are mixed with coded data. the output of this block is then fed into the 24-/36-bit buffer register, where the 40 bits are recombined to produce a 24-or 36- bit output (a user option). the 8-bit sync field register can be configured by the user to provide a pattern to facilitate synchroni- zation between the transmitter and receiver. the details of the code block are available to customers, and exclusive algorithms are available and under contract with fair- child. call your local sales office for details. the hisec generator is shipped with a standard algorithm as a standard product, with the configuration shown. figure 2 shows a general operational block diagram of the nm95hs01/02 hisec generator. the 4 key switch inputs shown use internal pull-up resistors, and are suitable for normally open, single pole input switches connected to ground. the inputs are buffered by debounce logic which repeatedly polls the inputs to determine if a key switch has been asserted. if any key switch input is seen as low for four continuous 10 ms samples, its associated output is set high, the hisec control logic is activated, and a security code is generated and transmitted. the timer block is used to set the key debounce time and the ir or rf clock times. these clock times are used as the time base for the chosen bit coding format. the timer block is also used to generate the interframe pause time, and the timeout delay, if these are enabled. these parameters are configured by the user in the 13-byte on-chip eeprom array. the nm95hs01 version of the device uses an rc network to clock the cki input pin. the cko/led pin is not required for clocking, but may be used for a visual indicator led. if the nm95hs02 crystal oscillator version is used, the device is clocked using both the cki and cko pins. if an led is used with this device, it may be grounded through the rfen /led pin. either the cko/led or the rfen/led output pins can provide the sink current needed to drive an indicator led. the rfen pin is active low during signal transmission, and is used to provide power to the rf circuit only during transmission to increase battery life. the transmit output (tx) pin is a configurable logic level output, and is used to transmit the encoded bit stream. an on-chip power- on reset circuit is used to initialize the device during power-up.
3 nm95hs01/nm95hs02 hisec high security rolling code generator connection diagrams 8Cpin so package (m8) top view see package number m08a (m8) or n08e (n) 14-pin so package (m14) and 14-pin dual-in-line package (n14) 14-pin tssop package (mt14) top view see package number m14a (m), mtc14 (mt14) n14a (n14) pin names pin description keyn key input rfen/led rf enable/led cko/led xtal clock/led tx data transmit cki rc clock input gnd ground v cc supply voltage ordering information commercial temperature range (0 c to +70 c) order number nm95hs01m8/nm95hs02m8 nm95hs01n/nm95hs02n nm95hs01m/nm95hs02m nm95hs01mt14/nm95hs02mt14 nm95hs01n14/nm95hs02n14 extended temperature range (-40 c to +85 c) order number nm95hs01em8/nm95hs02em8 nm95hs01en/nm95hs02en nm95hs01em/nm95hs02em nm95hs01en14/nm95hs02en14 key key rfen/led cko/led v cc gnd tx cki key1 key2 nc key3 key4 v cc gnd nc tx nc nc cki rfen/led cko/led ds012302-2 ds012302-3
4 nm95hs01/nm95hs02 hisec high security rolling code generator ordering information (continued) *note: keys 3 and 4 available in 14-pin packages. figure 2. operational block diagram of the nm95hs01/02 hisec generator general transmitter circuit configurations figure 3 shows several typical circuit configurations for a hisec based rke system transmitter. note that all circuits require few external components beyond a battery and transmitter stage. ir and rf bit timing may be optimized through the timer block settings in the eepr0m array, which allows flexibility in selecting the smallest and least expensive clock components in the chosen design range. the first two circuits are examples of rf transmitter applications, with both rc and crystal (xtal) oscillator clocks; the third circuit is an example of an ir transmitter application. two circuits are configured for an led. note that the led pin refers to a visual indicator led, and not the ir led which might be used in an ir transmitter circuit. the ledsel bit in the eeprom array determines whether the rfen/led or cko/led pins are dedicated to the led for a particular circuit configuration. led pin select options are detailed in table 1. design considerations for selecting and optimizing clock compo- nent values are detailed in the generator clock design param- eters section. timer block debounce logic eeprom registers (13 bytes) control logic dynamic code generator power-on reset v cc gnd cki cko key1 key2 key3* key4* tx rfen led data transmit block *note: keys 3 and 4 available in 14 pin packages. ds012302-4
5 nm95hs01/nm95hs02 hisec high security rolling code generator figure 3. typical transmitter circuit configurations table 1. led pin select options clock ledsel rfen/led cko/led function rc x rfen led rf mode with led xtal 0 led cko rf mode w/o led xtal 1 rfen cko ir mode with led either the led or rfen outputs of the nm95hs01/02 can be used to indicate device transmission. the led output is active during a pause, whereas the rfen output is active during frame transmission. the ir drive current is 10 ma so an amplifier stage may be needed. bit coding formats the nm95hs01/02 hisec generator supports eleven-bit coding formats which may be used for ir and rf transmission. seven-bit formats are available for rf applications, and four are available for ir applications. one-bit format is reserved for future use. bit coding formats are selected by configuring four bits in the eeprom array: irsel, prsel2, prsel1 and prsel0. table ii shows the possible bit coding options available. each bit coding format has a distinction which may be advanta- geous for a particular application. rf bit coding format 0 is the simplest bit coding scheme, and data may be easily recovered from a transmission by exclusive or-ing the data and clock stream. both rf bit coding formats 0 and 2 have a dc level that is independent of the data. rf format 4, and the ir modes operate with a constant transmis- sion energy per message, and rf coding formats 1, 3, 5 and 7 are pulse-width modulated (pwm) formats which are relatively easy to decode. rf coding format 7 has a low duty cycle. tx rfen led gnd cki key2 key1 v cc rf stage v cc r c tx rfen gnd cki key2 key1 v cc rf stage cko v cc r1 c2 c1 tx led gnd cki key2 key1 v cc ir stage cko v cc r1 c2 c1 ds012302-5
6 nm95hs01/nm95hs02 hisec high security rolling code generator bit coding formats (continued) the ir bit coding formats are modulated versions of rf coding format 4, and are all suitable for ir applications. the duty cycle and number of pulses are variable among these four to allow the user to fine tune the ir circuit power curve. ir bit coding formats all follow the same general pattern. in this mode, a logic 1 is always two periods long, and a 0 is always three periods long. this may be an important consideration when considering preamble and sync timing. waveform diagrams for all available rf and ir bit transmission coding formats are shown below. table 2. transmission bit coding options irsel prsel2 prsel1 prsel0 function 0000rf bit coding format 0 0001rf bit coding format 1 0010rf bit coding format 2 0011rf bit coding format 3 0100rf bit coding format 4 0101rf bit coding format 5 0110 reserved 0111rf bit coding format 7 1000ir bit coding format 1 1001ir bit coding format 2 1010ir bit coding format 3 1011ir bit coding format 4 1 1 x x reserved bit transmission coding formats rf bit coding format 0 (manchester code) rf bit coding format 1 (33%/66% end high) rf bit coding format 2 (50% duty cycle) rf bit coding format 3 (25%/50% start high) rf clock bit 1 bit 0 rf clock bit 1 bit 0 rf clock bit 1 bit 0 rf clock bit 1 bit 0 ds012302-6 ds012302-8 ds012302-7 ds012302-9
7 nm95hs01/nm95hs02 hisec high security rolling code generator bit transmission coding formats (continued) rf bit coding format 4 (ir style) rf bit coding format 5 (33%/66% start high) rf bit coding format 7 (low duty cycle 1:16/2:16) ir bit coding format 1 (5 pulses 33% duty cycle) ir bit coding format 2 (8 pulses 33% duty cycle) ir bit coding format 3 (5 pulses 25% duty cycle) rf clock bit 1 bit 0 (3 clocks long) (2 clocks long) rf clock bit 1 bit 0 rf clock bit 1 bit 0 ir clock ir clock ir clock bit 1 bit 0 ir clock ir clock ir clock bit 1 bit 0 ir clock ir clock ir clock bit 1 bit 0 ds012302-10 ds012302-11 ds012302-12 ds012302-13 ds012302-14 ds012302-15
8 nm95hs01/nm95hs02 hisec high security rolling code generator bit transmission coding formats (continued) ir bit coding format 4 (8 pulses 25% duty cycle) programmable signal output polarity the transmit (tx) output pin signal polarity and quiescent state output is controlled by the txpol bit, which may be configured in eepr0m. if txpol = 0, the tx output pin will be at a logic low when no frame is transmitted, or when a 0 appears as data in a frame. conversely, if txpoi = 1, the tx output pin will be at a logic high when no frame is transmitted, or when a 1 appears as data in a frame. this option allows the designer to choose between a configuration where a logic 1 represents power transmission (for example, when an rf stage is activated by driving the base of an npn transistor), and a configuration where a logic 0 represents power transmission (for example, when an ir led is connected between vcc and the tx output). data frames the nm95hs01/02 hisec generator transmits the encrypted data it generates as data frames. these frames are transmitted through an ir or rf transmitter stage using the bit coding format selected. the nm95hs01/02 transmits two types of data frames: a normal data frame, and a synchronization (sync) frame. the format of each frame is similar, but there are slight differences to suit the purposes of each. normal data frames are used to transmit encoded data in general operation. sync frames are used to synchronize (or initialize) the hisec to its decoder. data frames are comprised of a number of different fields. each field occupies a fixed position in the data frame, and serves a specific purpose. most data fields are user-configurable to some extent. the user may enable/disable the presence of a field, control its length, or modify its format. the user also has several options available to tailor the data frame transmission format, such as pause time between frames, and time-out time. options are configured by programming the on-chip eepr0m array. the content and format of each of the fields is discussed below. normal data frame the nm95hs01/02 hisec generator transmits normal data frames in general operating mode. frame transmission begins each time a key switch is asserted, and continues as long as the key is held down. the device has an option to terminate transmitting data frames, and go into halt mode, if a key is held down for more than 80 seconds (if the tlmeouten feature has been enabled). the normal data frame format contains both dynamic code and key application data (in the data field). since the length of several fields is adjustable, there are several possibilities for the length of the data frame. the shortest possible normal data frame is 29 bits, and the longest possible normal data frame is 92 bits. 24 bits of dynamic code, 4 bits of key application data, and 1 stop bit are always present. the composition of a normal data frame is shown in figure 4. sync frame the nm95hs01/02 hisec generator transmits sync frames only in sync mode so that it can synchronize itself with its decoder. this mode occurs only during initialization of the device, or after holding a key down for more than 10 seconds (if the autoresync feature has been enabled). the sync frame format contains both start code and a fixed 4-bit sync code of 0000. this sync code replaces the key application data in the data field, and is used to confirm hisec sync mode to the decoder. sync mode is built into the generator to allow resynchronization of the device under certain conditions as a convenience to the end user. if the designer wishes to preclude any possible resynchronization, the presence of the sync code allows the decoder to detect any synchronization attempt. since the length of several fields is adjustable, there are several possibilities for the length of a sync frame. the shortest possible sync frame is 45 bits, and the longest possible sync frame is 96 bits. 40 bits of start code, 4 bits of sync code, and 1 stop bit are always present. the composition of a sync frame is shown in figure 5. ir clock ir clock ir clock bit 1 bit 0 ds012302-16
9 nm95hs01/nm95hs02 hisec high security rolling code generator data frames (continued) 0/11 bits 0/8 bits 0/20/24 4 bits 24/36 bits 0/8 bits 1 bit bits preamble sync key id data dynamic parity stop field field field code field bit figure 4. normal data frame configuration 0/11 bits 0/8 bits 0/20/24 4 bits 40 bits 0/8 bits 1 bit bits preamble sync key id sync start parity stop field field code code field bit figure 5. sync frame configuration data frame fields data frames are comprised of a number of data fields. each field occupies a fixed position in the data frame, and serves a specific purpose. most data fields are user-configurable by programming the on-chip eeprom array. the content and format of each field is discussed below, as well as the eeprom options available. all data frame fields are transmitted most significant bit first. the preamble the user has the option of allowing a preamble to be tranmitted as the first frame of either a normal data frame or a sync frame. this option is enabled/disabled by setting the preamblepresent bit in the eeprom array. preamblepresent = 0 means no preamble is transmitted. preamblepresent = 1 means an 11-bit preamble is transmitted as described below. the purpose of the preamble is to generate a relatively long, clearly recognizable bit pattern to give the decoder a chance to wake up and configure its logic circuits and registers. this allows the receiver to be placed in a standby mode to conserve power for battery applications. the preamble is only transmitted once as the first frame of a data transmission, regardless of how long the key is held down, although the remaining frames of the data transmission (including any inter-frame pauses) will continue to repeat as long as the key remains depressed. the preamble has a fixed format of two bit times at system logic high, then one-bit time at system logic low, then eight zeroes using the user-selected bit coding format. this arrangement is clearly shown in figure 6for several bit coding formats. if desired, a preamble may be isolated from the frame by eight-bit times at logic low during a frame transmission. this can be achieved by enabling the sync field in nrz mode with the byte 0h. sync field if enabled, the sync field is transmitted in every normal data frame or sync frame to provide a bit timing reference for the rest of the frame. this allows the decoder to determine the proper bit coding format the generator is using, and to synchronize to it. the sync field option is set with the syncpresent bit in the eeprom array. if syncpresent = 0, no sync field is sent. if syncpresent = 1 an 8-bit sync field is included in the data transmission. this 8-bit field is transmitted most significant bit first. the sync field data is programmable, and can be encoded with any user-selected bit coding format, or with an nrz (unencoded binary) bit format. the option to select between a user bit coding format and nrz format is set by configuring the synctype bit in the eeprom array. if synctype = 0, sync field data is sent according to the user-selected ir or rf bit coding format. if synctype = 1, the information is sent in nrz format with the bit length determined by the chosen ir or rf bit coding format. for nrz bit coding, both high and low bit times are the same as the ir or rf bit coding time. for bit coding modes where the 1s and 0s have different bit lengths all ir modes for example the length of the nrz 1 and 0 bits have correspondingly different bit lengths. rf bit coding format 7 is a special case. as in the other formats, if synctype = 0, information is sent according to the user-set ir or rf bit coding format. however, if synctype = 1, a 0 is sent using the bit coding determined by the ir or rf coding format, and a 1 is sent as an nrz zero. this is to maintain the spirit of the low duty cycle arrangement for rf format 7. figure 7 shows sync field examples for several bit coding formats.
10 nm95hs01/nm95hs02 hisec high security rolling code generator data frame fields (continued) figure 6. preamble format examples figure 7. sync field exampies for data byte 03h key id field the key id field is another user option. both its presence and the length of its field can be configured in eeprom. if fixpresent = 0, no key id field will be transmitted with the frame. if fixpresent = 1, a 24-bit field will be transmitted. the contents of the key id field are programmable by the user. its purpose is to provide a unique identification code for each user key to allow a decoder to identify a particular key in applications where a decoder may be configured for multiple keys. since the key id register allows 24 bits, there are 2 24 possible key combinations. each user key will be unique, and take full advantage of the hisec generators high security coding scheme. the field size is selected with the fixsize bit. if fixsize = 1, the 24- bit field is selected. if fixsize = 0, the 20-bit field is selected. since a full 24 bits are allowed in the key id register, the nm95hs01/02 will transmit the most significant 20 bits if fixsize = 0. the field is transmitted in the user-selected bit coding format. data field the data field is transmitted with every frame. it has several uses, which are discussed here. the primary use of the data field is to indicate which key switch has been pressed. since each key switch input can be associated with a particular application, the decoder can determine which function to initiate. the data field is 4 bits long, and each key switch input is associated with a particular bit in the field. if any key switch is pressed, its corresponding bit in the data field will be seen as a 1. any key switch not pressed is seen as a default 0. key bits are transmitted in the order: k1, k2, k3, k4. the sync code field in the sync frame is a special case of the data field, and is found in the same position in the data frame. in any sync frame, the sync code is always 0000, so the decoder can always distinguish between a normal data frame and a sync frame. since each bit represents a key, and a data frame is initiated as a result of pressing a key, it is not possible to have all zeroes in a normal data frame. hhl00000000 hhl00000000 hhl00000000 rf format 2 rf format 5 rf format 7 0000001 1 000000 000000 11 0 00 00 011 0 00 00 011 11 rf format 5 sync type = 0 rf format 5 sync type = 1 rf format 0 sync type = 0 rf format 0 sync type = 1 rf format 7 sync type = 1 ds012302-18 ds012302-17
11 nm95hs01/nm95hs02 hisec high security rolling code generator data frame fields (continued) the data field can also serve as a low battery indicator. this is an option which can be enabled by setting the compareenable bit. if compareenable = 1, and the nm95hs01/02 detects a low battery level, the device will signal that fact by alternating between transmitting normal data frames with the correct key usage information, and transmitting normal data frames with a data field of 1111. in the first data frame, the data field will represent the true state of the four key inputs. in the next frame, this field will be all ones. this sequence will be repeated as long as frames are being transmitted. for sync frames, this field will not alternate, and the data will remain 0000 regardless of the battery level. setting compareenable = 0 disables the low battery detect option. dynamic code field the dynamic code field is transmitted with every frame, and its length is programmable. if dynsize = 0, a 24-bit field is sent; if dynsize = 1, a 36-bit field is sent. its function is to provide a secure dynamic code which changes with each new transmission. the field is the result of combining the 11-, 13-, and 16-bit crc registers using non-linear logic and feedback. the result of this process is stored in the 24-/36-bit buffer register. if dynsize = 0, 24 of the possible 36 bits are transmitted in the field. increasing the field length provides additional security. the start code field in a sync frame is a special case of the dynamic code field. in sync mode, 40 bits of data are sent regardless of the setting of the dynsize bit. parity field the parity field is an 8-bit field that is transmitted with every frame to ensure data integrity. it is a user option that is enabled by setting paritypresent = 1. the parity check is a bytewise exclusive or-ing of all the bytes in the data frame from the sync field to the dynamic code field. the preamble, parity field and stop bit are not included. in practice, the parity process works as follows: bit m of the 8-bit parity field is a modulo 2 addition of the data frame bits m, m+8, m+16, to the end of the frame. if the addition of the 1s in these bits is odd, bit m of the parity field is set to 1. if the addition is even, bit m is set to 0. this process is continued for all 8 parity bits. if the frame is not byte aligned, the parity field is calculated by zero extending the last four bits, calculating the bytewise exclusive or- ing of all the bytes as described above, then swapping the higher and lower nibbles to give the correct parity. stop bit the stop bit is present in all frames. it is used to delimit the end of the frame for bit formats that require a definite end. it is necessary for formats that end with a long zero pulse. ir modes require a stop bit to distinguish between a 0 and a 1 in the next-to-last bit of a frame. the stop bit is read as a 1, and is added for all modes. data frame sequencing and transmission the nm95hs01/02 becomes operational any time a key is pressed. when this happens, the code generator logic is clocked to randomize the data and generate a new rolling code. once the code is generated, data frames using this new code are repeat- edly transmitted over the tx output pin as long as the key remains pressed. these data frames are separated by a pause whose length is programmable. the transmission sequence is always begun by a preamble if this option is enabled. the preamble is only transmitted once, since its function is to wake the decoder from sleep mode if it is powered down for battery conservation. the preamble is then followed by a data frame, pause, data frame, pause, etc. transmission indication both the led and rfen signals can be used to indicate hisec rolling code transmission. the led output is active low during the transmission of a pause, whereas the rfen output is active low during transmission of either a frame or a pause. either output may be used to provide a visual indication of transmission by connect- ing an led between v cc and led or rfen . if the low battery detect option is enabled, and the battery is low, the led output is active only during the pause following the first frame of a new code transmission. it is not active on successive pauses, in order to conserve power. operational timing issues data frame pause length after the complete transmission of a data frame, a pause is inserted before the next data frame is transmitted. the pause length can be modifed by configuring the 2-bit pauselength parameter in eepr0m. pauselength is broken down into two single bit parameters, pause1 and pause0. available configura- tion options are shown in table 3. table 3. pause length select options pause1 pause0 function pause time 0 0 0 x p3 output no pause 0 1 8 x p3 output 20 ms 1 0 20 x p3 output 50 ms 1 1 50 x p3 output 100 ms hisec generator time-out if the nm95hs01/02 time-out option is enabled (timeouten = 1), the device will enter halt mode 80 seconds after a key is first activated, regardless of whether the key is still being pressed. this option guards against the condition that a key may be stuck low, which could drain the battery. if timeouten = 0, the generator will continue to transmit data frames as long as a key is pressed. hisec generator timer block bit timing and several function operating times are set in the generator through a user programmable timer block. this timer block is used to provide ir and rf bit timing signals, the interframe pause time, the autoresync timing period, and the time-out delay. the nm95hs01/02 timer block consists of three programmable 6- bit prescalers and a fixed 16-bit prescaler. the input to prescaler1 is 1 M4 of the frequency of cki. the output is the ir clock. this signal becomes the input to prescaler2. the output from prescaler2 is the rf clock. this signal then becomes the input to prescaler3. the output from prescaler3 is a target value of 2.5 ms. finally. this 2.5 ms timing signal becomes the input to the fixed 16-bit prescaler.
12 nm95hs01/nm95hs02 hisec high security rolling code generator operational timing issues (continued) there are several outputs from this prescaler. the 2.5 ms is divided by 4, 4096 and 32768, and these times are used to set the key debounce time (10 ms), the autoresync time (>10 sec), and the generator time-out period (>80 sec), respectively. the nm95hs01/02 timer block is shown in figure 8. the purpose of the prescalers is to provide various timing signals to the state machines in the generator. the ir clock is used as a time base for the various ir bit coding formats. the rf clock is used for rf bit coding formats. a programmable bit called sclk determines whether the ir clock (sclk = 0) or the rf clock (sclk = 1) is used as the bit timing time base. in addition to sclk, the system designer can program prescaler1, prescaler2 and prescaler3 separately to set the necessary division factors. since each of these prescalers is 6 bits, permissible values range from 2 to 64. the system designer must set the programmable prescalers to meet the necessary timing requirements for all the functions discussed above. all of these timings are interdependent. figure 9 provides the basis for an example in calculating the necessary timing for these functions, and setting the timer block appropriately. figure 8. the nm95hs01/02 timer block figure 9. nm95hs01/02 timer block example as an example, consider the following situation. a designer wishes to design an rf data transmitter using rf bit coding format 5 with a bit time of 1 ms. the designer also wishes to use a 3 mhz crystal oscillator as the system clock. the required bit time of 1 ms encompasses three rf clock periods for rf bit coding format 5. therefore, the rf clock time needs to be 1 M3 of 1 ms (=333 m s). the timer block has a target value of 2.5 ms (2500 m s) as the output of prescaler3. since the rf clock signal is divided by prescaler3, prescaler3 divides the signal by 2500/333 = 7.5. this figure is rounded off to become 8. one point of possible confusion should be clarified here. when- ever a division value is calculated for any of the 3 prescalers, the prescaler should be configured with one unit less than that division value. for example, in this case, we calculated a division value of 8 (after rounding) for prescaler3. therefore, prescaler3 should be programmed with 8 - 1=7. next we calculate values for prescaler1 and prescaler2. although the crystal oscillator uses both the cki and cko pins, only the cki input is relevant here. the cki input frequency is 3 mhz, and 1/4 of that is 0.75 mhz. this is the input frequency to the hisec timer block, and the corresponding timing signal is 1.33 m s. since the rf clock must be 333 m s, prescalers1 and 2 together must divide by 333/1.33 = 250. a convenient choice would be to make prescaler1 divide by 10 and prescaler2 divide by 25. therefore, load prescaler1 with 10 - 1 = 9, and prescaler2 with 25 - 1 = 24. debounce logic the key switch input signals are connected to the debounce logic block, which continuously polls the inputs to determine if a key switch has been asserted. if a key switch has been asserted, its normally high input will be seen as a low. lf the input is seen low for four continuous debounce strobe signals, it is considered to be a stable signal, and its associated output from the debounce logic block is set high. this enables the generator control logic, and a code is generated and transmitted. this debounced output signal is deasserted as soon as the key is released and its signal goes high again. this assumes normal operation. however, if a key remained pressed for a long time, the generator might time-out before seeing the signal go high again (if timeouten = 1). the generator would then enter halt mode even if the key remained pressed. the generator would come out of halt mode when it saw the falling edge of another key input, which would occur when another key is pressed. low battery detect option the nm95hs01/02 contains an internal comparator circuit that detects low battery voltage, and indicates this condition to the data frame generator. the compareenable parameter in eeprom enables this function (compareenable = 1). during halt mode, the comparator is switched off completely to minimize power con- sumption. the batterytype parameter in eeprom selects the threshold voltage range for the comparator. if batterytype = 1, the comparator assumes a 6v battery, and sets the low battery detect region to approxi- prescaler 1 prescaler2 prescaler 3 f cki fixed output 2.5 ms ir clock rf clock 6bit 6bit 6bit 4 rf clock bit 1 bit 0 bit time =1ms ds012302-19 ds012302-20
13 nm95hs01/nm95hs02 hisec high security rolling code generator operational timing issues (continued) mately 4.4v to 4.8v. if batterytype = 0, the comparator assumes a 3v battery, and sets the low battery detect region to approxi- mately 2.2v to 2.4v. data output signals are sampled for low voltage at the start of the data field during frame transmission. if a low battery voltage level is detected, and the detect option is enabled, the led will signal the condition by flashing at the first pause in the data frame transmission, and alternating normal data field data with a data field containing all ones. this procedure is explained more fully in the data field section. security aspects the basis of the hisec generator is to provide a means of communicating information between the device and its decoder across some distance. since data is transmitted at a distance, there is a possibility of signal interception and unauthorized use of the data by a third party. the nm95hs01/02 has been designed to provide such a high level of complexity and correlation immunity that intercepting the signal is immaterial. initialization/synchronization initialization is the process of synchronizing the generator with its decoder for the first time. the nm95hs01/02 uses the following procedure to initialize the device. the user inserts a new battery into the hisec-based device, which causes the led to light. the led also has a secondary function for synchronization and initialization procedures. it will light to prompt the end user that it expects some action, and therefore serves as a guide. when the led lights, the user presses a key. the led will go off as the generator begins randomizing its registers, and configuring its internal logic. when the user releases the key, the led will light a second time. this is a signal for the user to press a key again. this second action shifts the generator into sync mode. this causes the nm95hs01/02 to transmit at least four sync frames, allowing the decoder to synchronize to the generator. the genera- tor then exits sync mode, and is ready tor normal operation. resynchronization if synchronization is lost between the generator and its decoder, resynchronization is accomplished using a sync frame. a sync frame is generated in two cases: when the battery is removed and replaced, or the user initiates an initialization procedure by holding key switch 1 and key switch 2 simultaneously for 5 seconds. a sync frame provides the decoder with enough information to learn the key and synchronize to it. for the highest possible security protection, resynchronization can be completely excluded by configuring the decoder to recog- nize, and refuse to act upon, the transmission of a sync frame. the sync frame format is discussed more fully elsewhere, but briefly, it can be recognized by the presence of all zeroes in the data field. in this case, if synchronization is lost between the generator and decoder, they could not be made to function together. security aspects normal operation once the nm95hs01/02 has been initialized, the device will generate and transmit a new code each time a key is pressed. if a key is held down, the same frame (plus any pauses between frames) is transmitted repeatedly. if the key is held down for longer than 80 seconds, the generator will go into halt mode to conserve battery power, and will stop transmitting data frames (if the timeouten option is enabled). another option available during normal generator operation is the ability to generate a resync after a key has been pressed for more than 10 seconds (if the autoresync option is enabled). this option allows the end user to resynchronize the generator if necessary, without having to remove and replace the battery. forward calculation and code win- dows aside from using a sync frame, there is another way to ensure the nm95hs01/02 remains in sync with its decoder during normal operation. the decoder can perform a forward calculation to predict what the next generator codes will be. this is an important point, and should be considered carefully in designing the decod- ing system. in a well-designed system, the decoder should be able to calculate forward for some reasonable number of codes, and store the results for future reference. this allows the decoder to remain in sync even if it misses one or more codes from the generator. this could occur if the receiver did not receive a transmission clearly, or if someone activated the keys outside the range of the receiver. increasing the depth of this code window would allow the decoder to miss a greater number of codes from the generator, and still remain in sync. one method for implementing a code window is to include a microwire? eeprom (such as the nm93cx6) in the decoder design, and store the codes in memory. this becomes even more important if the decoder is designed to accomodate several hisec generator devices. in this case, the decoder should have a code window available for each device. generator clock design parameters table 4, table 5, and table 6 provide a basis for selecting component values for both the rc clocked generator (nm95hs01) and the crystal (xtal) oscillator clocked generator (nm95hs02). the component values shown in the tables have been chosen for low cost, general availability, and reliable operation. components are referenced to the circuit schematics shown in figure 3. though there is some flexibility in selecting alternate values, there are constraints on permissible component values. all resistors and capacitors should be kept within the following ranges; 3 k w r x 200 k w and 50 pf c x 200 pf. table 4. rc clock components, ta = 25 c, v cc = 5vC6.5v r (k w ) c (pf) cki (mhz) cki (ns) 3.3 82 2.12C2.32 470C430 5.6 100 1.1C1.17 870C850
14 nm95hs01/nm95hs02 hisec high security rolling code generator generator clock design parameters (continued) table 4. rc clock components, ta = 25 c, v cc = 5vC6.5v (continued) r (k w ) c (pf) cki (mhz) cki (ns) 6.8 100 0.9C0.95 1100C1050 table 5. rc clock components, ta = 25 c, v cc = 2.5v r (k w ) c (pf) cki (mhz) cki (ns) 3.3 82 1.53C1.6 650C600 5.6 100 0.9C1 1100C1000 6.8 100 0.8C0.83 1250C1200 table 6. xtal clock components, ta = 25 c, v cc = 2.5vC6.5v r1 (m w ) c1 (pf) c2 (pf) cki (mhz) cki (ns) 1 30 30C36 4 250 table 7. nm95hs01/02 eeprom array configuration and definitions parameter bits address function autoresync 1 byte 0, bit 7 allows user to send a sync frame by holding a key down for >10 seconds ledsel 1 byte 0, bit 6 determines whether rfen/led or cko/led is the led connect pin for the nm95hs02 batterytype 1 byte 0, bit 5 selects between 3v and 6v battery voltage timeouten 1 byte 0, bit 4 disables data transmission if key is depressed >80 seconds pause length 2 byte 0, bits 3C2 sets the pause time between data frames during data transmission (pause0/pause1) (0/20/50/100) ms factorydisablebit 1 byte 0, bit 1 disables ability to write to byte 12 writedisablebit 1 byte 0, bit 0 enables/disables ability to write into eeprom array preamblepresent 1 byte 1, bit 7 enables/disables presence of preamble field synctype 1 byte 1, bit 6 determines if sync field is sent in user-selected ir/rf format or default nrz format syncpresent 1 byte 1, bit 5 enables/disables presence of sync field fixsize 1 byte 1, bit 4 determines length of key id field (0/20/24 bits) fixpresent 1 byte 1, bit 3 enables/disables presence of key id field dynsize 1 byte 1, bit 2 determines length of dynamic code field (24/36 bits) paritypresent 1 byte 1, bit 1 enables/disables presence of parity field compareenable 1 byte 1, bit 0 enables/disables low battery detect option bittransmitformat selects among the 12 possible ir/rf bit coding formats irsel 1 byte 2, bit 7 selects between ir and rf bit coding formats prsei2,1,0 3 byte 2, bits 6C4 used with irsei to select particular bit coding format txpol 1 byte 2, bit 3 sets the quiescent output state and data logic level on the tx output pin sclk 1 byte 2, bit 2 determines whether the ir clock or rf clock is used as the bit timing time base prescaler3 6 byte 2, bits 1C0 sets interframe delay time and key debounce time (also generates byte 3, bits 7C4 timeout delay time) prescaler2 6 byte 3, bits 3C0 sets rf clock timing byte 4, bits 7C6 prescaler1 6 byte 4, bits 5C0 sets ir clock timing dynamiccode 24 bytes 5C7 sets initial configuration of the rolling code registers keyidcode 24 bytes 8C10 sets user-configurable key identification register syncfieldcode 8 byte 11 sets configuration of sync field register reserved 8 byte 12 reserved for factory use unique customized algorithm option note: the first bit clocked into the device is byte 0, bit 7. the seventh and eight bits are the chip disable bits. once they are set , and v cc is removed, the chip will be disabled.
15 nm95hs01/nm95hs02 hisec high security rolling code generator absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c input or output voltages with respect to ground all except k1 or k2 -0.5v to +7v k1 or k2 -0.5v to +13v lead temperature (soldering, 10 sec.) +300 c esd rating 2000v ambient operating temperature nm95hs01/nm95hs02 0 c to +70 c nm95hs01e/nm95hs02e -40 c to +85 c power supply (v cc ) range 2.2v to 6.5v nm95hs01/02 dc and ac electrical characteristics 2.2v v cc 6.5v (unless otherwise specified) symbol parameter conditions min typ max units v cc supply voltage 2.5 5.0 6.5 v v rw read/write voltage 4.5 5.0 5.5 v v sv supervoltage (note 2) 11.5 12.0 12.5 v i cc supply current halt mode (3.0v) (note 2) cki = 0 mhz, v cc = 3.0v 0.1 1 m a halt mode (6.0v) cki = 0 mhz, v cc = 6.0v 0.5 2 m a normal mode cki = 4.1 mhz, v cc = 6v 1 3 ma v ih input voltage (high) cki: logic high 0.8 v cc v all others; logic high 0.7 v cc v v il input voltage (low) cki: logic low 0.2 v cc v all others: logic low 0.2 v cc v i p pullup current v cc = 6v, v in = 0v 35 120 250 m a i rf leakage current (rfen) v cc = 6v, rfen = 6v 1 m a i out output current source (push-pull) v cc = 4.5v, v oh = 3.3v 10 ma sink (push-pull) v cc = 4.5v, v ol = 0.4v 15 ma t ps power supply rise time 1 m s 10 m s 10 ms i mp max. sink-source current per pin 20 ma v th comparator threshold voltage batttype = 0 (3v) 2.2 2.4 v batttype = 1 (6v) 4.4 4.8 v t ww k1 initiate write time t ww = t whw +t wlw 40 m s t whw write time high 20 m s t wlw write time low 20 m s t sw k2 setup time 20 m s t hw k2 hold time 20 m s t pw program write time 10 ms t ckihsw supervoltage low to clock high time 10 m s t svlw clock low to supervolt high time 10 m s t xw exit write time 10 m s t dsw data setup time 100 ns t dhw data hold time 100 ns t wr initiate k1 read time t wr = t whr +t wlr 40 m s t whr read time high 20 m s t wlr read time low 20 m s t ckihsr start read time 10 m s t cki clock period time xtal clock 2000 dc ns (note 4) rc clock 2000 dc ns t ckih clock high time xtal clock 1000 dc ns (note 4) rc clock 1000 dc ns t ckil clock low time xtal clock 1000 dc ns (note 4) rc clock 1000 dc ns
16 nm95hs01/nm95hs02 hisec high security rolling code generator nm95hs01/02 dc and ac electrical characteristics (continued) 2.2v v cc 6.5v (unless otherwise specified) symbol parameter conditions min typ max units t dar data access time t dar = t ckih +t dalr 1.1 m s t dalr data access time low 100 ns t endr end read time 10 m s t svlr k1 supervoltage low time (read) 10 m s t xr exit read time 10 m s note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not impli ed. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: the standby current of <1 m a is tested at 3v. during halt mode only a very small current is required to maintain the code in the shift registers. halt mod e is exited by depressing one of the input keys. note 3: the clock rate used to program the nm95hs01/02 is generally less than the normal operating mode clock rate, and should be tempo rarily reduced as necessary to meet the programming specifications shown here. for example, a generator might normally operate at 4 mhz, but should be program med at 0.5 mhz (2000 ns). note 4: parameter characterized but not 100% tested. capacitance (note 2) t a = +25 c, f = 1 mhz symbol test max units c in input capacitance 7 pf c out 0utput capacitance 12 pf typical halt mode current (na) vs voltage over termperature ds012302-23
17 nm95hs01/nm95hs02 hisec high security rolling code generator 8-lead (0.150" wide) molded small outline package, jedec order number nm95hs01m8 or nm95hs02m8 package number m08a 14-lead (0.150" wide) molded small outline package, jedec order number nm95hs01m14 or nm95hs02m14 package number m14a physical dimensions inches (millimeters) unless otherwise noted 123 4567 14 13 12 11 10 9 8 0.335 - 0.344 (8.509 - 8.788) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.014 (0.356) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ. 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
18 nm95hs01/nm95hs02 hisec high security rolling code generator 8-lead dual-in-line package order number nm95hs01n, nm95hs01en, nm95hs02n or nm95hs02en package number n08e 14-lead (0.300" wide) molded dual-in-line package order number nm95hs01n14 or nm95hs02n14 package number n14a physical dimensions inches (millimeters) unless otherwise noted 12 3 4 14 13 12 11 0.335 - 0.344 (8.509 - 8.738) 0.228 - 0.244 (5.791 - 6.198) 0.018 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.014 (0.356) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ. 5 10 6 9 7 8 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident
19 nm95hs01/nm95hs02 hisec high security rolling code generator physical dimensions inches (millimeters) unless otherwise noted 14-lead molded thin shrink small outline package, jedec order number nm95hs01mt14/nm95hs02mt14 package number mtc14 5.0 0.1 3.2 6.4 17 14 8 4.4 0.1 (7.72) typ (4.16) typ (1.78) typ (0.42) typ 0.2 c b a (0.65) typ 0.10 0.05 typ all lead tips 0.65 typ. 1.1 max typ 0.19 - 0.30 typ pin #1 ident 0.9 - 0.20 typ (0.9) 0 -8 0.6 0.1 0.25 seating plane gage plane see detail a dimensions are in millimeters land pattern recommendation detail a typ. scale: 40x - a - - b - - c - 0.13 c s b a s m 0.1 c all lead tips fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm95ms14 plug n play front-end devices for isa-bus systems july 1998 ? 1998 fairchild semiconductor corporation nm95ms14 plug n play front-end devices for isa-bus systems general description the nm95ms14 is the smaller of a family of devices designed to provide complete plug n play capability for isa bus systems. the nm95ms14 includes the necessary state machine logic to man- age the plug n play protocol in addition to switches for steering interrupt and dma requests. it also features a built-in 2k bits of serial eeprom for storing the resource data specified in the plug n play standard. in addition, 4k bits of eeprom is available for use by other on-board logic. this device provides a truly com- plete single-chip solution for implementing plug n play on isa- bus adapter cards. the nm95ms14 supports one logical device with a flexible choice of dma/irq selection and i/o chipselect generation. nm95ms14 is implemented using fairchilds advanced cmos process and operates single power supply. the nm95ms14 is available in a 48-pin tqfp package. block diagram features n complete implementation of plug n play standard direct interface to isa bus n two modes of operation dma mode extended interrupt mode n 6 or 8 isa bus interrupt lines and 2 drq/dack lines supported n on-chip eeprom for resource request table n additional 4 kbits of on-chip eeprom available for external access n 24 ma drivers for data outputs n 48-pin tqfp ds012315-1 address control decoder & control osc rstdrv state machine eeprom register block data buffer microwire port address control from isa bus function module support logic iocs<0:3>* irqx drqx ldackx* lirqx ldrqx dackx* from isa bus to isa bus sd<0:7> isa bus
2 www.fairchildsemi.com nm95ms14 plug n play front-end devices for isa-bus systems connection diagram commercial temperature range (0 c to +70 c) order number nm95ms14vbh signals type description sa<11:0> i address inputs from the isa bus. iord* i i/o read strobe from the isa bus. iowr* i i/o write strobe from the isa bus. aen i address enable from isa bus used in conjunction with dma. sd<7:0> i/o data bus lower byte from/to the isa bus. osc (note 2) i osc clock from the isa bus used for internal state machines. rstdrv i reset input from the isa bus. cs i chip select for microwire port. there should be a pulldown resistor of 4.7k on cs pin if unused externally or directly connected to gnd. sk, di i clock and data input lines for microwire bus connection to access a portion (4k) on chip eeprom. do o data output line for the microwire interface detailed above. irqout<5:0> o connection to isa bus interrupt request pins. on-chip interrupt request(s) may be connected to any 6 of the isa irq lines. irqin<1:0> i interrupt request from on-board logic drqin/iocs2* i dma request from on-board logic, or programmable chipselect (2) depending on mode selected. dackout*/iocs3* o dma acknowledge for on-board logic or programmable chipselect (3) depending on mode selected. isadrq<1:0>/ o connection for two isa bus dma request lines, or additional interrupt request lines irqout<7:6> depending on the mode selected. isadack<1:0>*/ i dma acknowledge from the isa bus or additional address lines depending on the mode sa<13:12> selected. iocs<1:0>* o programmable chip selects to address on-board peripheral. note 1: signal name with a * means its an active low signal. note 2: osc clock from isa bus is fixed at a standard frequency of 14.318 mhz. nm95ms14 is designed and tested for 14.318 mhz. howeve r the nm95ms14 can handle frequencies up to 24 mhz though it is not 100% tested. 15 16 13 14 17 18 19 20 21 22 23 24 28 26 27 29 36 35 34 33 32 31 30 sa0 irqout3 irqout2 irqout1 irqout0 isadrq0/irqout6 isadack0*/sa12 isadack1*/sa13 cs sk sa2 sa3 sa4 sa5 sa7 sa8 sa9 sa10 sa11 gnd sa6 25 9 11 10 81 2 3 4 5 6 7 12 isadrq1/irqout7 irqout4 sa1 irqin0 ioqin1 gnd drqin/iocs2* iowr* iord* iocs0* iocs1* rstdrv dackout*/iocs3* vcc irqout5 sd5 sd4 sd7 sd6 sd3 sd2 sd1 sd0 osc aen do di 37 47 46 45 44 43 41 40 39 38 42 48 nm95ms14 (tqfp) ds012315-2
3 www.fairchildsemi.com nm95ms14 plug n play front-end devices for isa-bus systems pinout details for the nm95ms14 mode 00 = dma mode; mode 01 = extended interrupt mode pin # pin name tqfp dma ext. intr. 1 rstdrv rstdrv 2 iocs1* iocs1* 3 iocs0* iocs0* 4 iord* iord* 5 iowr* iowr* 6v cc v cc 7 drqin iocs2* 8 dackout* iocs3* 9 gnd gnd 10 irqin1 irqin1 11 irqin0 irqin0 12 irqout5 irqout5 13 irqout4 irqout4 14 irqout3 irqout3 15 irqout2 irqout2 16 irqout1 irqout1 17 irqout0 irqout0 18 isadrq0 irqout6 19 isadrq1 irqout7 20 isadack* sa12 21 isadack1* sa13 22 cs cs 23 sk sk 24 sa0 sa0 pin # pin name 25 sa1 sa1 26 sa2 sa2 27 sa3 sa3 28 sa4 sa4 29 gnd gnd 30 sa5 sa5 31 sa6 sa6 32 sa7 sa7 33 sa8 sa8 34 sa9 sa9 35 sa10 sa10 36 sa11 sa11 37 di di 38 do do 39 aen aen 40 osc osc 41 sd0 sd0 42 sd1 sd1 43 sd2 sd2 44 sd3 sd3 45 sd4 sd4 46 sd5 sd5 47 sd6 sd6 48 sd7 sd7 note 3: mode selection (00 or 01) is done by setting ms bits in the eeprom configuration register. detailed information about this is d escribed in users guide.
4 www.fairchildsemi.com nm95ms14 plug n play front-end devices for isa-bus systems absolute maximum ratings (note 4) ambient storage temperature -65 c to +150 c all input or output voltages with respect to ground v cc + 1v to -0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min operating conditions ambient operating temperature nm95ms14 0 c to +70 c positive power supply (v cc ) 4.5v to 5.5v dc electrical characteristics symbol parameter test conditions limits units min typ max (note 5) i cca active power supply current f scl = 100 khz 10.0 ma i li input leakage current v in = gnd or v cc 0.2 1.0 m a i lo output leakage current v out = gnd to v cc 1.0 m a v il input low voltage -0.1 0.8 v v ih input high voltage 2.0 v cc + 1.0 v v ol output low voltage i ol = 24 ma (note 7) 0.4 v i ol = 2.1 ma (note 8) v oh output high voltage i oh = -3 ma (note 7) 2.4 v i oh = -400 m a (note 8) 2.4 v capacitance t a = +25 c, f = 1.0 mhz, v cc = 5v symbol test conditions max units ci/o (note 6) input/output capacitance vi/o = 0v 8 pf c in (note 6) input capacitance v in = 0v 6 pf c out (note 6) output capacitance v out = 0v 6 pf note 4: this footnote is intentionally blank. note 5: typical values are for t a = 25 c and nominal supply voltage (5v). note 6: this parameter is periodically sampled and not 100% tested. note 7: these values are for isa signals like sd[0:7], irqx, drqx. note 8: these values are for card signal like iocs[0:3]*, do(eeprom). ac electrical characteristics symbol parameter min max unit t aen aen valid to command active 100 ns t ac address valid to command active 88 ns t rvd active read to valid data 200 ns t ah address, aen hold from inactive command 30 ns t rdh read data hold from inactive read 5 ns t wd write data valid before write active 22 ns t wdh write data hold after write inactive 25 ns t csa chip selects valid from address valid 5 25 ns t csc chip selects valid from command active 5 25 ns t idd propagation delay for irq/drq/dack 5 25 ns
5 www.fairchildsemi.com nm95ms14 plug n play front-end devices for isa-bus systems timing diagrams (1) timings for isa read/write cycle (2) decode delay for chipselect generation (3) propagation delay for irq/drq/dack dma mode in the dma mode, support is provided for 1. one on-board dma request that is switchable to any two dma channels on the isa bus. 2. two on-board interrupt request lines switchable to any six irq lines on the isa bus. 3. two programmable i/o chip selects for on-board logic. figure 1 shows a block diagram of nm95ms14 configured for dma mode. introduction the nm95ms14 is a single-chip solution for the isa plug n play (pnp) specification. it implements the complete state ma- chine and the necessary logic for supporting configurable interrrupts and dma channels on the isa bus for one logical device. apart from providing plug n play capability, it has built-in eeprom that eliminates external eeprom. this device is available in a space saving 48-pin thin quad flat pack (tqfp) package. functional description nm95ms14 has two modes of operation, viz, dma mode and extended interrupt mode. these modes are programmed using the mode select (ms) bits in one of the configuration registers (refer to the users guide for detailed information). each of these modes are discussed below. aen sa[0:11] iord* iowr* read data sd[0:7] t rdh write data sd[0:7] t ac t ah valid address valid t wd t aen t rvd t wdh iord* iowr* t csc t csc iocs[0:1]* sa[0:11] valid address iocs[0:1]* t csa t csa (qualified with cmd) (addr decode only) irqin drqin isadack irqout drqout dackout t dd t dd ds012315-3 ds012315-4 ds012315-5
6 www.fairchildsemi.com nm95ms14 plug n play front-end devices for isa-bus systems block diagrams figure 1. extended interrupt mode in the ext. int mode, support is provided for: 1. two on-board interrupt request lines switchable to any eight irq lines on the isa bus. 2. four programmable i/o chip selects for on-board logic. 3. isa address sa12 and sa13 are also included for extended decode. figure 2 shows a block diagram of nm95ms14 configured for extended interrupt mode. figure 2. chipselect generation individual i/o chipselect can be generated in the following two ways: a) address decode only b) address decode qualified by command (iord*, iowr*). on-chip eeprom nm95ms14 has 6k of eeprom on chip. all the pnp resource data structure for the logical device is stored in this eeprom. of the 6k bits, 4k bits are available for the logical devices external usage. the logical device can access the eeprom through a microwire port, which is essentially a 4-wire serial bus. the pins cs, sk, di & do follow the exact timing as the standard microwire bus and are compatible to the nm93cxx family of eeproms. eeprom programming the entire 6k bits of eeprom can be programmed through the isa bus. the eeprom can be programmed by putting the device (nm95ms14) in the config. state (as defined in the pnp standard). under this state 4 registers at address 0xf0C0xf3 are accessible to program the eeprom. the data to be programmed is loaded in register at address 0xf3 and 0xf2 (lsb and msb respectively). the address to be programmed is loaded in register at address 0xf1. the ninth bit of address for 6k bits of memory is provided through the register at address 0xf0. both read write are possible. the isa bus scsi / modem / ethernet controllers nm95ms14 drq [0:1] iocs[0:1] cs,sk,di do dackout* drqin irqin0 irqin1 function module 3 2 2 rstdrv osc 2 dack [0:1]* 2 2 6 8 12 3 irqout [0:5] iord* iowr* aen sd[0:7] sa[0:11] eeprom (dma mode) isa bus seria; 1/o multi-media controllers nm95ms14 iocs[0:3] cs,sk,di do irqin0 irqin1 function module 3 2 4 rstdrv osc 2 8 14 3 8 irqout [0:7] iord* iowr* aen sd[0:7] sa[0:13] eeprom (extended interrupt mode) ds012315-6 ds012315-7
7 www.fairchildsemi.com nm95ms14 plug n play front-end devices for isa-bus systems eeprom programming (continued) actual operation does not begin until go ahead (ga) bit is set. programming a word takes approximately 10 ms. the status of the operation can be polled by the status bit. this bit is set when the operation is in progress and will be reset when complete. the registe r at address 0xf0 is command register. this is the handshake register in programming the eeprom and is explained below in a tabular format. command register 0xf0 bit[1:0] - op code bits 10 - read operation 01 - write operation bit[2] ga(go ahead bits) if set to 1 the programming will continue. bit[6:3] - reserved, should be 0. bit[7] - it provides a8 of the address. a[0:7] is provided by 0xf1 reg. (note 9) address register 0xf1 addressregister [a0Ca7] data register 0xf2 data byte [msb] data register 0xf3 data byte [lsb] status register 0x05 bit[0] - status/busy bit 0 is busy, 1 is done. note 9: the pnp resource data portion of the internal memory is at high address. hence to program that portion, bit [7] of register 0xf 0 (address a8) should be set to 1.
8 www.fairchildsemi.com nm95ms14 plug n play front-end devices for isa-bus systems physical dimensions inches (millimeters) unless otherwise noted tqfp package (vbh) package number vbh48a order number nm95ms14vbh fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 1.40 0.05 1.6 max 0.08 seating plane 0.20 min 0.05 - 0.10 12 top and bottom 0 min gage plane r 0.08 ?0.20 0.25 detail a typical see detail a 9.0 0.25 typ 1.0 112 36 25 13 pin #1 ident 24 48 37 0.5 typ. 7.0 0.1 0.60 0.15 0 - 7 0.125 typ optional: sharp corners except pin #1 ident corner
1 www.fairchildsemi.com nm95ms15 plug and play front-end device for isa-bus systems july 1998 ? 1998 fairchild semiconductor corporation nm95ms15 plug and play front-end device for isa-bus systems general description the nm95ms15 is one of the family of single chip solutions designed to provide complete plug and play capability for isa bus systems. the nm95ms15 includes the necessary state machine logic to manage the plug and play protocol in addition to switches for steering interrupt and dma requests. it also features a built-in 4k bits of serial eeprom for storing the resource data specified in the plug and play standard. in addition, 4k bits of the eeprom is available for use by other on-board logic. this device provides a truly complete single-chip solution for implementing plug and play on isa-bus adapter cards. the nm95ms15 supports two logical devices with a flexible choice of dma/irq selection, i/o, and memory chip select generation. nm95ms15 is implemented using fairchilds advanced cmos process and operates from a single power supply. the nm95ms15 is available in a 64-pin tqfp package. functional diagram features n single chip implementation of complete plug and play standard direct interface to isa-bus n three modes of operation normal dma mode extended interrupt mode extended dma mode n 6, 8, or 11 isa-bus interrupt lines and 3 drq/dack lines supported (irqs and drqs are mode dependent) n on-chip eeprom for resource request table n additional 4k bits of on-chip eeprom available for external access n 24 ma drivers for data outputs n 64-pin tqfp package ds012394-1 osc. from isa bus from isa bus to isa bus isa bus rstdrv address control address dackx* lirqx ldrqx control iocs<0:3>* function module support logic state machine decoder & control register block data buffer sd<0:7> microwire port eeprom memcs<0:1>* ldackx* irqx drqx
2 www.fairchildsemi.com nm95ms15 plug and play front-end device for isa-bus systems connection diagram commercial temperature range (0 c to +70 c) order number nm95ms15veh signals type description sa<19:0> i address inputs from the isa bus. iord* (note 1) , smemr* (note 1) i i/o and memory read strobes from the isa bus. iowr* (note 1) , smemw* (note 1) i i/o write and memory write strobes from the isa bus. aen i address enable from isa busused in conjunction with dma. sd<7:0> i/o data buslower bytefrom/to the isa bus. osc (note 2) i osc clock from isa busused for internal state machine. rstdrv i reset input from the isa bus. sk,di i clock and data input lines for microwire bus connection to access a portion (4k) on chip eeprom. cs i chip select for microwire bus connection to access 4k on chip eeprom. this pin should be pulled down to gnd, if the 4k user portion is not used. do o data output line for the microwire interface detailed above. irqout<5:0> o connection to isa bus interrupt request pins. on-chip interrupt requests may be connected to any of the 6 lines. irqout6/drqin1 i/o interrupt request line to the isa bus or dma request line from on-board logic. irqout7/dackout1* (note 1) o interrupt request line to the isa bus or dma ackowledge for on-board logic. irqin<1:0> i interrupt request from on-board logic. drqin0/iocs2* (note 1) i/o dma request from on-board logic or iocs2 depending on mode selected. dackout0*/iocs3* o dma acknowledge for on-board logic or iocs3 depending on mode selected. isadrq<2:0>/irqout<10:8> o connection for three isa bus dma request lines, or additional interrupt request lines depending on the mode selected. isadack<2:0>* (note 1) i dma acknowledge from the isa bus. iocs<1:0>* (note 1) o programmable chip selects to address on-board peripherals memcs<1:0>* (note 1) o programmable chip selects to address on-board rom/memory. note 1: * means active low signal rstdrv iocs1* iocs0* memcs1* memcs0* smemr* smemw* iowr* iord* vcc drqin0/iocs2* dackout0*/iocs3* gnd irqin1 irqin0 irqout5 drqin1/irqout6 dackout1*/irqout7 irqout4 irqout3 irqout2 irqout1 irqout0 isadrq0/irqout8 isadrq1/irqout9 isadrq2/irqout10 isadack0* isadack1* isadack2* cs sk sa0 sa15 sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 gnd sa4 sa3 sa2 sa1 sa16 sa17 di do sa18 sa19 aen osc sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 35 33 34 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 nm95ms15 nm95ms15 (tqpf) ds012394-2
3 www.fairchildsemi.com nm95ms15 plug and play front-end device for isa-bus systems connection diagram (continued) note 2: osc clock from isa bus is fixed at a standard frequency of 14.318 mhz. nm95ms15 is designed and tested for this frequency. ho wever nm95ms15 can handle frequencies up to 24 mhz though it is not 100% tested. pinout details for the nm95ms15 mode 00 = dma mode; mode 01 = extended interrupt mode; mode 10 = extended dma mode pin pin name # tqfp mode 00 mode 01 mode 10 33 sa1 sa1 sa1 34 sa2 sa2 sa2 35 sa3 sa3 sa3 36 sa4 sa4 sa4 37 gnd gnd gnd 38 sa5 sa5 sa5 39 sa6 sa6 sa6 40 sa7 sa7 sa7 41 sa8 sa8 sa8 42 sa9 sa9 sa9 43 sa10 sa10 sa10 44 sa11 sa11 sa11 45 sa12 sa12 sa12 46 sa13 sa13 sa13 47 sa14 sa14 sa14 48 sa15 sa15 sa15 49 sa16 sa16 sa16 50 sa17 sa17 sa17 51 di di di 52 do do do 53 sa18 sa18 sa18 54 sa19 sa19 sa19 55 aen aen aen 56 osc osc osc 57 sd0 sd0 sd0 58 sd1 sd1 sd1 59 sd2 sd2 sd2 60 sd3 sd3 sd3 61 sd4 sd4 sd4 62 sd5 sd5 sd5 63 sd6 sd6 sd6 64 sd7 sd7 sd7 note 3: mode selection (00, 01 or 10) is done by setting ms bits in the eeprom configuration register. detailed information about this is described in users guide. note 4: in mode 01, irqout8, 9, 10 are hardwired to isa bus interrupts irq10, irq11, irq12 respectively. this information supercedes the description in the nm95ms15 users guide. pin pin name # tqfp mode 00 mode 01 mode 10 1 rstdrv rstdrv rstdrv 2 iocs1* iocs1* iocs1* 3 iocs0* iocs0* iocs0* 4 memcs1* memcs1* memcs1* 5 memcs0* memcs0* memcs0* 6 smemr* smemr* smemr* 7 smemw* smemw* smemw* 8 iowr* iowr* iowr* 9 iord* iord* iord* 10 v cc v cc v cc 11 drqin0 iocs2* drqin0 12 dackout0* iocs3* dackout0* 13 gnd gnd gnd 14 irqin1 irqin1 irqin1 15 irqin0 irqin0 irqin0 16 irqout5 irqout5 irqout5 17 irqout6 irqout6 drqin1 18 irqout7 irqout7 dackout1* 19 irqout4 irqout4 irqout4 20 irqout3 irqout3 irqout3 21 irqout2 irqout2 irqout2 22 irqout1 irqout1 irqout1 23 irqout0 irqout0 irqout0 24 isadrq0 irqout8 (note 4) isadrq0 25 isadrq1 irqout9 (note 4) isadrq1 26 isadrq2 irqout10 (note 4) isadrq2 27 isadack0* nc isadack0* 28 isadack1* nc isadack1* 29 isadack2* nc isadack2* 30 cs cs cs 31 sk sk sk 32 sa0 sa0 sa0
4 www.fairchildsemi.com nm95ms15 plug and play front-end device for isa-bus systems absolute maximum ratings (note 5) ambient storage temperature -65 c to +150 c all input or output voltages with respect to ground v cc + 1v to -0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min operating conditions ambient operating temperature nm95ms15 0 c to +70 c positive power supply (v cc ) 4.5v to 5.5v dc electrical characteristics symbol parameter test conditions limits units min typ max (note 6) i cca active power supply current f scl = 100 khz 6 20 ma i li input leakage current v in = gnd to v cc 0.2 15 m a i lo output leakage current v out = gnd to v cc 15 m a v il input low voltage -0.1 0.8 v v ih input high voltage 2.0 v cc + 1.0 v v ol output low voltage i ol = 24 ma (note 8) 0.4 v i ol = 2.1 ma (note 9) v oh output high voltage i oh = -3 ma (note 8) 2.4 v i oh = -400 m a (note 9) 2.4 v capacitance t a = +25 c, f = 1.0 mhz, v cc = 5v symbol test conditions max units c i/o (note 7) input/output capacitance v i/o = 0v 8 pf c in (note 7) input capacitance v in = 0v 6 pf c out (note 7) output capacitance v out = 0v 6 pf note 5: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not impli ed. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 6: typical values are for t a = 25 c and nominal supply voltage (5v). note 7: this parameter is periodically sampled and not 100% tested. note 8: these values are for isa signals sd[0:7], irqx, drqx. note 9: these values are for card signal iocs[0:3]*, memcs[0:1]*, do(eeprom). ac electrical characteristics symbol parameter min max unit t aen aen valid to command active 100 ns t ac address valid to command active 88 ns t rvd active read to valid data 200 ns t ah address, aen hold from inactive command 30 ns t rdh read data hold from inactive read 5 ns t wd write data valid before write active 22 ns t wdh write data hold after write inactive 25 ns t csa chip selects valid from address valid 5 25 ns t csc chip selects valid from command active 5 25 ns t idd propagation delay for irq/drq/dack 5 25 ns
5 www.fairchildsemi.com nm95ms15 plug and play front-end device for isa-bus systems resource allocation amongst the two logical devices nm95ms15 supports two plug n play logical devices: logical device #0, and logical device #1. the total resource structure suppo rted by the nm95ms15 is allocated to each of these logical devices as follows: mode 00 logical device #0 logical device #1 1) i/o chipselects iocs0* iocs1* 2) memory chipselects memcs0* memcs1* 3) local irq input irqin0 irqin1 4) local dqr input drqin0 CCC mode 01 logical device #0 logical device #1 1) i/o chipselects iocs0* and iocs2* iocs1* and iocs3* 2) memory chipselects memcs0* memcs1* 3) local irq input irqin0 irqin1 mode 10 logical device #0 logical device #1 1) i/o chipselects iocs0* iocs1* 2) memory chipselects memcs0* memcs1* 3) local irq input irqin0 irqin1 4) local dqr input drqin0 drqin1
6 www.fairchildsemi.com nm95ms15 plug and play front-end device for isa-bus systems (1) timings for isa read/write cycle (2) decode delay for chip select generation note: cmd? means iord*, iowr*, smemr* and smemw* (3) propagation delay for irq/drq/dack aen sa[0:19] iord* iowr* read data sd[0:7] t rdh write data sd[0:7] t ac t ah valid address valid t wd t aen t rvd t wdh cmd? t csc t csc iocs[0:3]* memcs[0:1] sa[0:19] valid address iocs[0:3]* memcs[0:1] t csa t csa (qualified with cmd) (addr decode only) t idd irqin drqin isadack irqout drqout dackout t idd ds012394-3 ds012394-4 ds012394-5
7 www.fairchildsemi.com nm95ms15 plug and play front-end device for isa-bus systems introduction the nm95ms15 is a single-chip solution for the isa plug and play (pnp) specification. it implements the complete state machine and the necessary logic for supporting configurable interrupts and dma channels on the isa bus for one logical device. apart from providing pnp capability, it has built-in eeprom that eliminates external eeprom. this device is available in a space saving 64- pin thin quad flat pack (tqfp) package. functional description nm95ms15 has three modes of operation, viz, normal dma mode, extended interrupt mode and extended dma mode. these modes are programmed using the mode select (ms) bits in one of the configuration registers (refer to the users guide for detailed information). each of these modes are discussed below. normal dma mode in the normal dma mode, support is provided for 1. one on-board dma request that is switchable to any three dma channels on the isa bus. 2. two on-board interrupt request lines switchable to any eight irq lines on the isa bus. 3. two programmable i/o chip selects for on-board logic. 4. two programmable memory chip selects for on-board logic. figure 1 shows a block diagram of nm95ms15 configured for normal dma mode. figure 1. extended interrupt mode in the ext. int mode, support is provided for: 1. two on-board interrupt request lines switchable to any eleven irq lines on the isa bus. 2. four programmable i/o chip selects for on-board logic. 3. two programmable memory chip selects for on-board logic. figure 2 shows a block diagram of nm95ms15 configured for extended interrupt mode. isa bus scsi/modem/ethernet controllers nm95ms15 iocs[0:1]* memcs[0:1]* dackout0* drqin0 cs,sk,di do irqin0 irqin1 function module 2 3 2 rstdrv osc 2 irqout [0:7] 8 smemr* smemw* iow* ior* aen 5 sd[0:7] 8 sa[0:19] dack [0:2] 3 drq [0:2] 3 20 eeprom (normal dma mode) ds012394-6
8 www.fairchildsemi.com nm95ms15 plug and play front-end device for isa-bus systems figure 2. extended dma mode in the extended dma mode, support is provided for: 1. two on-board dma request that is switchable to any three dma channels on the isa bus. 2. two on-board interrupt request lines switchable to any six irq lines on the isa bus. 3. two programmable i/o chip selects for on-board logic. 4. two programmable memory chip selects for on-board logic. figure 3 shows a block diagram of nm95ms15 configured for extended dma mode. figure 3. chip select generation individual i/o or memory chip select can be generated in the following two ways: a) address decode only b) address decode qualified by command (iord*, iowr* or smemr*, smemw*). on-chip eeprom nm95ms15 has 8k bits of eeprom on chip. all the pnp resource data structure for the logical device is stored in this eeprom. of the 8k bits, 4k bits are available for the logical devices external usage. the logical device can access the eeprom through a microwire port, which is essentially a 4-wire serial bus. the pins cs, sk, di & do follow the exact timing as the standard microwire bus and are compatible to the nm93cxx family of eeproms. eeprom programming the entire 8k bits of eeprom can be programmed throughthe isa bus. the eeprom can be programmed by puttingthe device (nm95ms15) in the configuration state (as definedin the pnp standard). under this state 4 registers at address 0xf0C0xf3 are accessible to program the eeprom. the data to be programmed is loaded in register at address 0xf3 and 0xf2 (lsb and msb isa bus scsi/modem/ethernet controllers nm95ms15 iocs[0:1]* memcs[0:1]* dackout[0:1] drqin[0:1] cs,sk,di do irqin0 irqin1 function module 3 2 224 rstdrv osc 2 irqout [0:5] 6 smemr* smemw* iow* ior* aen 5 sd[0:7] 8 sa[0:19] dack [0:2] 3 drq [0:2] 3 20 eeprom (extended dma mode) isa bus serial i/o /multi-media controllers nm95ms15 iocs[0:3] memcs[0:1] cs,sk,di do irqin0 irqin1 function module 2 6 3 rstdrv osc 2 irqout [0:10] 11 smemr* smemw* iow* ior* aen 5 sd[0:7] 8 sa[0:19] 20 eeprom (extended interrupt mode) ds012394-7 ds012394-8
9 www.fairchildsemi.com nm95ms15 plug and play front-end device for isa-bus systems ninth bit of address for 8k bits of memory is provided through the register at address 0xf0. both read write are possible. the actual operation does not begin until go ahead (ga) bit is set. program- ming a word takes approximately 10 ms. the status of the operation can be polled by the status bit. this bit is set when the operation is in progress and will be reset when complete. the register at address 0xf0 is the command register. this is the handshake register in programming the eeprom and is ex- plained below in a tabular format. command register 0xf0 bit[1:0] - op code bits 10 - read operation 01 - write operation bit[2] ga(go ahead bits) if set to 1 the programming will continue. bit[6:3] - reserved, should be 0. bit[7] - it provides a8 of the address. a[0:7] is provided by 0xf1 reg. (note 10) status register 0x05 bit[0] - status/busy bit during programming 0 is busy, 1 is done. address register 0xf1 address register [a0Ca7] data register 0xf2 data byte [msb] data register 0xf3 data byte [lsb] note 10: the pnp resource data portion of the internal memory is at high address. hence to program that portion, bit [7] of register 0xf 0 (a8) should be set to 1.
10 www.fairchildsemi.com nm95ms15 plug and play front-end device for isa-bus systems physical dimensions inches (millimeters) unless otherwise noted tqfp packages (veh) order number nm95ms15veh package number veh64a 12.0 0.2 typ 10.0 0.1 17 32 64 49 33 48 16 1 0.5 typ. 0.22 0.05 typ. 1.40 0.05 see detail a 0.125 typ 0.5 - 0.15 0.08 seating plane 1.6 max detail a typical 1.0 0.60 +0.15 0.20 min gage plane 0 min 0 -7 11 -13 top & bottom r 0.08 min r 0.08 - 0.20 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm95ms16 plug and play front-end devices for isa-bus systems july 1998 ? 1998 fairchild semiconductor corporation nm95ms16 plug and play front-end devices for isa-bus systems general description the nm95ms16 is the smaller of a family of devices designed to provide complete plug and play capability for isa bus systems. the nm95ms16 includes the necessary state machine logic to manage the plug and play protocol in addition to switches for steering interrupt and dma requests. it also features a built-in 2 kbits of serial eeprom for storing the resource data specified in the plug and play standard. in addition, 4 kbits of eeprom is available for use by other on-board logic. this device provides a truly complete single-chip solution for implementing plug and play on isa-bus adapter cards. the nm95ms16 supports one logical device with a flexible choice of dma/irq selection and i/o chipselect generation as well as offering 16-bit addressing in mode 1. nm95ms16 is implemented using fairchilds advanced cmos process and operates single power supply. the nm95ms16 is available in a 48-pin tqfp package and 52-pin plcc package. block diagram features n complete implementation of plug and play standard direct interface to isa bus n two modes of operation dma mode extended interrupt mode ( windows ? 95 logo compatible) n 6 or 8 isa bus interrupt lines and 2 drq/dack lines supported n on-chip eeprom for resource request table n additional 4 kbits of on-chip eeprom available for external access n 24 ma drivers for data outputs n complete compliance to isa pnp specification (ver. 1.0a) n 48-pin tqfp, and 52-pin plcc packages ds012601-1 windows ? 95 is a registered trademark of microsoft corporation. osc. from isa bus from isa bus to isa bus isa bus rstdrv address control address dackx* lirqx ldrqx control iocs<0:2>* function module support logic state machine decoder & control register block data buffer sd<0:7> microwire port eeprom ldackx* irqx drqx
2 www.fairchildsemi.com nm95ms16 plug and play front-end devices for isa-bus systems connection diagrams commercial temperature range (0 c to +70 c) order number nm95ms16vbh order number nm95ms16v sa0 irqout4 irqout3 irqout2 irqout1 irqout0 isadrq0/irqout6 isadrq1/irqout7 isadack0*/sa12 isadack1*/sa13 cs sk di sd7 sd6 sd5 sd4 sd2 sd1 sd0 osc aen do sd3 rstdrv irqout5 irqin0 irqin1/sa14 gnd drqin/sa15 v cc iowr* iord* iocs0* iocs1* dackout*/iocs2* sa11 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 gnd 12 1 2 3 4 5 6 7 8 9 10 11 24 13 14 15 16 17 18 19 20 21 22 23 37 48 47 46 45 44 43 42 41 40 39 38 25 36 35 34 33 32 31 30 29 28 27 26 nm95ms16 (tqfp) 1 2 3 4 5 6 7 12 9 10 11 13 14 15 16 17 18 19 20 36 48 46 45 44 43 42 41 40 39 38 37 24 22 23 25 33 32 31 30 29 28 27 26 sa0 irqout3 irqout2 irqout1 irqout0 isadrq0/irqout6 isadrq1/irqout7 isadack0*/sa12 isadack1*/sa13 cs sk sd7 sd6 sd5 sd4 sd2 sd1 sd0 osc aen do sd3 irqout5 irqin0 irqin1/sa14 gnd drqin/isa15 vcc iowr* iord* iocs0* iocs1* dackout*/iocs2* sa11 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 gnd 51 52 50 49 35 34 nc nc nc 47 21 8 nc di irqout4 rstdrv sa1 nm95ms16 (plcc) ds012601-2 ds012601-3
3 www.fairchildsemi.com nm95ms16 plug and play front-end devices for isa-bus systems connection diagrams (continued) signals type description sa<11:0> i address inputs from the isa bus. iord* i i/o read strobe from the isa bus. iowr* i i/o write strobe from the isa bus. aen i address enable from isa bus used in conjunction with dma. sd<7:0> i/o data bus lower byte from/to the isa bus. osc (note 1) i osc clock from the isa bus used for internal state machines. rstdrv i reset input from the isa bus. cs i chip select for microwire port. there should be a pull down resistor of 4.7k on cs pin if unused externally, or directly connected to gnd. sk, di i clock and data input lines for microwire bus connection to access a portion (4k) on chip eeprom. do o data output line for the microwire interface detailed above. irqout<5:0> o connection to isa bus interrupt request pins. on-chip interrupt request(s) may be connected to any 6 of the isa irq lines. irqin<1:0> i interrupt request from on-board logic drqin/sa<15> i dma request from on-board logic, or address input from isa bus depending on mode selected. dackout* /iocs2* o dma acknowledge for on-board logic or programmable chipselect (2) depending on mode selected. isadrq<1:0>/irqout<7:6> o connection for two isa bus dma request lines, or additional interrupt request lines depending on the mode selected. isadack<1:0>*/sa<13:12> i dma acknowledge from the isa bus or additional address lines depending on the mode selected. iocs<1:0>* o programmable chip selects to address on-board peripheral. irqin<1>/sa<14> i interrupt request from on board logic or address input from isa bus depending on mode selected. *signal name with a * means its an active low signal. note 1: osc clock from isa bus is fixed at a standard frequency of 14.318 mhz. nm95ms16 is designed and tested for 14.318 mhz. howeve r nm95ms16 can handle frequencies up to 24 mhz though it is not 100% tested.
4 www.fairchildsemi.com nm95ms16 plug and play front-end devices for isa-bus systems pinout details for the nm95ms16 mode 00 = dma mode; mode 01 = extended interrupt mode tqfp pin dma mode ext.intr.mode 1 rstdrv rstdrv 2 iocs1* iocs1* 3 iocs0* iocs0* 4 iord* iord* 5 iowr* iowr* 6v cc v cc 7 drqin sa15 8 dackout* iocs2* 9 gnd gnd 10 irqin1 sa14 11 irqin0 irqin0 12 irqout5 irqout5 13 irqout4 irqout4 14 irqout3 irqout3 15 irqout2 irqout2 16 irqout1 irqout1 17 irqout0 irqout0 18 isadrq0 irqout6 19 isadrq1 irqout7 20 isadack0* sa12 21 isadack1* sa13 22 cs cs 23 sk sk 24 sa0 sa0 tqfp pin dma mode ext.intr.mode 25 sa1 sa1 26 sa2 sa2 27 sa3 sa3 28 sa4 sa4 29 gnd gnd 30 sa5 sa5 31 sa6 sa6 32 sa7 sa7 33 sa8 sa8 34 sa9 sa9 35 sa10 sa10 36 sa11 sa11 37 di di 38 do do 39 aen aen 40 osc osc 41 sd0 sd0 42 sd1 sd1 43 sd2 sd2 44 sd3 sd3 45 sd4 sd4 46 sd5 sd5 47 sd6 sd6 48 sd7 sd7 note: mode selection (00 or 01) is done by setting ms bits in the eeprom configuration register. detailed information about this is d escribed in users guide.
5 www.fairchildsemi.com nm95ms16 plug and play front-end devices for isa-bus systems absolute maximum ratings (note 2) ambient storage temperature -65 c to +150 c all input or output voltages with respect to ground v cc + 1v to -0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min operating conditions ambient operating temperature nm95ms16 0 c to +70 c positive power supply (v cc ) 4.5v to 5.5v dc electrical characteristics symbol parameter test conditions limits units min typ max (note 3) i cca active power supply current f scl = 100 khz 15 ma i li input leakage current v in = gnd or v cc 0.2 15 m a i lo output leakage current v out = gnd to v cc 15 m a v il input low voltage -0.1 0.8 v v ih input high voltage 2.0 v cc + 1.0 v v ol output low voltage i ol = 24 ma (note 5) 0.4 v i ol = 2.1 ma (note 6) v oh output high voltage i oh = -3 ma (note 5) 2.4 v i oh = -400 m a (note 6) 2.4 v capacitance t a = +25 c, f = 1.0 mhz, v cc = 5v symbol test conditions max units ci/o (note 4) input/output capacitance vi/o = 0v 8 pf cin (note 4) input capacitance vin = 0v 6 pf cout (note 4) output capacitance vout = 0v 6 pf note 2: stress above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 3: typical values are for t a = 25 c and nominal supply voltage (5v). note 4: this parameter is periodically sampled and not 100% tested. note 5: these values are for isa signals like sd[0:7], irqx, drqx. note 6: these values are for card signal like iocs[0:3]*, do(eeprom). ac electrical characteristics symbol parameter min max unit t aen aen valid to command active 100 ns t ac address valid to command active 88 ns t rvd active read to valid data 200 ns t ah address, aen hold from inactive command 30 ns t rdh read data hold from inactive read 5 ns t wd write data valid before write active 22 ns t wdh write data hold after write inactive 25 ns t csa chip selects valid from address valid 5 25 ns t csc chip selects valid from command active 5 25 ns t idd propagation delay for irq/drq/dack 5 25 ns
6 www.fairchildsemi.com nm95ms16 plug and play front-end devices for isa-bus systems timing diagrams timings for isa read/write cycle decode delay for chipselect generation propagation delay for irq/drq/dack introduction the nm95ms16 is a single-chip solution for the isa plug and play (pnp) specification. it implements the complete state machine and the necessary logic for supporting configurable interrrupts and dma channels on the isa bus for one logical device. apart from providing pnp capability, it has built-in eeprom that eliminates external eeprom. this device is available in a space saving 48-pin thin quad flat pack (tqfp) package. functional description nm95ms16 has two modes of operation, viz, dma mode and extended interrupt mode. these modes are programmed using the mode select (ms) bits in one of the configuration registers (refer to the nm95ms16 users guide for detailed information). each of these modes are discussed below. dma mode in the dma mode, support is provided for 1. one on-board dma request that is switchable to any two dma channels on the isa bus. 2. two on-board interrupt request lines switchable to any six irq lines on the isa bus. 3. two programmable i/o chip selects for on-board logic. figure 1 shows a block diagram of nm95ms16 configured for dma mode. aen sa[0:11] iord* iowr* read data sd[0:7] t rdh write data sd[0:7] t ac t ah valid address valid t wd t aen t rvd t wdh iord* iowr* t csc t csc iocs[0:1]* sa[0:11] valid address iocs[0:1]* t csa t csa (qualified with cmd) (addr decode only) t idd irqin drqin isadack irqout drqout dackout t idd ds012601-4 ds012601-5 ds012601-6
7 www.fairchildsemi.com nm95ms16 plug and play front-end devices for isa-bus systems introduction (continued) figure 1. extended interrupt mode in the ext.int. mode, support is provided for: 1. two on-board interrupt request lines switchable to any eight irq lines on the isa bus. 2. three programmable i/o chip selects for on-board logic. 3. isa address sa12Csa15 are also included for extended decode. figure 2 shows a block diagram of nm95ms16 configured for extended interrupt mode. figure 2. chipselect generation individual i/o chipselect can be generated in the following two ways: a) address decode only b) address decode qualified by command (iord*, iowr*). on-chip eeprom nm95ms16 has 6 kbits of eeprom on chip. all the pnp resource data structure for the logical device is stored in this eeprom. of the 6 kbits, 4 kbits are available for the logical devices external usage. the logical device can access the eeprom through a microwire port, which is essentially a 4-wire serial bus. the pins cs, sk, di and do follow the exact timing as the standard microwire bus and are compatible to the nm93cxx family of eeproms. isa bus scsi/modem/ethernet controllers nm95ms16 iocs[0:1] dackout* drqin cs,sk,di do irqin0 irqin1 function module 2 3 2 rstdrv osc 2 irqout [0:5] 6 iord* iowr* aen 3 sd[0:7] 8 sa[0:11] dack [0:1] 2 drq [0:1] 2 12 eeprom (dma mode) isa bus serial i/o /multi-media controllers nm95ms16 iocs[0:2] cs,sk,di do irqin0 function module 1 3 4 rstdrv osc 2 irqout [0:7] 8 iord* iowr* aen 3 sd[0:7] 8 sa[0:15] 16 eeprom (extended interrupt mode) ds012601-7 ds012601-8
8 www.fairchildsemi.com nm95ms16 plug and play front-end devices for isa-bus systems introduction (continued) eeprom programming the entire 6 kbits of eeprom can be programmed through the isa bus. the eeprom can be programmed by putting the device (nm95ms16) in the config. state (as defined in the pnp standard). under this state 4 registers at address 0xf0C0xf3 are accessible to program the eeprom. the data to be programmed is loaded in register at address 0xf3 and 0xf2 (lsb and msb respectively). the address to be programmed is loaded in register at address 0xf1. the ninth bit of address for 6 kbits of memory is provided through the register at address 0xf0. both read write are possible. the actual operation does not begin until go ahead (ga) bit is set. programming a word takes approximately 10 ms. the status of the operation can be polled by the status bit. this bit is set when the operation is in progress and will be reset when complete. the register at address 0xf0 is command register. this is the handshake register in programming the eeprom and is ex- plained below in a tabular format. command register 0xf0 bit[1:0] op code bits 10 - read operation 01 - write operation 11 - erase operation bit[2] ga(go ahead bits) if set to 1 the programming will continue. bit[6:3] reserved, should be 0. bit[7] it provides a8 of the address. a[0:7] is provided by 0xf1 reg. (note 7) address register 0xf1 addressregister [a0Ca7] data register 0xf2 data byte [msb] data register 0xf3 data byte [lsb] status register 0x05 bit[0] status/busy bit. 0 if busy, 1 is done. note 7: the pnp resource data portion of the internal memory is at high address. hence to program that portion, bit [7] of register 0xf 0 (address a8) should be set to 1.
9 www.fairchildsemi.com nm95ms16 plug and play front-end devices for isa-bus systems 52-lead molded plastic leaded chip carrier package number v52a order number nm95ms16v physical dimensions inches (millimeters) unless otherwise noted 45 x 0.045 [1.14] 0.785 - 0.795 [19.94 - 20.19] 0.600 [15.24] typ 0.050 [1.27] typ 1 7 8 20 21 33 34 46 52 pin 1 ident 47 0.750 - 0.756 [19.05 - 19.20] 0.026?.032 [0.66?.81] 0.013?.021 [0.33?.53] 0.045 [1.14] 0.020 [0.51] 0.690?.730 [17.53?8.54] 0.090?.130 [2.29?.30] typ typ min typ typ 0.165?.180 [4.19?.57] typ typ 45 x
10 www.fairchildsemi.com nm95ms16 plug and play front-end devices for isa-bus systems physical dimensions inches (millimeters) unless otherwise noted tqfp package (vbh) package number vbh48a order number nm95ms16vbh 1.40 0.05 1.6 max 0.08 seating plane 0.20 min 0.05 - 0.10 12 top and bottom 0 min gage plane r 0.08 ?0.20 0.25 detail a typical see detail a 9.0 0.25 typ 1.0 112 36 25 13 pin #1 ident 24 48 37 0.5 typ. 7.0 0.1 0.60 0.15 0 - 7 0.125 typ optional: sharp corners except pin #1 ident corner fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nm95ms18 plug 'n' play front end device for isa-bus systems july 1998 ? 1998 fairchild semiconductor corporation nm95ms18 plug & play front-end device for isa-bus systems (supports windows ? -nt, unix ? and legacy systems) general description the nm95ms18 is an industry standard isa plug-n-play control- ler that also supports non-plug-n-play platforms like dos, win3.1x, windows-nt and unix. in additon to being completely compliant to isa pnp specification (ver 1.0a), nm95ms18 integrates a total of 4kbit of onchip eeprom for both pnp resource data as well as non-pnp configuration data to provide a true single chip solution. nm95ms18 supports one logical device offering a flexible choice of dma, interrupt and i/o address decoding features within a single chip. nm95ms18 is implemented using fairchilds ad- vanced cmos process and operates on a single power supply. features n fully compliant with industry standard isa pnp specification (ver. 1.0a) block diagram n supports non-pnp platforms like windows-nt, unix, dos/win3.1x no configuration utilities needed n supports non-pnp "legacy" mode can be programmed to power-up in 31 settings n on-chip "write-protected" eeprom for: pnp resource data (2kbits) 31 power-on "legacy" configurations (2kbits) n two modes of operation: dma mode extended interrupt mode (supports pc-97 requirements) n configurable interrupt types: ttl o/p open drain o/p n supports wire-and i/o chipselects n fully compatible with nm95ms16 n available in 52-pin plcc package ds500033-1 pnp cycle detection logic state machine eeprom irq switch logic data buffer registers dma switch logic address decoder input sense logic test mode logic from switches npnp sw[0:4] isa bus rstdrv sa[0:11] iord iowr aen osc irqout[0:7] sd[0:7] isadrq[0:1] isadack[0:1] sa[0:15] iord iowr aen iocs[0:2] dackout drqin irqin[0:1] controller i/f
2 www.fairchildsemi.com nm95ms18 plug 'n' play front end device for isa-bus systems * signal name with a * indicates active low signal. ? multiplexed signals. please refer pinout details. block signal description signal type description sa[0:11] i address inputs from the isa bus. sa[12:15]? i address inputs from the isa bus. iord* i i/o read strobe from the isa bus. iowr* i i/o write strobe from the isa bus. aen i address enable strobe from isa bus. osc i 14.31818 mhz clock source from isa bus. rstdrv i reset signal from isa bus. sd[0:7] i/o isa data bus. irqin0 i source interrupt signal from onboard controller. irqin1? i source interrupt signal from onboard controller. irqout[0:5] o interrupt output signals from nm95ms18. can be connected to any of isa irq channels. irqout[6:7] ? o interrupt output signals from nm95ms18. can be connected to any of isa irq channels. drqin? i source dma request signal from onboard controller to nm95ms18. isadrq[0:1] ? o dma request output signals from nm95ms18. can be connected to any of isa dma channels. isadack[0:1]* ? i dma acknowledge output signals from respective isa dma channels to which isadrq[0:1] are connected. dackout* ? i dma acknowledge signal from nm95ms18 to onboard controller. iocs[0:1]* o programmable chipselects from nm95ms18 to onboard controller. iocs[2]* ? o programmable chipselects from nm95ms18 to onboard controller. n_p 'n' p* i input signal selecting either pnp mode or n_pnp mode of nm95ms18. this signal has a weak internal pull-up resistor defaulting to pnp mode and can be directly connected to ground . this signal is used in conjunction with sw[0:4] inputs. 1 - pnp mode. 0 - n_pnp mode. sw[0:4] i input signals to nm95ms18 selecting 1-out-of-31 non-plug-n-play configurations. all these signals have a weak internal pull-up resistor and can be directly connected to ground. these signals are used in conjunction with n_pnp signal. plcc pins irqout4 irqout3 irqout2 irqout1 irqout0 isadrq0 n_pnp* isadrq1 isadack0* isadack1* sw0 sw1 sa0 sd7 sd6 sd5 sd4 sd3 sd2 sw4 sd1 sd0 osc aen sw3 sw2 irqout5 irqin0 irqin1 gnd dackout* drqin nc iowr* v cc iord* iocs0* iocs1* rstdrv sa1 sa2 sa3 sa4 gnd sa5 nc sa6 sa7 sa8 sa9 sa10 sa11 1 525150494847 2 3 4 5 6 7 27 28 29 30 31 32 33 26 25 24 23 22 21 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 ds500033-2
3 www.fairchildsemi.com nm95ms18 plug 'n' play front end device for isa-bus systems pin # pin name mode dma ext. intr 1nc nc 2** (note 3) drqin sa15 3** dackout* iocs2* 4 gnd gnd 5** irqin1 sa14 6 irqin0 irqin0 7 irqout5 irqout5 8 irqout4 irqout4 9 irqout3 irqout3 10 irqout2 irqout2 11 irqout1 irqout1 12 irqout0 irqout0 13** isadrq0 irqout6 14 n_pnp n_pnp 15** isadrq1 irqout7 16** isadack0* sa12 17** isadack1* sa13 18 sw0 sw0 19 sw1 sw1 20 sa0 sa0 21 sa1 sa1 22 sa2 sa2 23 sa3 sa3 24 sa4 sa4 25 gnd gnd 26 sa5 sa5 ** pins with multiplexed signals pinout details for nm95ms18 (plcc package) pin # pin name mode dma ext. intr 27 nc nc 28 sa6 sa6 29 sa7 sa7 30 sa8 sa8 31 sa9 sa9 32 sa10 sa10 33 sa11 sa11 34 sw2 sw2 35 sw3 sw3 36 aen aen 37 osc osc 38 sd0 sd0 39 sd1 sd1 40 sw4 sw4 41 sd2 sd2 42 sd3 sd3 43 sd4 sd4 44 sd5 sd5 45 sd6 sd6 46 sd7 sd7 47 rstdrv rstdrv 48 iocs1* iocs1* 49 iocs0* iocs0* 50 iord* iord* 51 iowr* iowr* 52 v cc v cc
4 www.fairchildsemi.com nm95ms18 plug 'n' play front end device for isa-bus systems absolute maximum ratings (note 1) ambient storage temperature C65 c to +150 c all input or output voltages with respect to ground v cc + 1v to C0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm95ms18 0 c to +70 c positive power supply (v cc ) 4.5v to 5.5v note 1: absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. the databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. fairchild does not recommend operation outside databook sepcifications. dc electrical characteristics limits symbol parameter test conditions min typ max units (note 2) i cca active power supply current f scl = 100 khz tbd 10.0 ma i li input leakage current v in = gnd to v cc 0.2 1.0 m a i lo output leakage current v out = gnd to v cc 1.0 m a v il input low voltage -0.1 0.8 v v ih input high voltage 2.0 v cc + 1.0 v v ol output low voltage i ol = 24 ma (note 4) 0.4 v i ol = 2.1 ma (note 5) v oh output high voltage i oh = -3 ma (note 4) 2.4 v i oh = -400 m a (note 5) 2.4 v capacitance t a = +25 c, f = 1.0 mhz, v cc = 5v symbol test conditions min max units c i/o (note 3) input/output capacitance v i/o = 0v 8 pf c in (note 3) input capacitance v in = 0v 6 pf c out (note 3) output capacitance v out = 0v 6 pf note 2: typical values are for t a = 25 c and nominal supply voltage (5v). note 3 : this parameter is periodically sampled and not 100% tested. note 4 : these values are for isa signals like sd[0:7], irqx, drqx. note 5 : these values are for card signal like iocs[0:2]*, do(eeprom) ac electrical characteristics symbol parameter min max unit t aen aen valid to command active 100 ns t ac address valid to command active 88 ns t rvd active read to valid data 150 ns t ah address, aen hold from inactive command 30 ns t rdh read data hold from inactive read 5 ns t wd write data valid before write active 22 ns t wdh write data hold after write inactive 25 ns t csa chip selects valid from address valid 5 20 ns t csc chip selects valid from command active 5 20 ns t idd propagation delay for irq/drq/dack 5 20 ns
5 www.fairchildsemi.com nm95ms18 plug 'n' play front end device for isa-bus systems sa[0:15] iocs[0:1]* (addr decode only) iord* iowr* iocs[0:1]* (qualfied with cmd) valid address t csa t csa t csc t csc irq in drq in isadack irq out drq out dackout t idd t idd aen sa[0:15] iord* iowr* read data sd[0:7] write data sd[0:7} t rdh t ah t wd t wdh valid valid address t aen t ac t rvd timing diagrams timings for isa read/write cycle ds500033-3 ds500033-4 ds500033-5 decode delay for chipselect generation propagation delay for irq/drq/dack introduction nm95ms18 supports both plug-n-play platforms (pc with win- dows-95 and/or pnp bios) as well as non-plug-n-play plat- forms (pc with windows-nt, win3.x/dos and non-pnp bios). the choice of interface (pnp or non-pnp) is selected by using a single pin (n_pnp*). under pnp interface, nm95ms18 is fully compliant with isa plug-n-play specification (ver 1.0a) and is functionally compatible to its predecessor nm95ms16. under non-p 'n' p interface, nm95ms18 powers-up active with a prede- termined configuration eliminating any need for an external pnp configuration support. five external inputs to nm95ms18 allows to choose the default power-up configuration from 31 different predetermined configurations. nm95ms18 integrates 2 kbits of on-board eeprom to store all the 31 configuration information as well as an additional 2 kbits eeprom area to store standard pnp resource information. entire memory can be write protected. nm95ms18 also allows isa interrupts to be shared.
6 www.fairchildsemi.com nm95ms18 plug 'n' play front end device for isa-bus systems functional description as mentioned above, nm95ms18 can be configured for either plug-n-play environment or non-plug-n-play environment. under either interface, nm95ms18 provides a choice from 2 operating modes, viz, dma mode or extended interrupt mode offering additional flexibility in selecting a suitable set of features for a particular application. mode selection is made by setting ap- propriate bits in the " i/o decode qualification " register in onboard eeprom. refer to " nm95ms18 user's guide " for more detail. each of these modes is explained below. dma mode in the dma mode, nm95ms18 provides the following features: 1. two programmable i/o chipselects (iocs0*and iocs1*) each of which can be set to be decoded off of isa address isa bus switch v cc iocso 10k iocs1 sw4 sw3 sw2 sw1 sw0 npnp* nm95ms18 (dma mode) sound controller irqin[0:1] drqin dackout 10k rstdrv osc iord* iowr* aen sa[0:11] sd[0:7] irqout[0:5] isadrq[0:1] isadack[0:1] on off gnd dma mode ds500033-6 sa[0:11] and iord*/iowr* or just by sa[0:11] . in addition iocs1* signal can be internally wire-anded with iocs0* signal, to provide "output enable" signal for isa bus data buffers. 2. two local interrupt request signals switchable to any six irq channels on the isa bus. choice of actual isa irq channels selected is user dependent. also the type of the six irq outputs can be independently set to be either standard ttl type or open-drain type . selecting open-drain type allows interrupts to be shared on the isa bus. 3. one local dma request signal switchable to any two dma channels on the isa bus. choice of actual isa dma channels selected is user dependent. following figure shows a typical system block diagram of nm95ms18 used in dma mode. dma mode extended interrupt mode (supports pc-95/pc-97 requirements) in extended interrupt mode, nm95ms18 provides these features: 1. three programmable i/o chipselects (iocs0*, iocs1* and iocs2*) each of which can be set to be decoded off of isa address sa[0:11] and and iord*/iowr* or by just isa address bus only. in addition iocs1* and iocs2* signals can be internally wire-anded with iocs0* signal, to provide "output enable" signal for isa bus data buffers. 2. one on-board interrupt request signals switchable to any eight irq channels on the isa bus. choice of actual isa irq channels selected is user dependent. also the type of the eight irq outputs can be independently set to be either standard ttl type or open-drain type . selecting open- drain type allows interrupts to be shared on the isa bus. following figure shows a typical system block diagram of nm95ms18 used in extended interrupt mode.
7 www.fairchildsemi.com nm95ms18 plug 'n' play front end device for isa-bus systems extended interrupt mode (supports pc-95/pc-97 requirements) ds500033-7 isa bus switch v cc iocs0 iocs1 sw4 sw3 sw2 sw1 sw0 npnp* nm95ms18 (extended interrupt mode) isdn controller iocs1 irqin0 rstdrv osc iord* iowr* aen sa[0:15] sd[0:7] irqout[0:5] 10k on off gnd extended interrupt mode configuration #31 configuration #3 iocs0 (msb) iocs1 (msb) iocs2 (msb) irqin1 irqin0 irqin1 type irqin0 type x drqin bit[2:0] bit[3] bit[5:4] bit[7:6] bit[3:0] bit[7:4] iocs0 (lsb) word iocs1 (lsb) 8 bytes/ configuration iocs2 (lsb) configuration #2 configuration #1 ds500033-8 interface options of nm95ms18 plug-n-play/non-plug-n-play) 1) plug-n-play (pnp) interface ("/n_pnp" = 1) in a plug-n-play environment, a pnp configuration manager (typically pnp-bios, windows95 os or pnp utility) that resides on the pc would read the plug-n-play resource data fileand allocate the requested resource (i/o address space, irq etc). pnp configuration is actually a defined process of updating defined pnp registers on a pnp controller in a defined manner. the entire protocol and register summary is provided in the isa pnp specification (ver 1.0a). nm95ms18 is designed to be completely compliant with the existing isa pnp standard and hence provides seamless pnp support for an isa adapter. all that is required is to prepare the plug-n-play resource data for an applicatduring power-up, nm95ms18 defaults to plug-n-play interface if it senses logic "high" at the "n_pnp*" pin. this pin has an internal weak pullup logic and hence can be left unconnected for pnp interface. 2) non-plug-n-play (legacy) interface ("/n_pnp" = 0) in a legacy interface nm95ms18 is designed to ignore the standard pnp configuration protocol and instead self-configure to a specific configuration. a specific configuration is selected by a set of switch inputs sw[0:4]. all possible combinations of these 5 inputs provide 31 configurations to choose from (the 32nd configu- ration is reserved for field programming. refer section on "soft- ware write configuration" for more detail). it is also possible to use fewer than five switch inputs (sw[0:3], sw[0:2], sw[0:1] or sw[0] to have fewer legacy configurations (15, 7, 3 or 1 respectively). all these five switch inputs have weak internal pull-up resistor allow- ing unused switch pins to be left unconnected when necessary. during power-up, nm95ms18 defaults to legacy interface if it senses logic low at the n_p 'n' p* pin. along with n_p 'n' p* pin, the state of sw[0:4] inputs are also sensed to determine the particular legacy configuration that needs to be selected. each legacy configuration occupies 8 bytes (4 words) of internal memory as shown in the following figure.
8 www.fairchildsemi.com nm95ms18 plug 'n' play front end device for isa-bus systems interface options of nm95ms18 (plug- n-play/non-plug-n-play) (continued) configuration #1 (first configuration) is stored at the bottom 8 bytes (higher address) of the memory and is selected when the sw[0:4] input reflects a 01111 combination. following table describes all the configuration information with respect to sw[0:4] values and internal memory address. configuration /n_pnp sw[0:4] memory location memory location number signal combination (word address) (byte address) configuration #1 0 0-1-1-1-1 0xfc - 0xff 0x1f8 - 0x1ff configuration #2 0 1-0-1-1-1 0xf8 - 0xfb 0x1f0 - 0x1f7 configuration #3 0 0-0-1-1-1 0xf4 - 0xf7 0x1e8 - 0x1ef configuration #4 0 1-1-0-1-1 0xf0 - 0xf3 0x1e0 - 0x1e7 configuration #5 0 0-1-0-1-1 0xec - 0xef 0x1d8 - 0x1df configuration #6 0 1-0-0-1-1 0xe8 - 0xeb 0x1d0 - 0x1d7 configuration #7 0 0-0-0-1-1 0xe4 - 0xe7 0x1c8 - 0x1cf configuration #8 0 1-1-1-0-1 0xe0 - 0xe3 0x1c0 - 0x1c7 configuration #9 0 0-1-1-0-1 0xdc - 0xdf 0x1b8 - 0x1bf configuration #10 0 1-0-1-0-1 0xd8 - 0xdb 0x1b0 - 0x1b7 configuration #11 0 0-0-1-0-1 0xd4 - 0xd7 0x1a8 - 0x1af configuration #12 0 1-1-0-0-1 0xd0 - 0xd3 0x1a0 - 0x1a7 configuration #13 0 0-1-0-0-1 0xcc - 0xcf 0x198 - 0x19f configuration #14 0 1-0-0-0-1 0xc8 - 0xcb 0x190 - 0x197 configuration #15 0 0-0-0-0-1 0xc4 - 0xc7 0x188 - 0x18f configuration #16 0 1-1-1-1-0 0xc0 - 0xc3 0x180 - 0x187 configuration #17 0 0-1-1-1-0 0xbc - 0xbf 0x178 - 0x17f configuration #18 0 1-0-1-1-0 0xb8 - 0xbb 0x170 - 0x177 configuration #19 0 0-0-1-1-0 0xb4 - 0xb7 0x168 - 0x16f configuration #20 0 1-1-0-1-0 0xb0 - 0xb3 0x160 - 0x167 configuration #21 0 0-1-0-1-0 0xac - 0xaf 0x158 - 0x15f configuration #22 0 1-0-0-1-0 0xa8 - 0xab 0x150 - 0x157 configuration #23 0 0-0-0-1-0 0xa4 - 0xa7 0x148 - 0x14f configuration #24 0 1-1-1-0-0 0xa0 - 0xa3 0x140 - 0x147 configuration #25 0 0-1-1-0-0 0x9c - 0x9f 0x138 - 0x13f configuration #26 0 1-0-1-0-0 0x98 - 0x9b 0x130 - 0x137 configuration #27 0 0-0-1-0-0 0x94 - 0x97 0x128 - 0x12f configuration #28 0 1-1-0-0-0 0x90 - 0x93 0x120 - 0x127 configuration #29 0 0-1-0-0-0 0x8c - 0x8f 0x118 - 0x11f configuration #30 0 1-0-0-0-0 0x88 - 0x8b 0x110 - 0x117 configuration #31 0 0-0-0-0-0 0x84 - 0x87 0x108 - 0x10f software write 0 1-1-1-1-1 --
9 www.fairchildsemi.com nm95ms18 plug 'n' play front end device for isa-bus systems internal eeprom memory of nm95ms18 nm95ms18 has a total of 4kbits (512 bytes) onboard eeprom. of the 512 bytes, a mimimum of 264 bytes are allocated for storing plug-n-play resource data and the remaining 248 bytes can be used for storing up to 31 different default power-on non- pnp configurations (a.k.a. legacy configurations ). as shown in the above figure, depending on the number of legacy configura- tions supported (can be 31 or 15 or 7 or 3 or 1 or 0), the space for storing plug-n-play resource data can be extended to 512 bytes. software write configuration under non-pnp mode when sw[0:4] inputs reflect a 1-1-1-1-1 pattern, nm95ms18 selects a configuration called software write. primary use of this configuration is to allow field program- ming of the internal memory. need for a field programming might arise if the predetermined 31 legacy configurations are ex- hausted and needs to be updated with a new set of 31 (or less) legacy configurations. software-write configuration overrides the general write-protection (refer write-protection section) of- fered by nm95ms18, temporarily. under this software write configuration the nm95ms18 ex- pects an extended lfsr key which is nothing but the regular 32 byte writes of lfsr sequence (as defined in the pnp specifica- tion) followed by a 33rd byte write where the value is 0x9c. once the 33rd write is detected, nm95ms18 will automatically transtition to the config state of pnp mode where programming of internal memory is enabled. in this configuration nm95ms18 selects isa address 0x203 as the default read_data_port, by default. write protection nm95ms18 offers write-protection for the entire 4kbits of internal memory. protection is enabled by setting bit[15] of the i/ o decode qualification register to 0. setting this bit to 1 disables write-protection. under software write configuration this bit is overridden and write-protection is disabled. programming of onchip eeprom the entire 4kbit internal eeprom can be programmed through the isa bus or through microwire interface (test mode). each method is explained below. programming through isa bus this method is suited for in-circuit programmin where nm95ms18 is assembled on the isa board before programming. nm95ms18 is shipped with a 1 pattern at all its bit locations from factory. this means it is shipped with write-protection disabled. depending whether the write-protection is enabled or not there are two procedures to program the onchip memory. each of these two procedures are explained below. programming when "write-protection" is disabled follow the procedure defined in isa plug-n-play specification (ver. 1.0 a) to place nm95ms18 in "config" mode of plug-n-play protocol. once the device is is config state, programming of internal eeprom is enabled. programming is done by first setting the address of the location, data(16bit) to be programmed and then the "go ahead" bit to start the programming. a bit in the status register provides the status of the operation. a program- ming utility is also available from fairchild. following table summarizes all the registers involved during programming. pnp memory (264 bytes) using 31 non-pnp configurations non-pnp config memory (248 bytes) pnp memory (392 bytes) using 15 non-pnp configurations non-pnp config memory (120 bytes) pnp memory (456 bytes) using 7 non-pnp configurations non-pnp config memory (56 bytes) pnp memory (512 bytes) no non-pnp configurations ?? 512 bytes (4 k-bits) ds500033-9
10 www.fairchildsemi.com nm95ms18 plug 'n' play front end device for isa-bus systems internal eeprom memory of nm95ms18 (continued) programming interface programming eeprom register name register definition status and command register 0xf0 bit[1:0} op code bits 10 - read operation 01 - write operation 11 - erase operation bit [2] - ga (go ahead bits) if set to 1, the programming will continue bit [7:3] - reserved, should be 0 address register 0xf1 address register [a0 - a7] data register 0xf2 data byte [msb] data register 0xf3 data byte [lsb] status register 0x05 bit [0]: status/busy bit during programming, 0 is busy, 1 is done restdrv irqin0 sw0 100 ns 100 ns 100 ns 300 ns 5v 5v 12v 100 ns 500 ns 500 ns start of standard micro-wire access ds500033-10 programming when write-protec- tion is enabled in this case, programming is enabled when n_pnp* pin is 0 and the sw[0:4] inputs are 11111. programming procedure is same as programming when write-protection is disabled with the ex- ception of lfsr sequence. in this case 33-byte extended-lsfr should be used instead of 32-byte lfsr. programming through microwire interface (test mode) this method is suited when nm95ms18 is pre-programmed before board assembly. this method involves using special test mode of nm95ms18. once the device is in test mode, the entire internal memory can be programmed like a standard micro-wire eeprom. the protocol to place the device in test-mode makes use of the following three signals, viz. resetdrv, irqin0 and sw0. the timing diagram is shown below. note: all timings shown here are minimum values.
11 www.fairchildsemi.com nm95ms18 plug 'n' play front end device for isa-bus systems internal eeprom memory of nm95ms18 (continued) details of timing information for microwire protocol can be ob- tained from fairchilds microwire eeprom datasheets. please refer nm93c66 datasheet. this datasheet can be downloaded from fairchilds home page on world-wide-web. (http:// www.fairchildsemi.com) sharing of interrupts interrupt output (irqoutx) signals from nm95ms18 can be configured as either standard ttl type or open-drain type. interrupt outputs configured as open-drain type can share an interrupt on the isa bus. sharing of interrupt increases isa bus base address for iocs0 iocs1* wire-anded with iocs0* base address for iocs1 base address for iocs2 sa[0:15] iord*/iowr iocs0* iocs1* iocs2* iocs2* wire-anded with iocs0* ds500033-11 resource allocation probabilities and also allows presence of multiple cards of the same type. each irqoutx signal can be individually set for either interrupt type and this is done by setting appropriate bits in eeprom register. refer the users guide for more detail. wire-anding of i/o chipselects the iocs1* and iocs2* signals can be internally wire-anded with iocs0* signal on nm95ms18. when this feature is enabled, iocs0* signal can also act as output enable signal for isa bus data buffers eliminating extra glue logic on the board. setting appropriate bits in eeprom register enables this feature. refer the users guide for more detail. following diagram illustrates this feature. wire-anding of i/o chipselects note 1: this illustratory waveform assumes that both iocs1* and iocs2* are set to be wire-anded with iocs0*. they can also be set indiv idually. note 2: in this waveform, iocsx* are set to be decoded off of address and iord*/iowr. note 3: refer i/o decode qualification register description for more information.
12 www.fairchildsemi.com nm95ms18 plug 'n' play front end device for isa-bus systems physical dimensions inches (millimeters) unless otherwise noted 52 lead molded plastic leaded chip carrier package number v52a 45 x 0.045 [1.14] 0.785 - 0.795 [19.94 - 20.19] 0.600 [15.24] typ 0.050 [1.27] typ 1 7 8 20 21 33 34 46 52 pin 1 ident 47 0.750 - 0.756 [19.05 - 19.20] 0.026?.032 [0.66?.81] 0.013?.021 [0.33?.53] 0.045 [1.14] 0.020 [0.51] 0.690?.730 [17.53?8.54] 0.090?.130 [2.29?.30] typ typ min typ typ 0.165?.180 [4.19?.57] typ typ 45 x fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
1 www.fairchildsemi.com nmc27c16b rev. c nmc27c16b 16,384-bit (2048 x 8) cmos eprom nmc27c16b 16,384-bit (2048 x 8) cmos eprom general description the nmc27c16b is a high performance 16k uv erasable and electrically reprogrammable cmos eprom, ideally suited for applications where fast turnaround, pattern experimentation and low power consumption are important requirements. the nmc27c16b is packaged in a 24-pin dual-in-line package with a quartz window. the quartz window allows the user to expose the chip to ultraviolet light to erase the bit pattern. a new pattern can then be written into the device by following the programming procedure. this eprom is fabricated with fairchilds proprietary, time proven cmos double-poly silicon gate technology which combines high performance and high density with low power consumption and excellent reliability. block diagram january 1999 features n low cmos power consumption active power: 55 mw max standby power: 0.55 mw max n extended temperature range available, -40 c to +85 c n fast and reliable programming (100 m s for most bytes) n ttl compatible inputs/outputs n tri-state ? output n manufacturers identification code for automatic program- ming equipment n high current cmos level output drivers n upgrade for nmos 2716 ? 1999 fairchild semiconductor corporation output enable, chip enable, and program logic y decoder x decoder . . . . . . . . . output buffers 16,384-bit cell matrix data outputs o 0 - o 7 v cc gnd v pp oe ce/pgm a 0 - a 10 address inputs ds009180-1
2 www.fairchildsemi.com nmc27c16b rev. c nmc27c16b 16,384-bit (2048 x 8) cmos eprom connection diagram note: socket compatible eprom pin configurations are shown in the blocks adjacent to the nmc27c16b pins. top view order number nmc27c16bq see package number j24aq ds009180-2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c256 27256 27c128 27128 v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd nmc27c16b dual-in-line-package v cc a 8 a 9 v pp oe a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c32 2732 v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c64 2764 27c128 27128 27c256 27256 v cc pgm a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc pgm nc a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc a 8 a 9 a 11 oe/v pp a 10 ce o 7 o 6 o 5 o 4 o 3 27c32 2732 27c64 2764 commercial temp. range (0 c to 70 c) v cc = 5v 10% parameter/order number access time (ns) nmc27c16bq150 150 nmc27c16bq200 200 extended temp. range (-40 c to +85 c) v cc = 5v 10% parameter/order number access time (ns) nmc27c16bqe200 200 pin names a0Ca10 addresses ce/pgm chip enable/program oe output enable o0 Co7 outputs nc no connect
3 www.fairchildsemi.com nmc27c16b rev. c nmc27c16b 16,384-bit (2048 x 8) cmos eprom absolute maximum ratings (note 1) temperature under bias commercial parts -10 c to +80 c extended temp. parts -40 c to +85 c storage temperature -65 c to +150 c v cc supply with respect to ground +7.0v to -0.6v all input voltages except a9 with respect to ground (note 10) +6.5v to -0.6v all output voltages with respect to ground (note 10) v cc +1.0v to gnd - 0.6v v pp supply and a9 voltage with respect to ground +14.0v to -0.6v power dissipation 1.0w lead temp. (soldering, 10 sec.) 300 c operating conditions (note 8) temperature range nmc27c16bq150, 200 0 c to +70 c nmc27c16bqe 200 -40 c to +85 c v cc power supply +5v 10% read operation dc electrical characteristics symbol parameter conditions min typ max units (note 11) i li input load current v in = v cc or gnd 0.1 1 m a i lo output leakage current v out = v cc or gnd, ce = v ih 0.1 1 m a i cc1 v cc current (active) ce = v il , f=5 mhz (note 3) ttl inputs inputs = v ih or v il 520ma i/o = 0 ma i cc2 v cc current (active) ce = gnd, f = 5 mhz (note 3) cmos inputs inputs = v cc or gnd, 3 10 ma i/o = 0 ma i ccsb1 v cc current (standby) ce = v ih 0.1 1 ma ttl inputs i ccsb2 v cc current (standby) ce = v cc 0.5 100 m a cmos inputs i pp v pp load current v pp = 5.5v 10 m a v il input low voltage -0.2 0.8 v v ih input high voltage 2.0 v cc +1 v v ol1 output low voltage i ol = 2.1 ma 0.45 v v oh1 output high voltage i oh = -400 ma 2.4 v v ol2 output low voltage i ol = 10 m a 0.1 v v oh2 output high voltage i oh = -10 m av cc - 0.1 v ac electrical characteristics nmc27c16b symbol parameter conditions q150 q200, qe200 units min max min max t acc address to output delay ce = oe = v il 150 200 ns t ce ce to output delay oe = v il 150 200 ns t oe oe to output delay ce = v il 60 60 ns t df oe high to output float ce = v il 0 50 0 60 ns t cf ce high to output float oe = v il 0 50 0 60 ns t oh output hold from addresses, oe = oe = v il 00ns ce or oe , whichever occurred first
4 www.fairchildsemi.com nmc27c16b rev. c nmc27c16b 16,384-bit (2048 x 8) cmos eprom capacitance t a =+25?c, f = 1 mhz (note 4) symbol parameter conditions typ max units c in input capacitance v in = 0v 6 12 pf c out output capacitance v out = 0v 9 12 pf ac test conditions output load (note 12) 1 ttl gate and c l = 100 pf input rise and fall times 5 ns input pulse levels 0.45v to 2.4v timing measurement reference level inputs 0.8v and 2v outputs 0.8v and 2v ac waveforms (note 2) (note 9) note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . note 3: v pp may be connected to v cc except during programming. i cc1 the sum of the i cc active and i pp read currents. note 4: this parameter is only sampled and is not 100% tested. note 5: oe may be delayed up to t acc - t oe after the falling edge of ce without impact on t acc . note 6: the t df and t cf compare level is determined as follows: high to tri-state, the measured v oh1 (dc) - 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 7: tri-state may be attained using oe or ce . note 8: the power switching characteristics of eproms require careful device decoupling. it is recommended that a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. note 9: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 10: inputs and outputs can undershoot to -2.0v for 20 ns maximum. note 11: typical values are for t a = 25 c and nominal supply voltages. note 12: 1 ttl gate: i dl = 1.6 ma, i oh = 400 m a. c l : 100 pf includes fixture capacitance address valid valid output hi-z 2v 0.8v 2v 0.8v 2v 0.8v address output ce oe t ce 2v 0.8v (note 5) (note 5) t df t oe (note 6, 7) (note 6, 7) t oh hi-z t oe acc t cf t ds009180-3
5 www.fairchildsemi.com nmc27c16b rev. c nmc27c16b 16,384-bit (2048 x 8) cmos eprom programming characteristics (note 13) (note 14) (note 15) (note 16) symbol parameter conditions min typ max units t as address setup time 1 m s t oes oe setup time 1 m s t ds data setup time 1 m s t vcs v cc setup time 1 m s t vps v pp setup time 1 m s t ah address hold time 0 m s t dh data hold time 1 m s t df output enable to output float delay ce/pgm = v il 060ns t pw program pulse width 95 100 105 m s t oe data valid from oe ce/pgm = v il 150 ns i pp v pp supply current during ce = v ih 30 ma programming pulse oe = v ih i cc v cc supply current 10 ma t a temperature ambient 20 25 30 c v cc power supply voltage 6.0 6.25 6.5 v v pp programming supply voltage 12.5 12.75 13.0 v t fr input rise, fall time 5 ns v il input low voltage 0.0 0.45 v v ih input high voltage 3.0 4.0 v t in input timing reference voltage 0.8 2.0 v t out output timing reference voltage 0.8 2.0 v note 13: fairchilds standard product warranty applies only to devices programmed to specifications described herein. note 14: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 15: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v pp , v cc to gnd to suppress spurious voltage transients which may damage the device. note 16: programming and program verify are tested with the fast program algorithm, at typical power supply voltages and timings. the mi n and max limit parameters are design parameters, not tested or guaranteed. programming waveforms ds009180-4 t as t ah program program verify address stable t df data out valid data in stable hi-z t ds t dh t vcs t vps t pw t oes t oe 2v 0.8v 2v 0.8v 6.25v 12.75v 2v 0.8v 0v 0v address data v cc ce/pgm oe v pp
6 www.fairchildsemi.com nmc27c16b rev. c nmc27c16b 16,384-bit (2048 x 8) cmos eprom fast programming algorithm flow chart figure 1. yes no start addr = first location v cc = 6.25 v v pp = 12.75v x = 0 program one 100 s pulse increment x x = 20 ? verify byte device failed fail pass pass last address increment addr fail yes no 1st v cc = v pp =5.5v 2nd v cc = v pp =4.5v device failed fail pass device passed verify byte ds009180-5
7 www.fairchildsemi.com nmc27c16b rev. c nmc27c16b 16,384-bit (2048 x 8) cmos eprom functional description device operation the six modes of operation of the nmc27c16b are listed in table i. it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and v pp . the v pp power supply must be at 12.75v during the three programming modes, and must be at v cc in the other modes. the v cc power supply must be at 6.25v during the three programming modes, and at 5v in the other modes. read mode the nmc27c16b has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs t oe after the falling edge of oe , assuming that ce has been low and addresses have been stable for at least t acc - t oe . the sense amps are clocked for fast access time. v cc should therefore be maintained at operating voltage during read and verify. if v cc temporarily drops below the spec. voltage (but not to ground) an address transition must be performed after the drop to insure proper output data. standby mode the nmc27c16b has a standby mode which reduces the active power dissipation by 99%, from 100 mw to 0.50 mw. the nmc27c16b is placed in the standby mode by applying a cmos high signal to the ce input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output or-tying because nmc27c16bs are usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ce (pin 18) be decoded and used as the primary device selecting function, while oe (pin 20) be made a common connec- tion to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on pin 21 (v pp ) will damage the nmc27c16b. initially, and after each erasure, all bits of the nmc27c16b are in the 1 state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be pro- grammed, both 1s and 0s can be presented in the data word. the only way to change a 0 to a 1 is by ultraviolet light erasure. the nmc27c16b is in the programming mode when the v pp power supply is at 12.75v and oe is at v ih . it is required that at least a 0.1 m f capacitor be placed across v pp , v cc to ground to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 8 bits in parallel to the data output pins. when the address and data are stable, an active high, ttl program pulse is applied to the ce/pgm input. a program pulse must be applied at each address location to be programmed. the nmc27c16b is programmed with the fast programming algorithm shown in figure 1. each address is programmed with a series of 100 m s pulses until it verifies good, up to a maximum of 25 pulses. most memory cells will program with a single 100 m s pulse. the nmc27c16b must not be programmed with a dc signal applied to the ce/pgm input. programming multiple nmc27c16bs in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. like inputs of the paralleled nmc27c16bs may be connected together when they are pro- grammed with the same data. a high level ttl pulse applied to the ce/pgm input programs the paralleled nmc27c16bs. table 1. mode selection pins ce/pgm oe v pp v cc outputs mode (18) (20) (21) (24) (9-11), (13-17) read v il v il v cc 5d out standby v ih dont care v cc 5 hi-z output disable dont care v ih v cc 5 hi-z program v ih v ih 12.75v 6.25 d in program verify v il v il 12.75v 6.25 d out program inhibit v il v ih 12.75v 6.25 hi-z program inhibit programming multiple nmc27c16bs in parallel with different data is also easily accomplished. except for ce/pgm all like inputs (including oe) of the parallel nmc27c16bs may be com- mon. a ttl high level program pulse applied to an nmc27c16bs ce/pgm input with v pp at 12.75v will program that nmc27c16b. a ttl low level ce/pgm input inhibits the other nmc27c16bs from being programmed.
8 www.fairchildsemi.com nmc27c16b rev. c nmc27c16b 16,384-bit (2048 x 8) cmos eprom functional description (continued) program verify a verify should be performed on the programmed bits to determine whether they were correctly programmed. the verify may be performed with v pp at 12.75v. except during programming and program verify, v pp must be at v cc . manufacturers identification code the nmc27c16b has a manufacturers identification code to aid in programming. the code, shown in table 3, is two bytes wide and is stored in a rom configuration on the chip. it identifies the manufacturer and the device type. the code for the nmc27c16b is, 8f80, where 8f designates that it is made by fairchild semiconductor, and 80 designates a 16k part. the code is accessed by applying 12.0v 0.5v to address pin a9. addresses a1Ca8, a10, ce , and oe are held at v il . address a0 is held at v il for the manufacturers code, and at v ih for the device code. the code is read out on the 8 data pins. proper code access is only guaranteed at 25 c 5 c. the primary purpose of the manufacturers identification code is automatic programming control. when the device is inserted in an eprom programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. erasure characteristics the erasure characteristics of the nmc27c16b are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms (?). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000? C 4000? range. after programming, opaque labels should be placed over the nmc27c16b window to prevent unintentional erasure. covering the window will also prevent temporary functional failure due to the generation of photo currents. the recommended erasure procedure for the nmc27c16b is exposure to short wave ultraviolet light which has a wavelength of 2537?. the integrated dose (i.e., uv intensity x exposure time) for erasure should be a mimimum of 15 w-sec/cm 2 . the nmc27c16b should be placed within 1 inch of the lamp tubes during erasure. some lamps have a filter on their tubes which should be removed before erasure. table 2 shows the minimum nmc27c16b erasure time for various light intensities. an erasure system should be calibrated periodically. the distance from lamp to unit should be maintained at one inch. the erasure time increases as the square of the distance. (if distance is doubled the erasure time increases by a factor of 4.) lamps lose intensity as they age. when a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. incomplete erasure will cause symptoms that can be misleading. programmers, compo- nents, and even system designs have been erroneously sus- pected when incomplete erasure was the problem. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc , has three segments that are of interest to the system designerthe standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent on the output capacitance loading the device. the associated v cc tran- sient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces. table 2. minimum nmc27c16b erasure time light intensity erasure time (micro-watts/cm 2 ) (minutes) 15,000 20 10,000 25 5,000 50 table 3. manufacturers identification code pins a0 o7 o6 o5 o4 o3 o2 o1 o0 hex (8) (17) (16) (15) (14) (13) (11) (10) (9) data manufacturer code v il 10 0011 118f device code v ih 10 0000 0080
9 www.fairchildsemi.com nmc27c16b rev. c nmc27c16b 16,384-bit (2048 x 8) cmos eprom physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 uv window cavity dual-in-line package (q) order number nmc27c16bq package number j24aq 1.260 max 24 1 13 12 r 0.025 r 0.030-0.055 typ 0.270 ?0.290 uv window 0.590-0.620 0.180 max 0.060-0.100 typ 0.050-0.060 typ 0.015-0.021 typ glass sealant 0.020 -0.070 typ 0.10 max 0.090-0.110 typ 0.225 max typ 0.125 min typ 90 - 100 typ 0.685 +0.025 -0.060 0.008-0.015 typ 0.514 ?0.526
1 www.fairchildsemi.com nmc27c32b rev. c nmc27c32b 32,768-bit (4096 x 8) cmos eprom nmc27c32b 32,768-bit (4096 x 8) cmos eprom general description the nmc27c32b is a 32k uv erasable and electrically reprogrammable cmos eprom, ideally suited for applications where fast turnaround, pattern experimentation and low power consumption are important requirements. the nmc27c32b is designed to operate with a single +5v power supply with 10% tolerance. the nmc27c32b is packaged in a 24-pin dual-in-line package with a quartz window. the quartz window allows the user to expose the chip to ultraviolet light to erase the bit pattern. a new pattern can then be written electrically into the device by following the programming procedure. this eprom is fabricated with fairchilds proprietary, time proven cmos double-poly silicon gate technology which combines high performance and high density with low power consumption and excellent reliability. block diagram january 1999 features n low cmos power consumption active power: 55 mw max standby power: 0.55 mw max n industrial temperature range, -40 c to +85 c n fast and reliable programming n ttl, cmos compatible inputs/outputs n tri-state ? output n manufacturers identification code for automatic program- ming n high current cmos level output drivers n compatible with nmos 2732 ds008827-1 ? 1998 fairchild semiconductor corporation output enable, chip enable, and program logic y decoder x decoder . . . . . . . . . output buffers 32,768-bit cell matrix data outputs o 0 - o 7 v cc gnd v pp oe ce a 0 - a 11 address inputs
2 www.fairchildsemi.com nmc27c32b rev. c nmc27c32b 32,768-bit (4096 x 8) cmos eprom connection diagram note: socket compatible eprom pin configurations are shown in the blocks adjacent to the nmc27c32b pin. order number nmc27c32bq see package number j24aq 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c256 27256 27c128 27128 v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd nmc27c32b dual-in-line-package v cc a 8 a 9 a 11 oe/v pp a 10 ce o 7 o 6 o 5 o 4 o 3 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c16 2716 v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c64 2764 27c128 27128 27c256 27256 v cc pgm a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc a 14 a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc pgm nc a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc a 8 a 9 v pp oe a 10 ce o 7 o 6 o 5 o 4 o 3 27c16 2716 27c64 2764 ds008827-2 pin names a0Ca11 addresses ce chip enable oe output enable v pp programming voltage o0 Co7 outputs v cc power supply gnd ground commercial temp range (0 c to +70 c) v cc = 5v 10% parameter/order number access time (ns) nmc27c32bq150 150 nmc27c32bq200 200 industrial temp range (-40 c to +85 c) v cc = 5v 10% parameter/order number access time (ns) nmc27c32bqe200 200
3 www.fairchildsemi.com nmc27c32b rev. c nmc27c32b 32,768-bit (4096 x 8) cmos eprom absolute maximum ratings (note 1) temperature under bias -40 c to +85 c storage temperature -65 c to +150 c v cc supply voltage with respect to ground +7.0v to -0.6v all input voltages except a9 and oe/v pp with respect to ground (note 9) +6.5v to -0.6v all output voltages with respect to ground (note 9) v cc +1.0v to gnd-0.6v oe/v pp supply and a9 voltage with respect to ground +14.0v to -0.6v power dissipation 1.0w lead temperature (soldering, 10 sec.) 300 c operating conditions (note 6) temperature range nmc27c32bq150, 200 0 c to +70 c nmc27c32bqe 200 -40 c to +85 c v cc power supply +5v 10% read operation dc electrical characteristics symbol parameter conditions min typ max units i li input load current v in = v cc or gnd 0.01 1 m a i pp oe/v pp load current oe/v pp = v cc or gnd 10 m a i lo output leakage current v out = v cc or gnd, ce = v ih 0.01 1 m a i cc1 v cc current (active) ce = v il , f=5 mhz 5 20 ma ttl inputs inputs = v ih or v il , i/o = 0 ma i cc2 v cc current (active) ce = gnd, f = 5 mhz 3 10 ma cmos inputs inputs = v cc or gnd, i/o = 0 ma i ccsb1 v cc current (standby) ce = v ih 0.1 1 ma ttl inputs i ccsb2 v cc current (standby) ce = v cc 0.5 100 m a cmos inputs v il input low voltage -0.2 0.8 v v ih input high voltage 2.0 v cc +1 v v ol1 output low voltage i ol = 2.1 ma 0.45 v v oh1 output high voltage i oh = -400 m a 2.4 v v ol2 output low voltage i ol = 10 m a 0.1 v v oh2 output high voltage i oh = -10 m av cc - 0.1 v ac electrical characteristics nmc27c32b symbol parameter conditions q150 q200, qe200 units min max min max t acc address to output delay ce = oe = v il 150 200 ns t ce ce to output delay oe = v il 150 200 ns t oe oe to output delay ce = v il 60 60 ns t df oe high to output float ce = v il 0 50 0 60 ns t cf ce high to output float oe = v il 0 50 0 60 ns t oh output hold from addresses, ce = oe = v ce or oe , whichever 0 0 ns occurred first
4 www.fairchildsemi.com nmc27c32b rev. c nmc27c32b 32,768-bit (4096 x 8) cmos eprom capacitance (note 2) t a = +25 c, f = 1 mhz symbol parameter conditions typ max units c in1 input capacitance except oe/v pp v in = 0v 6 12 pf c in2 oe/v pp input capacitance v in = 0v 16 20 pf c out output capacitance v out = 0v 9 12 pf ac test conditions output load 1 ttl gate and c l = 100 pf (note 8) input rise and fall times 5 ns input pulse levels 0.45v to 2.4v timing measurement reference level inputs 0.8v and 2v outputs 0.8v and 2v ac waveforms (note 7) note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: this parameter is only sampled and is not 100% tested. note 3: oe may be delayed up to t acc - t oe after the falling edge of ce without impacting t acc . note 4: the t df and t cf compare level is determined as follows: high to tri-state, the measured v oh1 (dc) - 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 5: tri-state may be attained using oe or ce . note 6: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. note 7: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 8: 1 ttl gate: i ol = 1.6 ma, i oh = -400 m a c l : 100 pf includes fixture capacitance. note 9: inputs and outputs can undershoot to -2.0v for 20 ns max, except for oe/v pp which cannot exceed -0.2v. note 10: typical values are for t a = 25 c and nominal supply voltages. address valid valid output hi-z 2v 0.8v 2v 0.8v 2v 0.8v address output ce oe/v pp t ce 2v 0.8v (note 3) (note 3) t df (note 4, 5) (note 4, 5) t oh hi-z t oe acc t cf t ds008827-3
5 www.fairchildsemi.com nmc27c32b rev. c nmc27c32b 32,768-bit (4096 x 8) cmos eprom programming characteristics (note 11) (note 12) (note 13) (note 14) symbol parameter conditions min typ max units t as address setup time 1 m s t oes oe setup time 1 m s t ds data setup time 1 m s t vcs v cc setup time 1 m s t ah address hold time 0 m s t dh data hold time 1 m s t cf chip enable to output float delay oe = v il 060ns t pw program pulse width 95 100 105 m s t oeh oe hold time 1 m s t dv data valid from ce oe = v il 250 ns t prt oe pulse rise time 50 ns during programming t vr v pp recovery time 1 m s i pp v pp supply current during ce = v il ,30ma programming pulse oe = v pp i cc v cc supply current 10 ma t a temperature ambient 20 25 30 c v cc power supply voltage 6.0 6.25 6.5 v v pp programming supply voltage 12.5 12.75 13.0 v t fr input rise, fall time 5 ns v il input low voltage 0.0 0.45 v v ih input high voltage 2.4 4.0 v t in input timing reference voltage 0.8 2.0 v t out output timing reference voltage 0.8 2.0 v programming waveforms note 11: fairchilds standard product warranty applies only to devices programmed to specifications described herein. note 12: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 13: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v cc to gnd to suppress spurious voltage transients which may damage the device. note 14: programming and program verify are tested with the fast program algorithm, at typical power supply voltages and timings. t as t ah program program verify address n t cf data out valid add n data in stable add n hi-z t ds t dh t vcs t pw t oes t prt t vr t oeh t dv 2v 0.8v 2v 0.8v 2v 0.8v 2v 0.8v 6.0v 12.5v 0.8v 0v address data v cc oe/v pp ce ds008827-4
6 www.fairchildsemi.com nmc27c32b rev. c nmc27c32b 32,768-bit (4096 x 8) cmos eprom fast programming algorithm flow chart (note 14) figure 1. yes no start addr = first location v cc = 6.25 v v pp = 12.75 v x = 0 program one 100 s pulse increment x x = 20? verify byte device failed fail pass pass last address increment addr fail yes no pass device passed verify byte verify all bytes 1st v cc = v pp =5.5v 2nd v cc = v pp =4.5v device failed fail ds008827-5
7 www.fairchildsemi.com nmc27c32b rev. c nmc27c32b 32,768-bit (4096 x 8) cmos eprom functional description device operation the six modes of operation of the nmc27c32b are listed in table 1. a single 5v power supply is required in the read mode. all inputs are ttl levels except for oe/v pp during programming. in the program mode the oe/v pp input is pulsed from a ttl low level to 12.75v. read mode the nmc27c32b has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs t oe after the falling edge of oe, assuming that ce has been low and addresses have been stable for at least t acc Ct oe . the sense amps are clocked for fast access time. v cc should therefore be maintained at operating voltage during read and verify. if v cc temporarily drops below the spec. voltage (but not to ground) an address transition must be performed after the drop to ensure proper output data. standby mode the nmc27c32b has a standby mode which reduces the active power dissipation by 99%, from 55 mw to 0.55 mw. the nmc27c32b is placed in the standby mode by applying a cmos high signal to the ce input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output or-tying because eproms are usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connection. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recommended that ce (pin 18) be decoded and used as the primary device selecting function, while oe (pin 20) be made a common connec- tion to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on pin 20 oe/v pp will damage the nmc27c32b. initially, and after each erasure, all bits of the nmc27c32b are in the 1 state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be pro- grammed, both 1s and 0s can be presented in the data word. the only way to change a 0 to a 1 is by ultraviolet light erasure. the nmc27c32b is in the programming mode when oe/v pp is at 12.75v. it is required that at least a 0.1 m f capacitor be placed across v cc and ground to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 8 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. when the address and data are stable, an active low, ttl program pulse is applied to the ce input. a program pulse must be applied at each address location to be programmed. the nmc27c32b is programmed with the fast programming algorithm shown in figure 1. each address is programmed with a series of 100 m s pulses until it verifies good, up to a maximum of 25 pulses. most memory cells will program with a single 100 m s pulse. the nmc27c32b must not be programmed with a dc signal applied to the ce input. programming multiple nmc27c32bs in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. like inputs of the paralleled nmc27c32b may be connected together when they are pro- grammed with the same data. a low level ttl pulse applied to the ce input programs the paralleled nmc27c32b. table 1. mode selection pins ce oe/v pp v cc outputs mode (18) (20) (24) (9C11, 13C17) read v il v il 5v d out standby v ih dont care 5v hi-z program v il 12.75v 6.25v d in program verify v il v il 6.25v d out program inhibit v ih 12.75v 6.25v hi-z output disable dont care v ih 5v hi-z program inhibit programming multiple nmc27c32b in parallel with different data is also easily accomplished. except for ce all like inputs (including oe) of the parallel nmc27c32b may be common. a ttl low level program pulse applied to an nmc27c32bs ce input with oe /v pp at 12.75v will program that nmc27c32b. a ttl high level ce input inhibits the other nmc27c32b from being programmed.
8 www.fairchildsemi.com nmc27c32b rev. c nmc27c32b 32,768-bit (4096 x 8) cmos eprom functional description (continued) program verify a verify should be performed on the programmed bit to determine whether they were correctly programmed. the verify is accom- plished with oe/v pp and ce at v il . data should be verified t dv after the falling edge of ce . manufacturers identification code the nmc27c32b has a manufacturers identification code to aid in programming. the code, shown in table 2, is two bytes wide and is stored in a rom configuration on the chip. it identifies the manufacturer and the device type. the code for the nmc27c32b is, 8f01, where 8f designates that it is made by fairchild semiconductor, and 01 designates a 32k part. the code is accessed by applying 12.0v 0.5v to address pin a9. addresses a1Ca8, a10Ca11, ce , and oe are held at v il . address a0 is held at v il for the manufacturers code, and at v ih for the device code. the code is read out on the 8 data pins. proper code access is only guaranteed at 25 c 5 c. the primary purpose of the manufacturers identification code is automatic programming control. when the device is inserted in an eprom programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. erasure characteristics the erasure characteristics of the nmc27c32b are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms (?). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000? - 4000? range. after programming, opaque labels should be placed over the nmc27c32bs window to prevent unintentional erasure. covering the window will also prevent temporary functional failure due to the generation of photo currents. the recommended erasure procedure for the nmc27c32b is exposure to short wave ultraviolet light which has a wavelength of 2537?. the integrated dose (i.e., uv intensity x exposure time) for erasure should be a minimum of 15 w-sec/cm 2 . the nmc27c32b should be placed within 1 inch of the lamp tubes during erasure. some lamps have a filter on their tubes which should be removed before erasure. an erasure system should be calibrated periodically. the distance from lamp to unit should be maintained at one inch. the erasure time increases as the square of the distance. (if distance is doubled the erasure time increases by a factor of 4.) lamps lose intensity as they age. when a lamp is changed, the distance has changed or the lamp has aged, the system should be checked to make certain full erasure is occurring. incomplete erasure will cause symptoms that can be misleading. programmers, compo- nents, and even system designs have been erroneously sus- pected when incomplete erasure was the problem. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc , has three segments that are of interest to the system designer the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. the associated v cc transient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces. table 2. manufacturers identification code pins a0 o7 o6 o5 o4 o3 o2 o1 o0 hex (8) (17) (16) (15) (14) (13) (11) (10) (9) data manufacturer code v il 100011118f device code v ih 0000000101
9 www.fairchildsemi.com nmc27c32b rev. c nmc27c32b 32,768-bit (4096 x 8) cmos eprom physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 uv window cavity dual-in-line cerdip package (jq) order number nmc27c32bq package number j24aq 1.260 max 24 1 13 12 r 0.025 r 0.030-0.055 typ 0.270 ?0.290 uv window 0.590-0.620 0.180 max 0.060-0.100 typ 0.050-0.060 typ 0.015-0.021 typ glass sealant 0.020 -0.070 typ 0.10 max 0.090-0.110 typ 0.225 max typ 0.125 min typ 90 - 100 typ 0.685 +0.025 -0.060 0.008-0.015 typ 0.514 ?0.526
1 www.fairchildsemi.com nmc27c64 rev. c nmc27c64 65,536-bit (8192 x 8) cmos eprom nmc27c64 65,536-bit (8192 x 8) cmos eprom general description the nmc27c64 is a 64k uv erasable, electrically reprogrammable and one-time programmable (otp) cmos eprom ideally suited for applications where fast turnaround, pattern experimentation and low power consumption are important requirements. the nmc27c64 is designed to operate with a single +5v power supply with 10% tolerance. the cmos design allows the part to operate over extended and military temperature ranges. the nmc27c64q is packaged in a 28-pin dual-in-line package with a quartz window. the quartz window allows the user to expose the chip to ultraviolet light to erase the bit pattern. a new pattern can then be written electrically into the device by following the programming procedure. the nmc27c64n is packaged in a 28-pin dual-in-line plastic molded package without a transparent lid. this part is ideally block diagram january 1999 suited for high volume production applications where cost is an important factor and programming only needs to be done once. this family of eproms are fabricated with fairchilds proprietary, time proven cmos double-poly silicon gate technology which combines high performance and high density with low power consumption and excellent reliability. features n high performance cmos 150 ns access time n jedec standard pin configuration 28-pin plastic dip package 28-pin cerdip package n drop-in replacement for 27c64 or 2764 n manufacturers identification code ds008634-1 output enable, chip enable, and program logic y decoder x decoder . . . . . . . . . output buffers 65,536-bit cell matrix data outputs o 0 - o 7 v cc gnd v pp oe pgm ce a 0 - a 12 address inputs ? 1998 fairchild semiconductor corporation
2 www.fairchildsemi.com nmc27c64 rev. c nmc27c64 65,536-bit (8192 x 8) cmos eprom connection diagram note: socket compatible eprom pin configurations are shown in the blocks adjacent to the nmc27c64 pins. v cc pgm nc a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c512 27512 27c256 27256 v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd nmc27c64 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c32 2732 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c16 2716 v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 27c128 27128 27c256 27256 27c512 27512 v cc a 14 a 13 a 8 a 9 a 11 oe a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 v cc a 14 a 13 a 8 a 9 a 11 oe/v pp a 10 ce o 7 o 6 o 5 o 4 o 3 v cc pgm a 13 a 8 a 9 a 11 oe a 10 ce o 7 o 6 o 5 o 4 o 3 v cc a 8 a 9 v pp oe a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 v cc a 8 a 9 a 11 oe/v pp a 10 ce o 7 o 6 o 5 o 4 o 3 27c16 2716 27c32 2732 27c128 27128 ds008634-2 pin names a0Ca12 addresses ce chip enable oe output enable o 0 Co 7 outputs pgm program nc no connect v pp programming voltage v cc power supply gnd ground commercial temperature range v cc = 5v 10% parameter/order number access time (ns) nmc27c64q, n 150 150 nmc27c64q, n 200 200 extended temp range (-40 c to +85 c) v cc = 5v 10% parameter/order number access time (ns) nmc27c64qe, ne200 200
3 www.fairchildsemi.com nmc27c64 rev. c nmc27c64 65,536-bit (8192 x 8) cmos eprom read operation dc electrical characteristics symbol parameter conditions min typ max units i li input load current v in = v cc or gnd 10 m a i lo output leakage current v out = v cc or gnd, ce = v ih 10 m a i cc1 v cc current (active) ce = v il ,f=5 mhz 5 20 ma (note 9) ttl inputs inputs = v ih or v il , i/o = 0 ma i cc2 v cc current (active) ce = gnd, f = 5 mhz 3 10 ma (note 9) cmos inputs inputs = v cc or gnd, i/o = 0 ma i ccsb1 v cc current (standby) ce = v ih 0.1 1 ma ttl inputs i ccsb2 v cc current (standby) ce = v cc 0.5 100 m a cmos inputs i pp vpp load current v pp = v cc 10 m a v il input low voltage -0.1 0.8 v v ih input high voltage 2.0 v cc +1 v v ol1 output low voltage i ol = 2.1 ma 0.45 v v oh1 output high voltage i oh = -400 m a 2.4 v v ol2 output low voltage i ol = 0 m a 0.1 v v oh2 output high voltage i oh = 0 m av cc - 0.1 v ac electrical characteristics nmc27c64 symbol parameter conditions 150 200, e200 units min max min max t acc address to ce = oe = v il 150 200 ns output delay pgm = v ih t ce ce to output delay oe = v il , pgm = v ih 150 200 ns t oe oe to output delay ce = v il , pgm = v ih 60 60 ns t df oe high to output float ce = v il , pgm = v ih 0 60 0 60 ns t cf ce high to output float oe = v il , pgm = v ih 0 60 0 60 ns t oh output hold from ce = oe = v il addresses, ce or oe , pgm = v ih 00ns whichever occurred first absolute maximum ratings (note 1) temperature under bias -55 c to +125 c storage temperature -65 c to +150 c all input voltages except a9 with respect to ground (note 10) +6.5v to -0.6v all output voltages with respect to ground (note 10)v cc +1.0v to gnd -0.6v v pp supply voltage and a 9 with respect to ground during programming +14.0v to -0.6v v cc supply voltage with respect to ground +7.0v to -0.6v power dissipation 1.0w lead temperature (soldering, 10 sec.) 300 c esd rating (mil spec 883c, method 3015.2) 2000v operating conditions (note 7) temperature range nmc27c64q 150, 200 0 c to +70 c nmc27c64n 150, 200 nmc27c64qe 200 -40 c to +85 c nmc27c64ne 200 v cc power supply +5v 10%
4 www.fairchildsemi.com nmc27c64 rev. c nmc27c64 65,536-bit (8192 x 8) cmos eprom capacitance ta = +25?c, f = 1 mhz (note 2) nmc27c64q symbol parameter conditions typ max units c in input capacitance v in = 0v 6 8 pf c out output capacitance v out = 0v 9 12 pf capacitance ta = +25?c, f = 1 mhz (note 2) nmc27c64n symbol parameter conditions typ max units c in input capacitance v in = 0v 5 10 pf c out output capacitance v out = 0v 8 10 pf ac test conditions output load 1 ttl gate and c l = 100 pf (note 8) input rise and fall times 5 ns input pulse levels 0.45v to 2.4v timing measurement reference level inputs 0.8v and 2v outputs 0.8v and 2v ac waveforms (note 6) (note 9) note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: this parameter is only sampled and is not 100% tested. note 3: oe may be delayed up to t acc - t oe after the falling edge of ce without impacting t acc . note 4: the t df and t cf compare level is determined as follows: high to tri-state ? , the measured v oh1 (dc) ? 0.10v; low to tri-state, the measured v ol1 (dc) + 0.10v. note 5: tri-state may be attained using oe or ce . note 6: the power switching characteristics of eproms require careful device decoupling. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. note 7: the outputs must be restricted to v cc + 1.0v to avoid latch-up and device damage. note 8: 1 ttl gate: i ol = 1.6 ma, i oh = -400 m a. c l : 100 pf includes fixture capacitance. note 9: v pp may be connected to v cc except during programming. note 10: inputs and outputs can undershoot to -2.0v for 20 ns max. address valid valid output hi-z 2v 0.8v 2v 0.8v 2v 0.8v address output ce oe t ce 2v 0.8v (note 3) (note 3) t df t cf (notes 4, 5) (notes 4, 5) t oh hi-z t oe acc t
5 www.fairchildsemi.com nmc27c64 rev. c nmc27c64 65,536-bit (8192 x 8) cmos eprom programming characteristics (note 11) (note 12) (note 13) (note 14) symbol parameter conditions min typ max units t as address setup time 2 m s t oes oe setup time 2 m s t ces ce setup time 2 m s t ds data setup time 2 m s t vps v pp setup time 2 m s t vcs v cc setup time 2 m s t ah address hold time 0 m s t dh data hold time 2 m s t df output enable to ce = v il 0 130 ns output float delay t pw program pulse width 0.45 0.5 0.55 ms t oe data valid from oe ce = v il 150 ns i pp v pp supply current during ce = v il 30 ma programming pulse pgm = v il i cc v cc supply current 10 ma t a temperature ambient 20 25 30 ?c v cc power supply voltage 5.75 6.0 6.25 v v pp programming supply voltage 12.2 13.0 13.3 v t fr input rise, fall time 5 ns v il input low voltage 0.0 0.45 v v ih input high voltage 2.4 4.0 v t in input timing reference voltage 0.8 1.5 2.0 v t out output timing reference voltage 0.8 1.5 2.0 v
6 www.fairchildsemi.com nmc27c64 rev. c nmc27c64 65,536-bit (8192 x 8) cmos eprom programming waveforms (note 13) note 11: fairchilds standard product warranty applies to devices programmed to specifications described herein. note 12: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . the eprom must not be inserted into or removed from a board with voltage applied to v pp or v cc . note 13: the maximum absolute allowable voltage which may be applied to the v pp pin during programming is 14v. care must be taken when switching the v pp supply to prevent any overshoot from exceeding this 14v maximum specification. at least a 0.1 m f capacitor is required across v pp , v cc to gnd to suppress spurious voltage transients which may damage the device. note 14: programming and program verify are tested with the interactive program algorithm, at typical power supply voltages and timings. t as t ah program program verify address n t df data out valid add n data in stable add n hi-z t ds t dh t vcs t vps t ces t pw t oes t oe 2v 0.8v 2v 0.8v 2v 0.8v 2v 0.8v 6.0v 13.0v 0.8v address data v cc ce oe v pp pgm
7 www.fairchildsemi.com nmc27c64 rev. c nmc27c64 65,536-bit (8192 x 8) cmos eprom fast programming algorithm flow chart yes no start addr = first location v cc = 6.25 v v pp = 12.75v x = 0 program one 100 s pulse increment x x = 20 ? verify byte device failed fail pass pass last address increment addr fail yes no pass device passed verify byte 1st v cc = v pp =5.5v 2nd v cc = v pp =4.5v device failed fail figure 1.
8 www.fairchildsemi.com nmc27c64 rev. c nmc27c64 65,536-bit (8192 x 8) cmos eprom functional description device operation the six modes of operation of the nmc27c64 are listed in table 1. it should be noted that all inputs for the six modes are at ttl levels. the power supplies required are v cc and v pp . the v pp power supply must be at 12.75v during the three programming modes, and must be at 5v in the other three modes. the v cc power supply must be at 6v during the three programming modes, and at 5v in the other three modes. read mode the nmc27c64 has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. the programming pin (pgm) should be at v ih except during program- ming. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs t oe after the falling edge of oe , assuming that ce has been low and addresses have been stable for at least t acc C t oe . the sense amps are clocked for fast access time. v cc should therefore be maintained at operating voltage during read and verify. if v cc temporarily drops below the spec. voltage (but not to ground) an address transition must be performed after the drop to insure proper output data. standby mode the nmc27c64 has a standby mode which reduces the active power dissipation by 99%, from 55 mw to 0.55 mw. the nmc27c64 is placed in the standby mode by applying a cmos high signal to the ce input. when in standby mode, the outputs are in a high impedance state, independent of the oe input. output or-tying because nmc27c64s are usually used in larger memory arrays, fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. the 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. to most efficiently use these two control lines, it is recomended that ce (pin 20) be decoded and used as the primary device selecting function, while oe (pin 22) be made a common connec- tion to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. programming caution: exceeding 14v on pin 1 (v pp ) will damage the nmc27c64. initially, all bits of the nmc27c64 are in the 1 state. data is introduced by selectively programming 0s into the desired bit locations. although only 0s will be programmed, both 1s and 0s can be presented in the data word. a 0 cannot be changed to a 1 once the bit has been programmed. the nmc27c64 is in the programming mode when the v pp power supply is at 12.75v and oe is at v ih . it is required that at least a 0.1 m f capacitor be placed across v pp , v cc to ground to suppress spurious voltage transients which may damage the device. the data to be programmed is applied 8 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. for programming, ce should be kept ttl low at all times while v pp is kept at 12.75v. when the address and data are stable, an active low, ttl program pulse is applied to the pgm input. a program pulse must be applied at each address location to be programmed. the nmc27c64 is programmed with the fast programming algorithm shown in figure 1. each address is programmed with a series of 100 m s pulses until it verfies good, up to a maximum of 25 pulses. most memory cells will program with a single 100 m s pulse. the nmc27c64 must not be programmed with a dc signal applied to the pgm input. programming multiple nmc27c64s in parallel with the same data can be easily accomplished due to the simplicity of the program- ming requirements. like inputs of the paralleled nmc27c64s may be connected together when they are programmed with the same data. a low level ttl pulse applied to the pgm input programs the paralleled nmc27c64s. if an application requires erasing and reprogramming, the nmc27c64q uv erasable prom in a win- dowed package should be used. table 1. mode selection pins ce oe pgm v pp v cc outputs mode (20) (22) (27) (1) (28) (11C13, 15C19) read v il v il v ih 5v 5v d out standby v ih dont care dont care 5v 5v hi-z output disable dont care v ih v ih 5v 5v hi-z program v il v ih 13v 6v d in program verify v il v il v ih 13v 6v d out program inhibit v ih dont care dont care 13v 6v hi-z
9 www.fairchildsemi.com nmc27c64 rev. c nmc27c64 65,536-bit (8192 x 8) cmos eprom functional description (continued) program inhibit programming multiple nmc27c64s in parallel with different data is also easily accomplished. except for ce all like inputs (including oe and pgm) of the parallel nmc27c64 may be common. a ttl low level program pulse applied to an nmc27c64s pgm input with ce at v il and v pp at 13.0v will program that nmc27c64. a ttl high level ce input inhibits the other nmc27c64s from being programmed. program verify a verify should be performed on the programmed bits to determine whether they were correctly programmed. the verify may be performed with v pp at 13.0v. v pp must be at v cc , except during programming and program verify. manufacturers identification code the nmc27c64 has a manufacturers identification code to aid in programming. the code, shown in table 2, is two bytes wide and is stored in a rom configuration on the chip. it identifies the manufacturer and the device type. the code for the nmc27c64 is 8fc2, where 8f designates that it is made by fairchild semiconductor, and c2 designates a 64k part. the code is accessed by applying 12v 0.5v to address pin a9. addresses a1Ca8, a10Ca12, ce, and oe are held at v il . address a0 is held at v il for the manufacturers code, and at v ih for the device code. the code is read out on the 8 data pins. proper code access is only guaranteed at 25 c 5 c. the primary purpose of the manufacturers identification code is automatic programming control. when the device is inserted in a eprom programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. this automatic programming control is only possible with programmers which have the capability of reading the code. erasure characteristics the erasure characteristics of the nmc27c64 are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms (?). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000? C 4000? range. after programming, opaque labels should be placed over the nmc27c64s window to prevent unintentional erasure. covering the window will also prevent temporary functional failure due to the generation of photo currents. the recommended erasure procedure for the nmc27c64 is exposure to short wave ultraviolet light which has a wavelength of 2537 angstroms (?). the integrated dose (i.e., uv intensity x exposure time) for erasure should be a minimum of 15w-sec/cm 2 . the nmc27c64 should be placed within 1 inch of the lamp tubes during erasure. some lamps have a filter on their tubes which should be removed before erasure. an erasure system should be calibrated periodically. the distance from lamp to unit should be maintained at one inch. the erasure time increases as the square of the distance. (if distance is doubled the erasure time increases by a factor of 4.) lamps lose intensity as they age. when a lamp is changed, the distance has changed or the lamp has aged, the system should be checked to make certain full erasure is occurring. incomplete erasure will cause symptoms that can be misleading. programmers, compo- nents, and even system designs have been erroneously sus- pected when incomplete erasure was the problem. system consideration the power switching characteristics of eproms require careful decoupling of the devices. the supply current, i cc , has three segments that are of interest to the system designerthe standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. the associated v cc transient voltage peaks can be suppressed by properly selected decoupling capacitors. it is recommended that at least a 0.1 m f ceramic capacitor be used on every device between v cc and gnd. this should be a high frequency capacitor of low inherent inductance. in addition, at least a 4.7 m f bulk electrolytic capacitor should be used between v cc and gnd for each eight devices. the bulk capacitor should be located near where the power supply is connected to the array. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the pc board traces. table 2. manufacturers identification code pins a0 o7 o6 o5 o4 o3 o2 o1 o0 hex (10) (19) (18) (17) (16) (15) (13) (12) (11) data manufacturer code v il 100011118f device code v ih 11000010c2
10 www.fairchildsemi.com nmc27c64 rev. c nmc27c64 65,536-bit (8192 x 8) cmos eprom physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, t simshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 0.625 +0.025 -0.015 0.008-0.015 (0.229-0.381) 15.88 +0.635 -0.381 0.580 (14.73) 95 5 0.600 - 0.620 (15.24 - 15.75) 0.030 (0.762) max ( ( 0.108 0.010 (2.540 0.254) 0.018 0.003 (0.457 0.076) 0.20 (0.508) 0.125-0.145 (3.175-3.583) 0.125-0.165 (3.175-4.191) 0.050 (1.270) typ 0.053 - 0.069 (1.346 - 1.753) 0.050 0.015 (1.270 0.381) min 88 94 typ 12 34 28 27 26 25 1.393 - 1.420 (35.38 - 36.07) 0.510 0.005 (12.95 0.127) 0.062 (1.575) pin #1 ident 5 24 6 23 22 21 20 19 18 17 16 7 8 9 1011121314 15 rad dual-in-line package (n) order number nmc27c64n package number n28b 1.260 max (32.00) 24 1 13 12 0.025 (0.64) 0.030-0.055 (0.76 - 1.4) 0.270 - 0.290 (6.88 - 7.39) uv window 0.590-0.620 (15.03 - 15.79) 0.180 (4.59) max 0.060-0.100 (1.53 - 2.55) typ 0.050-0.060 (1.27 - 1.53) 0.015-0.021 (0.38 - 0.53) typ glass sealant 0.020 -0.070 (0.51 - 1.78) typ 0.10 (2.5) max 0.090-0.110 (2.29 - 2.80) typ 0.225 (5.73) 0.125 min (3.18) typ 90 - 100 typ 0.685 (17.40) +0.025 (0.64) -0.060 (-1.523) 0.008-0.015 (0.20 - 0.38) typ 0.514 - 0.526 (13.06 - 13.21) r r typ typ max typ dual-in-line package (q) order number nmc27c64q package number j28aq
pn2222a / mmbt2222a / mmpq2222 / nmt2222 / pzt2222a npn general purpose amplifier this device is for use as a medium power amplifier and switch requiring collector currents up to 500 ma. sourced from pro- cess 19. pn2222a c b e to-92 pzt2222a b c c sot-223 e mmbt2222a c b e sot-23 mark: 1p nmt2222 mmpq2222 c c c c c c c c soic-16 e b e b e b e b absolute maximum ratings* ta = 25c unless otherwise noted * these ratings are limiting values above which the serviceability of any semiconductor device may be impaired. notes : 1) these ratings are based on a maximum junction temperature of 150 degrees c. 2) these are steady state limits. the factory should be consulted on applications involving pulsed or low duty cycle operations. symbol parameter value units v ceo collector-emitter voltage 40 v v cbo collector-bas e voltage 75 v v ebo emitter-base voltage 6.0 v i c collector current - continuous 1.0 a t j , t stg operating and storage j unction temperature range -55 to +150 c sot-6 mark: .1b c1 e1 c2 b1 e2 b2 discrete power & signal technologies ? 1997 fairchild semiconductor corporation
pn2222a / mmbt2222a / mmpq2222 / nmt2222 / pzt2222a electrical characteristics ta = 25c unless otherwise noted symbol parameter test conditions min max units off characteristics on characteristics small signal characteristics (except mmpq2222 and nmt2222) f t current gain - bandwidth product i c = 20 ma, v ce = 20 v, f = 100 mhz 300 mhz c obo output capacitance v cb = 10 v, i e = 0, f = 100 khz 8.0 pf c ibo input capac itance v eb = 0.5 v, i c = 0, f = 100 khz 25 pf rbc c collector base time constant i c = 20 ma, v cb = 20 v, f = 31.8 mhz 150 ps nf noise figure i c = 100 m a, v ce = 10 v, r s = 1.0 k w , f = 1.0 khz 4.0 db re(h ie ) real part of common-emitter high frequency input impedance i c = 20 ma, v ce = 20 v, f = 300 mhz 60 w switching characteristics (except mmpq2222 and nmt2222) * pulse test: pulse width 300 m s, duty cycle 2.0% spice model v (br)ceo collector-emitter breakdown voltage* i c = 10 ma, i b = 0 40 v v (br)cbo collector-bas e breakdown voltage i c = 10 m a, i e = 0 75 v v (br) ebo emitter-base breakdown voltage i e = 10 m a, i c = 0 6.0 v i cex collector cutoff current v ce = 60 v, v eb(off) = 3.0 v 10 na i cbo collector cutoff current v cb = 60 v, i e = 0 v cb = 60 v, i e = 0, t a = 150 c 0.01 10 m a m a i ebo emitter cutoff current v eb = 3.0 v, i c = 0 10 na i bl base cutoff current v ce = 60 v, v eb(off) = 3.0 v 20 na h fe dc current gain i c = 0.1 ma, v ce = 10 v i c = 1.0 ma, v ce = 10 v i c = 10 ma, v ce = 10 v i c = 10 ma, v ce = 10 v, t a = -55 c i c = 150 ma, v ce = 10 v* i c = 150 ma, v ce = 1.0 v* i c = 500 ma, v ce = 10 v* 35 50 75 35 100 50 40 300 v ce( sat ) collector-emitter saturation voltage* i c = 150 ma, i b = 15 ma i c = 500 ma, i b = 50 ma 0.3 1.0 v v v be( sat ) base-emitter saturation voltage* i c = 150 ma, i b = 1.0 ma i c = 500 ma, i b = 5.0 ma 0.6 1.2 2.0 v v t d delay time v cc = 30 v, v be(off) = 0.5 v, 10 ns t r rise time i c = 150 ma, i b1 = 15 ma 25 ns t s storage time v cc = 30 v, i c = 150 ma, 225 ns t f fall time i b1 = i b2 = 15 ma 60 ns npn (is=14.34f xti=3 eg=1.11 vaf=74.03 bf=255.9 ne=1.307 ise=14.34f ikf=.2847 xtb=1.5 br=6.092 nc=2 isc=0 ikr=0 rc=1 cjc=7.306p mjc=.3416 vjc=.75 fc=.5 cje=22.01p mje=.377 vje=.75 tr=46.91n tf=411.1p itf=.6 vtf=1.7 xtf=3 rb=10) npn general purpose amplifier (continued)
pn2222a / mmbt2222a / mmpq2222 / nmt2222 / pzt2222a thermal characteristics ta = 25c unless otherwise noted symbol characteristic max units pn2222a *pzt2222a p d total device dissipation derate above 25 c 625 5.0 1,000 8.0 mw mw/ c r q jc thermal resistanc e, j unction to case 83.3 c/w r q ja thermal resistanc e, j unction to ambient 200 125 c/w symbol characteristic max units **mmbt2222a mmpq2222 p d total device dissipation derate above 25 c 350 2.8 1,000 8.0 mw mw/ c r q ja thermal resistanc e, j unction to ambient effective 4 die each die 357 125 240 c/w c/w c/w typical characteristics npn general purpose amplifier (continued) * device mounted on fr-4 pcb 36 mm x 18 mm x 1.5 mm; mounting pad for the collector lead min. 6 cm 2 . ** device mounted on fr-4 pcb 1.6" x 1.6" x 0.06." base-emitter on voltage vs collector current p19 0.1 1 10 25 0.2 0.4 0.6 0.8 1 i - collector current (ma) v - base-emitter on voltage (v) be(on) c v = 5v ce 25 c 125 c - 40 c base-emitter saturation voltage vs collector current 110100500 0.4 0.6 0.8 1 i - collector current (ma) v - base-emitter voltage (v) besat c b b = 10 25 c 125 c - 4 0 c collector-emitter saturation voltage vs collector current p19 110100500 0.1 0.2 0.3 0.4 i - collector current (ma) v - collector-emitter voltage (v) cesat 25 c c b b = 10 125 c - 40 c typical pulsed current gain vs collector current p19 0.1 0.3 1 3 10 30 100 300 0 100 200 300 400 500 i - collector current (ma) h - typical pulsed current gain c fe 125 c 25 c - 40 c v = 5v ce
pn2222a / mmbt2222a / mmpq2222 / nmt2222 / pzt2222a npn general purpose amplifier (continued) typical characteristics (continued) collector-cutoff current vs ambient temperature 25 50 75 100 125 150 0.1 1 10 100 500 t - ambient temperature ( c) i - collector current (na) a v = 40v cb cbo emitter transition and output capacitance vs reverse bias voltage p19 0.1 1 10 100 4 8 12 16 20 reverse bias voltage (v) capacitance (pf) f = 1 mhz c ob c te turn on and turn off times vs collector current 10 100 1000 0 80 160 240 320 400 i - collector current (ma) time (ns) i = i = t on t off b1 c b2 i c 10 v = 25 v cc switching times vs collector current p19 10 100 1000 0 80 160 240 320 400 i - collector current (ma) time (ns) i = i = t r t s b1 c b2 i c 10 v = 25 v cc t f t d power dissipation vs ambient temperature 0 25 50 75 100 125 150 0 0.25 0.5 0.75 1 temperature ( c) p - power dissipation (w) d o sot-2 23 to-92 sot-2 3
pn2222a / mmbt2222a / mmpq2222 / nmt2222 / pzt2222a test circuits 30 v 1.0 k w w w w w 16 v 0 200ns 200ns 500 w w w w w 200 w w w w w 50 w w w w w 37 w w w w w - 15 v 1.0 k w w w w w 6.0 v 0 30 v figure 2: saturated turn-off switching time figure 1: saturated turn-on switching time 1k npn general purpose amplifier (continued)
pn2907a / mmbt2907a / mmpq2907 / nmt2907 / pzt2907a symbol parameter value units v ceo collector-emitter voltage 60 v v cbo collector-base voltage 60 v v ebo emitter-base voltage 5.0 v i c collector current - continuous 800 ma t j , t stg operating and storage junction temperature range -55 to +150 c pnp general purpose amplifier this device is designed for use as a general purpose amplifier and switch requiring collector currents to 500 ma. sourced from process 63. absolute maximum ratings* ta = 25c unless otherwise noted * these ratings are limiting values above which the serviceability of any semiconductor device may be impaired. notes : 1) these ratings are based on a maximum junction temperature of 150 degrees c. 2) these are steady state limits. the factory should be consulted on applications involving pulsed or low duty cycle operations. pzt2907a b c c sot-223 e pn2907a c b e to-92 mmbt2907a c b e sot-23 mark: 2f mmpq2907 c c c c c c c c soic-16 e b e b e b e b nmt2907 sot-6 mark: .2b c1 e1 c2 b1 e2 b2 discrete power & signal technologies ? 1997 fairchild semiconductor corporation
pn2907a / mmbt2907a / mmpq2907 / nmt2907 / pzt2907a electrical characteristics ta = 25c unless otherwise noted off characteristics on characteristics small signal characteristics (except mmpq2907 and nmt2907) f t current gain - bandwidth product i c = 50 ma, v ce = 20 v, f = 100 mhz 200 mhz c obo output capacitance v cb = 10 v, i e = 0, f = 100 khz 8.0 pf c ibo input capacitance v eb = 2.0 v, i c = 0, f = 100 khz 30 pf switching characteristics (except mmpq2907 and nmt2907) t on turn-on time v cc = 30 v, i c = 150 ma, 45 ns t d delay time i b1 = 15 ma 10 ns t r rise time 40 ns t off turn-off time v cc = 6.0 v, i c = 150 ma 100 ns t s storage time i b1 = i b2 = 15 ma 80 ns t f fall time 30 ns * pulse test: pulse width 300 m s, duty cycle 2.0% spice model symbol parameter test c onditions min max units v ( br ) ceo collector-emitter breakdown voltage* i c = 10 ma, i b = 060v v ( br ) cbo collector-base breakdown voltage i c = 10 m a, i e = 0 60 v v ( br ) ebo emitter-base breakdown voltage i e = 10 m a, i c = 0 5.0 v i b base cutoff current v cb = 30 v, v eb = 0.5 v 50 na i cex collector cutoff current v ce = 30 v, v be = 0.5 v 50 na i cbo collector cutoff current v cb = 50 v, i e = 0 v cb = 50 v, i e = 0, t a = 150 c 0.02 20 m a m a h fe dc current gain i c = 0.1 ma, v ce = 10 v i c = 1.0 ma, v ce = 10 v i c = 10 ma, v ce = 10 v i c = 150 ma, v ce = 10 v* i c = 500 ma, v ce = 10 v* 75 100 100 100 50 300 v ce( sat ) collector-emitter saturation voltage* i c = 150 ma, i b = 15 ma i c = 500 ma, i b = 50 ma 0.4 1.6 v v v be( sat ) base-emitter saturation voltage i c = 150 ma, i b = 15 ma* i c = 500 ma, i b = 50 ma 1.3 2.6 v v pnp (is=650.6e-18 xti=3 eg=1.11 vaf=115.7 bf=231.7 ne=1.829 ise=54.81f ikf=1.079 xtb=1.5 br=3.563 nc=2 isc=0 ikr=0 rc=.715 cjc=14.76p mjc=.5383 vjc=.75 fc=.5 cje=19.82p mje=.3357 vje=.75 tr=111.3n tf=603.7p itf=.65 vtf=5 xtf=1.7 rb=10) pnp general purpose amplifier (continued)
pn2907a / mmbt2907a / mmpq2907 / nmt2907 / pzt2907a thermal characteristics ta = 25c unless otherwise noted symbol characteristic max units pn2907a *pzt2907a p d total device dissipation derate above 25 c 625 5.0 1,000 8.0 mw mw / c r q jc thermal resistance, junction to case 83.3 c/w r q ja thermal resistance, junction to ambient 200 125 c/w symbol characteristic max units **mmbt2907a mmpq2907 p d total device dissipation derate above 25 c 350 2.8 1,000 8.0 mw mw / c r q ja thermal resistance, junction to ambient effective 4 die each die 357 125 240 c/w c/w c/w pnp general purpose amplifier (continued) typical characteristics * device mounted on fr-4 pcb 36 mm x 18 mm x 1.5 mm; mounting pad for the collector lead min. 6 cm 2 . ** device mounted on fr-4 pcb 1.6" x 1.6" x 0.06." typical pulsed current gain vs collector current 0.1 0.3 1 3 10 30 100 300 0 100 200 300 400 500 i - collector current (ma) h - typical pulsed current gain c fe 125 c 25 c - 40 c v = 5v ce collector-emitter saturation voltage vs collector current 1 10 100 500 0 0.1 0.2 0.3 0.4 0.5 i - collector current (ma) v - collector emitter voltage (v) c cesat b = 10 25 c - 40 oc 125 oc
pn2907a / mmbt2907a / mmpq2907 / nmt2907 / pzt2907a pnp general purpose amplifier (continued) typical characteristics (continued) base-emitter saturation voltage vs collector current 1 10 100 500 0 0.2 0.4 0.6 0.8 1 i - collector current (ma) v - base emitter voltage (v) c besat 25 c - 40 oc 125 oc b = 10 base emitter on voltage vs collector current 0.1 1 10 25 0 0.2 0.4 0.6 0.8 1 i - collector current (ma) v - base emitter on voltage (v) c beon v = 5v ce 25 c - 40 oc 125 oc collector-cutoff current vs. ambient temperature 25 50 75 100 125 0.01 0.1 1 10 100 t - ambient temperature ( c) i - collector current (na) a cbo o v = 35v cb input and output capacitance vs reverse bias voltage 0.1 1 10 50 0 4 8 12 16 20 reverse bias voltage (v) capacitance (pf) c ob c ib switching times vs collector current 10 100 1000 0 50 100 150 200 250 i - collector current (ma) time (ns) i = i = t r t s b1 c b2 i c 10 v = 15 v cc t f t d turn on and turn off times vs collector current 10 100 1000 0 100 200 300 400 500 i - collector current (ma) time (ns) i = i = t on t off b1 c b2 i c 10 v = 15 v cc
pn2907a / mmbt2907a / mmpq2907 / nmt2907 / pzt2907a pnp general purpose amplifier (continued) typical characteristics (continued) rise time vs collector and turn on base currents 10 100 500 1 2 5 10 20 50 i - collector current (ma) i - turn 0n base current (ma) 30 ns c t = 15 v r b1 60 ns power dissipation vs ambient temperature 0 25 50 75 100 125 150 0 0.25 0.5 0.75 1 temperature ( c) p - power dissipation (w) d o sot-223 to-92 sot-23 test circuits figure 1: saturated turn-on switching time test circuit figure 2: saturated turn-off switching time test circuit 1.0 k w w w w w - 6.0 v 15 v 1.0 k w w w w w - 30 v 0 200ns 200ns - 16 v 0 50 w w w w w 200 w w w w w 1 k w w w w w 37 w w w w w 50 w w w w w 30 v
trademarks acex? coolfet? crossvo l t? e 2 cmos tm f act? f act quiet series? f ast ? f as t r? g t o? hisec? the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy f airchilds products are not authorized for use as critical components in life suppo r t devices or systems without the express written appro v al of f airchild semiconduc t or corpor a tion. as used herein: isoplanar? microwire? pop? power t rench? qs? quiet series? supersot?-3 supersot?-6 supersot?-8 t inylogic? 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the bod y , or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the use r . 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to a f fect its safety or e f fectiveness. product s t a tus definitions definition of t erms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconducto r . the datasheet is printed for reference information onl y . formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein to improve reliabilit y , function or design. fairchild does not assume any liability arising out of the applic a tion or use of any product or circuit described herein; neither does it convey any license under its pa tent rights, nor the rights of others.

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