? 2004 fairchild semiconductor corporation an010919 www.fairchildsemi.com fairchild semiconductor application note may 1991 revised february 2004 AN-780 operating ecl from a single positive supply AN-780 operating ecl from a single positive supply introduction ecl is normally specified for operation with a negative v ee power source and a negative v tt termination supply. this is the optimum operating configuration for ecl but not the only one. operating ecl from a positive v cc supply is a practical alternative that is gaining in popularity. positive referenced ecl, or pecl as it is referred to, has been implemented in various mixed signal asic for use in the video graphics and communications fields and is used in clock distribution as well. new single supply translator chips are becoming available to facilitate the interface of pecl logic levels to ttl and back again. logic designers who strive for maximum speed in a system, now can easily replace sections of ttl logic with ecl and operate in pecl fashion from the common ttl v cc supply. standard negative supply ecl operation and why figure 1 shows f100k logic elements operating in stan- dard negative supply ecl configuration. the most positive potential is the primary voltage reference for ecl opera- tion. standard ecl input and output levels are therefore negative potentials referenced to the stable passive ground (0v). the inherent f100k voltage compensation permits stable input and output levels over a broad range of v ee ?s; i.e., ? 4.2 to ? 5.7 vdc for 300 series f100k. thus ecl logic operating from a ? 4.2v v ee is compatible to logic operating from a ? 5.7v supply assuming both are refer- enced to a common 0v ground. since ecl logic outputs only source currents that originate from the potential applied to its v cc /v cca pins, the use of a 0v low impedance and low inductance ground potential is the optimum choice for operation. the use of a continuous copper ground plane as the primary ecl reference is the ideal source for the high frequency transient currents demanded by the logic during switching. note that despite the ideal nature of a ground plane as the primary ecl ref- erence, when mixing ttl (or other noisy circuitry) into ecl systems, the recommendation is to reference the ttl to a separate ground plane. this is to keep the high transient ttl switching energy out of the primary ecl reference and preserve ecl noise margins. when f100k ecl output signal interconnection lengths are direct and short enough, transmission line effects may be ignored and then only a re output biasing resistor is required for logic operation. please refer to section seven of the ? f100k ecl logic databook and design guide ? for a more detailed explanation of transmission line effects and ecl termination techniques. the re resistor provides bias to keep the ecl emitter follower output transistor on for both high and low logic states. the re resistor is nor- mally connected between the ecl output and the most negative potential (v ee ) thus permitting ? single ? supply operation. the v ee potential will ideally be distributed to the ecl logic from a power plane or bus which has low dc series resis- tance and low ac impedance. the low ac impedance is essential to supply the transient energy needed during switching. although the inherent nature of ecl by design is to maintain essentially constant i ee current even during switching, the charging and discharging of internal and external capacitances and the switching currents in the re resistors place transient demands on v ee . the degree to which the user can maintain complementary balance of ecl output loading will greatly influence the nature of the transient i ee demands. f100k 300 series voltage levels specified for standard negative v ee supply operation conditions: v cc /v cca = 0.0 vdc ground v ee = ? 4.2 to ? 5.7 vdc rt = 50 ? ; v tt = ? 2.0 vdc all levels w.r.t. ground figure 1. ecl standard operation from a negative v ee supply level min typ max units v oh ? 1.025 ? 0.955 ? 0.87 vdc v ih ? 1.165 ? 0.87 vdc v bb ? 1.320 vdc v il ? 1.83 ? 1.475 vdc v ol ? 1.83 ? 1.705 ? 1.62 vdc
www.fairchildsemi.com 2 AN-780 standard negative supply ecl operation and why (continued) the usual recommendation for the v ee plane is to bypass every ecl device at its v ee pin with a good rf quality ceramic capacitor. the point at which the re resistors return to the v ee plane should also be bypassed particu- larly if it is a single return from a multiple resistor r-pak. values from 0.01 f to 0.10 f of the ? high k class ii dielectric ? ceramic z5u grade capacitor are recommended for commercial applications. the lower series inductance inherent in the leadless chip style capacitor is preferred over leaded types for highest frequency performance. the ? mid k class ii dielectric ? ceramic x7r grade capacitor offers acceptable bypass operating characteristics over the broader temperature range of ? 55 c to + 125 c. bulk bypassing of the v ee plane with a 1 f to 10 f is rec- ommended at the point where the v ee supply connects to the plane. aluminum or tantalum electrolytic capacitors are usually used for bulk bypassing. miniaturized surface mount electrolytic capacitors are available for use in high density component applications. in typical ecl system designs, some inter-connection lengths will exceed the critical values and force the consid- eration of transmission line effects. the most common high performance and power efficient termination scheme requires the use of a negative 2.0v v tt termination supply. a single rt resistor in conjunction with the v tt supply will terminate each output's transmission line in its characteris- tic impedance and will also provide optimum bias to the ecl output transistor. the v tt potential will ideally be distributed to the rt termi- nators from a power plane which has low dc series resis- tance and low ac impedance. the low ac impedance is essential to supply the transient energy in the termination resistors during switching. bypassing v tt wherever rt resistors return to the v tt plane is essential to maintaining the low ac impedance of the plane. capacitor recommen- dations for bypassing v tt are the same as for v ee above. the regulation of the v tt supply is not critical. a variation of 5% from nominal causes typically only 12 mv varia- tion in output levels for 50 ? terminations or 7 mv variation for 100 ? terminations. note that in standard ecl configu- ration, the v tt supply need only sink current into its nega- tive terminal (single ended v tt operation with positive terminal grounded). v tt here will typically be a simple series regulated supply. if the need for single negative sup- ply operation is paramount, a less power efficient thevenin termination scheme can be used between the v cc /v cca and v ee planes and selective use of series damping in conjunction with re resistors may also be implemented. the pecl transformation transforming ecl from negative supply to positive supply operations is conceptually quite easy. just offset all stan- dard ecl operating potentials by a positive amount equal to an absolute value within the normal v ee operating range. for f100k 300 series the normal v ee range is ? 4.5 to ? 5.7 vdc. a 5v offset fits nicely within the range and happens to match the nominal potential for ttl systems. thus v ee becomes the 0v ground with v cc /v cca offset to + 5v and v tt (if required) offset to + 3 vdc. figure 2 illus- trates the transformation (from figure 1). f100k 300 series voltage levels specified for positive v cc supply [pecl] operation conditions: v cc /v cca = 4.2 to 5.7 vdc v ee = 0.0v to ground rt = 50 ? ; v tt = v cc ? 2.0 vdc all levels w.r.t. ground figure 2. ecl operation from a positive v cc supply [pecl] considerations for pecl operation all the considerations previously discussed for standard operation still apply; i.e., solid isolated and well bypassed reference planes, etc. some additional considerations apply for pecl operation. pecl input and output levels are referenced to the active positive v cc rail that is variable and subject to line and load regulation. pecl level compatibility between sub-systems or systems can be difficult if precise v cc distribution and accuracy are not maintained throughout. differential pecl signal transmission and reception between systems may be necessary to ease the v cc accuracy burden. this active positive v cc potential is the primary reference for pecl levels and the source of pecl switching cur- rents. the distribution of v cc to pecl logic is just as important as is the ground distribution to the standard ecl configuration. v cc should be delivered from a continuous copper plane with liberal use of high frequency decoupling capacitors at each pecl device's v cc /v cca pins. if ttl or other noisy circuitry is to share the v cc , a sepa- rate powerplane should be provided. ttl switching tran- sients should be isolated from the pecl v cc plane to preserve pecl noise immunity. again, differential pecl operation may be warranted for situations where noise control is limited and good common mode noise rejection is required. the various requirements for output termination and bias previously discussed for standard ecl applies directly to pecl operation. note that the nominal + 3v v tt supply in pecl mode is required to sink current into its positive ter- level min typ max units v oh v cc ? 1.025 v cc ? 0.955 v cc ? 0.87 vdc v ih v cc ? 1.165 v cc ? 0.87 vdc v bb v cc ? 1.320 vdc v il v cc ? 1.83 v cc ? 1.475 vdc v ol v cc ? 1.83 v cc ? 1.705 v cc ? 1.62 vdc
3 www.fairchildsemi.com AN-780 power supply sequencing considerations (continued) minal (single ended v tt operation with negative terminal grounded) from the emitter follower outputs through the rt resistors. a current sinking v tt supply will be necessary if operated single ended to ground. the v tt supply should track the v cc supply keeping a nominal 2v offset to assure optimum biasing of the outputs. the v ee for pecl operation is 0v or ground potential and should be distributed from a continuous copper plane in consideration of handling the transients switching currents from the re bias resistors. although the pecl v ee plane will be somewhat tolerant of ttl noise, the recommenda- tion is to isolate ttl transient switching energy in a sepa- rate ttl ground plane. powerplanes the dedication and organization of powerplanes is essen- tial to successful ecl system design. figure 3 illustrates an optimum powerplane implementation for standard ecl operation on a printed circuit mother board in conjunction with ttl circuitry. figure 4 shows an optimum powerplane configuration for pecl operation. note that the dedication and positioning of separate ecl and ttl powerplanes is intended to preserve ecl noise immunity when operating in a mixed signal environment. figure 3. powerplane layup for standard ecl operation figure 4. powerplane layup for positive referenced ecl the optimum multiple powerplane approach may not be feasible for some designs. logic and powerplane partition- ing (islands) can be used to control noise when ecl and ttl must share the same powerplane. figure 5 illustrates the basic concept where areas of a system board are orga- nized by logic type and share the same horizontal power- plane. low pass filters are usually used to help isolate high frequency signals in sections of the shared plane. power supply sequencing considerations in logic systems where multiple independent power sup- plies are used, or where two independently powered sys- tems are connected logically, some consideration must be given to supply sequencing. this is particularly true for ecl/pecl logic due to placement of esd (electrostatic discharge) protection diodes on the inputs and outputs. figure 6 shows the typical esd diode placement in a f100k 300 series device. figure 7 and figure 8 illustrate independently powered ecl driver and receiver operating with an independent ground referenced v tt termination supply. figure 5. powerplane and logic partitioning figure 6. f100k 300 series esd diode circuit placement when the devices (figure 7) are operated in standard ecl fashion, v ee1 may be off while v ee2 and v tt remain on without causing a forward bias potential on any of the esd diodes. note that both the true and complement outputs of the ecl1 driver will source logic one current simulta- neously to the v tt supply when v ee1 is off while v tt remains on. emitter follower transistors of ecl1 are biased on to a logic high level by the v tt /rt even in absence of v ee1 . the potential for v tt current overload exists under these circumstances. when v ee2 is powered off and v tt remains on, the low rail input esd diode of ecl2 (connected to v ee2 ) will forward bias and conduct heavily as v tt tries to re-power the v ee2 rail. the diode conduction will be limited by the rt resistor and the impedance of the off v ee2 supply in parallel with the ecl2 logic impedance. although the esd diode cur- rent density rating will typically support this current over- stress, the recommendation is to avoid this by insuring that v ee2 and v tt are ramped together and that v ee2 is never more positive than v tt by 0.5v. when the devices (figure 8) are operated in pecl fashion, there is a very clear forward bias hazard to esd diodes when supplies are sequenced. if v cc2 is dropped before v cc1 , the positive referenced emitter followers of ecl1 will attempt to re-power up ecl2 through its high rail input esd diode (connected to v cc ). the ecl emitter follower outputs are low impedance voltage sources (6 ? typical) copper plane 1 signal 2 ttl 0v ground 3 ttl + 5v v cc 4 auxiliary gnd/power/thermal 5 ecl ? 2v v tt 6 ecl ? 4.5v v ee 7 ecl 0v ground 8 signal copper plane 1 signal 2 ttl 0v ground 3 ttl + 5v v cc 4 auxiliary gnd/power/thermal 5 ecl + 3v v tt 6 ecl 0v v ee /ground 7 ecl + 5v v cc 8 signal
www.fairchildsemi.com 4 AN-780 single supply translators?the new wave approach (continued) and can source an incredible amount of current (greater than 200 ma each output). thus v cc2 must never be more negative than v cc1 by 1.0v to avoid current overstress. when v cc1 is powered off and v tt and v ee2 remain on, the output esd diode of ecl1 (connected to v cc1 ) will for- ward bias and conduct heavily as v tt tries to re-power the v cc1 rail. the diode conduction will be current limited by the rt resistor and the impedance of the off v cc1 supply in parallel with the ecl1 impedance. although the esd diode current density rating will typically support this current over- stress, the recommendation is to avoid this by insuring that v tt is never more positive than v cc1 by 0.5v. if v cc1 and v cc2 are dropped while v tt remains on, then v tt tries to re-power both v cc rails through the output esd diode of ecl1 and the high rail input esd diode of ecl2. the forward bias current is limited by the rt resistor and the v cc1 /v cc2 supply impedance in parallel with the collec- tive logic impedance. this diode overstress is undesirable and should be avoided by insuring that v tt is never more positive than v cc1 or v cc2 by more than 0.5v. if v tt is dropped before v cc1 , then increased load current can flow through the rt resistor from the emitter follower output of ecl1. therefore v tt ramping should be timed with v cc1 and v cc2 . from the previous discussion, the most critical concern is that no pecl receiver should be powered down if driven directly by a powered up pecl driver without some form of current limiting. the inputs to the receiver must be current limited with external resistors of 100 ? or greater to be able to survive the overstress caused if v cc1 is ever permitted to be more positive than v cc2 by more than 1.0v. although the use of current limiting resistors will alter the effective input edge rates and device propagation delays slightly, careful selection and placement of resistors will minimize device performance degradation. use of surface mounted chip resistors located close to the input is recommended. figure 7. esd diodes in standard ecl operation figure 8. esd diodes in pecl operation dual supply translators ? the conventional approach dual supply ecl-to-ttl and ttl-to-ecl ic translators have been in general use for several years. these devices perform the logic level translations between ecl operating from a negative v ee supply and ttl operating from a posi- tive v cc supply. this approach naturally allows each logic family to operate in their conventional and data book spec- ified manner. system designers typically are most comfort- able with the dual supply approach. this conventional method permits the use of the most familiar design practice for ecl and should easily yield reliable mixed signal sys- tem operation. the growing list of f100k 300 series dual supply translators, as shown in figure 9, is testimony to the continued popularity and versatility of this approach. note 1: v bb provided for single-ended operation figure 9. table of f100k 300 series dual supply translators single supply translators ? the new wave approach single supply translators that allow pecl-to-ttl or ttl- to-pecl interfaces are a recent addition to the f100k 300 series ecl family. development of these devices is moti- vated by the need for a convenient technique by which higher performance ecl logic can be integrated into exist- ing ttl systems containing a single positive supply. these devices should also provide a vehicle for new lower cost designs of mixed signal single supply systems. figure 10 describes three such devices being offered in the f100k 300 series family. the popularity of pecl operation is expected to grow significantly as designers become more familiar with the technique. as interest and usage of single supply translators increase, the family of this type of device can be expected to expand. a simple illustration of the ease with which the single sup- ply translator can accomplish the interface from ttl to pecl and back to ttl is shown in figure 11. note that the translator devices have on chip v cc partitions that facilitate the use of dual powerplanes for the preservation of ecl features 100324 100325 100329 100395 data bits 6 6 8 9 ecl-to-ttl x x x ttl-to-ecl x x flow-thru x x latched registered x x ecl differential input x (note 1) ecl differential output x ecl output drive ( ? ) 50 50 ecl cutoff (hi z) x ttl output drive (ma) (i ol /i oh ) 20/ ? 2 24/ ? 3 64/ ? 15 ttl 3-state x x ecl control pins x x ttl control pins x tpd e to t (ns max) 4.8 7.7 6.4 tpd t to e (ns max) 3.0 3.9 i ee (ma max) ? 70 ? 37 ? 199 ? 67 i ee (ma max) (cutoff) ? 199 i cc (ma max) 38 65 74 65
5 www.fairchildsemi.com AN-780 operating ecl from a single positive supply single supply translators ? the new wave approach (continued) noise immunity. differential operation on the pecl side of the translator is recommended to be used to maximize noise immunity. a v bb reference voltage output is provided on the 100390 device to facilitate single ended operation. note 2: v bb provided for single-ended operation figure 10. table of f100k 300 series single supply translators figure 11. use of single supply translators features 100390 100391 data bits 6 6 ecl-to-ttl x ttl-to-ecl x cmos-to-ecl ecl differential input x (note 2) ecl differential output x ecl output drive ( ? ) 50 ecl cutoff (hi z) ttl output drive (ma) (i ol /i oh ) 24/ ? 3 ttl 3-state x ttl control pins x x cmos control pins tpd e to t (ns max) 6.4 tpd t to e (ns max) 1.7 tpd c to e (ns max) i ee (ma max) (cutoff) i cc (ma max) 48 60 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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