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description the ads7852 is an 8-channel, 12-bit analog-to-digital (a/d) converter complete with sample-and-hold, internal 2.5v reference and a full 12-bit parallel output interface. typical power dissipation is 13mw at at 500khz throughput rate. the ads7852 features both a nap mode and a sleep mode further reducing the power consumption to 2mw. the input range is from 0v to twice the reference voltage. the reference voltage can be overdriven by an external voltage. the ads7852 is ideal for multi-channel applications where low power and small size are critical. medical instrumenta- tion, high-speed data acquisition and laboratory equipment are just a few of the applications that would take advantage of the special features offered by the ads7852. the ads7852 is available in an tqfp-32 package and is fully specified and guaranteed over the ?0 c to +85 c temperature range. 12-bit, 8-channel, parallel output analog-to-digital converter features 2.5v internal reference 8 input channels 500khz sampling rate single 5v supply 1lsb: inl, dnl guaranteed no missing codes 70db sinad low power: 13mw tqfp-32 package applications data acquisition test and measurement industrial process control medical instruments a d s 7 8 5 2 sar cdac ads7852 output latches and 3-state drivers comparator clk busy wr cs rd a0 a1 a2 8-channel mux internal +2.5v ref buffer v ref 10k ? ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 3-state parallel data bus ads7852 sbas111a ?september 2001 www.ti.com production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 1998, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ads7852 sbas111a 2 electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. analog inputs to agnd, any channel input .............. 0.3v to (v d + 0.3v) ref in ......................................................................... 0.3v to (v d + 0.3v) digital inputs to dgnd .............................................. 0.3v to (v d + 0.3v) ground voltage differences: agnd, dgnd ..................................... 0.3v +v ss to agnd .......................................................................... 0.3v to 6v power dissipation .......................................................................... 325mw maximum junction temperature ................................................... +150 c operating temperature range ......................................... 40 c to +85 c storage temperature range .......................................... 65 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum condi- tions for extended periods may affect device reliability. absolute maximum ratings (1) a2 a1 a0 channel selected 0 0 0 channel 0 0 0 1 channel 1 0 1 0 channel 2 0 1 1 channel 3 1 0 0 channel 4 1 0 1 channel 5 1 1 0 channel 6 1 1 1 channel 7 ads7852 channel selection maximum maximum relative gain specified accuracy error package temperature package ordering transport product (lsb) (lsb) package-lead designator range marking (1) number media, quantity ads7852y 2 40 tqfp-32 pbs 40 c to +85 c a52 ads7852y/250 tape and reel, 250 ads7852y """""" ads7852y/2k tape and reel, 2000 ads7852yb 1 25 tqfp-32 pbs 40 c to +85 c a52 ads7852yb/250 tape and reel, 250 ads7852yb """""" ads7852yb/2k tape and reel, 2000 note: (1) performance grade information is marked on the reel. package/ordering information
ads7852 sbas111a 3 electrical characteristics at t a = 40 c to +85 c, f s = 500khz, f clk = 16 f s , and v ss = +5v, using internal reference, unless otherwise specified. ads7852y ads7852yb parameter conditions min typ max min typ max units resolution 12 ? bits analog input input voltage range 0 5 ?? v input impedance 5m ? ? input capacitance 15 ? pf input leakage current 1 ? a dc accuracy no missing codes 12 ? bits integral linearity error 2 1 lsb (1) differential linearity error 1 0.5 1lsb offset error 2 5 1 ? lsb offset error drift 4 ? ppm/ c offset error match 1 ? lsb gain error (1) ext ref = 2.5000v 15 10 lsb gain error int ref 40 25 lsb gain error drift 25 ? ppm/ c gain error match 1 ? lsb noise 150 ? vrms power supply rejection ratio worst-case ? , +v ss = 5v 5% 1.2 ? lsb sampling dynamics conversion time 13.5 ? clk cycles acquisition time 1.5 ? clk cycles throughput rate 500 ? khz multiplexer settling time 500 ? ns aperture delay 5 ? ns aperture jitter 30 ? ps ac accuracy signal-to-noise ratio 72 ? db total harmonic distortion (3) v in = 5vp-p at 50khz 74 72 77 76 db signal-to-(noise+distortion) v in = 5vp-p at 50khz 68 70 71 72 db spurious free dynamic range v in = 5vp-p at 50khz 76 74 78 77 db channel-to-channel isolation v in = 5vp-p at 50khz 95 ? db reference output internal reference voltage 2.48 2.50 2.52 ??? v internal reference drift 30 ? ppm/ c input impedance cs = gnd 5 ? g ? cs = v ss 5 ? g ? source current (4) static load 50 ? a reference input range 2.0 2.55 ?? v resistance (5) to internal reference voltage 10 ? k ? digital input/output logic family cmos ? logic levels: v ih i ih = +5 a3+v ss + 0.3 ?? v v il i il = +5 a 0.3 0.8 ?? v v oh i oh = 250 a3.5 ? v v ol i ol = 250 a0.4 ? v data format straight binary ? power supply requirement +v ss specified performance 4.75 5.25 ?? v quiescent current 2.6 3.5 ?? ma normal power 13 17.5 ?? mw nap mode current (6) 600 800 ?? a sleep mode current (6) 10 30 ?? a temperature range specified performance 40 +85 ?? c storage 65 +150 ?? c ? specifications same as ads7852y. notes: (1) lsb means least significant bit, with v ref equal to +2.5v, one lsb is 1.22mv. (2) measured relative to an ideal, full-scale input of 4.999v. thus, gain error includes the error of the internal voltage reference. (3) calculated on the first nine harmonics of the input freque ncy. (4) if the internal reference is required to source current to an external load, the reference voltage will change due to the internal 10k ? resistor. (5) can vary 30%. (6) see timing characteristics for further detail.
ads7852 sbas111a 4 top view tqfp pin name description 1 ain0 analog input channel 0 2 ain1 analog input channel 1 3 ain2 analog input channel 2 4 ain3 analog input channel 3 5 ain4 analog input channel 4 6 ain5 analog input channel 5 7 ain6 analog input channel 6 8 ain7 analog input channel 7 9 agnd analog ground, gnd = 0v 10 v ref voltage reference input and output. see electrical characteristics table for ranges. decouple to ground with a 0.1 f ceramic capacitor and a 2.2 f tantalum capacitor. 11 dgnd digital ground, gnd = 0v 12 a2 channel address. see channel selection table for details. 13 a1 channel address. see channel selection table for details. 14 a0 channel address. see channel selection table for details. 15 db11 data bit 11 (msb) 16 db10 data bit 10 17 db9 data bit 9 18 db8 data bit 8 19 db7 data bit 7 20 db6 data bit 6 21 db5 data bit 5 22 db4 data bit 4 23 db3 data bit 3 24 db2 data bit 2 25 db1 data bit 1 26 db0 data bit 0 (lsb) 27 wr write input. active low. use to start a new conversion and to select an analog channel via address inputs a0, a1 and a2 in combination with cs. 28 busy busy output goes low and stays low during a conversion. busy rises when a conversion is complete. 29 clk external clock input. the clock speed determines the conversion rate by the equation: f clk = 16 f sample . 30 rd read input. active low. use to read the data outputs in combination with cs. also use (in conjunction with a0 or a1) to place device in power-down mode. 31 cs chip select input. active low. the combination of cs taken low and wr taken low initiates a new conversion and places the outputs in tri-state mode. 32 v ss voltage supply input. nominally +5v. decouple to ground with a 0.1 f ceramic capacitor and a 10 f tantalum capacitor. pin descriptions pin configuration ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 db2 db3 db4 db5 db6 db7 db8 db9 ads7852y 32 31 30 29 28 27 26 25 v ss cs rd clk busy wr db0 (lsb) db1 9 10 11 12 13 14 15 16 agnd v ref dgnd a2 a1 a0 db11 (msb) db10
ads7852 sbas111a 5 typical characteristics at t a = +25 c, v ss = +5v, f sample = 500khz, f clk = 16 f sample , and internal reference, unless otherwise specified. spectral performance (4096 point fft, f in = 49.561khz, 0.5db) frequency (khz) 0 50 100 150 200 250 amplitude (db) 0 20 40 60 80 100 120 spectral performance (4096 point fft, f in = 100.7081khz, 0.5db) frequency (khz) 0 50 100 150 200 250 amplitude (db) 0 20 40 60 80 100 120 spectral performance (4096 point fft, f in = 199.5851khz, 0.5db) frequency (khz) 0 50 100 150 200 250 amplitude (db) 0 20 40 60 80 100 120 spectral performance (4096 point fft, f in = 247.1921khz, 0.5db) frequency (khz) 0 50 100 150 200 250 amplitude (db) 0 20 40 60 80 100 120 change in spurious free dynamic range and total harmonic distortion vs temperature temperature ( c) 50 25 0 25 50 75 100 sfdr delta from +25 c (db) thd delta from +25 c (db) 1.0 0.5 0.0 0.5 1.0 1.0 0.5 0.0 0.5 1.0 sfdr thd (1) note: (1) first nine harmonics of the input frequency f in = 49.6khz, 0.5db change in signal-to-noise ratio and signal-to-(noise+distortion) vs temperature temperature ( c) 50 25 0 25 50 75 100 snr and sinad delta from +25 c (db) 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 sinad snr f in = 49.6khz, 0.5db
ads7852 sbas111a 6 typical characteristics (cont.) at t a = +25 c, v ss = +5v, f sample = 500khz, f clk = 16 f sample , and internal reference, unless otherwise specified. signal-to-noise and signal-to-(noise+distortion) vs input frequency 76 74 72 70 68 66 10k 100k 1m 1k input frequency (hz) snr sinad snr and sinad (db) spurious free dynamic range and total harmonic distortion vs input frequency 90 85 80 75 70 90 85 80 75 70 10k 100k 1m 1k sfdr (db) thd (db) *first nine harmonics of the input frequency thd* sfdr integral linearity error vs code output code 000 h 400 h 800 h c00 h fff h ile (lsbs) 1.00 0.75 0.50 0.25 0.00 0.25 0.50 0.75 1.00 differential linearity error vs code output code 000 h 400 h 800 h c00 h fff h dle (lsbs) 1.00 0.75 0.50 0.25 0.00 0.25 0.50 0.75 1.00 change in internal reference voltage vs temperature temperature ( c) 50 25 0 25 50 75 100 delta from +25 c (mv) 6.0 4.0 2.0 0.0 2.0 4.0 6.0 change in gain error vs temperature temperature ( c) 50 25 0 25 50 75 100 delta from +25 c (lsb) 8 6 4 2 0 2 4 6 8
ads7852 sbas111a 7 typical characteristics (cont.) at t a = +25 c, v ss = +5v, f sample = 500khz, f clk = 16 f sample , and internal reference, unless otherwise specified. change in gain error vs temperature (with external 2.5v reference) temperature ( c) 50 25 0 25 50 75 100 delta from +25 c (lsb) 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 change in offset vs temperature temperature ( c) 50 25 0 25 50 75 100 delta from +25 c (lsb) 1.0 0.8 0.6 0.4 0.2 0.0 0.2 0.4 change in worst-case channel-to-channel offset mismatch vs temperature temperature ( c) 50 25 0 25 50 75 100 delta from +25 c (lsb) 0.10 0.05 0.00 0.05 0.10 change in worst-case channel-to-channel gain mismatch vs temperature temperature ( c) 50 25 0 25 50 75 100 delta from +25 c (lsb) 0.020 0.015 0.010 0.005 0.000 0.005 0.010 0.015 0.020 change in worst-case integral linearity and differential linearity vs sample rate sample rate (khz) 100 200 300 400 500 600 700 800 delta relative to f sample = 500khz (lsb) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.5 1.0 delta il delta dl change in worst-case integral linearity and differential linearity vs temperature temperature ( c) 50 25 0 25 50 75 100 delta from +25 c (lsb) 0.050 0.025 0.000 0.025 0.050 delta dl delta il
ads7852 sbas111a 8 typical characteristics (cont.) at t a = +25 c, v ss = +5v, f sample = 500khz, f clk = 16 f sample , and internal reference, unless otherwise specified. supply current vs temperature temperature ( c) 50 25 0 25 50 75 100 supply current (ma) 2.680 2.675 2.670 2.665 2.660 2.655 f sample = 500khz supply current vs sample rate sample rate (khz) 100 200 300 400 500 600 supply current (ma) 2.9 2.8 2.7 2.6 2.5 2.4 2.3 change in nap current and sleep current vs temperature temperature ( c) 50 25 0 25 50 75 100 delta from +25 c ( a) 25 20 15 10 5 0 5 10 nap sleep change in gain and offset vs supply voltage v ss (v) 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.20 5.25 5.15 delta from v ss = 5.00v (lsb) 0.25 0.20 0.15 0.10 0.05 0.00 0.05 0.10 0.15 0.20 0.25 offset gain 30 25 20 15 10 5 0 power supply rejection vs power supply ripple frequency power supply rejection (mv/v) 100 10k 100k 1m 1k 10
ads7852 sbas111a 9 theory of operation the ads7852 is a high-speed successive approximation register (sar) analog-to-digital (a/d) converter with an internal 2.5v bandgap reference. the architecture is based on capacitive redistribution which inherently includes a sample/hold function. the converter is fabricated on a 0.6mi- cron cmos process. figure 1 shows the basic operating circuit for the ads7852. the ads7852 requires an external clock to run the conver- sion process. this clock can vary between 200khz (12.5hz throughput) and 8mhz (500khz throughput). the duty cycle of the clock is unimportant as long as the minimum high and low times are at least 50ns and the clock period is at least 125ns. the minimum clock frequency is governed by the parasitic leakage of the capacitive digital-to-analog (cdac) capacitors internal to the ads7852. the front-end input multiplexer of the ads7852 features eight single-ended analog inputs. channel selection is per- formed using the address pins a0 (pin 14), a1 (pin 13), and a2 (pin 12). when a conversion is initiated, the input voltage is sampled on the internal capacitor array. while a conversion is in progress, all channel inputs are discon- nected from any internal function (see truth table for addressing). the range of the analog input is set by the voltage on the v ref pin. with the internal 2.5v reference, the input range is 0v to 5v. an external reference voltage can be placed on v ref , overdriving the internal voltage. the range for the external voltage is 2.0v to 2.55v, giving an input voltage range of 4.0v to 5.1v. figure 1. typical circuit configuration. ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 db2 db3 db4 db5 db6 db7 db8 db9 ads7852y 32 31 30 29 28 27 26 25 chip select read input clock input busy output write input v ss cs rd clk busy wr db0 (lsb) db1 9 10 11 12 13 14 15 16 a2 select a1 select a0 select agnd v ref dgnd a2 a1 a0 db11 (msb) db10 10 f + 0.1 f +5v analog supply + 2.2 f + 0.1 f + 0v to 5v
ads7852 sbas111a 10 analog inputs the ads7852 features eight single-ended inputs. while the static current into each analog input is basically zero, the dynamic current depends on the input voltage and sample rate. essentially, the current into the device must charge the internal hold capacitor during the sample period. after this capacitor has been fully charged, no further input current is required. for optimum performance, the source driving the analog inputs must be capable of charging the input capaci- tance to a 12-bit settling level within the sample period. this can be as little as 350ns in some operating modes. while the converter is in the hold mode, or after the sampling capacitor has been fully charged, the input impedance of the analog input is greater than 1g ? . reference the reference voltage on the v ref pin establishes the full- scale range of the analog input. the ads7852 can operate with a reference in the range of 2.0v to 2.55v corresponding to a full-scale range of 4.0v to 5.1v. the voltage at the v ref pin is internally buffered and this buffer drives the capacitor dac portion of the converter. this is important because the buffer greatly reduces the dynamic load placed on the reference source. since the voltage at v ref will be unavoidably affected by noise and glitches generated during the conversion process, it is highly recommended that the v ref pin be bypassed to ground as outlined in the sections that follow. internal reference the ads7852 contains an onboard 2.5v reference, resulting in a 0v to 5v input range on the analog input. the specifi- cations table gives the various specifications for the internal reference. this reference can be used to supply a small amount of source current to an external load but the load should be static. due to the internal 10k ? resistor, a dy- namic load will cause variations in the reference voltage, and will dramatically affect the conversion result. note that even a static load will reduce the internal reference voltage seen at the buffer input. the amount of reduction depends on the load and the actual value of the internal ?0k ? ?resistor. the value of this resistor can vary by 30%. the v ref pin should be bypassed with a 0.1 f ceramic capacitor placed as close to the ads7852 as possible. in addition, a 2.2 f tantalum capacitor should be used in parallel with the ceramic capacitor. external reference the internal reference is connected to the v ref pin and to the internal buffer via an on-chip 10k ? series resistor. because of this configuration, the internal reference voltage can easily be overridden by an external reference voltage. the voltage range for the external voltage is 2.00v to 2.55v, corresponding to an analog input range of 4.0v to 5.1v. while the external reference will not have to provide significant dynamic current to the v ref in, it does have to drive the series 10k ? resistor that is connected to the 2.5v internal reference. accounting for the maximum difference between the external reference voltage and the internal reference voltage, and the processing variations for the on-chip 10k ? resistor, this current can be as high as 75 a. in addition, the v ref pin should still be bypassed to ground with at least a 0.1 f ceramic capacitor placed as close to the ads7852 as possible. depending on the particular reference and a/d conversion speed, additional bypass capacitance may be required, such as the 2.2 f tanta- lum capacitor shown in the typical circuit configuration (figure 1). close attention should be paid to the stability of any external reference source that is driving the large bypass capacitors present at the v ref pin. basic operation figure 1 shows the simple circuit required to operate the ads7852 with channel 0 selected. a conversion can be initiated by bringing the wr pin (pin 27) low for a minimum of 35ns. busy (pin 28) will output a low during the conversion process and rises only after the conversion is complete. the 12 bits of output data will be valid on pins 15 through 26 following the rising edge of busy. starting a conversion a conversion is initiated on the falling edge of the wr input, with valid signals on a0, a1, a2, and cs. the ads7852 will enter the conversion mode on the first rising edge of the external clock following the wr pin going low. the conversion process takes 13.5 clock cycles (1.5 cycles for the db0 decision, 2 clock cycles for the db5 decision, and 1 clock cycle for each of the other bit deci- sions). this allows 2.5 clock cycles for sampling. upon initiating a conversion, the busy output will go low approximately 20ns after the falling edge of the wr pin. the busy output will return high just after the ads7852 has finished a conversion and the output data will be valid on pins 15 through 26. the rising edge of busy can be used to latch the output data into an external device. it is recom- mended that the data be read immediately after each conver- sion since the switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter? performance (see figure 2). channel addressing the selection of the analog input channel to be converted is controlled by address pins a0, a1, and a2. this channel becomes active on the rising edge of wr with cs held low. the data on the address pins should be stable for at least 10ns prior to wr going high. the address pins are also used to control the power-down functions of the ads7852. careful attention must be paid to the status of the address pins following each conversion. if the user does not want the ads7852 to enter either of the power-down modes following a conversion, the a0 and a1 pins must be low when rd and cs are returned high after reading the data at the end of a conversion (see the power- down mode section of this data sheet for more details).
ads7852 sbas111a 11 reading data data from the ads7852 will appear at pins 15 through 26. the msb will output on pin 15 while the lsb will output on pin 26. the outputs are coded in straight binary (with 0v = 000 h and 5v = fff h ). following a conversion, the busy pin will go high. after busy has been high for at least t 14 seconds, the cs and rd pins may be brought low to enable the 12-bit output bus. cs and rd must be held low for at least 25ns following busy high. data will be valid 30ns after the falling edge of both cs and rd. the output data will remain valid for 20ns following the rising edge of both cs and rd (see figure 2 for the read cycle timing diagram). figure 2. ads7852 write/read timing. digital output straight binary description analog input binary code hex code least significant 1.2207mv bit (lsb) full scale 4.99878v 1111 1111 1111 fff midscale 2.5v 1000 0000 0000 800 midscale 1lsb 2.49878v 0111 1111 1111 7ff zero full scale 0v 0000 0000 0000 000 table i. ideal input voltages and output codes. symbol description min typ max units t conv conversion time 1.75 s t acq acquisition time 0.25 s t ckp clock period 125 5000 ns t ckl clock low 40 ns t ckh clock high 40 ns t 1 wr low prior to rising edge of clk 35 ns t 2 wr low after rising edge of clk 20 ns t 3 cs low after rising edge of clk 20 ns t 4 cs and rd high 25 ns t 5 busy delay after cs low 20 ns t 6 rd low 25 ns t 7 address hold time 5 ns t 8 address setup time 5 ns t 9 bus access time 30 ns t 10 bus relinquish time 5 ns t 11 cs to rd setup time 0 ns t 12 rd to cs hold time 0 ns t 13 clk low to busy high 10 ns t 14 busy to rd delay 0 ns t 15 rd high to clk low 50 ns 123456789 10 11 12 13 14 15 16 123456789 10 11 12 13 14 15 16 12345678 clk hold wr cs busy rd address bus data bus t ckh t ckl t 2 t 4 t 4 t 1 t 3 t conv t acq t ckp conversion n address n + 1 address n + 2 conversion n + 1 hi-z hi-z hi-z data valid data valid t 5 t 10 t 6 t 8 t 7 t 9
ads7852 sbas111a 12 figure 3. entering nap using rd and a0. figure 4. initiating wake-up using rd and a0. power-down mode the ads7852 has two different power-down modes: the nap mode and the sleep mode. in the nap mode, all analog and digital circuitry, with the exception of the voltage reference, is powered off. in the sleep mode, everything is powered off. while the sleep mode affords the lowest power consump- tion, the time to come out of sleep mode can be considerable since it takes the internal reference voltage a finite amount of time to power up and reach a stable value. this latency can result in spurious output data for a minimum of ten conver- sion cycles at a 500khz sampling rate. it should also be noted that any external load connected to the v ref pin will exacerbate this effect since a discharge path for the v ref bypass capacitor is provided during the sleep cycle. even the parasitic leakage of the bypass capacitor itself should be considered if the unit is left in the sleep mode for an extended period. after power-up, this capacitor must be recharged by the internal reference voltage and the on-chip 10k ? series resistor. under worst-case conditions (e.g., the bypass capacitor is completely discharged), the output data can be invalid for several hundred milliseconds. since the nap mode maintains the voltage on the v ref pin by keeping the internal reference powered-up, valid conversions are available immediately after the nap mode is terminated. the simplest way to use the power-down mode is following a conversion. after a conversion has finished and busy has returned high, cs and rd must be brought low for a minimum of 25ns. when rd and cs are returned high, the ads7852 will enter the power-down mode on the rising edge of rd. if cs is always kept low, the power-down mode will be controlled exclusively by rd. depending on the status of the a0 and a1 address pins, the ads7852 will either enter the nap mode, the sleep mode, or be returned to normal operation in the sampling mode. see table ii and figures 3 and 4 for further details. rd a2 a1 a0 power-down mode x 0 0 none x 1 0 sleep x01 nap x 1 1 sleep = signifies rising edge of rd pin. x = don't care table ii. ads7852 power-down mode. cs rd clk busy a0 a1 t 11 t 12 t 7 t 8 t 6 note: rising edge of 1 st rd while a0 = 1 initiates power-down immediately. a1 must be low to enter nap mode. t 13 t 14 cs rd clk a1 a0 t 11 t 12 t 7 t 8 t 6 t 15 note: rising edge of 2nd rd while a0 = 0 places the ads7852 in sample mode. a1 must be low to initiate wake-up.
ads7852 sbas111a 13 in addition to using the address pins in conjunction with rd, the power-down mode can also be terminated implicitly by starting a new conversion (e.g., taking wr low while cs is low). if it is desired to keep the ads7852 in a power- down state for a period that is greater than dictated by the sampling rate, the convert signal driving the wr pin must be disabled. the typical supply current of the ads7852, with a 5v supply and a 500khz sampling rate, is 2.6ma. in the nap mode, the typical supply current is 600 a. in the sleep mode, the current is typically reduced to 10 a. layout for optimum performance, care should be taken with the physical layout of the ads7852 circuitry. this is particu- larly true if the clk input is approaching the maximum throughput rate. the basic sar architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. thus, driving any single conver- sion for an n-bit sar converter, there are n ?indows?in which large external transient voltages can affect the conver- sion result. such glitches might originate from switching power supplies, nearby digital logic, or high power devices. the degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the exter- nal event. their error can change if the external event changes in times with respect to the clk input. with this in mind, power to the ads7852 should be clean and well bypassed. a 0.1 f ceramic bypass capacitor should be placed as close to the device as possible. in addition, a 1 f to 10 f capacitor is recommended. if needed an even larger capacitor and a 5 ? or 10 ? series resistor may be used to low pass filter a noisy supply. the ads7852 draws very little current from an external reference on average as the reference voltage is internally buffered. however, glitches from the conversion process appear at the v ref input and the reference source must be able to handle this. whether the reference is internal or external, the v ref pin should be bypassed with a 0.1 f capacitor. an additional larger ca- pacitor may also be used, if desired. if the reference voltage is external and originates from an op amp, make sure it can drive the bypass capacitor or capacitors without oscillation. the gnd pin should be connected to a clean ground point. in many cases, this will be the ?nalog?ground. avoid connec- tions which are too near the grounding point of a microcontroller or digital signal processor. if needed, run a ground trace directly from the converter to the power supply entry point. the ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. figure 5. timing diagram and test circuits for param- eters in figure 2. voltage waveforms for t dis load circuit for t dis and t en d out test point t dis waveform 2, t en v cc t dis waveform 1 100pf c load 3k ? t dis cs/shdn d out waveform 1 (1) d out waveform 2 (2) 90% 10% v ih notes: (1) waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. (2) waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control.
ads7852 sbas111a 14 mpqf027 november 1995 pbs (s-pqfp-g32) plastic quad flatpack gage plane 16 9 0,13 nom 0,25 0,40 0,70 seating plane 0,10 min 4087735/a 11/95 17 0,17 0,23 8 5,05 4,95 sq 3,50 typ 24 25 1 32 6,90 7,10 sq 1,05 0,95 1,20 max 0,08 0,50 m 0,08 0 C 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. package drawing
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