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features ? 16 channel gps correlator ? 8192 search bins with gps acquisition accelerator ? accuracy: 2.5m cep (stand-alone, s/a off) ? time to first fix: 34s (cold start) ? acquisition sensitivity: ?140 dbm ? tracking sensitivity: ?150 dbm utilizes the arm7tdmi ? arm ? thumb ? processor core ? high-performance 32-bit risc architecture ? high-density 16-bit instruction set ? embedded ice (in-circuit emulator) 128 kbyte internal ram 384 kbyte internal rom with u-blox gps firmware fully programmable external bus interface (ebi) ? maximum external address space of 8 mbytes ? up to 4 chip selects ? software programmable 8-bit/16-bit external data bus 6-channel peripheral data controller (pdc) 8-level priority, individually maska ble, vectored interrupt controller ? 2 external interrupts 32 user-programmable i/o lines 1 usb device port ? universal serial bus (usb) v2.0 fu ll-speed device speci fication compliant ? embedded usb v2.0 full-speed transceiver ? suspend/resume logic ? ping-pong mode for isochronous and bulk endpoints 2 usarts ? 2 dedicated peripheral data cont roller (pdc) channels per usart master/slave spi interface ? 2 dedicated peripheral data controller (pdc) channels ? 8-bit to 16-bit programmable data length ? 4 external slave chip selects programmable watchdog timer advanced power management controller (apmc) ? peripherals can be d eactivated individually ? geared master clock to reduce power consumption ? sleep state with disabled master clock ? hibernate state with 32.768 khz master clock real time clock (rtc) 2.3v to 3.6v or 1.8v supply voltage includes power supervisor 1.8v to 3.3v user-definable i/o voltag e for several gpios with 5v tolerance 1 kbyte battery backup memory 9 mm 9 mm 100-pin bga package (lfbga100) electrostatic sensitive device. observe precautions for handling. gps baseband processor atr0621 summary preliminary rev. 4890as?gps?09/05 note: this is a summary docu ment. a complete document is available under nda. for more information, please con- tact your local atmel sales office.
2 4890as?gps?09/05 atr0621 [preliminary] 1. description the gps baseband processor atr0621 includes a 16-channel gps correlator and is based on the arm7tdmi ? processor core. this processor has a high-performance 32-bit ri sc architecture and very low power con- sumption. in addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. the atr0621 has a usb device port. this port is compliant with the universal serial bus (usb) v2.0 full- speed device specification. the atr0621 has a direct connection to off-chip memory, includ- ing flash, through the external bus interface (ebi). the atr0621 includes full gps firmware, licensed from u-blox ag, which performs the basic gps operation, including tracking, acquisition, na vigation and position data output. for normal pvt (position/velocity/time) applications, there is no need for off-chip flash memory or rom. in order to be able to store configuration settings , connecting a serial eeprom is supported. for customer-specific applications, a so ftware development kit is available. the atr0621 is manufactured using the atmel high-density cmos technology. by combining the arm7tdmi microcontroller core with on-chip sram, 16-channel gps correlator and a wide range of peripheral functions on a monolithic chip, the atr0621 provides a highly-flexi- ble and cost-effective solution for gps applications.
3 4890as?gps?09/05 atr0621 [preliminary] figure 1-1. block diagram embedded ice interface to off-chip memory (ebi) sram 128k rom 384k b r i d g e jtag asb pdc2 usb usart1 usart2 spi pio2 controller watchdog special function reset con- troller advanced power manage- ment controller sdm generator gps accelerator gps correlators pio2 pio2 arm7tdmi apb advanced interrupt controller sram rtc nsleep nshdn xt_in nreset tms tck tdo tdi ntrst dbg_en em_da0 em_da15 em_a1 em_a19 clk23 rf_on p0/nantshort p15/anton p31/rxd1 p18/txd1 p22/rxd2 p21/txd2 p2/boot_mode p3/ncs1 p4/ncs0 p5/nwe/nwr0 p6/noe/nrd p11/em_a21 p10/em_a0/nlb p16/neeprom p8/statusled p28/em_a20 p30/agcout0 p7/nub/nwr1 power supply manager ldo_en ldo_in ldo_out ldobat_in vbat p1/gpsmode0 p12/gpsmode2 p13/gpsmode3 p17/gpsmode5 p23/gpsmode7 p24/gpsmode8 p26/gpsmode10 p27/gpsmode11 p29/gpsmode12 p19/gpsmode6 p25/naadet0 p14/naadet1 p9/extint0 sighi0 siglo0 vbat18 xt_out p20/timepulse usb transceiver usb_dm usb_dp timer counter
4 4890as?gps?09/05 atr0621 [preliminary] 2. architectural overview 2.1 description the atr0621 architecture consis ts of two main buse s, the advanced s ystem bus (asb) and the advanced peripheral bus (apb). the asb is designed for ma ximum performance. it inter- faces the processor with the on-chip 32-bit memories and the external memories and devices by means of the external bus interface (ebi). the apb is designed for accesses to on-chip peripherals and is optimized for low power cons umption. the amba bridge provides an inter- face between the asb and the apb. an on-chip peripheral data controller (pdc 2) transfers data between the on-chip usarts/spi and the on-chip and off-chip memori es without processor intervention. most importantly, the pdc2 removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. it can transfer up to 64k con- tiguous bytes without reprogramming the starting address. as a result, the performance of the microcontroller is increased and the power consumption reduced. the atr0621 peripherals are designed to be eas ily programmable with a minimum number of instructions. each peripheral has a 16 kbyte address space allocated in the upper 3 mbyte of the 4 gbyte address space. (except for the interrupt controller, which has 4 kbyte address space.) the peripheral base address is the lowest address of its memory space. the periph- eral register set is composed of control, mode, data, status, and interrupt registers. to maximize the efficiency of bit manipulati on, frequently written registers are mapped into three memory locations. the first address is used to set the individual register bits, the second resets the bits, and the third address reads the value stored in the register. a bit can be set or reset by writing a ?1? to the corresponding position at the appropriate address. writing a ?0? has no effect. individual bits can thus be mo dified without having to use costly read-modify- write and complex bit-manipulation instructions. all of the external signals of the on-chip peri pherals are under the control of the parallel i/o (pio2) controller. the pio2 controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. after reset, the user must carefully program the pio2 controller in order to define which peripheral signals are connected with off-chip logic. the arm7tdmi ? processor operates in little-endian mode on the atr0621 gps baseband. the processor's internal architecture and the arm ? and thumb ? instruction sets are described in the arm7tdmi datasheet. the memory map and the on-chip peripherals are described in detail in the atr0621 full datas heet. the electrical and mechanical characteris- tics are also documented in the atr0621 full datasheet. the arm standard in-circuit emulation debug interface is supported via the jtag/ice port of the atr0621. features of the rom firmware are described in software documentation available from u-blox ag.
5 4890as?gps?09/05 atr0621 [preliminary] 3. pin configuration 3.1 pinout figure 3-1. pinout lfbga100 (top view) atr0621 1 2 3 4 5 6 7 8 9 10 abcdefghj k table 3-1. atr0621 pinout pin name lfbga100 pin type pull resistor (reset value) (1) firmware label pio bank a pio bank b clk23 g9 in dbg_en h4 in pd em_a1 a6 out em_a2 a5 out em_a3 a4 out em_a4 a2 out em_a5 a3 out em_a6 b5 out em_a7 b4 out em_a8 b2 out em_a9 d4 out em_a10 c2 out em_a11 d6 out em_a12 d7 out em_a13 c3 out em_a14 c1 out em_a15 d5 out em_a16 c6 out em_a17 f8 out notes: 1. pd = internal pull-down resistor, pu = internal pull-up resistor, oh = switched to output high at reset 2. vddio is the supply voltage for the following gpio pins: p1, p2 , p8, p12, p14, p16, p17, p18, p19, p20, p21, p23, p24, p25, p26, p27 and p29 3. vdd_usb is the supply voltage for the following usb pins: usb_dm and usb_dp. for operation of the usb interface, sup- ply of 3.0v to 3.6v is required.
6 4890as?gps?09/05 atr0621 [preliminary] em_a18 b3 out em_a19 c5 out em_da0 b6 i/o pd em_da1 b10 i/o pd em_da2 c7 i/o pd em_da3 c10 i/o pd em_da4 d10 i/o pd em_da5 e7 i/o pd em_da6 e9 i/o pd em_da7 b7 i/o pd em_da8 b8 i/o pd em_da9 a9 i/o pd em_da10 c8 i/o pd em_da11 b9 i/o pd em_da12 d8 i/o pd em_da13 c9 i/o pd em_da14 d9 i/o pd em_da15 e8 i/o pd gnd a1 in gnd a10 in gnd k1 in gnd k10 in ldobat_in k8 in ldo_en h7 in ldo_in k7 in ldo_out h6 out nreset c4 i/o open drain pu nshdn g7 out nsleep j6 out ntrst k2 in pd p0 k9 i/o pd nantshort p1 g3 i/o configurable (pd) gpsmode0 agcout1 p2 g4 i/o configurable (pd) boot_mode ?0? clk32k p3 h5 i/o oh ncs1 ncs1 ?0? p4 a7 i/o oh ncs0 ncs0 ?0? p5 b1 i/o oh nwe/nwr0 nwe/nwr0 ?0? table 3-1. atr0621 pinout (continued) pin name lfbga100 pin type pull resistor (reset value) (1) firmware label pio bank a pio bank b notes: 1. pd = internal pull-down resistor, pu = internal pull-up resistor, oh = switched to output high at reset 2. vddio is the supply voltage for the following gpio pins: p1, p2 , p8, p12, p14, p16, p17, p18, p19, p20, p21, p23, p24, p25, p26, p27 and p29 3. vdd_usb is the supply voltage for the following usb pins: usb_dm and usb_dp. for operation of the usb interface, sup- ply of 3.0v to 3.6v is required.
7 4890as?gps?09/05 atr0621 [preliminary] p6 a8 i/o oh noe/nrd noe/nrd ?0? p7 d2 i/o oh nub/nwr1 nub/nwr1 ?0? p8 g2 i/o statusled ?0? p9 j8 i/o pu extint0 extint0 p10 e4 i/o oh em_a0/nlb em_a0/nlb ?0? p11 h10 i/o oh em_a21 ncs2 em_a21 p12 f3 i/o configurable (pu) gpsmode2 npcs2 p13 g10 i/o pu gpsmode3 extint1 p14 j5 i/o configurable (pd) naadet1 ?0? p15 k5 i/o pd anton p16 e1 i/o configurable (pu) neeprom sighi1 nwd_ovf p17 j4 i/o configurable (pd) gpsmode5 sck1 sck1 p18 k4 i/o configurable (pu) txd1 txd1 ?0? p19 f1 i/o configurable (pu) gpsmode6 siglo1 ?0? p20 h2 i/o configurable (pu) timepulse sck2 sck2 timepulse p21 f2 i/o configurable (pu) txd2 txd2 ?0? p22 h8 i/o pu rxd2 rxd2 p23 h3 i/o configurable (pu) gpsmode7 sck sck mclk_out p24 h1 i/o configurable (p u) gpsmode8 mosi mosi ?0? p25 d1 i/o configurable (pu) naadet0 miso miso ?0? p26 g8 i/o configurable (pu) gpsmode10 nss npcs0 ?0? p27 e2 i/o configurable (pu) gpsmode11 npcs1 p28 g1 i/o oh em_a20 ncs3 em_a20 p29 e3 i/o configurable (pu) gpsmode12 npcs3 p30 g5 i/o pd agcout0 agcout0 ?0? p31 h9 i/o pu rxd1 rxd1 rf_on k6 out pd sighi0 f9 out siglo0 e10 out tck j3 in pu tdi j2 in pu tdo k3 out tms j1 in pu usb_dm f10 i/o usb_dp d3 i/o vbat j7 in table 3-1. atr0621 pinout (continued) pin name lfbga100 pin type pull resistor (reset value) (1) firmware label pio bank a pio bank b notes: 1. pd = internal pull-down resistor, pu = internal pull-up resistor, oh = switched to output high at reset 2. vddio is the supply voltage for the following gpio pins: p1, p2 , p8, p12, p14, p16, p17, p18, p19, p20, p21, p23, p24, p25, p26, p27 and p29 3. vdd_usb is the supply voltage for the following usb pins: usb_dm and usb_dp. for operation of the usb interface, sup- ply of 3.0v to 3.6v is required.
8 4890as?gps?09/05 atr0621 [preliminary] 3.2 signal description vbat18 g6 out vdd18 e6 in vdd18 f7 in vdd18 f6 in vddio (2) e5 in vdd_usb (3) f5 in xt_in j9 in xt_out j10 out table 3-1. atr0621 pinout (continued) pin name lfbga100 pin type pull resistor (reset value) (1) firmware label pio bank a pio bank b notes: 1. pd = internal pull-down resistor, pu = internal pull-up resistor, oh = switched to output high at reset 2. vddio is the supply voltage for the following gpio pins: p1, p2 , p8, p12, p14, p16, p17, p18, p19, p20, p21, p23, p24, p25, p26, p27 and p29 3. vdd_usb is the supply voltage for the following usb pins: usb_dm and usb_dp. for operation of the usb interface, sup- ply of 3.0v to 3.6v is required. table 3-2. atr0621 signal description module name function type active level comment ebi em_a0 to em_a21 external memory address bus output ? all valid after reset em_da0 to em_da15 external memory data bus i/o ? internal pull-down resistor ncs0 to ncs1 chip select output lo w output high in reset state ncs2 to ncs3 chip select output lo w output high in reset state nwr0 lower byte write signal output low output high in reset state nwr1 upper byte write signal output low output high in reset state nrd read signal output low output high in reset state nwe write enable output low out put high in reset state noe output enable output low out put high in reset state nub upper byte select (16-bit sram) out put low output high in reset state nlb lower byte select (16-bit sram) o utput low output high in reset state boot_mode boot mode input input ? pio-controlled after reset, internal pull-down resistor usart txd1-2 transmit data output outp ut ? pio-controlled after reset rxd1-2 receive data input input ? pio-controlled after reset sck1-2 external synchronous serial clock i/o ? pio-controlled after reset usb usb_dp usb data (d+) i/o ? usb_dm usb data (d-) i/o ? apmc rf_on output ? interface to atr0600 rtc nsleep sleep output output low interface to atr0600 nshdn shutdown output output low connect to pin ldo_en xt_in oscillator input input ? rtc oscillator xt_out oscillator output output ? rtc oscillator
9 4890as?gps?09/05 atr0621 [preliminary] spi sck spi clock i/o ? pio-controlled after reset mosi master out slave in i/o ? p io-controlled after reset miso master in slave out i/o ? pio-controlled after reset nss/npcs0 slave select i/o low pio-controlled after reset npcs1-3 slave select output low pio-controlled after reset wd nwd_ovf watchdog timer overflow output ? pio-controlled after reset pio p0-31 programmable i/o port i/o ? input after reset gps gpsmode0-12 gps mode input ? pio -controlled after reset sighi1 digital if input ? interface to atr0600 siglo1 digital if input ? interface to atr0600 sighi2 digital if input ? pio-controlled after reset siglo2 digital if input ? pio-controlled after reset timepulse gps synchronized time pulse output ? pio-controlled after reset jtag/ice tms test mode select input ? internal pull-up resistor tdi test data in input ? internal pull-up resistor tdo test data out output ? tck test clock input ? internal pull-up resistor ntrst test reset input input low internal pull-down resistor dbg_en debug enable input ? internal pull-down resistor clock clk23 clock input input ? interface to atr0600, schmitt trigger input mclk_out master clock output outp ut ? pio-controlled after reset reset nreset reset input i/o low open drain with internal pull-up resistor power vdd18 power ? core voltage 1.8v vbat18 power ? backup power 1.8v vddio power ? variable i/o voltage vdd_usb power ? usb voltage 3.0v to 3.6v gnd power ? ground ldobat ldobat_in power ? 1.8v to 3.6v vbat power ? 1.95v to 3.6v vbat18 out ? 1.8v backup voltage ldo18 ldo_in ldo in power ? 1.65v to 3.6v ldo_out ldo out power ? 1.8v core voltage, max. 100 ma ldo_en ldo enable input ? table 3-2. atr0621 signal description (continued) module name function type active level comment
10 4890as?gps?09/05 atr0621 [preliminary] 3.3 setting gpsmode0 to gpsmode12 the start-up configuration of a rom-based syst em without external non-volatile memory is defined by the status of the gpsmode pins after system reset. alternatively, the system can be configured through message commands passed through the serial interface after start-up. if flash memory is available, configuration data can be st ored in flash memory. if eeprom memory is connected, configuration data can be stored in eeprom. default designates set- tings used by rom firmware if gpsmode configuration is disabled (gpsmode0 =0). 3.3.1 enable gpsmode pin configuration 3.3.2 sensitivity settings table 3-3. gpsmode functions pin function gpsmode0 enable configur ation with gpsmode pins gpsmode1 this pin is used for fixnow functionality and not used for gpsmode configuration gpsmode2 gps sensitivity settings gpsmode3 gpsmode4 this pin (naadet1) is used as active antenna supervisor input and not used for gpsmode configuration gpsmode5 serial i/o configuration gpsmode6 gpsmode7 usb power mode gpsmode8 general i/o configuration gpsmode9 this pin (naadet0) is used as active antenna supervisor input and not used for gpsmode configuration gpsmode10 general i/o configuration gpsmode11 gpsmode12 serial i/o configuration table 3-4. enable configurati on with gpsmode pins gpsmode0 (reset = pd) description 0 ignore all gpsmode pins. the default settings as indicated below are used 1 use settings as specified with gpsmode[2, 3, 5 to 8, 10 to12] table 3-5. gps sensitivity settings gpsmode3 (fixed pu) gpsmode2 (reset = pu) description 0 0 auto mode 0 1 fast mode 1 0 normal mode (default) 1 1 high sensitivity
11 4890as?gps?09/05 atr0621 [preliminary] 3.3.3 serial i/o configuration the atr0621 features a two-stage i/o message and protocol selection procedure for the two available serial ports. at the first stage, a certain protocol can be enabled or disabled for a given usart port. selectable protocols are rtcm, nmea and ubx. at the second stage, messages can be enabled or disabled for each ena bled protocol on each port. in all configura- tions discussed below, all protocols are enabled on all ports. but output messages are enabled in a way that ports appear to communicate at only one protocol. however, each port will accept any input message in any of the three impl emented protocols. both usart ports accept input messages in all three supported protocols (nmea, rtcm and ubx) at the configured baud rate. input messages of all three protocols can be arbitrarily mixed. response to a query input message will always use the same protocol as the query input message. in auto mode, no output message is sent out by default, but all input messages are accepted at any supported ba ud rate. response to query input co mmands will be given the same proto- col and baud rate as it was used for the query command. using the respective configuration commands, periodic output messages can be enabled. the following message settings are used in table 3-6 : table 3-6. serial i/o configuration gpsmode12 (reset = pu) gpsmode6 (reset = pu) gpsmode5 (reset = pd) usart1 (output protocol/ baud rate (kbaud)) usart2 (output protocol/ baud rate (kbaud)) messages information messages 0 0 0 ubx/57.6 nmea/19.2 high user, notice, warning, error 0 0 1 ubx/38.4 nmea/9.6 medium user, notice, warning, error 0 1 0 ubx/19.2 nmea/4.8 low user, notice, warning, error 0 1 1 ?/auto ?/auto off none 1 0 0 nmea/19.2 ubx/57.6 high user, notice, warning, error 1 0 1 nmea/4.8 ubx/19.2 low user, notice, warning, error 1 1 0 nmea/9.6 ubx/38.4 medium user, notice, warning, error 1 1 1 ubx/115.2 nmea/19.2 debug all table 3-7. supported messages at setting low nmea port standard gga, rmc ubx port nav sol, svinfo table 3-8. supported messages at setting medium nmea port standard gga, rmc, gsa, gsv, gll, vtg, zda ubx port nav sol, svinfo, posecef, posllh, status, dop, velecef, velned, timegps, timeutc, clock
12 4890as?gps?09/05 atr0621 [preliminary] the following settings apply if gpsmode configuration is not enabled, that is, gpsmode = 0 ( rom-defaults ): 3.3.4 usb power mode for correct response to the usb host queries, th e device has to know its power mode. this is configured via gpsmode7. if set to bus powered , an upper current limit of 100 ma is reported to the usb host; that is, the devi ce classifies itself as a ?low-p ower bus-powered function? with no more than one usb power unit load. table 3-9. supported messages at setting high nmea port standard gga, rmc, gsa, gsv, gll, vtg, zda, grs, gst proprietary pubx00, pubx03, pubx04 ubx port nav sol, svinfo, posecef, posllh, status, dop, velecef, velned, timegps, timeutc, clock mon schd, io, ipc table 3-10. supported messages at setting debug (additional undocumented message may be part of output data) nmea port standard gga, rmc, gsa, gsv, gll, vtg, zda, grs, gst proprietary pubx00, pubx03, pubx04 ubx port nav sol, svinfo, posecef, posllh, status, dop, velecef, velned, timegps, timeutc, clock mon schd, io, ipc rxm raw (raw message support requires an additional license) table 3-11. serial i/o default setting if gpsmode configuration is deselected (gpsmode0 = 0) usart1/usb nmea usart2 ubx baud rate (kbaud) 57.6, auto enabled 57.6, auto enabled input protocol ubx, nmea, rtcm ubx, nmea, rtcm output protocol nmea ubx messages gga, rmc, gsa, gsv nav: sol, svinfo information messages (ubx inf or nmea txt) user, notice, warning, error user, notice, warning, error table 3-12. usb power modes gpsmode7 (reset = pu) description 0 usb device is bus-powered (max. current limit 100 ma) 1 usb device is self-powered (default)
13 4890as?gps?09/05 atr0621 [preliminary] 3.3.5 active antenna supervisor if gpsmode configuration is enabled, the two pins p0/nantshort and p15/anton, plus one pin of p25/naadet0/miso or p14/naadet1 are initialized as general purpose i/os and used as follows: p15/anton is an output which can be used to switch on and off the antenna power supply. input p0/nantshort will indicate an antenna sh ort circuit, that is, ze ro dc voltage at the antenna, to the firmware. if the antenna is switched off by output p15/anton, it is assumed that also input p0/nantshort will signal zero dc voltage, that is, switch to its active low state. input p25/naadet0/miso or p14/naadet1 will indicate that a dc current is sunk into the antenna. in case of short circuit, both p0 and p25/p14 will be active, that is, at low level. if the antenna is switched off by output p15/anton, it is assumed that input p25/naadet0/miso will also signal zero dc current, that is, sw itch to its active low state. which pin is used as naadet (p14 or p25) depends on the settings of gpsmode11 and gpsmode10 ( table 3-14 ). table 3-13. pin usage of active antenna supervisor pin usage meaning p0/nantshort nantshort active antenna short circuit detection high = no antenna dc short circuit present low = antenna dc short circuit present p25/naadet0/ miso or p14/naadet1 naadet active antenna detection input high = no active antenna present low = active antenna is present p15/anton anton active antenna power on output high = power supply to active antenna is switched on low = power supply to active antenna is switched off table 3-14. antenna detection i/o settings gpsmode11 (reset = pu) gpsmode10 (reset = pu) gpsmode9 (reset = pu) location of naadet comment 0 0 0 p25/naadet0/miso 0 0 1 p25/naadet0/miso 0 1 0 p14/naadet1 reserved for further use. do not use this setting. 0 1 1 p14/naadet1 (default) 1 0 0 p14/naadet1 reserved for further use. do not use this setting. 1 0 1 p14/naadet1 reserved for further use. do not use this setting. 1 1 0 p25/naadet0/miso 1 1 1 p25/naadet0/miso
14 4890as?gps?09/05 atr0621 [preliminary] the antenna superv isor software will be configured as follows: 1. enable control signal 2. enable short circuit detection (power down antenna via anton if short is detected via nantshort) 3. enable open circuit detection via naadet 3.4 external connections for a working gps system figure 3-2. example of an external connection atr0601 sigh sigl sc p1 atr0621 sighi siglo clk23 rf_on nsleep p2 em_da0 - 15 see table 3-15 em_a1 - 19 nc nreset nc see table 3-15 p20 timepulse p16 - 17 see table 3-15 p0 - 7 p9 - 15 see table 3-15 p19 see table 3-15 p23 - 30 see table 3-15 usb_dm usb_dp optional usb p31 p18 optional usart 1 p22 p21 optional usart 2 p8 status led tms nc tdi nc tck nc ntrst nc tdo nc test_mode nc dbg_en nc nshdn ldo_en ldo_out vdd18 +3v (see power supply) ldo_in ldobat_in gnd gnd vbat18 +3v (see power supply) tout1 nc xt_in xt_out 32.368 khz (see rtc)
15 4890as?gps?09/05 atr0621 [preliminary] table 3-15. recommended pin connection pin name recommended external circuit p0/nantshort internal pull-down resistor; can be left open. p1/gpsmode0 pull-up resistor to vdd18 or pull-down resistor to gnd if used as input by user application; connect to gnd or vdd18 if unused or used as gpsmode pin only. see gpsmode definitions in ?setting gpsmode0 to gpsmode12? on page 10 . can be left open if configured as output by user application. if this pin is left open, the gpsmode pin configurat ion feature must be completely disabled by user application. p2/boot_mode internal pull-down resistor, leave open . p3/ncs1 output in default rom firmware: leave open ; only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user applicati on and not always driven from external sources. p4/ncs0 output in default rom firmware: leave open ; only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user applicati on and not always driven from external sources. p5/nwe/nwr0 output in default rom firmware: leave open ; only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user applicati on and not always driven from external sources. p6/noe/nrd output in default rom firmware: leave open ; only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user applicati on and not always driven from external sources. p7/nub/nwr1 output in default rom firmware: leave open ; only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user applicati on and not always driven from external sources. p8/statusled output in default rom firmware: leave open ; only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user applicati on and not always driven from external sources. p9/extint0 pull-up resistor to vdd18 or pull-down resistor to gnd or conne ct to gnd or vdd18 if unused. never leave open. p10/em_a0/nlb output in default rom firmware: leave open ; only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user applicati on and not always driven from external sources. p11/em_a21 pull-up resistor to vdd18 or pull-down resistor to gnd (this pin is used as address line em_a21 by standard firmware, do not connect to gnd or vdd18 directly). never leave open. p12/ncs2/gpsmode2 pull-up resistor to vdd18 or pull-down resistor to gnd if used as input by user application, or connect to gnd or vdd18 if unused or used as gpsmode pin only. see gpsmode definitions in ?setting gpsmode0 to gpsmode12? on page 10 . can be left open if not used as gpsmode pin and configured as output by user application. p13/extint1/gpsmode3/ ncs3 pull-up resistor to vdd18 or pull-down resistor to gnd if used as input by user application, or connect to gnd or vdd18 if unused or used as gpsmode pin only. see gpsmode definitions in section ?setting gpsmode0 to gpsmode12? on page 10 . never leave open. p14/sck0/gpsmode4 pull-up resistor to vdd18 or pull-down resistor to gnd if used as input by user application; connect to gnd or vdd18 if unused or used as gpsmode pin only. see gpsmode definitions in ?setting gpsmode0 to gpsmode12? on page 10 . can be left open if not used as gpsmode pin and configured as output by user application. p15/anton internal pull-down resistor; can be left open. p16/nwd_ovf output in default rom firmware: leave open ; only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user applicati on and not always driven from external sources. p17/sck1/gpsmode5 pull-up resistor to vdd18 or pull-down resistor to gnd if used as input by user application; connect to gnd or vdd18 if unused or used as gpsmode pin only. see gpsmode definitions in ?setting gpsmode0 to gpsmode12? on page 10 . can be left open if not used as gpsmode pin and configured as output by user application. p18/txd1 output in default rom firmware: leave open ; only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user applicati on and not always driven from external sources. note: ?never leave open? means: this pin needs a defined level, even if vdd18 is not supplied and system is in backup mode.
16 4890as?gps?09/05 atr0621 [preliminary] p19/siglo2/gpsmode6 pull-up resistor to vdd18 or pull-down resistor to gnd if used as input by user application; connect to gnd or vdd18 if unused or used as gpsmode pin only. see gpsmode definitions in ?setting gpsmode0 to gpsmode12? on page 10 . can be left open if not used as gpsmode pin and configured as output by user application. p20/sck2/timepulse output in default rom firmware: leave open ; only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user applicati on and not always driven from external sources. p21/txd2 output in default rom firmware: leave open ; only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user applicati on and not always driven from external sources. p22/rxd2 pull-up resistor to vdd18 or connect to vdd18 if unused. pull-do wn resistor also possible if used as gpio input by user application. never leave open. p23/sck/gpsmode7 pull-up resistor to vdd18 or pull-down resistor to gnd if used as input by user application; connect to gnd or vdd18 if unused or used as gpsmode pin only. see gpsmode definitions in ?setting gpsmode0 to gpsmode12? on page 10 . can be left open if not used as gpsmode pin and configured as output by user application. p24/mosi/gpsmode8 pull-up resistor to vdd18 or pull-down resistor to gnd if used as input by user application; connect to gnd or vdd18 if unused or used as gpsmode pin only. see gpsmode definitions in ?setting gpsmode0 to gpsmode12? on page 10 . can be left open if not used as gpsmode pin and configured as output by user application. p25/miso/gpsmode9 pull-up resistor to vdd18 or pull-down resistor to gnd if used as input by user application; connect to gnd or vdd18 if unused or used as gpsmode pin only. see gpsmode definitions in ?setting gpsmode0 to gpsmode12? on page 10 . can be left open if not used as gpsmode pin and configured as output by user application. p26/nss/npcs0/ gpsmode10 pull-up resistor to vdd18 or pull-down resistor to gnd if used as input by user application; connect to gnd or vdd18 if unused or used as gpsmode pin only. see gpsmode definitions in ?setting gpsmode0 to gpsmode12? on page 10 . use pull-up resistor to vdd18, if spi is used. never leave open. p27/npcs1/gpsmode11 pull-up resistor to vdd18 or pull-down resistor to gnd if used as input by user application; connect to gnd or vdd18 if unused or used as gpsmode pin only. see gpsmode definitions in ?setting gpsmode0 to gpsmode12? on page 10 . can be left open if not used as gpsmode pin and configured as output by user application. p28/em_a20/npcs2 output in default rom firmware: leave open ; only needs pull-up resistor to vdd18 or pull-down resistor to gnd if used as gpio input by user applicati on and not always driven from external sources. p29/npcs3/gpsmode12 pull-up resistor to vdd18 or pull-down resistor to gnd if used as input by user application; connect to gnd or vdd18 if unused or used as gpsmode pin only. see gpsmode definitions in ?setting gpsmode0 to gpsmode12? on page 10 . can be left open if not used as gpsmode pin and configured as output by user application. p30/agcout0 internal pull-up resistor, leave open . p31/rxd1 pull-up resistor to vdd18 or connect to vdd18 if unused. pull-do wn resistor also possible if used as gpio input by user application. never leave open. em_da0 to em_da15 if no external memory is used, can be left open (int ernal pull-down). if an external memory is connected to these pins, a defined level is needed when all external memories are inactive. table 3-15. recommended pin connection (continued) pin name recommended external circuit note: ?never leave open? means: this pin needs a defined level, even if vdd18 is not supplied and system is in backup mode.
17 4890as?gps?09/05 atr0621 [preliminary] 4. oscillator figure 4-1. crystal connection 32 khz crystal oscillator xt_in xt_out atr0621 internal 32.768 khz clock rtc 32.768 khz 50 ppm max. 25 pf max. 25 pf 5. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters pin symbol min. max. unit operating free air temperature range ?40 +85 c storage temperature ?60 +150 c dc supply voltage vdd18 ?0.3 +1.95 v dc supply voltage vddio ?0.3 +1.95 v dc supply voltage vdd_usb ?0.3 +3.6 v dc supply voltage ldo_in ?0.3 +3.6 v dc supply voltage ldobat_in ?0.3 +3.6 v dc supply voltage vbat ?0.3 +3.6 v dc input voltage em_da0 to em_da15, p0, p3 to p7, p10, p11, p15, p28, p30, si ghi, siglo, clk23, xt_in, tms, tck, tdi, ntrst, dbg_en, ldo_en, nreset ?0.3 +1.95 v dc input voltage usb_dm, usb_dp ?0.3 +3.6 v dc input voltage p1, p2, p8, p9, p12 to p14, p16 to p27, p29, p30 ?0.3 +5.0 v note: minimum/maximum limits are at +25c ambi ent temperature, unless otherwise specified
18 4890as?gps?09/05 atr0621 [preliminary] 6. power consumption mode conditions typ. unit sleep at 1.8v, no clk23 0.065 (1) ma shutdown rtc and backup sram only 0.007 (1) ma normal satellite acquisition 25 ma normal tracking on 6 channels with 1 fix/s; each additional active tracking channel adds 0.5 ma 14 ma all channels disabled 11 ma note: 1. specified value only 7. electrical characteristics no. parameters test conditions pi n symbol min. typ. max. unit type* 1.1 dc supply voltage core vdd18 vdd18 1.65 1.8 1.95 v 1.2 dc supply voltage vddio domain (1) vddio vddio 1.65 1.8/3.3 3.6 v 1.3 dc supply voltage usb (2) vdd_usb vddusb 3.0 3.3 3.6 v 1.4 dc supply voltage backup domain (3) vbat18 vbat18 1.65 1.8 1.95 v 1.5 dc output voltage vdd18 v o,18 0vdd18v 1.6 dc output voltage vddio v o,io 0 vddio v 1.7 low-level input voltage vdd18 domain vdd18 = 1.65v to 1.95v v il,18 ?0.3 0.3 vdd18 v 1.8 high-level input voltage vdd18 domain vdd18 = 1.65v to 1.95v v ih,18 0.7 vdd18 vdd18 + 0.3 v 1.9 low-level input voltage vddio domain vddio = 1.65v to 3.6v v il,io ?0.3 0.3 vddio v 1.10 high-level input voltage vddio domain vddio = 1.65v to 3.6v v ih,io 0.7 vddio 5.0 v 1.11 low-level input voltage vbat18 domain vbat18 = 1.65v to 1.95v p9, p13, p22, p31 v il,bat ?0.3 0.41 v 1.12 high-level input voltage vbat18 domain vbat18 = 1.65v to 1.95v p9, p13, p22, p31 v ih,bat 1.46 5.0 v 1.13 low-level input voltage usb vdd_usb = 3.0v to 3.6v dp, dm v il,usb ?0.3 0.8 v 1.14 high-level input voltage usb vdd_usb = 3.0v to 3.6v dp, dm v ih,usb 2.0 vdd_usb + 0.3 v *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. vddio is the supply voltage for the following gpio-pins: p1, p2, p8, p12, p14, p16, p17, p1 8, p19, p20, p21, p23, p24, p25, p26, p27 and p29 2. values defined for operating the usb interface. otherwise vdd_usb may be connected to 1.8v or 0v supply. 3. supply voltage vbat18 for backup domain is generated internally by the ldobat.
19 4890as?gps?09/05 atr0621 [preliminary] 9. package lfbga100 8. ordering information extended type number package remarks ATR0621-7FQY lfbga100 9 mm 9 mm, 0.80 mm pitch, pb-free specifications according to din technical drawings package: r-lfgba 100_g dimensions in mm ? 0.08 m a b c 9 0.05 9 0.05 7.2 0.8 a c c 0.2 c c 0.12 0.15 (4x) b seating plane 7.2 1.4 max (0.36) 0.53 ref. 0.27 ... 0.37 bottom view top view a1 corner a1 corner 1 a b c d e f g h j k a e d c b 2345 678910 1098 76 543 21 issue: 1; 02.09.05 drawing-no.: 6.580-5003.01-4 0.8 ? 0.15 m ? 0.38 ... 0.48 (100x) f k j h g
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