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| white electronic designs !" ##$%& '( #) !!"#$ %& % '( ' ) *!+,-!.+, !//+, # & 0 ) 0# 1 2 !-.-3-4 0# 5 0 # 5 6' # * * 7 67 !!" #$ -8(6(&9!: ; 5(661.4% 4<. 6 * 3<.<. ; 6 #$ 9 7 7 4 7 ' - 6 ; 5(661.4% ' * !+,-!.+, !//+,; * 9 * ) - 7 ** * 7 - * ; ' * 9 / 7 ; 7 7 7 7 * !" # $ %" &'('# # $ %" &'('# # ) " *+',-./ # 0 0 # 0 0 0 1 0 0 0 0 # 0 0 # 0 # 0 # # 2# # # # 2 ) 0 ) 3 # # 3 4# # 0 # 0 # # 4 # # 0 # # 5 # # 0 # # 0 $ 0 # # 0 $ 0 0 # 0 0 60 0 0 0 6 7# 0 0 0 0 0 # 7 *+',-./ * "$+, white electronic designs dqmc dqmd dq b dq a dq 8-15 dq 0-7 dq 8-15 dq 0-7 addr 0-11 ba 0 ba 1 dqma dqmb ce ras cas we clk cke ba 0 ba 1 ldqm udqm cs ras cas we clk cke ba 0 ba 1 ldqm udqm cs ras cas we clk cke dq d dq c a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 /ap a 11 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 /ap a 11 dq 0-31 white electronic designs ! "# $ !"# $ % & & ' % & & ' (( ! ) * + $ + $ + $ * , " * * , - ./ * , " * * , && +& ./ ) *(00 ) +&1 * /*2 /** &" 3 * 00 * * 0 0 44 *560 7 8""9 05" 2 0 *" 4 " 4 :2 ,00 0 * 00* 4;2 * ; 4 :2 0 * *2 4 0 * * 0 42 4 * 0 2 0 ; 0 0 2;2 0 " 4<8 0* 60 " 8""* 2 4 0; * 8 4 4 * 40" ;; 2 * 6 / 2 2 / $= / 2 2 (># / &= /? )0 ) 0 : <4 , 00 "2 2% ; (97 0 * 0 " 4 *0 4 ; 2 2% /?< : 2 : 2 : 0 /?0 44 2 : 0 /?0 @4 2 : 2 2%a/?< 0 ) *( " 4 a0 4" 4 a * ;9 ;* 0" 4 /< )0 2 : /<4 0 6 * 6 4 :2 * 6" 0% * 6 0 82 /?a/?< 4(>7 9a/ )0 2 : 1 0 " 4 0 : *0 4 ; 2 2%a/a9a 41<4 ; * 6 1< 8 2 46 (97 @ a@ : 2 02(976 %0 6 2 : (* @ %2 : 2 "" 422 a 4 ; 0 * 44* 00 9 # 0 " 4 *0 2 2% 4 (* 9 4 *1* 2 "" 422 a 4 ; 0 2 " 44* 00 / # 0 " 4 *0 a 2 2% 4 44 * 44* 00a )00 4 : % * 2 * * 4 ; ) : @*0 9 4 *1* 22 ; )0 a * 2 * 00 2 4 4@ a@ 4 ; 0 6 % 6 * 2 * 4; )0 a * 2 * 040 6 4 (* )* 2 * 2 "" 422 a )00 42 b2 @ a@ 2 * 2 6 % 0# * 2 * ; )0 a 6 %06 * 2 * 4* *4 00 ; 0 ;@ a @ ; )0 a @ a@ 00 4 4 ; 26 % * 2 * (> : ( * " 8 4 0 " 0 , ( " 0% 2 0 (>6;; *0 " 4 2 0 0 " 4 9 4 (>7 )0 7 0% " 4 a(>7 0 2 ; 2 2%22 0 4 2 * 0 6;; *0 % 6 1* 2 : " 4 a(>7 0 2 ;c * 4 * 0 0 *4" 0%6 4 6 * ; 0 6 6 2%0 1* * ;(>70 a ) * 4 * 4; * 6;; *0 4 2 * 2 0 4 * 4 * 4; * 6;; *0 "* : 0 "" * "$+, white electronic designs ! " 8 9 ":;9*; * 8!<*& 9 " ;& <= '== +>= ++- " 8 9 ;9*; , $ 8 &, ":& <+ ',= +?= +,= $! 8 % " $ $ # 9 @;& <*- + + + $ & # 9 @;& < & + + + *0 <# & <*- *== *== *== $! 8 % " 0 a$ ! 8 " :%'= 0 " # 9 " ;& < /= /= /= 0 ! 8 $! 8 % " $ $ # 9 @;& <*- *+ *+ *+ $ # 9 @;& < *+ *+ *+ ": % " 0 a$ 0 <# & <*- .= .= .= 9 ":; ! 8 " :%'= 0 # 9 " ;& < &0 ! 8 ,= ,= ,= b! 9+; - 9 " ; ,,= ,+= ,+= b b! . =(+# ' ' ' # white electronic designs $% " " &" % "'" (( " ) ""$% &) ! +==a*=a* **a= *a= ! = = =a*a+a' =a*a+a' , = * *a+a'a= *a=a'a+ * = +a'a=a* +a'a=a* * * 'a=a*a+ 'a+a*a= * ! = = = =a*a+a'a,a-a.a/ =a*a+a'a,a-a.a/ = = * *a+a'a,a-a.a/a= *a=a'a+a-a,a/a. = * = +a'a,a-a.a/a=a* +a'a=a*a.a/a,a- > = * * 'a,a-a.a/a=a*a+ 'a+a*a=a/a.a-a, * = = ,a-a.a/a=a*a+a' ,a-a.a/a=a*a+a' * = * -a.a/a=a*a+a'a, -a,a/a.a*a=a'a+ * * = .a/a=a*a+a'a,a- .a/a,a-a+a'a=a* * * * /a=a*a+a'a,a-a. /a.a-a,a'a+a*a= 2 <=a** ? > & c*& c+ $ 8 c'& c,((( 0 9%; 9 " =a%; ((( a *& ((( +","-% +",". !"#$ %&&' (($) *+ ,-. /*)*+ -.,/*)0 -. / % 1 & *'2*-. /*'2-.,/', -. /&( 1&(3'' 1 4+&( (& 1&(3 5% 1 & * '2*-. /* '2-.,/ ', -. /&( 1&(3''1 4+'&( (& 1&(3 % 1 & *5'2*-. /*5'2-.,/5', -. /&( 1&(3'' 1 4+' &( (& 1&(3 0% &&' 1 * &&&( +'2*-. /* +'2-.,/+',-. /&( (& 67 1 1&(3 ( 7 8( 17* && (( 1&(3 9% 1 & *+'2*-. /*+'2-.,/+', -. /&( 8(& 1 ((* 1 5 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a 9 a 7 a 6 a 5 a 4 a 3 a 8 a 2 a 1 a 0 mode register (mx) address bus m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a 10 a 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m11, m10 = "0, 0" to ensure compatibility with future devices. * "$+, white electronic designs //0#1 *20#1 !!0#1 0 03 0 03 0 03 %6" 9*; <' / *=== > *=== *= *=== <+ /(- *=== *= *=== *+ *=== : " %9*&+; -(, . / 36" 9+; ''' 3)3$ 5"!9'; +(- ' ' 5$ 5"!9'; ''' 6" 9'; +++ 36" 9'; *** ad9+; *(= *(= *(= 3"8!ad //> ": ": %9,; *- += += %9,; *- += += $! 86" 9,; += += +, ":6" 9,; -= *+=&=== -= *+=&=== .= *+=&=== %6" a " 9,; .= /= >= %6" a b!9,&>; /= /= >= " 0 %9-; *** " $! 89-; *** " 9-; *** %9.; *(- *(- *(- 0 b# " 9/; + + + *+* !"#$ #& ( :(&(3 & - '+0/&1 5 && ): && & ;- ) / <'&1 1(&(3((&8 17 81 (&(3((& . 0 & 8 ( & &&7( &&7((&(& ( 9 :( ( * ( 1 ,( 1 7 &'. # white electronic designs 5 $ 0 2 " $:" % % 8" 8" 3 e e $ b! b!9 ; 3 3 3 e e e e % b b! 3 3 e e e e $! 8 " 8 $ ! 8 3 e 3 e e + $! 8 3 e 3 e e 3 e ": 3 e 3 3 e + 5" 3 e 3 e + 5" "! $! 8 3 e 3 e 3 + 3 e 3 e + "! $! 8 3 e 3 3 e 3 + 6 " " 3 e 3 3 e e e e ' 0 " 3 e 3 3 3 e e e e :" 3 e 3 e e e e e e e % e e e e e e e e e , 5" " 3 e e e e e e e e - " 3 e e e e e 3 e e e - $ % e 3 e e e e e e e . @" e 3 3 e e e e e e e . 00 4 # $ !"#$ && #= 1 "*6"* #* #* => 7 (&(3 3#&( -/*)+ 1 3&( *) 1 3&( 5= 6 ((& ?(&(3& * ((& & 8 & #& ( = & (( * @"& a@ 1&6 &* ? &(&(3 . 6 !(&(3& 8 . 0=> ( => 6 = ((&*=> (&(3 1& 1( ( (&(3& => &7 3( 6 ( (& 6 ( 7 * 6 (&(31 -?(&(3& (/ &&1 3 1( 1 == * 7(( b & - / 7(!(&(3& 8 . * "$+, white electronic designs %" """""""""""5 """""""""""""""""""""""" ( . % % $ ( ( 3 e e e e e e e 0# * 3 3 e e e e e @" b b! "! :" + 3 3 3 3 e e @" b b! "!0 " + b b! 3 3 3 e e ) + 3 3 e e e ) + 3 e e e e ) + e e e e e e " " b b! 3 e e e e e e e 0# * $ 3 3 e e e e e $ @"& " + 3 e e e e e ) + 3 e 3 e " " $ + 33 3 ee e 33 3 e e b! " b! ' 33 3 e 6 !6 3 3 3 e e b! 3 3 $ 8" , 3 3 e e e b! " b! 3 3e e ' 3 3 e 6 !6 3 3 e e % b b! , 3 3 $ 8" e e e e e e e $ , 33 e ee e ee b! " " ! 6 !6 % ! 3 e e e e e e 8" @% - ! " : 3 e e e e e e @" @% e e e e e e " " !"#$ % 7 # @" 1& 7((& 6 @" & * (&(3 ' 1& (& @"- / 1 1 ( ". 5 - / ( # :&# ( # 1& =*#& * # ( &1 &&1 3& 1 & &( # 1& 5 $ # $ white electronic designs # $ %" """""" ( $ !6 7 4 ( + 8 6 $ 8" ! 8" + 3 e e b b! b b! +&' 3 e e $! 8 0 " 3 3 ": ": !"b" 3 5" $! 8 ) , 3 3 $! 8 ) + 3 3 e e 6 " " 0 " + 3 3 3 e e 0 " 0 " 3 e e e e e :" 0 " $ - $ 8" ) 3 e e b b! ) 3 e e $! 8 $! 8 . 3 3 ": ) + ": 3 5" 5"f " "b $! 8 /&> 3 3 f " "b $! 8 /&> 3 3 e e 6 " " 0 " 3 3 3 e e 0 " 0 " 3 e e e e e :" 0 " $ 8" ) 3 e e b b! ) 3 e e $! 8 6 " f !$ ! 8 3 3 ": ) , 3 5" 6 " f ! 5" % >&? 3 3 6 " f % >&? 3 3 e e 6 " " 6 " ! 3 3 3 e e 0 " " ! 3 e e e e e :" " ! $ 8" ) 3 e e b b! ) 3 e e $! 8 6 " f !$ ! 8 3 3 ": ) , 5" 3 5" 6 " f 5 "% >&? 3 3 6 " f ! % >&? 3 3 e e 6 " " 6 " ! 3 3 3 e e 0 " " ! 3 e e e e e :" " ! $ 8" ) 3 e e b b! ) 3 e e $! 8 ) , "! 3 3 " : ) , $! 8 3 5 " ) 3 3 ) 3 3 e e 6 " " ) 3 3 3 e e 0 " " ! 3 e e e e e :" " ! * "$+, white electronic designs %" ( $ 7 4 ( + 8 6 $ 8" ) 3 e e b b! ) 3 e e $! 8 ) , 5" "! 3 3 ": ) , $! 8 3 5 " ) 3 3 ) 3 3 e e 6 " " ) 3 3 3 e e 0 " " ! 3 e e e e e :" " ! $ 8" ) 3 e e b b! ) 3 e e $! 8 0 " f 9;" b 3 3 ": ) , $! 8" 8 3 5 " $! 8 ) , 3 3 $! 8 ) , 3 3 e e 6 " " 0 " f 9;" b 3 3 3 e e 0 " 0 " f 9;" b 3 e e e e e :" 0 " f 9;" b $ 8" ) 3 e e b b! ) 3 e e $! 8 ) , 3 3 ": ) ,&*= ": " 8 3 5 " ) , 3 3 ) , 3 3 e e 6 " " 0 " f ": b 3 3 3 e e 0 " 0 " f ": b 3 e e e e e :" 0 " f ": b $ 8" ) 3 e e b b! ) 3 e e $! 8 ) , 3 3 ": ) , 5" :" 8 3 5 " 5"f " "b $! 8 ? 3 3 f " "b $! 8 ? 3 3 e e 6 " " 0 " f ": b 3 3 3 e e 0 " 0 " f ": b 3 e e e e e :" 0 " f ": b $ 8" ) 3 e e b b! ) 3 e e $! 8 ) , 5" :" 8 3 3 " : ) , "! 3 5" ) ,&? $! 8 3 3 ) ,&? 3 3 e e 6 " " 0 " f$! 8 b 3 3 3 e e 0 " 0 " f$! 8 b 3 e e e e e :" 0 " f$! 8 b # $ white electronic designs !"#$ @" 1 ( 7- / 7((& && # 1 3 ( 1 & 3 1& && & ( 5: @" ( 7- / #= - / * @" ( 7-&/ #& # & 1 3*&( 1 3 ( && &:&( 1 3 1 (1 # ( 1 & & 1 3 0: @" ( 7-&/ = * ! . ( 7 - / 1 9 # #=& - / ((1 ( 7 ,+ ( ( ( 7 2( 1( *1 * (78 ( && & 1 3 1 3& - / %" ( $ 7 4 ( + 8 6 $ 8" ) 3 e e b b! ) 3 e e $! 8 ) 3 3 " : ) b!" 8 3 5 " ) 3 3 ) 3 3 e e 6 " " 0 " f b 3 3 3 e e 0 " 0 " f b 3 e e e e e :" 0 " f b $ 8" ) 3 e e b b! ) 3 e e $! 8 ) 8" 3 3 ": ) " 8 3 5 " ) 3 3 ) 3 3 e e 6 " " ) 3 3 3 e e 0 " 0 " f b % 3 e e e e e :" 0 " f b % # $ * "$+, white electronic designs ! " 5" 1& 1& ( ( ( &&1 ( c ( &1 3( ( ( = * ": g 5" = = = * * = * * !"#$ && .( @"d =>( 1e ( " a@ 3 ( 7d ( &&1+c *= $ = * $! 8 = = = = = * = * = = * * * @ @ " = = "" ! 8& : ": b ( = * " ! 8& : ": b ( * = " ! 8& : ": b ( * * " ! 8& : ": b ( = = ! 8&! 8 b ( = * ! 8&! 8 b ( * = ! 8&! 8 b ( * * ! 8&! 8 b ( $ = * ras cas addr ba dqm t ss t sh a 10 /ap cke clock ce cb cc rb ca ra t sh dq row active precharge read write read row active db qc we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high t ss t sh t rcd t rp t ras t rcd t ss t sh t ss bs bs bs bs bs note 3 note 3 note 4 rb note 3 note 2, 3 note 2, 3 note 2 note 4 note 2, 3 ra bs qa t sh t ss t oh t sac t slz t ss t sh t ss t sh t rac t ss t sh t ccd t ch t cl t cc don't care note 2 white electronic designs # $ ras cas addr ba dqm a 10 /ap cke clock ce key raa dq mode register set row active (a-bank) auto refresh auto refresh precharge (all banks) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t rp raa high-z t rfc t rfc high level is necessary high level is necessary don't care * "$+, white electronic designs % & ! # !"#$ ((& 8 ( & &= ( ( 1 ((&- #a ('/ 17 & 7 & 1& ( a 7 & &&1f'g- / (&(3 5(( ( 7( h- i #& ('/i ! &&1f'g 1 -* * *,d&& 1 1 / ras cas addr ba dqm a 10 /ap cke clock ce rb cb0 ca0 ra cl = 2 dq row active (a-bank) write (a-bank) precharge (a-bank) precharge (a-bank) read (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high t rcd t rc rb note 1 ra qa0 t shz t shz t rdl t rdl t rac t rac qa1 qa2 qa3 db0 db1 db2 db3 cl = 3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 t sac t sac t oh t oh note 3 note 4 note 4 note 3 don't care note 2 white electronic designs ' & ! # !"#$ 11 *=>&1 ((& ( 71( ( && a * =a1 ( *&&1 5=>& 37 & ( ( ((& ( 1 1 : ( ((&&&1 3 && ras cas addr ba dqm a 10 /ap cke clock ce cc0 cd0 ca0 ra cl = 2 dq write (a-bank) write (a-bank) read (a-bank) precharge (a-bank) read (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high t rcd ra qa0 t rdl t cdl qa1 qb0 qb1 qb2 dc0 dc1 dd0 dd1 cl = 3 qa0 qa1 qb0 qb1 dc0 dc1 dd0 dd1 don't care cb0 note 2 note 3 note 1 * "$+, white electronic designs ( ! # !"#$ "( 1e ( #* # 6" (&(3 1 1( *1 ( 1 3 1 ras cas addr ba dqm a 10 /ap cke clock ce cac cbd cae rbb caa raa cl = 2 dq read (a-bank) read (a-bank) read (b-bank) row active (b-bank) read (b-bank) precharge (a-bank) read (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high raa qaa2 qaa3 qbb0 qbb1 qbb2 qbb3 qac0 qac1 qbd0 qbd1 qae0 qae1 cl = 3 qaa2 qaa3 qaa0 qaa1 qaa0 qaa1 qbb0 qbb1 qbb3 qbb2 qac0 qac1 qbd0 qbd1 qae0 qae1 don't care cbb note 2 note 1 rbb white electronic designs ! # !"#$ 1 1 ( *=>&1 37 & 1 1 ( *1 ( 1 3 1 ras cas addr ba dqm a 10 /ap cke clock ce cac cbd rbb caa raa dq write (a-bank) write (b-bank) row active (b-bank) write (b-bank) precharge (both banks) write (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high raa daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 dbd0 dbd1 daa1 daa0 daa2 don't care cbb note 2 note 1 rbb t rdl t cdl * "$+, white electronic designs ) & ! # !"$ &1 ( & ras cas addr ba dqm a 10 /ap cke clock ce rac cac caa rbb raa cl = 2 read (a-bank) row active (a-bank) read (a-bank) write (b-bank) precharge (a-bank) row active (b-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high raa qaa3 dbb0 dbb1 dbb2 dbb3 qac0 qac1 qaa1 qaa0 qaa2 don't care cbb note 1 rac rbb t cdl qac2 cl = 3 dq qaa3 dbb0 dbb1 dbb2 dbb3 qac0 qac1 qaa1 qaa0 qaa2 white electronic designs "* &! ! ! # !"$ &1( && 1 &( - ( a )d #6 / ras cas addr ba dqm a 10 /ap cke clock ce cb ca rb ra cl = 2 auto precharge start point (b-bank) auto precharge start point (a-bank) write with auto precharge (b-bank) read with auto precharge (a-bank) row active (b-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high ra qa3 db0 db1 db2 db3 qa1 qa0 qa2 don't care rb cl = 3 dq qa3 db0 db1 db2 db3 qa1 qa0 qa2 * "$+, white electronic designs "" &$ ! # !"$ => 7 1( ras cas addr ba dqm a 10 /ap cke clock ce cb cc ca dq read read dqm write write dqm write dqm clock suspension clock suspension read row active we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ra qa0 t shz t shz qa1 qa2 qa3 dc0 dc2 don't care qb1 qb1 ra note 1 white electronic designs " ! & ! !"#$ && *1 1 # ( 1& 1 7 &=> 1 * ( # ( && 17 # & 1&* 1 * # &1( ( && j%&& 1 ((&j 5 7 & 71 & ras cas addr ba dqm a 10 /ap cke clock ce cab caa raa cl = 2 precharge (a-bank) read (a-bank) burst stop read (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high don't care raa qaa0 qaa1 qaa2 qaa3 qaa4 qab1 qab0 qab3 qab2 qab5 qab4 cl = 3 dq qaa0 qaa1 qaa2 qaa3 qaa4 qab1 qab0 qab3 qab2 qab5 qab4 note 3 1 1 2 2 * "$+, white electronic designs " ! & ! !"#$ && *1 1 # ( 1& = ' ((& 1( ( 1 ( (&&: 1 => 1( ( 7 7 & => & 37 & ( ( ((& ( 11 : ( ((&&&1 3 && 5 7 & 71 & ras cas addr ba dqm a 10 /ap cke clock ce cab caa raa dq precharge (a-bank) write (a-bank) burst stop write (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high don't care raa daa0 daa1 daa2 daa3 daa4 dab1 dab0 dab3 dab2 dab5 dab4 note 2 t rdl t bdl white electronic designs "# ! !"#$ #6 1&1 jf j #- # / #6* 1 & . jj & 1 & 6 #6 ( ( .( *3 & 17& ( .( 1 '((&* ( #6 ( * . ((& ( ras cas addr ba dqm a 10 /ap cke clock ce cbc cad rbb caa raa cl = 2 row active (a-bank) read (a-bank) row active (b-bank) write with auto precharge (b-bank) precharge (both banks) write (a-bank) read with auto precharge (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high raa qab0 qab1 dbc0 qad0 qad1 daa0 don't care cab note 2 rbb rac rac cl = 3 dq qab0 qab1 dbc0 qad0 qad1 daa0 note 1 * "$+, white electronic designs "% +,! ! # !"#$ 1 3&1& ( @"&1 & a@i ( 7( 5 7& (( - / ras cas addr ba dqm a 10 /ap cke clock ce ra ca dq precharge read row active precharge power-down entry precharge power-down exit active power-down entry active power-down exit we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 note 3 note 2 t ss don't care t ss t ss t shz note 1 ra qa1 qa0 qa2 white electronic designs "' ! & !"#$ "* #d # @"&1& (&(3((& (&(3((&* && (& (&(3( 1e ( .( @" 57( & & @" jaj !( 7( & * 81. & # (&(3 1 1&1 @" 0 " 8 @" ( & &. 9 @((&1 81& &. 1 ras cas addr ba dqm a 10 /ap cke clock ce dq auto refresh self refresh entry self refresh exit we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t ss don't care note 1 note 3 note 4 t rfc min note 6 note 5 note 7 hi-z hi-z note 2 * "$+, white electronic designs " ! "( !"#$ 1 3( &1( & 1 # ((& ((& !=" "k:#" #" l a" "* #* #*d6" ( 7 (&(3((& 3&& & (&(3((&&1 1 # ( 7 5& # 1& ras cas addr dqm cke clock ce ra key dq new command new command auto refresh mrs we 012 345678 012345 678910 don't care t rfc hi-z hi-z note 2 note 1 note 3 high high white electronic designs "") - "' aa=:" #:! # ": :aa:"" # = " f": aal: : f"# 4 0 !"# !"# !"# 2.79 (0.110) max 0.711 (0.028) max 1.27 (0.050) typ 1.27 (0.050) typ a b c d e f g h j k l m n p r t u 14.00 (0.551) typ a1 corner 20.32 (0.800) typ 22.00 (0.866) typ 7.62 (0.300) typ r 1.52 (0.060) max (4x) |
Price & Availability of WED3DL328V10BC
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