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M28W431 4 mbit (512kb x8, boot block) low voltage flash memory august 1998 1/27 ai01714b 19 a0-a18 w dq0-dq7 v pp v cc M28W431 g e v ss 8 rp wp figure 1. logic diagram 2.7v to 3.6v supply voltage 12v 5% programming voltage fast access time: 100ns program/erase controller (p/e.c.) automatic static mode memory erase in blocks boot block (top location) with hardware write and erase protection parameter and main blocks 100,000 program/erase cycles low power consumption 20 years data retention defectivity below 1ppm/year electronic signature manufacturer code: 20h device code: f7h description the M28W431 flash memory is a non-volatile memorythat may be erased electricallyat the block level and programmed by byte. the interface is directly compatible with most microprocessors. the device is offered in tsop40 (10 x 20mm) package. a0-a18 address inputs dq0-dq7 data input / outputs e chip enable g output enable w write enable wp write protect rp reset/power down/boot block unlock v pp program & erase supply voltage v cc supply voltage v ss ground table 1. signal names tsop40 (n) 10 x 20mm
v ss dq1 dq2 a7 a1 e a4 a3 a11 a17 a14 a15 dq7 a9 a16 g nc dq5 dq3 nc v cc dq4 dq6 a8 w a18 v pp rp ai02149 M28W431 (normal) 10 1 11 20 21 30 31 40 a0 a12 a13 nc a10 a5 a6 v cc dq0 v ss a2 wp figure 2. tsop pin connections warning: nc = not connected. symbol parameter value unit t a ambient operating temperature (4) 40 to 85 c t bias temperature under bias 50 to 125 c t stg storage temperature 65 to 150 c v io (2, 3) input or output voltages 0.6 to 5 v v cc supply voltage 0.6 to 5 v v (a9, rp) (2) a9, rp voltage 0.6 to 13.5 v v pp (2) program supply voltage, during erase or programming 0.6 to 14 v notes: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not i mplied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. 2. minimum voltage may undershoot to 2v during transition and for less than 20ns. 3. maximum voltage may overshoot to 6v during transition and for less than 20ns. 4. depends on range. table 2. absolute maximum ratings (1) organization the M28W431 is organized as 512k x 8. memory control is provided by chip enable, output enable and write enable inputs. a reset/power down/boot block unlock, tri-level input, places the memory in deep power down, normal operation or enables programming and erasing of the boot block. memory blocks erasure of the memory is in blocks. there are 7 blocks in the memory address space, one boot block of 16 kbytes, two 'key parameter blocks' of 8 kbytes, one 'main block' of 96 kbytes, and three 'main blocks'of 128 kbytes.the M28W431 locates the boot block starting at the top (7ffffh). the blocks mappings are shown in figure 3. each block of the memorycan be erased separatelyover typically 100,000 times and erasure takes typically 1 second. the boot block is hardware protected from accidental programming or erasure, depend- ing on the rp and wp signals. program/erase commands in the boot block are executed only when rp is at v hh or wp is at v ih (while rp is at v ih ). the memory blocks protection scheme is shown in table3. blockerasure may be suspended in order to read data from other blocks of the memory, and then resumed. programming and erasure of the memory blocks is disabled when the program supply is at v ppl . bus operations six operationscan be performedby the appropriate bus cycles, read byte from the array, read elec- tronic signature, output disable, standby, power down and write the command of an instruction. 2/27 M28W431
command interface commands can be written to a command interface (c.i.) latch to perform read, programming, erasure and to monitor the memory's status. when power is first applied, on exit from power down or if v cc falls below v lko , the command interface is reset to read memory array. instructions and commands eight instructions are defined to perform read memory array, read status register, read elec- tronic signature, erase, program, clear status register, erase suspend and erase resume. an internalprogram/erasecontroller (p/e.c.)handles all timing and verification of the program and erase instructions and provides status bits to indicate its operation and exit status. instructions are com- posed of a first command write operation followed by either second command write, to confirm the commands for programming or erase, or a read operationto read data from the array, the electronic signature or the status register. for added data protection, the instructions for byte program and block erase consist of two commands that are written to the memory and which start the automatic p/e.c. operation. byte programming takes typically11 m s, blockerase typically 3 second. erasure of a memory block may be suspended in order to read data from another block and then resumed. a status register may be read at any time, including during the programming or erase cycles, to monitor the progress of the operation. 16k boot block ai01716b 7ffffh 7c000h 7bfffh 7a000h 79fffh 78000h 77fffh 00000h 8k parameter block 8k parameter block 96k main block 128k main block 128k main block 128k main block 60000h 5ffffh 40000h 3ffffh 20000h 1ffffh a0-a18 byte wide M28W431 top boot block figure 3. memory map, byte-wide addresses v pp rp wp first two parametric block other blocks xv il x protected protected v il v ih x protected protected v pplk v ih v il protected unprotected v pplk vih v ih unprotected unprotected notes: x' = don't care rp is the reset/power down/ parametric block unlock input. v pp is the program or erase supply voltage. v ih /v il are logic high and low levels. v pplk is the program voltage lock-out. table 3. memory blocks protection truth table 3/27 M28W431
power saving the M28W431 has a number of power saving features. a cmos standby mode is entered when the chip enablee and the reset/powerdown (rp) signals are at v cc , when the supply current drops to typically 40 m a. a deep power down mode is enabled when the reset/power down (rp) signal is at v ss , where the supply currentdrops to typically 3 m a. the time required to awake from the deep power down mode is 1 m s maximum, with instruc- tions to the c.i. recognised after only 880ns. signal descriptions address inputs (a0-a18). the address signals, inputs for the memory array, are latched during a write operation. a9 address input is also used for the electronic signature operation. when a9 is raised to 12v the electronic signature may be read. the a0 signal is used to select two bytes, when a0 is low the manufacturercode is read and when a0 is high the device code. data input/outputs (dq0-dq7). the data inputs, a byte to be programmedor a command to the c.i., are latched when both chip enable e and write enable w are active. the data output from the memory array, the electronic signature or status register is valid when chip enable e and output enable g are active. the output is high impedance when the chip is deselected or the outputs are disabled. chip enable (e). the chip enable activates the memory control logic, input buffers, decoders and sense amplifiers. e high de-selects the memory and reducesthe power consumption to the standby level. e can also be used to control writing to the command register and to the memory array, while w remains at a low level. both addresses and data inputs are then latched on the rising edge of e. reset/power down (rp). this is a tri-level input which locks the boot block from programming and erasure, and allows the memory to be put in deep power down. when rp is high (up to 4.1v max) and wp is low the boot block is locked and cannot be pro- grammed or erased. when rp is above 11.4v the boot block is unlocked for programmingor erasure. with rp low the memory is in deep power down, and if rp is within v ss +0.2v the lowest supply current is absorbed. output enable (g). the output enable gates the outputs through the data buffers during a read operation. write enable (w). it controls writing to the com- mand register and input address and data latches. both addresses and data inputs are latched on the rising edge of w. write protect (wp). the write protect is an addi- tionnal hardware control input to protect or unpro- tect the boot block from write operations for systems where v hh voltage is not available to rp pin. when v pp is at v pph and rp is at v ih ,ifwpis at v il the boot block is protected; if wp is at v ih , the boot block is unprotected and can be erased and programmed just like all other blocks. when v pp is at v pph and rp is at v hh , the wp is don't care and the boot block is unprotected. see table 3 for a complete picture of the blocks protection scheme. v pp programsupply voltage. thissupply voltage is used for memory programming and erase. v pp 10% tolerance option is provided for applica- tionrequiring maximum 100 writeand erase cycles. v cc supply voltage. it is the main circuit supply. v ss ground. it is the reference for all voltage measurements. device operations operations are defined as specific bus cycles and signals which allow memory read, command write, output disable, standby, power down, and electronic signature read. they are shown in ta- ble 4. operation e g w rp dq0 - dq7 read byte v il v il v ih v ih data output write byte v il v ih v il v ih data input output disable v il v ih v ih v ih hi-z standby v ih xxv ih hi-z power down x x x v il hi-z note: x=v il or v ih ,v pp =v ppl or v pph . table 4. operations 4/27 M28W431
code e g w a0 a9 a1-a8 & a10-a18 dq0 - dq7 manufact. code v il v il v ih v il v id don't care 20h device code v il v il v ih v ih v id don't care f7h note: rp = v ih . table 5. electronic signature read. read operations are used to output the contents of the memory array, the status register or the electronic signature. both chip enable e and output enable g must be low in order to read the output of the memory. the chip enable input also provides power control and should be used for device selection. output enable should be used to gate data ontothe output independentof thedevice selection. the data read depends on the previous command written to the memory (see instructions rd, rsr and rsig). write. write operationsare used to give instruction commands to the memory or to latch input data to be programmed. a write operationis initiated when chip enable e is low and write enable w is low with output enable g high. commands, input data and addresses are latched on the rising edge of w or e. output disable. the data outputs are high imped- ance when the output enable g is high with write enable w high. standby. the memory is in standby when the chip enable e is high. the power consumption is re- duced to the standbylevel and the outputsare high impedance, independent of the output enable g or write enable w inputs. powerdown. thememoryis in power down when rp is low. the power consumption is reduced to the power down level, and outputs are in high impedance, independant of the chip enable e, output enable g or write enable w inputs. electronic signature. two codes identifying the manufacturer and the device can be read from the memory, the manufacturer code for stmi- croelectronics is 20h, and the device codes is f7h. these codes allow programming equipment or ap- plications to automatically match their interface to the characteristics of the particular manufacturer's product. the electronic signature is output by a read array operation when the voltage applied to a9 is at v id , the manufacturer code is output when the address input a0 is low and the devicecode when this input is high. other address inputs are ignored. the electronic signature can also be read, without raising a9 to v id , after giving the memory the instruction rsig (see the relevant instruction). instructions and commands the memory includes a command interface (c.i.) which latches commands written to the memory. instructions are made up from one or more com- mands to perform memory read, read status register, read electronic signature, erase, pro- gram, clear status register, erase suspend and erase resume. these instructions require from 1 to 3 operations, the first of which is always a write operation and is followed by either a further write operation to confirm the first command or a read operation(s) to output data. a status register indicates the p/e.c. status ready or busy, the suspend/in-progress status of erase operations, the failure/success of erase and program operations and the low/correct value of the program supply voltage v pp . the p/e.c. automatically sets bits b3 to b7 and clears bit b6 & b7. it cannot clear bits b3 to b5. the register can be read by the read status register (rsr) instruction and cleared by the clear status register (clrs) instruction. the meaning of the bits b3 to b7 is shown in table 8. bits b0 to b2 are reserved for future use (and should be masked out during status checks). read (rd) instruction. the read instruction con- sists of one write operation giving the command ffh. subsequent read operations will read the addressed memory array content. read status register (rsr) instruction. the read status register instruction may be given at any time, including while the program/erase con- troller is active. it consists of one write operation giving the command 70h. subsequentread opera- tions output the contents of the status register. the contents of the status register are latched on the falling edge of e or g signals, and can be read until e or g returns to its initial high level. either e or g must be toggled to v ih to update the latch. additionally, any read attempt during program or erase operation will automatically output the con- tents of the status register. 5/27 M28W431
mne- monic instruction cycles 1st cycle 2nd cycle operation address (1) data operation address data rd read memory array 1+ write x ffh read (2) read address data rsr read status register 1+ write x 70h read (2) x status register rsig read electronic signature 3 write x 90h read (2) signature address (3) signature ee erase 2 write x 20h write block address d0h pg program 2 write x 40h or 10h write address data input clrs clear status register 1 write x 50h es erase suspend 1 write x b0h er erase resume 1 write x d0h notes: 1. x = don't care. 2. the first cycle of the rd, rsr or rsig instruction is followed by read operations to read memory array, status register or electronic signature codes. any number of read cycle can occur after one command cycle. 3. signature address bit a0=v il will output manufacturer code. address bit a0=v ih will output device code. other address bits are ignored. table 6. instructions read electronic signature (rsig) instruction. this instructionuses 3 operations.it consistsof one write operation giving the command 90h followed by two read operations to output the manufacturer hex code command 00h invalid/reserved 10h alternative program set-up 20h erase set-up 40h program set-up 50h clear status register 70h read status register 90h read electronic signature b0h erase suspend d0h erase resume/erase confirm ffh read array table 7. commands and device codes. the manufacturer code, 20h, is output when the address line a0 is low, and the device code is f7h. it is issued when a0 is high. erase (ee) instruction. this instruction uses two write operations. the first command written is the erase set-up command 20h. the second com- mand is the erase confirm command d0h. during the input of the secondcommand an addressof the block to be erased is given and this is latched into the memory. if the second command given is not the erase confirm command then the status regis- ter bits b4 and b5 are set and the instructionaborts. read operations output the status register after erasure has started. during the executionof the erase by the p/e.c., the memory accepts only the rsr (read status reg- ister) and es (erase suspend) instructions. status register bit b7 returns '0' while the erasure is in progress and '1' when it has completed. after com- pletion the status register bit b5 returns '1' if there has been an erase failure because erasure has not been verified even after the maximum number of erase cycles have been executed. status reg- ister bit b3 returns '1' if v pp does not remain at v pph level when the erasure is attemptedand/or proced- ing. 6/27 M28W431
mne- monic bit name logic level definition note p/ecs 7 p/e.c. status '1' ready indicates the p/e.c. status, check during program or erase, and on completion before checking bits b4 or b5 for program or erase success '0' busy ess 6 erase suspend status '1' suspended on an erase suspend instruction p/ecs and ess bits are set to '1'. ess bit remains '1' until an erase resume instruction is given. '0' in progress or completed es 5 erase status '1' erase error es bit is set to '1' if p/e.c. has applied the maximum number of erase pulses to the block without achieving an erase verify. '0' erase success ps 4 program status '1' program error ps bit set to '1' if the p/e.c. has failed to program a byte. '0' program success vpps 3 v pp status '1' v pp low, abort vpps bit is set if the v pp voltage is below v pph (min) when a program or erase instruction has been executed. '0' v pp ok 2 reserved 1 reserved 0 reserved notes: logic level '1' is high, '0' is low. table 8. status register v pp must be at v pph when erasing, erase should not be attempted when v pp M28W431
erase suspend (es) instruction. the erase op- eration may be suspendedby this instruction which consists of writing the command b0h. the status register bit b6 indicates whether the erase has actually been suspended, b6 = '1', or whether the p/e.c. cycle was the last and the erase is com- pleted, b6 = '0'. during the suspension the memory will respond only to read (rd), read status register (rsr) or erase resume (er) instructions. read operations initially output the status register while erase is suspended but, following a read instruction, data from other blocks of the memory can be read. v pp must be maintained at v pph while erase is sus- pended. if v pp does not remain at v pph or the rp signal goes low while erase is suspended then erase is aborted while bits b5 and b3 of the status register are set. erase operation must be repeated after having cleared the status register, to be cer- tain to erase the block. erase resume (er) instruction. if an erase sus- pend instruction was previously executed, the erase operation may be resumed by giving the command d0h. the status register bit b6 is cleared when erasure resumes. read operations output the status register after the erase is resumed. the suggested flow charts for programs that use the programming, erasure and erase suspend/re- sumefeatures of the memories are shownin figure 11 to figure 13. programming. the memory can be programmed byte-by-byte. the program supply voltage v pp must be applied before program instructions are given, and if the programming is in the boot block, rp must also be raised to v hh or wp set to v ih to unlock the boot block. the programsupply voltage may be applied continuously during programming. the program sequence is started by writing a pro- gram set-up command (40h) to the command interface,this isfollowed by writingthe addressand data byte to the memory. the program/erase con- troller automatically starts and performs the pro- gramming after the second write operation, providing that the v pp voltage (and rp, wp volt- ages if programming the boot block) are correct. during the programming the memory status is checked by reading the status register bit b7 which shows the status of the p/e.c. bit b7 = '1' indicates that programming is completed. a full status check can be made after each byte or after a sequence of data has been programmed. the status check is made on bit b3 for any possible v pp error and on bit b4 for any possible program- ming error. erase. the memory can be erased by blocks. the program supply voltage v pp must be applied be- fore the erase instruction is given, and if the erase is of the boot block rp must also be raised to v hh or wp set to v ih to unlock the boot block. the erase sequence is started by writing an erase set-up command (20h) to the command interface, this is followed by an address in the block to be erased and the erase confirm command (d0h). the program/erase controller automatically starts and performs the block erase, providing the v pp voltage (and the rp and wp voltages if the erase is of the boot block) are correct. during the erase the memory status is checked by reading the status register bit b7 which shows the status of the p/e.c. bit b7 = '1' indicates that erase is completed. a full status check can be made after the block erase by checking bit b3 for any possible v pp error, bits b5 and b6 for any command sequence errors (erase suspended) and bit b5 alone for an erase error. reset. note that after any program or erase in- struction has completed with an error indication or after any v pp transitions down to v ppl the com- mand interface must be reset by a clear status register instruction before data can be accessed. power supply automatic power saving the M28W431 place itself in a lower power state when not beingaccessed. followinga readopera- tion, after a delay equal to the memoryaccess time, the supply current is reduced from a typical read current of 10ma (cmos inputs) to less than 2ma. power down the memory provides a power down control input rp. when this signal is taken to below v ss + 0.2v all internal circuits are switched off and the supply current drops to typically 3 m a and the program current to typically 3 m a. if rp is taken low during a memory read operation then the memory is de-se- lected and the outputs become high impedance. if rp is taken low during a program or erase se- quence then it is aborted and the memory content is no longer valid. recovery from deep power down requires 1 m stoa memory read operation, or 880ns to a command write. on return from power down the status regis- ter is cleared to 00h. 8/27 M28W431
power up the supply voltage v cc and the program supply voltage v pp can be applied in any order. the mem- ory command interface is reset on power up to read memory array, but a negative transition of chip enable e or a change of the addresses is required to ensure valid data outputs. care must be taken to avoid writes to the memory when v cc is above v lko and v pp powers up first. writes can be inhibited by driving either e or w to v ih . the memory is disabled until rp is up to v ih . supply rails normal precautions must be taken for supply volt- age decoupling, each device in a system should have the v cc and v pp rails decoupled with a 0.1 m f capacitor close to the v cc and v ss pins. the pcb trace widths should be sufficient to carry the v pp program and erase currents required. input rise and fall times 10ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v table 9. ac measurement conditions ai01417 3v 0v 1.5v figure 4. ac testing input output waveform ai01968 0.8v out c l = 30pf or 100pf c l includes jig capacitance 3.3k w 1n914 device under test figure 5. ac testing load circuit symbol parameter test condition min max unit c in input capacitance v in =0v 6 pf c out output capacitance v out =0v 12 pf note: 1. sampled only, not 100% tested. table 10. capacitance (1) (t a =25 c, f = 1 mhz ) 9/27 M28W431
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 10 m a i cc (1, 3) supply current (read) ttl e = v il ,g=v il , f = 5mhz 25 ma supply current (read) cmos e = v ss ,g=v ss , f = 5mhz 25 ma i cc1 (3) supply current (standby) ttl e = v ih ,rp=v ih 300 m a supply current (standby) cmos e=v cc 0.2v, rp = v cc 0.2v 150 m a i cc2 (3) supply current (power down) cmos rp = v ss 0.2v 5 m a i cc3 supply current (program) program in progress 50 ma i cc4 supply current (erase) erase in progress 30 ma i cc5 (2) supply current (erase suspend) e = v ih , erase suspended 10 ma i pp program current (read or standby) v pp > v cc 200 m a i pp1 program current (read or standby) v pp v cc 15 m a i pp2 program current (power down) rp = v ss 0.2v 5 m a i pp3 program current (program) program in progress 30 ma i pp4 program current (erase) erase in progress 30 ma i pp5 program current (erase suspend) erase suspended 200 m a v il input low voltage 0.5 0.6 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 2ma 0.4 v v oh output high voltage i oh = 2ma 2.4 v v ppl program voltage (normal operation) 0 4.1 v v pph program voltage (program or erase operations) 5% range 11.4 12.6 v program voltage (program or erase operations) 10% range 10.8 13.2 v v id a9 voltage (electronic signature) 11.4 13 v i id a9 current (electronic signature) a9 = v id 500 m a v lko supply voltage (erase and program lock-out) 2v v hh input voltage (rp, boot unlock) boot block program or erase 11.4 13 v notes: 1. automatic power saving reduces i cc to 2ma typical in static operation. 2. current increases to i cc +i cc5 during a read operation. 3. cmos levels v cc 0.2v and v ss 0.2v. ttl levels v ih and v il . 4. v cc = 3.0v to 3.6v for 100ns speed class. table 11. dc characteristics (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c; v cc (4) = 2.7v to 3.6v; v pp = 12v 5%) 10/27 M28W431
symbol alt parameter M28W431 unit -100 -120 v cc = 3.3v 0.3v c l = 30pf v cc = 2.7v to 3.6v c l = 30pf min max min max t avav t rc address valid to next address valid 100 120 ns t avqv t acc address valid to output valid 100 120 ns t phqv t pwh power down high to output valid 1 1 m s t elqx (2) t lz chip enable low to output transition 0 0 ns t elqv (3) t ce chip enable low to output valid 100 120 ns t glqx (2) t olz output enable low to output transition 0 0 ns t glqv (3) t oe output enable low to output valid 40 45 ns t ehqx (2) t oh chip enable high to output transition 0 0 ns t ehqz (2) t hz chip enable high to output hi-z 35 40 ns t ghqx (2) t oh output enable high to output transition 0 0 ns t ghqz (2) t df output enable high to output hi-z 35 40 ns t axqx (2) t oh address transition to output transition 0 0 ns notes: 1. see ac testing measurement conditions for timing measurements. 2. sampled only, not 100% tested. 3. g may be delayed by up to t elqv -t glqv after the falling edge of e without increasing t elqv . table 12a. read ac characteristics (1) (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c; v pp = 12v 5%) 11/27 M28W431
symbol alt parameter M28W431 unit -150 -180 v cc = 2.7v to 3.6v v cc = 2.7v to 3.6v min max min max t avav t rc address valid to next address valid 150 180 ns t avqv t acc address valid to output valid 150 180 ns t phqv t pwh power down high to output valid 1 1 m s t elqx (2) t lz chip enable low to output transition 0 0 ns t elqv (3) t ce chip enable low to output valid 150 180 ns t glqx (2) t olz output enable low to output transition 0 0 ns t glqv (3) t oe output enable low to output valid 60 70 ns t ehqx (2) t oh chip enable high to output transition 0 0 ns t ehqz (2) t hz chip enable high to output hi-z 50 60 ns t ghqx (2) t oh output enable high to output transition 0 0 ns t ghqz (2) t df output enable high to output hi-z 45 55 ns t axqx (2) t oh address transition to output transition 0 0 ns notes: 1. see ac testing measurement conditions for timing measurements. 2. sampled only, not 100% tested. 3. g may be delayed by up to t elqv -t glqv after the falling edge of e without increasing t elqv . table 12b. read ac characteristics (1) (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c; v pp = 12v 5%) 12/27 M28W431
dq0-dq7 ai01292c valid a0-a18 e rp taxqx tavav valid tavqv telqv telqx tglqv tglqx tphqv power-up and standby address valid and chip enable outputs enabled data valid standby a0-a18 g tghqx tghqz tehqx tehqz figure 6. read mode ac waveforms note: write enable (w) = high 13/27 M28W431
symbol alt parameter M28W431 unit -100 -120 v cc = 3.3v 0.3v c l = 30pf v cc = 2.7v to 3.6v c l = 30pf min max min max t avav t wc write cycle time 100 120 ns t phwl t ps power down high to write enable low 1 1 m s t elwl t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 130 130 ns t dvwh t ds data valid to write enable high 130 130 ns t whdx t dh write enable high to data transition 0 0 ns t wheh t ch write enable high to chip enable high 10 10 ns t whwl t wph write enable high to write enable low 50 50 ns t avwh t as address valid to write enable high 95 95 ns t phhwh (4) t phs power down v hh (boot block unlock) to write enable high 200 200 ns t wphwh write protect high to write enable high 100 120 ns t vphwh (4) t vps v pp high to write enable high 200 200 ns t whax t ah write enable high to address transition 10 10 ns t whqv1 (2, 3) write enable high to output valid 6 6 m s t whqv2 (2, 3) write enable high to output valid (boot block erase) 0.3 0.3 sec t whqv3 (2) write enable high to output valid (parameter block erase) 0.3 0.3 sec t whqv4 (2) write enable high to output valid (main block erase) 1.5 1.5 sec t qvph (4) t phh output valid to reset/power down high 0 0 ns t qvvpl (4) output valid to v pp low 0 0 ns t phbr (4) reset/power down high to boot block relock 200 200 ns notes: 1. see ac testing measurement conditions for timing measurements. 2. time is measured to status register read giving bit b7 = '1'. 3. for program or erase of the boot block rp must be at v hh ,orwpatv ih . 4. sampled only, not 100% tested. table 13a. write ac characteristics, write enable controlled (1) (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c; v pp = 12v 5%) 14/27 M28W431
symbol alt parameter M28W431 unit -150 -180 v cc = 2.7v to 3.6v v cc = 2.7v to 3.6v min max min max t avav t wc write cycle time 150 180 ns t phwl t ps power down high to write enable low 1 1 m s t elwl t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 130 130 ns t dvwh t ds data valid to write enable high 130 130 ns t whdx t dh write enable high to data transition 0 0 ns t wheh t ch write enable high to chip enable high 10 10 ns t whwl t wph write enable high to write enable low 50 50 ns t avwh t as address valid to write enable high 95 95 ns t phhwh (4) t phs power down v hh (boot block unlock) to write enable high 200 200 ns t wphwh write protect high to write enable high 150 180 ns t vphwh (4) t vps v pp high to write enable high 200 200 ns t whax t ah write enable high to address transition 10 10 ns t whqv1 (2, 3) write enable high to output valid 6 6 m s t whqv2 (2, 3) write enable high to output valid (boot block erase) 0.3 0.3 sec t whqv3 (2) write enable high to output valid (parameter block erase) 0.3 0.3 sec t whqv4 (2) write enable high to output valid (main block erase) 1.5 1.5 sec t qvph (4) t phh output valid to reset/power down high 0 0 ns t qvvpl (4) output valid to v pp low 0 0 ns t phbr (4) reset/power down high to boot block relock 200 200 ns notes: 1. see ac testing measurement conditions for timing measurements. 2. time is measured to status register read giving bit b7 = '1'. 3. for program or erase of the boot block rp must be at v hh ,orwpatv ih . 4. sampled only, not 100% tested. table 13b. write ac characteristics, write enable controlled (1) (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c; v pp = 12v 5%) 15/27 M28W431
e g w dq0-dq7 command cmd or data status register rp v pp valid a0-a18 tavav tqvph tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh tphwl twhwl tphhwh tvphwh power-up and set-up command confirm command or data input status register read boot block unblock twhqv1,2,3,4 ai01293e twphwh wp figure 7. program & erase ac waveforms, w controlled note: command input and status register read output is on dq0-dq7 only. 16/27 M28W431
symbol alt parameter M28W431 unit -100 -120 v cc = 3.3v 0.3v c l = 30pf v cc = 2.7v to 3.6v c l = 30pf min max min max t avav t wc write cycle time 100 120 ns t phel t ps power down high to chip enable low 1 1 m s t wlel t cs write enable low to chip enable low 0 0 ns t eleh t cp chip enable low to chip enable high 130 130 ns t dveh t ds data valid to chip enable high 130 130 ns t ehdx t dh chip enable high to data transition 0 0 ns t ehwh t wh chip enable high to write enable high 10 10 ns t ehel t cph chip enable high to chip enable low 50 50 ns t aveh t as address valid to chip enable high 95 95 ns t phheh (4) t phs power down v hh (boot block unlock) to chip enable high 200 200 ns t wpheh write protect high to chip enable high 100 120 ns t vpheh (4) t vps v pp high to chip enable high 200 200 ns t ehax t ah chip enable high to address transition 10 10 ns t ehqv1 (2, 3) chip enable high to output valid 6 6 m s t ehqv2 (2, 3) chip enable high to output valid (boot block erase) 0.3 0.3 sec t ehqv3 (2) chip enable high to output valid (parameter block erase) 0.3 0.3 sec t ehqv4 (2) chip enable high to output valid (main block erase) 1.5 1.5 sec t qvph (4) t phh output valid to reset/power down high 0 0 ns t qvvpl (4) output valid to v pp low 0 0 ns t phbr (4) reset/power down high to boot block relock 200 200 ns notes: 1. see ac testing measurement conditions for timing measurements. 2. time is measured to status register read giving bit b7 = '1'. 3. for program or erase of the boot block rp must be at v hh ,orwpatv ih . 4. sampled only, not 100% tested. table 14a. write ac characteristics, chip enable controlled (1) (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c; v pp = 12v 5%) 17/27 M28W431
symbol alt parameter M28W431 unit -150 -180 v cc = 2.7v to 3.6v v cc = 2.7v to 3.6v min max min max t avav t wc write cycle time 150 180 ns t phel t ps power down high to chip enable low 1 1 m s t wlel t cs write enable low to chip enable low 0 0 ns t eleh t cp chip enable low to chip enable high 130 130 ns t dveh t ds data valid to chip enable high 130 130 ns t ehdx t dh chip enable high to data transition 0 0 ns t ehwh t wh chip enable high to write enable high 10 10 ns t ehel t cph chip enable high to chip enable low 50 50 ns t aveh t as address valid to chip enable high 95 95 ns t phheh (4) t phs power down v hh (boot block unlock) to chip enable high 200 200 ns t wpheh write protect high to chip enable high 150 180 ns t vpheh (4) t vps v pp high to chip enable high 200 200 ns t ehax t ah chip enable high to address transition 10 10 ns t ehqv1 (2, 3) chip enable high to output valid 6 6 m s t ehqv2 (2, 3) chip enable high to output valid (boot block erase) 0.3 0.3 sec t ehqv3 (2) chip enable high to output valid (parameter block erase) 0.3 0.3 sec t ehqv4 (2) chip enable high to output valid (main block erase) 1.5 1.5 sec t qvph (4) t phh output valid to reset/power down high 0 0 ns t qvvpl (4) output valid to v pp low 0 0 ns t phbr (4) reset/power down high to boot block relock 200 200 ns notes: 1. see ac testing measurement conditions for timing measurements. 2. time is measured to status register read giving bit b7 = '1'. 3. for program or erase of the boot block rp must be at v hh ,orwpatv ih . 4. sampled only, not 100% tested. table 14b. write ac characteristics, chip enable controlled (1) (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c; v pp = 12v 5%) 18/27 M28W431
e g dq0-dq7 command cmd or data status register rp v pp valid a0-a18 tavav tqvph tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tphel tehel tphheh tvpheh power-up and set-up command confirm command or data input status register read boot block unblock tehqv1,2,3,4 ai01294d w twpheh wp figure 8. program & erase ac waveforms, e controlled 19/27 M28W431
parameter test conditions M28W431 unit min typ max main block program v pp = 12v 5% 1.4 5.3 sec boot or parameter block erase v pp = 12v 5% 2 8.6 sec main block erase v pp = 12v 5% 3.4 17 sec table 15. byte program, erase times (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c; v cc = 2.7v to 3.6v) write 40h command ai01278 start write address & data read status register yes no b7 = 1 yes no b3 = 0 yes no b4 = 0 end v pp low error (1, 2) program error (1, 2) pg instruction: write 40h command write address & data (memory enters read status state after the pg instruction) do: read status register (e or g must be toggled) while b7 = 1 if b3 = 0, v pp low error: error handler if b4 = 0, program error: error handler figure 9. program flowchart and pseudo code notes: 1. status check of b3 (v pp low) and b4 (program error) can be made after each byte programming or after a sequence. 2. if a v pp low or program erase is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. 20/27 M28W431
write 20h command ai01279 start write block address & d0h command read status register yes no b7 = 1 yes no b3 = 0 yes no b4, b5 = 1 end v pp low error (1) command sequence error ee instruction: write 20h command write block address (a12-a17) & command d0h (memory enters read status state after the ee instruction) do: read status register (e or g must be toggled) if ee instruction given execute suspend erase loop while b7 = 1 if b3 = 0, v pp low error: error handler if b4, b5 = 0, command sequence error: error handler yes no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 0, erase error: error handler figure 10. erase flowchart and pseudo code note: 1. if v pp low or erase error is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. 21/27 M28W431
write b0h command ai01280 start read status register yes no b7 = 1 yes no b6 = 1 erase continues erase complete write ffh command es instruction: write b0h command (memory enters read register state after the es instruction) do: read status register (e or g must be toggled) while b7 = 1 if b6 = 0, erase completed (at this point the memory wich accept only the rd or er instruction) rd instruction: write ffh command one o more data reads from another block write d0h command er instruction: write d0h command to resume erasure read data from another block figure 11. erase suspend & resume flowchart and pseudo code 22/27 M28W431
ai01286c byte identifier yes no 90h read status yes 70h no clear status yes 50h no program set-up yes 40h or 10h no erase set-up yes 20h no erase command error yes ffh wait for command write (1) read status read array program read status yes ready (2) no yes d0h no a b no figure 12. command interface and program erase controller flowchart (a) notes: 1. if no command is written, the command interface remains in its previous valid state. upon power-up, on exit from power-down or if v cc falls below v lko , the command interface defaults to read array mode. 2. p/e.c. status (ready or busy) is read on status register bit 7. 23/27 M28W431
ai01287b read status yes no 70h b erase yes ready (2) no a b0h no read status yes ready (2) no erase suspend yes d0h read status read array yes erase suspended ? read status (read status) yes no (erase resume) no figure 13. command interface and program erase controller flowchart (b) note: 2. p/e.c. status (ready or busy) is read on status register bit 7. 24/27 M28W431
ordering information scheme note: 1. this speed is obtained with a power supply of v cc = 3.3v 0.3v and a load capacitance at 30pf. devices are shipped from the factory with the memory content erased (to ffh). for a list of available options (speed, package, etc...) or for further informationon any aspect of this device, please contact the stmicroelectronics sales office nearest to you. operating voltage w 2.7v to 3.6v array matrix 3 top boot speed -100 (1) 100ns -120 120ns -150 150ns -180 180ns package n tsop40 10 x 20mm option tr tape & reel packing temp. range 1 0 to 70 c 5 20 to 85 c 6 40 to 85 c example: M28W431 -100 n 1 tr 25/27 M28W431
tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.17 0.27 0.007 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 9.90 10.10 0.390 0.398 e 0.50 - - 0.020 - - l 0.50 0.70 0.020 0.028 a 0 5 0 5 n40 40 cp 0.10 0.004 tsop40 - 40 lead plastic thin small outline, 10 x 20mm drawing is not to scale. 26/27 M28W431
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. spec ifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com 27/27 M28W431

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