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?lansc310 microcontroller programmers reference manual rev. a, april 1996
? 1996 by advanced micro devices, inc. advanced micro devices reserves the right to make changes in its products without notice in order to improve design or performance characteristics. this publication neither states nor implies any warranty of any kind, including but not limited to implied warrants of merchantability or ?ness for a particular application. amd assumes no responsibility for the use of any circuitry other than the circuitry in an amd product. the information in this publication is believed to be accurate in all respects at the time of publication, but is subject to change without notice. amd assumes no responsibility for any errors or omissions, and disclaims responsibility for any consequences resulting from the use of the information included herein. additionally, amd assumes no responsibility for the functioning of undescribed features or parameters. trademarks amd, the amd logo and combinations thereof are trademarks of advanced micro devices, inc. am386 and am486 are registered trademarks, ?lan and e86 are trademarks, and fusione86 is a service mark of advanced micro devices, inc. product names used in this publication are for identi?ation purposes only and may be trademarks of their respective companies.
table of contents iii table of contents chapter 1 introduction purpose of this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi in this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii related amd publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii chapter 2 power management 1.1 power management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.1 power-management modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.2 pmu operating-mode transitions . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.1.3 pmu clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.4 reading the pmu mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.5 merging of pmu modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.6 programming example: power-management setup . . . . . . . . . . 1-9 1.1.7 programming example: peripheral-device power . . . . . . . . . . 1-11 1.2 external-device control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.2.1 power-management control pins . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.2.2 programmable general-purpose pins 2 and 3 . . . . . . . . . . . . . 1-15 1.2.3 latched power pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.3 clock-switching logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.3.1 cpu/memory clock switching . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.3.2 clock startup and shutdown logic. . . . . . . . . . . . . . . . . . . . . . 1-16 1.4 activity monitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.5 state-transition timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.6 wake-up logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.7 smi and nmi control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.7.1 temporary-on mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 1.7.2 enabling smis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 1.7.3 processing nmi or smi source. . . . . . . . . . . . . . . . . . . . . . . . . 1-28 1.7.4 accesses to powered-down device smi . . . . . . . . . . . . . . . . . 1-29 1.7.5 treatment of pending smis. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 1.7.6 external smi pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 1.7.7 external smi with a single device . . . . . . . . . . . . . . . . . . . . . . 1-31 1.7.8 external smi with multiple devices. . . . . . . . . . . . . . . . . . . . . . 1-31 1.8 battery-management logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 1.8.1 battery level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 1.8.2 battery level 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 1.8.3 battery level 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 1.8.4 battery level 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 1.8.5 ac input status pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 1.9 suspend/resume pin logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 1.9.1 required initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37 1.9.2 start of smi handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37 1.9.3 suspend input caused the smi . . . . . . . . . . . . . . . . . . . . . . . . 1-37 1.9.4 suspend pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 1.9.5 resume input caused the smi. . . . . . . . . . . . . . . . . . . . . . . . . 1-39 1.9.6 resume pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39 1.9.7 things to avoid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39
iv table of contents 1.10 auto low-speed logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 1.11 micro power-off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 1.12 other power-saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 1.12.1 dma clock stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 1.12.2 data-path disabling logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 1.12.3 slow refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 1.12.4 quiet bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 chapter 3 memory management 2.1 system memory: dram and bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 dram con?urations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.2 refresh and wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.3 maximum isa and local bus con?urations . . . . . . . . . . . . . . . 2-5 2.2 rom-bios memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3 rom-dos memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.5 other memory controller information . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.5.1 rom chip-select command gating . . . . . . . . . . . . . . . . . . . . . 2-14 2.5.2 wait states and command delays . . . . . . . . . . . . . . . . . . . . . . 2-14 2.5.3 high-speed clock rom cycles . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.5.4 rom chip-select signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.5.5 dos chip-select signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.5.6 self-refresh drams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.5.7 80-ns dram support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 chapter 4 pc/at peripheral registers 3.1 bus initialization registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.1 bus initialization enable register (port 3d4h, index 12h) . . . . . 3-2 3.1.2 bus initialization register (port 3d4h, index 19h) . . . . . . . . . . . 3-2 3.1.3 parallel port address select register (port 3d4h, index 20h) . . 3-3 3.2 pc/at-compatible port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.1 interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.2 programmable interval timer registers . . . . . . . . . . . . . . . . . . . 3-4 3.2.3 dma controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.4 dma page registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.5 parallel port interface registers . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.2.6 uart registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.2.7 real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.3 miscellaneous pc/at-compatible port registers . . . . . . . . . . . . . . . . . . 3-20 3.3.1 xt keyboard data register (port 060h) . . . . . . . . . . . . . . . . . . 3-20 3.3.2 port b register (port 061h). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.3.3 nmi/rtc index address register (port 070h) . . . . . . . . . . . . . 3-21 3.3.4 rtc index data register (port 071h) . . . . . . . . . . . . . . . . . . . . 3-21 3.3.5 port 92 (port 092h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 chapter 5 configuration registers 4.1 con?uration register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.1 port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.2 index registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.3 con?uring the ?lansc310 microcontroller . . . . . . . . . . . . . . . . 4-4 4.2 con?uration port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.2.1 con?uration address register (port 022h) . . . . . . . . . . . . . . . 4-11 4.2.2 con?uration data register (port 023h). . . . . . . . . . . . . . . . . . 4-11 4.3 con?uration index registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.3.1 reserved registers (index 00-07h) . . . . . . . . . . . . . . . . . . . . . 4-11 4.3.2 resume mask register (index 08h) . . . . . . . . . . . . . . . . . . . . . 4-11 4.3.3 resume status register (index 09h) . . . . . . . . . . . . . . . . . . . . 4-12
table of contents v 4.3.4 reserved registers (indexes 0a-0eh) . . . . . . . . . . . . . . . . . . . 4-12 4.3.5 reserved register (index 0fh) . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.3.6 reserved registers (indexes 10?9h) . . . . . . . . . . . . . . . . . . . 4-12 4.3.7 i/o timeout register (index 40h) . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.3.8 smi enable register (index 41h) . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.3.9 smi i/o status register (index 42h) . . . . . . . . . . . . . . . . . . . . . 4-14 4.3.10 smi status register (index 43h) . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.3.11 miscellaneous 4 register (index 44h). . . . . . . . . . . . . . . . . . . . 4-15 4.3.12 pio address register (index 45h) . . . . . . . . . . . . . . . . . . . . . . 4-15 4.3.13 pio timer register (index 46h) . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.3.14 drive timer register (index 47h) . . . . . . . . . . . . . . . . . . . . . . . 4-17 4.3.15 control a register (index 48h) . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.3.16 reserved registers (indexes 49?fh) . . . . . . . . . . . . . . . . . . . 4-18 4.3.17 mms memory wait state 2 register (index 50h) . . . . . . . . . . . 4-19 4.3.18 rom con?uration 2 register (index 51h). . . . . . . . . . . . . . . . 4-20 4.3.19 reserved registers (indexes 52?fh) . . . . . . . . . . . . . . . . . . . 4-20 4.3.20 command delay register (index 60h) . . . . . . . . . . . . . . . . . . . 4-20 4.3.21 i/o wait state register (index 61h) . . . . . . . . . . . . . . . . . . . . . 4-22 4.3.22 mms memory wait state 1 register (index 62h) . . . . . . . . . . . 4-23 4.3.23 wait state control register (index 63h) . . . . . . . . . . . . . . . . . . 4-25 4.3.24 version register (index 64h). . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 4.3.25 rom con?uration 1 register (index 65h). . . . . . . . . . . . . . . . 4-27 4.3.26 memory con?uration 1 register (index 66h) . . . . . . . . . . . . . 4-28 4.3.27 mmsa address extension 1 register (index 67h) . . . . . . . . . . 4-29 4.3.28 shadow ram enable 1 register (index 68h) . . . . . . . . . . . . . . 4-29 4.3.29 shadow ram enable 2 register (index 69h) . . . . . . . . . . . . . . 4-30 4.3.30 reserved register (index 6ah). . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4.3.31 miscellaneous 2 register (index 6bh) . . . . . . . . . . . . . . . . . . . 4-30 4.3.32 mms address extension 1 register (index 6ch) . . . . . . . . . . . 4-31 4.3.33 mms address register (index 6dh) . . . . . . . . . . . . . . . . . . . . . 4-31 4.3.34 mms address extension 2 register (index 6eh) . . . . . . . . . . . 4-33 4.3.35 miscellaneous 1 register (index 6fh). . . . . . . . . . . . . . . . . . . . 4-34 4.3.36 miscellaneous 6 register (index 70h). . . . . . . . . . . . . . . . . . . . 4-35 4.3.37 mmsa device 1 register (index 71h). . . . . . . . . . . . . . . . . . . . 4-36 4.3.38 mmsa device 2 register (index 72h). . . . . . . . . . . . . . . . . . . . 4-37 4.3.39 mmsb device register (index 73h) . . . . . . . . . . . . . . . . . . . . . 4-38 4.3.40 mmsb control register (index 74h) . . . . . . . . . . . . . . . . . . . . . 4-39 4.3.41 activity mask 1 register (index 75h). . . . . . . . . . . . . . . . . . . . . 4-40 4.3.42 activity mask 2 register (index 76h). . . . . . . . . . . . . . . . . . . . . 4-41 4.3.43 control b register (index 77h) . . . . . . . . . . . . . . . . . . . . . . . . . 4-42 4.3.44 reserved registers (indexes 78?fh) . . . . . . . . . . . . . . . . . . . 4-42 4.3.45 power control 1 register (index 80h) . . . . . . . . . . . . . . . . . . . . 4-42 4.3.46 power control 2 register (index 81h) . . . . . . . . . . . . . . . . . . . . 4-43 4.3.47 nmi/smi enable register (index 82h) . . . . . . . . . . . . . . . . . . . 4-43 4.3.48 high-speed to low-speed timer register (index 83h) . . . . . . 4-44 4.3.49 low-speed to doze timer register (index 84h) . . . . . . . . . . . . 4-44 4.3.50 doze to sleep timer register (index 85h) . . . . . . . . . . . . . . . . 4-44 4.3.51 sleep to suspend timer register (index 86h) . . . . . . . . . . . . . 4-44 4.3.52 suspend to off timer register (index 87h) . . . . . . . . . . . . . . . 4-45 4.3.53 software mode control register (index 88h) . . . . . . . . . . . . . . 4-45 4.3.54 general-purpose i/o 0 register (index 89h) . . . . . . . . . . . . . . 4-46 4.3.55 reserved registers (indexes 8a-8bh) . . . . . . . . . . . . . . . . . . . 4-46 4.3.56 i/o activity address 0 register (index 8ch) . . . . . . . . . . . . . . . 4-46 4.3.57 i/o activity address 1 register (index 8dh) . . . . . . . . . . . . . . . 4-46 4.3.58 reserved register (index 8eh). . . . . . . . . . . . . . . . . . . . . . . . . 4-46 4.3.59 clock control register (index 8fh). . . . . . . . . . . . . . . . . . . . . . 4-47 4.3.60 reserved register (index 90h) . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 4.3.61 general-purpose i/o control register (index 91h). . . . . . . . . . 4-47
vi table of contents 4.3.62 uart clock enable register (index 92h) . . . . . . . . . . . . . . . . . 4-49 4.3.63 reserved register (index 93h) . . . . . . . . . . . . . . . . . . . . . . . . . 4-49 4.3.64 general-purpose i/o 2 register (index 94h) . . . . . . . . . . . . . . 4-49 4.3.65 general-purpose i/o 3 register (index 95h) . . . . . . . . . . . . . . 4-49 4.3.66 reserved registers (indexes 96?9h) . . . . . . . . . . . . . . . . . . . 4-49 4.3.67 memory write activity lower boundary register (index 9ah) . 4-50 4.3.68 memory write activity upper boundary register (index 9bh) . 4-50 4.3.69 general-purpose i/o 1 register (index 9ch) . . . . . . . . . . . . . . 4-51 4.3.70 reserved register (index 9dh) . . . . . . . . . . . . . . . . . . . . . . . . 4-51 4.3.71 auto low-speed control register (index 9fh) . . . . . . . . . . . . . 4-51 4.3.72 activity status 1 register (index a0h) . . . . . . . . . . . . . . . . . . . 4-53 4.3.73 activity status 2 register (index a1h) . . . . . . . . . . . . . . . . . . . 4-53 4.3.74 pmu status 1 register (index a2h) . . . . . . . . . . . . . . . . . . . . . 4-54 4.3.75 cpu status 0 register (index a3h) . . . . . . . . . . . . . . . . . . . . . 4-54 4.3.76 cpu status 1 register (index a4h) . . . . . . . . . . . . . . . . . . . . . 4-55 4.3.77 nmi/smi control register (index a5h) . . . . . . . . . . . . . . . . . . . 4-56 4.3.78 reserved register (index a6h). . . . . . . . . . . . . . . . . . . . . . . . . 4-56 4.3.79 pmu control 1 register (index a7h). . . . . . . . . . . . . . . . . . . . . 4-56 4.3.80 reserved register (index a8h). . . . . . . . . . . . . . . . . . . . . . . . . 4-57 4.3.81 smi mms upper page register (index a9h) . . . . . . . . . . . . . . 4-57 4.3.82 smi mms page register (index aah). . . . . . . . . . . . . . . . . . . . 4-57 4.3.83 power control 3 register (index abh) . . . . . . . . . . . . . . . . . . . 4-58 4.3.84 power control 4 register (index ach) . . . . . . . . . . . . . . . . . . . 4-59 4.3.85 pmu control 3 register (index adh) . . . . . . . . . . . . . . . . . . . . 4-60 4.3.86 reserved register (index aeh) . . . . . . . . . . . . . . . . . . . . . . . . 4-60 4.3.87 pmu control 2 register (index afh) . . . . . . . . . . . . . . . . . . . . 4-61 4.3.88 function enable 1 register (index b0h) . . . . . . . . . . . . . . . . . . 4-61 4.3.89 function enable 2 register (index b1h) . . . . . . . . . . . . . . . . . . 4-62 4.3.90 pirq con?uration register (index b2h) . . . . . . . . . . . . . . . . . 4-64 4.3.91 miscellaneous 5 register (index b3h) . . . . . . . . . . . . . . . . . . . 4-65 4.3.92 function enable 3 register (index b4h) . . . . . . . . . . . . . . . . . . 4-66 4.3.93 reserved registers (indexes b5h-b7h) . . . . . . . . . . . . . . . . . . 4-66 4.3.94 rom con?uration 3 register (index b8h) . . . . . . . . . . . . . . . 4-67 4.3.95 memory con?uration 2 register (index b9h) . . . . . . . . . . . . . 4-69 4.3.96 miscellaneous 3 register (index bah) . . . . . . . . . . . . . . . . . . . 4-70 appendix a configuration index register reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-1 appendix b xt-keyboard interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .b-1 index
vii list of figures figure 1-1 pmu operating-mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4 figure 1-2 pll control flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-18 figure 1-3 state transition flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-20 figure 1-4 smi processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-26 figure 1-5 smi device-powerdown flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-30 figure 2-1 typical at address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 figure 2-2 ?lansc310 microcontroller bus configurations . . . . . . . . . . . . . . . . . . . . .2-5 figure 2-3 high memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 figure 2-4 copying rom contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 figure 2-5 memory mapping system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9 figure 2-6 mmsa and mmsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 figure 2-7 mms mapping example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12 figure b-1 xt keyboard block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 figure b-2 xt keyboard timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3
viii list of tables table 1-1 pmu clock speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 table 1-2 inactivity states and transition intervals . . . . . . . . . . . . . . . . . . . . . . . . 1-10 table 1-3 power-management setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 table 1-4 power-management control pin settings . . . . . . . . . . . . . . . . . . . . . . . 1-12 table 1-5 pio timeout settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 table 1-6 smi-generation settings for pio accesses . . . . . . . . . . . . . . . . . . . . . . 1-13 table 1-7 pmc pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 table 1-8 wake-up signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 table 1-9 registers that enable smi sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 table 1-10 battery-level management functionality . . . . . . . . . . . . . . . . . . . . . . . . 1-32 table 2-1 memory initialization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 table 2-2 refresh initialization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 table 2-3 memory-speed initialization example . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 table 2-4 33-mhz wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 table 2-5 bus configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 table 2-6 rom-bios address initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 table 2-7 mms mapping example settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 table 2-8 command delay duration for various cycles . . . . . . . . . . . . . . . . . . . . 2-14 table 2-9 wait states for various cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 table 2-10 romcs wait-state control-bit logic. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 table 2-11 doscs wait-state control-bit logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 table 3-1 bus initialization index and data registers . . . . . . . . . . . . . . . . . . . . . . . 3-2 table 3-2 enabling the bus initialization registers . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 table 3-3 parallel port i/o select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 table 3-4 interrupt controller 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 table 3-5 interrupt controller 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 table 3-6 system timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 table 3-7 dma controller 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 table 3-8 dma controller 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 table 3-9 dma page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 table 3-10 interrupt id bit logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 table 3-11 word length bit logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 table 3-12 real-time clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 table 3-13 rtc register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 table 3-14 register a periodic-interrupt rate-selection bits (32.768 khz). . . . . . . 3-18 table 3-15 register a time-base divider-chain bits . . . . . . . . . . . . . . . . . . . . . . . 3-18 table 4-1 configuration port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 table 4-2 mandatory configuration bit settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 table 4-3 recommended configuration bit settings . . . . . . . . . . . . . . . . . . . . . . . . 4-4 table 4-4 pio timer setting logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 table 4-5 pio address range decode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 table 4-6 hard-disk-drive and floppy-disk-drive timer setting bit logic . . . . . . 4-18 table 4-7 rom-dos wait-state select logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 table 4-8 rom-dos command-delay select logic . . . . . . . . . . . . . . . . . . . . . . . 4-19 table 4-9 8-bit isa i/o access command delay . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 table 4-10 8-bit isa memory access command delay. . . . . . . . . . . . . . . . . . . . . . 4-21 table 4-11 rom-bios wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 table 4-12 refresh-cycle wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
ix table 4-13 floppy-disk-drive wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 table 4-14 hard-disk-drive wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 table 4-15 general bus i/o wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 table 4-16 8-bit isa memory-cycle wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 table 4-17 16-bit isa memory-cycle wait states . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 table 4-18 dram first cycle wait state select logic. . . . . . . . . . . . . . . . . . . . . . . 4-25 table 4-19 dram bank miss wait state select logic . . . . . . . . . . . . . . . . . . . . . . . 4-25 table 4-20 read version stepping level decode . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 table 4-21 refresh interval select logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 table 4-22 bus option status table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 table 4-23 memory configuration (dram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 table 4-24 mmsa/b page register i/o addresses . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 table 4-25 page register contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 table 4-26 mmsa base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 table 4-27 mms memory range select logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 table 4-28 pmu mode select logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 table 4-29 pll restart time select logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 table 4-30 hit-count limit bit logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51 table 4-31 trigger period select logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52 table 4-32 low-speed duration period select logic. . . . . . . . . . . . . . . . . . . . . . . . 4-52 table 4-33 last pmu mode indicator bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54 table 4-34 present pmu mode indicator bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55 table 4-35 low-speed pll mode cpu clock speed select. . . . . . . . . . . . . . . . . . 4-60 table 4-36 latch and buffer logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-62 table 4-37 high-speed pll frequency select . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63 table 4-38 ram mode decode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63 table 4-39 interrupt redirect logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65 table 4-40 rom-bios enable and wait-state select logic . . . . . . . . . . . . . . . . . . 4-66 table 4-41 rom-dos enable and wait-state select logic . . . . . . . . . . . . . . . . . . 4-67 table 4-42 rom-dos linear-address decode-size select logic . . . . . . . . . . . . . 4-68 table 4-43 output drive strength select logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-69 table 4-44 i/o drive type description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-69 table 4-45 parallel port pin redefinition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70
introduction xi preface introduction the ?lan sc310 microcontroller is a highly integrated, low-power, single-chip system composed of the am386 sxlv microprocessor plus the additional logic needed for an at-compatible personal computer. it is designed for embedded pc solutions. the ?lansc310 microcontroller features precise power management and high integration, while providing the user with industry-standard interfaces. the ?lansc310 microcontrollers architecture consists of the following functional modules: n the am386sxlv cpu itself, which is optimized for 3.3-v operation and includes system management mode (smm) power-management hardware n a power-management controller that interfaces to the cpu?s smm and is tightly integrated with the internal clock-generator hardware n a pc/at-compatible memory controller and associated mapping hardware n an optional cpu local bus or full isa-bus controller n standard pc/at system logic and peripheral controllers (dma, interrupt controller, timer, isa-bus controller, and epp parallel port) n additional peripheral controllers (uart and real-time clock) purpose of this manual this manual provides supplemental information unique to the ?lansc310 microcontroller, power-management and memory-management programming considerations, and a detailed description of the additional registers. for logic and software descriptions applicable to the am386sxlv cpu, see the am386dxlv and am386sxlv microprocessors technical reference manual, pid 16944. for information on the pc/at-compatible peripherals in the ?lansc310 microcontroller (e.g., 8259a, 8254), refer to the documentation for the individual part.
xii introduction in this manual this manual is organized in the following manner: chapter 1, ?ower management,?explains how to use the power-management features of the ?lansc310 microcontroller to conserve battery power. chapter 2, ?emory management,?describes the pc/at-compatible memory controller and the mms mapping hardware and address spaces. chapter 3, ?c/at peripheral registers, provides information on the standard pc/at peripheral registers. chapter 4, ?on?uration registers, provides information on the ?lansc310 microcon- trollers con?uration registers. appendix a, ?on?uration index register reference, lists the con?uration index regis- ters in alphabetical order. appendix b, ?t-keyboard interface, explains how to implement the xt keyboard func- tion in the ?lansc310 microcontroller. related amd publications to order publications, see ?iterature ordering on the back of this manual. pid no. publication and description 20668 ?lansc310 microcontroller data sheet describes the ?lansc310 microcontrollers technical features, signal pins, internal controllers, and electrical speci?ations. 16944 am386dxlv and am386sxlv microprocessors technical reference manual describes system management mode (smm) and explains how to use the system management interrupt (smi). 19255 fusione86 sm catalog provides information on tools that speed an e86 family embedded product to market. includes products from expert suppliers of embedded development software.
power management 1-1 chapter 1 power management in general, the purpose of todays power management is to reduce the wattage consumption of battery-powered computers in order to extend the useful amount of computing that can be done with a single battery charge. power management is based on the following principal techniques: n employing process technologies (e.g., cmos) that have intrinsically low power requirements n employing lower voltages whenever possible n continuously monitoring the activity of the computer and either turning off components that are not in use or reducing their clock speed all these techniques are extensively employed in the ?lansc310 microcontroller, but only the third technique is under programmer control. power management monitors all system activities (e.g., keyboard, screen, and disk events) and?ased on the state of the sys- tem?etermines in which operating mode the system should be running for best power conservation. in addition, the ?lansc310 microcontroller can manage the power consumption of peripheral devices. this control can be integrated into the operating-mode mechanism, or it can be handled separately via the system management interrupt (smi). the ?lansc310 microcontroller can be programmed so that various conditions, such as peripheral accesses, can cause an smi to occur. an smi causes the cpu to save the operating state of the processor and switch to a special interrupt service routine. this routine can then be used to turn on peripherals. the ?lansc310 microcontrollers power management unit (pmu) controls ?e power- management control (pmc) pins and four programmable general-purpose i/o (pgp) pins that can be used by system designers to control different external peripherals. external pins, such as the four low-battery interrupts (bl4 ?l1 ), the ac power detect (acin), the external smi (extsmi), and the sus /res pin, can also cause smis or mode changes to occur. certain power-management functions are disabled when the acin input is detected because it is assumed that the system is no longer using a battery. this chapter contains sample microprocessor programs for setting up power- management functions for the ?lansc310 microcontroller. however, no attempt is made to cover all possible power-management situations, and the examples given are merely suggestions.
1-2 power management 1.1 power management unit the primary design goal of the power management unit (pmu) is to control the power of the entire system so as to eliminate or minimize the excess use of current, particularly when it is not needed at a speci? time. the pmu uses the following techniques to con- serve power: n slows down clocks when the system is not in active use n shuts off clocks to parts of the system that are idle n shuts off power to parts of the system that are idle n reduces power use when batteries are low an additional goal of a good pmu design is to make these functions as transparent to the user as possible and to avoid any possibility of disastrous side effects, such as accidental loss of data. the ?lansc310 microcontrollers pmu includes the following principal components: n pmu state machine defines certain levels of system activity and the allowable state transitions. depending on the current level of activity registered by the pmu state, the system may, for example, run clocks at a high speed, a low speed, or turn them off. the current and previous pmu states may be read; in addition, the pmu may be forced into a specific state by a software command. n external device-control interface allows the pmu to control external power switches to different devices. the on or off status of most of these devices may be specifically programmed for each of the available power-management states. in addi- tion, dedicated logic enables the power to three specific devices to be automatically turned off after a specified time-out period during which no activity has occurred. if one of these devices is accessed after power has been turned off, an smi is automatically generated so that the i/o instruction can be retried after powering up the device. n clock-switching logic synchronously switches different clock sources to the cpu clock, or switches off the cpu clock and phase-locked loops (plls). n activity monitors check for certain external or cpu events that indicate system activity. on receipt of an event, this logic causes the pmu state machine to switch to high-speed pll mode. by definition, activities function only while the cpuclk signal is running. n state-transition timer defines the allowable periods of inactivity before pmu state changes occur. n wake-up logic allows certain events to start the clocks and restart the on-board plls. wake-ups are independent of whether the cpuclk signal is on or off. wake- ups force the pmu into high-speed pll mode. n nmi and smi control allows certain external, internally generated, or cpu events to generate a nonmaskable interrupt (nmi) or smi to the cpu. if the cpu clock is not running when a triggering event occurs, this logic can cause the pmu to start the cpu clock to process the interrupt. n battery-management logic includes four levels of battery-power handling. certain levels can be programmed to generate smis or nmis, slow the cpu clock, or force the system into sleep or suspend mode. n suspend and resume pin logic provides a user-operable method of forcing the pmu to enter sleep mode or to wake up from sleep, suspend, or off mode.
power management 1-3 n auto low-speed logic provides an option of slowing the cpu clock according to a programmable duty cycle while the system is in high-speed pll mode, providing additional power savings. n other power-saving features include additional power-saving functions which may be utilized at the system designer?s discretion. each of these pmu components is discussed in greater detail later in this chapter. 1.1.1 power-management modes the ?lansc310 microcontrollers power-management unit (pmu) provides the following power-management states or modes : n high-speed pll n low-speed pll n doze n sleep n suspend n off each mode is de?ed by a different combination of cpu and peripheral operation. a given system may utilize all six states for the maximum granularity of pmu modes, or it may merge some of the states into as few as three effective pmu modes. for a given pmu state, the controller can: specify different clock rates to various devices, turn off clocks, control external devices by way of programmable pins, and allow or disal- low certain events to cause the unit to enter a subsequent pmu mode. a state diagram for the pmu state machine is shown in figure 1-1 on page 1-4. in addi- tion, through the software mode control register at index 88h, the pmu can be forced into any mode except the off mode by a software command.
1-4 power management 1.1.1.1 high-speed pll mode in high-speed pll mode, all system clocks run at their highest speeds. for the cpu, the high-speed pll rate (supplied by the clk2 signal) is software con?urable to 40, 50, or 66 mhz, yielding internal cpu operation speeds (cpuclk) of 20, 25, or 33 mhz, respec- tively. the low-speed pll rate (also supplied by the clk2 signal) is ?ed at 18.432 mhz, yielding an internal cpu operation speed (cpuclk) of 9.2 mhz. the high-speed pll rate only applies to certain types of cpu cycles. normally, the cpu is clocked at the low-speed pll rate, even in high-speed pll mode. for cpu dram, local-bus, fast-rom, and idle cycles, the clock is dynamically switched to run at the high- speed pll rate. any activity (or wake-up) de?ed by the software will cause the pmu to select high- speed pll mode. in this mode, power conservation takes a back seat to cpu processing power. figure 1-1 pmu operating-mode transitions notes: 1. this picture simpli?s the function of the sus /res pin. for more details, see ?uspend/resume pin logic on page 1-34. 2. acin low and either bl2 or bl4 low have the same effect as the sus /res pin. sus /res pin wake-up or sus /res pin wake-up or sus /res pin sus /res pin high-speed pll mode inactivity 3 resin = 0 activity or wake-up inactivity 4 inactivity 5 inactivity 1 inactivity 2 sus /res pin activity wake-up or sus /res pin doze mode low-speed pll mode sleep mode off mode suspend mode
power management 1-5 power-management control (pmc) pins can be used to control power to peripheral devices on a per-mode basis. software can restore power to any peripherals whose power (controlled by its associated pmc pin state) was removed by a previous transition to a lower-power mode. 1.1.1.2 low-speed pll mode low-speed pll mode is the ?st level of power conservation. it is entered after a speci- ?d elapsed time with no activity, programmed using the high-speed to low-speed mode timer register at index 83h. in this pmu mode, the cpu, dma, and other internal system clocks run at reduced rates. the low-speed pll clock, whose rate is always ?ed at 18.432 mhz, is sent through a programmable divider. the minimum divisor is 2. this yields a maximum programmable clk2 rate of 9.216 mhz, which results in a maximum internal operation speed (cpuclk) of 4.608 mhz. pll divisors of 2, 4, 8, and 16 can be selected for dividing the low-speed pll clock in low-speed pll mode. no dynamic switching of clk2 to the high-speed pll rate is done in this mode. all other clocks and peripherals run at full speed. power-management software may optionally shut off the high-speed pll. depending on the frequency of this pll, up to 750 m a may be saved by this action. if this is done, a pll start-up delay of 256 ms (programmed in the clock control register at index 8fh) must elapse before high-speed pll mode can be re-entered. pmc pins may be used to control power to peripheral devices on a per-mode basis. soft- ware may restore power to any peripherals whose power (controlled by their associated pmc pin states) was removed by a previous transition to a lower power mode. 1.1.1.3 doze mode doze mode is the second level of power conservation. the cpu, system, and dma clocks, and the high-speed pll are stopped. this mode is entered after a programmed time without activity has elapsed. for details, see ?ow-speed to doze timer register (index 84h) on page 4-44. by default, the cpu clock is stopped in doze mode, along with the dma clock and inter- nal system clock (see table 1-1 on page 1-6). the video, uart, and 8254 timer clocks are driven by the low-speed pll, which is enabled by default. by allowing these clocks to run, it is possible for timer and keyboard interrupts to be generated.
1-6 power management through an option enabled by setting bit 3 of the mmsb control register at index 74h, the pmu can be programmed to periodically start the low-speed cpu clock when the irq0 pin (generated by the 8254 timer) is asserted. by default, the clock runs only while irq0 is active or the isr0 bit is high, stopping on the next refresh after this condition is no longer valid. in this case, the cpu clock runs at 9.2 mhz. the 8259 interrupt controller must be programmed to unmask irq0. by setting bit 0 of the pmu control 2 register at index afh, the run time may be extended for 64 refresh cycles after isr0 goes low. by setting bit 7 of the power control 1 register at index 80h, the low-speed pll and video pll can be shut down in doze mode. shutting down the low-speed pll also shuts down the 8254 timer clock, the uart clock, and the keyboard clock; therefore, the irq0 wake- up cannot be used in this instance. the high-speed pll is always shut down in this mode. the pmc pins may be programmed to a specitc state for this mode. an nmi or smi may be generated upon entering doze mode. the cpuclk signal runs at 9.2 mhz during the nmi or smi handler. table 1-1 pmu clock speeds mode high-speed cpuclk low-speed cpuclk video clock dma clock sysclk 8254 clock (timer) 16450 clock (uart) high-speed pll 33/25/20 mhz 9.2 mhz 14.336 mhz 4.6 mhz 9.2 mhz 1.19 mhz 1.8432 mhz low-speed pll 9.2 mhz 4.608/2.304/ 1.152/0.56 mhz 14.336 mhz 2.3/1.2/0.58/ 0.29 mhz 9.2 mhz 1.19 mhz 1.8432 mhz doze dc 1 dc 1 14.3 mhz/ dc 2 dc 1 9.2 mhz/ dc 2 1.19 mhz/ dc 2 1.8 mhz/dc 2 sleep dc 9.2 mhz/ dc 4 14.3 mhz/ dc 2 4.6 mhz/ dc 4 dc 1.19 mhz/ dc 2 1.8 mhz/dc 2 suspend dc 9.2 mhz/ dc 4 14.3 mhz/ dc 2 4.6 mhz/ dc 4 dc 1.19 mhz/ dc 2 1.8 mhz/dc 2 off dc 9.2 mhz/ dc 4 14.3 mhz/ dc 3 4.6 mhz/ dc 4 dc 1.19 mhz/ dc 3 1.8 mhz/dc 3 notes: the dma clock can be stopped except during dma transfers. the function enable 1 register at index b0h controls this function. the cpu clock speed in low-speed pll mode is selectable. for additional information, see ?mu control 3 register (index adh) on page 4-60. 1. can be programmed to run intermittently (on the irq0 pin) at 9.2 mhz. 2. is a programmable option, but not on a per-clock basis?ll clocks with this note are controlled by a single on/off select for that pmu mode. 3. is a programmable option?e?cts the setting in suspend mode. 4. can be programmed to run at 9.2 mhz during temporary-on nmi or smi handlers.
power management 1-7 1.1.1.4 sleep mode sleep mode is the third level of power conservation. in addition to the clocks disabled in doze mode, the keyboard clock (external sysclk signal) is disabled, regardless of whether the low-speed pll is enabled. sleep mode is entered after a programmable time without activity has elapsed. for details, see ?oze to sleep timer register (index 85h) on page 4-44. in this mode, the cpu, system, and dma clocks are stopped and cannot be restarted unless one of the following events occurs: n an smi or nmi on bl1 or bl3 (when enabled) n an smi or nmi generated on a change to suspend mode n a wake-up event causes an exit from sleep mode to high-speed pll mode in the ?st two cases, the clock runs only during the smi or nmi routine and then stops again. the keyboard clock is also shut down and can only be restarted by waking up to high-speed pll mode. the high-speed pll is always shut down in sleep mode. by setting bit 3 of the power control 2 register at index 81h, the low-speed pll and video pll also may be shut down in this mode. in this case, the low-speed and video pll is restarted before responding to an smi or nmi or changing to high-speed pll mode. when changing to high-speed pll mode, the high-speed pll is also restarted. note that the low-speed pll is divided to generate the 8254 timer clock. the pmc pins may be programmed to a speci? state for sleep mode. an nmi or smi may be generated upon entering sleep mode, in which case the handler runs at 9.2 mhz. 1.1.1.5 suspend mode with regard to the clocks and plls, suspend mode has the same functionality as sleep mode. but bit 7 of the power control 2 register at index 81h enables shutdown of the video and low-speed plls in suspend mode. the distinction between suspend and sleep mode is in the way the external power-management control (pmc) pins behave and may be programmed to behave. the pmc pins may be programmed to a speci? state for this mode. an nmi or smi may be generated upon entering suspend mode, in which case the handler runs at 9.2 mhz. 1.1.1.6 off mode off is a powered-down mode in which the programmable general-purpose 2 and 3 (pgp2 and pgp3) pins are set to a prede?ed state, and memory refresh may be dis- abled. the state of the pgp pins is determined by the general-purpose i/o 2 and 3 regis- ters at indexes 94h and 95h, and the general-purpose i/o control register at index 91h. the system cannot be programmed to enter off mode directly. the only method of off mode entry is by expiration of the suspend to off mode timer register at index 87h. when this happens, the pmu state machine is left in suspend mode, and an internal, nonreadable ?p-?p is set, indicating off mode. an nmi or smi may be generated upon entering off mode. refresh may be programmed to be disabled when the pmu is in off mode. setting bit 7 of the memory con?uration 2 register at index b9h causes the ras and cas outputs to be driven low when the pmu is in off mode. the system logic should power off the dram in this mode, or the low ras and cas outputs may keep the row buffers enabled,
1-8 power management thus drawing additional power from the dram devices. dram content is invalid when exiting from off mode when the disable-refresh feature is being used. 1.1.2 pmu operating-mode transitions figure 1-1 on page 1-4 shows the ?lansc310 microcontrollers six operating modes and the transitions that can occur between them. in this diagram, the term inactivity , followed by a number from 1 to 5, refers to different timer intervals of inactivity, which are set by programming the mode timer registers at indexes 83?7h. the term activity refers to the programmer-speci?d computing activities set in the following registers: n activity mask 1 and 2 registers at indexes 75?6h n i/o activity address 0 and 1 registers at indexes 8c?dh n memory write activity lower and upper boundary registers at indexes 9a?bh n pmu control 1? registers at indexes a7h, afh, and adh for more information, see the programming examples later in this chapter. the sus /res pin is an external pin that can be triggered to cause a transition between modes. each power-management mode is characterized by a different clock-frequency pattern the cpu, system bus, and many peripheral devices have their own clocks. several clock- switching permutations are possible through the use of the pmu modes. the plls act as sources for other clocks as follows: n high-speed pll generates the high-speed cpu/memory clock only. it can be pro- grammed to run at either 40, 50, or 66 mhz, yielding an internal cpu operating fre- quency of 20, 25, or 33 mhz, respectively. the pmu state machine has controls that can disable this clock to prevent it from being used or, in addition, turn off the pll. n low-speed pll is divided to generate the following clocks: low-speed cpu/internal system clock 8254 timer clock 8250 uart clock 9.2-mhz keyboard-controller clock/external sysclk the pmu state machine has controls that can disable some of these clocks to prevent them from being used or, in addition, turn off the pll entirely. n video pll generates the clock that for a 14.336 mhz signal that can, under pro- gram control, be driven on the ?lansc310 microcontroller? x1out or x14out pins. this signal can be used as a clock for an lcd display. the disable for this clock is shared with the low-speed pll. if the low-speed pll is turned off, the video pll is also turned off. as shown in table 1-1 on page 1-6, in high-speed pll mode, the cpuclk signal can be programmed to run at 33 mhz, 25 mhz, 20 mhz, or 9.2 mhz during dram, local-bus, fast-rom, and idle cycles. in all other cases, the cpuclk signal runs at 9.2 mhz. in low-speed pll mode, the cpuclk signal can be programmed to run at 4.6 mhz, 2.27 mhz, 1.13 mhz, or 0.568 mhz. the cpuclk signal cannot run at 9.2 mhz in low- speed pll mode, and it always runs at the same speed regardless of the type of cycle.
power management 1-9 1.1.3 pmu clock sources the ?lansc310 microcontrollers pmu uses the 32-khz clock to derive its internal timing. this clock runs off the ?lansc310 microcontrollers internal oscillator, which cannot be disabled. many events are synchronized with the internal refresh signal, which by default is derived from the 32-khz clock. if the ?lansc310 microcontrollers pmu is being used in a system design, the refresh clock must not be set to timer channel 1 because the timer is disabled in some pmu modes. the remainder of this section describes the functionality of the system during each of the pmu states. later sections discuss the different ways the pmu can be caused to enter these states. 1.1.4 reading the pmu mode the current pmu mode can be read from the cpu status 1 register at index a4h. if the pmu is in the off mode, this register indicates suspend mode. pmu mode changes always take effect on the next refresh after the mode change was registered. the mode that is read from the cpu status 1 register at index a4h is one refresh delay in advance of the internal signals that actually execute the functions of the pmu mode. therefore, if it is necessary to know the exact mode of the pmu at a speci? time (e.g., for the purpose of determining the state of the pmc signals), the software must read the cpu status 1 register on two successive refreshes and verify that the mode has not changed. 1.1.5 merging of pmu modes although six pmu modes are de?ed, the system designer may reduce the effective number of pmu modes by de?ing identical functions for some of the modes. for exam- ple, assuming that full-isa or local-bus modes are being used, a three-mode system that effectively merges the doze, sleep, suspend, and off modes can be achieved. to merge the doze, sleep, suspend, and off modes, use the following procedure: 1. set bit 7 of the power control 1 register at index 80h and bits 3 and 7 of the power control 2 register at index 81h to disable the low-speed and video plls in doze, sleep, and suspend modes. 2. set all the pmc bits to the same value for doze, sleep, and suspend modes. 3. do not enable the pgp2 and pgp3 pins to change in off mode. the net effect of this procedure is to create a three-mode system, effectively consisting of high-speed pll, low-speed pll, and suspend modes, where doze, sleep, suspend, and off modes have been merged into a single new pseudo-suspend mode. 1.1.6 programming example: power-management setup neglecting peripheral control for the moment, the ?st step in setting up power-manage- ment for a system is to de?e what constitutes activity . the following events constitute activity: n dma requests and interrupt requests (drq, irq) n keyboard, lpt, com, and programmable i/o port accesses n mms, video memory, and programmable memory range accesses n hard disk drive and floppy disk drive accesses n ac adapter active (rising edge of acin)
1-10 power management the second step is to detne the absence of activity as inactivity . the third step is to detne the time intervals of inactivity to be allowed before the system automatically shifts itself to lower levels of power consumption. for this example, the inactivity time intervals used are shown in table 1-2 on page 1-10. the settings in table 1-3 on page 1-11 implement these steps. in this case, activity is considered to include most conventional interrupts and peripheral accesses. however, accesses to special i/o port ranges or memory ranges are not considered activity. the inactivity timings shown are fairly conventional for notebook and palmtop computers. table 1-2 inactivity states and transition intervals state from this mode to this mode interval inactivity 1 high-speed pll low-speed pll 1?6 s inactivity 2 low-speed pll doze 10 s inactivity 3 doze sleep 10 min inactivity 4 sleep suspend 10 s inactivity 5 suspend off 1 hr
power management 1-11 1.1.7 programming example: peripheral-device power the simplest way to control peripheral devices is to integrate their control into the above mode-based system. the ?lansc310 microcontroller allows ?e external power-manage- ment control (pmc) pins to be activated in such a way that they can indicate to external devices the mode of the system. simple logic can be used to disable the peripheral when the system is in speci? modes. table 1-3 power-management setup instruction ports index and data comment iow iow 022h 023h 75h 0100 0000 activity: dma requests, irq15?rq2 (except irq8 and irq4?rq3), keyboard, and mms inactivity: ac adapter iow iow 022h 023h 76h 1011 0000 activity: hard disk drive, ?ppy disk drive, lpt, com i/o, and video memory accesses inactivity: programmable i/o ports and memory ranges iow iow 022h 023h 08h 1110 0011 activity: irq8 and irq4?rq3 (these wake up the system from sleep, suspend, and off modes) iow iow 022h 023h afh 1100 0000 set the granularity of the low-speed to doze timer register to 1? s and the high-speed to low-speed timer register to 1?6 s, respectively. iow iow 022h 023h 83h 0000 0001 set the high-speed to low-speed timer register to 1?6 s (high-speed to low-speed mode transition). iow iow 022h 023h 84h 0010 1000 set the low-speed to doze timer register to 10 s (low-speed to doze mode transition). iow iow 022h 023h 85h 1001 0110 set the doze to sleep timer register to 10 min (doze to sleep mode transition). iow iow 022h 023h 86h 1010 0000 set the sleep to suspend timer register to 10 s (sleep to suspend mode transition). iow iow 022h 023h 87h 0011 1000 set the suspend to off timer register to 59 min, 44 s [1 hr] (suspend to off mode transition). note: for this and subsequent examples, the index registers cannot be programmed directly, but must be accessed by writing the location of the index register to address 22h and the data for the index register to address 23h. for example, the ?st i/o access in the above example can either be implemented using 8-bit accesses: mov al,75h out 22h,al mov al,40h out 23h,al or 16-bit accesses: mov ax,4075 out 22h,ax
1-12 power management as a concrete example, consider the previous example, which has several peripheral devices (?oppy disk drive, serial port, etc.). suppose the following peripheral-power-man- agement scheme is to be implemented: n 10 s of inactivity?turn off the floppy disk drive n 10 min of inactivity?turn off the serial port transceiver this scheme can be implemented by using doze mode to signal the ?oppy disk drive, and sleep or suspend mode to signal the transceiver. the pmc pins can be programmed to provide this control through the power control 1e4 registers at indexes 80e81h and abeach. the settings shown in table 1-4 on page 1-12 provide the following scheme: n pmc1 is activated when the system is in high-speed pll or low-speed pll mode n pmc2 is activated when the system is in doze mode n pmc3 is activated when the system is in sleep mode n pmc4 is activated when the system is in suspend mode the designer can use the pmc4epmc2 pins to disable the ?oppy disk drive and the transceiver. a more elaborate system permits the control of each peripheral on an individual basis. the settings shown in table 1-5 on page 1-12 extend the pmc initialization example to show how to power down an external device after 8 s. the following example shows how the ?lansc310 microcontroller can be programmed to make the pmc1 pin change state after 8 s of system inactivity. the designer can use this signal to turn off power to the external device. table 1-4 power-management control pin settings instruction ports index and data comment iow iow 022h 023h ach 0001 0000 activate pmc1 when in high-speed pll or low-speed pll mode. iow iow 022h 023h 80h 0100 0000 activate pmc2 when in doze mode. iow iow 022h 023h abh 1000 1011 activate pmc3 when in sleep mode and activate pmc4 when in suspend mode. table 1-5 pio timeout settings instruction ports index and data comment iow iow 022h 023h 45h 1100 000 set pio address to the window at port 300h. iow iow 022h 023h 46h 0100 0110 set the i/o window size to 8 bytes and the timeout to 8 s.
power management 1-13 if the time-out period expires, the pmc1 pin is pulled low, which causes the external device?s power to be turned off. if the program then attempts to access the external device via i/o addresses in the range 300e307h, then an smi is generated. this proce- dure allows the program to turn on external device power before reissuing the access. the settings shown in table 1-6 on page 1-13 enable smi generation for pio accesses to that address range. an smi causes the cpu to store its internal state at location 060000h, which in this example is mapped by the memory mapping system to 200000h. the cpu begins exe- cuting at the reset vector, and the code executes the smi handler after it checks the smi ?ag. by checking the smi status register at index 43h, the smi handler determines that a pio access caused the smi. then the handler can turn on the external device?s power by set- ting bit 4 of the power control 4 register at index ach, which causes the pmc1 pin to be reset, thus restoring power to the device. table 1-6 smi-generation settings for pio accesses instruction ports index and data comment iow iow 022h 023h a9h 1100 xxxx set the smi memory-mapping system (mms) (bits 23?2) to 00; enable smi mms. iow iow 022h 023h aah 1000 0000 set the smi mms to 200000h. iow iow 022h 023h 43h 0000 0000 reset the smi status register. iow iow 022h 023h 41h 0000 0100 enable smi for pio accesses. note: in this and subsequent examples, the notation xxxx refers to a ?ld of bits whose value must be preserved. that is, the programmer must execute an i/o-read?odify?/o-write cycle to ensure that the current contents of this ?ld are not changed.
1-14 power management 1.2 external-device control interface the external-device control interface includes the following pins: n power-management control (pmc4?mc0) n programmable general-purpose (pgp3?gp2) n latched power (lph ) 1.2.1 power-management control pins the power-management control (pmc4?mc0) pins may be used for either or both of the following purposes: n general-purpose control of external devices in conjunction with the pmu state machine n timer-controlled shutdown of a floppy disk drive (addresses 3f0?f7h), hard disk drive (addresses 1f0?f7h), or user-specified i/o device in conjunction with the ?lansc310 microcontroller? smi interface. 1.2.1.1 general-purpose control using the pmu state machine when using the pmc pins for general-purpose control, pmc4 and pmc2?mc0 are non- inverting and drive a 0 at reset. pmc3 is inverting and will drive a 1 at reset. each pin may be programmed to drive a unique state in high-speed pll, low-speed pll, doze, sleep, and suspend modes. pin state switching occurs on the next refresh cycle after a pmu state change. the signals are not synchronous and may glitch when changing to high-speed pll mode. internal gray encoding prevents glitching when the pmu states are cycling down sequentially from high-speed pll mode. table 1-7 on page 1-14 sum- marizes the functionality of these pins. 1.2.1.2 timer-controlled shutdown using the smi interface when using pmc4 or pmc1?mc0 for timer-controlled shutdown of devices, the smi timer logic must be enabled through the smi enable register at index 41h. in addition, the bits in the general-purpose i/o 0? and 4 registers that correspond to the modes in which the devices normally run should be programmed to 1. a pmc output pin goes high to enable a device. the pin goes low to disable a device under any of the following condi- tions: n the smi device timer expires. n the pmu enters sleep, suspend, or off mode. table 1-7 pmc pin functionality pmc pin no. control register output sense smi timer function 0 index ach, bits 3? noninverting floppy disk drive (3f0?f7h) 1 index ach, bits 7? noninverting programmable i/o address 2 index 80h, bits 6 and 2 index 81h, bits 6 and 2 noninverting (none) 3 index abh, bits 3? inverting (none) 4 index abh, bits 7? noninverting hard disk drive (1f0?f7h)
power management 1-15 n the pmu enters another mode for which the device is programmed to turn off. it is also important to understand that an expiring smi device timer clears all four of the pmc control bits for that device by a short pulse generated when the timer expires. in addition, the control-register bits for that device are held in reset when the pmu is in sleep, suspend, or off mode. these conditions only apply to pmc pins that have an smi device timer enabled by the smi enable register at index 41h. for more information, see accesses to powered-down device smi on page 1-29. 1.2.2 programmable general-purpose pins 2 and 3 through an option enabled via the general-purpose i/o 2 and 3 registers at indexes 94?5h and the general-purpose i/o control register at index 91h, the pgp3?gp2 pins can be enabled to switch from high to low when the pmu enters off mode. this option can be enabled as follows: n pgp2 clear bits 4 and 5 of the general-purpose i/o control register at index 91h, and set bit 7 of the general-purpose i/o 2 register at index 94h. n pgp3 clear bits 6 and 7 of the general-purpose i/o control register, and set bit 7 of the general-purpose i/o 3 register at index 95h. this setup causes the pgp pins to default to 1. when the pmu enters off mode, the pgp2 or pgp3 pin is driven by the inverse of bit 7 of the general-purpose i/o 2 register or the general-purpose i/o 3 register, respectively. because the pmu timer delay to off mode can be set to as long as 256 min, this feature can be used to turn off a device after a prolonged period of inactivity. 1.2.3 latched power pin the latched power (lph ) pin can be used to indicate a low battery. the default state of lph is 0. when enabled by setting bit 7 of the mmsb control register at index 74h, a 0 on the battery level 4 (bl4 ) input pin causes lph to drive a 1, provided that the acin (ac input active) pin is also 0.
1-16 power management 1.3 clock-switching logic the ?lansc310 microcontrollers clock-switching logic handles the task of switching clock speeds as directed by the pmu or other input, and sequencing the shutdown and startup of the clocks and plls. 1.3.1 cpu/memory clock switching the cpu clock-switching circuit delivers a signal that switches cleanly between the high- speed pll clock and a low-speed clock source in high-speed pll mode. the low-speed clock source switches cleanly between the low-speed pll clock (9.2 mhz) and a select- able slow clock on a pmu state transition (see table 1-1 on page 1-6). the high-speed pll clock is used only under narrowly de?ed conditions. the high- speed clock must be enabled by setting bit 6 of the i/o wait state register at index 61h. doing this enables the use of the high-speed clock after the next refresh cycle if the high- speed pll is already started. in addition, the pmu must be in high-speed pll mode and the current bus cycle must be one of the following types of cycles: n cpu idle n local dram n fast rom n local bus use of the high-speed clock is disallowed when all of the following conditions are true: n bl1 is low n bit 5 of the pmu control 2 register at index afh has been set to enable this feature n acin is low if the auto low-speed logic is enabled, use of the high-speed clock is disallowed periodi- cally to conserve power. in cases where the use of the high-speed pll clock is disal- lowed, the low-speed plls 9.2-mhz cpu clock is used. when the pmu is in low-speed pll mode, the cpu clock is generated from the low- speed clock source. this is a programmable divider chain controlled by bits 1? of the pmu control 3 register at index adh which provides a clock frequency of 9.216 mhz that is divided by 2, 4, 8, or 16. these bits should be changed only when the pmu is not in low-speed pll mode. when a temporary-on condition occurs while the pmu is in doze, sleep, suspend, or off mode?nd the cpu/memory clock is enabled to run?he 9.2-mhz cpu clock is used. the high-speed pll clock frequency may be selected by writing to bits 4? of the func- tion enable 2 register at index b1h. these bits should not be changed when the high- speed clock is enabled. 1.3.2 clock startup and shutdown logic the clock startup and shutdown logic provides a mechanism for properly coordinating the activation of the ?lansc310 microcontrollers plls with the cpus clock-enabling logic. the ?wchart in figure 1-2 on page 1-18 illustrates the logic ?w. for the high-speed clock, there is a choice of turning off the pll in either low-speed pll mode or doze
power management 1-17 mode, selectable through bit 2 of the pmu control 3 register at index adh. for the low- speed clock, there are a number of options with regard to when the pll is turned off. these options are controlled using bits 7 and 3 of the power control 1 and 2 registers at indexes 80e81h. the pll startup time must be programmed in the clock control register at index 8fh to allow suftcient startup time for the pll before the clocks are engaged. it is recommended that the startup time be programmed to at least 256 ms when starting from a pmu mode where the low-speed pll is disabled. a startup time of 128 ms can be used if the low-speed pll will never be disabled. if the pmu is returning to high-speed pll mode from a mode where the high-speed pll was disabled but the low-speed pll was enabled, the cpu clock will begin operating at 9.2 mhz immediately. after the pll startup time expires, the cpu clock switches to the high-speed pll frequency if enabled to do so via bit 6 of the i/o wait state register at index 61h.
1-18 power management figure 1-2 pll control flowchart system reset (resin must be active for entire pll startup time) pll startup completed clock enabled (bit 2 of index adh) = 1? disable clock high-speed clock/pll 1 no no high-speed pll mode? ye s high-speed pll mode? disable clock disable pll high-speed pll or low-speed pll mode? 1 ye s no no ye s ye s pll disabled high-speed pll mode? enable pll index 8fh startup time completed? enable clock ye s ye s no no system reset (resin must be active for entire pll startup time) pll startup completed clock enabled clock-disable request? disable clock 2 ye s low-speed clock/pll clock-shutdown request? clock-enable request? ye s ye s no no pll disabled clock-enable request? no enable pll index 8fh startup time completed? enable clock ye s ye s no disable pll no 2
power management 1-19 1.4 activity monitors the activity-monitor logic keeps track of events that indicate that the cpu or peripherals are in demand. examples of such events are i/o or memory decodes to certain addresses, dma requests, interrupts, and changes in status signals. when an activity event is recognized, the pmu state machine immediately switches to high-speed pll mode on the next refresh cycle. the exception to this rule is that activities are not recog- nized during execution of smis or nmis. all pmu activities are edge detected. activities that are referred to in table 1-3 on page 1-11 can be classi?d as cpu-related and non-cpu-related. the cpu-related activities that the ?lansc310 microcontrollers pmu is able to count as events are selected via the activity mask 1 and 2 registers at indexes 75?6h, with status read from the activity status 1 and 2 registers at indexes a0?1h. the non-cpu-related activities that the pmu is able to count as events are selected using the resume mask register at index 08h, with status read from the resume status regis- ter at index 09h. non-cpu-related activities are also classi?d as wake-up events. note that it also is possible for some of the cpu-related activities to wake up the pmu. both types of wake-ups are discussed in ?ake-up logic on page 1-23. detected activities in the activity status 1 and 2 registers at indexes a0?1h and the resume status register at index 09h are indicated by a 1 in the appropriate bit. after reading one of these registers, software should write any value to clear the register. figure 1-3 on page 1-20 shows how activities play a part in the power-management ?w.
1-20 power management figure 1-3 state transition flowchart wake up cpu to execute (extended time optional) power on bios initialization perform smi or nmi (figure 1-4) doze mode: ?stop cpu clock ?pmc pins change state ?stop high-speed pll ?stop low-speed pll (optional) high-speed pll mode: ?pmc pins change state ?all plls enabled ?high-speed cpu clock low-speed pll mode: ?reduce cpu clock speed ?reduce system/dma clock speed ?stop high-speed pll (optional) 1 activities detected before high-speed to low-speed timer expired? ye s no activities detected before low-speed to doze timer expired? no mode-change smi or nmi enabled? no ye s ye s ye s irq0 enabled in doze mode? irq0 occurred? activities detected? doze to sleep transition timer expired? 2 no ye s no no ye s ye s no
power management 1-21 figure 1-3 state transition flowchart (continued) perform smi or nmi (figure 1-4) perform smi or nmi (figure 1-4) sleep mode: ?pmc pins change state ?stop low-speed and video plls (optional) suspend mode: ?pmc pins change state ?stop low-speed and video plls (optional) off mode: ?pmc pins in suspend state ?pgp pins 2 and 3 change state (optional) ?other controls same as suspend mode ?disable dram refresh (optional) 2 mode-change smi or nmi enabled? no ye s wake-up occurred? ye s 1 sleep to suspend timer expired? no no ye s mode-change smi or nmi enabled? wake-up occurred? suspend to off timer expired? mode-change smi or nmi enabled? wake-up occurred? perform smi or nmi (figure 1-4) no ye s no ye s no no ye s ye s no ye s
1-22 power management 1.5 state-transition timer the state-transition-timer logic allows the system designer to specify the amount of time that the pmu waits between state transitions when no activity is occurring. as shown in table 1-3 on page 1-11, the time values are programmed through the mode timer regis- ters at indexes 83?7h. the high-speed to low-speed timer register at index 83h is used in high-speed pll mode. by default, it is programmed in increments of 1?12 s, with a minimum time of 1?12 s when set to a value of 1 and a maximum time of 498 ms (1?12 ?255) when pro- grammed to ffh. if bit 6 of the pmu control 2 register at index afh is 1, the time incre- ments for this register change to 1?6 s, for a minimum time of 1?6 s and a maximum time of 15.94 s. when this time expires, the pmu changes to low-speed pll mode. the low-speed to doze timer register at index 84h is used in low-speed pll mode. by default, it is programmed in increments of 1?6 s, with a minimum time of 1?6 s when set to a value of 1 and a maximum time of 15.94 s when programmed to ffh. if bit 7 of the pmu control 2 register at index afh is 1, the time increments for this register change to 1? s, for a minimum time of 1? s and a maximum time of 63.75 s. when this time expires, the pmu changes to doze mode. the doze to sleep timer register at index 85h is used in doze mode. it is always pro- grammed in 4-s increments, with a minimum time of 4 s and a maximum time of 1020 s (4 ?255). when this time expires, the pmu changes to sleep mode. the sleep to suspend timer register at index 86h is used in sleep mode. it is always pro- grammed in 1?6-s increments, with a minimum time of 1?6 s and a maximum time of 15.94 s (1?6 ?255). when this time expires, the pmu changes to suspend mode. the suspend to off timer register at index 87h is used in suspend mode. it is always programmed in 64-s increments, with a minimum time of 64 s and a maximum time of 16320 s (64 ?255), equivalent to 4 hr and 32 min. when this time expires, the pmu changes to off mode. since off mode is the last state, there is no timer for it. the state transition timer, also known as the pmu timer, is an internal timer whose value cannot be read by the system. this timer counts up from 0 and is compared to the transition timer register associated with the current pmu mode. when the pmu timer exceeds the time programmed into the appropriate mode timer register, the mode change is initiated and the pmu timer is reset to 0. when one of the above registers is cleared, upon reaching the pmu mode corresponding to that register, the pmu timer will reset and stop counting. the pmu will thus remain in that mode unless an activity is detected or the pmu is forced into another state via the sus /res pin, bl2 or bl4 pin, or a write to the software mode control register at index 88h. thus, for example, if the high-speed to low-speed timer register at index 83h is cleared, the pmu never leaves high-speed pll mode unless one of the pre- viously mentioned events occurs.
power management 1-23 the pmu timer is also reset by any of the following events: n an unmasked pmu activity event n a write to the software mode control register at index 88h n an smi or nmi caused by the battery-level pins, a pmu mode change, or a sus /res pin pulse (the timer is held in reset during one of the above smis until a write to the nmi/smi control register at index a5h occurs) n the high-speed or low-speed pll is started (the timer is held in reset until startup is completed) 1.6 wake-up logic the ?lansc310 microcontrollers wake-up logic provides a mechanism for allowing cer- tain external events to bring the pmu out of sleep, suspend, or off mode into high- speed pll mode. these events are de?ed in the resume mask register at index 08h. see table 1-8 on page 1-23 for a list of the wake-up signals and associated trigger mech- anisms. if the pmu is in low-speed pll or doze mode, these wake-up events function as activities, returning the pmu to high-speed pll mode. the events that may be allowed are ring-indicate signals from the internal uart, as well as irq3 or irq4 (from the internal uart or an external pin, depending on the system con?uration) and irq8 (from the internal rtc only). in addition to the events de?ed in the resume mask register, a rising edge on drq2 could be programmed as a wake-up event through bit 2 of the activity mask 1 register at index 75h. a rising edge on acin may be enabled as a wake-up activity (bit 6 of the activity mask 1 register and bit 4 of the pmu control 3 register at index adh). and a rising edge on irq1 (at keyboard interrupt) could also be enabled as a wake-up activity (bit 4 of the activity mask 1 register). if the table 1-8 wake-up signal descriptions signal trigger description drq1 rising edge active until drq1 goes low. not maskable at the dma controller. drq2 rising edge active until drq2 goes low. not maskable at the dma controller. drq3 rising edge active until drq3 goes low. not maskable at the dma controller. drq5 rising edge active until drq5 goes low. not maskable at the dma controller. drq6 rising edge active until drq6 goes low. not maskable at the dma controller. drq7 rising edge active until drq7 goes low. not maskable at the dma controller. irq1 rising edge active until the keyboard controller deasserts irq1. not maskable at the pic. irq3 rising edge active until irq3 goes low or channel 3 receives int/ack and eoi. maskable at the pic. irq4 rising edge active until irq4 goes low or channel 4 receives int/ack and eoi. maskable at the pic. irq8 rising edge active until irq8 goes low or channel 8 receives int/ack and eoi. maskable at the pic. ri falling edge active only until the next refresh. clearing bit 5 of the resume status register at index 09h prior to the next refresh may not clear the ri activity status.
1-24 power management system is contgured in maximum isa mode, it is also possible to use drq1 or drq7edrq3 as rising-edge wake-up events (bits 0, 2, and 3 of the activity mask 1 regis- ter). if the system is contgured in local-bus mode, the choice of drqs is limited to drq1, drq2, or drq5. when using irq or drq pins as wake-up signals, external hardware must hold the active state (high) until the pmu returns to high-speed pll mode. (this is not necessary for the ring-indicate wake-up signals because they are internally latched.) irq wake-up events (irq3, irq4, and irq8) are masked at the pic and must be enabled in order to generate a wake-up. however, unlike the irqs, the drq events are not masked at the dma controller. also, for irq wake-ups, care must be taken to ensure signal integrity on the irq lines. glitches on the irq lines as small as 4 ns will cause a wake-up to occur. the pmu has no ability to tlter glitches; therefore, the system could be returned to high- speed pll mode by what amounts to a spurious interrupt. if using multiple drqs and/or irqs as wake-up signals, the system designer must ensure that one wake-up signal does not block the others by being held continuously in the active state while its corresponding pmu-activity-mask bit is set to 0. these wake-up sources are logically ored before edge detection is performed. wake-ups received dur- ing temporary-on smi or nmi routines (see temporary-on mode on page 1-26) require the following special attention: 1. the wake-up is delayed (not serviced by the pmu logic) until the smi or nmi routine is completed. 2. the wake-up is serviced and cleared before exiting the smi or nmi handler when all of the following conditions are true: ? cpu interrupts are enabled by the routine (to handle other non-wake-up events) ? there is an associated interrupt service routine (isr) for the wake-up event ? the wake-up is not masked at the pic note that the interrupt handler does not have to explicitly clear the wake-up source. the cpu just has to acknowledge the active irq channel. this results in a lost wake-up event from the trst case. therefore, if cpu interrupts need to be serviced from within an smi/nmi handler, the irqs that are set up as wake-ups must be masked off at the pic (disabled) at the beginning of the smi/nmi routine, and unmasked (re-enabled) upon exit- ing the routine. make sure cpu interrupts are disabled before re-enabling wake-ups at the pic. the ring-in wake-up (ri ) persists only until the next refresh. if software tries to clear the status bits in the resume status register prior to that subsequent refresh, the bits may remain set. software must clear the resume status register on two successive refreshes. an additional wake-up event is the sus /res pin. this event is not maskable by the sys- tem. for more information, see suspend/resume pin logic on page 1-34. figure 1-3 on page 1-20 shows how wake-ups play a part in the power-management ?ow.
power management 1-25 1.7 smi and nmi control the use of smis gives the designer the ability to customize and extend the features of a systems power management. this is due to the transparency of smis relative to operat- ing systems and application software. the ?lansc310 microcontroller may be pro- grammed to generate smis from the following sources: n pmu mode changes (e.g., on a change from sleep mode to suspend mode) n battery-level changes (bl1 , bl2 , and bl3 ) n sus /res pin activation (only on wake-up) n attempted i/o accesses to devices that the pmu has powered down after a specified time-out period n interrupts from irq0 (timer channel 0 must be programmed and irq0 must be enabled at the 8259 pic) n system-management interrupts on the extsmi pin n i/o accesses to the rtc or the external 8042 keyboard controller of the above smi sources, the ?st three may be programmed to generate an nmi instead of an smi. refer to figure 1-4 on page 1-26 for the general ?w of an smi or nmi.
1-26 power management 1.7.1 temporary-on mode only the ?st three smi or nmi sources listed above will cause the cpu, dma, and inter- nal system clocks to start if they were stopped. if not in the high-speed pll or low- speed pll mode, the clocks will run based on the 9.2-mhz frequency until the next refresh after an i/o write to the nmi/smi control register at index a5h is performed. this is called temporary-on mode. this mode is useful when it is desired to have the cpu perform certain tasks before changing pmu modes, or when the cpu receives a low-battery indication or a resume keystroke, regardless of whether it is asleep or awake. for the ?st two sources, when in temporary-on mode, the pmu remains in the same state it was in before the cpu clock started. it does not change to high-speed pll mode. for the third source, the pmu makes a transition to high-speed pll mode before the smi is generated. writing to the nmi/smi control register causes the pmu to leave temporary-on mode and return to figure 1-4 smi processing flowchart exit smi or nmi handler mode-change smi or nmi from figure 1-3 smi or nmi enabled for requesting device/event? miscellaneous smi or nmi sources battery low (bl1 ,bl2 , or bl3 ) i/o cycle attempted to power off peripheral timer interrupt (irq0) generate smi/nmi (pmu starts cpuclk if source was mode change, bl1 , bl3 , or resume keystroke) smi or nmi routine flow: 1. determine source of smi or nmi (read registers a5h, 43h, and b3h). 2. clear smi or nmi request (write index a2h, 43h, b3h, or address of external device). 3. perform tasks. smi or nmi routine flow: read a5h again. any additional bits set? smi or nmi routine flow: was smi or nmi source the resume key, bl3 ?l1 , or mode change? ye s smi or nmi routine flow: write to register a5h to enable mode change no no ye s
power management 1-27 normal operation for the mode it was previously in, except that for a mode-change smi, the pmu will advance to the next pmu mode after leaving temporary-on mode. note that if the pmu was in high-speed pll mode when receiving a battery-level-change smi or nmi, it does not slow down the clock, but continues running at high-speed pll mode clock rates. while the pmu is in temporary-on mode, all activities, wake-up events, and pmu mode transition timers are disabled. however, activities and wake-up events are internally latched and cause the appropriate action to be taken when exiting temporary- on mode. when the system smi handler determines that an smi has been generated from the trst three sources, the write to the nmi/smi control register at index a5h should always be performed at the end of the smi handler. the nmi/smi control register should be read just prior to writing to it. if any additional smi ?ags are set, they should be processed prior to writing the nmi/smi control register. in some cases, it may be important to ensure that the cpu clocks are stopped prior to exiting the smi/nmi routine. this prevents the main code from accessing a device that was just powered down in the routine. this can be accomplished by polling the port b register for a refresh after the write to the nmi/smi control register. the clocks are stopped when the refresh occurs. when the clocks start again, the smi/nmi routine tn- ishes executing. 1.7.2 enabling smis to enable smi generation, bit 7 of the mmsb socket register at index a9h must be 1. if bit 7 is 0, the ?st three smi and nmi sources generate nmis instead of smis. when enabling smis, the smi mms page register at index aah and bits 4 and 5 of the mmsb socket register must be programmed to set the mms page where smi cpu core data will be preserved. bit 0 of the miscellaneous 2 register at index 6bh gives the programmer the option of forcing address bit 20 low during smi routines. table 1-9 on page 1-27 shows the registers that enable the various smi sources. table 1-9 registers that enable smi sources register name index smi enable 41h nmi/smi control a5h function enable 1 b0h pmu control 3 adh nmi/smi enable 82h
1-28 power management 1.7.3 processing nmi or smi source on reset, ?mware must check bit 7 of the version register at index 64h to determine if the reset was caused by an smi. upon receiving an smi and entering the smi handler, the cpu must then poll the various smi status registers to determine the source of the smi. the status registers are as follows: n miscellaneous 5 register at index b3h for the extsmi pin n smi status register at index 43h for the following sources: hard disk drive floppy disk drive programmable i/o 8042 accesses rtc accesses irq0 generation pmu status changes if pmu status changes (bit 5) cause the smi, the smi handler must read the nmi/smi control register at index a5h to determine the source of the pmu smi. if the smi or nmi is caused by either pmu status changes or irq0 generation, the pmu status 1 register at index a2h must be written in order to reset the smi generation logic. this write must occur after reading the smi status register at index 43h and the nmi/smi control register at index a5h. failure to follow this order may result in additional smis being generated with incorrect status. if the smi or nmi was caused by a pmu status change, a write to the nmi/smi control register must occur near the end of the routine. prior to performing this write, the nmi/smi control register should be read again to determine if additional pmu status changes need to be processed. if additional pmu status changes need to be processed, the write to the nmi/smi control register should be delayed, the pmu status 1 register should again be written, and any code speci? to the new status change should be exe- cuted. a condition exists where the smi or nmi state-transition status (as re?cted in the nmi/smi control register at index a5h) can be different than the pmus current state. if a state-transition smi or nmi is received (and subsequently queued by the pmu logic) while the system is executing another state-transition smi or nmi routine, and the system is forced to another state via the software mode control register at index 88h, before exit- ing the routine but after clearing the nmi/smi control register (to allow the state transi- tion), then an incoherency causing the difference can occur. the source of the incoherency lies in the fact that as soon as the current smi or nmi completes, the cpu begins processing the queued-up state-transition smi or nmi. upon entry to the handler, if the code reads the nmi/smi control register to determine the source of the smi/nmi, the pmu reports a state transition based on the mode change before the write to the software mode control register, while a read of the current state as shown in the cpu status 1 register at index a4h reports the mode that occurred after the write to the software mode control register.
power management 1-29 to prevent this incoherency from occurring, forced state transitions caused by writes to the software mode control register should not be performed after a write to the nmi/smi control register from within a temporary-on smi or nmi routine. 1.7.4 accesses to powered-down device smi the ?lansc310 microcontrollers automatic device-power-down logic consists of a set of three timers, each dedicated to a speci? device at a hardwired (?ppy disk drive and hard disk drive) or programmed (pio) address, and associated with a speci? pmc pin (see table 1-7 on page 1-14). the ?wchart in figure 1-5 on page 1-30 illustrates the operation of this logic. each timer may be programmed to one of 16 possible time-out val- ues. see ?io timer register (index 46h) on page 4-16 and ?rive timer register (index 47h) on page 4-17. each timer is cleared when an activity is detected on the assigned address. the addresses for ?ppy disk drives and hard disk drives are hard- wired to the at standard locations. the pio address register at index 45h is used to set the pio base address. bits 6 and 7 of the pio timer register at index 46h set the number of bytes decoded. optionally, bit 0 (irqen) of the miscellaneous 4 register at index 44h may be set to enable a hard disk drive interrupt (irq14) and a ?ppy-disk-drive interrupt (irq6) to also be considered activities by their respective timers. however, these irqs will not generate smis.
1-30 power management smis from the timer-controlled devices are enabled by bits 2e0 of the smi enable register at index 41h. once a device is enabled, the trst i/o access to that device after enabling smis generates an smi. this initial smi can be differentiated from subsequent smis by virtue of the fact that the pmc power pins have not been cleared. after this trst smi is processed, the timer is enabled. any i/o access (or optional interrupts) to the device resets the timer. if no accesses occur before the timer expires, the smi generator is armed and the next i/o access generates an smi and resets the timer. expiration of the timer also causes the appropriate general-purpose i/o register to change to 0, which then causes the device to power down if the pmc pin is used to control device power. in this case, an smi indicates that an i/o access was attempted to a powered-down device. in the ?lansc310 microcontroller, cpu i/o trapping is enabled, so it is possible to retry the attempted i/o instruction after powering up the device by reinitializing the appropriate pmc register and performing whatever device initialization commands are required. the states of address bit 0, ior , io w , and bhe are latched in the smi i/o status register at index 42h at the end of the i/o command that caused the smi. note that this applies only figure 1-5 smi device-powerdown flowchart initialize smi logic timer-controlled smi enabled device i/o access? no ye s smi generated device timer is reset and begins counting device i/o access? ye s no timer expired? reset device timer pmc pin goes low, arming the smi generator device i/o access? no ye s ye s no
power management 1-31 to the smis enabled at the smi enable register at index 41h and the function enable 1 register at index b0h. optionally, trmware may enable the next i/o access to any of the timer-controlled devices to unconditionally cause an smi by writing a 0 to the appropriate bit in the i/o timeout register at index 40h. i/o trapping for powered-down devices is only applicable when the cpu is not servicing an smi. therefore, smi handlers should poll the i/o timeout register at index 40h before accessing i/o devices that may be powered down. if any of bits 2e0 are 0, and the corre- sponding bits in the smi enable register are 1, then i/o accesses to those devices will generate an smi. 1.7.5 treatment of pending smis if an smi is already in progress, the ?lansc310 microcontroller detects and holds as pending another incoming smi from a different device. when the current smi routine is ?ished executing, another smi is immediately asserted if other smis have been gener- ated and not cleared. the exceptions to this are smis that are generated from i/o decodes, which include the real-time clock (rtc), keyboard, ?ppy disk drive, hard disk drive, and pio. in these cases, another smi is not generated. however, the status bits in the smi status register at index 43h are 1. 1.7.6 external smi pin the external smi (extsmi) pin is enabled by bit 4 of the function enable 1 register at index b0h. this pin may be used by an external device to generate an smi. it may be used for a single device or multiple devices as explained below. pin polarity may be selected using bit 5 of this register. 1.7.7 external smi with a single device if the extsmi polarity bit (bit 5 of the function enable 1 register at index b0h) is 1, a fall- ing edge on extsmi causes an smi request to be generated. extsmi should then be held low by the external device until the smi handler releases it via an i/o write to the external device. the state of the extsmi pin may be read at bit 1 of the miscellaneous 5 register at index b3h to determine that extsmi has been activated. if the extsmi polar- ity bit is 0, then all of the above polarities are reversed. 1.7.8 external smi with multiple devices the external smi (extsmi) pin may be treated as an open-drain signal driven by multi- ple devices. as with a single device, each smi-generating device should continue assert- ing extsmi until acknowledged by the smi handler. after determining that the extsmi pin is asserted (bit 1 of the miscellaneous 5 register at index b3h), the smi handler must poll each external device and clear its smi-generating logic if needed. when all external devices are serviced, the extsmi pin should return to the inactive state. as long as the extsmi pin is active, smis to the cpu will be repeatedly generated.
1-32 power management 1.8 battery-management logic the ?lansc310 microcontrollers battery-management logic allows the system designer to specify up to four battery-detection levels. the four battery-level-indication input pins are named bl1 , bl2 , bl3 , and bl4 . a 0 on one of these inputs indicates a low-battery condition for that level. another pin named acin, when high, indicates that external non- battery power has been applied. the following paragraphs give a description of the func- tionality of each of these pins. table 1-10 on page 1-32 provides a summary of the functionality of bl4 ?l1 . 1.8.1 battery level 1 the battery level 1 (bl1 ) pin is intended to be used as a ?st-line warning, indicating that battery power is low, but that enough power remains for continued use. the state of this pin may be read directly at the cpu status 0 register at index a3h. through an option enabled by bit 5 of the pmu control 2 register at index afh, the cpu clock in high-speed pll mode can be forced to run at 9.2 mhz on all cycles when bl1 and acin are low, thus prolonging battery life. bl1 may also be programmed to generate smis. this feature is enabled by bit 5 of the nmi/smi enable register at index 82h. this is a level-triggered smi (i.e., the input should be held in the trigger state, not pulsed). after system reset, a level change on bl1 from 1 to 0 generates an smi. during the smi service routine, the cpu must read the nmi/smi control register at index a5h to reset the bl1 smi-generation logic. this read also sets the logic to look for the opposite state on bl1 to trigger the next smi. therefore, any change of state on bl1 generates an smi, provided that a read from the nmi/smi control register is always performed in the smi service routine. because the nmi/smi control register is also one of the smi source-polling registers, this read is needed anyway to determine the smi source. the smi handler must also write to the pmu status 1 register at index a2h to clear the pmu smi request. an smi generated by bl1 causes the cpu clock to be started, regardless of the pmu mode (see ?emporary-on mode on page 1-26). the clock remains running until the next refresh cycle following a write to the nmi/smi control register at index a5h. 1.8.2 battery level 2 the battery level 2 (bl2 ) pin is intended to be used as a second-line warning in a four- level battery-management system, or as a ?al warning in a two-level system. the state of this pin may be read directly at the cpu status 0 register at index a3h. table 1-10 battery-level management functionality pin slow clock level smi edge smi force to sleep force to suspend bl1 nn bl2 nn bl3 n bl4 n
power management 1-33 the pmu may be programmed to automatically enter sleep mode after a 0 is detected on bl2 while acin is also at 0. this feature is enabled by clearing bit 6 of the mmsb control register at index 74h, and is enabled by default. the pmu does not enter sleep mode instantaneously, but steps down a mode level on each refresh until sleep mode is reached. once the pmu is in sleep mode, the pmu state-transition timers control transi- tions to suspend and off modes. enabled wake-up/activity events will cause the pmu to change to high-speed pll mode. however, the pmu will step down a mode level on each refresh if the bl2 pin is low. pmu state transition to sleep mode can be temporarily interrupted by enabling low-to-doze or doze-to-sleep mode-change nmi/smi events in the nmi/smi enable register at index 82h. smis may be generated by bl2 . this feature is enabled by bit 6 of the nmi/smi enable register. there are important differences between the smi behavior of bl2 relative to bl1 and bl3 . smis are generated only on falling edges of bl2 . during the smi handler, the cpu must read the nmi/smi control register at index a5h to reset the bl2 smi genera- tion logic. the smi service routine must also write to the pmu status 1 register at index a2h to clear the pmu smi request. smis from bl2 are masked in sleep, suspend, and off modes and when pin bl4 is low. if an smi from bl2 occurs in doze mode and the cpu clock is stopped, the clock is started to execute the smi. the clock remains running until the next refresh cycle follow- ing a write to the nmi/smi control register. 1.8.3 battery level 3 the battery level 3 (bl3 ) pin is intended to be used as a third-line warning, indicating that battery power is low, but that enough power remains for limited use. the state of this pin may be read directly at the cpu status 0 register at index a3h. bl3 may also be programmed to generate smis. this feature is enabled by bit 7 of the nmi/smi enable register at index 82h. the functionality of this smi is analogous to that of the bl1 smi. an smi generated by bl3 causes the cpu clock to be started, regardless of the pmu mode (see ?emporary-on mode on page 1-26). the clock remains running until the next refresh cycle following a write of 0 to the nmi/smi control register at index a5h. 1.8.4 battery level 4 the battery level 4 (bl4 ) pin is intended to be used as an indication of the end of useful battery life. it cannot be programmed to generate an smi, and the state of bl4 cannot be read. the pmu may be programmed to automatically enter suspend mode after a 0 is detected on bl4 while acin is also 0. this feature is enabled by clearing bit 7 of the mmsb con- trol register at index 74h and is enabled by default. the pmu does not enter suspend mode instantaneously, but steps down a mode level on each refresh until suspend mode is reached. once the pmu is in suspend mode, the pmu state-transition timers control when (or if) there will be a transition to off mode. after the pmu has been forced into this condition, enabled wake-up/activity events will cause the pmu to transition to high-speed pll mode. however, the pmu steps down a mode level on each refresh if the bl4 pin is low. pmu state transition to suspend mode can be temporarily interrupted by enabling low-to-doze, doze-to-sleep, or sleep-to-suspend mode-change nmi/smi events in the nmi/smi enable register at index 82h.
1-34 power management even if the automatic suspend-mode feature is disabled, a 0 on bl4 always forces the pmu into suspend mode on the next refresh after entering sleep mode. however, system wake-up is allowed. 1.8.5 ac input status pin the ac input status (acin) pin is used to indicate that a permanent power source is driv- ing the system. when acin is high (indicating that external power is applied), the pmu state-transition timers are disabled for high-speed pll to low-speed pll, low-speed pll to doze, and doze-to-sleep mode transitions. this allows the system to remain in high-speed pll mode when ac power is available. sleep-to-suspend and suspend-to- off mode-transition timers are still enabled. this allows the pmu to change all the way to off mode after the pmu changes to sleep mode due to the sus /res pin logic. setting bit 5 of the miscellaneous 6 register at index 70h has the same effect as asserting the acin pin, with the exception that the force-to-sleep and force-to-suspend functions of bl2 and bl4 are disabled only by asserting the external acin pin. the acin pin can also be programmed to generate a pmu-activity event. doing this ensures that if external power is connected to a system with dead batteries, the pmu will automatically wake up. the activity is enabled by setting bit 4 of the pmu control 3 regis- ter at index adh and clearing bit 6 of the activity mask 1 register at index 75h. the pmu event is generated by detecting a rising edge on an internal signal that is the logical or of the external acin pin and the internal software sacin bit (in the miscellaneous 6 register at index 70h). 1.9 suspend/resume pin logic the suspend/resume (sus /res ) pin allows the system designer to provide an end-user mechanism for either waking up the system (i.e., forcing it into high-speed pll mode) or putting it into sleep mode. in a typical system design, this is realized by way of a special key on the system that is logically connected to this pin. the suspend/resume logic is triggered by a rising edge on the external sus /res pin. if the pmu is in high-speed pll, low-speed pll, or doze mode, such an event causes the pmu to immediately step down through the pmu states (one step per refresh cycle) until it reaches sleep mode, at which point control passes back to the pmu state machine. if the pmu is in sleep, suspend, or off mode, and it receives a rising edge on the same pin, it will jump directly to high-speed pll mode on the next refresh cycle. the information in this section should be used as a guide to understanding many of the controls and caveats of implementing an smi as it pertains to a suspend/resume opera- tion. the pseudocode that is provided only addresses handling of sus /res activity. therefore, it represents only a portion of a potentially more complex smi handler. code designed to manage a platform that utilizes smis to restart instructions after reinitializing powered-down devices, handling battery-low warnings, waking up as a result of an activ- ity other than the sus /res activity, and so forth requires additional event handling that is beyond the scope of this section. in addition, this section assumes that you understand the system management mode (smm) capabilities of the ?lansc310 microcontrollers cpu core. for more information on smm and smi functionality for the ?lansc310 microcontrollers cpu core, see the 3-volt system logic for personal computers manua l, pid 17028.
power management 1-35 this section deals with handling a suspend/resume operation using the smi capability of the ?lansc310 microcontroller. the pmu is designed to be able to perform a minimal suspend/resume operation without any software intervention. however, software may be required to handle platform-specitc code that takes care of peripheral-device state save, device power-down, or general cleanup prior to suspend. if this is done, software may be required to perform device-state restoration or other tasks upon resume so that the entire process is transparent to the application code. these tasks may be handled by either an nmi or an smi. this is a system-design deci- sion. the use of an smi to handle suspend/resume operations is shown here for demon- stration purposes. the ?lansc310 microcontroller?s pmu has the following capabilities that are critical to implementing a suspend/resume capability using smis: 1. the pmu, if it is in sleep, suspend, or off mode and upon detecting a rising edge on the sus /res pin, may generate a processor smi request (bit 0 of the nmi/smi enable register at index 82h). 2. the pmu, if it is in sleep, suspend, or off mode and upon detecting a rising edge on the sus /res pin, wakes up the processor into high-speed pll mode. 3. the pmu, if it is in high-speed pll, low-speed pll, or doze mode, and upon detect- ing a rising edge on the sus /res pin, steps down one pmu state per refresh until it reaches sleep mode. 4. the pmu may generate a processor smi request when the sleep-to-suspend mode timer expires (sleep to suspend timer register at index 86h and bit 3 of the nmi/smi enable register at index 82h). features 1 and 4 must be enabled individually to implement an smi-based sus- pend/resume capability (see the indicated contguration registers). features 2 and 3 are automatic and require no setup. note that there is no capability for the pmu to directly generate an smi request as a result of activity on the sus /res pin that would result in a transition to sleep mode. for the purpose of this documentation, assume that the sus- pend smi request is generated by utilizing feature 4. the ?lansc310 microcontroller?s sus /res pin serves both as a go-to-sleep (suspend) and a wake-up (resume) signal input. in either case, a rising edge on the sus /res pin is considered activity. this manual refers to such activity on the sus /res input when the pmu is in sleep, suspend, or off modes as a resume input . the same activity, if it occurs when the pmu is in high-speed pll, low-speed pll, or doze mode is referred to as a suspend input .
1-36 power management other issues that should be considered are as follows: n while processing a suspend input, an smi occurs as a result of the sleep-to-suspend transition (in this example). in order to process the smi, the pmu enters temporary- on mode. near the end of the smi handler, a write of any value should be made to the nmi/smi control register at index a5h. this causes the pmu to transition into sus- pend mode on the refresh following the write to the nmi/smi control register. n when the pmu generates an smi, a bit is set in the nmi/smi control register to indi- cate to software which pmu event generated the smi. writing any value to the nmi/smi control register clears this bit. n prior to writing the nmi/smi control register, the register should be read again to determine if any additional smi events have occurred during the time it took to process the previous event. if additional smi events have occurred, they should also be pro- cessed starting with a write to the pmu status 1 register at index a2h. otherwise, these events may be lost. n if in temporary-on mode, activity on the sus /res pin is delayed until a write to the nmi/smi control register occurs. n temporary-on mode is not a pmu mode in the normal sense. its state cannot be read at the cpu status 1 register at index a4h like other pmu modes. it is really a special- case state that turns on system clocks to allow the cpu to temporarily process instruc- tions. this allows servicing an event that may occur while the pmu is in a clock- stopped mode. n a suspend input causes further activity on the sus /res pin to be ignored until the pmu has finished transitioning to sleep mode. n the pmu can request that the processor perform an smi. this request is in the form of holding the cpu?s smi signal active. the cpu ignores this request if it is already pro- cessing an smi, and it continues to do so until the smi handler executes the res3 instruction. the res3 instruction signals the end of the smi. if the pmu is asserting an smi request when res3 is executed, another smi signal is generated by the cpu. otherwise, control returns to the software that was initially interrupted by the smi. n once an smi handler is entered, it must clear the pmu?s smi request to the cpu. this is done by writing any value to the pmu status 1 register at index a2h. the smi cpu input is level sensitive. as stated above, if a pmu smi request is pending upon execu- tion of res3, another smi is generated immediately by the cpu. this write to the pmu status 1 register should happen after the smi status register at index 43h and the nmi/smi control register at index a5h are read to determine the cause of the smi, but before the smi status register and the nmi/smi control register are written in order to clear their status. n when a resume input is serviced by the pmu, it places the pmu into full-on mode and then generates the resume smi. in other words, the pmu is not in a temporary- on mode during this smi. a suspend input at this point in the code will immediately start transitioning the pmu towards sleep mode. n the smm memory area can be redirected through an mms page at 060000h to point to any location in system memory.
power management 1-37 1.9.1 required initialization for the following sus /res smi-handler design to work, the following con?uration-regis- ter initializations must be performed: n initialize the sleep-to-suspend time-out to a nonzero value, such as writing 01h to the sleep to suspend timer register at index 86h. n allow the resume input to generate an smi. this is done via bit 0 of the nmi/smi enable register at index 82h. n set bit 7 of the smi mms upper page register at index a9h to select an smi instead of an nmi. this choice applies to all pmu events that are unmasked via the nmi/smi enable register at index 82h. n set up the smm memory area to the desired system memory location (bits 5? of the smi mms upper page register at index a9h and the smi mms page register at index aah). n mask all wake-up events (via the resume mask register at index 08h) and activities that can cause the system to wake up (bits 6 and 4? of the activity mask 1 register at index 75h). this means only the resume input can wake up the system from sleep or suspend modes, ensuring the resume smi is always executed. 1.9.2 start of smi handler smi handler code must determine why the handler has been entered. since all smis cause the processor to enter real mode and jump to the reset vector, it must be deter- mined early in the boot code whether an smi handler is being executed (bit 7 of the ver- sion register at index 64h). if so, the handler must determine whether a suspend or a resume is in progress. this may be accomplished by reading the nmi/smi control regis- ter at index a5h and checking to see whether the smi was caused by a sleep-to-sus- pend mode transition (bit 3) or by a resume input (bit 0). 1.9.3 suspend input caused the smi if a suspend input caused the smi, the following events occurred: 1. the system was running in high-speed pll, low-speed pll, or doze mode. 2. a rising edge was detected on the sus /res input (a suspend input). 3. the pmu started to ignore further activity on the sus /res input (sus /res activity). 4. the pmu stepped down through the pmu modes, one per refresh, until sleep mode was entered. (note that the pmu would wake up to high-speed pll mode if a resume input had occurred at this point.) 5. the sleep-to-suspend timer expired. 6. the pmu mode started to change from sleep to suspend, causing an smi. at the same time, the pmu became capable of buffering (delaying) one subsequent sus /res activity. (if this activity occurred at this point, it would be delayed until index a5h was next written. the pmu would then process the activity as if it had just occurred.) in addition, the pmu entered temporary-on mode, causing the cpu to start running at 9.2 mhz. 7. when the smi handler was entered, smis were automatically masked by the cpu until the next execution of the res3 instruction.
1-38 power management 1.9.4 suspend pseudocode 1. the pmu status 1 register at index a2h is written in order to clear the pmu smi request to the cpu. 2. platform-dependent code prepares the system for the suspend operation. 3. the bit location in the smm ram state-save area that contains the value of bit 12 of dr7 (the processors state) must be cleared. this handles an ?lansc310 microcon- troller cpu errata where bit 12 of dr7 is automatically set prior to the smm state save. if this bit is not cleared in the smm state-save area prior to the cpu executing a res3 instruction, the erroneous bit is reloaded into dr7 and the trace opcode (f1h) is rede?ed as a soft smi. the next trace instruction causes a soft smi to occur. 4. the nmi/smi control register at index a5h is read to determine if any additional smi events have occurred while processing the suspend smi. these additional events should also be processed or they will be lost. 5. the nmi/smi control register is written, which causes the pmu to exit temporary-on mode on the next refresh and transition from sleep to suspend mode. at the same time, the ability of the next rising edge on the sus /res input to generate a wake-up into high-speed pll mode is converted to immediate instead of buffered. 6. at this point, the smi handler polls bit 4 of the at-compatible b port (61h), looking for at least one refresh. each time the bit toggles, a refresh has occurred. this must be done to ensure that the pmu transition into suspend mode occurs before any more of the suspend smi handler is executed. the cpu clock thus stops before the res3 instruction is executed. this is done to prevent control from being returned to the appli- cation that was interrupted by the smi. this should be avoided because the system has been prepared for suspend mode. peripheral devices may have been turned off, which causes errors if accessed in this state. the cpu clock is now stopped and the system is suspended. from this point on, an edge on the sus /res pin is considered a resume input. note that although res3 has not been executed by the cpu (thus ending the suspended smi), all remaining suspend-smi code after this is processed as the result of a resume input. the effect is that the last few instructions of the suspend handler (everything before res3) are really the ?st few instructions of the resume code. this is not to say that the resume smi entry point is any- where in the suspend smi handler. the remainder of the handler execution follows: 7. a resume input is detected. this transitions the pmu into high-speed pll mode and causes it to assert an smi request to the cpu. note that the smi request is not seen by the cpu at this point because res3 has not been generated for the suspend smi. 8. the cpu res3 instruction is executed to signal the end of the smi routine. this allows the cpu to detect pending smis asserted by the pmu. as a result of the pend- ing smi request, an smi is generated immediately, and the smi routine is entered to process the resume.
power management 1-39 1.9.5 resume input caused the smi if a resume input caused the smi, the following events occurred: 1. the cpu was in the sleep, suspend, or off mode. 2. a rising edge was detected by the sus /res input. 3. the pmu jumped directly into high-speed pll mode on the ?st refresh following the resume input. note: at this point, the next sus /res edge is considered a suspend input. 4. the resume input caused an smi. 5. the smi handler was entered and smis were automatically masked by the cpu until a res3 is executed. 1.9.6 resume pseudocode 1. the pmu status 1 register at index a2h is written in order to clear the pmu smi request to the cpu. 2. platform-dependent code prepares the system for the resume operation. 3. the nmi/smi control register at index a5h is read to determine if any additional smi events have occurred while processing the suspended smi. these additional events should also be processed or they will be lost. 4. when the pmu generates an smi, a bit is set in the nmi/smi control register to indi- cate to software the pmu event that generated the smi. the nmi/smi control register is written to clear this bit. 5. the bit location in the smm ram state-save area that contains bit 12 of dr7 (the pro- cessors state) must be cleared. this handles an ?lansc310 microcontroller cpu errata where bit 12 of dr7 is automatically set prior to the smm state save. if this bit is not cleared in the smm state-save area prior to the cpu executing a res3 instruction, the erroneous bit will be reloaded into dr7. the trace opcode (f1h) is rede?ed as a soft smi. the next trace instruction then causes a soft smi to occur. 6. the cpu res3 instruction is executed to signal the end of the smi routine and to arm further smis. 7. the application program regains control. 1.9.7 things to avoid do not allow the suspend handler to execute res3 until the resume keystroke occurs. failure to adhere to this results in control returning to the application program with the cpu clock running for a short period of time. if application code is executed during this time, there is a chance that powered-down peripherals will be accessed. even dram may be powered down at this point as a result of the preparation for suspend mode.
1-40 power management 1.10 auto low-speed logic the ?lansc310 microcontrollers auto low-speed logic provides a way for the system designer to ?e-tune the systems current consumption in high-speed pll mode. auto low-speed mode is enabled by setting bit 3 of the control b register at index 77h. auto low-speed mode has no effect unless the high-speed clock is enabled at bit 6 of the i/o wait state register at index 61h. when enabled, the auto low-speed logic causes the use of the high-speed clock to be disallowed at periodic intervals when in high-speed pll mode. during the active trigger period, all bus cycles are performed at 9.2 mhz in high- speed pll mode. there is no effect in any other pmu mode. the start and end of the low-speed interval is synchronized with refresh. to program the trigger and duration peri- ods, see ?uto low-speed control register (index 9fh) on page 4-51. 1.11 micro power-off mode the micro power-off feature of the ?lansc310 microcontroller should not be confused with a pmu mode or state such as high-speed pll mode, low-speed pll mode, or suspend mode. there is no software processing required or available to enter the micro power-off mode. for most applications, micro power-off mode is like completely turning off the power to the system while maintaining real-time clock operation and cmos contents. the system enters micro power-off mode immediately when the ioreset pin is sam- pled low. there is no option to generate an smi or nmi to save the system state upon detection of ioreset being asserted. the type of micro power-off dram refresh performed (cas-before-ras, or self-refresh) is the same as that for which the part was contgured (via bit 3 of the miscellaneous 5 register at index b3h) prior to sampling the ioreset pin low. exiting micro power-off mode is analogous to a power-up cold boot, with the exception that the bits shown below remain set to their previously programmed values. the contgu- ration-register bits that are not reset when exiting micro power-off mode are as follows: n bits 1e0 of the version register at index 64h n bits 7e0 of the clock control register at index 8fh n bits 7e4 and 2e0 of the reserved register at index 9dh n bit 1 of the pmu control 1 register at index a7h n bit 3 of the miscellaneous 5 register at index b3h n bits 4e0 of the miscellaneous 3 register at index bah the one software option that relates to micro power-off mode is whether the dram con- tents will be maintained along with the cmos/rtc functions mentioned in the preceding paragraph. this option is enabled by setting bit 2 of the miscellaneous 3 register at index bah. this bit is cleared upon core reset, using the resin pin. ioreset has no effect on this bit. the bit may be used by system trmware to determine whether or not dram has been retained after an ioreset has occurred. for more information on the micro power-off mode, see the ?lansc310 microcontroller data sheet, pid 20668 .
power management 1-41 1.12 other power-saving features the ?lansc310 microcontroller has additional features that provide reduced power con- sumption. these features can be enabled at the system designers discretion. 1.12.1 dma clock stop this feature is enabled by bit 3 of the function enable 1 register at index b0h. it causes the clock to the 8237 dma controller to stop except when actually needed to perform a dma transfer. this feature operates independently of the pmu mode. if clocks are not disabled by the pmu, the dma clock starts after one of the drqs goes active high, and the dma clock continues running until aen is deasserted. 1.12.2 data-path disabling logic the following bits help limit the amount of data-bus toggling in the ?lansc310 microcon- troller to peripheral devices which are not in use: n bits 4 and 5 of the pmu control 1 register at index a7h can be set to disable data-bus toggling to the internal uart and pmu blocks during memory cycles. n bit 4 of the miscellaneous 4 register at index 44h, if 1, disables data-bus toggling to most of the ?lansc310 microcontroller (except between the cpu and the external data-bus interface) during internal dram cycles. 1.12.3 slow refresh for systems using dram that supports slow refresh, the ?lansc310 microcontroller pro- vides ?e user-selectable refresh rates. the default refresh rate is the slowest: 8192 refreshes per second. if bits 0 and 1 of pmu control 1 register at index a7h are 0, the refresh rate is controlled by bits 1 and 0 of the version register at index 64h. sup- ported rates are 32768, 16384, 10922, and 8192 refreshes per second. if bit 0 of the pmu control 1 register at index a7h is 0 and bit 1 is 1, the refresh rate becomes 65536 refreshes per second; if bit 0 is 1, the 8254 becomes the refresh source. 1.12.4 quiet bus setting bit 2 of the control a register at index 48h disables memr and memw on the isa bus from toggling during internal memory cycles.
memory management 2-1 chapter 2 memory management from the programmers perspective, the ?lansc310 microcontroller manages three sep- arate 16-mbyte memory-address spaces: system memory rom bios rom dos in addition, the ?lansc310 microcontroller manages a single 64-kbyte i/o address space. only the system-memory-address space is directly accessible in its entirety; the rom- bios and rom-dos address spaces are directly accessible in part. the bulk of the rom-bios and rom-dos address spaces are accessible only via a memory-mapping system. the actual memory of a system based on the ?lansc310 microcontroller consists of memory devices?ram and eproms or ?sh memory. usually, only a subset of each address space corresponds with any device, and many addresses are not associated with any device. for example, a typical con?uration might have only 8 mbyte of dram system memory, 128 kbyte of bios rom, and 128 kbyte of dos rom. the ?lansc310 microcontrollers memory controller unit (mcu) is responsible for man- aging access to the address spaces and the associated physical memory.
2-2 memory management 2.1 system memory: dram and bus figure 2-1 on page 2-2 shows a typical system address space for the ?lansc310 micro- controller. the three regions of system-address space are conventional memory (the ?st 640 kbyte), high memory (the next 384 kbyte), and extended memory (the remaining 15 mbyte). only the ?st mbyte (conventional and high memory)?long with the ?st 64 kbyte of extended memory?an be accessed while the ?lansc310 microcontroller is in real mode without using the mms. all 16 mbyte of system-address space may be addressed while the ?lansc310 microcontroller is in protected mode. for more informa- tion on real and protected modes, see the am486 microprocessor software users manual , pid 18497. in figure 2-1 on page 2-2, the shaded portion of the address space represents on-board memory. that is, it represents the portion of the system address space that is currently associated with physical memory chips attached to the ?lansc310 microcontrollers sys- tem board (e.g., in simms). the unshaded portion can be associated with memory devices connected to the isa or local bus. these addresses will be empty if no isa or local-bus memory devices are attached. for on-board memory, the ?lansc310 microcontroller supports only dram. the ?lansc310 microcontroller supports two different bus con?urations: n local bus with a partial isa bus n maximum isa bus the selection of one of these two options must be made when the system is designed and may not be changed dynamically. this choice also affects the meaning and behavior of several pins. for information on exactly which pins are affected, refer to the ?lansc310 microcontroller data sheet, pid 20668 . figure 2-1 typical at address space 000000h extended memory 0a0000h 0fffffh 100000h ffffffh top of on-board memory 09ffffh 640 kbyte 1 mbyte 16 mbyte high memory conventional memory
memory management 2-3 2.1.1 dram configurations the ?lansc310 microcontroller supports up to 16 mbyte of on-board dram, organized as one or two memory banks (16-bit data path to memory). the ras0 and ras1 signals enable the banks, while the cas0l , cas0h , cas1l , and cas1h signals are used to select the upper and lower sections of each bank. each bank is 16 bits wide and contains 1, 2, or 4 chips depending on the bit architecture of the memory chips. the following bits are used to specify the memory size and architecture: n bits 4? of the memory con?uration 1 register at index 66h n bits 7? of the function enable 2 register at index b1h n bit 7 of the function enable 3 register at index b4h insight into the mapping of both dram con?urations can be gained by examining table 4-23 on page 4-28 and table 4-38 on page 4-63. as an example of how to program the memory con?uration, the settings in table 2-1 on page 2-3 select a 4-mbyte memory that is organized into two banks and con?ured for enhanced-page-mode operation. 2.1.2 refresh and wait states the ?lansc310 microcontroller supports two memory refresh modes: n 8254-based dram refresh n slow-refresh dram the 8254-based dram refresh cannot be selected if power management is performed because the 8254 clock will be turned off in suspend mode. memory refresh needs to remain enabled since the pmu uses the refresh pulse to synchronize events. the refresh frequency is under programmer control. see ?mu control 1 register (index a7h) on page 4-56 and ?ersion register (index 64h) on page 4-26. for example, the settings shown in table 2-2 on page 2-3 perform the following opera- tions: n select slow-refresh mode for dram refreshes. the drams are refreshed at the rate selected by bits 1 and 0 of the version register at index 64h. n select the 32-khz clock input as the refresh source. table 2-1 memory initialization example instruction ports data comment iow iow 022h 023h b4h 0100 0000 enable the memory con?uration 1 register at index 66h to select memory con?uration. iow iow 022h 023h 66h xxx1 0011 select 4-mbyte memory con?uration (enhanced page mode). note that bits 6? are read only. table 2-2 refresh initialization example instruction ports data comment iow iow 022h 023h a7h xxxx xx00 enable slow refresh; select 32-khz clock for refresh source; disable refresh during sleep mode.
2-4 memory management the ?lansc310 microcontroller also supports a variety of speeds of rom. some speeds require wait states to be inserted in memory accesses between the point in a cycle when the read or write signal is asserted and the point where the data is transferred to or from the memory device. the number of wait states to be inserted under different conditions is under programmer control. page-mode drams are organized so that successive locations are along the same row, or page . this allows the memory controller to generate a single-row address if successive accesses happen to lie in the same page (a page hit ). when a page hit occurs, the mem- ory cycle can be shortened by eliminating the row-address portion of the cycle. at the programmers discretion, wait states may be inserted into the page-mode cycle. the pro- grammer has the option to set the number of wait states after a page miss and the num- ber of ?st-cycle wait states. the number of wait states for a page-hit read cycle and a page-hit write cycle are ?ed at 0 and 1, respectively. the settings in table 2-3 on page 2-4 set up page-mode dram accesses using the mod select bit of the memory con?uration 1 register at index 66h. they set the ?st-cycle wait state to 3 cycles (the default) and the bank-miss wait states to 5 by setting the following bits: n bits 5 and 6 of the wait state control register at index 63h n bit 5 of the rom con?uration 1 register at index 65h n bit 4 of the mms memory wait state 1 register at index 62h the ?lansc310 microcontroller also supports enhanced page mode when both banks of dram are used. it may be selected using bit 0 of the memory con?uration 1 register at index 66h. this mode effectively doubles the page size by arranging the dram address lines such that one page is spread across both dram banks. this avoids the precharge penalty that would otherwise occur when incrementing across the bank-section boundary. for more information on the enhanced-page-mode address translation, see the ?lansc310 microcontroller data sheet, pid 20668 . table 2-3 memory-speed initialization example instruction ports data comment iow iow 022h 023h 66h xxxx xx10 set memory mode to page-mode drams. note that bits 7? of this register are read only because they affect the choice of bus. iow iow 022h 023h 63h x11x xxxx set top bits of ?st-cycle wait state to 3 and bank-miss wait state to 5. iow iow 022h 023h 65h xx1x xxxx set low bit of ?st-cycle wait to 3. iow iow 022h 023h 62h xxx1 xxxx set low bit of bank-miss waits to 5.
memory management 2-5 table 2-4 on page 2-5 shows the number of wait states required in a 33-mhz ?lansc310 microcontroller con?uration for 70-ns page-mode drams. 2.1.3 maximum isa and local bus configurations the ?lansc310 microcontroller is designed as a single-chip integration of all the principal components needed for an embedded pc. the ?lansc310 microcontroller supports the following strategies for video control: n a local-bus interface n the ?lansc310 microcontrollers maximum isa bus interface the local-bus interface is integrated with the memory controller and the isa-bus control- ler, and it permits fast transfers to and from external local-bus peripherals such as video controllers. these two strategies are alternatives because they share the same set of pins. the con- ?uration employed (local bus or maximum isa bus) depends on the initial values of bits 5 and 6 in the memory con?uration 1 register at index 66h at system reset. these initial values are determined by the values of the dtr and r ts pins, which are estab- lished by pull-up or pull-down resistors attached to the pins. they are not set at run time by programming the registers. table 2-5 on page 2-5 shows the meaning of these pins and bits. table 2-4 33-mhz wait states cycle type wait states read cycle, page hit 0 write cycle, page hit 1 first cycle 3 page miss 5 table 2-5 bus con?uration bus selected dtr (cfg1) r ts (cfg0) local bus 1 0 maximum isa x 1 figure 2-2 ?lansc310 microcontroller bus con?urations ?lansc310 microcontroller local-bus mode dtr (high) rts (low) common local bus ?lansc310 microcontroller maximum isa bus mode maximum isa bus common dtr (high) rts (high)
2-6 memory management 2.2 rom-bios memory rom-bios memory is accessed when the ?lansc310 microcontroller activates the bios chip-select signal (r omcs ). the combination of this signal and the 24 address lines de?es a separate 16-mbyte rom-bios address space. however, usually only a few hundred kbyte of this space are occupied by physical rom devices. rom bios may be accessed directly or as a function of the mms. with the ?lansc310 microcontroller, up to 320 kbyte of non-mms rom bios is supported, and addresses in the ranges 0a0000?affffh and 0c0000?fffffh can be supported. the address range for the rom bios is set via the rom con?uration 1 register at index 65h and the rom con?uration 2 register at index 51h. for additional information, see chapter 3, ?c/at peripheral registers. figure 2-3 on page 2-6 shows a diagram of high memory with all the address ranges indicated that may be programmed in the ?lansc310 microcontroller to generate r omcs (indicated by the word bios ). this ?ure also shows the address ranges that may be shadowed. accesses to the boot- vector location, ff0000?fffffh, always assert the r omcs signal. rom bios is accessed as an 8-bit device unless the system hardware drives mcs16 active, which results in a 16-bit access. there is no programmable option to set whether the rom bios is an 8-bit or 16-bit device. as an example, the settings shown in table 2-6 on page 2-6 implement a 128-kbyte rom bios located at 0e0000?fffffh. figure 2-3 high memory note: the shaded area (0c0000?f0000h) is shadowable. table 2-6 rom-bios address initialization instruction ports data comment iow iow 022h 023h 51h xxxx xxx0 disable r omcs for 0a0000?affffh. iow iow 022h 023h 65h xxxx 0010 enable r omcs for 0e0000?fffffh; disable it for 0c0000?dffffh. 0a0000h bios 0b0000h 0c0000h 0d0000h 0e0000h 0f0000h high memory video bios bios bios bios
memory management 2-7 in order to speed up bios accesses, many pc systems copy the rom-bios contents into on-board dram at startup. then the system is set to send rom-bios accesses to the dram instead of the rom. this technique is called rom shadowing . the usual implementation is to copy the bios image stored in rom to the same addresses in system ram, and then transfer program control to the bios image in sys- tem ram (see figure 2-4 on page 2-7). for example, to shadow rom to ram in a system where the bios rom is a 128-kbyte section located from 0e0000h to 0fffffh in cpu address space, the following algorithm can be implemented: 1. copy the rom-based image into a 128-kbyte buffer in conventional ram. 2. jump to the exact same place in the conventional ram-based bios image that was being executed in the rom-based bios image. 3. enable the ?lansc310 microcontrollers shadow-ram function and disable the shadow rams write-protect feature by setting bits 4 and 7 of the rom con?uration 1 register at index 65h. 4. set the shadow-ram address range to match the bios roms range of 0e0000h to 0fffffh by writing ffh to the shadow ram enable 2 register at index 69h. 5. disable r omcs for the range 0e0000?fffffh by setting bit 0 and clearing bit 1 of the rom con?uration 1 register. 6. copy the conventional ram-based bios image to shadow ram from 0e0000h to 0fffffh. once this is done, shadow ram may optionally be write protected by clear- ing bit 7 of the rom con?uration 1 register. 7. jump to the same place in the shadow-ram-based bios image that was being exe- cuted in the conventional ram-based bios image. note: use caution when performing read-modify-write sequences of the rom con?uration 1 register. bit 0 reads the inverse of what was last written; therefore, it must be ?pped again prior to write-back to keep r omcs settings unchanged. figure 2-4 copying rom contents 16 mbyte 16 mbyte system memory rom- bios memory 0fffffh 0e0000h 0fffffh 0e0000h 00 copy copy
2-8 memory management 2.3 rom-dos memory rom-dos memory is accessed whenever the ?lansc310 microcontroller activates the doscs chip-select signal. the combination of this signal and the 24 address lines de?es a separate 16-mbyte rom-dos address space. this implementation is particu- larly well suited for accessing roms that contain a disk image loaded by dos. hence the name rom dos. the rom-dos address space can be con?ured as either an 8-bit or 16-bit device. bit 1 of the rom con?uration 2 register at index 51h controls this. the default is an 8-bit device. the rom-dos address space is typically accessed using the ?lansc310 microcontrol- lers mms, which is described in ?emory mapping on page 2-9. in addition to using mms, up to 15 mbyte minus 64 kbyte of rom-dos address space can also be accessed as direct system memory using linear address decodes. bits 3? of the rom con?uration 3 register at index b8h determine the address range used for the rom- dos decode. if these bits are 0, the rom-dos address space is accessible only through mms. table 4-42 on page 4-68 provides the bit settings for the allowable address ranges. note that the top of the address range is ?ed at feffffh. the address range ff0000?fffffh is reserved for rom bios. as the size of the rom-dos linear-decode address space increases, the lower address boundary decreases. care must be taken to ensure that the rom-dos linear-decode address range does not overlap the on-board dram range. bits 7? of the miscellaneous 1 register at index 6fh can be used to prevent the upper portion of system dram from being accessed as direct system memory, thereby eliminating the con?ct.
memory management 2-9 2.4 memory mapping the ?lansc310 microcontrollers memory controller supports a memory mapping sys- tem (mms). the mms de?es two windows in the ?st mbyte of system address space: n mmsa, with eight 16-kbyte pages n mmsb, with four 16-kbyte pages the programmer can set these pages to point to any similarly sized page of rom dos, rom bios, or on-board dram. once these pages are programmed, an address gener- ated in a system-address page is automatically translated into an access to the mapped page of the other address space. figure 2-5 on page 2-9 shows the basic idea. using the ?lansc310 microcontrollers mms windows, it is possible to access every addressable location in each of the ?e address spaces listed. the beginning of the mmsa window may be located at one of six starting addresses between 0c0000h and 0d4000h. the mmsb window always starts at 0a0000h. figure 2-6 on page 2-10 shows how high memory contains the mmsa and mmsb win- dows. notice that mmsa can have six different positions, depending on how the mms address register at index 6dh is programmed. the mmsa window size is ?ed at 128 kbyte (8 pages ?16 kbyte). the mmsb window size is ?ed at 64 kbyte (4 pages ? 16 kbyte). figure 2-5 memory mapping system page 2 page 3 page 4 page 5 page 6 0 0 0 system memory 16 mbyte 16 mbyte 16 mbyte mmsa mmsb page 0 page 1 page 2 page 3 page 0 page 1 page 7 rom-bios memory on-board dram memory 16 mbyte rom dos 0
2-10 memory management the mms windows and their corresponding pages are set up by programming several con?uration registers in the ?lansc310 microcontroller. in particular, control is exer- cised through the following registers: n rom con?uration 1 register at index 65h n mmsa address extension 1 register at index 67h n mms address extension 1 and 2 registers at indexes 6ch and 6eh n mms address register at index 6dh n mmsa device 1 and 2 registers at indexes 71h and 72h n mmsb device register at index 73h n mmsb control register at index 74h all the index registers used in this section can be referenced in appendix a, ?on?ura- tion index register reference, as mms registers except for the rom con?uration 1 register. bits 3? of the mms address register at index 6dh de?e the location in i/o space of the eight mmsa and four mmsb page registers. bit 1 of the mmsb control reg- ister at index 74h determines whether the page-register i/o locations are accessing mmsa page registers or mmsb page registers. each mms window contains a global switch that enables or disables all the pages within that window. bit 5 of the rom con?uration 1 register at index 65h is the switch bit for mmsa. bit 0 of the mmsb control register at index 74h is the switch bit for mmsb. as stated earlier, each mms page is a ?ed size of 16 kbyte. each page is mappable to an equal-size page located on a 16-kbyte boundary in one of the three address spaces: rom dos, rom bios, or on-board dram. each individual page within an mms window can be enabled or disabled by setting or clearing a bit in its corresponding page register. system ram is not the default device that is accessed if an mms window or a page of an mms window is disabled. this allows externally decoded, memory-mapped devices on figure 2-6 mmsa and mmsb 0f0000h 0e0000h 0d0000h 0c0000h 0b0000h 0a0000h mmsa high memory mmsb
memory management 2-11 the isa bus to exist in the address spaces that are normally decoded by the mms win- dows. thus, if more than 640 kbyte of system ram is desired for use by a dos memory extender (for example), the mms page should be programmed to point to system ram explicitly. this feature also allows a block of system address space in high memory to be left open for use by the emm386 memory manager to map in pages of extended memory using capabilities provided by 386-class and higher processors. another implication of system ram not being the default device is that if the base address for mmsa is not set to 0c0000h, only externally decoded devices can utilize the address space abandoned by mmsa in this example. more speci?ally, if mmsa is made to start at 0c8000h, the 32 kbyte of address space from 0c0000h to 0c7fffh is usable only if decoded by an external isa memory-mapped device (e.g., a vga rom). the address spaces?om dos and rom bios?re implemented as chip-select sig- nals in the ?lansc310 microcontroller to eliminate the need for external address decod- ing. cycles to these devices use the isa command signals, memr and memw. thus, any external device that does not have access to the chip signals generated by the ?lansc310 microcontroller (such as isa devices) may have address con?cts with cycles that use the mms mapping. there is no separate command-signal option for interfacing to the dos rom. it is sug- gested that the dos or application rom be made to physically reside above 1 mbyte in the system-address space to avoid con?cts with devices whose decoding is ?ed by the pc/at architecture. it is invalid to have rom bios shadowing enabled for a region that contains an enabled mms page. if this is done, con?cts will result when accessing the overlapping areas. for example, if rom bios shadowing is enabled for the address range 0e0000?effffh and the mmsa starting address is set to 0c4000h, then mmsa page 7 (0e0000?e3fffh) should always remain disabled. figure 2-7 on page 2-12 shows an example of mms mapping between system-address space and all three address spaces. in this example, there are 8 mbyte of on-board mem- ory. one page of rom-bios space, two pages of rom-dos space, and two pages of on-board memory are being mapped. the settings in table 2-7 on page 2-13 de?e the mms mapping shown in figure 2-7 on page 2-12.
2-12 memory management figure 2-7 mms mapping example notes: the con?uration is summarized as follows: mmsa base address: 0d0000h page 0: on-board (5fc000?fffffh) page 1: on-board (600000?03fffh) page 2: (not mapped) page 3: (not mapped) page 4: (not mapped) page 5: (not mapped) page 6: rom dos (220000?23fffh) page 7: rom dos (ffc000?fffffh) mmsb base address: 0a0000h page 0: (not mapped) page 1: (not mapped) page 2: (not mapped) page 3: rom bios (400000?03fffh) page 2 page 3 page 4 page 5 page 6 system memory mmsa mmsb page 0 page 1 page 2 page 3 page 0 page 1 page 7 0a0000h on-board memory 0affffh 0d0000h 0effffh 0 16 mbyte rom bios 0 rom dos 16 mbyte 8 mbyte 0 dram
memory management 2-13 table 2-7 mms mapping example settings instruction ports data comment iow iow 022h 023h 66h xxx1 011x set on-board memory size to 8 mbyte. note that bits 7? are read only because they affect the choice of bus. iow iow 022h 023h 74h xxxx xx1x select mmsa for programming. iow iow 022h 023h 6dh 0100 0000 set mmsa base address to d0000h and i/o base address to 0208h. iow iow 022h 023h 6ch 1000 0000 set all translated mmsa a23s (page 7 = 1, others = 0). iow iow 022h 023h 6eh 0000 1110 set a22 and a21 for mmsa pages 0?. iow iow 022h 023h 67h 1101 0000 set a22 and a21 for mmsa pages 4?. iow iow iow iow iow iow iow iow 0208h 2208h 4208h 6208h 8208h a208h c208h e208h 1111 1111 1000 0000 0xxx xxxx 0xxx xxxx 0xxx xxxx 0xxx xxxx 1000 1000 1111 1111 translate a20?14 of mmsa page 0; enable the page. translate a20?14 of mmsa page 1; enable the page. disable translation for mmsa page 2. disable translation for mmsa page 3. disable translation for mmsa page 4. disable translation for mmsa page 5. translate a20?14 of mmsa page 6; enable the page. translate a20?14 of mmsa page 7; enable the page. iow iow 022h 023h 71h xxxx 0101 set memory type for mmsa pages: 0? on board (pages 2-3 not mapped). iow iow 022h 023h 72h 0000 xxxx set memory type for mmsa pages: 6? rom dos (pages 4-5 not mapped). iow iow 022h 023h 65h x1xx xxxx enable mmsa. iow iow 022h 023h 74h xxxx xx01 enable mmsb and select mmsb for programming. iow iow 022h 023h 6ch xxxx 0xxx set all translated mmsb a23s (pages 0,1, 2 not translated). iow iow 022h 023h 6eh 10xx xxxx set a22 and a21 for mmsb page 3 (pages 0,1, 2 not translated). iow iow iow iow 0208h 2208h 4208h 6208h 0xxx xxxx 0xxx xxxx 0xxx xxxx 1000 0000 disable translation for mmsb page 0. disable translation for mmsb page 1. disable translation for mmsb page 2. translate a20?14 of mmsb page 3; enable the page. iow iow 022h 023h 73h 11xx xxxx set memory type for mmsb pages: 0? (unmapped), 3 (rom bios).
2-14 memory management 2.5 other memory controller information 2.5.1 rom chip-select command gating the doscs and r omcs chip-select outputs of the ?lansc310 microcontroller are, by default, internally gated with the memory-read command (memr ) or the memory-write command (memw ). in the ?lansc310 microcontroller, the following con?uration regis- ter bits may be used to disable the command gating and allow the doscs and r omcs signals to be available as address decodes only: n bit 2 of the miscellaneous 5 register at index b3h enables the r omcs signal as an address decode as follows: 0 address decode with command gating 1 address decode only n bit 4 of the rom con?uration 3 register at index b8h enables the doscs sig- nal as an address decode as follows: 0 address decode with command gating 1 address decode only when the cpu clock is stopped, the r omcs and doscs chip-selects are forced high. 2.5.2 wait states and command delays the ?lansc310 microcontroller provides several programmable options for controlling the number of wait states and command delays inserted into a cycle. this section covers wait states and command delays for rom-bios, rom-dos, and isa cycles. a command delay is inserted between the point in a memory or i/o cycle where the address is placed on the bus and the point where the memory or i/o, read or write, com- mand signal is asserted. this delay gives slower devices extra time to decode the address. command delays do not lengthen the overall cycle time. that is, the command signal is deasserted at the same time it normally is (determined by the number of wait states), without the command delay. the net effect is a shortened command time. table 2-8 on page 2-14 documents the duration of the command delay for the various cycles. table 2-8 command delay duration for various cycles cycle type command delay duration (in sysclk cycles) 8-bit isa memory 1 or 0.5 (determined by bit 2 of the command delay register at index 60h) 8-bit rom-dos memory 0, 0.5, or 1 (determined by bit 2 of the command delay register and bits 2 and 6 of the mms memory wait state 2 register) 8-bit rom-bios memory 0.5 16-bit memory (all) 0 8-bit external i/o (0100?3ffh) 0.5, 1, 2 (determined by bits 0 and 1 of the command delay register) 8-bit internal i/o (000?ffh) 0.5 16-bit external i/o (0100?3ffh) 0.5
memory management 2-15 wait states extend the amount of time the read- or write-command signal is asserted for memory or i/o accesses. this has the effect of increasing the total length of the cycle. table 2-9 on page 2-15 documents the number of wait states for the various rom-dos, rom-bios and isa cycles. 2.5.3 high-speed clock rom cycles to improve the rom-access times, an option is provided so that accesses using the r omcs or doscs chip selects may run at the high-speed cpu clock rate rather than the low-speed cpu clock rate of 9.2 mhz. 2.5.4 rom chip-select signal the high-speed cpu clock rate is enabled for the rom chip-select (r omcs ) signal and unique wait-state controls for each rom chip-select may be programmed through the miscellaneous 5 register at index b3h. n bit 6 of the miscellaneous 5 register at index b3h enables r omcs rom accesses to run at the high-speed cpu clock rate as follows: 0 disabled (default) 1 enabled n bits 5 and 4 of the miscellaneous 5 register at index b3h control the number of wait states for fast r omcs cycles (see table 2-10 on page 2-16). table 2-9 wait states for various cycles cycle type number of wait states (in sysclk cycles) 8-bit isa memory 8-bit rom bios (mms-accessed) 2, 3, 4, or 5 (determined by bits 0 and 1 of the mms memory wait state 1 register at index 62h) 8-bit rom dos (mms accessed and linearly decoded) 1, 2, 3, 4, or isa setting (determined by bits 2? of the mms memory wait state 2 register) 8-bit rom bios (not mms accessed) 2 or 3 (determined by bits 7 and 4 of the command delay register at index 60h) 16-bit rom-dos, rom-bios and isa memory 1, 2, 3, or 4 (determined by bits 3 and 2 of the mms memory wait state 1 register) 8-bit internal i/o (000?ffh) 2 or 4 (determined by bit 3 of the wait state control register at index 63h) 8-bit ?ppy-disk-drive i/o (3f0?f7h) 2, 3, 4, or 5 (determined by bits 1 and 0 of the i/o wait state register at index 61h) 8-bit hard-disk-drive i/o (1f0?f7h) 2, 3, 4, or 5 (determined by bits 3 and 2 of the i/o wait state register) other 8-bit i/o (100?ffh) 2, 3, 4, or 5 (determined by bits 5 and 4 of the i/o wait state register) 16-bit i/o 3 or 4 (determined by bit 2 of the wait state control register)
2-16 memory management note that if the ?lansc310 microcontroller is in its maximum isa bus mode, the bale output will not be generated for high-speed r omcs cycles. it is recommended that fast r omcs cycles not be enabled in systems where the target r omcs device is an 8-bit device and other devices in the system assert mcs16 . this is because the mcs16 timing is violated when the isa bus is running at the high-speed pll frequency. for more details, refer to the ?lansc310 microcontroller isa bus anomalies application note , available from the applications hotline. 2.5.5 dos chip-select signal the cpu clock rate is enabled for the dos chip-select (doscs ) signal, and unique wait-state controls for each rom chip select may be programmed through the rom con?uration 3 register at index b8h. n bit 7 of the rom con?uration 3 register at index b8h enables doscs rom accesses to run at the high-speed cpu clock rate as follows: 0 disabled (default) 1 enabled n bits 6 and 5 of the rom con?uration 3 register at index b8h control the num- ber of wait states for fast doscs cycles (see table 2-11 on page 2-16). note that if the ?lansc310 microcontroller is in its maximum-isa-bus mode, the bale output will not be generated for high-speed doscs cycles. table 2-10 romcs wait-state control-bit logic index b3h bit 5 index b3h bit 4 wait states 00 4 01 3 10 2 11 1 table 2-11 doscs wait-state control-bit logic index b8h bit 6 index b8h bit 5 wait states 00 4 01 3 10 2 11 1
memory management 2-17 bit 1 of the rom con?uration 2 register at index 51h should be 1 when enabling fast 16-bit doscs cycles. it is recommended that fast doscs cycles not be enabled in sys- tems where the target doscs device is an 8-bit device and other devices in the system assert mcs16 . this is because the mcs16 timing is violated when the isa bus is running at the high-speed pll frequency. for more details, see the ?lansc310 microcontroller isa bus anomalies application note , available from the applications hotline. 2.5.6 self-refresh drams self-refreshing drams are supported in the ?lansc310 microcontroller as follows: n bit 3 of the miscellaneous 5 register at index b3h enables self-refresh mode when the pmu changes to a mode that causes the cpu clock to stop as follows: 0 disabled (default) 1 enabled n upon exiting the stop clock, the system logic forces one cas-before-ras refresh cycle before the normal cas-before-ras refresh logic takes control. n if a complete burst row refresh is required by the dram, the ?lansc310 microcontrol- ler will not directly support this. 2.5.7 80-ns dram support the ?lansc310 microcontroller supports 80-ns drams when running at 25 mhz, and 70-ns drams when running at 33 mhz.
pc/at peripheral registers 3-1 chapter 3 pc/at peripheral registers the ?lansc310 microcontroller contains internal registers used to display the status of various ?lansc310 microcontroller internal states, to serve as the target for software commands, to act as data paths to external peripherals, and to access other registers. all ?lansc310 microcontroller registers have an address. a small number of registers have explicit i/o addresses?hat is, their location is ?ed in the i/o address space of the am386sxlv processor. however, most of the registers are addressed via an indirect addressing scheme in which a few registers with actual i/o addresses are used to point to the others. this system is explained below in the sections where it is relevant. this chapter only describes the peripheral registers; the con?uration registers are described in the following chapter. for purposes of this manual, the ?lansc310 micro- controllers register set is divided into two groups: n core at-compatible peripheral registers (and miscellaneous at-compatible registers) n con?uration registers registers in the ?st group have explicit i/o addresses, and are directly addressed in i/o space. registers in the second group are addressed indirectly, and have an index value instead of an i/o address. notes: 1. when using a logic analyzer to probe the address, data, and control lines of the ?lansc310 microcontroller, accesses to the internal registers can be captured, with the exception of reads from even addresses. however, when internal registers are accessed, db ufoe is not asserted. 2. in general, the ?lansc310 microcontrollers cores decode only up to address bit a9 for i/o accesses. what this means is that the i/o address space is mirrored every 400h bytes. care should be taken when assigning peripherals i/o addresses above 3ffh so that con?cts with the mirrored i/o registers are avoided.
3-2 pc/at peripheral registers 3.1 bus initialization registers the ?lansc310 microcontroller contains a small number of registers that are indexed off i/o address 3d4h and 3d5h. these registers must be initialized before any local bus or isa bus accesses can be done. refer to table 4-2, "mandatory con?uration bit set- tings," on page 4-3 for a typical initialization programming sequence. once the initializa- tion sequence is complete, these registers can no longer be accessed and any accesses to these i/o addresses will go external on the local bus or isa bus as appropriate. 3.1.1 bus initialization enable register (port 3d4h, index 12h) this index must be read before any of the other port 3d4h index registers can be accessed. 3.1.2 bus initialization register (port 3d4h, index 19h) this register must be initialized before any local bus or isa bus accesses can be done. once this register is written, no other registers in the port 3d4h register set can be accessed. thus, if you wish to access the parallel port address select register (port 3d4h, index 20h) to change the parallel port base address, you must do so before writing index 19h. table 3-1 bus initialization index and data registers port r/w register name description 3d4h w index address index (pointer) to a speci? register in this register set 3d5h r/w index data data for the speci? register in this register set table 3-2 enabling the bus initialization registers perform this access to or from this port with this data write 3d4h 12h (address value) read 3d5h 7 0 field bit (reserved) reset 00000000 bit name r/w function 7? w (reserved?ust be 0) 5 w (reserved?ust be 1) 4-0 (reserved)
pc/at peripheral registers 3-3 3.1.3 parallel port address select register (port 3d4h, index 20h) this register controls the base i/o port address of the internal parallel port. 3.2 pc/at-compatible port registers the core peripherals of the ?lansc310 microcontroller are four standard integrated cir- cuits and logical components compatible with the ibm pc/at motherboard: n 8259a programmable interrupt controller n 8254 counter-timer n 8237a dma controller and dma page n pc/at standard parallel port n uart n real-time clock in addition, one other logical component is often grouped with the core peripherals: n miscellaneous pc/at-compatible registers in this section and the next, these components are described. the miscellaneous pc/at- compatible registers are given their own section because these registers are discussed in detail. only the i/o addresses are shown for the ?st three components, and the reader is directed to standard data sheets for more details. 3.2.1 interrupt controller registers the ?lansc310 microcontroller has two integrated interrupt controllers. these registers are pc/at-compatible versions of the industry-standard 8259a programmable interrupt controller. i/o addresses for the interrupt controller are shown in table 3-4 and in table 3-5 on page 3-4. 7 0 field parallel port i/o select bit (reserved) prnprt1 prnprt0 reset 00000001 bit name r/w function 7? w (reserved?ust be 0) 1? prnprt1?rnprt0 w parallel port i/o select printer i/o port select (see table 3-3 on page 3-3). table 3-3 parallel port i/o select bit 1 bit 0 parallel port i/o base 0 0 (disabled) 0 1 (default) 3bxh 1 0 37xh 1 1 27xh
3-4 pc/at peripheral registers 3.2.2 programmable interval timer registers the timer that is integrated into the ?lansc310 microcontroller is a pc/at-compatible ver- sion of the industry-standard 8254 programmable interval timer. this counter occupies i/o addresses 040?43h. the timer register de?ition and locations are shown in table 3-6 on page 3-5. table 3-4 interrupt controller 1 port r/w description 020h w initialization control word 1, ic1 (d4 =1) 021h w initialization control word 3, master, ic1 021h w initialization control word 3, slave, ic1 021h w initialization control word 4, ic1 021h r/w operation control word 1, (imr), ic1 020h w operation control word 2, ic1 (d5,4 = 00) 020h w operation control word 3, ic1 (d5,4 = 01) 020h r interrupt request register (irr), ic1 020h r in service register (isr), ic1; state register, ic1 note: refer to the 8259a data sheet for an explanation of the control words. table 3-5 interrupt controller 2 port r/w description 0a0h w initialization control word 1, ic2 (d4=1) 0a1h w initialization control word 2, ic2 0a1h w initialization control word 3, master, ic2 0a1h w initialization control word 3, slave, ic2 0a1h w initialization control word 4, ic2 0a1h r/w operation control word 1, (imr), ic2 0a0h w operation control word 2, ic2 (d5,4=00) 0a0h w operation control word 3, ic2 (d5,4=01) 0a0h r interrupt request register (irr), ic2 0a0h r in service register (isr), ic2; state register, ic2 note: refer to the 8259a data sheet for an explanation of the control words.
pc/at peripheral registers 3-5 the input clock to the ?lansc310 microcontrollers 8254 timer runs at 1.1892 mhz. this deviates from the at-compatible standard of 1.19318 mhz. this 0.4% difference can result in incorrect dos clock readings over time if the difference is not taken into account. in at-compatible systems, the bios loads a value of 0ffffh into timer 0, resulting in a timer interrupt every 54.93 ms. to program the ?lansc310 microcontroller to generate the timer-0 interrupt at the same rate, load timer 0 with a value of 0ff23h. a second option is to write the bios timer tick handler to reload the dos clock at regular intervals from the real-time clock (rtc), which maintains accurate time. 3.2.3 dma controller registers the two dma controllers that are integrated in the ?lansc310 microcontroller are pc/at- compatible versions of the industry-standard 8237a dma controller. dma controller addresses are shown in table 3-7 on page 3-6 and in table 3-8 on page 3-7. table 3-6 system timer registers port r/w description 040h r/w timer/counter 0 count register 041h r/w timer/counter 1 count register 042h r/w timer/counter 2 count register 043h r/w timer control word register note: refer to the 8254 data sheet for an explanation of the control words.
3-6 pc/at peripheral registers table 3-7 dma controller 1 port r/w description 000h r/w ch0 base address 001h r/w ch0 base word count 002h r/w ch1 base address 003h r/w ch1 base word count 004h r/w ch2 base address 005h r/w ch2 base word count 006h r/w ch3 base address 007h r/w ch3 base word count 008h r/w ch3 0 read status register/write command register 009h r/w ch3 0 write request register 00ah w ch3 0 write single mask register bit 00bh w ch3 0 write mode register 00ch w ch3 0 clear byte pointer flip-flop 00dh r/w ch3 0 read temporary register/write master clear 00eh r/w ch3 0 clear mask register 00fh w ch3 0 write all mask register bits note: refer to the 8237a data sheet for an explanation of these registers.
pc/at peripheral registers 3-7 3.2.4 dma page registers dma page registers provide the upper address bits during dma transfers. the processor writes the page registers before enabling dma transfers. addresses for the page regis- ters are shown in table 3-9 on page 3-8. table 3-8 dma controller 2 port r/w description 0c0h r/w ch4 base address 0c2h r/w ch4 base word count 0c4h r/w ch5 base address 0c6h r/w ch5 base word count 0c8h r/w ch6 base address 0cah r/w ch6 base word count 0cch r/w ch7 base address 0ceh r/w ch7 base word count 0d0h r/w read status register/write command register 0d2h w write request register 0d4h w write single mask register bit 0d6h w write mode register 0d8h w clear byte pointer flip-flop 0dah r/w read temporary register/write master clear 0dch w clear mask register 0deh w write all mask register bits note: refer to the 8237a data sheet for an explanation of these registers.
3-8 pc/at peripheral registers 3.2.5 parallel port interface registers the parallel port is register-compatible with the industry-standard, at-compatible, epp- compliant parallel port. the parallel port can be set up to have a base i/o address of 3bch, 278h, or 378h. epp support is only possible when the base i/o address is set to 278h or 378h. epp-mode enable and bidirectional enable/control are set by bits 2? of the function enable 1 register at index b0h. the parallel port interrupt is ?ed at irq7. the base i/o address is set using bits 1? of the parallel port address select register (port 3d4h, index 20h).the setting of the parallel port base i/o address can only be done during the processor initialization sequence. refer to section 3.1.2, "bus initialization register (port 3d4h, index 19h)," on page 3-2 and to table 4-2, "mandatory con?ura- tion bit settings," on page 4-3 for details on this initialization sequence. after the parallel port i/o address has been set and, optionally, the epp support or bidi- rectional support has been enabled, then the parallel port registers may be accessed as i/o ports. the parallel port register ?lds are different for at-compatible mode vs. epp- compliant mode. section 3.2.5.1, "at-compatible mode," describes the parallel port reg- isters when the parallel port is con?ured for at-compatible mode. section 3.2.5.2, "epp- compliant mode," describes the parallel port registers when the parallel port is con?- ured for epp-compliant mode. table 3-9 dma page registers address r/w description 0080h r/w general register 0081h r/w channel 2 page register 0082h r/w channel 3 page register 0083h r/w channel 1 page register 0084h r/w general register 0085h r/w general register 0086h r/w general register 0087h r/w channel 0 page register 0088h r/w general register 0089h r/w channel 6 page register 008ah r/w channel 7 page register 008bh r/w channel 5 page register 008ch r/w general register 008dh r/w general register 008eh r/w general register 008fh r/w general register
pc/at peripheral registers 3-9 3.2.5.1 at-compatible mode 3.2.5.1.1 parallel data port (ports 278h, 378h, & 3bch) 3.2.5.1.2 parallel status port (ports 279h, 379h, & 3bdh) 3.2.5.1.3 parallel control port (ports 27ah, 37ah, & 37eh) 7 0 bit data bits 7? default bit name r/w function 7? r/w parallel port data register 7 0 bit b usy a ck pe slct err (reserved) default 00000000 bit name r/w function 7b usy r 0 = printer busy (active low) 6a ck r 0 = printer acknowledge. the printer pulses this line low when it has received a byte of data (active low) 5 pe r 1 = paper end 4 slct r 1 = printer selected 3 err r 0 = printer error (active low) 2? r (reserved) 7 0 bit (reserved) dir irqen slctin init autofdxt strobe default 00000000 bit name r/w function 7? r (reserved) 5 dir r/w bidirectional parallel port data direction: 0 = out (normal printer) 1 = in 4 irqen r/w 1 = printer irq enable. clearing this bit clears any pending interrupts. 3 slctin r/w 1 = printer selected 0 = not selected 2 init r/w printer reset signal control: 0 = hold printer in reset 1 = release printer from reset 1 autofdxt r/w auto-line feed signal control: 1 = a ut ofdxt pin active 0 strobe r/w printer port strobe signal control: 1 = str obe pin active
3-10 pc/at peripheral registers 3.2.5.2 epp-compliant mode 3.2.5.2.1 parallel data port (ports 278h & 378h) 3.2.5.2.2 parallel status port (ports 279h & 379h) 3.2.5.2.3 parallel control port (ports 27ah & 37ah) 7 0 bit data bits 7? default (unde?ed) bit name r/w function 7? r/w parallel port data register 7 0 bit b usy a ck pe slct err ackstat (reserved) eppto default 00000000 bit name r/w function 7b usy r 0 = printer busy (active low) 6a ck r 0 = printer acknowledge. the printer pulses this line low when it has received a byte of data (active low). 5 pe r 1 = paper end 4 slct r 1 = printer selected 3 err r 0 = printer error (active low) 2 ackstat r this bit is latched low when ack transitions low to high. reading this bit sets it to 1. 1 r (reserved) 0 eppto r epp time-out status: 0 = no time-out 1 = epp cycle time-out occurred this bit is reset when either the status register is read or when epp mode is enabled. 7 0 bit (reserved) dir irqen (reserved) init (reserved) default 00000000 bit name r/w function 7? r (reserved) 5 dir r/w bidirectional parallel port data direction: 0 = out (normal printer) 1 = in 4 irqen r/w 1 = printer irq enable. clearing this bit clears any pending interrupts. 3 r (reserved) 2 init r/w printer reset signal control: 0 = hold printer in reset 1 = release printer from reset 1? r (reserved)
pc/at peripheral registers 3-11 3.2.5.2.4 parallel epp address port (ports 27bh & 37bh) 3.2.5.2.5 parallel epp 32-bit data register (ports 27c?7fh & 37c?7fh) a 32-bit i/o write to 27ch or 37ch causes four back-to-back 8-bit bus cycles to occur to the four epp data registers. an epp data strobe is generated for all four bus cycles. a 16-bit i/o write to 27ch or 37ch causes two back-to-back 8-bit bus cycles to occur to the epp data registers 27ch or 37ch and 27dh or 37dh. in common practice, all write accesses to the parallel port epp data register (8-, 16-, or 32-bit i/o instructions) should be directed to port 27ch or 37ch. 3.2.6 uart registers the uart implemented in the ?lansc310 microcontroller is register-compatible with the industry-standard 16450 universal asynchronous receiver/transmitter. 3.2.6.1 transmitter holding register (ports 2f8h & 3f8h) this write-only register contains the data waiting to be transferred. bit 7 is the most signif- icant bit; bit 0 is the least signi?ant bit. 3.2.6.2 receiver buffer register (ports 2f8h & 3f8h) this read-only register contains the data received. bit 7 is the most signi?ant bit; bit 0 is the least signi?ant bit. 7 0 bit address bits 7? default (unde?ed) bit name r/w function 7? r/w address register 7 0 bit address bits 7? default (unde?ed) bit name r/w function 7? r/w address register 7 0 field data to be transmitted default 00000000 7 0 field data to be received default 00000000
3-12 pc/at peripheral registers 3.2.6.3 divisor latch lower byte (ports 2f8h & 3f8h) this register controls the programmable baud-rate generator that is capable of dividing 1.843 mhz by values from 1 to (2 16 ?1). two 8-bit registers store the divisor; this read/write register contains the lower byte. 3.2.6.4 divisor latch upper byte (ports 2f8h & 3f9h) this register controls the programmable baud-rate generator that is capable of dividing 1.843 mhz (i/p osc) by values from 1 to (2 16 ?1). two 8-bit registers store the divisor; this read/write register contains the upper byte. 3.2.6.5 interrupt enable register (ports 2f9h & 3f9h) this register is used to enable uart functions. 3.2.6.6 interrupt identi?ation register (ports 2fah & 3fah) this register is used to identify the nature of an interrupt. 7 0 field baud-rate divisor, lower byte default 00000000 7 0 field baud-rate divisor, upper byte default 00000000 7 0 bit (reserved) emsi elsi etdei erdi default 00000000 bit name r/w function 7? w (reserved) 3 emsi w enable modem status interrupt 2 elsi w enable receiver line status interrupt 1 etdei w enable transmitter holding register empty interrupt 0 erdi w enable receiver data ready interrupt 7 0 field interrupt id bit (reserved) id1 id0 ip default 00000000 bit name r/w function 7? r (reserved) 2 id1 r interrupt id, bit 1 1 id0 r interrupt id, bit 0 0 ip r 0 = interrupt pending
pc/at peripheral registers 3-13 3.2.6.7 line control register (ports 2fbh & 3fbh) this register controls certain line characteristics. table 3-10 interrupt id bit logic id1 id0 priority interrupt type 1 1 1 receiver line status 1 0 2 received data ready 0 1 3 transmitter holding register empty 0 0 4 modem status 7 0 field word length bit dlab sb sp eps pe stp wlb1 wlb0 default 00000000 bit name r/w function 7 dlab r/w divisor latch access bit 0: 1 = enable divisor programming 0 = disable divisor programming 6 sb r/w set break bit 5 sp r/w stuck parity: 1 = enable 4 eps r/w even parity: 1 = enable 3 pe r/w parity enable: 1 = enable 2 stp r/w stop bit: 0 = 1 stop bit 1 = 1.5 stop bits if word length is 5 (2 stop bits if word length is 6, 7, or 8) 1 wlb1 r/w word length, bit 1 0 wlb0 r/w word length, bit 0 table 3-11 word length bit logic bit 1 bit 0 word length (bits) 00 5 01 6 10 7 11 8
3-14 pc/at peripheral registers 3.2.6.8 modem control register (ports 2fch & 3fch) this register governs certain modem characteristics. 3.2.6.9 line status register (ports 2fdh & 3fdh) this register reports the line status. this is a read-only register unless bit 1 of the control a register at index 48h is 1, in which case it becomes read/write. 7 0 bit (reserved) loop out2 out1 rts dtr default 00000000 bit name r/w function 7? r/w (reserved) 4 loop r/w local loop-back diagnostic test: 1 = enable loop 0 = normal operation 3 out2 r/w out2 (must be 1 to enable interrupts) 2 out1 r/w out1 1 rts r/w r ts : 1 = enable r ts 0 dtr r/w dtr : 1 = enable dtr note: if loop-back is enabled, interrupts from the uart are disabled and the four modem control signals (dtr , r ts , out1 , and out2 ) are internally connected to dsr , cts , ri , and dcd , respectively. 7 0 bit (reserved) temt thre bi fe pe oe dr default 00000000 bit name r/w function 7 r (reserved) 6 temt r 1 = transmitter empty 5 thre r 1 = transmitter holding register empty 4 bi r 1 = break interrupt 3 fe r 1 = framing error 2 pe r 1 = parity error 1 oe r 1 = overrun error 0 dr r 1 = data ready
pc/at peripheral registers 3-15 3.2.6.10 modem status register (ports 2feh & 3feh) this register reports more status information. 3.2.6.11 scratch pad register (ports 2ffh & 3ffh) this is a general-purpose register. 7 0 bit rlsd ri dsr cts drlsd teri ddsr dcts default 00000000 bit name r/w function 7 rlsd r status of dcd from modem 6 ri r status of ri from modem 5 dsr r status of dsr from modem 4 cts r status of cts from modem 3 drlsd r delta data carrier detect 2 teri r trailing edge of ring indicator from modem 1 ddsr r delta data set ready 0 dcts r delta clear to send 7 0 field i/o port number default 00000000 bit name r/w function 7? r/w scratch data
3-16 pc/at peripheral registers 3.2.7 real-time clock n counts seconds, minutes, and hours of the day n counts days of the week, date, month, and year n binary or bcd representation of time, calendar, and alarm n 12?4-hr clock with a . m . and p . m . in 12-hr mode n daylight-savings-time option n automatic end-of-month recognition n automatic leap-year compensation n 14 bytes of clock and control registers n 114 bytes of general-purpose ram n three interrupts are separately software maskable and testable n time-of-day alarm (once per second to once per day) n periodic interrupt rates from 122 ms to 500 ms n end-of-clock update cycle the real-time clock (rtc) block in the ?lansc310 microcontroller is compatible with the motorola mc146818a device used in pc/at systems. this block consists of a time-of-day clock with an alarm and a 100-yr calendar. the clock/calendar can be represented in binary or bcd, has a programmable periodic interrupt, and has 114 bytes of static user ram. the rtc block is powered from the same power as the core logic. the block also has 10 registers for time, calendar, and alarm data and four general-pur- pose registers. the interrupt signal from the rtc is an active-low signal and is routed to interrupt-request line 8. 3.2.7.1 addressing the rtc is accessed using 8-bit-wide i/o cycles at addresses 70h and 71h. the contents of the rtc registers and its 114 bytes of ram are accessed in an indexed fashion. table 3-12 real-time clock port r/w register name description 070h w rtc index address index (pointer) to the data in the rtc 071h r/w rtc index data data stored in the rtc note: bit 7 of the nmi/rtc index register, i/o address 70h, is the enmi control bit. if this bit is set, nmis are masked. bits 6? of this register are used to access the rtc registers and ram.
pc/at peripheral registers 3-17 3.2.7.2 rtc registers the rtc registers and ram are indexed with the address map shown in table 3-13 on page 3-17. 3.2.7.2.1 register a (rtc index 0ah) table 3-13 rtc register summary rtc index function 0 seconds 1 seconds alarm 2 minutes 3 minutes alarm 4 hours 5 hours alarm 6 day of week 7 date of month 8 month 9 year 10 register a 11 register b 12 register c 13 register d 14?27 user-static ram 7 0 bit uip dv2 dv1 dv0 rs3 rs2 rs1 rs0 default (unde?ed) bit name function 7 uip update in progress: this bit is a status bit that can be polled by a program to indicate that the clock/calendar is currently being updated. 6? dv2?v0 divider chain: these bits select the time-base frequency for the clock. (table 3-15 on page 3-18 describes the operation of these bits.) 3? rs3?s0 rate selection: these bits select the periodic interrupt rate. (table 3-14 on page 3-18 describes the operation of these bits.)
3-18 pc/at peripheral registers table 3-14 register a periodic-interrupt rate-selection bits (32.768 khz) rs3 rs2 rs1 rs0 periodic interrupt rate 0000 (none) 0001 (reserved) 0010 (reserved) 0011 122.070 m s 0100 244.141 m s 0101 488.281 m s 0110 976.562 m s 0111 1.953125 ms 1000 3.90625 ms 1001 7.8125 ms 1010 15.625 ms 1011 31.25 ms 1100 62.5 ms 1101 125 ms 1110 250 ms 1111 500 ms table 3-15 register a time-base divider-chain bits dv2 dv1 dv0 time base frequency 0 1 0 32.768 khz (at-compatible setting) note: other combinations of divider bits are used for test purposes only.
pc/at peripheral registers 3-19 3.2.7.2.2 register b (rtc index 0bh) 3.2.7.2.3 register c (rtc index 0ch) 3.2.7.2.4 register d (rtc index 0dh) 7 0 bit set pie aie uie sqwe dm 24/12 dse default (unde?ed) bit name function 7 set set time: this bit prevents the time calendar from being incremented. 6 pie programmable interrupt enable: this bit enables the periodic interrupt ?g (pf) in register c to generate an interrupt request. 5 aie alarm interrupt enable: this bit enables the alarm ?g (af) in register c to generate an interrupt request. 4 uie update-ended enable: this bit enables the update-ended ?g (uf) in register c to generate an interrupt request. 3 sqwe square wave enable: this bit is not used. 2 dm data mode: this bit selects between bcd and binary formats for the time and calendar: 1 = bcd 0 = binary 1 24/12 hour format: this bit establishes the format of the hours byte for 24- or 12-hr time: 1 = 24-hr clock 0 = 12-hr clock 0 dse daylight savings time: this bit enables the clock to automatically account for daylight savings time adjustments: 1 = enabled 0 = disabled 7 0 bit irqf pf af uf (reserved) default 0000 bit name function 7 irqf interrupt request flag: this bit is read only and is set when any of these register c bits are set: pf, af, or uf. 6 pf periodic interrupt flag: this bit is read only and is set according to the rate set by the rs3?s0 bits in register a. 5 af alarm flag: this bit is read only and is set when the current item matches the alarm time. 4 uf update-ended flag: this bit is read only and is set at the end of each time-update cycle. 3? (reserved) 7 0 bit vrt (reserved) default 0000000 bit name function 7 vrt valid ram and time: this bit is read only and is reset when the resin pin is asserted low. this bit is set by reading register d. 6? (reserved)
3-20 pc/at peripheral registers 3.3 miscellaneous pc/at-compatible port registers 3.3.1 xt keyboard data register (port 060h) the xt keyboard data register is located at i/o address 060h. this read-only, 8-bit regis- ter holds the data from the xt keyboard. the xt keyboard is enabled by setting bit 3 (xtkbden) of the pmu control 3 register at index adh. while the xt keyboard is enabled, this register is cleared by setting bit 7 of the port b register. 3.3.2 port b register (port 061h) port b is an at-standard, miscellaneous-feature control register which is located at i/o address 061h. the lower 4 bits of the 8-bit register are read/write control bits that enable or disable nmi check-condition sources and sound-generation features. the most signi? cant 4 bits are read-only bits that return status and diagnostic information. bit 4 (rfd) toggles state with every refresh. bit 5 (t2out) follows the state of the timer 2 output. bit 6 (iochck) is set upon detection of a channel check and is cleared upon the reading of this register. bits 6 and 7 of this register have alternate functions when the xt keyboard feature is enabled by setting bit 3 of index adh. 7 0 field data received from the xt keyboard default 00000000 7 0 bit (reserved) iochck t2out rfd eic (reserved) spkd t2g default 00000000 bit name r/w function 7 (alt.) w r/w (reserved) 1 = clear xt keyboard data register 6 (alt.) iochck kbclken r r/w i/o channel check 1 = enable kbclk as an output 5 t2out r timer 2 output 4 rfd r refresh detected 3 eic w/r enable i/o channel check: 0 = enable 2 (reserved) 1 spkd w/r speaker data: 1 = enable speaker output 0 t2g w/r timer 2 gate (speaker): 1 = speaker gated on
pc/at peripheral registers 3-21 3.3.3 nmi/rtc index address register (port 070h) both the pmu and the i/o channel check are possible sources for the generation of an nmi to the internal cpu. the master nmi enable function can inhibit any nmis from reaching the cpu regardless of the state of the individual source enables. the nmi enable bit in this register is a write-only bit and it has an active-0 sense. the default value for the nmi enable bit is 1, which inhibits nmi generation. a write to this i/o address must always be followed by a write to?r read from?ddress 71h to ensure proper operation of the rtc. 3.3.4 rtc index data register (port 071h) this register is used to read data from, or write data to, the real-time clock indexed by bits 6? in i/o register 070h. 3.3.5 port 92 (port 092h) this is the system control port a register and is for at compatibility. 7 0 bit enmi rtc index address bits 6? default 10000000 bit name r/w function 7 enmi w 0 = enable nmi 1 = disable nmi (default) 6? w rtc index address note: for a de?ition of the index values, see real-time clock, on page 3-16. 7 0 bit rtc data bits 7? default 00000000 bit name r/w function 7? r/w rtc data bits 7? 7 0 bit (reserved) alta20 hotrst default 00000000 bit name r/w function 7? r (reserved) 1 alta20 w a20 gate control: 1 = a20 is cpua20 0 = a20 is 0 if bit 0 of index 6fh is 0 and the a20gate pin is 0 0 hotrst w a low-to-high transition in this bit causes cpurst to be asserted for 16 cpu clock cycles.
configuration registers 4-1 chapter 4 configuration registers the ?lansc310 microcontrollers con?uration registers are de?ed as those registers that control the four central functions: n general control n isa bus control n memory control unit (mcu) n power management unit (pmu) these registers provide a uniform method of accessing the device's control and con?u- ration parameters. the parameters are mapped into bits and bit ?lds contained in logical groupings of 8-bit registers. most of the con?uration registers are set to a default value by a system reset condition. the default values have been speci?d to allow the device to correctly execute bios code out of the local flash memory or rom upon exiting the reset state.
4-2 configuration registers 4.1 configuration register overview there are two basic types of registers that are used to con?ure the ?lansc310 micro- controller: n port registers n index registers 4.1.1 port registers the con?uration port registers are located in i/o space. they are addressed directly by the ?lansc310 microcontroller. the con?uration port registers are listed in table 4-1 on page 4-2. for a description of each port register, see ?on?uration port registers on page 4-11. the con?uration address register points to the index register to be read or written when a data-register i/o cycle occurs. the con?uration data register is used to read or write the index register. reading the con?uration data register reads the contents of the index register. writing a value to the con?uration data register writes that value to the index register. the contents of the con?uration address register is static relative to multiple data regis- ter reads and writes. this allows for read-modify-write operations. the address of the index register is written to the con?uration address register, and then the data is read, modi?d, and written back to the con?uration data register without rewriting the con?- uration address register. 4.1.2 index registers the con?uration index registers are located in a separate internal memory space. they are addressed indirectly by the ?lansc310 microcontroller. for a description of each index register, see ?on?uration index registers on page 4-11. 4.1.2.1 mandatory settings default settings of the microcontroller guarantee that code can be fetched and executed out of the rom bios address space and that the con?uration index registers can be accessed upon power up. several of the con?uration index registers contain bits that must be written soon after reset with their speci?d values in order for the device to oper- ate as speci?d. these mandatory bits control things such as chip-test modes, interrupt mapping, smi generation, and cycle timings. table 4-1 con?uration port registers port register 022h con?uration address 023h con?uration data
configuration registers 4-3 setting of these mandatory bits must be done prior to enabling any other functions of the device. this chapter describes the con?uration registers that are indexed off i/o port 22h. however, table 4.2, ?andatory con?uration bit settings on page 4-3 shows a few registers that are accessed through port 3d4h and 3d5h. port 3d4h registers are described in the section ?us initialization registers on page 3-2. the ?andatory con- ?uration bit settings table shows the following: n mandatory bit settings indexed off port 3d4h for any speed operation n mandatory bit settings indexed off port 22h for any speed operation n additional mandatory bit settings indexed off port 22h for 33-mhz system speed n mandatory bit settings indexed off port 22h for 33-mhz and 25-mhz system speed table 4-2 mandatory con?uration bit settings mandatory bit settings accessed through ports 3d4h and 3d5h index bit settings (x = don? care) 12h read (see note 1) 20h 0 0 0 0 0 0 x x (see note 2) 19h 0 0 1 x x x x x 1. port 3d4h, index 12h, must be read before indexes 20h and 19h are written. 2. note: port 3d4h, index 20h, selects the parallel port base i/o address through bits 0 and 1. this selection can only be made before index 19h is written. mandatory bit settings indexed off port 22h index bit settings (x = don? care) 0fh 1 1 1 1 1 1 1 1 44h 1 0 x x 0 0 0 x 51h x x x x 0 0 x x 60h x x 0 x 0 x x x 62h 0 x x x x x x x 63h x x x x x x 0 x 64h 1 0 0 x 1 1 x x 66h x x x x x x 1 x 6ah 0 0 0 0 0 0 0 0 6bh 0 x x 1 x x x x 70h x x x x x x x 1 74h x x 0 0 x x x x 80h x x x x 0 x x x 8fh 1 x x 0 x x x x 93h 0 0 0 0 0 0 0 0 9dh 0 1 0 0 0 0 0 0
4-4 configuration registers 4.1.2.2 recommended settings table 4-3 on page 4-4 contains recommended bit settings that improve the performance of the microcontroller under certain conditions. these bits should be set in addition to the bits listed in table 4-2 on page 4-3. 4.1.3 configuring the ?lansc310 microcontroller when you are ready to con?ure the ?lansc310 microcontroller, you program its con?- uration index registers according to your systems requirements. the following sections identify the index registers?nd the bits within them?hat you use to control different aspects of the ?lansc310 microcontroller. mandatory bit settings indexed off port 22h index bit settings (x = don? care) b1h x x 0 x x x x x b4h x 1 x x x x x x bah x x x 1 x x x x additional 33-mhz bit settings indexed off port 22h index bit settings (x = don? care) 60h x 0 0 x 0 x x x 62h 0 x x 1 x x x x 63h x 1 1 x x x 0 x 65h x x 1 x x x x x additional 33-mhz and 25-mhz bit settings indexed off port 22h index bit settings (x = don? care) 6bh 0 x x 1 x 0 x x table 4-3 recommended con?uration bit settings index bit settings (x = don? care) 44h x x x 1 x x x x 63h x x x x 1 1 x x a7h x x 1 1 x x x 0 table 4-2 mandatory con?uration bit settings (continued)
configuration registers 4-5 4.1.3.1 to control the pc/at bus and its timing 4.1.3.2 to determine the bus con?uration 4.1.3.3 to control cpu and pc/at compatibility 4.1.3.4 to control the speed of the cpu see and program bits ?ontrol a register (index 48h) on page 4-18 2 ?ommand delay register (index 60h) on page 4-20 2? ?/o wait state register (index 61h) on page 4-22 5? ?ms memory wait state 1 register (index 62h) on page 4-23 3? ?ait state control register (index 63h) on page 4-25 3? ?iscellaneous 5 register (index b3h) on page 4-65 6, 5?, and 2 ?om con?uration 3 register (index b8h) on page 4-67 7? see and program bits ?emory con?uration 1 register (index 66h) on page 4-28 6? see and program bits ?arallel port address select register (port 3d4h, index 20h) on page 3-3 1? ?ort 92 (port 092h) on page 3-21 1? ?ontrol a register (index 48h) on page 4-18 1 ?iscellaneous 2 register (index 6bh) on page 4-30 0 ?iscellaneous 1 register (index 6fh) on page 4-34 1? ?ontrol b register (index 77h) on page 4-42 7? ?art clock enable register (index 92h) on page 4-49 0 see and program bits ?/o wait state register (index 61h) on page 4-22 6 ?iscellaneous 2 register (index 6bh) on page 4-30 2 ?ontrol b register (index 77h) on page 4-42 3 ?uto low-speed control register (index 9fh) on page 4-51 3? ?mu control 3 register (index adh) on page 4-60 1? ?mu control 2 register (index afh) on page 4-61 5 ?unction enable 2 register (index b1h) on page 4-62 4?
4-6 configuration registers 4.1.3.5 to control direct memory accesses 4.1.3.6 to enable interrupts and specify how they are mapped 4.1.3.7 to set up memory mapping (mms windows) see and program bits ?/o wait state register (index 61h) on page 4-22 7 ?iscellaneous 1 register (index 6fh) on page 4-34 3? ?unction enable 1 register (index b0h) on page 4-61 3 see and program bits ?ontrol b register (index 77h) on page 4-42 7? ?mi/smi enable register (index 82h) on page 4-43 7? ?mi mms upper page register (index a9h) on page 4-57 7 ?mu control 3 register (index adh) on page 4-60 6 ?unction enable 1 register (index b0h) on page 4-61 5? ?irq con?uration register (index b2h) on page 4-64 7? see and program bits ?om con?uration 1 register (index 65h) on page 4-27 6 ?msa address extension 1 register (index 67h) on page 4-29 7? ?ms address extension 1 register (index 6ch) on page 4-31 7? ?ms address register (index 6dh) on page 4-31 7? ?ms address extension 2 register (index 6eh) on page 4-33 7? ?msa device 1 register (index 71h) on page 4-36 7? ?msa device 2 register (index 72h) on page 4-37 7? ?msb device register (index 73h) on page 4-38 7? ?msb control register (index 74h) on page 4-39 1?
configuration registers 4-7 4.1.3.8 to set up the system dram 4.1.3.9 to set up the parallel port 4.1.3.10 to set up the uart see and program bits ?iscellaneous 4 register (index 44h) on page 4-15 4 ?ommand delay register (index 60h) on page 4-20 6 ?ms memory wait state 1 register (index 62h) on page 4-23 4 ?ait state control register (index 63h) on page 4-25 6? ?ersion register (index 64h) on page 4-26 4 and 1? ?om con?uration 1 register (index 65h) on page 4-27 7 and 5? ?emory con?uration 1 register (index 66h) on page 4-28 4? ?hadow ram enable 1 register (index 68h) on page 4-29 7? ?hadow ram enable 2 register (index 69h) on page 4-30 7? ?iscellaneous 1 register (index 6fh) on page 4-34 7? ?iscellaneous 6 register (index 70h) on page 4-35 0 ?mu control 1 register (index a7h) on page 4-56 1? ?unction enable 2 register (index b1h) on page 4-62 7? ?iscellaneous 5 register (index b3h) on page 4-65 3 ?unction enable 3 register (index b4h) on page 4-66 7 ?emory con?uration 2 register (index b9h) on page 4-69 7? ?iscellaneous 3 register (index bah) on page 4-70 2 see and program bits ?arallel port address select register (port 3d4h, index 20h) on page 3-3 1? ?unction enable 1 register (index b0h) on page 4-61 2? ?iscellaneous 3 register (index bah) on page 4-70 4? see and program bits ?ontrol a register (index 48h) on page 4-18 1 ?ontrol b register (index 77h) on page 4-42 7? ?art clock enable register (index 92h) on page 4-49 0
4-8 configuration registers 4.1.3.11 to set up the general-purpose and pmc pins 4.1.3.12 to control the clocks (phase-locked loops) see and program bits ?iscellaneous 6 register (index 70h) on page 4-35 6 ?msb control register (index 74h) on page 4-39 2 ?ower control 1 register (index 80h) on page 4-42 6 and 2 ?ower control 2 register (index 81h) on page 4-43 6 and 2 ?eneral-purpose i/o 0 register (index 89h) on page 4-46 7? ?eneral-purpose i/o control register (index 91h) on page 4-47 7? ?eneral-purpose i/o 2 register (index 94h) on page 4-49 7? ?eneral-purpose i/o 3 register (index 95h) on page 4-49 7? ?eneral-purpose i/o 1 register (index 9ch) on page 4-51 7? ?pu status 0 register (index a3h) on page 4-54 0 ?pu status 1 register (index a4h) on page 4-55 3 ?ower control 3 register (index abh) on page 4-58 7? ?ower control 4 register (index ach) on page 4-59 7? ?mu control 3 register (index adh) on page 4-60 3 ?irq con?uration register (index b2h) on page 4-64 7? and 3? ?iscellaneous 3 register (index bah) on page 4-70 4? see and program bits ?/o wait state register (index 61h) on page 4-22 6 ?iscellaneous 2 register (index 6bh) on page 4-30 2 ?msb control register (index 74h) on page 4-39 3 ?ontrol b register (index 77h) on page 4-42 3 ?ower control 1 register (index 80h) on page 4-42 7 ?ower control 2 register (index 81h) on page 4-43 7 and 3 ?lock control register (index 8fh) on page 4-47 2? ?art clock enable register (index 92h) on page 4-49 0 ?uto low-speed control register (index 9fh) on page 4-51 3? ?mu control 3 register (index adh) on page 4-60 3? ?mu control 2 register (index afh) on page 4-61 5 and 0 ?unction enable 1 register (index b0h) on page 4-61 6 and 3 ?unction enable 2 register (index b1h) on page 4-62 4? ?iscellaneous 3 register (index bah) on page 4-70 3
configuration registers 4-9 4.1.3.13 to control power management activities and events 4.1.3.14 to determine power management status see and program bits ?iscellaneous 4 register (index 44h) on page 4-15 0 ?io address register (index 45h) on page 4-15 7? ?io timer register (index 46h) on page 4-16 7? and 3? ?rive timer register (index 47h) on page 4-17 7? ?iscellaneous 6 register (index 70h) on page 4-35 5 ?msb control register (index 74h) on page 4-39 7? and 3 ?ctivity mask 1 register (index 75h) on page 4-40 7? ?ctivity mask 2 register (index 76h) on page 4-41 7? ?ower control 1 register (index 80h) on page 4-42 7? and 2 ?ower control 2 register (index 81h) on page 4-43 7? and 3? ?oftware mode control register (index 88h) on page 4-45 2? ?/o activity address 0 register (index 8ch) on page 4-46 7? ?/o activity address 1 register (index 8dh) on page 4-46 7? ?emory write activity lower boundary register (index 9ah) on page 4-50 7? and 0 ?emory write activity upper boundary register (index 9bh) on page 4-50 7? and 2? ?ower control 3 register (index abh) on page 4-58 7? ?ower control 4 register (index ach) on page 4-59 7? ?mu control 3 register (index adh) on page 4-60 4 ?mu control 2 register (index afh) on page 4-61 0 see and program bits ?esume status register (index 09h) on page 4-12 5? ?ctivity status 1 register (index a0h) on page 4-53 7? ?ctivity status 2 register (index a1h) on page 4-53 7? ?mu status 1 register (index a2h) on page 4-54 7 ?pu status 0 register (index a3h) on page 4-54 6? ?pu status 1 register (index a4h) on page 4-55 7 and 2? ?mi/smi control register (index a5h) on page 4-56 7? ?iscellaneous 5 register (index b3h) on page 4-65 1?
4-10 configuration registers 4.1.3.15 to control the power management state timers 4.1.3.16 to map rom accesses and control rom cycles 4.1.3.17 to control smis and determine status see and program bits ?igh-speed to low-speed timer register (index 83h) on page 4-44 7? ?ow-speed to doze timer register (index 84h) on page 4-44 7? ?oze to sleep timer register (index 85h) on page 4-44 7? ?leep to suspend timer register (index 86h) on page 4-44 7? ?uspend to off timer register (index 87h) on page 4-45 7? ?mu control 2 register (index afh) on page 4-61 7? see and program bits ?ms memory wait state 2 register (index 50h) on page 4-19 6 and 2? ?om con?uration 2 register (index 51h) on page 4-20 1? ?ommand delay register (index 60h) on page 4-20 7 and 4 ?ms memory wait state 1 register (index 62h) on page 4-23 6? ?om con?uration 1 register (index 65h) on page 4-27 3? ?iscellaneous 5 register (index b3h) on page 4-65 6? and 2 ?om con?uration 3 register (index b8h) on page 4-67 7? see and program bits ?/o timeout register (index 40h) on page 4-12 2? ?mi enable register (index 41h) on page 4-13 4? ?mi i/o status register (index 42h) on page 4-14 3? ?mi status register (index 43h) on page 4-14 6? ?ait state control register (index 63h) on page 4-25 7 ?ersion register (index 64h) on page 4-26 7 ?iscellaneous 2 register (index 6bh) on page 4-30 0 ?mi/smi enable register (index 82h) on page 4-43 7? ?mu status 1 register (index a2h) on page 4-54 7? ?mi/smi control register (index a5h) on page 4-56 7? ?mi mms upper page register (index a9h) on page 4-57 7? ?mi mms page register (index aah) on page 4-57 7? ?mu control 3 register (index adh) on page 4-60 6 ?unction enable 1 register (index b0h) on page 4-61 5? ?iscellaneous 5 register (index b3h) on page 4-65 1?
configuration registers 4-11 4.2 configuration port registers 4.2.1 configuration address register (port 022h) this register contains the index of the con?uration index register being programmed. 4.2.2 configuration data register (port 023h) this register is used to read data from, or write data to, the register pointed to by the con- ?uration address register. 4.3 configuration index registers these registers are listed in index numerical order. see appendix a for an alphabetical list by register name. 4.3.1 reserved registers (index 00-07h) these index locations are reserved. 4.3.2 resume mask register (index 08h) when set, bits 5? of this register mask the corresponding function. bit 5 clearing this bit allows the internal uart ring indicate to wake up the system. bit 4 clearing this bit allows the internal rtc to wake up the system. bit 3 clearing this bit allows a rising edge on irq4 (whether internally or externally generated) to wake up the system. irq4 should be held at 1 until the wake-up is complete. bit 2 clearing this bit allows a rising edge on irq3 (whether internally or externally generated) to wake up the system. irq3 should be held at 1 until the wake-up is complete. 7 0 field index of con?uration index register default 00000000 7 0 field data transferred to/from con?uration index register default 00000000 7 0 bit (reserved) rimsk irq8msk irq4msk irq3msk (reserved) default 00000000 bit name r/w function 7-6 r/w (reserved) 5 rimsk r/w if this bit is 0, a ring-in input can wake up the system. 4 irq8msk r/w if this bit is 0, irq8 can wake up the system. 3 irq4msk r/w if this bit is 0, irq4 can wake up the system. 2 irq3msk r/w if this bit is 0, irq3 can wake up the system. 1-0 r/w (reserved)
4-12 configuration registers 4.3.3 resume status register (index 09h) a 1 in any bit in this register indicates that the corresponding function caused the system to wake up. 00h must be written to this register to clear it. 4.3.4 reserved registers (indexes 0a-0eh) these index locations are reserved. 4.3.5 reserved register (index 0fh) this index location is reserved and must be initialized to ffh at boot time. 4.3.6 reserved registers (indexes 10?9h) these index locations are reserved. 4.3.7 i/o timeout register (index 40h) this register may be used with the smi enable register at index 41h to determine if an i/o-device access generates an smi. if a bit in this register is 0 and the corresponding bit in the smi enable register is 1, the next i/o access to that device causes an smi. in addition, writing a 0 to a bit enables an smi to occur on the next i/o access to that device. writing a 1 has no effect. for more information, see ?ccesses to powered-down device smi on page 1-29. 7 0 bit (reserved) prim_ri irq8 irq4 irq3 (reserved) default 00000000 bit name r/w function 7? r/w (reserved) 5 prim_ri r/w system was awakened by a ring-in from the internal uart 4 irq8 r/w system was awakened by irq8 3 irq4 r/w system was awakened by irq4 2 irq3 r/w system was awakened by irq3 1-0 r/w (reserved) 7 0 bit (reserved) piotoltch fdtoltch hdtoltch default 00000000 bit name r/w function 7? r/w (reserved) 2 piotoltch r/w 1 = pio access caused the smi; pio smis are masked until this bit is 0 1 fdtoltch r/w 1 = floppy disk drive access caused the smi; ?ppy-disk-drive smis are masked until this bit is 0 0 hdtoltch r/w 1 = hard disk drive access caused the smi; hard-disk-drive smis are masked until this bit is 0
configuration registers 4-13 4.3.8 smi enable register (index 41h) this register is used to control the generation of individual smis upon access to a speci? i/o location. a value of 1 in each bit enables an smi to be generated when the corre- sponding device is accessed. a value of 0 disables smi generation for the corresponding device. for bits 2?, an smi is generated on the ?st access to the i/o address after one of the following events occur: n the smi is enabled n the timer expires n the corresponding bit in the i/o timeout register at index 40h is 0 n the pmu enters sleep or suspend mode i/o accesses that occur before the timer expires cause the timer to be reloaded. the hard-disk-drive and ?ppy-disk-drive timers are also reloaded when bit 0 of the miscellaneous 4 register at index 44h is 1 and irq14 (hard disk drive) or irq6 (?ppy disk drive) is asserted. for more information, see ?ccesses to powered-down device smi on page 1-29. 7 0 bit (reserved) rtcsmien kbsmien enpio enfd enhd default 00000000 bit name r/w function 7? r/w (reserved) 4 rtcsmien r/w 1 = enable smi generation on access to i/o address 07xh 3 kbsmien r/w 1 = enable smi generation on 8042 access 2 enpio r/w 1 = enable smi generation on pio access 1 enfd r/w 1 = enable smi generation on ?ppy-disk-drive (3f0?f7h) access 0 enhd r/w 1 = enable smi generation on hard-disk-drive (1f0?f7h) access
4-14 configuration registers 4.3.9 smi i/o status register (index 42h) this register contains the states of the cpu bus when an smi is generated. software can read this register to determine the type of bus cycle executed. this register is updated when an i/o access generates an smi that corresponds to bits 4? of the smi enable register at index 41h or an extsmi pin event. 4.3.10 smi status register (index 43h) this register contains the status of smi sources. a 1 in any of these bits indicates that the corresponding device generated an smi. the programmer may clear this register by writ- ing to it; the data written is irrelevant. for information on the smi enables that correspond to the bits in this register, see ?mi enable register (index 41h) on page 4-13 and ?mu control 3 register (index adh) on page 4-60. 7 0 bit (reserved) iow ior bhe a0 default 00000000 bit name r/w function 7? (reserved) 3 iow r state of io w when smi was generated: 1 = io w was active 2 ior r state of ior when smi was generated: 1 = ior was active 1 bhe r state of bhe when smi was generated: 0 = bhe was active 0 a0 r state of address bit 0 when smi was generated 7 0 bit (reserved) irq0smi pmcsmi rtcsmien kbsmien piosmi fdsmi hdsmi default 00000000 bit name r/w function 7 r/w (reserved, must be 0) 6 irq0smi r/w 1 = irq0 requested an smi 5 pmcsmi r/w 1 = pmu mode change, bl event, or sus /res event requested an smi 4 rtcsmien r/w 1 = smi generation on access to address 07xh 3 kbsmien r/w 1 = smi generation on 8042 access 2 piosmi r/w 1 = pio requested an smi 1 fdsmi r/w 1 = floppy disk drive requested an smi 0 hdsmi r/w 1 = hard disk drive requested an smi
configuration registers 4-15 4.3.11 miscellaneous 4 register (index 44h) this register is used to clear the hard-disk-drive timer and control data propagation through the ?lansc310 microcontroller. 4.3.12 pio address register (index 45h) this register is used to program pio address bits a9?2. the pio base address can be anywhere in the range 000?fch and should be programmed on an address boundary that corresponds to the address-decode range speci?d in bits 6 and 7 of the pio timer register at index 46h. 7 0 bit (reserved) disden (reserved) irqen default 00000000 bit name r/w function 7 w (reserved?ust be 1) 6 w (reserved?ust be 0) 5 w (reserved) 4 disden w 1 = data read from dram via a cpu cycle is propagated only through the ?lansc310 microcontrollers cpu core 0 = the dram data is propagated to all internal ?lansc310 microcontroller cores 3? w (reserved?ust be 0) 0 irqen w if 1, irq14 (hard disk drive) or irq6 (?ppy disk drive) causes the hard-disk- drive timer or ?ppy-disk-drive timer to reload (see index 47h) 7 0 field i/o address bits 9? bit a9 a8 a7 a6 a5 a4 a3 a2 default 00000000 bit name r/w function 7 a9 r/w pio address bit a9 6 a8 r/w pio address bit a8 5 a7 r/w pio address bit a7 4 a6 r/w pio address bit a6 3 a5 r/w pio address bit a5 2 a4 r/w pio address bit a4 1 a3 r/w pio address bit a3 0 a2 r/w pio address bit a2
4-16 configuration registers 4.3.13 pio timer register (index 46h) this register is used to program the pio time-out period. if no accesses are made to the i/o range speci?d by the pio address register at index 45h in the time-out period speci- ?d here, pmc1 is driven low. this line may be used to control power to an external device. bits 6 and 7 of this register may be used to mask bits 2? of the pio address reg- ister. for more information, see ?mi enable register (index 41h) on page 4-13. 7 0 field decode range timer setting bit ra1 ra0 (reserved) piot3 piot2 piot1 piot0 default 00000000 bit name r/w function 7 ra1 r/w pio decode range bit 1 6 ra0 r/w pio decode range bit 0 5? r/w (reserved) 3 piot3 r/w pio timer setting bit 3 2 piot2 r/w pio timer setting bit 2 1 piot1 r/w pio timer setting bit 1 0 piot0 r/w pio timer setting bit 0 table 4-4 pio timer setting logic piot3 piot2 piot1 piot0 period 0000 128 ms 0001 256 ms 0010 512 ms 00111 s 01002 s 01014 s 01108 s 011116 s 100032 s 100164 s 1010 128 s 1011 256 s 1100 512 s 1101 1024 s 1110 2048 s 1111 4096 s
configuration registers 4-17 4.3.14 drive timer register (index 47h) this register is used to program the hard-disk-drive and ?ppy-disk-drive time-out peri- ods. if no accesses are made to the hard-disk drive in the time-out period speci?d here, pmc4 is driven low. if no accesses are made to the ?ppy disk drive in the time-out period speci?d here, pmc0 is driven low. these lines may be used to control power to those drives. for more details concerning the use of this register, see ?mi enable regis- ter (index 41h) on page 4-13. table 4-5 pio address range decode logic ra1 ra0 pio address range 0 0 4 bytes 0 1 8 bytes 1 0 16 bytes 1 1 32 bytes 7 0 field floppy-disk-drive timer setting hard-disk-drive timer setting bit fdt3 fdt2 fdt1 fdt0 hdt3 hdt2 hdt1 hdt0 default 00000000 bit name r/w function 7 fdt3 w floppy-disk-drive timer setting bit 3 6 fdt2 w floppy-disk-drive timer setting bit 2 5 fdt1 w floppy-disk-drive timer setting bit 1 4 fdt0 w floppy-disk-drive timer setting bit 0 3 hdt3 w hard-disk-drive timer setting bit 3 2 hdt2 w hard-disk-drive timer setting bit 2 1 hdt1 w hard-disk-drive timer setting bit 1 0 hdt0 w hard-disk-drive timer setting bit 0
4-18 configuration registers 4.3.15 control a register (index 48h) this register contains miscellaneous control functions. bit 1 of this register converts the uart control register at port 3fdh from read only (the default) to read/write, which is compatible with the 16450. bit 2 causes the memr and memw signals to be disabled during on-board memory cycles. 4.3.16 reserved registers (indexes 49?fh) these index locations are reserved. table 4-6 hard-disk-drive and floppy-disk-drive timer setting bit logic hdt3 or fdt3 hdt2 or fdt2 hdt1 or fdt1 hdt0 or fdt0 period 0000 128 ms 0001 256 ms 0010 512 ms 00111 s 01002 s 01014 s 01108 s 011116 s 100032 s 100164 s 1010 128 s 1011 256 s 1100 512 s 1101 1024 s 1110 2048 s 1111 4096 s 7 0 bit (reserved) discmd lsrwcntl (reserved) default 00000000 bit name r/w function 7? w (reserved) 2 discmd w 1 = disable memr and memw signals on the bus during on-board memory cycles 1 lsrwcntl w 1 = enable uart line status register (index 3fdh) for writes (retains 16450 compatibility) 0 w (reserved)
configuration registers 4-19 4.3.17 mms memory wait state 2 register (index 50h) this register is used to specify the command delay and the number of wait states used with 8-bit accesses to rom dos. the reference clock is the internal version of sysclk. for more information, see ?ait states and command delays on page 2-14. table 4-7 on page 4-19 and table 4-8 on page 4-19 describe the wait states and com- mand delays for 8-bit rom dos accesses (rom accessed via doscs ). 7 0 field rdosws bit (reserved) rdoscmdl (reserved) rdoswsen rdosws1 rdosws0 default 00000000 bit name r/w function 7 w reserved 6 rdoscmdl w romdos (rom accessed by doscs ) command delay 5-3 w reserved 2 rdoswsen w 8-bit rom dos (rom accessed by doscs ) wait state enable 1 rdosws1 w 8-bit rom dos (rom accessed by doscs ) wait states, bit 1 0 rdosws0 w 8-bit rom dos (rom accessed by doscs ) wait states, bit 0 table 4-7 rom-dos wait-state select logic enfstrdos bit 7 of index b8h rdoswsen rdosws1 rdosws0 rom wait states 0100 4 0101 3 0110 2 0111 1 0 0 x x controlled by bits 1? in index 62h 1 x x x controlled by bits 6? in index b8h table 4-8 rom-dos command-delay select logic rdoswsen bit 2 of index 50h rdoscmdl bit 6 of index 50h 8mcd bit 2 of index 60h rom-dos memory-cycle command delay 0 x 0 1 sysclk cycle 0 x 1 0.5 sysclk cycle 1 1 x 0 delay
4-20 configuration registers 4.3.18 rom configuration 2 register (index 51h) this register is used to enable rom bios accesses and to set the rom-dos accesses as 16-bit transfers. for more information on con?uration bits for rom-bios accesses, see ?om con?uration 1 register (index 65h) on page 4-27. 4.3.19 reserved registers (indexes 52?fh) these index locations are reserved. 4.3.20 command delay register (index 60h) this register is used to select different command delays for isa-bus i/o cycles and wait states for both mms and non-mms memory cycles. 7 0 bit (reserved) romdos16 enroma default 00000000 bit name r/w function 7? w (reserved?ust be 0) 1 romdos16 w 1 = select 16-bit rom-dos con?uration 0 enroma w 1 = r omcs is active when the address is within 0a0000?affffh 7 0 field iocd bit romws1 refws (reserved) romws0 (reserved) 8mcd iocd1 iocd0 default 00000000 bit name r/w function 7 romws1 w rom-bios, non-mms-cycle wait states, bit 1 6 refws w refresh wait states. must be 0 for 33-mhz operation. 5 w (reserved?ust be 0) 4 romws0 w rom-bios, non-mms-cycle wait states, bit 0 3 w (reserved?ust be 0) 2 8mcd w 8-bit isa memory cycle command delay 1 iocd1 w 8-bit isa i/o cycle command delay, bit 1 0 iocd0 w 8-bit isa i/o cycle command delay, bit 0 table 4-9 8-bit isa i/o access command delay iocd1 iocd0 sysclk cycles delayed 0 0 1 (default) 012 1 x 0.5 note: acts on addresses from 100h to 3ffh.
configuration registers 4-21 table 4-10 8-bit isa memory access command delay 8mcd sysclk cycles delayed 0 1 (default) 1 0.5 table 4-11 rom-bios wait states romws1 romws0 number of wait cycles 103 012 1 1 (invalid combination) 0 0 3 (default) note: these bits control the number of wait cycles for rom-bios accesses only during non-mms cycles. during mms cycles to rom bios, the number of wait cycles is controlled by the settings for isa memory cycles found in the mms memory wait state select 1 register, index 62h. table 4-12 refresh-cycle wait states refws sysclk cycles in refresh delay 12 0 3 (default) note: for 33-mhz operation, this bit must be 0.
4-22 configuration registers 4.3.21 i/o wait state register (index 61h) this register de?es the number of wait states for i/o cycles to different i/o addresses. it also contains the control for forcing the cpu clock to run at 9.2 mhz from the low-speed pll during high-speed pll mode. the number of wait states selected in this register must be greater than the bus i/o com- mand delay speci?d in the command delay register at index 60h. after reset, the cpu clock runs at low speed (9.2 mhz). write a 1 to bit 6 of this register to enable the cpu to run at high speed (the speed set by bits 4? of the function enable 2 register at index b1h). the cpu only runs in high speed during dram accesses, local bus accesses, fast rom accesses, and while idle. isa accesses cause the cpu clock to switch to 9.2 mhz, thus saving power. 7 0 field iows hdws fdws bit dmamms speed iows1 iows0 hdws1 hdws0 fdws1 fdws0 default 00000000 bit name r/w function 7 dmamms w 0 = disable mms during dma 1 = enable mms in dma cycle 6 speed w cpu clock speed select: 0 = force all operations to be low speed (9.2 mhz) 1 = high speed 5 iows1 w other bus i/o wait states, bit 1 4 iows0 w other bus i/o wait states, bit 0 3 hdws1 w hard-disk-drive wait states, bit 1 2 hdws0 w hard-disk-drive wait states, bit 0 1 fdws1 w floppy-disk-drive wait states, bit 1 0 fdws0 w floppy-disk-drive wait states, bit 0 table 4-13 floppy-disk-drive wait states fdws1 fdws0 sysclk cycles delayed 0 0 5 (default) 014 103 112 note: acts on addresses from 3f0?f7h.
configuration registers 4-23 4.3.22 mms memory wait state 1 register (index 62h) this register de?es the wait states for different memory accesses. table 4-16 on page 4-24 describes 8-bit isa memory-cycle wait states. these bits also apply for any 8-bit cycles to rom bios addressed through the mms map where memcs16 is not asserted. table 4-14 hard-disk-drive wait states hdws1 hdws0 sysclk cycles delayed 0 0 5 (default) 014 103 112 note: acts on addresses from 1f0?f7h. table 4-15 general bus i/o wait states iows1 iows0 sysclk cycles delayed 0 0 5 (default) 014 103 112 note: acts on addresses from 100h to 3ffh, except 3f0?f7h, 1f0?f7h, and the mms i/o base address. 7 0 field 16bmws 8bmws bit (reserved) nfrdosen nfromen misout 16bmws1 16bmws0 8bmws1 8bmws0 default 00000000 bit name r/w function 7 w (reserved?ust be 0) 6 nfrdosen w 1 = enable writes to devices selected by doscs 5 nfromen w 1 = enable writes to devices selected by r omcs pin 4 misout w page mode bank miss and time-out wait state select (see table 4-19 on page 4-25): 0 = 3 wait states 1 = 5 wait states this bit must be 1 for 33-mhz operation. 3 16bmws1 w wait states bit 1 for 16-bit isa memory cycles 2 16bmws0 w wait states bit 0 for 16-bit isa memory cycles 1 8bmws1 w wait states bit 1 for 8-bit isa memory cycles 0 8bmws0 w wait states bit 0 for 8-bit isa memory cycles
4-24 configuration registers table 4-17 on page 4-24 describes 16-bit isa memory-cycle wait states. the following applies for cycles when either memcs16 is asserted or rom dos is set up for 16-bit cycles. table 4-16 8-bit isa memory-cycle wait states 8bmws1 8bmws0 sysclk cycles delayed 0 0 (default) 5 014 103 112 table 4-17 16-bit isa memory-cycle wait states 16bmws1 16bmws0 sysclk cycles delayed 0 0 (default) 4 013 102 111
configuration registers 4-25 4.3.23 wait state control register (index 63h) this register de?es the wait states for miscellaneous accesses. bit 7 this bit controls the size of the mms page that is mapped to address 60000h when an smi occurs. refer to ?mi mms page register (index aah) on page 4-57. 7 0 bit smmsize bkmiss fcycwait1 fcycwait0 intiowait 16iowait (reserved) shutd default 00000000 bit name r/w function 7 smmsize w smm memory range select: 0 = 16 kbyte 1 = 64 kbyte 6 bkmiss w set dram bank-miss wait state in page mode 5 fcycwait1 w set dram ?st-cycle wait state in page mode 4 fcycwait0 w set dram ?st-cycle wait state in page mode. see table 4-18 on page 4-25. 3 intiowait w this bit controls the number of wait states for i/o addresses to internal cores: 0 = 4 wait states 1 = 2 wait states 2 16iowait w wait state select for 16-bit i/o cycles 0 = 4 wait cycles 1 = 3 wait cycles 1 w (reserved?ust be 0) 0 shutd w wait state select for shutdown cycle: 0 = 16 cycles 1 = 32 cycles note: bits 5 and 6 of this register must be set for 33-mhz operation. see also bit 5 of index 65h. table 4-18 dram first cycle wait state select logic pfws bit 5 of index 65h fcycwait1 bit 5 fcycwait0 bit 4 dram first-cycle wait states in page mode 0 x 0 (default) 1 0x12 10x2 1 1 x (33 mhz) 3 table 4-19 dram bank miss wait state select logic bkmiss bit 6 misout bit 4 of index 62h dram bank-miss wait states in page mode x 0 (default) 3 014 1 1 (33 mhz) 5
4-26 configuration registers 4.3.24 version register (index 64h) this register displays whether smi is active. in addition, bits 2? of this register can be read to determine the major stepping level information (processor version). bits 6? hold the minor stepping (additional revision) information. writing to this register selects the refresh rate for dram and enables enhanced page mode when using 512-kbit 8-bit drams. 4.3.24.1 read functions 4.3.24.2 write functions bits 1? these bits are not reset when exiting micro power off mode. the refresh interval shown in table 4-21 on page 4-27 is selected only if bits 1? of the pmu control 1 register at index a7h are both 0. 7 0 field minor level major level bit rsmi default 00000000 bit name r/w function 7 rsmi r smi active 6? r minor step level (revision) 2? r major step level (revision) table 4-20 read version stepping level decode revision minor level bits 6 5 4 3 major level bits 2 1 0 a 0 0 0 0 0 0 1 b0?2 0 0 0 0 0 1 0 b3 0 0 0 1 0 1 0 7 0 bit (reserved) epmode (reserved) refsel1 refsel0 default 00000000 bit name r/w function 7 w (reserved?ust be 1) 6? w (reserved?ust be 0) 4 epmode w enable enhanced page mode when the value of bits 4? of index 66h is 010b and bit 7 of index b4h is 0. bit 0 of index 66h must also be 1. 3? w (reserved?ust be 1) 1 refsel1 w refresh interval select, bit 1 0 refsel0 w refresh interval select, bit 0
configuration registers 4-27 4.3.25 rom configuration 1 register (index 65h) this register is used to con?ure rom accesses. bits 3? are used to set the size of the bios rom that is connected to the r omcs signal. when each bit is 1, the r omcs sig- nal goes active during accesses within the corresponding address range. r omcs must be disabled for regions that are shadowed. bit 4 enables shadow ram and bit 7 is the shadow ram write protect. this bit must be 1 to allow writes to the shadow ram. bit 6 this bit enables/disables all windows in mmsa. if this bit is 0, all windows are disabled. if this bit is 1, each window can be individually enabled/disabled via bit 7 of the appropriate page register. bit 5 this bit must be 1 for 33-mhz operation. bit 0 read-modify-write operations must invert bit 0 if bit 0 is not to be changed by the operation. table 4-21 refresh interval select logic refsel1 refsel0 refresh interval (cycles per second) 0 0 8192 0 1 10922 1 0 16384 1 1 32768 7 0 bit disw enmmsa pfws shadow enromc enromd enrome enromf default 00000000 bit name r/w function 7 disw r/w 0 = shadow ram write protect 6 enmmsa r/w 1 = mmsa enable 5 pfws r/w page mode ?st-cycle wait state select (see index 63h, bit 5, and table 4-18 on page 4-25) 4 shadow r/w 1 = shadow ram enable 3 enromc r/w 1 = r omcs is active when address is within range 0c0000?cffffh. 2 enromd r/w 1 = r omcs is active when address is within range 0d0000?dffffh. 1 enrome r/w 1 = r omcs is active when address is within range 0e0000?effffh. 0 enromf r/w 0 = r omcs is active when address is within range 0f0000?fffffh. this bit reads back the inverse of what was written to it. writing a 0 enables access.
4-28 configuration registers 4.3.26 memory configuration 1 register (index 66h) this register controls memory size and operating mode. bus con?uration is determined by the state of the dtr and r ts pins at reset. software may read the latched state of sout as it was sampled at reset. sout may be used as a general-purpose latched input. 7 0 field ms bit soutl cfg0 cfg1 ms2 ms1 ms0 (reserved) mod0 default 00000000 bit name r/w function 7 soutl r latched state of sout at reset 6 cfg0 r latched state of r ts at reset 5 cfg1 r latched state of dtr at reset 4 ms2 r/w memory bank con?uration, bit 2 3 ms1 r/w memory bank con?uration, bit 1 2 ms0 r/w memory bank con?uration, bit 0 1 r/w (reserved?ust be 1) 0 mod0 r/w dram enhanced page mode is enabled when this bit is set (see index 64h, bit 4) table 4-22 bus option status table bus selected cfg1 cfg0 reserved 0 x 2x clock local bus 1 0 maximum isa 1 1 table 4-23 memory con?uration (dram) bit 7 of index b4h ms2 ms1 ms0 total memory bank 0 bank 1 0 0 0 1 1 mbyte 1 mbyte 0 0 1 0 2 mbyte 1 mbyte 1 mbyte 0 0 1 1 2 mbyte 2 mbyte 0 1 0 0 4 mbyte 2 mbyte 2 mbyte 0 1 0 1 8 mbyte 8 mbyte 0 1 1 0 16 mbyte 8 mbyte 8 mbyte note: see indexes b4h and b1h for additional dram con?urations.
configuration registers 4-29 4.3.27 mmsa address extension 1 register (index 67h) this is the mmsa register containing address-extension bits 21?2 for pages 4?. bit 1 of the mmsb control register at index 74h must be 1 prior to writing this register. 4.3.28 shadow ram enable 1 register (index 68h) this register controls the shadow-ram mapping range. mapping is disabled by default. 7 0 field page 7 page 6 page 5 page 4 bit e7a22 e7a21 e6a22 e6a21 e5a22 e5a21 e4a22 e4a21 default 00000000 bit name r/w function 7 e7a22 r/w mmsa page 7 address extension bit 22 6 e7a21 r/w mmsa page 7 address extension bit 21 5 e6a22 r/w mmsa page 6 address extension bit 22 4 e6a21 r/w mmsa page 6 address extension bit 21 3 e5a22 r/w mmsa page 5 address extension bit 22 2 e5a21 r/w mmsa page 5 address extension bit 21 1 e4a22 r/w mmsa page 4 address extension bit 22 0 e4a21 r/w mmsa page 4 address extension bit 21 7 0 bit sdcf sd8b sd47 sd03 sccf sc8b sc47 sc03 default 00000000 bit name r/w function 7 sdcf r/w enable shadow ram at range 0dc000?dffffh 6 sd8b r/w enable shadow ram at range 0d8000?dbfffh 5 sd47 r/w enable shadow ram at range 0d4000?d7fffh 4 sd03 r/w enable shadow ram at range 0d0000?d3fffh 3 sccf r/w enable shadow ram at range 0cc000?cffffh 2 sc8b r/w enable shadow ram at range 0c8000?cbfffh 1 sc47 r/w enable shadow ram at range 0c4000?c7fffh 0 sc03 r/w enable shadow ram at range 0c0000?c3fffh
4-30 configuration registers 4.3.29 shadow ram enable 2 register (index 69h) this register controls the shadow-ram mapping range. mapping is disabled by default. 4.3.30 reserved register (index 6ah) this register is reserved and must be 00h. 4.3.31 miscellaneous 2 register (index 6bh) this register contains several miscellaneous control bits. 7 0 bit sfcf sf8b sf47 sf03 secf se8b se47 se03 default 00000000 bit name r/w function 7 sfcf r/w enable shadow ram at range 0fc000?fffffh 6 sf8b r/w enable shadow ram at range 0f8000?fbfffh 5 sf47 r/w enable shadow ram at range 0f4000?f4000h 4 sf03 r/w enable shadow ram at range 0f0000?f3fffh 3 secf r/w enable shadow ram at range 0ec000?effffh 2 se8b r/w enable shadow ram at range 0e8000?ebfffh 1 se47 r/w enable shadow ram at range 0e4000?e7fffh 0 se03 r/w enable shadow ram at range 0e0000?e3fffh 7 0 bit (reserved) cpu_idle (reserved) a20smi default 00000000 bit name r/w function 7 w (reserved?ust be 0) 6? r (reserved) 4 r/w (reserved?ust be 1) 3 r (reserved) 2 cpu_idle w selects whether cpu idle cycles are dynamically switched to use the high- speed clock frequency: 0 = high speed 1 = low speed (9.2 mhz) this bit must be 0 for 33-mhz and 25-mhz operation. 1 (reserved) 0 a20smi w controls gate a20 during smi access: 1 = a20 propagates 0 = a20 low
configuration registers 4-31 4.3.32 mms address extension 1 register (index 6ch) this is the mms register that contains address-extension bit 23 for all pages. bits 3? provide mapped address-extension bit 23 for both mmsa and mmsb (pages 0?). before programming this register, software must select the region to program (i.e., mmsa or mmsb). this selection is performed via bit 1 of the mmsb control register at index 74h. 4.3.33 mms address register (index 6dh) this register selects the base i/o addresses and page addresses. bits 3? provide selection of page-register i/o addresses for both mmsa (pages 0?) and mmsb (pages 0?). these page registers get mapped at different i/o locations as listed in table 4-24 on page 4-32. once the i/o address spaces for these registers are programmed, writes to these address spaces store mapped address-extension bits 20?4 for the windows in mmsa and mmsb as indicated in table 4-25 on page 4-32. 7 0 bit e7a23 e6a23 e5a23 e4a23 e3a23 e2a23 e1a23 e0a23 default 00000000 bit name r/w function 7 e7a23 r/w mmsa page 7 address extension bit 23 6 e6a23 r/w mmsa page 6 address extension bit 23 5 e5a23 r/w mmsa page 5 address extension bit 23 4 e4a23 r/w mmsa page 4 address extension bit 23 3 e3a23 r/w mmsa/mmsb page 3 address extension bit 23 2 e2a23 r/w mmsa/mmsb page 2 address extension bit 23 1 e1a23 r/w mmsa/mmsb page 1 address extension bit 23 0 e0a23 r/w mmsa/mmsb page 0 address extension bit 23 7 0 field base address page address bit emba3 emba2 emba1 emba0 emio3 emio2 emio1 emio0 default 00000000 bit name r/w function 7 emba3 r/w mmsa base address, bit 3 6 emba2 r/w mmsa base address, bit 2 5 emba1 r/w mmsa base address, bit 1 4 emba0 r/w mmsa base address, bit 0 3 emio3 r/w mmsa/b page register(s) i/o address, bit 3 2 emio2 r/w mmsa/b page register(s) i/o address, bit 2 1 emio1 r/w mmsa/b page register(s) i/o address, bit 1 0 emio0 r/w mmsa/b page register(s) i/o address, bit 0
4-32 configuration registers bits 7? provide selection of starting addresses of memory windows in mmsa (pages 0?). these windows get mapped at different system-memory address locations as listed in table 4-26 on page 4-33. once the system-memory address spaces for these windows are programmed (i.e., the base address is selected) and the page register i/o addresses are selected, the software can program the page registers. software must also program the other address extension registers (mms address extension 2 register at index 6eh, mmsa address extension 1 register at index 67h, and mms address extension 1 register at index 6ch) before a page in the mmsa or the mmsb is enabled. see the rom con?uration 1 register at index 65h and the mmsb control register at index 74h to enable the mmsa and the mmsb. note that the mmsb base address is ?ed at 0a0000h and is not under software control. table 4-24 mmsa/b page register i/o addresses bit page register i/o address 3210 page 0 page 1 page 2 page 3 page 4 page 5 page 6 page 7 0000 208h 2208h 4208h 6208h 8208h a208h c208h e208h 0001 218h 2218h 4218h 6218h 8218h a218h c218h e218h 0101 258h 2258h 4258h 6258h 8258h a258h c258h e258h 0110 268h 2268h 4268h 6268h 8268h a268h c268h e268h 1010 2a8h 22a8h 42a8h 62a8h 82a8h a2a8h c2a8h e2a8h 1011 2b8h 22b8h 42b8h 62b8h 82b8h a2b8h c2b8h e2b8h 1110 2e8h 22e8h 42e8h 62e8h 82e8h a2e8h c2e8h e2e8h table 4-25 page register contents description bit name r/w function 7 pageen r/w 0 = page disable 1 = page enable 6 ea20 r/w mmsa/b translate address bit a20 5 ea19 r/w mmsa/b translate address bit a19 4 ea18 r/w mmsa/b translate address bit a18 3 ea17 r/w mmsa/b translate address bit a17 2 ea16 r/w mmsa/b translate address bit a16 1 ea15 r/w mmsa/b translate address bit a15 0 ea14 r/w mmsa/b translate address bit a14
configuration registers 4-33 : 4.3.34 mms address extension 2 register (index 6eh) this is the mms register containing address-extension bits 21?2 for pages 0?. bits 7? provide mapped address-extension bits 22?1 for both the mmsa and the mmsb (pages 0?). before programming this register, software must select the region to program (i.e., mmsa or mmsb). this selection is performed via bit 1 of the mmsb control register at index 74h. table 4-26 mmsa base addresses bit base address 7654 page 0 page 1 page 2 page 3 page 4 page 5 page 6 page 7 0000 c0000h c4000h c8000h cc000h d0000h d4000h d8000h dc000h 0001 c4000h c8000h cc000h d0000h d4000h d8000h dc000h e0000h 0010 c8000h cc000h d0000h d4000h d8000h dc000h e0000h e4000h 0011 cc000h d0000h d4000h d8000h dc000h e0000h e4000h e8000h 0100 d0000h d4000h d8000h dc000h e0000h e4000h e8000h ec000h 0101 d4000h d8000h dc000h e0000h e4000h e8000h ec8000h f0000h 7 0 field page 3 page 2 page 1 page 0 bit e3a22 e3a21 e2a22 e2a21 e1a22 e1a21 e0a22 e0a21 default 00000000 bit name r/w function 7 e3a22 r/w mmsa/mmsb page 3 address extension bit 22 6 e3a21 r/w mmsa/mmsb page 3 address extension bit 21 5 e2a22 r/w mmsa/mmsb page 2 address extension bit 22 4 e2a21 r/w mmsa/mmsb page 2 address extension bit 21 3 e1a22 r/w mmsa/mmsb page 1 address extension bit 22 2 e1a21 r/w mmsa/mmsb page 1 address extension bit 21 1 e0a22 r/w mmsa/mmsb page 0 address extension bit 22 0 e0a21 r/w mmsa/mmsb page 0 address extension bit 21
4-34 configuration registers 4.3.35 miscellaneous 1 register (index 6fh) this register is used to control isa and mcu functions. mms memory range provides a method for disabling on-board memory accesses when directly accessing memory (non-mms cycles). the programmed mms memory range is subtracted from the amount of on-board memory con?ured by bits 4? of the memory con?uration 1 register at index 66h or bits 7? of the function enable 2 register at index b1h. if the programmed mms memory range is equal to or greater than the con?- ured amount of on-board memory, then on-board memory is disabled and all memory cycles are transferred on the isa bus. 7 0 field mmsz bit mmsz3 mmsz2 mmsz1 mmsz0 mrdly dmws rescpu gatea20 default 00000000 bit name r/w function 7 mmsz3 r/w mms memory range, bit 3 6 mmsz2 r/w mms memory range, bit 2 5 mmsz1 r/w mms memory range, bit 1 4 mmsz0 r/w mms memory range, bit 0 3 mrdly memr delay: 1 = delay memr by 1 dmack cycle 0 = no delay for memr 2 dmws r/w dma wait states: 1 = 2 wait cycles 0 = 1 wait cycle 1 rescpu r/w cpu reset: a low-to-high transition in this bit automatically resets the cpu. the reset lasts for 16 proclk cycles. 0 gatea20 r/w a20 gate control: 1 = a20 is cpua20 0 = a20 is 0 if bit 0 of port 92h and the a20gate pin are also 0 table 4-27 mms memory range select logic bit 7654 mms memory range bit 7654 mms memory range 0000 no mms 1000 8 mbyte 0001 1 mbyte 1001 9 mbyte 0010 2 mbyte 1010 10 mbyte 0011 3 mbyte 1011 11 mbyte 0100 4 mbyte 1100 12 mbyte 0101 5 mbyte 1101 13 mbyte 0110 6 mbyte 1110 14 mbyte 0111 7 mbyte 1111 15 mbyte
configuration registers 4-35 for example, assume that 8 mbyte of dram have been con?ured as on-board main memory. if the user desires to have 10 mbyte of linearly addressed dos rom, then bits 7? of the miscellaneous 1 register at index 6fh should be programmed to 0010b. this allows all accesses in the range 000000?fffffh to transfer to dram and all accesses in the range 600000?fffffh to be isa bus transfers. for more information, see ?om-dos memory on page 2-8. 4.3.36 miscellaneous 6 register (index 70h) this register is used to control mcu and pmu functions. bit 5 setting this bit is equivalent to asserting the acin pin, except that the bl4 ?l0 pins are not gated with this bit. therefore, the bl4 ?l0 pins can still change the state of the pmu. 7 0 bit (reserved) pgp0dir sacin (reserved) default 00000000 bit name r/w function 7 r/w (reserved) 6 pgp0dir r/w pgp0 pin direction: 0 = input 1 = output 5 sacin r/w software acin input: 1 = pmu behaves as if acin pin was asserted 4? r/w (reserved) 0 r/w (reserved?ust be 0)
4-36 configuration registers 4.3.37 mmsa device 1 register (index 71h) this register selects the peripheral device that each mmsa page controls. 7 0 field page 3 device page 2 device page 1 device page 0 device bit emdp31 emdp30 emdp21 emdp20 emdp11 emdp10 emdp01 emdp00 default 00000000 bit name r/w function 7 emdp31 r/w mmsa page 3 device type, bit 1 6 emdp30 r/w mmsa page 3 device type, bit 0 5 emdp21 r/w mmsa page 2 device type, bit 1 4 emdp20 r/w mmsa page 2 device type, bit 0 3 emdp11 r/w mmsa page 1 device type, bit 1 2 emdp10 r/w mmsa page 1 device type, bit 0 1 emdp01 r/w mmsa page 0 device type, bit 1 0 emdp00 r/w mmsa page 0 device type, bit 0 page 3 device select page 2 device select bit 76 selected device bit 54 selected device 0 0 mms rom dos 0 0 mms rom dos 0 1 mms on-board main memory 0 1 mms on-board main memory 1 0 reserved 1 0 reserved 1 1 mms bios 1 1 mms bios page 1 device select page 0 device select bit 32 selected device bit 10 selected device 0 0 mms rom dos 0 0 mms rom dos 0 1 mms on-board main memory 0 1 mms on-board main memory 1 0 reserved 1 0 reserved 1 1 mms bios 1 1 mms bios
configuration registers 4-37 4.3.38 mmsa device 2 register (index 72h) bits of this register select the peripheral device that each mmsa page controls. 7 0 field page 7 device page 6 device page 5 device page 4 device bit emdp71 emdp70 emdp61 emdp60 emdp51 emdp50 emdp41 emdp40 default 00000000 bit name r/w function 7 emdp71 r/w mmsa page 7 device type, bit 1 6 emdp70 r/w mmsa page 7 device type, bit 0 5 emdp61 r/w mmsa page 6 device type, bit 1 4 emdp60 r/w mmsa page 6 device type, bit 0 3 emdp51 r/w mmsa page 5 device type, bit 1 2 emdp50 r/w mmsa page 5 device type, bit 0 1 emdp41 r/w mmsa page 4 device type, bit 1 0 emdp40 r/w mmsa page 4 device type, bit 0 page 7 device select page 6 device select bit 76 selected device bit 54 selected device 0 0 mms rom dos 0 0 mms rom dos 0 1 mms on-board main memory 0 1 mms on-board main memory 1 0 reserved 1 0 reserved 1 1 mms bios 1 1 mms bios page 5 device select page 4 device select bit 32 selected device bit 10 selected device 0 0 mms rom dos 0 0 mms rom dos 0 1 mms on-board main memory 0 1 mms on-board main memory 1 0 reserved 1 0 reserved 1 1 mms bios 1 1 mms bios
4-38 configuration registers 4.3.39 mmsb device register (index 73h) bits of this register select the peripheral device that each mmsb page controls. 7 0 field page 3 device page 2 device page 1 device page 0 device bit emdp31 emdp30 emdp21 emdp20 emdp11 emdp10 emdp01 emdp00 default 00000000 bit name r/w function 7 emdp31 r/w mmsb page 3 device type, bit 1 6 emdp30 r/w mmsb page 3 device type, bit 0 5 emdp21 r/w mmsb page 2 device type, bit 1 4 emdp20 r/w mmsb page 2 device type, bit 0 3 emdp11 r/w mmsb page 1 device type, bit 1 2 emdp10 r/w mmsb page 1 device type, bit 0 1 emdp01 r/w mmsb page 0 device type, bit 1 0 emdp00 r/w mmsb page 0 device type, bit 0 page 3 device select page 2 device select bit 76 selected device bit 54 selected device 0 0 mms rom dos 0 0 mms rom dos 0 1 mms on-board main memory 0 1 mms on-board main memory 1 0 reserved 1 0 reserved 1 1 mms bios 1 1 mms bios page 1 device select page 0 device select bit 32 selected device bit 1 0 selected device 0 0 mms rom dos 0 0 mms rom dos 0 1 mms on-board main memory 0 1 mms on-board main memory 1 0 reserved 1 0 reserved 1 1 mms bios 1 1 mms bios
configuration registers 4-39 4.3.40 mmsb control register (index 74h) this register controls mcu and pmu functions. bit 7 if bit 7 = 0 and acin = 0, the pmu transitions to suspend mode when bl4 = 0. bit 6 if bit 6 = 0 and acin = 0, the pmu transitions to sleep mode when bl2 = 0. this bit has no effect on whether an smi for bl2 is generated. it also does not have an effect on the status read at the cpu status 0 register at index a3h. bit 1 because the mmsa and the mmsb use the same i/o address for the page registers and address extension registers for pages 0?, this bit selects either the mmsa or the mmsb for programming. in other words, this bit directs the i/o address to either the mmsa or the mmsb. if this bit is 1, an i/o cycle accesses the mmsa; otherwise, an i/o cycle accesses the mmsb. bit 0 this bit enables/disables all windows in the mmsb. if this bit is 0, all windows are disabled. if this bit is 1, each window can be individually enabled/disabled via bit 7 of the appropriate page register. 7 0 bit nenlb4 nenlb2 (reserved) enpmcirq0 pgp1dir mmsabsel enmmsb default 0000 0 000 bit name r/w function 7 nenlb4 r/w 1 = bl4 going active does not cause the pmu to transition to suspend mode. 6 nenlb2 r/w 1 = bl2 going active does not cause the pmu to transition to sleep mode. 5 r/w (reserved?ust be 0) 4 r/w (reserved?ust be 0) 3 enpmcirq0 r/w enable irq0 active in doze mode: 1 = enabled. if this bit is 1 and bit 0 of the pmu control 2 register at index afh is 0, the cpuclk signal is active while irq0 is high in doze mode. if this bit is 1 and bit 0 of the pmu control 2 register is 1, the cpuclk signal remains active for an additional 64 refresh cycles after irq0 is deasserted. 2 pgp1dir r/w pgp1 pin direction: 0 = input 1 = output 1 mmsabsel r/w mmsa and mmsb select bit: 0 = mmsb 1 = mmsa 0 enmmsb r/w enable mmsb: 1 = enabled
4-40 configuration registers 4.3.41 activity mask 1 register (index 75h) this register is used in conjunction with the activity mask 2 register at index 76h and the resume mask register at index 08h to enable which activities are detected by the pmu. each of these bits masks out the corresponding activity. a 1 means the activity is masked; a 0 means it is counted. for information on status and enabling acin activity, see ?ctivity status 1 register (index a0h) on page 4-53 and ?mu control 3 register (index adh) on page 4-60. bit 7 int means that all interrupts from irq2 to irq15 can serve as pmu activity that causes a pmu transition from either low-speed pll or doze mode to high-speed pll mode. this bit does not allow the above stated irq levels to wake up the processor from sleep, suspend, or off mode. irq3, irq4, and irq8 can be programmed individually by the resume mask register at index 08h to act as wake-up events. unmasking these events allows their occurrence to wake up the system from sleep, suspend, or off mode into high-speed pll mode. bit 6 bit 4 of the pmu control 3 register at index adh must also be set to permit acin going active to count as activity. 7 0 bit int acin mms kb drq3 drq2 drq1 drq7?rq5 default 0000000 0 bit name r/w function 7 int r/w interrupt recognition: 1 = disabled 0 = enabled 6 acin r/w ac adapter input or low-to-high transition of bit 5 of the miscellaneous 6 register at index 70h recognition: 1 = disabled 0 = enabled 5 mms r/w mms cycle activity recognition: 1 = disabled 0 = enabled 4 kb r/w keyboard interrupt (irq1) activity recognition: 1 = disabled 0 = enabled 3 drq3 r/w drq3 activity recognition: 1 = disabled 0 = enabled 2 drq2 r/w drq2 activity recognition: 1 = disabled 0 = enabled 1 drq1 r/w drq1 activity recognition: 1 = disabled 0 = enabled 0 drq7?rq5 r/w drq7?rq5 activity recognition: 1 = disabled 0 = enabled note: activities are not detected during the execution of smis or nmis.
configuration registers 4-41 bits 6 and 3? these activities also wake up the system from sleep, suspend, or off mode into high-speed pll mode. bit 4 unlike other irqs, irq1 activity cannot be masked by the 8259 pic. 4.3.42 activity mask 2 register (index 76h) this register is used in conjunction with the activity mask 1 register at index 75h and the resume mask register at index 08h to enable which activities are detected by the pmu. each of these bits masks the corresponding activity when set. for more information on activity status reporting, see ?ctivity status 2 register (index a1h) on page 4-53. 7 0 bit pmw vd pio1 pio0 com hd fd lpt default 00000000 bit name r/w function 7 pmw r/w memory address range (de?ed in the memory write activity lower and upper boundary registers at indexes 9ah and 9bh) recognition: 1 = disabled 0 = enabled 6 vd r/w video memory write recognition: 1 = disabled 0 = enabled 5 pio1 r/w i/o address range (de?ed in the i/o activity address 1 register at index 8dh) recognition: 1 = disabled 0 = enabled 4 pio0 r/w i/o address range (de?ed in the i/o activity address 0 register at index 8ch) recognition: 1 = disabled 0 = enabled 3 com r/w com1?om2 read/write recognition: 1 = disabled 0 = enabled 2 hd r/w hard disk drive read/write recognition: 1 = disabled 0 = enabled 1 fd r/w floppy disk drive read/write recognition: 1 = disabled 0 = enabled 0 lpt r/w lpt1?pt3 read/write recognition: 1 = disabled 0 = enabled note: activities are not detected during smi or nmi execution.
4-42 configuration registers 4.3.43 control b register (index 77h) this register controls various general functions. bit 6 if the ?lansc310 microcontroller is in local bus mode, program the pirq con?uration register at index b2h so it does not con?ct with the irq selection for the internal uart. bit 3 this bit is only useful if bit 6 of the i/o wait state register at index 61h is 1, which puts the cpu clock into high-speed pll mode. otherwise, the cpu clock is always operating at the low-speed pll frequency. this function is not dependent on any activity (see ?uto low-speed control register (index 9fh) on page 4-51). 4.3.44 reserved registers (indexes 78?fh) these index locations are reserved. 4.3.45 power control 1 register (index 80h) this register controls the pmc2 output pin in high-speed pll mode, low-speed pll mode, and doze mode. it also enables/disables the low-speed pll and video pll in doze mode. 7 0 bit uart_ir4 uart_ir3 uart_iop uart_en autlow (reserved) default 00000000 bit name r/w function 7 uart_ir4 r/w set internal uart irq to irq4 6 uart_ir3 r/w set internal uart irq to irq3 5 uart_iop r/w 0 = set internal uart i/o address to 3f8?ffh 1 = set internal uart i/o address to 2f8?ffh 4 uart_en r/w 1 = enable internal uart 3 autlow r/w 1 = enable auto low-speed 2? r/w (reserved) 7 0 bit 0clk_doz dz2 (reserved) fo2 (reserved) default 00000000 bit name r/w function 7 0clk_doz r/w 1 = low-speed pll and video pll are shut down in doze mode 6 dz2 r/w 1 = state of pmc2 pin in doze mode 5? r/w (reserved) 3 r/w (reserved?ust be 0) 2 fo2 r/w 1 = state of pmc2 pin in high-speed pll and low-speed pll modes 1? r/w (reserved) note: the state of pmc2 after power-on is low. when the bit is 0, the corresponding pmc output is low. for details, see chapter 1, ?ower management.
configuration registers 4-43 4.3.46 power control 2 register (index 81h) this register activates the pmc2 output pin in sleep, suspend, and off modes. it also enables/disables the low-speed pll and video pll in sleep, suspend, and off modes. 4.3.47 nmi/smi enable register (index 82h) this register is used to enable the generation of nmis or smis during certain conditions, such as mode changes or battery-low conditions. by default, nmis and smis are dis- abled. the choice of smis or nmis is selected by bit 7 of the smi mms upper page regis- ter at index a9h. 7 0 bit 0clk_sus su2 0clk_slp sp2 default 00000000 bit name r/w function 7 0clk_sus r/w 1 = low-speed pll and video pll are shut down in suspend and off modes 6 su2 r/w 1 = state of pmc2 pin in suspend and off modes 5? r/w (reserved) 3 0clk_slp r/w 1 = low-speed pll and video pll are shut down in sleep mode 2 sp2 r/w 1 = state of pmc2 pin in sleep mode 1? r/w (reserved) note: the state of pmc2 after power-on is low. when the bit is 0, the corresponding pmc output is low. for details, see chapter 1, ?ower management. 7 0 bit bl3 bl2 bl1 sus slp dz on resu default 00000000 bit name r/w function 7 bl3 r/w 1 = battery low warning 3 generates an nmi or smi 6 bl2 r/w 1 = battery low warning 2 generates an nmi or smi 5 bl1 r/w 1 = battery low warning 1 generates an nmi or smi 4 sus r/w 1 = pmu generates nmi or smi before entering off mode from suspend mode 3 slp r/w 1 = pmu generates nmi or smi before entering suspend mode from sleep mode 2 dz r/w 1 = pmu generates nmi or smi before entering sleep mode from doze mode 1 on r/w 1 = pmu generates nmi or smi before entering doze mode from low-speed pll mode 0 resu r/w 1 = sus /res pin will generate nmi or smi note: bit 7 of at-compatible port 70h must be 0 for nmis to occur.
4-44 configuration registers 4.3.48 high-speed to low-speed timer register (index 83h) this read/write register is used to program the time-out period from high-speed pll mode to low-speed pll mode. the minimum period is 1?12 s. the maximum period is 15.94 s. a value of 00h disables the pmu timer. if any activities are detected during the timer counting period, the pmu timer is reset to 00h automatically. note: the timer granularity can be changed to 1?6 s by setting bit 6 of the pmu control 2 register at index afh. 4.3.49 low-speed to doze timer register (index 84h) this read/write register is used to program the time-out period from low-speed pll mode to doze mode. the minimum period is 1?6 s; the maximum is 63.75 s. a value of 00h disables the pmu timer. if any activities are detected during the timer counting period, the pmu timer is reset to 00h automatically and returns to high-speed pll mode. note: the timer granularity can be changed to 1? s by setting bit 7 of the pmu control 2 register at index afh. 4.3.50 doze to sleep timer register (index 85h) this read/write register is used to program the time-out period from doze mode to sleep mode. the minimum period is 4 s; the maximum is 1024 s. a value of 00h disables the pmu timer. if any activities are detected during the timer counting period, the pmu timer is reset to 00h automatically and returns to high-speed pll mode. 4.3.51 sleep to suspend timer register (index 86h) this read/write register is used to program the time-out period from sleep mode to sus- pend mode. the minimum period is 1?6 s; the maximum is 16 s. a value of 00h disables the pmu timer. if a wake-up or the resume key is detected during the timer counting period, the pmu timer is reset to 00h automatically and the system returns to high-speed pll mode. 7 0 field time-out period in multiples of 1?12 s or 1?6 s default 00000000 7 0 field time-out period in multiples of 1?6 s or 1? s default 00000000 7 0 field time-out period in multiples of 4 s default 00000000 7 0 field time-out period in multiples of 1?6 s default 00000000
configuration registers 4-45 4.3.52 suspend to off timer register (index 87h) this read/write register is used to program the time-out period from suspend mode to off mode. the minimum period is 1 min; the maximum is 256 min. a value of 00h disables the pmu timer. if a wake-up or the resume key is detected during the timer counting period, the counter is reset to 00h automatically and the system returns to high-speed pll mode. 4.3.53 software mode control register (index 88h) this register allows software to force the system into a particular mode. 7 0 field time-out period in multiples of 1 min default 00000000 7 0 field spc bit spc2 spc1 spc0 default 00000000 bit name r/w function 7? w (reserved) 2 spc2 w software command control bit 2 1 spc1 w software command control bit 1 0 spc0 w software command control bit 0 note: do not force the pmu from a clock-stopped state (sleep, suspend, or off mode) into the low-speed pll mode or doze mode. instead, force the pmu into high-speed pll mode. this ensures that internal ?gs are properly reset for future pmu transitions. table 4-28 pmu mode select logic spc2 spc1 spc0 mode 0 0 0 high-speed pll 1 0 0 low-speed pll 0 0 1 doze 0 1 1 sleep 0 1 0 suspend
4-46 configuration registers 4.3.54 general-purpose i/o 0 register (index 89h) this is a write-only register. this register is used to control the pgp0 pin in either direct- control mode or address-decode mode when pgp0 is con?ured as an output. in direct- control mode, the state of pgp0 is controlled by bit 7. when bit 7 is 1, the pgp0 output is low. when bit 7 is 0, pgp0 is high. in address-decode mode, pgp0 functions as a sim- ple address decode. pgp0 is high until the sa9?a3 signals match bits 6? of this regis- ter, at which time pgp0 goes low for as long as the signals match. pgp0 can also be gated internally with the i/o write command signal. the general-purpose i/o control register at index 91h is used to select how pgp0 operates as an output. bit 6 of the miscellaneous 6 register at index 70h is used for pgp0 direction control. 4.3.55 reserved registers (indexes 8a-8bh) these index locations are reserved. 4.3.56 i/o activity address 0 register (index 8ch) this register is used by the pmu software to program the i/o address that the activity monitor checks (bit 4 of the activity mask 2 register at index 76h is the mask). this is a write-only register. status is read from bit 4 of the activity status 2 register at index a1h. 4.3.57 i/o activity address 1 register (index 8dh) this register is used by the pmu software to program the i/o address that the activity monitor checks (bit 5 of the activity mask 2 register at index 76h is the mask). this is a write-only register. status is read from bit 5 of the activity status 2 register at index a1h. 4.3.58 reserved register (index 8eh) this index location is reserved. 7 0 field address bits 9? bit dx a9 a8 a7 a6 a5 a4 a3 default 00000000 7 0 field i/o address, bits 9? bit (reserved) a9 a8 a7 a6 a5 a4 a3 default 00000000 7 0 field i/o address, bits 9? bit (reserved) a9 a8 a7 a6 a5 a4 a3 default 00000000
configuration registers 4-47 4.3.59 clock control register (index 8fh) this register is used to program the crystal restart-delay time and cpu restart-delay time. bits 7? of this register are not reset when exiting micro power off mode. c 4.3.60 reserved register (index 90h) this index location is reserved. 4.3.61 general-purpose i/o control register (index 91h) this register is used to control the pgp3?gp0 pins. pgp0 and pgp1 can be driven directly, can be gated by i/o commands, or can be driven by simple address decodes. pgp2 and pgp3 can be automatically switched to a programmable level when the power management unit switches to off mode, can be gated by i/o commands, or can be driven by simple address decodes (i.e., each pair of pins has three ways it can be controlled). when implemented as simple-address decodes, the pgp pin goes active when the address bus matches the address bits (bits 9?) programmed into the general-purpose 7 0 bit (reserved) xst2 xst1 xst0 default 00000000 bit name r/w function 7 w (reserved?ust be 1) 6? w (reserved) 4 w (reserved?ust be 0) 3 w (reserved) 2 xst2 w pll restart delay time control bit 2 1 xst1 w pll restart delay time control bit 1 0 xst0 w pll restart delay time control bit 0 table 4-29 pll restart time select logic xst2 xst1 xst0 pll restart time 0 0 0 4 ms 0 0 1 8 ms 0 1 0 16 ms 0 1 1 32 ms 1 0 0 64 ms 1 0 1 128 ms 1 1 0 256 ms 111 1 s note: a 256-ms restart time is recommended when clocks are started from a pmu state where the low-speed pll is disabled. a 128-ms restart time is recommended when clocks are started from a pmu state where the low-speed pll is enabled. results are not guaranteed if values less than these are used. this restart value applies to both high-speed pll and low-speed pll mode restarts.
4-48 configuration registers i/o register for that pgp pin. all remaining address bits are don? cares. it is up to the system designer to externally qualify this pin with the ior , io w , memr , or memw com- mand signal. for more information, see the descriptions for each of the general-purpose i/o registers in this chapter (indexes 89h, 94h, 95h, and 9ch). . 7 0 field pgp pin 3 pgp pin 2 pgp pin1 pgp pin 0 bit pg3io1 pg3io0 pg2io1 pg2io0 pg1io1 pg1io0 pg0io1 pg0io0 default 00000000 bit name r/w function 7 pg3io1 w program general-purpose pin 3 gate control bit 1 6 pg3io0 w program general-purpose pin 3 gate control bit 0 5 pg2io1 w program general-purpose pin 2 gate control bit 1 4 pg2io0 w program general-purpose pin 2 gate control bit 0 3 pg1io1 w program general-purpose pin 1 gate control bit 1 2 pg1io0 w program general-purpose pin 1 gate control bit 0 1 pg0io1 w program general-purpose pin 0 gate control bit 1 0 pg0io0 w program general-purpose pin 0 gate control bit 0 pg0io1 pg0io0 pgp0 output 0 0 pgp0 direct control mode 1 0 pgp0 gates with i/o write command 0 1 pgp0 acts as an address decode only 1 1 pgp0 acts as an address decode only pg1io1 pg1io0 pgp1 output 0 0 pgp1 direct control mode 1 0 pgp1 acts as an address decode only 0 1 pgp1 gates with i/o read command 1 1 pgp1 acts as an address decode only pg2io1 pg2io0 pgp2 output 0 0 pgp2 automatically switches to the inverse of bit 7 of the general-purpose i/o 2 register at index 94h when the pmu is switched to off mode 1 0 pgp2 gates with i/o write command 0 1 pgp2 acts as an address decode only 1 1 pgp2 acts as an address decode only pg3io1 pg3io0 pgp3 output 0 0 pgp3 automatically switches to the inverse of bit 7 of the general-purpose i/o 3 register at index 95h when the pmu is switched to off mode 1 0 pgp3 acts as an address decode only 0 1 pgp3 gates with i/o read command 1 1 pgp3 acts as an address decode only
configuration registers 4-49 4.3.62 uart clock enable register (index 92h) this register is used to control the uart clock. 4.3.63 reserved register (index 93h) this index location is reserved and must be 0. 4.3.64 general-purpose i/o 2 register (index 94h) this is a write-only register. this register is used to control the pgp2 pin in either power- management mode or address-decode mode. in power-management mode, the state of pgp2 is high when the pmu is not in off mode. when the pmu transitions to off mode, the state of pgp2 is determined by bit 7. when bit 7 is 1, pgp2 is low. when bit 7 is 0, pgp2 is high. in address-decode mode, pgp2 functions as a simple address decode. pgp2 is high until the sa9?a3 signals match bits 6? of this register, at which time pgp2 goes low for as long as the signals match. pgp2 can also be gated internally with the i/o write command signal. the general-purpose i/o control register at index 91h is used to select how pgp2 operates as an output. pgp2 cannot operate as an input. 4.3.65 general-purpose i/o 3 register (index 95h) this is a write-only register. this register is used to control the pgp3 pin in either power- management mode or address-decode mode. in power-management mode, the state of pgp3 is high when the pmu is not in off mode. when the pmu transitions to off mode, the state of pgp3 is determined by bit 7. when bit 7 is 1, pgp3 is low. when bit 7 is 0, pgp3 is high. in address-decode mode, pgp3 functions as a simple address decode. pgp3 is high until the sa9?a3 signals match bits 6? of this register, at which time pgp3 goes low for as long as the signals match. pgp3 can also be gated internally with the i/o read command signal. the general-purpose i/o control register at index 91h is used to select how pgp3 operates as an output. pgp3 cannot operate as an input. 4.3.66 reserved registers (indexes 96?9h) these index locations are reserved. 7 0 bit (reserved) enclk default 00000000 bit name r/w function 7? w (reserved) 0 enclk w 1 = enable clock to internal 16450 uart 7 0 field address bits 9? bit dx a9 a8 a7 a6 a5 a4 a3 default 00000000 7 0 field address bits 9? bit dx a9 a8 a7 a6 a5 a4 a3 default 00000000
4-50 configuration registers 4.3.67 memory write activity lower boundary register (index 9ah) this register speci?s the low memory-address boundary that the activity monitor counts as activity (addresses a23?20 are all 0). the high memory address is de?ed by the programmable memory write activity upper boundary register at index 9bh. this activity is enabled/masked by bit 7 of the activity mask 2 register at index 76h. this is a write- only register. an activity is generated when a memory write to any address greater than the low address and less than the high address occurs. address bits a13?0 are don? cares when determining if the memory address is within the programmable range. 4.3.68 memory write activity upper boundary register (index 9bh) this register speci?s the high memory-address boundary that the activity monitor counts as activity (addresses a23?20 are all 0). the low memory-address boundary is speci?d by the programmable memory write activity lower boundary register at index 9ah. this activity is enabled/masked by bit 7 of the activity mask 2 register at index 76h. this is a write-only register. an activity is generated when a memory write to any address greater than the low address and less than the high address occurs. 7 0 bit lsa19 lsa18 lsa17 lsa16 lsa15 lsa14 (reserved) enhit default 00000000 bit name r/w function 7 lsa19 w lower boundary memory address sa19 6 lsa18 w lower boundary memory address sa18 5 lsa17 w lower boundary memory address sa17 4 lsa16 w lower boundary memory address sa16 3 lsa15 w lower boundary memory address sa15 2 lsa14 w lower boundary memory address sa14 1 w (reserved) 0 enhit w hit count function enable 7 0 field hit count limit bit hsa19 hsa18 hsa17 hsa16 (reserved) sc2 sc1 sc0 default 00000000 bit name r/w function 7 hsa19 w upper boundary memory address sa19 6 hsa18 w upper boundary memory address sa18 5 hsa17 w upper boundary memory address sa17 4 hsa16 w upper boundary memory address sa16 3 w (reserved) 2? sc2?c0 w hit count limit, bits 2?
configuration registers 4-51 4.3.69 general-purpose i/o 1 register (index 9ch) this is a write-only register. it is used to control the pgp1 pin in either direct-control mode or address-decode mode when pgp1 is con?ured as an output. in direct-control mode, the state of pgp1 is controlled by bit 7. when bit 7 is 1, pgp1 is low. when bit 7 is 0, pgp1 is high. in address-decode mode, pgp1 functions as a simple address decode. pgp1 is high until the sa9?a3 signals match bits 6? of this register, at which time pgp1 goes low for as long as the signals match. pgp1 can also be gated internally with the i/o read command signal. the general-purpose i/o control register at index 91h is used to select how pgp1 operates as an output. bit 2 of the mmsb control register at index 74h is used for pgp1 direction control. 4.3.70 reserved register (index 9dh) this index location is reserved and must be set to 40h. 4.3.71 auto low-speed control register (index 9fh) this register controls the auto low-speed trigger and duration period. bit 3 of the control b register at index 77h disables or enables the trigger; bit 6 of the i/o wait state register at index 61h enables the high-speed cpu clock. table 4-30 hit-count limit bit logic bit 210 hit-count limit 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 notes: the hit count is cleared when a pmu state-transition counter expires or any other activity occurs. thus, all memory writes must occur in the same pmu state, without other activity, before they count as activity. if the hit-count limit is 2 and two or more memory write cycles fall into the range speci?d by the address range, it counts as activity. if bit 0 of the memory write activity lower boundary register at index 9ah is not set, then this function is disabled. 7 0 field address bits 9? bit dx a9 a8 a7 a6 a5 a4 a3 default 00000000
4-52 configuration registers 7 0 field low speed trigger period bit (reserved) low1 low0 t1 t0 default 00000000 bit name r/w function 7? (reserved) 3 low1 w low-speed duration bit 1 2 low0 w low-speed duration bit 0 1 t1 w trigger period bit 1 0 t0 w trigger period bit 0 table 4-31 trigger period select logic t1 t0 trigger period 0 0 4 s 0 1 8 s 1 0 16 s 1 1 32 s table 4-32 low-speed duration period select logic low1 low0 low-speed period 0 0 0.25 s 0 1 0.5 s 1 0 1 s 1 1 2 s
configuration registers 4-53 4.3.72 activity status 1 register (index a0h) this register contains the activity status of system peripherals and signals. a 1 indicates activity. software can clear this register by writing any data to it. 4.3.73 activity status 2 register (index a1h) this register contains the activity status of system peripherals and signals. a 1 indicates activity. software can clear this register by writing any data to it. 7 0 bit int acin mms kb drq3 drq2 drq1 drq0 default 00000000 bit name r/w function 7 int r/w 1 = interrupt was detected active 6 acin r/w 1 = ac adapter input or bit 5 of the miscellaneous 6 register at index 70h was detected active 5 mms r/w 1 = mms was detected active 4 kb r/w 1 = keyboard was detected active 3 drq3 r/w 1 = drq3 was detected active 2 drq2 r/w 1 = drq2 was detected active 1 drq1 r/w 1 = drq1 was detected active 0 drq0 r/w 1 = drq5, drq6, or drq7 was detected active note: int includes all interrupts from irq2 to irq15. 7 0 bit pmw vd pio1 pio0 com hd fd lpt default 00000000 bit name r/w function 7 pmw r 1 = programmable memory range write access was detected active 6 vd r 1 = video memory write (0b0000?bffffh) was detected active 5 pio1 r 1 = general-purpose i/o 1 register was detected active 4 pio0 r 1 = general-purpose i/o 0 register was detected active 3 com r/w 1 = com1 or com2 was detected active 2 hd r/w 1 = hard disk drive was detected active 1 fd r/w 1 = floppy disk drive was detected active 0 lpt r/w 1 = lpt1, lpt2, or lpt3 was detected active
4-54 configuration registers 4.3.74 pmu status 1 register (index a2h) this register contains the status of the lph pin. 4.3.75 cpu status 0 register (index a3h) 7 0 bit lph1 (reserved) default 00000000 bit name r/w function 7 lph1 r status of lph pin 6-0 r (reserved) 7 0 field last mode battery low bit (reserved) lind2 lind1 lind0 bl3in bl2in bl1in pg0in default 00000000 bit name r/w function 7 r (reserved) 6 lind2 r last pmu state indicator 2 5 lind1 r last pmu state indicator 1 4 lind0 r last pmu state indicator 0 3 bl3in r battery low detect pin 3 (bl3 ) input data 2 bl2in r battery low detect pin 2 (bl2 ) input data 1 bl1in r battery low detect pin 1 (bl1 ) input data 0 pg0in r programmable general-purpose i/o pin 0 (pgp0) input data note: the last pmu mode indicator bits are not updated for pmu state transitions caused by writes to the software mode control register at index 88h. table 4-33 last pmu mode indicator bits lind2 lind1 lind0 last mode 0 0 0 high-speed pll 1 0 0 low-speed pll 0 0 1 doze 0 1 1 sleep 0 1 0 suspend
configuration registers 4-55 4.3.76 cpu status 1 register (index a4h) the last mode status is accurate only between the time when an event transitions the pmu to high-speed pll mode and when the timer expires in high-speed pll mode. this function is intended to allow the system to know what state the pmu was in when an event brought it out of a lower-power mode than high-speed pll mode. this register must be read before the timer expires in high-speed pll mode. 7 0 field present state bit acin (reserved) pg1in pind2 pind1 pind0 default 00000000 bit name r/w function 7 acin r acin input status 6? r (reserved) 3 pg1in r status of the pgp1 pin 2 pind2 r pmu indicator bit 2 1 pind1 r pmu indicator bit 1 0 pind0 r pmu indicator bit 0 table 4-34 present pmu mode indicator bits pind2 pind1 pind0 present mode 0 0 0 high-speed pll 1 0 0 low-speed pll 0 0 1 doze 0 1 1 sleep 0 1 0 suspend
4-56 configuration registers 4.3.77 nmi/smi control register (index a5h) reading this register returns the status information on the source of an nmi or smi. writ- ing this register allows the mode change to occur on the next refresh cycle after the write. for example, if the ?lansc310 microcontroller is programmed to generate an nmi or smi when the mode changes from low-speed pll mode to doze mode, then the pmu stays in low-speed pll mode after the generation of an nmi or smi until software writes to this register to enable the mode change. 4.3.78 reserved register (index a6h) this index location is reserved. 4.3.79 pmu control 1 register (index a7h) this register is used to control various pmu functions. 7 0 bit bl3 bl2 bl1 su sp dz on resume default 00000000 bit name r/w function 7 bl3 r/w 1 = the bl3 (battery low third warning) generated an nmi or smi 6 bl2 r/w 1 = the bl2 (battery low second warning) generated an nmi or smi 5 bl1 r/w 1 = the bl1 (battery low ?st warning) generated an nmi or smi 4 su r/w 1 = the nmi or smi was generated from suspend mode to off mode 3 sp r/w 1 = the nmi or smi was generated from sleep mode to suspend mode 2 dz r/w 1 = the nmi or smi was generated from doze mode to sleep mode 1 on r/w 1 = the nmi or smi was generated from low-speed pll mode to doze mode 0 resume r/w 1 = the nmi or smi was generated by the sus /res pin 7 0 bit (reserved) enadin2 enadin1 (reserved) slref refsel default 00000000 bit name r/w function 7? r/w (reserved) 5 enadin2 r/w 1 = ?lansc310 microcontroller disables data propagation to uart and pmu controller in memory cycle 4 enadin1 r/w 1 = ?lansc310 microcontroller disables data propagation to display controller in memory cycle 3? r/w (reserved) 1 slref r/w enable slow refresh for dram (if bit 0 is set, this bits setting has no meaning): 0 = enable slow refresh. when slow refresh is enabled, the version register at index 64h programs the 32-khz divisor for the source. 1 = disable slow refresh. the refresh rate is 65536 s unless bit 0 is set. this bit is not reset when exiting micro power off mode. 0 refsel r/w select dram refresh source (this bit setting overrides any setting for bit 1): 0 = use 32-khz clock multiplied by 2 (65536 s) as refresh source 1 = use 8254 as refresh source note: if the pmu is enabled to stop the 8254 clock, setting bit 0 will cause the dram refresh to be lost.
configuration registers 4-57 4.3.80 reserved register (index a8h) this index location is reserved. 4.3.81 smi mms upper page register (index a9h) this register, together with the ?mi mms page register (index aah) on page 4-57 is used to control the mms page used during an smi. 4.3.82 smi mms page register (index aah) this register is used to control the smi mms page register. 7 0 bit gensmi (reserved) smia23 smia22 (reserved) default 00000000 bit name r/w function 7 gensmi r/w 1 = ?lansc310 microcontroller generates an smi instead of an nmi for the sources enabled in the nmi/smi enable register at index 82h. (bit 7 of the at- compatible port 70h must be 0 for nmis to occur.) 6 r/w (reserved) 5 smia23 r/w smi mms translate address a23 for smi only. see ?mi mms page register (index aah) on page 4-57. 4 smia22 r/w smi mms translate address a22 for smi only. see ?mi mms page register (index aah) on page 4-57. 3-0 r/w (reserved) 7 0 bit smia21 smia20 smia19 smia18 smia17 smia16 smia15 smia14 default 00000000 note: smi mms is active only in system management mode (smm). bit name r/w function 7 smia21 r/w smi mms translate address bit a21 6 smia20 r/w smi mms translate address bit a20 5 smia19 r/w smi mms translate address bit a19 4 smia18 r/w smi mms translate address bit a18 3 smia17 r/w smi mms translate address bit a17 2 smia16 r/w smi mms translate address bit a16 1 smia15 r/w smi mms translate address bit a15 0 smia14 r/w smi mms translate address bit a14 note: a special mms with page address 060000h is used for the smi function. smi accesses that use the mms always map to on-board memory.
4-58 configuration registers 4.3.83 power control 3 register (index abh) this register activates the pmc3 and pmc4 output pins in high-speed pll mode, low- speed pll mode, doze mode, sleep mode, and suspend mode. the pmc4 pin can be programmed to toggle inactive when the hard-disk-drive timer expires. for more informa- tion on using pmc4 with the hard-disk-drive timer, see ?ccesses to powered-down device smi on page 1-29. 7 0 bit su4 sp4 dz4 fo4 su3 sp3 dz3 fo3 default 00000000 bit name r/w function 7 su4 r/w state of pmc4 pin in suspend mode 6 sp4 r/w state of pmc4 pin in sleep mode 5 dz4 r/w state of pmc4 pin in doze mode 4 fo4 r/w state of pmc4 pin in high-speed pll and low-speed pll modes 3 su3 r/w inverse state of pmc3 pin in suspend mode 2 sp3 r/w inverse state of pmc3 pin in sleep mode 1 dz3 r/w inverse state of pmc3 pin in doze mode 0 fo3 r/w inverse state of pmc3 pin in high-speed pll and low-speed pll modes notes: the initial state of pmc4 after power-on is low. when the bit is 0, the corresponding pmc output for that pmu mode is low. the initial state of pmc3 after power-on is high. when the bit is 0, the corresponding pmc output for that pmu mode is high. pmc4 is the pin associated with the dedicated hard-disk-drive address activity decode and timer. if pmc4 is not used for the hard disk drive, the hard-disk-drive timer and associated control must be disabled. bits 7? of this register are cleared when the hard-disk-drive timer expires.
configuration registers 4-59 4.3.84 power control 4 register (index ach) this register activates the pmc0 and pmc1 output pins in high-speed pll mode, low- speed pll mode, doze mode, sleep mode, and suspend mode. the pmc0 pin can be programmed to toggle inactive when the ?ppy-disk-drive timer expires. the pmc1 pin can be programmed to toggle inactive when the pio timer expires. for more information on using the pmc pins with the timers, see ?ccesses to powered-down device smi on page 1-29. bits 7? these bits are cleared as a result of the pio timer expiring. bits 3? these bits are cleared as a result of the ?ppy-disk-drive timer expiring. 7 0 bit su1 sp1 dz1 fo1 su0 sp0 dz0 fo0 default 00000000 bit name r/w function 7 su1 r/w state of pmc1 pin in suspend mode 6 sp1 r/w state of pmc1 pin in sleep mode 5 dz1 r/w state of pmc1 pin in doze mode 4 fo1 r/w state of pmc1 pin in high-speed pll and low-speed pll modes 3 su0 r/w state of pmc0 pin in suspend mode 2 sp0 r/w state of pmc0 pin in sleep mode 1 dz0 r/w state of pmc0 pin in doze mode 0 fo0 r/w state of pmc0 pin in high-speed pll and low-speed pll modes notes: the initial state of pmc0 and pmc1 after power-on is low. when the bit is 0, the corresponding pmc output for that pmu mode is low. pmc0 is associated with the dedicated ?ppy-disk-drive address activity decode and timer. if pmc0 is not used for the ?ppy disk drive, the ?ppy-disk-drive timer and associated control must be disabled. pmc1 is associated with the dedicated pio address activity decode and timer. if pmc1 is not used for the pio, the pio timer and associated control must be disabled.
4-60 configuration registers 4.3.85 pmu control 3 register (index adh) this register controls several pmu functions. when switching the low-speed frequency, the low-speed pll is divided. this divided frequency is selected for use when the pmu is not in the low-speed pll mode. the low-speed clock select bits (bits 1 and 0 of the pmu control 3 register) should be modi?d only when the pmu is not in low-speed pll mode. bit 4 this bit is used in conjunction with bit 6 of the activity mask 1 register at index 75h. if bit 4 of the pmu control 3 register is 0, bit 6 of the activity mask 1 register has no function. bits 1? these bits only have an effect in low-speed pll mode. 4.3.86 reserved register (index aeh) this register is reserved. 7 0 field clock select bit (reserved) irq0smien (reserved) enacin xtkbden mainoff onclk1 onclk0 default 00000000 bit name r/w function 7 r/w (reserved) 6 irq0smien r/w 1 = 8254 channel 0 generates an smi instead of the normal irq0. note that the irq0 in the pic must be enabled to allow this condition. 5 r/w (reserved) 4 enacin r/w 1 = acin is treated as activity 3 xtkbden r/w 1 = allows the 8042cs and sysclk pins to become three-stated so they may be used as inputs, all other requirements being met. it also quali?s an internal decode so that port 60h is read as an internal port. it further switches a multiplexer to vector irq1 from the external pin to the output of this circuitry. 2 mainoff r/w 1 = ?lansc310 microcontroller turns off the high-speed pll in low-speed pll mode; otherwise, the high-speed pll is turned off in doze mode. 1 onclk1 r/w low-speed pll mode cpu clock bit 1 0 onclk0 r/w low-speed pll mode cpu clock bit 0 table 4-35 low-speed pll mode cpu clock speed select onclk1 onclk0 clock frequency to cpu internal cpu operation speed 0 0 9.216 mhz 4.608 mhz 0 1 4.608 mhz 2.304 mhz 1 0 2.304 mhz 1.152 mhz 1 1 1.152 mhz 0.576 mhz
configuration registers 4-61 4.3.87 pmu control 2 register (index afh) this register controls several pmu operations. 4.3.88 function enable 1 register (index b0h) bit 3 when this bit is set, the dma clock runs only when a dma access is happening; it is stopped between dma transfers. bit 1 this bit is used to con?ure the ?lansc310 microcontrollers parallel-port control outputs for the parallel-port hardware interface implemented on the system board. when bit 1 is 0, db ufoe is not generated during parallel-port accesses. this bit should only be 0 if the system is implemented without a system buffer. this bit must be 1 for systems that have a system buffer and implement a parallel port with either an input buffer and output latch, or just an output latch. 7 0 bit chgon chgfuset bl1lowsp (reserved) extir0act default 00000000 bit name r/w function 7 chgon r/w low-speed to doze mode timer register (index 84h) unit value: 1 = 1 4 s 0 = 1 16 s 6 chgfuset r/w high-speed to low-speed mode timer register (index 83h) unit value: 1 = 1 16 s 0 = 1 512 s 5 bl1lowsp r/w 1 = set cpu clock speed to low speed (9.2 mhz) in high-speed pll mode if bl1 is low and acin is low. 4e1 r/w (reserved) 0 extir0act r/w 1 = extend cpu run time for an additional 64 refresh cycles following irq0 while in doze mode. this bit is effective only if bit 3 of the mmsb control register at index 74h is 1. 7 0 bit (reserved) x1sel extsmiedg extsmien dmastclk eppmode ppisbi ppbienb default 00000000 bit name r/w function 7 r/w (reserved) 6 x1sel w x1out clock select: 0 = x1out determined by bit 2 of index b1h 1 = x1out driven by baudout 5 extsmiedg r/w external smi active edge 1 = active-low external smi 0 = active-high external smi 4 extsmien r/w 1 = enable external smi 3 dmastclk r/w 1 = dma stop clock (power-save mode) enable 2 eppmode r/w epp mode enable for parallel port 1 ppisbi r/w bidirectional con?uration enable for parallel port 0 ppbienb r/w bidirectional enable for parallel port
4-62 configuration registers bit 0 this bit is used to enable the bidirectional control for the parallel port. this bit functions only if bit 1 is 1. when bit 0 is 0, the parallel-port data-latch output-enable signal from the ?lansc310 microcontrollers cpu, ppoen , is forced low, causing the parallel- port data-latch to drive the parallel-port data bus. when bit 0 is 1, the ppoen signal is controlled by bit 5 of the parallel port control register. 4.3.89 function enable 2 register (index b1h) bit 7? when bit 7 of the function enable 3 register at index b4h is 1, the values of bits 6 and 7 of this register determine the dram mode as shown in table 4-38 on page 4-63. bit 4? do not change these bits while running in the high-speed pll mode. to change these bits, ?st clear bit 6 of the i/o wait state register at index 61h, then wait for the next refresh to occur. then change the high-speed pll frequency and return to using the high-speed pll. table 4-36 latch and buffer logic ppbienb ppisbi eppmode mode 0 0 0 output latch, no system buffer, no input buffer, pp output only 0 0 1 (invalid combination) 0 1 0 output latch, system buffer, no input buffer, pp output only 0 1 1 output latch, system buffer, no input buffer, epp mode 1 0 0 (invalid combination) 1 0 1 (invalid combination) 1 1 0 output latch, system buffer, input buffer, pp is bidirectional 1 1 1 output latch, system buffer, input buffer, epp mode 7 0 bit eb_rmmd1 eb_rmmd0 (reserved) hspllfq1 hspllfq0 xtaluse (reserved) default 00000000 bit name r/w function 7 eb_rmmd1 r/w ram mode select bit 0 6 eb_rmmd0 r/w ram mode select bit 1 5 r/w (reserved?ust be 0) 4 hspllfq1 r/w high-speed pll frequency select, bit 1 3 hspllfq0 r/w high-speed pll frequency select, bit 0 2 xtaluse r/w crystal interface: 1 = 14.336 mhz out on x1out pin 0 = three-state x1out pin (see bit 6 of the function enable 1 register at index b0h) 1-0 (reserved)
configuration registers 4-63 table 4-37 high-speed pll frequency select hspllfq 10 high-speed pll (clk2) frequency 0 0 40 mhz 0 1 50 mhz 1 0 66 mhz 1 1 (reserved) note: in order to meet dram timing at 33 mhz, the following registers need to be programmed as indicated: clear bit 6 of the command delay register at index 60h. set bit 4 of the mms memory wait state 1 register at index 62h. set bit 5 of the rom con?uration 1 register at index 65h. set bits 5 and 6 of the wait state control register at index 63h. table 4-38 ram mode decode logic ram mode index b4h bit 7 index b1h bits 7? total memory bank 0 bank 1 256-kbit 4-bit dram 1 0 0 512 kbyte 512 kbyte e 256-kbit 4-bit dram 1 0 1 1 mbyte 512 kbyte 512 kbyte asymmetric 1-mbit 16-bit dram 1 1 0 2 mbyte 2 mbyte e asymmetric 1-mbit 16-bit dram 1 1 1 4 mbyte 2 mbyte 2 mbyte (see table 4-23 on page 4-28) 0 x x controlled by bits 4e2 of index 66h notes: if bit 7 of the function enable 3 register at index b4h is 1, bits 4? of the memory con?uration 1 register at index 66h are disabled. bit 0 of the memory con?uration 1 register determines page mode or enhanced page mode. if the 4-mbyte memory con?uration is selected, the enhanced page mode must be selected by setting bit 0 of the memory con?uration 1 register. page mode is illegal for this con?uration.
4-64 configuration registers 4.3.90 pirq configuration register (index b2h) this register selects the irq level to which the pirq0 and pirq1 pins are connected. see table 4-39 on page 4-65 for the valid irq selections. in full isa bus mode, this reg- ister has no effect. this register is valid for local bus mode only. in full isa bus mode, pirq0 is connected to irq3, and pirq1 is connected to irq6. 7 0 field pirq1 steering pirq0 steering bit pirq1sl3 pirq1sl2 pirq1sl1 pirq1sl0 pirq0sl3 pirq0sl2 pirq0sl1 pirq0sl0 default 00000000 bit name r/w function 7 pirq1sl3 r/w pirq1 irq select, bit 3 6 pirq1sl2 r/w pirq1 irq select, bit 2 5 pirq1sl1 r/w pirq1 irq select, bit 1 4 pirq1sl0 r/w pirq1 irq select, bit 0 3 pirq0sl3 r/w pirq0 irq select, bit 3 2 pirq0sl2 r/w pirq0 irq select, bit 2 1 pirq0sl1 r/w pirq0 irq select, bit 1 0 pirq0sl0 r/w pirq0 irq select, bit 0 note: do not program either of the pirq pins such that they con?ct with other irqs. for example, do not program both pirq pins to the same level or to the irq level used by the internal uart. interrupt sharing is not supported.
configuration registers 4-65 4.3.91 miscellaneous 5 register (index b3h) this register is used to obtain miscellaneous status information. table 4-39 interrupt redirect logic pirq1sl3?irq1sl0 or pirq0sl3?irq0sl0 pirq1 or pirq0 3210 irq selected 0000 (none) 0001 (reserved) 0010 (reserved) 0011 irq3 0100 irq4 0101 irq5 0110 irq6 0111 irq7 1000 (reserved) 1001 irq9 1010 irq10 1011 irq11 1100 irq12 1101 (reserved) 1110 irq14 1111 irq15 7 0 bit 32khzste enfstromcs fstromws1 fstromws0 enselfref enbromcs extsmiste (reserved) default 00000000 bit name r/w function 7 32khzste r state of the 32-khz clock 6 enfstromcs r/w 1 = r omcs rom accesses enabled to run at the high-speed clock rate 5 fstromws1 r/w fast bios rom wait-state select 1 4 fstromws0 r/w fast bios rom wait-state select 0 3 enselfref r/w self-refresh dram mode when cpuclk is halted: 0 = cas-before-ras refresh (default) 1 = self-refresh this bit is not reset when exiting micro power off mode. 2 enbromcs r/w 1 = r omcs enabled as an address decode, but not quali?d with memr or memw 1 extsmiste r state of external smi pin 0 (reserved)
4-66 configuration registers bit 6 this bit should not be set for systems that assert mcs16 because running the isa bus at the high-speed pll frequency violates mcs16 timing. when bit 6 is set, the maximum isa bus signal, bale, is not asserted for cycles to the r omcs decode space. this may cause isa decode con?cts for devices that use bale to catch la23?a17. bits 5? when the r omcs rom accesses are enabled to run at high speed (bit 6), these bits control the number of wait states for these cycles as shown in table 4-40 on page 4-66. bit 1 this bit indicates the state of the external smi pin; it should be read to determine if an external smi is being generated. the smi handler should poll this bit and verify that it goes inactive prior to exiting the handler. 4.3.92 function enable 3 register (index b4h) this register is used to enable additional dram modes. bit 7 when this bit is 0, ram mode is determined by bits 4? of the memory con?uration 1 register at index 66h. setting this bit enables additional dram modes con?ured via bits 7? of the function enable 2 register at index b1h. 4.3.93 reserved registers (indexes b5h-b7h) these index locations are reserved. table 4-40 rom-bios enable and wait-state select logic enfstromcs fstromws1?stromws0 number of wait states for r omcs cycle 0 x x (fast r omcs disabled) 10 0 4 10 1 3 11 0 2 11 1 1 7 0 bit enrame2 (reserved) default 00000000 bit name r/w function 7 enrame2 r/w 1 = enable additional dram modes corresponding to bits 7? of the function enable 2 register at index b1h 6 (reserved?ust be 1) 5? (reserved)
configuration registers 4-67 4.3.94 rom configuration 3 register (index b8h) this register controls the size of rom dos and the number of wait states for a doscs cycle. bit 7 this bit should not be set when decoding an 8-bit device in systems that assert mcs16 because running the isa bus at the high-speed pll frequency violates mcs16 timing. bit 7 can be used if doscs accesses a 16-bit device by setting bit 1 of the rom con?uration 2 register at index 51h. also, when bit 7 is 1, the maximum isa bus signal, bale, is not asserted for cycles to the doscs decode space. this may cause isa decode con?cts for devices that use bale to latch la23?a17. bits 6? when the doscs rom accesses are enabled to run at high speed (bit 7), these bits control the number of wait states for these cycles as shown in table 4-41 on page 4-67. bits 3? these bits decode to the sizes shown in table 4-42 on page 4-68. 7 0 bit enfstrdos frdosws1 frdosws0 enrdoscs rdossiz3 rdossiz2 rdossiz1 rdossiz0 default 0 0000000 bit name r/w function 7 enfstrdos r/w 1 = enable doscs accesses to run at the high-speed cpu clock rate 6 frdosws1 r/w doscs wait state select bit 0 5 frdosws0 r/w doscs wait state select bit 1 4 enrdoscs r/w 1 = enable doscs as an address decode not quali?d with memr or memw 3 rdossiz3 r/w doscs size select bit 3 2 rdossiz2 r/w doscs size select bit 2 1 rdossiz1 r/w doscs size select bit 1 0 rdossiz0 r/w doscs size select bit 0 table 4-41 rom-dos enable and wait-state select logic enfstrdos frdosws1?rdosws0 number of wait states for doscs cycle 0 x x (see index 50h) 10 0 4 10 1 3 11 0 2 11 1 1
4-68 configuration registers table 4-42 rom-dos linear-address decode-size select logic rdossiz3?dossiz0 doscs address decode dos rom size 0 0 0 0 (doscs uses mms mapping) (na) 0 0 0 1 f00000?effffh 1 mbyte?4 kbyte 0 0 1 0 e00000?effffh 2 mbyte?4 kbyte 0 0 1 1 d00000?effffh 3 mbyte?4 kbyte 0 1 0 0 c00000?effffh 4 mbyte?4 kbyte 0 1 0 1 b00000?effffh 5 mbyte?4 kbyte 0 1 1 0 a00000?effffh 6 mbyte?4 kbyte 0 1 1 1 900000?effffh 7 mbyte?4 kbyte 1 0 0 0 800000?effffh 8 mbyte?4 kbyte 1 0 0 1 700000?effffh 9 mbyte?4 kbyte 1 0 1 0 600000?effffh 10 mbyte?4 kbyte 1 0 1 1 500000?effffh 11 mbyte?4 kbyte 1 1 0 0 400000?effffh 12 mbyte?4 kbyte 1 1 0 1 300000?effffh 13 mbyte?4 kbyte 1 1 1 0 200000?effffh 14 mbyte?4 kbyte 1 1 1 1 100000?effffh 15 mbyte?4 kbyte note: the linear doscs decode range must not overlap the on-board memory decode range unless the on-board memory in the overlapping range is disabled via bits 7? of the miscellaneous 1 register at index 6fh.
configuration registers 4-69 4.3.95 memory configuration 2 register (index b9h) this register disables refresh in off mode and selects programmable drive strengths, as shown in table 4-43 on page 4-69 and table 4-44 on page 4-69. 7 0 bit disrefoff (reserved) memdats1 memdats0 memadrs1 memadrs0 memctls1 memctls0 default 00000000 bit name r/w function 7 disrefoff r/w disable refresh in the pmu off mode 6 r/w (reserved) 5 memdats1 r/w d15?0 drive strength select 1 4 memdats0 r/w d15?0 drive strength select 0 3 memadrs1 r/w ma10?a0/sa23?a13 and mwe drive strength select 1 2 memadrs0 r/w ma10?a0/sa23?a13 and mwe drive strength select 0 1 memctls1 r/w ras0 , ras1 drive strength select 1 0 memctls0 r/w ras0 , ras1 drive strength select 0 table 4-43 output drive strength select logic drive strength select bit value 1 0 output drive strength 0 0 e (default) 0 1 c 1 0 d 1 1 three-state output table 4-44 i/o drive type description drive type vccio (ma) iol ttl (ma) ioh ttl (ma) c 3.0?.5 7.7?0.8 8.6 to 34.2 d 3.0?.5 7.7?0.8 10.3 to 40.8 e 3.0?.5 10.2?4.1 13.6 to 53.9 note: current out of a pin is given as a negative value.
4-70 configuration registers 4.3.96 miscellaneous 3 register (index bah) this register enables the 14-mhz clock output on afdt and preserves dram during micro power off mode. bit 3 when this bit is 1, the 14.336-mhz clock output is enabled on pin 80. bit 2 when this bit is 1, dram timing is maintained when entering micro power off mode. it should be set if the contents of dram are to be preserved during micro power off mode. bits 1? these bits are not reset when exiting micro power off mode. 7 0 bit (reserved) en_14m_pp en_mpom (reserved) default 00000000 bit name r/w function 7? r/w (reserved) 4 r/w (reserved?ust be 0) 3 en_14m_pp r/w 1 = enable 14.336-mhz clock output on afdt 2 en_mpom r/w 1 = preserve dram during micro power off mode 1? r/w (reserved) table 4-45 parallel port pin rede?ition pin no. name new function 80 afdt 14.336-mhz clock 84 slctin pcmcoe 89 init pcmcwe
configuration index register reference a-1 appendix a configuration index register reference con?uration index registers are used to set up and monitor the system con?uration of the ?lansc310 microcontroller. the following table lists the con?uration index registers alphabetically by name. use it when you know the name of a con?uration index register but not its index. for a complete description of each of these registers, see ?on?uration index registers on page 4-11. for information on how to access these registers, see ?on?uration reg- ister overview on page 4-2. con?uration index register index function activity mask 1 75h pmu activity mask 2 76h pmu activity status 1 a0h pmu activity status 2 a1h pmu auto low-speed control 9fh pmu clock control 8fh pmu command delay 60h isa/mcu control a 48h control control b 77h control cpu status 0 a3h pmu cpu status 1 a4h pmu doze to sleep timer 85h pmu drive timer 47h pmu function enable 1 b0h pmu function enable 2 b1h pmu function enable 3 b4h mcu general-purpose i/o 0 89h pmu general-purpose i/o 1 9ch pmu general-purpose i/o 2 94h pmu general-purpose i/o 3 95h pmu general-purpose i/o control 91h pmu high-speed to low-speed timer 83h pmu i/o activity address 0 8ch pmu i/o activity address 1 8dh pmu i/o timeout 40h pmu i/o wait state 61h isa/mcu low-speed to doze timer 84h pmu memory con?uration 1 66h mcu memory con?uration 2 b9h mmu memory write activity lower boundary 9ah pmu memory write activity upper boundary 9bh pmu miscellaneous 1 6fh isa/mcu
a-2 configuration index register reference miscellaneous 2 6bh mcu miscellaneous 3 bah mmu/pmu miscellaneous 4 44h pmu miscellaneous 5 b3h pmu miscellaneous 6 70h pmu/mcu mms address 6dh mcu mms address extension 1 6ch mcu mms address extension 2 6eh mcu mms memory wait state 1 62h mcu mms memory wait state 2 50h mcu mmsa address extension 1 67h mcu mmsa device 1 71h mcu mmsa device 2 72h mcu mmsb control 74h pmu/mcu mmsb device 73h mcu nmi/smi control a5h pmu nmi/smi enable 82h pmu pio address 45h pmu pio timer 46h pmu pirq con?uration b2h pmu pmu control 1 a7h pmu pmu control 2 afh pmu pmu control 3 adh pmu pmu status 1 a2h pmu power control 1 80h pmu power control 2 81h pmu power control 3 abh pmu power control 4 ach pmu resume mask 08h pmu resume status 09h pmu rom con?uration 1 65h mcu rom con?uration 2 51h mcu rom con?uration 3 b8h mmu shadow ram enable 1 68h mcu shadow ram enable 2 69h mcu sleep to suspend timer 86h pmu smi enable 41h pmu smi i/o status 42h pmu smi mms page aah pmu smi mms upper page a9h pmu smi status 43h pmu software mode control 88h pmu suspend to off timer 87h pmu uart clock enable 92h pmu version 64h pmu wait state control 63h mcu con?uration index register index function
xt-keyboard interface b-1 appendix b xt-keyboard interface the xt-keyboard interface consists of clock and data inputs to the elansc310 microcon- troller and is compatible with the ibm pc/xt keyboard. one of the elansc310 microcon- trollers output pins, such as a programmable general-purpose (pgp) pin, may be used to drive an actual xt-keyboard reset input. the kb clock input is synchronized by two serial ?p-?ps, which are clocked by the ck218 signal. this signal is actually the cpu clock signal divided by 6. the (thus delayed) kb clock signal is then used to clock the data into the kb data shift register. the ?st bit to be clocked in is the start bit, and must be a logic 1 (high). eight more bits are then shifted in, beginning with the least signi?ant bit. on the ninth clock, the start bit is shifted into the dff, which drives the kb interrupt output and is connected to irq1. at this same time, the kb data i/o pad changes directions to become an output and is driven low as a busy indication to the keyboard or other driving device. at this time, the host should respond to the interrupt and read the byte assembled in the kb data shift register at port 060h. the host also has the option of driving the clock pin low as an addi- tional handshake indication. after the host has read the byte from port 060h, the host clears the kb data shift register and the interrupt ?p-?p by writing a 1 and then a 0 to bit 7 of port 061h. this action not only clears the shift register and interrupt, but also releases the data line to function as an input again. figure b-1 xt keyboard block diagram (8042cs ) kb data kb clock (sysclk) sync clk (ck218) nclrkb dff kb data shift register kb clock synchronizer kb int out kb data out
b-2 xt-keyboard interface b.1 xt keyboard enable the ?lansc310 microcontrollers xt keyboard circuitry is enabled by bit 3 of index 0adh. setting this bit n allows the 8042cs and sysclk pins to become three-stated so they may be used as inputs (all other requirements being met). n quali?s an internal decode so that port 060h is read as an internal port. n switches a multiplexer to vector irq1 from the external pin to the output of this cir- cuitry. b.2 keyboard interface control two bits are provided for control of the xt keyboard interface. these bits are located at port 061h. bit 7 is used to clear the keyboard interrupt and shift register, a ?p-?p that enables the data line as an output (to act as a busy signal to the keyboard when low). two writes are required for the proper operation of this bit?ne to set, and another to clear it. if bit 7 is not cleared, the shift register is held in a clear con?uration. bit 6, when high, makes the kbclk line an output (driving it low), which can also be used as a busy signal to the keyboard. b.3 keyboard data port once a serial keyboard byte has been assembled, it can be read at port 060h. b.4 i/o map summary n setting bit 3 of index adh enables the xt keyboard. n port 060h contains the keyboard data. n setting bit 7 of port 061h clears the keyboard shift register and interrupt. n setting bit 6 of port 061h forces the keyboard clock low. b.5 pins used the xt keyboard option uses the following pins: n sysclk becomes the keyboard clock (xtclk). n 8042cs becomes the keyboard data (xtdat). because both pins can also act as outputs and the data line is driven as an output at the end of each transferred byte, the pins must be driven by open-drain or open-collector drivers with external pull-ups.
xt-keyboard interface b-3 b.6 timing the xt-keyboard clock runs at approximately 100 khz, or 10 m s per bit. the falling edge of the xtclk input clocks the shift register, but it is delayed by two cpuclk periods divided by 6. therefore, xtdat should be changed on the rising edge of the xtclk sig- nal. the xt-keyboard interface runs at speeds as high as 250 khz. figure b-2 xt keyboard timing diagram 01 2345 67 xtclk xtdat kbirq shift register clear
index i-1 numbers 0clk_doz bit, 4-42 0clk_slp bit, 4-43 0clk_sus bit, 4-43 8-bit isa i/o access command delay (table), 4-20 8-bit isa i/o memory access command delay (table), 4-21 8bmws0 bit 8-bit isa memory-cycle wait states (table), 4-24 function, 4-23 8bmws1 bit 8-bit isa memory-cycle wait states (table), 4-24 function, 4-23 8mcd bit function, 4-20 rom dos command delay select logic (table), 4-19 16bmws0 bit 16-bit isa memory-cycle wait states (table), 4-24 function, 4-23 16bmws1 bit 16-bit isa memory-cycle wait states (table), 4-24 function, 4-23 16iowait bit, 4-25 24/12 bit, 3-19 32khzste bit, 4-65 80-ns dram support, 2-17 8042cs pin, for xt-keyboard enable, b-2 8254 clock (timer) speeds (table), 1-6 16450 clock (uart) speeds (table), 1-6 a a20smi bit, 4-30 ac input status pin, 1-34 acin bit activity mask 1 register (index 75h), 4-40 activity status 1 register (index a0h), 4-53 cpu status 1 register (index a4h), 4-55 acin pin, 1-34 ack bit parallel status port (ports 279h & 379h), 3-10 parallel status port (ports 279h, 379h, & 3bdh), 3-9 activity cpu and non-cpu related, 1-19 events constituting activity, 1-9 inactivity states and transition intervals (table), 1-9 activity mask 1 register (index 75h) activity selection, 1-19 bit descriptions, 4-40 4-41 generating pmu-activity event with acin pin, 1-34 pmu operating-mode transitions, 1-8 activity mask 2 register (index 76h) activity selection, 1-19 bit descriptions, 4-40 pmu operating-mode transitions, 1-8 activity monitors definition, 1-2 purpose and use, 1-19 state transition flowchart (figure), 1-20 activity status 1 register (index a0h) activity monitoring, 1-19 bit descriptions, 4-53 activity status 2 register (index a1h) activity monitoring, 1-19 bit descriptions, 4-53 address registers configuration address register (port 022h), 4-11 i/o activity address 0 register (index 8ch), 4-46 i/o activity address 1 register (index 8dh), 1-8 , 4-46 mms address extension 1 register (index 6ch), 4-31 mms address extension 2 register (index 6eh), 4-33 mms address register (index 6dh), 4-31 4-33 mmsa address extension 1 register (index 67h), 4-29 nmi/rtc index address register (port 070h), 3-21 parallel epp address port (ports 27bh & 37bh), 3-11 pio address register (index 45h), 4-15 index
i-2 index af bit, 3-19 aie bit, 3-19 alta20 bit, 3-21 am386sxlv microprocessor, integration in ?lansc310 microcontroller, xi at peripheral registers. see pc/at peripheral regis- ters. autlow bit, 4-42 auto low-speed control register (index 9fh) bit descriptions, 4-52 low-speed duration period select logic (table), 4-52 trigger period select logic (table), 4-52 auto low-speed logic overview, 1-3 purpose and use, 1-40 autofdx bit, 3-9 b battery-management logic, 1-32 1-34 ac input status (acin) pin, 1-34 battery level 1 (bl1 ) pin, 1-32 battery level 2 (bl2 ) pin, 1-32 1-33 battery level 3 (bl3 ) pin, 1-33 battery level 4 (bl4 ) pin, 1-33 1-34 functionality of bl4 ?l1 (table), 1-32 overview, 1-2 bhe bit, 4-14 bi bit, 3-14 bkmiss bit dram bank miss wait state select logic (table), 4-25 function, 4-25 bl1 bit nmi/smi enable register (index 82h), 4-43 bl1 pin, 1-32 bl1in bit, 4-54 bl1lowsp bit, 4-61 bl2 bit nmi/smi enable register (index 82h), 4-43 bl2 pin battery-management logic, 1-32 1-34 smi generation, 1-33 bl2in bit, 4-54 bl3 bit nmi/smi enable register (index 82h), 4-43 bl3 pin, 1-33 bl3in bit, 4-54 bl4 pin, 1-33 1-34 bus bus option status table, 4-28 determining bus configuration (table), 4-5 general bus i/o wait states (table), 4-23 pc/at bus, 4-5 quiet bus feature, 1-41 bus configurations, 2-5 2-6 ?lansc310 microcontroller bus configurations (fig- ure), 2-5 isa and local bus configurations, 2-5 pins for bus configuration (table), 2-5 supported by ?lansc310 microcontroller, 2-2 busy bit parallel status port (ports 279h & 379h), 3-10 parallel status port (ports 279h, 379h & 3bdh), 3-9 c cas0h signal selecting dram memory banks, 2-3 cas0l signal selecting dram memory banks, 2-3 cas1l signal selecting dram memory banks, 2-3 central processing unit. see cpu. cfg0 bit bus option status table, 4-28 function, 4-28 cfg1 bit bus option status table, 4-28 function, 4-28 chgfuset bit, 4-61 chgon bit, 4-61 clock control register (index 8fh) bit descriptions, 4-47 pll restart time select logic (table), 4-47 clock sources, pmu, 1-9
index i-3 clocks. see also specific clocks. clock-switching permutations available with pmu modes, 1-8 keyboard clock, b-2 pmu clock speeds (table), 1-6 registers for controlling (table), 4-8 clock-switching logic, 1-16 1-18 clock startup and shutdown logic, 1-16 logic flowchart (figure), 1-18 cpu/memory clock switching, 1-16 1-17 definition, 1-2 com bit activity mask 2 register (index 76h), 4-41 activity status 2 register (index a1h), 4-53 command delay register (index 60h) 8-bit isa i/o access command delay (table), 4-20 8-bit isa memory access command delay (table), 4-21 bit descriptions, 4-20 refresh cycle wait states (table), 4-21 rom bio wait states (table), 4-21 command delays duration for various cycles (table), 2-14 purpose and use, 2-14 configuration address register (port 022h), 4-11 configuration data register (port 023h), 4-11 configuration index registers activity mask 1 register (index 75h), 1-8 , 1-19 , 1-34 , 4-40 4-41 activity mask 2 register (index 76h), 1-8 , 1-19 , 4-41 activity status 1 register (index a0h), 1-19 , 4-53 activity status 2 register (index a1h), 1-19 , 4-53 auto low-speed control register (index 9fh), 4-51 clock control register (index 8fh), 4-47 command delay register (index 60h), 4-20 control a register (index 48h), 4-18 control b register (index 77h), 4-42 controlling low-speed cpu clock, 1-6 cpu status 0 register (index a3h), 4-54 cpu status 1 register (index a4h), 1-9 , 4-55 doze to sleep timer register (index 85h), 1-22 , 4-44 drive timer register (index 47h), 4-17 function enable 1 register (index b0h), 1-31 , 4-61 4-62 function enable 2 register (index b1h), 2-3 , 4-62 4-63 general-purpose i/o 0 register (index 89h), 4-46 general-purpose i/o 1 register (index 9ch), 4-51 general-purpose i/o 2 register (index 94h), 1-7 , 4-49 general-purpose i/o 3 register (index 95h), 1-7 , 4-49 general-purpose i/o control register (index 91h), 1-7 , 4-47 4-48 high-speed to low-speed timer register (index 83h), 1-22 , 4-44 i/o activity address 0 register (index 8ch), 1-8 , 4-46 i/o activity address 1 register (index 8dh), 1-8 , 4-46 i/o timeout register (index 40h), 1-31 i/o wait state register (index 61h), 4-22 4-23 low-speed to doze timer register (index 84h), 4-44 mandatory settings, 4-2 4-4 memory configuration 1 register (index 66h), 2-3 , 2-4 , 4-28 memory configuration 2 register (index b9h), 1-7 , 4-69 memory write activity lower boundary register (in- dex 9ah), 1-8 , 4-50 memory write activity upper boundary register (in- dex 9bh), 1-8 , 4-50 4-51 miscellaneous 1 register (index 6fh), 2-8 , 4-34 4-35 miscellaneous 2 register (index 6bh), 1-27 , 4-30 miscellaneous 3 register (index bah), 4-70 miscellaneous 4 register (index 44h), 1-29 , 1-41 , 4-15 miscellaneous 5 register (index b3h), 1-28 , 2-15 , 4-65 miscellaneous 6 register (index 70h), 1-34 mms address extension 1 register (index 6ch), 4-31 mms address extension 2 register (index 6eh), 4-33 mms address register (index 6dh), 4-31 4-33 mms memory wait state 1 register (index 62h), 2-4 , 4-23 4-24 mms memory wait state 2 register (index 50h), 4-19 mmsa address extension 1 register (index 67h), 4-29 mmsa device 1 register (index 71h), 4-36 mmsa device 2 register (index 72h), 4-37 mmsb control register (index 74h), 1-6 , 1-33 , 4-39 mmsb device register (index 73h), 4-38 mmsb socket register (index a9h), 1-27 , 4-43 nmi/smi control register (index a5h), 1-26 1-29 , 1-32 , 1-33 , 1-36 , 1-38 , 1-39 , 4-56 nmi/smi enable register (index 82h), 1-32 , 1-33 , 1-37 , 4-43 overview, 4-2 pio address register (index 45h), 1-29 , 4-15 pio timer register (index 46h), 1-29 , 4-16 4-17 pirq configuration register (index b2h), 4-64 pmu control 1 register (index a7h), 1-8 , 1-41 , 4-56 pmu control 2 register (index afh), 1-22 , 1-32 , 4-61 4-62 pmu control 3 register (index adh), 1-8 , 1-34 , 4-60 pmu operating-mode transitions, 1-8 power control 1 register (index 80h), 1-6 , 1-9 , 4-42 power control 2 register (index 81h), 1-7 , 1-9 , 4-43 power control 3 register (index abh), 4-58
i-4 index power control 4 register (index ach), 4-59 recommended settings, 4-4 reference list in alphabetical order (table), a-1 a-2 reserved register (index 6ah), 4-30 reserved register (index 8bh), 4-46 reserved register (index 8eh), 4-46 reserved register (index 90h), 4-47 reserved register (index 93h), 4-49 reserved register (index 9dh), 4-51 reserved register (index aeh), 4-60 reserved registers (indexes 49?fh), 4-18 reserved registers (indexes 52?fh), 4-20 reserved registers (indexes 78?fh), 4-42 reserved registers (indexes 96?9h), 4-49 resume mask register (index 08h), 1-19 , 4-11 resume status register (index 09h), 1-19 , 4-12 rom configuration 1 register (index 65h), 2-4 , 2-7 , 4-27 rom configuration 2 register (index 51h), 2-8 , 4-20 rom configuration 3 register (index b8h), 2-8 , 2-16 , 4-67 4-68 shadow ram enable 1 register (index 68h), 4-29 shadow ram enable 2 register (index 69h), 4-30 sleep to suspend timer register (index 86h), 1-22 , 1-37 , 4-44 smi enable register (index 41h), 1-30 , 1-31 , 4-13 smi i/o status register (index 42h), 1-30 , 4-14 smi mms page register (index aah), 1-27 , 4-57 smi status register (index 43h), 1-28 , 4-14 software mode control register (index 88h), 1-28 1-29 , 4-45 suspend to off timer register (index 87h), 1-22 , 4-45 uart clock enable register (index 92h), 4-49 version register (index 64h), 4-26 wait state control register (index 63h), 2-4 , 4-25 configuration port registers configuration address register (port 022h), 4-11 configuration data register (port 023h), 4-11 overview, 4-2 configuring ?lansc310 microcontroller clocks (phase-locked loops), 4-8 cpu and pc/at compatibility (table), 4-5 determining bus configuration (table), 4-5 direct memory accesses (table), 4-6 general-purpose and pmc pins, 4-8 interrupts and their mapping (table), 4-6 memory mapping (mms windows) (table), 4-6 parallel port (table), 4-7 pc/at bus and its timing (table), 4-5 power management activities and events (table), 4-9 power management state timers (table), 4-10 power management status (table), 4-9 rom accesses and rom cycles (table), 4-10 smis and smi status (table), 4-10 speed of cpu (table), 4-5 system dram (table), 4-7 uart (table), 4-7 control a register (index 48h), 4-18 control b register (index 77h), 4-42 cpu and pc/at compatibility, controlling (table), 4-5 cpu clock, low-speed, controlling, 1-6 cpu speed, controlling (table), 4-5 cpu status 0 register (index a3h) bit descriptions, 4-54 last pmu mode indicator bits (table), 4-54 reading status of bl2 pin, 1-32 cpu status 1 register (index a4h) bit descriptions, 4-55 present pmu mode indicator bits (table), 4-55 reading pmu mode, 1-9 cpu_idle bit, 4-30 cpuclk high-speed pll mode, 1-4 low-speed pll mode, 1-5 pmu clock speeds (table), 1-6 cts bit, 3-15 d data-path disabling logic, 1-41 dbufoe signal, 4-61 dcts bit, 3-15 ddsr bit, 3-15 device-power-down logic description, 1-29 1-31 smi device-powerdown flowchart (figure), 1-30 dir bit parallel control port (ports 27ah & 37ah), 3-10 parallel control port (ports 27ah, 37ah, & 37eh), 3-9 direct memory access, controlling (table), 4-6 discmd bit, 4-18 disden bit, 4-15 disk drive management registers drive timer register (index 47h), 4-17 i/o wait state register (index 61h), 4-22 4-23
index i-5 floppy disk drive wait states (table), 4-22 hard drive wait states, 4-23 smi enable register (index 41h), 4-13 smi status register (index 43h), 4-14 disk drives, powered-down, 1-29 1-31 disrefoff bit, 4-69 disw bit, 4-27 divider-chain bits, time-base (table), 3-18 divisor latch lower byte (ports 2f8h & 3f8h), 3-12 divisor latch upper byte (ports 2f8h & 3f9h), 3-12 dlab bit, 3-13 dm bit, 3-19 dma access, controlling (table), 4-6 dma clock clock stop feature, 1-41 pmu clock speeds (table), 1-6 dma controller registers dma controller 1 addresses (table), 3-5 dma controller 2 addresses (table), 3-7 dma page registers, 3-7 3-8 dmamms bit, 4-22 dmastclk bit, 4-61 dmws bit, 4-34 documentation contents of manual, xii literature fulfillment service, xii purpose of this manual, xi related amd publications, xii dos chip-select signal doscs wait-state control-bit logic (table), 2-16 high-speed clock rom cycles, 2-15 purpose and use, 2-16 doscs signal accessing rom dos memory, 2-8 address decode (table), 4-68 controlling with rom configuration 3 register (index b8h), 4-67 dos chip-select signal, 2-8 high-speed clock rom cycles, 2-15 number of wait states of doscs cycle (table), 4-67 rom chip-select command gating, 2-14 rom chip-select signal, 2-15 wait-state control-bit logic (table), 2-16 doze mode. see also low-speed to doze timer regis- ter (index 84h). 1-5 1-6 doze to sleep timer register (index 85h) description, 4-44 state-transition timing, 1-22 dr bit, 3-14 dram 80-ns dram support, 2-17 8254-based dram refresh, 2-3 configurations, 2-2 dram bank miss wait state select logic (table), 4-25 dram first cycle wait state select logic (table), 4-25 enhanced page mode, 2-4 memory configuration (dram (table), 4-28 memory initialization example (table), 2-3 page-mode drams, 2-4 registers for setting up (table), 4-7 self-refresh drams, 2-17 slow refresh, 2-3 drive timer register (index 47h) bit descriptions, 4-17 hard drive and floppy disk drive timer setting bit logic (table), 4-18 drlsd bit, 3-15 drq pins as wake-up signals, 1-24 drq0 bit, 4-53 drq1 bit activity mask 1 register (index 75h), 4-40 activity status 1 register (index a0h), 4-53 drq1 signal (table), 1-23 drq2 bit activity mask 1 register (index 75h), 4-40 activity status 1 register (index a0h), 4-53 drq2 signal (table), 1-23 drq3 bit activity mask 1 register (index 75h), 4-40 activity status 1 register (index a0h), 4-53 drq3 signal (table), 1-23 drq5 signal (table), 1-23 drq6 signal (table), 1-23 drq7 signal (table), 1-23
i-6 index drq7?rq5 bits, 4-40 dse bit, 3-19 dsr bit, 3-15 dtr bit, 3-14 dv2?v0 bits, 3-17 dz bit nmi/smi control register (index a5h), 4-56 nmi/smi enable register (index 82h), 4-43 dz0 bit, 4-59 dz1 bit, 4-59 dz2 bit, 4-42 dz3 bit, 4-58 dz4 bit, 4-58 e e0a21 bit, 4-33 e0a22 bit, 4-33 e0a23 bit, 4-31 e1a21 bit, 4-33 e1a22 bit, 4-33 e1a23 bit, 4-31 e2a21 bit, 4-33 e2a22 bit, 4-33 e2a23 bit, 4-31 e3a21 bit, 4-33 e3a22 bit, 4-33 e3a23 bit, 4-31 e4a21 bit, 4-29 e4a22 bit, 4-29 e4a23 bit, 4-31 e5a21 bit, 4-29 e5a22 bit, 4-29 e5a23 bit, 4-31 e6a21 bit, 4-29 e6a22 bit, 4-29 e6a23 bit, 4-31 e7a21 bit, 4-29 e7a22 bit, 4-29 e7a23 bit, 4-31 eb_rmmd0 bit, 4-62 eb_rmmd1 bit, 4-62 eic bit, 3-20 ?lansc310 microcontroller architecture, xi configuring. see configuring ?lansc310 microcon- troller. overview, xi elsi bit, 3-12 emba0 bit, 4-31 emba1 bit, 4-31 emba2 bit, 4-31 emba3 bit, 4-31 emdp00 bit mmsa device 1 register (index 71h), 4-36 mmsb device register (index 73h), 4-38 emdp01 bit mmsa device 1 register (index 71h), 4-36 mmsb device register (index 73h), 4-38 emdp10 bit mmsa device 1 register (index 71h), 4-36 mmsb device register (index 73h), 4-38 emdp11 bit mmsa device 1 register (index 71h), 4-36 mmsb device register (index 73h), 4-38 emdp20 bit mmsa device 1 register (index 71h), 4-36 mmsb device register (index 73h), 4-38 emdp21 bit mmsa device 1 register (index 71h), 4-36 mmsb device register (index 73h), 4-38 emdp30 bit mmsa device 1 register (index 71h), 4-36
index i-7 mmsb device register (index 73h), 4-38 emdp31 bit mmsa device 1 register (index 71h), 4-36 mmsb device register (index 73h), 4-38 emdp40 bit, 4-37 emdp41 bit, 4-37 emdp50 bit, 4-37 emdp51 bit, 4-37 emdp61 bit, 4-37 emdp70 bit, 4-37 emdp71 bit, 4-37 emio0 bit, 4-31 4-32 emio1 bit, 4-31 4-32 emio2 bit, 4-31 4-32 emio3 bit, 4-31 4-32 emsi bit, 3-12 en_14m_pp bit, 4-70 en_mpom bit, 4-70 enacin bit, 4-60 enadin1 bit, 4-56 enadin2 bit, 4-56 enclk bit, 4-49 enfd bit, 4-13 enfstrdos bit function, 4-67 rom dos enable and wait-state select logic (table), 4-67 rom dos wait state select logic (table), 4-19 enfstromcs bit, 4-65 enhanced page mode, 2-4 enhd bit, 4-13 enhit bit, 4-50 enmi bit, 3-21 enmmsa bit, 4-27 enmmsb bit, 4-39 enpio bit, 4-13 enpmcirq0 bit, 4-39 enrame2 bit, 4-66 enrdoscs bit, 4-67 enroma bit, 4-20 enromc bit, 4-27 enromd bit, 4-27 enrome bit, 4-27 enromf bit, 4-27 enselfref bit, 4-65 epmode bit, 4-26 epp-compliant registers. see parallel port interface registers. eppmode bit, 4-61 eppto bit, 3-10 eps bit, 3-13 erdi bit, 3-12 err bit parallel status port (ports 279h & 379h), 3-10 parallel status port (ports 279h, 379h & 3bdh), 3-9 etdei bit, 3-12 external-device control interface 1-14 1-15 definition, 1-2 latched power pin, 1-15 power-management control (pmc4-pmc0) pins, 1-14 1-15 programmable general-purpose pins 2 and 3, 1-15 extir0act bit, 4-61 extsmi pin external smi with multiple devices, 1-31 generating smis, 1-31 extsmiedg bit, 4-61 extsmien bit, 4-61 extsmiste bit, 4-65
i-8 index f fcycwait0 bit dram first cycle wait state select logic (table), 4-25 function, 4-25 fcycwait1 bit dram first cycle wait state select logic (table), 4-25 function, 4-25 fd bit activity status 2 register (index a1h), 4-53 bit descriptions, 4-41 fdsmi bit, 4-14 fdt0 bit, 4-17 fdt1 bit, 4-17 fdt2 bit, 4-17 fdt3 bit, 4-17 fdws0 bit floppy disk drive wait states (table), 4-22 function, 4-22 fdws1 bit floppy disk drive wait states (table), 4-22 function, 4-22 fe bit, 3-14 floppy disk drive management. see disk drive manage- ment registers. fo0 bit, 4-59 fo1 bit, 4-59 fo2 bit, 4-42 fo3 bit, 4-58 fo4 bit, 4-58 frdosws0 bit function, 4-67 rom dos enable and wait-state select logic (table), 4-67 frdosws1 bit function, 4-67 rom dos enable and wait-state select logic (table), 4-67 fstromws0 bit, 4-65 fstromws1 bit, 4-65 function enable 1 register (index b0h) bit descriptions, 4-61 4-62 extsmi pin management, 1-31 latch and buffer logic (table), 4-62 powered-down device smis, 1-31 function enable 2 register (index b1h) bit descriptions, 4-62 dram memory configuration, 2-3 high-speed pll frequency select (table), 4-63 ram mode decode logic (table), 4-63 function enable 3 register (index b4h) 4-66 g gatea20 bit, 4-34 general-purpose i/o 1 register (index 9ch), 4-51 general-purpose i/o 2 register (index 94h) bit descriptions, 4-49 determining state of pgp pins in off mode, 1-7 general-purpose i/o 3 register (index 95h) bit descriptions, 4-49 determining state of pgp pins in off mode, 1-7 general-purpose i/o control register (index 91h) bit descriptions, 4-47 4-48 determining state of pgp pins in off mode, 1-7 general-purpose i/o register (index 89h), 4-46 general-purpose pins. see pgp pins, controlling. gensmi bit, 4-57 h hard disk drive management. see disk drive manage- ment registers. hd bit activity status 2 register (index a1h), 4-53 bit descriptions, 4-41 hdsmi bit, 4-14 hdt0 bit, 4-17 hdt1 bit, 4-17 hdt2 bit, 4-17 hdt3 bit, 4-17 hdtoltch bit, 4-12 hdws0 bit
index i-9 function, 4-22 hard drive wait states (table), 4-23 hdws1 bit function, 4-22 hard drive wait states (table), 4-23 high-speed clock rom cycles, 2-15 high-speed pll mode clock-switching logic, 1-16 1-17 logic flowchart (figure), 1-18 high-speed pll frequency select (table), 4-63 pmu operating-mode transitions, 1-8 purpose and use, 1-4 1-5 shutting off with software, 1-5 high-speed to low-speed timer register (index 83h) description, 4-44 state-transition timing, 1-22 hit-count limit bit logic (table), 4-51 hotrst bit, 3-21 hsa16 bit, 4-50 hsa17 bit, 4-50 hsa18 bit, 4-50 hsa19 bit, 4-50 hspllfq0 bit, 4-62 hspllfq1 bit, 4-62 i i/o activity address 0 register (index 8ch) description, 4-46 pmu operating-mode transitions, 1-8 i/o activity address 1 register (index 8dh) description, 4-46 pmu operating-mode transitions, 1-8 i/o drive type description (table), 4-69 i/o timeout register (index 40h) bit descriptions, 4-12 powered-down device smis, 1-31 i/o wait state register (index 61h) bit descriptions, 4-22 floppy disk drive wait states (table), 4-22 general bus i/o wait states (table), 4-23 hard drive wait states (table), 4-23 id0 bit, 3-12 id1 bit, 3-12 inactivity states and transition intervals (table), 1-10 init bit parallel control port (ports 27ah & 37ah), 3-10 parallel control port (ports 27ah, 37ah & 37eh), 3-9 int bit activity mask 1 register (index 75h), 4-40 activity status 1 register (index a0h), 4-53 interrupt registers interrupt controller 1 i/o addresses (table), 3-4 interrupt controller 2 i/o addresses (table), 3-4 interrupt enable register (ports 2f9h & 3f9h), 3-12 interrupt identification register (ports 2fah & 3fah) bit descriptions, 3-12 interrupt id bit logic (table), 3-13 interrupt redirect logic (table), 4-65 pirq configuration register (index b2h), 4-64 interrupts enabling and specifying mapping (table), 4-6 intiowait bit, 4-25 iocd0 bit, 4-20 iocd1 bit, 4-20 iochck bit, 3-20 ior bit, 4-14 ioreset pin, 1-40 iow bit, 4-14 iows0 bit function, 4-22 general bus i/o wait states (table), 4-23 iows1 bit function, 4-22 general bus i/o wait states (table), 4-23 ip bit, 3-12 irq pins as wake-up signals, 1-24 irq0smi bit, 4-14 irq0smien bit, 4-60 irq1 signal (table), 1-23 irq14 bit, 1-29 irq3 bit, 4-12
i-10 index irq3 signal (table), 1-23 irq3msk bit, 4-11 irq4 bit, 4-12 irq4 signal (table), 1-23 irq4msk bit, 4-11 irq6 bit, 1-29 irq8 bit, 4-12 irq8 signal (table), 1-23 irq8msk bit, 4-11 irqen bit enabling hard-drive interrupt, 1-29 miscellaneous 4 register (index 44h), 4-15 parallel control port (ports 27ah & 37ah), 3-10 parallel control port (ports 27ah, 37ah, & 37eh), 3-9 irqf bit, 3-19 isa bus configurations, 2-5 bus configuration (table), 2-5 ?lansc310 microcontroller bus configurations (fig- ure), 2-5 i/o access command delay, 8-bit (table), 4-20 memory access command delay, 8-bit (table), 4-21 memory-cycle wait states (table) 16-bit, 4-24 8-bit, 4-24 k kb bit activity mask 1 register (index 75h), 4-40 4-41 activity status 1 register (index a0h), 4-53 kbclken bit, 3-20 kbsmien bit smi enable register (index 41h), 4-13 smi i/o status register (index 42h), 4-14 keyboard clock, disabled in sleep mode, 1-7 keyboard. see xt-keyboard interface. l latch and buffer logic (table), 4-62 latched power pin, 1-15 lind0 bit, 4-54 lind1 bit, 4-54 lind2 bit, 4-54 line control register (ports 2fbh & 3fbh) bit descriptions, 3-13 word length bit logic (table), 3-13 line status register (ports 2fdh & 3fdh), 3-14 loop bit, 3-14 low0 bit, 4-52 low1 bit, 4-52 low-speed cpu clock, controlling, 1-6 low-speed duration period select logic (table), 4-52 low-speed pll mode clock-switching logic, 1-16 logic flowchart (figure), 1-18 description, 1-5 low-speed pll mode cpu clock speed select (table), 4-60 pmu operating-mode transitions, 1-8 low-speed to doze timer register (index 84h) description, 4-44 state-transition timing, 1-22 lph pin, 1-15 lph1 bit, 4-54 lpt bit activity mask 2 register (index 76h), 4-41 activity status 2 register (index a1h), 4-53 lsa14 bit, 4-50 lsa15 bit, 4-50 lsa16 bit, 4-50 lsa17 bit, 4-50 lsa18 bit, 4-50 lsa19 bit, 4-50 lsrwcntl bit, 4-18 m mainoff bit, 4-60 manual. see documentation. mcs16 signal, 4-66 , 4-67
index i-11 memadrs0 bit, 4-69 memadrs1 bit, 4-69 memctls0 bit, 4-69 memctls1 bit, 4-69 memdats0 bit, 4-69 memdats1 bit, 4-69 memory configuration 1 register (index 66h) bit descriptions, 4-28 bus option status (table), 4-28 dram memory configuration, 2-3 memory configuration (dram) (table), 4-28 setting up page-mode dram accesses, 2-4 memory configuration 2 register (index b9h) bit descriptions, 4-69 i/o drive type description (table), 4-69 off mode function, 1-7 output drive strength select logic (table), 4-69 memory management. see also memory mapping sys- tem (mms). 16-mbyte address spaces, 2-1 64-mbyte address spaces, 2-1 80-ns dram support, 2-17 dos chip-select signal, 2-16 2-17 doscs wait-state control-bit logic (table), 2-16 high-speed clock rom cycles, 2-15 overview, 2-1 rom bios memory, 2-6 2-7 address initialization (table), 2-6 copy rom contents (figure), 2-7 high memory (figure), 2-6 rom chip-select command gating, 2-14 rom chip-select signal, 2-15 romcs wait-state control-bit logic (table), 2-16 rom dos memory, 2-8 self-refresh drams, 2-17 system memory. see also dram configurations, 2-3 system memory. see also dram, 2-2 2-6 isa and local bus configurations, 2-5 2-6 overview, 2-2 2-3 refresh and wait states, 2-3 2-5 typical at address space (figure), 2-2 wait states and command delays, 2-14 command delay duration for various cycles (table), 2-14 wait states for various cycles (table), 2-15 memory mapping system (mms). see also specific mms bits and registers. 2-9 2-13 memory mapping system (figure), 2-9 mms mapping example (figure), 2-12 mms mapping example settings (table), 2-13 mmsa and mmsb (figure), 2-10 registers for setting up, 2-10 , 4-6 memory write activity lower boundary register (index 9ah) bit descriptions, 4-50 hit-count limit bit logic (table), 4-51 pmu operating-mode transitions, 1-8 memory write activity upper boundary register (index 9bh) bit descriptions, 4-50 pmu operating-mode transitions, 1-8 memr signal disabling, 4-18 quiet bus feature, 1-41 memw signal disabling, 4-18 quiet bus feature, 1-41 merging pmu modes, 1-9 micro power off mode, 1-40 mirrored i/o register conflicts (note), 3-1 miscellaneous 1 register (index 6fh) bit descriptions, 4-34 mms memory range select logic (table), 4-34 4-35 preventing overlap of linear-decode address range, 2-8 miscellaneous 2 register (index 6bh) bit descriptions, 4-30 enabling smis, 1-27 miscellaneous 3 register (index bah) bit descriptions, 4-70 miscellaneous 4 register (index 44h) bit descriptions, 4-15 data-path disabling logic, 1-41 powered-down device smis, 1-29 miscellaneous 5 register (index b3h) bit descriptions, 4-65 controlling number of wait states, 2-16 determining source of smis, 1-28 enabling high-speed clock rate, 2-15 rom bios enable and wait-state select logic (table), 4-66 miscellaneous 6 register (index 70h) bit descriptions, 4-35 generating pmu-activity event with acin pin, 1-34
i-12 index misout bit dram bank miss wait state select logic (table), 4-25 mms memory wait state 1 register (index 62h), 4-23 mms address extension 1 register (index 6ch), 4-31 mms address extension 2 register (index 6eh), 4-33 mms address register (index 6dh) bit descriptions, 4-31 4-32 mmsa base addresses (table), 4-33 mmsa/b page register i/o addresses (table), 4-32 page register contents description (table), 4-32 mms bit, 4-53 mms memory range select logic (table), 4-34 4-35 mms memory wait state 1 register (index 62h) 16-bit isa memory-cycle wait states (table), 4-24 8-bit isa memory-cycle wait states (table), 4-24 bit descriptions, 4-23 setting up page-mode dram accesses, 2-4 mms memory wait state 2 register (index 50h) bit descriptions, 4-19 rom dos command delay select logic (table), 4-19 rom dos wait state select logic (table), 4-19 mms. see memory mapping system (mms). mmsa address extension 1 register (index 67h), 4-29 mmsa device 1 register (index 71h) bit descriptions, 4-36 page 0-3 device select (table), 4-36 mmsa device 2 register (index 72h) bit descriptions, 4-37 page 4-7 device select (table), 4-37 mmsabsel bit, 4-39 mmsb control register (index 74h) bit descriptions, 4-39 enabling sleep mode on battery level 2, 1-33 starting low-speed cpu clock, 1-6 mmsb device register (index 73h) bit descriptions, 4-38 page 0-3 device select (table), 4-38 mmsz0 bit, 4-34 mmsz1 bit, 4-34 mmsz2 bit, 4-34 mmsz3 bit, 4-34 mod0 bit, 4-28 modem control register (ports 2fch & 3fch), 3-14 modem status register (ports 2feh & 3feh), 3-15 mrdly bit, 4-34 ms0 bit function, 4-28 memory configuration (dram) (table), 4-28 ms1 bit function, 4-28 memory configuration (dram) (table), 4-28 ms2 bit function, 4-28 memory configuration (dram) (table), 4-28 n nenlb2 bit, 4-39 nenlb4 bit, 4-39 nfrdosen bit, 4-23 nfromen bit, 4-23 nmi/rtc index address register (port 070h), 3-21 nmi/smi control register (index a5h) description, 4-56 enabling bl1 pin, 1-32 processing nmi or smi source, 1-28 resume pseudocode, 1-39 smi generation by bl2 pin, 1-33 suspend pseudocode, 1-38 suspend/resume operation, 1-36 temporary-on-mode, 1-26 1-27 nmi/smi enable register (index 82h) bit descriptions, 4-43 enabling bl1 pin, 1-32 selecting nmi or smi, 4-43 smi generation by bl2 pin, 1-33 start of smi handler, 1-37 nmis. see also smi and nmi control. overview, 1-2 suspend/resume operation, 1-35 nonmaskable interrupt (nmi). see nmis. o oe bit, 3-14 off mode, 1-7 1-8
index i-13 on bit nmi/smi control register (index a5h), 4-56 nmi/smi enable register (index 82h), 4-43 onclk0 bit, 4-60 onclk1 bit, 4-60 operating-mode transitions, pmu high-speed pll, 1-8 illustration, 1-4 low-speed pll, 1-8 registers for setting activities, 1-8 video pll, 1-8 out1 bit, 3-14 out2 bit, 3-14 output drive strength select logic (table), 4-69 p page 0-3 device select (table) mmsa device 1 register (index 71h), 4-36 mmsb device register (index 73h), 4-38 page 4-7 device select (table), 4-37 page mode enhanced page mode, 2-4 page-mode drams, 2-4 page register contents description (table), 4-32 mmsa/b page register i/o addresses (table), 4-32 pages definition, 2-4 page hits, 2-4 parallel port registers for setting up (table), 4-7 parallel port interface registers, 3-8 3-11 at-compatible mode parallel control port (ports 27ah, 37ah, & 37eh), 3-9 parallel data port (ports 278h, 378h, & 3bch), 3-9 parallel status port (ports 279h, 379h & 3bdh), 3-9 epp-compliant mode parallel control port (ports 27ah & 37ah), 3-10 parallel data port (ports 278h & 378h), 3-10 parallel epp 32-bit data register (ports 27c-27fh & 37c-37fh), 3-11 parallel epp address port (ports 27bh & 37bh), 3-11 parallel status port (ports 279h & 379h), 3-10 overview, 3-8 3-11 pc/at bus. see also bus. controlling pc/at bus and its timing (table), 4-5 determining bus configuration (table), 4-5 pc/at compatibility with cpu, controlling (table), 4-5 pc/at peripheral registers conflicts with mirrored i/o registers (note), 3-1 dma controller registers dma controller 1 addresses (table), 3-5 dma controller 2 addresses (table), 3-7 dma page registers, 3-7 3-8 interrupt controller registers interrupt controller 1 i/o addresses (table), 3-3 interrupt controller 2 i/o addresses (table), 3-4 nmi/rtc index address register (port 070h), 3-21 overview, 3-1 parallel port interface registers, 3-8 3-11 at-compatible mode parallel control port (ports 27ah, 37ah, & 37eh), 3-9 parallel data port (ports 278h, 378h, & 3bch), 3-9 parallel status port (ports 279h, 379h & 3bdh), 3-9 epp-compliant mode parallel control port (ports 27ah & 37ah), 3-10 parallel data port (ports 278h & 378h), 3-10 parallel epp 32-bit data register (ports 27c-27fh & 37c-37fh), 3-11 parallel epp address port (ports 27bh & 37bh), 3-11 parallel status port (ports 279h & 379h), 3-10 overview, 3-8 3-11 uart registers divisor latch lower byte (ports 2f8h & 3f8h, 3-12 divisor latch upper byte (ports 2f8h & 3f9h), 3-12 interrupt enable register (ports 2f9h & 3f9h), 3-12 interrupt identification register (ports 2fah & 3fah), 3-12 3-13 line control register (ports 2fbh & 3fbh), 3-13 line status register (ports 2fdh & 3fdh), 3-14 modem control register (ports 2fch & 3fch), 3-14 modem status register (ports 2feh & 3feh), 3-15 receiver buffer register (ports 2f8h & 3f8h), 3-11 scratch pad register (ports 2ffh & 3ffh), 3-15 transmitter holding register (ports 2f8h & 3f8h), 3-11 xt keyboard data register (port 060h), 3-20
i-14 index port 92 (port 092h), 3-21 port b register (port 061h), 3-20 probing address data with logic analyzer (note), 3-1 programmable interval timer registers, 3-4 real-time clock addressing, 3-16 overview, 3-16 register a (rtc index 0ah), 3-17 3-18 register b (rtc index 0bh), 3-19 register c (rtc index 0ch), 3-19 register d (rtc index 0dh), 3-19 rtc register summary (table), 3-17 rtc index data register (port 071h), 3-21 system timer registers (table), 3-5 pe bit line control register (ports 2fbh & 3fbh), 3-13 line status register (ports 2fdh & 3fdh), 3-14 parallel status port (ports 279h & 379h), 3-10 parallel status port (ports 279h, 379h, & 3bdh), 3-9 periodic-interrupt rate-selection bits (table), 3-18 peripheral-device power programming example, 1-11 1-13 pio timeout settings (table), 1-12 power-management control pin settings (table), 1-12 smi-generation settings for pio access (table), 1-13 pf bit, 3-19 pfws bit dram first cycle wait state select logic (table), 4-25 rom configuration 1 register (index 65h), 4-27 pg0in bit, 4-54 pg0io0 bit, 4-48 pg0io1 bit, 4-48 pg1in bit, 4-55 pg1io0 bit, 4-48 pg1io1 bit, 4-48 pg2io0 bit, 4-48 pg2io1 bit, 4-48 pg3io0 bit, 4-48 pg3io1 bit, 4-48 pgp pins, controlling general-purpose i/o 1 register (index 9ch), 4-51 general-purpose i/o 2 register (index 94h), 1-7 , 4-49 general-purpose i/o 3 register (index 95h), 1-7 , 4-49 general-purpose i/o control register (index 91h), 1-7 , 4-47 4-48 general-purpose i/o register (index 89h), 4-46 registers for setting up (table), 4-8 pgp0dir bit, 4-35 pgp1dir bit, 4-39 pgp2 pin, 1-15 pgp3 pin, 1-15 pie bit, 3-19 pind0 bit, 4-55 pind1 bit, 4-55 pind2 bit, 4-55 pio address register (index 45h) bit descriptions, 4-15 powered-down device smis, 1-29 pio timeout settings example (table), 1-12 pio timer register (index 46h) address range decode logic (table), 4-17 bit descriptions, 4-16 powered-down device smis, 1-29 setting logic (table), 4-16 pio0 bit activity mask 2 register (index 76h), 4-41 activity status 2 register (index a1h), 4-53 pio1 bit activity mask 2 register (index 76h), 4-41 activity status 2 register (index a1h), 4-53 piosmi bit, 4-14 piot0 bit, 4-16 piot1 bit, 4-16 piot2 bit, 4-16 piot3 bit, 4-16 piotoltch bit, 4-12 pirq configuration register (index b2h) bit descriptions, 4-64 interrupt redirect logic (table), 4-65 pmc pins pio timeout settings example (table), 1-12
index i-15 power-management control pin settings (table), 1-12 pmc pins. see power-management control (pmc4-pmc0) pins. pmcsmi bit, 4-14 pmu clock speeds (table), 1-6 pmu control 1 register (index a7h) bit descriptions, 4-56 data-path disabling logic, 1-41 pmu operating-mode transitions, 1-8 pmu control 2 register (index afh) bit descriptions, 4-61 enabling bl1 pin, 1-32 state-transition timer, 1-22 pmu control 3 register (index adh) bit descriptions, 4-60 generating pmu-activity event with acin pin, 1-34 low-speed pll mode cpu clock speed select (table), 4-60 pmu operating-mode transitions, 1-8 pmu mode last pmu mode indicator bits (table), 4-54 pmu mode select logic (table), 4-45 present pmu mode indicator bits (table), 4-55 pmu operating-mode transitions, 1-8 pmu state machine general-purpose control using pmc pins, 1-14 purpose and use, 1-2 pmu status 1 register (index a2h) 4-54 pmu timer. see state-transition timer. pmu. see power management unit (pmu). pmw bit activity mask 2 register (index 76h), 4-41 activity status 2 register (index a1h), 4-53 port 92 (port 092h), 3-21 port b register (port 061h), 3-20 power control 1 register (index 80h) bit descriptions, 4-42 merging pmu modes, 1-9 shutting down low-speed and video plls in doze mode, 1-6 power control 2 register (index 81h) bit descriptions, 4-43 merging pmu modes, 1-9 shutting down low-speed and video plls sleep mode, 1-7 suspend mode, 1-7 power control 3 register (index abh), 4-58 power control 4 register (index ach), 4-59 power management unit (pmu), 1-2 1-13 clock sources, 1-9 components, 1-2 1-3 merging pmu modes, 1-9 operating-mode transitions description, 1-8 illustration, 1-4 power conservation techniques, 1-2 power management modes, 1-3 1-8 doze mode, 1-5 1-6 high-speed pll mode, 1-4 1-5 low-speed pll mode, 1-5 off mode, 1-7 1-8 overview, 1-3 pmu clock speeds (table), 1-6 sleep mode, 1-7 suspend mode, 1-7 programming examples inactivity states and transition intervals (table), 1-10 peripheral-device power, 1-11 1-13 pio timeout settings (table), 1-12 power management control pin settings (table), 1-12 power-management setup, 1-9 1-11 table, 1-11 smi-generation settings for pio accesses (table), 1-13 reading pmu mode, 1-9 power management. see also power management unit (pmu). activity monitors description, 1-19 state transition flowchart (figure), 1-20 auto low-speed logic, 1-40 battery-management logic, 1-32 1-34 ac input status (acin) pin, 1-34 battery level 1 (bl1 ) pin, 1-32 battery level 2 (bl2 ) pin, 1-32 1-33 battery level 3 (bl3 ) pin, 1-33 battery level 4 (bl4 ) pin, 1-33 1-34 functionality of bl4-bl1 (table), 1-32 clock-switching logic, 1-16 1-18 clock startup and shutdown logic, 1-16 logic flowchart (figure), 1-18 cpu/memory clock switching, 1-16 data-path disabling logic, 1-41 dma clock stop, 1-41 external-device control interface, 1-14 1-15 latched power pin, 1-15
i-16 index power-management control (pmc4-pmc0) pins, 1-14 1-15 programmable general-purpose pins 2 and 3, 1-15 micro power-off mode, 1-40 overview, 1-1 quiet bus, 1-41 registers for managing (table), controlling activities and events, 4-9 controlling power management state timers, 4-10 determining power management status, 4-9 resume pseudocode, 1-39 slow refresh, 1-41 smi and nmi control, 1-25 1-31 accesses to powered-down device smi, 1-29 1-31 device-powerdown flowchart (figure), 1-30 enabling smis, 1-27 external smi with multiple devices, 1-31 with single device, 1-31 external smi pin, 1-31 processing flowchart (figure), 1-26 processing nmi or smi source, 1-28 1-29 sources for generating smis, 1-25 state-transition timer, 1-22 1-23 suspend/resume pin logic, 1-34 1-39 avoiding problems, 1-39 capabilities required, 1-35 overview, 1-34 1-35 programming considerations, 1-36 required initialization, 1-37 resume input causing smi, 1-39 resume inputs, 1-35 start of smi handler, 1-37 suspend input causing smi, 1-37 suspend inputs, 1-34 suspend pseudocode, 1-38 techniques, 1-1 temporary-on-mode, 1-26 1-27 treatment of pending smis, 1-31 wake-up logic, 1-23 1-24 powered-down device smis description, 1-29 1-31 smi device-powerdown flowchart (figure), 1-30 power-management control (pmc4-pmc0) pins, 1-14 1-15 general-purpose control using pmu state machine, 1-14 pmc pin functionality (table), 1-14 purpose and use, 1-14 registers for setting up (table), 4-8 timer-controlled shutdown using smi interface, 1-14 1-15 ppbienb bit, 4-61 ppisbi bit, 4-61 ppoen signal, 4-62 prim_ri bit, 4-12 programmable general-purpose pins 2 and 3, see also pgp pins, controlling. 1-15 programmable interval timer registers description, 3-4 system timer registers (table), 3-5 pseudo-suspend mode, 1-9 q quiet bus, 1-41 r ra0 bit, 4-16 ra1 bit, 4-16 ram mode decode logic (table), 4-63 ras0 signal, 2-3 ras1 signal, 2-3 rdoscmdl bit function, 4-19 rom dos command delay select logic (table), 4-19 rdossiz3-rdossiz0 bits functions, 4-67 rom dos linear address decode size select logic (table), 4-68 rdosws0 bit function, 4-19 rom dos wait state select logic (table), 4-19 rdosws1 bit function, 4-19 rom dos wait state select logic (table), 4-19 rdoswsen bit function, 4-19 rom dos command delay select logic (table), 4-19 rom dos wait state select logic (table), 4-19 read only memory. see rom bios memory. reading pmu mode, 1-9 real-time clock addressing, 3-16 overview, 3-16 register a (rtc index 0ah) bit descriptions, 3-17
index i-17 periodic-interrupt rate-selection bits (table), 3-18 time-base divider-chain bits (table), 3-18 register b (rtc index 0bh), 3-19 register c (rtc index 0ch), 3-19 register d (rtc index 0dh), 3-19 rtc register summary (table), 3-17 receiver buffer register (ports 2f8h & 3f8h), 3-11 refresh states 8254-based dram refresh, 2-3 refresh cycle wait states (table), 4-21 refresh initialization example (table), 2-3 refresh interval select logic (table), 4-27 self-refresh drams, 2-17 slow refresh, 1-41 , 2-3 refresh states, 2-3 2-4 refsel bit, 4-56 refsel0 bit function, 4-26 refresh interval select logic (table), 4-27 refsel1 bit function, 4-26 refresh interval select logic (table), 4-27 refws bit, 4-20 register a (rtc index 0ah) bit descriptions, 3-17 periodic-interrupt rate-selection bits (table), 3-18 time-base divider-chain bits (table), 3-18 register b (rtc index 0bh), 3-19 register c (rtc index 0ch), 3-19 register d (rtc index 0dh), 3-19 rescpu bit, 4-34 reserved register (index 6ah), 4-30 reserved register (index 8bh), 4-46 reserved register (index 8eh), 4-46 reserved register (index 90h), 4-47 reserved register (index 93h), 4-49 reserved register (index 9dh), 4-51 reserved register (index aeh), 4-60 reserved registers (indexes 49?fh), 4-18 reserved registers (indexes 52?fh), 4-20 reserved registers (indexes 78?fh), 4-42 reserved registers (indexes 96?9h), 4-49 resin pin, 1-40 resu bit, 4-43 resume bit, 4-56 resume mask register (index 08h) bit descriptions, 4-11 non-cpu activity selection, 1-19 resume status register (index 09h) activity monitoring, 1-19 bit descriptions, 4-12 rfd bit, 3-20 ri bit, 3-15 ri signal (table), 1-23 rimsk bit, 4-11 ring-in wake-ups, 1-24 ring-indicate signals, 1-23 rlsd bit, 3-15 rom bios memory, 2-6 2-7 address initialization (table), 2-6 copying rom contents to dram, 2-7 illustration, 2-7 enable and wait-state select logic (table), 4-66 high memory (figure), 2-6 registers for mapping and controlling (table), 4-10 wait states (table), 4-21 rom chip-select command gating, 2-14 rom chip-select signal high-speed clock rom cycles, 2-15 purpose and use, 2-16 romcs wait-state control-bit logic (table), 2-16 rom configuration 1 register (index 65h) bit descriptions, 4-27 caution when performing read-modify-write-se- quence (note), 2-7 setting up page-mode dram accesses, 2-4 rom configuration 2 register (index 51h) bit descriptions, 4-20 controlling rom-dos address space, 2-8
i-18 index rom configuration 3 register (index b8h) accessing rom-dos address space, 2-8 bit descriptions, 4-67 controlling number of wait states, 2-16 enabling high-speed clock rate, 2-16 rom dos enable and wait-state logic (table), 4-67 rom dos linear address decode size select logic (table), 4-68 rom dos memory, 2-8 command delay select logic (table), 4-19 description, 2-8 enable and wait-state logic (table), 4-67 linear address decode size select logic (table), 4-68 registers for mapping and controlling (table), 4-10 wait state select logic (table), 4-19 rom shadowing, 2-6 romcs signal enabling and disabling, 2-6 2-7 high-speed clock rom cycles, 2-15 rom chip-select command gating, 2-14 rom chip-select signal, 2-15 wait-state control-bit logic (table), 2-16 romdos16 bit, 4-20 romws0 bit, 4-20 romws1 bit, 4-20 rs3?s0 bits, 3-17 rtc index data register (port 071h), 3-21 rtc registers. see real-time clock. rtcsmien bit smi enable register (index 41h), 4-13 smi i/o status register (index 42h), 4-14 rts bit, 3-14 s sacin bit, 4-35 sb bit, 3-13 sc03 bit, 4-29 sc2-sc0 bits, 4-50 sc47 bit, 4-29 sc8b bit, 4-29 sccf bit, 4-29 scratch pad register (ports 2ffh & 3ffh), 3-15 sd03 bit, 4-29 sd47 bit, 4-29 sd8b bit, 4-29 sdcf bit, 4-29 se03 bit, 4-30 se47 bit, 4-30 se8b bit, 4-30 secf bit, 4-30 set bit, 3-19 sf03 bit, 4-30 sf47 bit, 4-30 sf8b bit, 4-30 sfcf bit, 4-30 shadow bit, 4-27 shadow ram enable 1 register (index 68h), 4-29 shadow ram enable 2 register (index 69h), 4-30 shutd bit, 4-25 slct bit parallel status port (ports 279h & 379h), 3-10 parallel status port (ports 279h, 379h, & 3bdh), 3-9 slctin bit, 3-9 sleep mode purpose and use, 1-7 sleep to suspend timer register (index 86h) description, 4-44 initializing for suspend/resume operation, 1-37 state-transition timing, 1-22 slow refresh, 1-41 , 2-3 slp bit, 4-43 slref bit, 4-56 smi and nmi control. see also nmis, smis. 1-25 1-31 accesses to powered-down device smi, 1-29 device-powerdown flowchart (figure), 1-30 enabling smis, 1-27 registers for (table), 1-27
index i-19 external smi with multiple devices, 1-31 with single device, 1-31 external smi pin, 1-31 processing nmi or smi source, 1-28 smi processing flowchart (figure), 1-26 sources for generating smis, 1-28 temporary-on mode, 1-26 1-27 treatment of pending smis, 1-31 smi enable register (index 41h) bit descriptions, 4-13 powered-down device smis, 1-30 1-31 using with i/o timeout register (index 40h), 4-12 smi i/o status register (index 42h) bit descriptions, 4-14 powered-down device smis, 1-30 smi mms page register (index aah) bit descriptions, 4-57 enabling smis, 1-27 smi mms upper page register (index a9h) enabling smis, 1-27 selecting smi or nmi, 4-43 smi status register (index 43h) bit descriptions, 4-14 determining source of smis, 1-28 smia14 bit, 4-57 smia15 bit, 4-57 smia16 bit, 4-57 smia17 bit, 4-57 smia18 bit, 4-57 smia19 bit, 4-57 smia20 bit, 4-57 smia21 bit, 4-57 smia22 bit, 4-57 smia23 bit, 4-57 smis generation by bl2 and bl3 , 1-33 overview, 1-1 , 1-2 registers for controlling and determining status (ta- ble), 4-10 resume input causing smi, 1-39 smi-generation settings for pio access example (ta- ble), 1-13 suspend input causing smi, 1-37 suspend/resume operation, 1-35 start of smi handler, 1-37 timer-controlled shutdown using smi interface, 1-14 1-15 smm ram state-save area resume pseudocode, 1-39 suspend pseudocode, 1-38 software mode control register (index 88h) avoiding incoherency in smi or nmi state-transitions, 1-29 bit descriptions, 4-45 pmu mode select logic (table), 4-45 soutl bit, 4-28 sp bit line control register (ports 2fbh & 3fbh), 3-13 nmi/smi control register (index a5h), 4-56 sp0 bit, 4-59 sp1 bit, 4-59 sp2 bit, 4-43 sp3 bit, 4-58 sp4 bit, 4-58 spc0 bit, 4-45 spc1 bit, 4-45 spc2 bit, 4-45 speed bit, 4-22 spkd bit, 3-20 sqwe bit, 3-19 state machine. see pmu state machine. state-transition timer, 1-22 1-23 definition, 1-2 events causing reset, 1-23 programming with mode timer registers, 1-22 registers for controlling (table), 4-10 state-transitions avoiding incoherency in smi or nmi state-transitions, 1-28 1-29 flowchart (figure), 1-20 stepping level, determining. see version register (in- dex 64h). stp bit, 3-13
i-20 index strobe bit, 3-9 su bit, 4-56 su0 bit, 4-59 su1 bit, 4-59 su2 bit, 4-43 su3 bit, 4-58 su4 bit, 4-58 sus bit, 4-43 sus/res pin. see also suspend/resume operation. overview, 1-2 pmu operating-mode transitions (figure), 1-4 resume input, 1-35 suspend input, 1-35 wake-up events, 1-24 suspend mode automatic entry upon battery level 4, 1-33 1-34 pseudo-suspend mode, 1-9 purpose and use, 1-7 suspend to off timer register (index 87h) state-transition timing, 1-22 suspend/resume operation, 1-34 1-36 avoiding problems, 1-36 programming considerations, 1-35 purpose and use, 1-34 required configuration-register initializations, 1-37 resume input causing smi, 1-39 resume pseudocode, 1-39 start of smi handler, 1-37 suspend input causing smi, 1-37 suspend pseudocode, 1-38 using smis, 1-35 sysclk signal disabled in sleep mode, 1-7 xt-keyboard clock (xtclk), b-2 sysclk speeds (table), 1-6 system management interrupt (smi). see smis. system timer registers (table), 3-5 t t1 bit, 4-52 t2g bit, 3-20 t2out bit, 3-20 temporary-on mode purpose and use, 1-26 1-27 suspend/resume operation, 1-36 temt bit, 3-14 teri bit, 3-15 thre bit, 3-14 time-base divider-chain bits (table), 3-18 timer registers doze to sleep timer register (index 85h), 1-22 , 4-44 high-speed to low-speed timer register (index 83h), 1-22 , 4-44 low-speed to doze timer register (index 84h), 1-22 , 4-44 sleep to suspend timer register (index 86h), 1-22 , 1-37 , 4-44 suspend to off timer register (index 87h), 1-22 , 4-45 timer-controlled shutdown using smi interface, 1-14 1-15 transmitter holding register (ports 2f8h & 3f8h), 3-11 trigger period select logic (table), 4-52 u uart registers converting port 3fdh from read only to read/write, 4-18 divisor latch lower byte (ports 2f8h & 3f8h), 3-12 divisor latch upper byte (ports 2f8h & 3f9h), 3-12 interrupt enable register (ports 2f9h & 3f9h), 3-12 interrupt identification register (ports 2fah & 3fah), 3-12 3-13 line control register (ports 2fbh & 3fbh), 3-13 line status register (ports 2fdh & 3fdh), 3-14 modem control register (ports 2fch & 3fch), 3-14 modem status register (ports 2feh & 3feh), 3-15 receiver buffer register (ports 2f8h & 3f8h), 3-11 registers for setting up uart (table), 4-7 scratch pad register (ports 2ffh & 3ffh), 3-15 transmitter holding register (ports 2f8h & 3f8h), 3-11 uart clock enable register (index 92h), 4-49 uart_en bit, 4-42 uart_iop bit, 4-42 uart_ir3 bit, 4-42 uart_ir4 bit, 4-42
index i-21 uf bit, 3-19 uie bit, 3-19 uip bit, 3-17 v vd bit activity mask 2 register (index 76h), 4-41 activity status 2 register (index a1h), 4-53 version register (index 64h) bit descriptions, 4-26 read functions (table), 4-26 read version stepping level decode (table), 4-26 refresh interval select logic (table), 4-27 write functions (table), 4-26 video clock speeds (table), 1-6 video pll, 1-8 vrt bit, 3-19 w wait state registers i/o wait state register (index 61h) bit descriptions, 4-22 floppy disk drive wait states (table), 4-22 general bus i/o wait states (table), 4-23 hard drive wait states (table), 4-23 mms memory wait state 1 register (index 62h) 16-bit isa memory-cycle wait states (table), 4-24 8-bit isa memory-cycle wait states (table), 4-24 bit descriptions, 4-23 setting up page-mode dram accesses, 2-4 mms memory wait state 2 register (index 50h) bit descriptions, 4-19 rom dos command delay select logic (table), 4-19 rom dos wait state select logic (table), 4-19 wait state control register (index 63h) bit descriptions, 4-25 dram bank miss wait state select logic (table), 4-25 dram first cycle wait state select logic (table), 4-25 setting up page-mode dram accesses, 2-4 wait states and command delays 33-mhz wait states (table), 2-5 command delay duration for various cycles (table), 2-14 enhanced page mode, 2-4 memory-speed initialization example (table), 2-4 page-mode drams, 2-4 rom-bios, rom-dos, and isa cycles, 2-14 wait states for various cycles (table), 2-15 wake-up logic definition, 1-2 events allowed, 1-23 1-24 irq or drq pins, 1-24 ring-in wake-ups, 1-24 temporary-on smi or nmi routine requirements, 1-24 wake-up signal descriptions (table), 1-23 wake-up logic, 1-23 1-24 wlb0 bit, 3-13 wlb1 bit, 3-13 x x1sel bit, 4-61 xt keyboard data register (port 060h), 3-20 xtaluse bit, 4-62 xtclk, b-2 xtkbden bit, 4-60 xt-keyboard interface block diagram, b-1 controlling, b-2 enabled by bit 3 of index 0adh, b-2 i/o map summary, b-2 keyboard data port, b-2 overview, b-1 pins used, b-2 timing, b-3

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