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rti-1 f eatures p complete mil-std-1553b remote terminal interface compliance p dual-redundant data bus operation supported p internal illegalization of selected mode code commands p external illegal command de?ition capability p automatic dma control and address generation p operational status available via dedicated lines or internal status register p asd/enasc (formerly seafac) tested and approved p available in ceramic 84-lead leadless chip carrier and 84-pin pingrid array p full military operating temperature range, -55 c to +125 c, screened to the speci? test methods listed in table i of mil-std-883, method 5004, class b p jan-quali?d devices available figure 1. ut1553b rti functional block diagram mil-std-1553b serial bus transceiver i/o in a out in b out output multiplexing and self test wrap-around logic decoder channel a decoder channel b encoder mux 16 mode code/ sub address command recognition logic control and error logic data transfer logic illegal command memory address control timeout clock and reset logic 2mhz data i/o bus output en memory address outputs control inputs host system address inputs control outputs timeron 12mhz reset ut1553b rti remote terminal interface
rti-2 table of contents 1.0 architecture and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1.1 direct memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1.2 transparent memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 internal register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3 mode codes and subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.4 mil-std-1553b subaddress and mode codes . . . . . . . . . . . . . . . . . . . . . . . .9 1.5 remote terminal address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.6 internal self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.7 power-up and master reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.8 encoder and decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.9 illegal command decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.0 memory map example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.0 pin identification and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0 maximum and recommended operating conditions . . . . . . . . . . . . . . . . . 21 5.0 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.0 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.0 package outline drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
rti-3 1.0 a rchitecture a nd o peration the ut1553b rti is an interface device linking a mil- std-1553 serial data bus and a host microprocessor system. the rtis mil-std-1553b interface includes encoding/ decoding logic, error detection, command recognition, memory address control, clock, and reset circuits. decoders the ut1553b rti contains two separate free-running decoders to insure that all redundancy requirements of mil- std-1553b are met. each decoder receives, decodes, and veri?s biphase manchester ii data. proper frequency and edge skew are also veri?d. command recognition logic the command recognition logic monitors the output of both decoders at all times. recognition of a valid command causes a reset of present interface activity followed by execution of the command. this procedure meets the requirement for superseding valid commands. encoder the encoder receives serial data from the data transfer logic, converts it to manchester ii form with proper synchronization and parity, and passes it to the output and self-test logic. data transfer logic the data transfer logic provides double-buffered 16-bit parallel-to-serial and serial-to-parallel conversion during reception and transmission of data. memory address control the memory address control logic controls the output of the three-state address lines during memory access. in dma system implementations, the memory address control provides rti-generated addresses. in a pseudo-dual-port memory con?uration, the memory address control logic provides either rti-generated or host system addressing. control and error logic the control and error logic performs the following four major functions: - interface control for proper processing of mil- std-1553b commands - error checking of both mil-std-1553b data and rti operation - memory control (dma or pseudo-dual-port) for proper data transfer - operational status and control signal generation output multiplexing and self-test logic this logic directs the output of the encoder to one of four places:- channel a outputs - channel b outputs - channel a decoders during self-test - channel b decoders during self-test clock and reset logic the ut1553b rti requires a 12mhz input clock to operate properly. the rti provides a 2mhz output for the system designer to use. the device provides a hardware reset pin as well as software-generated reset. timer logic the ut1553b rti has a built-in 730ms timer that is activated when the encoder is about to transmit. the timer is reset upon receipt of a valid command, master reset, or a time-out condition. 1.1 host interface con?ure the rti into the host system for either a direct memory or transparent memory access. the following sections discuss the system con?uration for each method of memory management. 1.1.1 direct memory access in the direct memory access con?uration the rti and host arbitrate for the shared 2k x 16 memory space. to request access to memory the rti asserts direct memory request output (dmarq); the system bus arbiter grants the rti access to memory by asserting the direct memory access grant signal (memck ). the system arbiter should not assert the memck signal before the rti has requested access to memory (i.e., dmarq asserted). once granted access to memory, the rti address out (addr out(10:0)), ram chip select (rcs ), ram read/ write (rrd/r wr ), and data bus (data i/o(15:0)) provide the interface signals to control the memory access. figure 2 shows an example of a direct memory access system con?uration; for clarity the interface buffers and logic are excluded. the host microprocessor also gains access to memory by arbitration. take care to insure that bus contention does not occur between the host and rti address buses or memory control signals. to place the rti address out bus in a high impedance state negate the adoen input pin. also note that outputs rcs and rrd/r wr are not three-state outputs. when the rti is not writing to memory, bidirectional data bus data i/o(15:0) is an input (i.e., not actively driving the bus).
rti-4 the host microprocessor gains access to the rti internal registers by controlling input pins cs , ctrl , addr in (10:0), and rd/wr . during message processing the host microprocessor should limit access to rti internal registers. 1.1.2 transparent memory access con?ured in the transparent memory mode the host microprocessor accesses shared memory through the rti. arbitration for access to the bus is performed as discussed in section 1.1.1 of this document. when granted access to memory, the rti asserts memory control signals addr out(10:0), rcs , and rrd/r wr . for host-controlled memory accesses the ram memory address from the host is propagated from the address in bus addr in (10:0) to the address out bus addr out (10:0). memory control signals rd/wr and cs are also propagated through the rti as rrd/r wr and rcs . input ctrl is negated during all transparent memory accesses to prevent the rti from inadvertently performing an internal register access or software reset. while cs is asserted, the rtis bidirectional data bus data i/o (15:0) is an input (i.e., not actively driving bus). the host microprocessor gains access to the rti internal registers by controlling input pins cs , ctrl , addr in (10:0), and rd/wr . during message processing the host microprocessor should limit access to rti internal registers. the host should not assert cs while the rti is performing a memory access. 1.2 internal register description the rti uses three internal registers to allow the host to control the rti operation and monitor its status. the host uses the following inputs control (ctrl ), chip select (cs ), read/write (rd/wr ), and addr in (0) to read the 16-bit system register or write to the 8-bit control register. the control register toggles bits in the mil-std-1553b status word, enables biphase inputs, selects terminal active ?g, and puts the part in self-test. the system register supplies operational status of the ut1553b rti to the host. the last command register saves the command word for a transmit last command mode code, along with operational status from the system register. shared memory host computer rti ut1553b dma controller figure 2. direct memory access con?uration data(15:0) addr(10:0) control control control register (write only) figure 3. transparent memory access con?uration shared memory host computer rti ut1553b dma controller data(15:0) addr in (10:0) control addr out (10:0) control data i/o (15:0)
rti-5 the 8-bit write-only control register manages the operation of the rti. write to the control register by applying a logic zero to cs , ctrl , rd/wr , and addr in (0); if addr in (0) is a logic one a master reset occurs. data is loaded into the control register via i/o pins data(7:0). control register writes must occur 50ns before the rising edge of comstr to latch data in the outgoing status word. system register (read only) the 16-bit read-only system register provides the rti system status. read the system register by applying a logic zero to cs , ctrl , addr in (0), and a logic one to rd/wr . the 16-bit contents of the system register are read from data i/o pins data(15:0). bit number initial condition description 0 [0] channel a enable. a logic one enables channel a biphase inputs. 1 [0] channel b enable. a logic one enables channel b biphase inputs. 2 [0] terminal flag. a logic one sets the terminal flag bit of the status register. 3 [0] system busy. a logic one sets the busy bit of the system register and inhibits rti access to memory. no data words are retrieved or stored; command word is stored. 4 [0] subsystem busy. a logic one sets the subsystem flag bit of the status register. 5 [0] self-test channel select. this bit selects which channel the internal self-test checks; a logic one selects channel a and a logic zero selects channel b. 6 [0] self-test enable. a logic one sets the rti in the internal self-test mode and inhib- its normal operation. internal testing is not visible on biphase output channels. 7 [0] service request. a logic one sets the service request bit of the status register. x srv rq self test subs busy tf ch b en ch a en self ch [ ] de?es reset state control register (write only) msb figure 4. control register x x x x x x x [0] [0] [0] [0] [0] [0] [0] [0] lsb bit number initial condition description 0 [0] mcsa(0). the lsb of the mode code or subaddress as indicated by the logic state of bit 5. 1 [0] mcsa(1). mode code or subaddress as indicated by the state of bit 5. 2 [0] mcsa(2). mode code or subaddress as indicated by the state of bit 5. 3 [0] mcsa(3). mode code or subaddress as indicated by the state of bit 5. 4 [0] mcsa(4). mode code or subaddress as indicated by the state of bit 5. 5 [0] mc /sa. a logic one indicates that bits 4 through 0 are the subaddress of the last command word, and that the last command word was a normal transmit orreceive command. a logic zero indicates that bits 4 through 0 are a mode code, and that the last command was a mode code. 6 [1] channel a/b . a logic one indicates that the most recent command arrived onchannel a; a logic zero indicates that it arrived on channel b.
rti-6 7 [0] channel b enabled. a logic one indicates that channel b is available for both reception and transmission. 8 [0] channel a enabled. a logic one indicates that channel a is available for both reception and transmission. 9 [1] terminal flag enabled. a logic one indicates that the bus controller has not issued an inhibit terminal flag mode code. a logic zero indicates that the bus controller, via the above mode code, is overriding the host sys- tems ability to set the terminal flag bit of the status word. 10 [0] busy. a logic one indicates the busy bit is set. this bit is reset when the systembusy bit in the control register is reset. 11 [0] self-test. a logic one indicates that the rti is in the self-test mode. this bit isreset when the self-test is terminated. 12 [0] ta parity error. a logic one indicates the wrong terminal address parity; it causes the biphase inputs to be disabled and a message error condition. this bit is reset by reloading the terminal address latch with correct parity. 13 [0] message error. a logic one indicates that a message error has occurred since the last system register read. this bit is not reset until the system register has been examined and the message error condition is removed. 14 [0] valid message. a logic one indicates that a valid message has been received since the last system register read. this bit is not reset until the system register has been examined. 15 [0] terminal active. a logic one indicates the device is executing a transmit or receive operation. the state of this bit is the logical nand of the external xmit and rcv pins. mcsa 4 mcsa 3 tapa err mess err val mess mcsa 0 mcsa 1 mcsa 2 self- test term actv busy tfen ch a en ch b en chnl a/b mc / sa figure 5. system registers [0] [0] [0] [0] [0] [0] [1] [0] [0] [1] [0] [0] [0] [0] [0] [0] [ ] de?es reset state system register (read only) msb lsb
rti-7 last command register (read only) the 16-bit read-only last command register provides the host with last command and operational status information. the rti transmits the lower 11 bits of this register along with terminal address upon receipt of a transmit last command mode code. read the last command register by applying a logic zero to cs , ctrl , and a logic one to rd/wr and addr in (0). the 16-bit contents of the last command register are read from data i/o pins data(15:0). 1.3 mode codes and subaddresses the ut1553b rti provides subaddress and mode code decoding meeting mil-std-1553b. in addition, the device has automatic internal illegal command decoding for reserved mil-std-1553b mode codes. upon command word validation and decode, status pins mcsa(4:0) and mc /sa become valid. status pin mc /sa will indicate whether the data pins mcsa(4:0) are mode code or subaddress information. status register bits 5 through 0 contain the same information as pins mcsa(4:0) and mc / sa. the system designer can use signals mcsa(4:0), mc /sa, brdcst , xmit , and rcv to illegalize mode codes, subaddresses, and other message formats via the illegal command (ill comm) input (see ?ure 23 on page 36). the rti will internally decode the following mode codes as illegal: - dynamic bus control - selected transmitter shutdown - override selected transmitter shutdown - all reserved mode codes if the rti receives one of the above mode codes, the rti responds by transmitting a status word with the message error bit set to logic one. mode codes which involve data transfer are processed like receive and transmit commands. the rti will not generate dma request for transmit status word and transmit last command mode codes since the information is stored internal to the rti. the following mode codes require assistance from the host: - synchronize - initiate self-test - reset remote terminal for example, the rti will accept and respond to a reset remote terminal mode code; however it will not perform a reset operation. the host must interpret the mode code and take appropriate action. the rti does not de?e or interpret the following data words associated with mode code commands: - transmit vector word - synchronize with data word - transmit bit word the rti will accept and respond to mode code with data; the host must interpret or de?e the data word. the rti will store or retrieve the data required for mode code command from block #1 of the receive or transmit page . bit number initial condition description 0 through 10 [all 1s] least signi?ant 11 bits of the last command word. 11 [0] busy bit. system register bit 10. 12 [0] self-test. system register bit 11. 13 [1] terminal flag enabled. system register bit 9. 14 [1] channel a/b . system register bit 6. 15 [1] illegal command. the rti illegalized the last command.
rti-8 rti mode code handling procedure t/r mode code function operation 0 10100 selected transmitter shutdown 2 1. command word stored 2. mes err pin asserted 3. message error latch set in system register 4. status word transmitted 0 10101 override selected transmitter shutdown 2 1. command word stored 2. mes err pin asserted 3. message error latch set in system register 4. status word transmitted 0 10001 synchronize (w/data) 1. command word stored 2. data word stored 3. status word transmitted 1 00000 dynamic bus control 2 1. command word stored 2. mes err pin asserted 3. message error latch set in system register 4. status word transmitted 1 00001 synchronize 1 1. command word stored 2. status word transmitted 1 00010 transmit status word 3 1. command word stored 2. status word transmitted 1 00011 initiate self-test 1 1. command word stored 2. status word transmitted 1 00100 transmitter shutdown 1. command word stored 2. alternate bus shutdown 3. status word transmitted 1 00101 override transmitter shutdown 1. command word stored 2. alternate bus enabled 3. status word transmitted 1 00110 inhibit terminal flag bit 1. command word stored 2. terminal flag bit set to zero and disabled 3. status word transmitted 1 00111 override inhibit terminal flag bit 1. command word stored bit 2. terminal flag bit enabled, but not set to logic one 3. status word transmitted 1 01000 reset remote terminal 1 1. command word stored 2. status word transmitted 1 10010 transmit last command word 3 1. status word transmitted 2. last command word transmitted 1 10000 transmit vector word 1. command word stored 2. status word transmitted 3. data word transmitted 1 10011 transmit bit word 1. command word stored 2. status word transmitted 3. data word transmitted notes: 1. further host interaction required for mode code operation. 2. reserved mode code; a) mes err pin asserted, b) message error bit set, c) status word transmitted (me bit set to logic one). 3.status word not affected.
rti-9 1.4 mil-std-1553b subaddress and mode code de?itions 1.5 remote terminal address assign the rti remote terminal address by either a software or hardware exercise. the host assigns the rti remote terminal address by performing a control register write; the terminal address bus (ta(4:0)) is strobed into the rti remote terminal address register upon completion of the control register write. to assign the rti remote terminal address via hardware, use the t alen /parity input pin operating in the terminal latch address enable mode. the terminal address bus is latched into the rti while the t alen is asserted (i.e., logic low). valid remote terminal addresses (rta) include decimal 0 through 31 if broadcast is disabled, 0 through 30 if broadcast is enabled parity checker an address parity check is performed to insure the remote terminal address applied to ta(4:0) was properly latched into the remote terminal address register. to perform a parity check, enable the rti parity circuit via ext test and ext tst ch sel a/b input pins. the parity bit is entered through the t alen /parity input pin operating in the parity mode. input pins ext test and ext tst ch sel a/b control dual-function input pin t alen /parity; see table 2 for description of operation. if a parity error exists, the parity error bit of the system register is set to a logic one, biphase channels a and b are disabled (set to logic zero), the message error bit set to logic one, and the message error pin is asserted. table 1. subaddress and mode code de?itions per mil-std-1553b subaddress field binary (decimal) message format receive transmit description 00000 (00) 1 1 mode code indicator 00001 (01) user de?ed user de?ed 00010 (02) user de?ed user de?ed 00011 (03) user de?ed user de?ed 00100 (04) user de?ed user de?ed 00101 (05) user de?ed user de?ed 00110 (06) user de?ed user de?ed 00111 (07) user de?ed user de?ed 01000 (08) user de?ed user de?ed 01001 (09) user de?ed user de?ed 01010 (10) user de?ed user de?ed 01011 (11) user de?ed user de?ed 01100 (12) user de?ed user de?ed 01101 (13) user de?ed user de?ed 01110 (14) user de?ed user de?ed 01111 (15) user de?ed user de?ed 10000 (16) user de?ed user de?ed 10001 (17) user de?ed user de?ed 10010 (18) user de?ed user de?ed 10011 (19) user de?ed user de?ed 10100 (20) user de?ed user de?ed 10101 (21) user de?ed user de?ed 10110 (22) user de?ed user de?ed 10111 (23) user de?ed user de?ed 11000 (24) user de?ed user de?ed 11001 (25) user de?ed user de?ed 11010 (26) user de?ed user de?ed 11011 (27) user de?ed user de?ed 11100 (28) user de?ed user de?ed 11101 (29) user de?ed user de?ed 11110 (30) user de?ed user de?ed 11111 (31) 1 1 mode code indicator note: 1. refer to mode code assignments per mil-std-1553b
rti-10 the following are examples of sequences used to enter remote terminal addresses into the rti. example 1. hardware-controlled remote terminal address (parity check disabled): state 0, 2, or 3 (i.e., 00, 10, or 11) t alen - asserted (i.e., logic low) ta(4:0) - valid rta example 2. software-controlled remote terminal address (parity check disabled): ext test and ext tst ch sel a/b in state 0, 2, or 3 (i.e., 00, 10, or 11) ctrl - logic zero cs - logic zero rd/wr - logic zero addr in (0) - logic zero t alen - logic one ta(4:0) - valid rta example 3. software controlled remote terminal address (parity check enabled): ext test and ext tst ch sel a/b in state 1 (i.e., 01) ctrl - logic zero cs - logic zero rd/wr - logic zero addr in (0) - logic zero parity - input must provide odd parity for the ta(4:0) bus ta(4:0) - valid rta for examples 1 and 2, enabling the parity check circuit (state 1) after the remote terminal address is stored results in a parity check of the data loaded into the remote terminal address register. 1.6 internal self-test setting bit 6 of the control register to a logic one enables the internal self-test. disable channels a and b at this time to prevent bus activity during self-test by setting bits 0 and 1 of the control register to a logic zero. normal operation is inhibited when internal self-test is enabled. the rtis self-test capability is based on the fact that the mil-std- 1553b status word sync pulse is identical to the command word sync pulse. thus, if the status word from the encoder is fed back to the decoder, the rti will recognize the incoming status word as a command word and thus cause the rti to transmit another status word. after the host invokes self-test, the rti self-test logic forces a status word transmission even though the rti has not received a command word. the status word is sent to decoder a or b depending on the channel the host selected for self-test. the host controls the self-test by periodically changing the bit patterns in the status word being transmitted. writing to the control register bits 2, 3, 4, and 8 changes the status word. monitor the self-test by sampling either the system register or the external status pins (i.e. command strobe (comstr ), transmit (xmit ), receive (rcv )). for a more detailed explanation of internal self-test, consult the utmc publication rti internal self-test routine. 1.7 power-up master reset reset the rti by invoking either a hardware or software master reset after power-up to place the device in a known state. the master reset clears the decoder and encoder registers, the command recognition logic, the control and error logic (which includes the status, control and system registers), the data transfer logic, and the memory address control logic. after reset, con?ure the device for operation via a control register write. table 2. parity checking state # ext test ext tst ch sel a/b function of t alen /parity 0 0 0 terminal address latch enable. active low signal used to latch ta(4:0) into rti. internal parity checker disabled. 1 0 1 parity. internal remote terminal address parity checker enabled. t alen /parity pin func- tions as parity bit for ta(4:0) bus. proper oper- ation requires odd parity. 2 1 0 terminal address latch enable. do not assert ext tst during reset, otherwise self-test is invoked. 3 1 1 terminal address latch enable. do not assert ext tst during reset, otherwise self-test is invoked.
rti-11 perform a hardware reset by asserting the mrst input pin for a minimum of 500ns. during reset negate the ext test pin (i.e., logic low); assertion of the ext test pin forces the rti to enter the external self-test mode of operation. software reset the rti by simultaneously applying a logic zero to input pins cs , rd/wr , and ctrl while the least signi?ant bit of the address input bus is a logic one (addr in (0)=0). 1.8 encoder and decoder the rti interfaces directly to a bus transmitter/receiver via the rti manchester ii encoder/decoder. the ut1553b rti receives the command word from the mil-std-1553b bus and processes it either by the primary or secondary decoder. each decode checks for the proper sync pulse and manchester waveform, edge skew, correct number of bits, and parity. if the command is a receive command, the rti processes each incoming data word for correct word count and contiguous data. if an invalid message error is detected, the message error pin is asserted, the rti ceases processing the remainder (if any) of the message, and it then suppresses status word transmission. upon command validation recognition, the external status outputs are enabled. reception of illegal commands does not suppress status word transmission. a timer precludes transmission greater than 730ms by the assertion of fail-safe timer (timer on ). this timer is reset upon receipt of another valid command. 1.9 illegal command decoding the host has the option of asserting the ill comm pin to illegalize a received command word. on receipt of an illegal command, the rti sets the message error bit in the status word, sets the message error output, and sets the message error latch in the system register. use the following rti outputs to externally decode an illegal command, mode code or subaddress indicator (mc / sa), mode code or subaddress bus mcsa(4:0), command strobe (comstr ), broadcast (brdcst ), etc. (see ?ure 6 pages 11-12). to illegalize a transmit command the ill comm pin is asserted 3.3ms after status goes to a logic one. assertion of the ill comm pin within 3.3ms allows the rti to respond with the message error bit of the outgoing status word at a logic one. for an illegal receive command, the ill comm pin is asserted within 18.2ms after the comstr transitions to a logic zero in order to suppress data words from being stored (suppress dmarq assertions). in addition, the ill comm pin must be at a logic one throughout the reception of the message until status is asserted. if the illegal command is mode code 2, 4, 5, 6, 7, or 18, assert the ill comm pin within 664ns after command strobe (comstr ) transitions to logic zero. asserting the ill comm pin within the 664 nanoseconds inhibits the mode code function. the above timing conditions also apply when the host externally decodes an illegal broadcast command. the host must remove the illegal command condition so that the next command is not falsely decoded as illegal. these requirements are easily met if the comstr output is used to qualify the ill comm input to the rti. p command word cs ds data word p p status word ss ds data word p biphase in biphase out rcv comstr status figure 6a. illegal receive command decoding ill comm 18.2 m s note: 1. illegal command condition; status word message error bit set to logic one, rtimes err pin set to a logic one, rti status re gister message error bit set to logic one. dma activity suppressed
rti-12 2.0 m emory m ap e xample the rti is capable of addressing 2048 x 16 of external memory for message storage. the 2k memory space is divided into two 1k pages and subdivided into 32 blocks of 32 x 16: page 1 (receive): 32 blocks for receive messages (32 x 16) page 2 (transmit): 32 blocks for transmit messages (32 x 16) address decode the rti derives addresses (i.e., data pointers) for external memory directly from the 11 least signi?ant bits of the command word. the address data pointer corresponds to addr out (10:0) during rti memory accesses. t/r = addr out (10) subaddress/mode = addr out (9:5) word count/mode code = addr out (4:0) the t/r bit of the command word becomes the most signi?ant bit of the data pointer; the t/r bit serves to divide the ram into transmit and receive pages of 1k each. the 5-bit subaddress/mode ?ld is used to select 1 of 32 possible message storage blocks within the transmit or receive message page. the 5-bit word count/mode code ?ld acts as a data pointer to select one of 32 locations within the message storage block. multiple word messages are stored from top to bottom within the message storage block. for mode commands, the address data pointer always contains 00000 in the mc /sa ?ld, regardless of whether 00000 or 11111 was received. forcing the mode code ?ld to 00000 reserves the ?st message storage block on both pages (receive and transmit) for mode code messages that require data. the 5-bit mode code speci?s which of the 32 locations within the message storage block to access. p command word cs p status word ss biphase in biphase out xmit status figure 6b. illegal transmit command decoding ill comm 3.3 m s note: 1. illegal command condition; status word message error bit set to logic one, rti mes err pin set to a logic one, rti status register message error bit set to logic one. dma activity suppressed 1.0 m s (min) comstr p cs biphase in mc /sa comstr figure 6c. mode code command decoding ill comm 664ns note: 1. to illegalize mode codes 2, 4, 5, 6, 7, or 18 assert ill comm within 664ns of comstr s transition to logic zero. asserting the ill comm within 664ns inhibits the mode code function. command word
rti-13 for ?rap-around?applications (transmission of data previously received), force the rti to store and receive messages on one memory page. to accomplish one-page operation do not use the t/r output pin. eliminating the t/ r limits the rti access to only one page and the rti will not differentiate between receive and transmit pages. table 3. rti memory map 1: receive memory map 2: transmit memory map block # operation address field (hex) block # operation address field (hex) 1 mode code 1 000 to 01f 1 mode code 1 400 to 41f 2 subaddress 1 020 to 03f 2 subaddress 1 420 to 43f 3 subaddress 2 040 to 05f 3 subaddress 2 440 to 45f 4 subaddress 3 060 to 07f 4 subaddress 3 460 to 47f 5 subaddress 4 080 to 09f 5 subaddress 4 480 to 49f 6 subaddress 5 0a0 to 0bf 6 subaddress 5 4a0 to 4bf 7 subaddress 6 0c0 to 0df 7 subaddress 6 4c0 to 4df 8 subaddress 7 0e0 to 0ff 8 subaddress 7 4e0 to 4ff 9 subaddress 8 100 to 11f 9 subaddress 8 500 to 51f 10 subaddress 9 120 to 13f 10 subaddress 9 520 to 53f 11 subaddress 10 140 to 15f 11 subaddress 10 540 to 55f 12 subaddress 11 160 to 17f 12 subaddress 11 560 to 57f 13 subaddress 12 180 to 19f 13 subaddress 12 580 to 59f 14 subaddress 13 1a0 to 1bf 14 subaddress 13 5a0 to 5bf 15 subaddress 14 1c0 to 1df 15 subaddress 14 5c0 to 5df 16 subaddress 15 1e0 to 1ff 16 subaddress 15 5e0 to 5ff 17 subaddress 16 200 to 21f 17 subaddress 16 600 to 61f 18 subaddress 17 220 to 23f 18 subaddress 17 620 to 63f 19 subaddress 18 240 to 25f 19 subaddress 18 640 to 65f 20 subaddress 19 260 to 27f 20 subaddress 19 660 to 67f 21 subaddress 20 280 to 29f 21 subaddress 20 680 to 69f 22 subaddress 21 2a0 to 2bf 22 subaddress 21 6a0 to 6bf 23 subaddress 22 2c0 to 2df 23 subaddress 22 6c0 to 6df 24 subaddress 23 2e0 to 2ff 24 subaddress 23 6e0 to 6ff 25 subaddress 24 300 to 31f 25 subaddress 24 700 to 71f 26 subaddress 25 320 to 33f 26 subaddress 25 720 to 73f 27 subaddress 26 340 to 35f 27 subaddress 26 740 to 75f 28 subaddress 27 360 to 37f 28 subaddress 27 760 to 77f 29 subaddress 28 380 to 39f 29 subaddress 28 780 to 79f 30 subaddress 29 3a0 to 3bf 30 subaddress 29 7a0 to 7bf 31 subaddress 30 3c0 to 3df 31 subaddress 30 7c0 to 7df 32 unused 3e0 to 3ff 32 unused 7e0 to 7ff notes : 1. receive mode codes with data: - synchronize with data - selected transmitter shutdown (illegal) - override selected transmitter shutdown (illegal) 2. transmit mode codes with data: - transmit vector word - transmit bit word
rti-14 3.0 p in i dentification a nd d escription rcs rrd/r wr rcv xmit mc /sa comstr timer on status mes err ut1553b rti power v dd ground v ss mrst biphase out biphase in biphase in a o terminal address ta0 ta1 ta2 ta3 ta4 t alen /parity mode/code subaddress mcsa0 mcsa1 mcsa2 mcsa3 mcsa4 status signals bcen ill comm cs rd/wr ctrl adoen control signals addr in 0 addr in 1 address bus addr in(10:0) data i/o 12 data i/o 13 data i/o 15 data i/o 0 data i/o 1 data i/o 2 data i/o 3 data i/o 4 data i/o 5 data i/o 6 data i/o 7 data i/o 8 data i/o 9 data i/o 10 data i/o 11 data bus data(15:0) 12mhz biphase in a z biphase in b o biphase in b z biphase out a o biphase out a z biphase out b o biphase out b z clock reset v ss 2mhz ch a/b data i/o 14 figure 7. ut1553b rti pin description addr in 2 addr in 3 addr in 4 addr in 5 addr in 6 addr in 7 addr in 8 addr in 9 addr in 10 dmarq memck dma ext test ext tst ch sel a/b test addr out 0 addr out 1 addr out 2 addr out 3 addr out 4 addr out 5 addr out 6 addr out 7 addr out 8 addr out 9 addr out 10 address bus addr out (10:0) (k3) (k1) (h2) (g3) (g1) (f3) (e1) (f2) (d2) (b1) (b2) (l1) (j2) (h1) (g2) (f1) (e3) (e2) (d1) (c1) (c2) (l9) (k9) (d11) (f11) (b10) (k2) (f10) (k11) (l7) (g10) (k7) (e9) (e10) (c11) (l3) (l5) (l6) (j7) (f9) (e11) (h11) (b11) (k6) (j6) (g11) (d10) (j5) (l4) (k4) (l2) (k5) (b8) (b7) (a7) (c6) (b9) (c10) (a1) (b3) (a2) (a3) (b4) (a4) (c5) (b5) (a5) (a6) (c7) (b6) (a8) (a9) (a10) (a11) (j10) (k10) (g9) (h10) (l10) (l11) (k8) (l8) note: pingrid array numbers are in parentheses. lcc pin numbers are not in parentheses. 27 28 32 30 37 39 33 34 64 62 60 58 56 52 14 16 17 18 19 49 41 22 21 51 38 45 43 23 26 25 44 46 50 15 20 13 9 7 5 3 1 8 8 7 7 7 74 73 72 71 70 69 68 67 66 65 63 61 59 57 55 53 11 10 8 6 4 2 84 82 80 78 76 29 31 48 47 54 12 42 35 24 40 brdcst 36 (j11) (j1)
rti-15 legend for type and active ?lds: ti = ttl input tui = ttl input (pull-up) tdi = ttl input (pull-down) to = ttl output tto = three-state ttl output ttb = three-state ttl bidirectional [ ] - values in parentheses indicate the initialized state of output pin. data bus name pin number type active description lcc pga data i/o 15 53 a11 ttb -- bit 15 (msb) of the bidirectional data bus. data i/o 14 55 a10 ttb -- bit 14 of the bidirectional data bus. data i/o 13 57 a9 ttb -- bit 13 of the bidirectional data bus. data i/o 12 59 a8 ttb -- bit 12 of the bidirectional data bus. data i/o 11 61 b6 ttb -- bit 11 of the bidirectional data bus. data i/o 10 63 c7 ttb -- bit 10 of the bidirectional data bus. data i/o 9 65 a6 ttb -- bit 9 of the bidirectional data bus. data i/o 8 66 a5 ttb -- bit 8 of the bidirectional data bus. data i/o 7 67 b5 ttb -- bit 7 of the bidirectional data bus. data i/o 6 68 c5 ttb -- bit 6 of the bidirectional data bus. data i/o 5 69 a4 ttb -- bit 5 of the bidirectional data bus. data i/o 4 70 b4 ttb -- bit 4 of the bidirectional data bus. data i/o 3 71 a3 ttb -- bit 3 of the bidirectional data bus. data i/o 2 72 a2 ttb -- bit 2 of the bidirectional data bus. data i/o 1 73 b3 ttb -- bit 1 of the bidirectional data bus. data i/o 0 74 a1 ttb -- bit 0 (lsb) of the bidirectional data bus. input address bus name pin number type active description lcc pga addr in 10 75 b2 ti -- bit 10 (msb) of the address input bus. addr in 9 77 b1 ti -- bit 9 of the address input bus. addr in 8 79 d2 ti -- bit 8 of the address input bus. addr in 7 81 f2 ti -- bit 7 of the address input bus. addr in 6 83 e1 ti -- bit 6 of the address input bus. addr in 5 1 f3 ti -- bit 5 of the address input bus. addr in 4 3 g1 ti -- bit 4 of the address input bus. addr in 3 5 g3 ti -- bit 3 of the address input bus. addr in 2 7 h2 ti -- bit 2 of the address input bus. addr in 1 9 k1 ti -- bit 1 of the address input bus. addr in 0 13 k3 ti -- bit 0 (lsb) of the address input bus.
rti-16 ; output address bus name pin number type active description lcc pga addr out 10 76 c2 tto -- bit 10 (msb) of the address output bus. addr out 9 78 c1 tto -- bit 9 of the address output bus. addr out 8 80 d1 tto -- bit 8 of the address output bus. addr out 7 82 e2 tto -- bit 7 of the address output bus. addr out 6 84 e3 tto -- bit 6 of the address output bus. addr out 5 2 f1 tto -- bit 5 of the address output bus. addr out 4 4 g2 tto -- bit 4 of the address output bus. addr out 3 6 h1 tto -- bit 3 of the address output bus. addr out 2 8 j1 tto -- bit 2 of the address output bus. addr out 1 10 j2 tto -- bit 1 of the address output bus. addr out 0 11 l1 tto -- bit 0 (lsb) of the address output bus. remote terminal address inputs name pin number type active description lcc pga ta4 56 b9 tui -- remote terminal address bit 4 (msb). ta3 58 b8 tui -- remote terminal address bit 3. ta2 60 b7 tui -- remote terminal address bit 2. ta1 62 a7 tui -- remote terminal address bit 1. ta0 c6 64 tui -- remote terminal address bit 0. t alen/ parity 52 c10 tui -- remote terminal address latch enable/ remote terminal parity input. function of input is de?ed by he state of pin ext test and ext tst ch sel a/b . for ext test = 0, ext tst ch sel a/b = 1, t alen /parity must provide odd parity for the remote terminal address. for all other states of ext test and ext tst ch sel a/b (i.e., 00, 10, 11) t alen /parity functions as an active low address strobe.
rti-17 mode code/subaddress outputs name pin number description lcc pga mc /sa 21 k6 to -- mode code/subaddress indicator. if mc /sa is low, it indicates that the most recent command word is a mode code command. if mc /sa is high, it indicates that the most recent command word is for a subaddress. this output indicates whether the mode code/subaddress outputs (i.e., mcsa(4:0)) contain mode code or sub- address information. mcsa4 19 k5 to -- mode code/subaddress 4. if mc /sa is low, this pin represents the most signi?ant bit of the the most recent command word (the msb of the mode code). if mc /sa is high, this pin represents the msb of the subaddress. mcsa3 18 j5 to -- mode code/subaddress 3. mcsa2 17 l4 to -- mode code/subaddress 2. mcsa1 16 k4 to -- mode code/subaddress 1. mcsa0 14 l2 to -- mode code/subaddress 0. if mc /sa is low, this pin represents the least signi?ant bit of the the most recent command word. if mc /sa is high, this pin represents the lsb of the sub- address biphase inputs name pin number description lcc pga biphase in a z 39 g9 ti -- receiver - channel a, zero input. idle low manchester input from the 1553 bus transceiver. biphase in a o 37 h10 ti -- receiver - channel a, one input. this input is thecomplement of biphase in a z. biphase in b z 34 j10 ti -- receiver - channel b, zero input. idle low manchester input from the 1553 bus transceiver. biphase in b o 33 k10 ti -- receiver - channel b, one input. this input is the complement of biphase in b z. type active
rti-18 biphase outputs name pin number description lcc pga biphase out a z 28 k8 to -- transmitter - channel a, zero output. this manchester-encoded data output is connected to the 1553 bus transmitter input. the output is idle low. biphase out a o 27 l8 to -- transmitter - channel a, one output. this output is the complement of biphase out a z. the output is idle low. biphase out b z 30 l10 to -- transmitter - channel b, zero output. this manchester-encoded data output is connected to the 1553 bus transmitter. the output is idle low. biphase out b o 32 l11 to -- transmitter - channel b, one output. this output is the complement of biphase out b z. the output is idle low. master reset and clock name pin number description lcc pga mrst 40 g10 tui al master reset. initializes all internal functions of the rti. mrst must be asserted 500 nanoseconds before normal rti operation. (500ns minimum). 12mhz 35 k11 ti -- 12mhz input clock. this is the rti system clock that requires an accuracy greater than 0.01% with a duty cycle from 50% 10%. 2mhz 24 l7 to -- 2mhz clock output. this is a 2mhz output gener- ated by the 12mhz input clock. this clock is stopped when mrst is low. power and ground name pin number description lcc pga v dd 54 b10 pwr -- +5v dc . power supply must be +5v dc 10%. v ss 1 2 42 k2 f10 gnd gnd -- -- ground reference. zero v dc logic ground. type active type active type active
rti-19 control pins name pin number type active description lcc pga cs 44 e9 ti al chip select. active low input for host access of transparent memory or the rti internal registers. in the transparent memory con?uration cs is propa- gated through the rti to the rcs output. ctrl 50 c11 ti al control. the host processor uses the active low ctrl input signal in conjunction with cs and rd/ wr to access the rti internal registers. ctrl is also used in the software assignment of the terminal address and programmed reset. adoen 15 l3 ti al address output enable. when adoen is low the address out bus (addr out (15:0)) is active. if adoen = 1 the address out bus is high impedance. rd/wr 46 e10 ti -- read/write. the host processor uses a high level on this input in conjunction with cs and ctrl to read the rti internal registers. a low level on this input is used in conjunction with cs and ctrl to write to internal rti registers. in the transparent memory con?uration rd/wr is propagated through the rti to the rrd/r wr output. bcen 25 k7 tui al broadcast enable. active low input enables broad- cast commands. ill comm 20 l5 tdi ah illegal command. the host processor uses the ill comm input to inform the rti that the present command is illegal. ill comm is used in conjunc- tion with mcsa(4:0) and mc /sa to de?e system dependent illegal commands.
rti-20 status outputs name pin number type active description lcc pga rcs 43 f9 to al ram chip select. active low output used to enable memory for access. rrd/r wr 45 e11 to -- ram read/write. high output enables memory read, low output enables memory write, used in conjunction with rcs ). normally high output. comstr 22 j6 to al command strobe. comstr is an active low output of 500ns duration identifying receipt of a valid command. timer on 41 g11 to al fail-safe timer. the timer on output pulses low for 730ms when the rti begins transmit- ting (i.e., rising edge of status) to provide a fail-safe timer meeting the requirements of mil-std-1553b. this pulse is reset when comstr goes low or during master reset. in the external self-test mode timer on does not recognize comstr and resets after 730ms. mes err 49 d10 to ah message error. the active high mes err out- put signals that the message error bit in the sta- tus register has been set due to receipt of an invalid command or an error during message sequence. mes err will reset to logic zero on receipt of next valid command. ch a/b 26 l6 to -- channel a/b . output identifying the channel on which the most recent valid command was received. channel a = 1, channel b = 0. xmit 38 h11 to al transmit. active low output identi?s a transmit command message transfer by the rti is in progress. rcv 51 b11 to al receive. active low output identi?s a receive command message transfer by the rti is in progress. brdcst 36 j11 to al broadcast. brdcst is an active low output that identi?s receipt of a valid broadcast com- mand. status 23 j7 to ah status. active high output pulse indicating that the rti is in the process of transmitting a status word.
rti-21 4.0 o perating c onditions absolute maximum ratings 1 (referenced to vss) recommended operating conditions bus arbitration name pin number type active description lcc pga dmarq 47 f11 to ah direct memory access request. active high output requesting rti access to memory. memck 48 d11 ti al memory clock (dma grant). active low input signaling the rti that a memory access is granted. internal to the rti, receipt of memck generates ram chip select and ram read/write signals. ext tst 29 l9 tdi -- external self-test enable. multi-function input pin. in self-test mode forcing this pin high allows the monitoring of self-test activity at the bus stub. when the rti is not in self-test this pin de?es the function of t alen /parity. ext tst ch sel a/b 31 k9 tui -- external self-test channel select. a/b multi- function input pin. in self-test mode forcing this pin high selects the channel on which the self- test is performed (channel a = 1, channel b = 0). when the rti is not in self-test this pin de?es the function of t alen /parity. symbol parameter limits unit v dd dc supply voltage -0.3 to +7.0 v v io voltage on any pin -0.3 to v dd +0.3 v i i dc input current 10 ma t stg storage temperature -65 to +150 c p d maximum power dissipation 300 mw t j maximum junction temperature +175 c q jc thermal resistance, junction-to-case 20 c/w note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specicati on is not recommended. exposure to absolute maximum rating conditions for extended periods may affect device reliability. symbol parameter limits unit v dd dc supply voltage 4.5 to 5.5 v v in dc input voltage 0 to v dd v t c temperature range -55 to +125 c f o operating frequency 12 .01% mhz
rti-22 5.0 dc e lectrical c haracteristics (vdd = 5.0v 10%; -55 c < tc < +125 c) symbol parameter condition minimum maximum unit v il low-level input voltage 0.8 v v ih high-level input voltage 2.0 v i in input leakage current ttl inputs inputs with pull-down resistors inputs with pull-up resistors v in = v dd or v ss v in = v dd v in = v ss -10 110 -2750 10 2750 -110 m a m a m a v ol low-level output voltage i ol = 4ma 0.4 v v oh high-level output voltage i oh = -400 m a 2.4 v i oz three-state output leakage current v o = v dd or v ss -10 +10 m a i os short-circuit output current 1, 2 v dd = 5.5v, v o = v dd v dd = 5.5v, v o = 0v -90 90 ma ma c in input capacitance 3 ?= 1mhz @ 0v 10 pf c out output capacitance 3 ?= 1mhz @ 0v 15 pf c io bidirect i/o capacitance 3 ?= 1mhz @ 0v 25 pf i dd average operating current 1, 4 ?= 12mhz, cl = 50pf 50 ma qi dd quiescent current note 5 1.5 ma notes: 1. supplied as a design limit but not guaranteed or tested. 2. not more than one output may be shorted at a time for a maximum duration of one second. 3. measured only for initial qualication, and after process or design changes that could affect input/output capacitance. 4. includes current through input pull-ups. instantaneous surge currents on the order of 1 ampere can occur during output switc hing. voltage supply should be adequately sized and decoupled to handle a large surge current. 5. all inputs with internal pull-ups or pull-downs should be left open circuit. all other inputs tied high or low. sync bit times command word 5 5 5 1 data word 1 status word sync sync 5 1 remote terminal address subaddress/mode code t/r data word count/ mode code p 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 p data 1 1 1 1 1 1 1 figure 8. mil-std-1553b word formats 16 remote terminal address message error instrumentation service request reserved broadcast command received busy subsystem flag dynamic bus control acceptance terminal flag parity 1 1
rti-23 6.0 ac e lectrical c haracteristics 3, 4 (over recommended operating conditions) to data valid to high z to response - to response to response input - input - input input input input - input to high z to data valid input - to response - parameter symbol bus output out-of-phase output in-phase input notes: 1. timing measurements made at (v ih min + v il max)/2. 2. timing measurements made at (v ol max + v oh min)/2. 3. based on 50pf load. 12 1 2 1 2 v ih min v il max v ih min v il max v oh min v ol max v oh min v ol max v oh min v ol max t a t b t c t d t e t f t g t h t a t b t c t d t e t f t g t h figure 9a. typical timing measurements 90% figure 9b. ac test loads and input waveforms note: 30pf including scope probe and test socket input pulses 10% 10% 90% < 2ns < 2ns 50pf 3v 0v 5v ? i ref (source) v ref i ref (sink)
rti-24 dmarq memck rcs rrd/r wr data bus addr out bus t 10a symbol parameter minimum maximum units addr out valid to dmarq active 3 dmarq active to memck active 2, 3 memck active to rcs active 4 memck inactive to rcs inactive 4 memck active to rrd/r wr active memck inactive to rrd/r wr inactive memck pulse width 1, 2, 4 memck active to data bus valid 4 memck inactive to data bus high impedance 3 883 992 0- -67 -61 -61 -58 83 - - 115 5 101 notes: 1. allows a 20ns data valid set-up time before rcs and rrd/r wr go high. 2. the sum t b + t e must not exceed 18.8ms. 3. supplied as a design limit, but not guaranteed or tested. 4. guaranteed by test. figure 10. rti memory write ns ns ns ns ns ns ns ns ns t 10a t 10b t 10e t 10c t 10h t 10f t 10d t 10i t 10g t 10b t 10c t 10d t 10e t 10f t 10g t 10h t 10i
rti-25 dmarq memck rcs data bus addr out bus symbol parameter minimum maximum units addr out valid to dmarq active 3 dmarq active to memck active 3 memck active to rcs active 4 memck inactive to rcs inactive 4 memck pulse width 1, 2, 4 input data valid to memck inactive 4 input data valid after rcs inactive 4 883 992 0 -67 -61 50 - - 45 5 notes: 1. allows a 20ns data valid set-up time before rcs and rrd/r wr go high. 2. the sum t b + t e must not exceed 18.8ms. 3. supplied as a design limit, but not guaranteed or tested. 4. guaranteed by test. figure 11. rti memory read t 11a 14.9 - - 18.3 ns ns ns ns ns ns m s m s dmarq active to memck inactive 4 t 11h t 11b t 11e t 11c t 11f t 11d t 11g t 11a t 11b t 11c t 11d t 11e t 11f t 11g t 11h
rti-26 addr in (0) symbol parameter minimum maximum units input data valid before write control inactive (set-up time) 3 20 figure 12. control register write timing ns ns ns ns data bus (cntrl + cs + rd/wr ) t 12c 25 20 20 - - - - write control logical or input data valid after write control inactive (hold-time) 3 addr in valid before write control asserts 1, 3 addr in valid after write control negates 2, 3 notes: 1. set-up time required to prevent inadvertent software reset. 2. hold-time required to prevent inadvertent software reset. 3. guaranteed by test. t 12d t 12a t 12b t 12a t 12b t 12c t 12d
rti-27 addr in (0) t 13c symbol parameter minimum maximum units data bus valid after read control valid whilve addr in (0) = 0 or 1 figure 13. system and last command register read timing ns ns ns data bus (cntrl + cs ) - - read control logical or 1, 2 data bus valid after addr in (0) = 0 or 1 while read control = 0 read control negation to data bus high impedance 3 notes: 1. addr in (0) = 0 system register read. 2. addr in (0) = 1 last command register read. 3. supplied as a design limit but not guaranteed or tested. 132 70 101 - t 13b t 13a t 13a t 13b t 13c
rti-28 timer on symbol parameter minimum maximum units status active to timer on active 1 figure 14. rt fail-safe timer signal relationships ns ms ms biphase out - - status timer on active to ?st biphase out transition 1 timer on low pulse width 1 note: 1. supplied as a design limit, but not guaranteed or tested. 31 4 732 t 14a comstr ns comstr active to timer on reset 1 31 1.2 - t 14c t 14b t 14d t 14a t 14b t 14c t 14d
rti-29 cs rcs adoen addr in bus figure 15. rti propagation delays addr out bus memck sym- parameter minimum maximum units cs active to rcs active 2 cs negation to rcs negation 2 rd/wr active to rrd/r wr active 2 rd/wr negation to rrd/r wr negation 2 adoen active to addr out active 2 cs active to addr out valid 2 addr in valid to addr out valid 2 adoen negation to addr out high impedance 1 48 -45 -35 6 6 -44 42 50 note: 1. supplied as a design limit, but not guaranteed or tested. 2. guaranteed by test. ns ns ns ns ns ns ns ns t 15a rd/wr rrd/r wr - cs active to memck active (memck not recognized) 1 13 ns - cs negation to memck active (memck recognized) 1 10 ns - - -40 52 t 15a t 15e t 15i t 15c t 15f t 15g t 15h t 15j t 15dv t 15b t 15b t 15c t 15d t 15e t 15f t 15g t 15h t 15i t 15j
rti-30 comstr figure 16. command word validation t 16a biphase in rcv xmit ch a/b p command brdcst mc /sa mcsa(4:0) addr out 1 mess err symbol parameter minimum maximum units command word parity to comstr and rcv or xmit active 4 comstr pulse width 4 command word parity to ch a/b valid 4 status output signals valid to comstr active 2, 4 mes err reset after comstr active 4 3.67 - 430 745 m s m s ns ns 3.58 2.58 2.66 750 notes: 1. adoen is asserted (i.e., logic low). 2. status signals include brdcst , mc /sa, mcsa(4:0), and addr out. 3. measured from mid-bit parity crossing. 4. supplied as a design limit, but not guaranteed or tested. 3 499 502 ns t 16b t 16c t 16d t 16e t 16a t 16b t 16c t 16d t 16e
rti-31 figure 17. receive command message processing biphase in dmarq status p data symbol parameter minimum maximum units data word parity bit to status word response 1, 3 data word parity bit to dmarq active 2, 3 status active to biphase out active 3 status pulse width 3 9.37 4.98 4.48 m s m s m s 8.80 3.58 3.68 notes: 1. measured from last data word mid-bit parity crossing. 2. measured from transmitted status word sync eld mid-bit crossing. 3. supplied as a design limit, but not guaranteed or tested. 1 biphase out p status 2 sync t 17a rcv 1.24 1.25 m s addr out addr out valid before dmarq (h) 3 - 0.90 m s t 17b t 17c t 17d t 17e t 17a t 17b t 17c t 17d t 17e
rti-32 figure 18. transmitted data timing dmarq sym- parameter minimum maximum units dmarq active to sync ?ld of transmitted data word dmarq active to dmarq active xmit negation after last dmarq active 17.18 m s m s 17.15 - 19.2 note: * supplied as a design limit but not guaranteed or tested. biphase 460 500 m s t 18a t 18c t 18b * t 18a * t 18b * t 18c 20 20 00 xmit
rti-33 figure 19. mode command message processing biphase in data/cmd symbol parameter minimum maximum units response time biphase in to bi- phase out 2 command word parity bit to comstr asser- tion 1 3.67 m s m s 3.58 8.80 9.37 notes: 1. measured from data or command word mid-bit parity crossing. 2. measured from transmitted status word sync eld mid-bit crossing. * supplied as a design limit but not guaranteed or tested. 1 biphase t 19a mes err * * t 19g t 19a t 19b p status sync 2 t 19c t 19b t 19e t 19f t 19d status active to biphase out active m s 1.24 1.25 * t 19c status pulse width m s 4.48 4.98 * t 19d command word parity bit to xmit assertion m s 3.58 3.67 * t 19e xmit pulse width for mode code reception m s 1.00 - * t 19f command word parity bit to mes err as- sertion m s 6.57 6.68 * t 19g comstr status xmit p
rti-34 figure 20. message error biphase in p data symbol parameter minimum maximum units data word parity bit to mes err assertion 1 command word parity bit to mes err assertion rt to rt transfer 2 23.63 m s m s 23.50 55.4 55.5 notes: 1. measured from last data word mid-bit parity crossing. 2. no response from transmitter. * supplied as a design limit but not guaranteed or tested. 1 mes err t 20a biphase in p rcv cmd 1 p xmit cmd mes err * * t 20b t 20a t 20b
rti-35 ut1553b rti host subsystem addr in (10:0) data(15:0) control ut63m125 1553 transceiver 1553 bus a 1553 bus b figure 21. rti general system diagram (idle low interface) figure 22. rti transceiver interface diagram biphase channel a biphase channel b rti in o in z out o out z timer on utmc 63m125 channel a channel b txin- txinhb rxout rxout txin txin rxout rxout txin txin in o in z out o out z ch a/b logic
rti-36 illegal command decoder rti figure 23. mode code/subaddress illegalization circuit mc /sa mcsa0 mcsa1 mcsa2 mcsa3 mcsa4 comstr brdcst rcv xmit ill comm p command c p status word ss biphase in biphase out rc comstr dmarq memck rc rrd/r wr addr out bus data bus status valid valid figure 24. receive command with two data words d data p d data p
rti-37 p command cs ds data word p p status word ss ds data word biphase in biphase out xmit comstr dmarq memck rcs rrd/r wr addr out bus data bus status valid valid figure 25. transmit command with two data words
rti-38 p ackage o utline d rawings l l k h g f e d c b a 1234567891011 figure 26a. ut1553b rti pingrid array con?uration (bottom view) l l l l l l l l l1 l1 k k k k k k k k k k1 k1 j j j j1 j1 h h h1 h1 g g g1 g1 f f f1 f1 e e e1 e1 d d d1 d1 c c c1 c1 b b b b b b b b b b1 b1 a a a a a a a a a a1 a1 c c c j j j g f e g f e f1 addr out 5 f2 addr in 7 f3 addr in 5 f9 rcs f10 v ss f11 dmarq g1 addr in 4 g2 addr out 4 g3 addr in 3 g9 biphase in a z g10 mrst g11 timer on h1 addr out 3 h2 addr in 2 h10 biphase in a o h11 xmit c1 addr out 9 c2 addr out 10 c5 data i/o 6 c6 ta 0 c7 data i/o 10 c10 t alen /parity c11 ctrl d1 addr out 8 d2 addr in 8 d10 mes err d11 memck e1 addr in 6 e2 addr out 7 e3 addr out 6 e9 cs e10 rd/wr e11 rrd/r wr a1 data i/o 0 a2 data i/o 2 a3 data i/o 3 a4 data i/o 5 a5 data i/o 8 a6 data i/o 9 a7 ta 1 a8 data i/o 12 a9 data i/o 13 a10 data i/o 14 a11 data i/o 15 b1 addr in 9 b2 addr in 10 b3 data i/o 1 b4 data i/o 4 b5 data i/o 7 b6 data i/o 11 b7 ta 2 b8 ta 3 b9 ta 4 b10 v dd b11 rcv j1 addr out 2 j2 addr out 1 j5 mcsa 3 j6 comstr j7 status j10 biphase in b z j11 brdcst k1 addr in 1 k2 v ss k3 addr in 0 k4 mcsa 1 k5 mcsa 4 k6 mc /sa k7 bcen k8 biphase out a z k9 ext tst ch sel a/b k10 biphase in b o k11 12mhz l1 addr out 0 l2 mcsa 0 l3 adoen l4 mcsa 2 l5 ill comm l6 ch a/b l7 2mhz l8 biphase out a l9 ext test l10 biphase out b l11 biphase out b
rti-39 1 addr in 5 2 addr out 5 3 addr in 4 4 addr out 4 5 addr in 3 6 addr out 3 7 addr in 2 8 addr out 2 9 addr in 1 10 addr out 1 11 addr out 0 12 v ss 13 addr in 0 14 mcsa0 15 adoen 16 mcsa1 17 mcsa2 18 mcsa3 73 data i/o 1 74 data i/o 0 75 addr in 10 76 addr out 10 77 addr in 9 78 addr out 9 79 addr in 8 80 addr out 8 81 addr in 7 82 addr out 7 83 addr in 6 84 addr out 6 19 mcsa 4 20 ill comm 21 mc/sa 22 comstr 23 status 24 2mhz 25 bcen 26 ch a/b 27 biphase out a o 28 biphase out a z 29 ext test 30 biphase out b z 31 ext tst ch sel a/b 32 biphase out b o 33 biphase in b o 34 biphase in b z 35 12mhz 36 brdcst 37 biphase in a o 38 xmit 39 biphase in a z 40 mrst 41 timer on 42 v ss 43 rcs 44 cs 45 rrd/r wr 46 rd/wr 47 dmarq 48 memck 49 mes err 50 ctrl 51 rcv 52 talen/parity 53 data i/o 15 54 v dd 55 data i/o 14 56 ta4 57 data i/o 13 58 ta3 59 data i/o 12 60 ta2 61 data i/o 11 62 ta1 63 data i/o 10 64 ta0 65 data i/o 9 66 data i/o 8 67 data i/o 7 68 data i/o 6 69 data i/o 5 70 data i/o 4 71 data i/o 3 72 data i/o 2 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 16 19 32 31 30 29 28 27 26 25 24 23 22 21 20 18 17 15 14 13 12 74 1110 9 8 7 6 5 4 3 2 1 8483 8281 80797877 7675 figure 26b. ut1553b rti chip carrier con?uration (top view)
packaging -1 package selection guide note: 1. 84lcc package is not available radiation-hardened. product rti rtmp rtr bcrt bcrtm bcrtmp rts xcvr 24-pin dip (single cavity) x 36-pin dip (dual cavity) x 68-pin pga x x 84-pin pga x x x x 1 144-pin pga x 84-lead lcc x x x 1 36-lead fp (dual cavity) (50-mil ctr) x 84-lead fp x x 132-lead fp x x
packaging-2 1 144-pin pingrid array e 1.565 0.025 -b- d 1.565 0.025 -a- 0.080 ref. (2 places) 0.040 ref. 0.100 ref. (4 places) a 0.130 max. q 0.050 0.010 a a l 0.130 0.010 pin 1 i.d. (geometry optional) -c- (base plane) b 0.018 0.002 0.030 0.010 c a b c side view top view 0.003 min. typ. d1/e1 1.400 0.100 typ. e pin 1 i.d. (geometry optional) 2 r p n m l k j h g f e d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 notes: 1. true position applies to pins at base plane (datum c). 2. true position applies at pin tips. 3. all package finishes are per mil-m-38510. 4. letter designations are for cross-reference to mil-m-38510. bottom view
packaging -3 132-lead flatpack (25-mil lead spacing) side view top view bottom view a-a detail a 0.018 max. ref. 0.014 max. ref. (at braze pads) l 0.250 min. ref. lead kovar see detail a a a c 0.005 + 0.002 - 0.001 a 0.110 0.006 d1/e1 0.950 0.015 sq. d/e 1.525 0.015 sq. pin 1 i.d. (geometry optional) e 0.025 notes: 1. all package finishes are per mil-m-38510. 2. letter designations are for cross-reference to mil-m-38510. s1 0.005 min. typ.
packaging-4 84- lcc side view top view bottom view a-a notes: 1. all package finishes are per mil-m-38510. 2. letter designations are for cross-reference to mil-m-38510. l/l1 0.050 0.005 typ. b1 0.025 0.003 e 0.050 e1 0.015 min. pin 1 i.d. (geometry optional) j 0.020 x 455 ref. h 0.040 x 45_ ref. (3 places) d/e 1.150 0.015 sq. a 0.115 max. a1 0.080 0.008 a a pin 1 i.d. (geometry optional)
packaging -5 84-lead flatpack (50-mil lead spacing) side view top view bottom view a-a d/e 1.810 0.015 sq. notes: 1. all package finishes are per mil-m-38510. 2. letter designations are for cross-reference to mil-m-38510. detail a d1/e1 1.150 0.012 sq. a 0.110 0.060 a a c 0.007 0.001 lead kovar see detail a pin 1 i.d. (geometry optional) b 0.016 0.002 l 0.260 min. ref. s1 0.005 min. typ. 0.050 e 0.014 max. ref. (at braze pads) 0.018 max. ref.
packaging-6 84-pin pingrid array side view top view bottom view a-a d 1.100 0.020 e 1.100 0.020 -b- -a- a 0.130 max. q 0.050 0.010 l 0.130 0.010 a a -c- (base plane) b 0.018 0.002 pin 1 i.d. (geometry optional) 1.000 d1/ e 0.100 typ. 0.003 min. l k j h g f e d 1 2 3 4 5 6 7 8 9 10 11 notes: 1. true position applies to pins at base plane (datum c). 2. true position applies at pin tips. 3. all packages finishes are per mil-m-38510. 4. letter designations are for cross-reference to mil-m-38510. pin 1 i.d. (geometry optional) 1 0.030 0.010 c a b c 2
packaging -7 side view top bottom view a-a d 1.100 0.020 pin 1 i.d. (geometry optional) l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 notes: 1 true position applies to pins at base plane (datum c). 2 true position applies at pin tips. 3. all packages finishes are per mil-m-38510. 4. letter designations are for cross-reference to mil-m-38510. pin 1 i.d. (geometry optional) d1/e1 1.00 0.003 min. typ. e 0.100 typ. a 0.130 max. q 0.050 0.010 l 0.130 0.010 a a -a- -b- e 1.100 0.020 -c- (base plane) 68-pin pingrid array 0.030 0.010 c a b 1 2 c ? ? b 0.010 0.002
packaging-8 d 1.800 0.025 36-lead flatpack, dual cavity (100-mil lead spacing) top view end view e 0.750 0.015 notes: 1 all package finishes are per mil-m-38510. 2. it is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. a thermally conductive material such as mereco xln-589 or equivalent should be used. 3. letter designations are for cross-reference to mil-m-38510. pin 1 i.d. (geometry optional) l 0.490 min. b 0.015 0.002 e 0.10 c 0.008 + 0.002 - 0.001 q 0.080 0.010 (at ceramic body) a 0.130 max.
packaging -9 36-lead flatpack, dual cavity (50-mil lead spacing) top e 0.700 + 0.015 notes: 1. all package finishes are per mil-m-38510. 2. it is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. a thermally conductive material such as mereco xln-589 or equivalent should be used. 3. letter designations are for cross-reference to mil-m-38510. c 0.007 + 0.002 - 0.001 q 0.070 + 0.010 (at ceramic body) a 0.100 max. end d 1.000 0.025 b 0.016 + 0.002 e 0.050 pin 1 i.d (geometry optional) l 0.330 min.
packaging-10 36-lead side-brazed dip, dual cavity top view end view e 0.590 0.012 notes: 1. all package finishes are per mil-m-38510. 2. it is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. a thermally conductive material such as mereco xln-589 or equivalent should be used. 3. letter designations are for cross-reference to mil-m-38510. pin 1 i.d. (geometry optional) side view s1 0.005 min. d 1.800 0.025 s2 0.005 max. e 0.100 a 0.155 max. l/l1 0.150 min. c 0.010 + 0.002 - 0.001 e1 0.600 + 0.010 (at seating plane) b 0.018 0.002
packaging -11 e 0.590 0.015 s1 0.005 min. s2 0.005 max. top view pin 1 i.d. (geometry optional) d 1.200 0.025 side view a 0.140 max. l/l1 0.150 min. 0.100 e notes: 1. all package finishes are per mil-m-38510. 2. it is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. a thermally conductive material such as mereco xln-589 or equivalent should be used. 3. letter designations are for cross-reference to mil-m-38510. end view c 0.010 + 0.002 - 0.001 e1 0.600 + 0.010 (at seating plane) b 0.018 0.002 24-lead side-brazed dip, single cavity
ordering information ut1553b rti remote terminal interface: lead finish: (a) = solder (c) = gold (x) = optional case outline: (z) = 84 pin pga class designator: (b) = jan class q device type 01 = 10% to 35% clock duty cycle drawing number: jm38510/555 total dose: (-) = none federal stock class designator: no options 5962 * * * * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an "x" is specified when ordering, part marking will match the lead finish and will be either "a" (solder) or "c" (gold).
ut1553b rti remote terminal interface lead finish: (a) = solder (c) = gold (x) = optional screening: (c) = military temperature (p) = prototype package type: (g) = 84 pin pga modifier: rti = 10% to 35% clock duty cycle utmc core part number ut1553b - * * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an "x" is specified when ordering, part marking will match the lead finish and will be either "a" (solder) or "c" (gold). 3. mil temp range flow per utmc?s manufacturing flows document. devices are tested at -55 c , room temperature, and 125 c . 4. prototpe flow per utmc?s document manufacturing flows and are tested at 25 c only. lead finish is gold only. 5. prototypes and reduced high-reliability devices are only available with 40% to 60% clock duty cycle.

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