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1 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation sp6120b optimized for single supply, 3v - 5.5v applications high efficiency: greater than 95% possible "anyfet tm" technology: capable of switching either pfet or nfet high side switch selectable discontinuous or continuous conduction mode fast transient response from window comparator 16-pin tssop, small size ac curate 1% reference over line, load and temperature accurate 10% frequency accurate, rail to rail, 43mv, over-current sensing resistor programmable frequency resistor programmable output voltage low quiescent current: 950 a, 10 a in shutdown hiccup over-current protection capacitor programmable soft start guaranteed boost voltage to enhance high side nfet low voltage, anyfet tm , synchronous ,buck controller ideal for 2a to 10a, high performance, dc-dc power converters applications dsp microprocessor core i/o & logic industrial control distributed power low voltage power description the sp6120b is a fixed frequency, voltage mode, synchronous pwm controller designed to work from a single 5v or 3.3v input supply. sipex's unique "anyfet tm" technology allows the sp6120b to be used for resolving a multitude of price/performance trade-offs. it is separated from the pwm controller market by being the first controller to offer precision, speed, flexibility, protection and efficiency over a wide range of operating conditions. sp6120b nc enable isp isn v fb comp ss r osc bst gh swn gnd pgnd gl v cc prog nmos high side drive prog = gnd enable cp 100pf cz 4.7nf rz 15k c ss 0.33 f r osc 18.7k cv cc 2.2 f v in mbr0530 c bst 1 f qt 3.3v v in c in 330 f x 2 rs 22.1k cs 39nf l1 2.5 h 1.9v 1a to 8a v ou t rf 5.23k c out 470 f x 3 ri 10k qb ds c b 1 f sp6120b nc enable isp isn v fb comp ss r osc bst gh swn gnd pgnd gl v cc prog pmos high side drive prog = v cc enable cp 100pf cz 4.7nf rz 15k c ss 0.33 f r osc 18.7k cv cc 2.2 f v in qt1 3.3v v in c in 330 f x 2 rs 22.1k cs 39nf l1 2.5 h 1.9v 1a to 8a v ou t rf 5.23k c out 470 f x 3 ri 10k qb ds 1 2 16 15 14 13 12 11 3 4 5 6 7 8 10 9 n/c enable isp isn v fb comp ss r osc bst gh swn gnd pgnd gl v cc prog sp6120b 16 pin tssop qt, qb = fairchild fds6690a qt1 = fairchild fds6375 (pmos only) l1 = panasonic etqp6f2r5sfa ds = stmicroelectronics stps2l25u c in = sanyo 6tpb330m c out = sanyo 4tpb470m now available in lead free packaging
2 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation electrical characteristics unless otherwise specified: 3.0v < v cc <5.5v, 3.0v < bst < 13.2v, r osc = 18.7k ? , c comp = 0.1 f, c ss = 0.1 f, enable = 3v, cgh = cgl = 3.3nf, v fb = 1.25v, isp = isn = 1.25v, swn = gnd = pgnd = 0v, -40 c < t amb <85 c (note 1) absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v cc ............................................................................... 7v bst ........................................................................ 13.2v bs t- swn .................................................................... 7v swn .................................................................. -1v to 7v gh ..................................................... -0.3v to bst +0.3v gh-swn ..................................................................... 7v all other pins ....................................... -0.3v to v cc +0.3v peak output current < 10 s gh, gl ........................................................................ 2a operating temperature range sp6120c ................................................ 0 c to +70 c sp6120e .............................................. -40 c to +85 c junction temperature, t j ...................................... +125 c storage temperature range .................. -65?c to +150?c power dissipation lead temperature (soldering 10 sec) ................... +300?c esd rating ........................................................ 2kv hbm parameter conditions min typ max units quiescent current v cc supply current no switching - 0.95 1.8 ma v cc supply current (disabled) enable = 0v - 5 20 a bst supply current no switching, v bst = v cc -120 a no switching, v cc = 5v, v bst = 10v - 100 150 a error amplifier error amplifier transconductance 600 s comp sink current v fb = 1.35v, comp = 0.5v, no faults 15 35 65 a comp source current v fb = 1.15v, comp = 1.6v 15 35 65 a comp output impedence 3 m ? v fb input bias current - 60 100 na reference error amplifier reference trimmed with error amp in unity gain 1.238 1.250 1.262 v v fb 3% low comparator 3 %v ref v fb 3% high comparator 3 %v ref oscillator & delay path oscillator frequency 270 300 330 khz oscillator frequency #2 r osc = 10.2k ? 450 500 550 khz duty ratio loop in control -100% dc possible 95 % r osc voltage information only - moves 0.65 v with oscillator trim minimum gh pulse width v cc > 4.5v, ramp up comp 120 250 ns voltage > 0.6v until gh starts switching
3 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation electrical characteristics unless otherwise specified: 3.0v < v cc <5.5v, 3.0v < bst < 13.2v, r osc = 18.7k ? , c comp = 0.1 f, c ss = 0.1 f, enable = 3v, cgh = cgl = 3.3nf, v fb = 1.25v, isp = isn = 1.25v, swn = gnd = pgnd = 0v, -40 c < t amb <85 c (note 1) note 1: specifications to -40 c are guaranteed by design, characterization and correlation with statistical process control. parameter conditions min typ max units softstart ss charge current v ss = 1.5v 25 50 70 a ss discharge current v ss = 1.5v 2 5 7 a comp discharge current v comp = 0.5v, fault initiated 200 500 - a comp clamp voltage v fb < 1.0v, vss = 2.5v 2.0 2.4 2.8 v ss ok threshold 1.7 2.0 2.2 v ss fault reset 0.2 0.25 0.3 v ss clamp voltage 2.0 2.4 2.8 v over current & zero current comparators over current comparator rail to rail common mode input 32 43 54 mv threshold voltage isn, isp input bias current - 60 250 na zero current comparator visp - visn 2 mv threshold uvlo v cc start threshold 2.75 2.85 2.95 v v cc stop threshold 2.65 2.75 2.9 v enable enable threshold on 1.45 off 0.65 v enable pin source current 0.6 4 9 a gate driver gh rise time v cc > 4.5v - 40 110 ns gh fall time v cc > 4.5v - 40 110 ns gl rise time v cc > 4.5v - 40 110 ns gl fall time v cc > 4.5v - 40 110 ns gh to gl non-overlap time v cc > 4.5v 0 60 140 ns gl to gh non-overlap time v cc > 4.5v 0 60 140 ns v bst ok threshold v cc = 3.0v, fb=1.15v, search gl high 4.0 4.8 5.0 v v cc = 5.5v, fb=1.15v, search gl high 7.3 7.8 8.3 v forced gl on v bst < v bst ok threshold, fb =1.15v 200 350 650 ns
4 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation pin description name function pin number 1 n/c no connection 2 enable ttl compatible input with internal 4ua pullup. floating or venable> 1.5v will enable the part, venable < 0.65v disables part. 3 isp current sense positive input: rail to rail input for over-current detection, 43mv threshold with 10 s (typ) response time. 4 isn current sense negative input: rail to rail input for over-current detection. 5v fb feedback voltage pin: inverting input of the error amplifier and serves as the output voltage feedback point for the buck converter. the output voltage is sensed and can be adjusted through an external resistor divider. 6 comp error amplifier compensation pin: a lead lag network is typically connected to this pin to compensate the feedback loop. this pin is clamped by the ss voltage and is limited to 2.8v maximum. 7s s soft start programming pin: this pin sources 50 a on start-up. a 0.01 f to 1 f capacitor on this pin is typically enough capacitance to soft start a power supply. in addition, hiccup mode timing is controlled by this pin through the 5 a discharge current. the ss voltage is clamped to 2.7v maximum. 8r osc frequency programming pin: a resistor to ground is used to program frequency. typical values - 18,700 ? , 300khz; 10,200 ? , 500khz. 9 prog programming pin: prog = gnd; mode = nfet/continous prog = 68k ? to gnd; mode = nfet/discontinous prog = vcc; mode = pfet/continous prog = 68k ? to vcc; mode = pfet/discontinous 10 v cc i.c. supply pin: esd structures also hooked to this pin. properly bypass this pin to pgnd with a low esl/esr ceramic capacitor. 11 gl synchronous fet driver: 1nf/20ns typical drive capability. 12 pgnd power ground pin: used for power stage. connect directly to gnd at i.c. pins for optimal performance. 13 gnd ground pin: main ground pin for i.c. 14 swn switch node reference: high side mosfet driver reference. can also be tied to gnd for low voltage applications. 15 gh high side mosfet driver: can be nfet or pfet depending on program mode. 1nf/20ns typical drive capability. maximum voltage rating is referenced to swn. 16 bst high side driver supply pin. when v bst is less than v bst ok threshold, gl is forced to turn on for at least 300ns. this is intended for enough time to charge the bst capacitor.
5 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation block diagram application schematic figure 1. schematic 3.3v to 1.9v power supply qt, qb = fairchild fds6690a l1 = panasonic etqp6f2r5sfa ds = stmicroelectronics stps2l25u + - + - - + - + - + - + - + + - synchronous driver driver logic soft start & hiccup logic s q r set dominant f ault latch s q r program logic window comparator logic + - t off enable gnd v fb comp v cc isp isn reference ss 2.85 v on 2.75 v off 430mv 3 4 2 13 5 6 10 ss 2v v fb 3% low enable v fb 1.25v gm error amplifier v fb zero crossing detect 250mv ss 7 i charge 0.65v 12 8 pgnd r osc 11 14 15 16 9 continuous/ discontinuous nfet/pfet on 100% off 100% reset dominant pwm latch qpwm f ault f (khz) = 5.7e6/r osc ( ? ) + - 10 s ovc uvlo 1v ramp 3% 3% - + prog bst gh swn - + gl x 10 c in = sanyo 6tpb330m c out = sanyo 4tpb470m sp6120b nc enable isp isn v fb comp ss r osc bst gh swn gnd pgnd gl v cc prog nmos high side drive prog = gnd enable cp 100pf cz 4.7nf rz 15k c ss 0.33 f r osc 18.7k cv cc 2.2 f v in mbr0530 c bst 1 f qt 3.3v v in c in 330 f x 2 rs 22.1k cs 39nf l1 2.5 h 1.9v 1a to 8a v ou t rf 5.23k c out 470 f x 3 ri 10k qb ds c b 1 f
6 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation efficiency (%) 50 60 70 80 90 100 0246 output current (a) 810 figure 2. efficiency vs. output current figure 3. load regulation figure 4. load step response: 0.4a to 2a figure 5. load step response: 0.4a to 7a typical performance characteristics refer to circuit in figure 1 with v in = 3.3v; v out = 1.9v, r osc = 18.7k ? , and t amb = +25 c unless otherwise noted. figure 6. start-up response: 5a load 1.875 1.880 1.885 1.890 1.895 1.900 1.905 1.910 1.915 1.920 1.925 012345 load current (a) v out (v) v out gate high i out (1a/div) v out gate high i out (5a/div) v out v in soft start i in (1a/div) figure 7. overcurrent: 9a load v out v in soft start i out (5a/div)
7 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation typical performance characteristics unless otherwise specified: v cc = bst = enable = 3.3v, r osc = 18.7k ? , c comp = 0.1 f, c ss = 0.1 f, cgh = cgl = 3.3nf, v fb = 1.25v, isp = isn = 1.25v, swn = gnd = pgnd = 0v, t amb = 25 c. figure 8. error amplifier reference vs. temperature figure 9. overcurrent comparator threshold voltage vs. temperature figure 10. ss charge current vs. temperature with v ss = 1.5v figure 11. ss discharge current vs. temperature with v ss = 1.5v figure 12. v fb 3% high comparator vs. temperature figure 13. v fb 3% low comparator vs. temperature -0.20 -0.10 0.00 0.10 0.20 0.30 -40 -15 10 35 60 85 1.25v ref (%) temperature ( c) -47 -40 -15 10 35 60 85 ss charge ( a) -46 -45 -44 temperature ( c) 5.00 5.05 5.10 5.15 5.20 5.25 -40 -15 10 35 60 85 ss discharge ( a) temperature ( c) 2.6 2.8 3.0 3.2 3.4 3.6 -40 -15 10 35 60 85 temperature ( c) v fb high (% v ref ) -3.2 -3.0 -2.8 -2.6 -2.4 -2.2 -40 -15 10 35 60 85 temperature ( c) v fb low (% v ref ) -40 -15 10 35 60 85 overcurrent (mv) 40 42 44 temperature ( c) 46 48 38
8 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation figure 14. v cc start threshold vs. temperature figure 15. v cc stop threshold vs. temperature figure 16. oscillator frequency vs. temperature figure 17. oscillator frequency vs. r osc with v cc = 5v and cgh = cgl = open. 2.900 -40 -15 10 35 60 85 v cc start (v) temperature ( c) 2.875 2.850 2.825 2.800 2.850 -40 -15 10 35 60 85 v cc stop (v) temperature ( c) 2.825 2.800 2.775 2.750 302 -40 -15 10 35 60 85 frequency (khz) temperature ( c) 301 300 299 298 200 300 400 500 600 700 800 510152 02530 frequency (khz) r osc (k ? ) typical performance characteristics unless otherwise specified: v cc = bst = enable = 3.3v, r osc = 18.7k, c comp = 0.1 f, c ss = 0.1 f, cgh = cgl = 3.3nf, v fb = 1.25v, isp = isn = 1.25v, swn = gnd = pgnd = 0v, t amb = 25 c. theory of operation general overview the sp6120b is a constant frequency, voltage mode pwm controller for low voltage, dc/dc step down converters. it has a main loop where an external resistor (r osc ) sets the frequency and the driver is controlled by the comparison of an error amp output (comp) and a 1v ramp signal. the error amp has a transconductance of 600 s, an output impedance of 3 m ? , an internal pole at 2 mhz and a 1.25v reference input. although the main control loop is capable of 0% and 100% duty cycle, its response time is limited by the external component selection. therefore, a sec- ondary loop, including a window comparator positioned 3% above and below the reference, has been added to insure fast response to line and load transients. a unique ?ipple & frequency independent?algorithm, added to the secondary loop, insures that the window comparator does not interfere with the main loop during normal operation. in addition to receiving driver com- mands from the main and secondary loops, the driver logic is also controlled by the program- ming logic, fault logic and zero crossing comparator. the programming logic tells the driver logic whether the controller is using a pfet or nfet high side driver as well as whether the controller is operating in continuous or dis- continuous mode. the fault logic holds the high and low side drivers off if v cc dips below 2.75v, if an over current condition exists, or if the part is disabled through the enable pin. the zero crossing comparator turns the lower driver off
9 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation if the conduction current reaches zero and the driver logic has made an attempt to turn the lower driver on and the programming logic is set for discontinuous mode. lastly, the 4 ? driv- ers have internal gate non-overlap circuitry and are designed to drive mosfets associated with converter designs in the 5a to 10a range. typi- cally the high side driver is referenced to the swn pin; further improving the efficiency and performance of the converter. enable low quiescent mode or ?leep mode?is initi- ated by pulling the enable pin below 650mv. the enable pin has an internal 4 a pull-up current and does not require any external inter- face for normal operation. if the enable pin is driven from a voltage source, the voltage must be above 1.45v in order to guarantee proper ?wake?operation. assuming that v cc is above 2.85v, the sp6120b transitions from ?leep mode?to ?wake mode?in about 20 s to 30 s and from ?wake mode?to ?leep mode?in a few microseconds. sp6120b quiescent current in sleep mode is 20 a maximum. during sleep mode, the high side and low side mosfets are turned off and the comp and ss pins are held low. bootstrap circuit when sp6120b is programmed to drive a high side n channel mosfet, a bootstrap circuit is required to generate a voltage higher than v in to fully enhance the top mosfet. a typical boot- strap only requires a capacitor and diode shown as c bst and d bst in the application circuit on the front page. when the bottom mosfet q b is turned on, d bst is forward biased and charges the c bst close to v in . when the top mosfet turn on, the switch node swings to the v in voltage. now the voltage at the bst pin is 2*v in and d bst is reverse biased. the bst pin voltage powers the high side mosfet driver, and thus the gh output goes up to 2*v in to provide a v ds equal to v in . under certain conditions, the bottom mosfet may not turn on long enough to replenish c bst voltage. therefore, when the top mosfet turns on, the bst pin may not be high enough to fully enhance the switch. to prevent this operation, sp6120b monitors the bst pin voltage in refer- ence to the v cc voltage. when the bst pin voltage is less than v bst ok threshold, the controller forces the gl to turn on for mini- mum gl on at the end of the switching cycle. this provides enough time to recharge the c bst and ensures the proper operation of the boot- strap circuit. uvlo assuming that the enable pin is either pulled high or floating, the voltage on the v cc pin then determines operation of the sp6120b. as v cc rises, the uvlo block monitors v cc and keeps the high side and low side mosfets off and the comp and ss pins low until v cc reaches 2.85v. if no faults are present, the sp6120b will initiate a soft start when v cc exceeds 2.85v. hysteresis (about 100mv) in the uvlo comparator pro- vides noise immunity at start-up. soft start (see figures on next page) soft start is required on step-down controllers to prevent excess inrush current through the power train during start-up. typically this is managed by sourcing a controlled current into a program- ming capacitor (on the ss pin) and then using the voltage across this capacitor to slowly ramp up either the error amp reference or the error amp output (comp). the control loop creates nar- row width driver pulses while the output voltage is low and allows these pulses to increase to their steady-state duty cycle as the output voltage increases to its regulated value. as a result of controlling the inductor volt*second product during start-up, inrush current is also controlled. the presence of the output capacitor creates extra current draw during start-up. simply stated, dv out /dt requires an average sustained current in the output capacitor and this current must be considered while calculating peak inrush current and over current thresholds. since the sp6120b ramps up the error amp reference voltage, an expression for the output capacitor current can be written as: ic out = (c out /c ss ) * (v out /1.25) * 50 a general overview: continued
10 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation time 3% low enable voltage v(v cc ) 0v swn v oltage v(v cc ) 0v faul t reset voltage v(v cc ) 0v inductor current i load 0v error amplifier reference v oltage 0v 1.25v v out = v(eamp ref)* (1+rf/ri) ss voltage 0v 0.25v 0.7v 2.0v 2.4v dv ss /dt = 50 a/c ss v(isp) - v(isn) 0v 250mv v(v cc ) 0v 0v 2.0v ss voltage fa ult voltage 2.4v 43mv as the figure shows, the ss voltage controls a variety of signals. first, provided all the external fault conditions are removed, the fault latch is reset and the ss cap begins to charge. when the ss voltage reaches around 0.3v, the error amp refer- ence begins to track the ss voltage while maintain- ing the 0.3v differential. as the ss voltage reaches 0.7v, the driver begins to switch the high side and low side mosfets with narrow pulses in an effort to keep the converter output regulated. as the error amp reference ramps upward, the driver pulses widen until a steady state value is reached. t he ?ump?in the inductor current transfer curve is indicative of excess charge current incurred due to the finite prop agation delay of the controller. when the ss voltage reaches 2.0v, the second- ary loop including the 3% window comparator is enabled. lastly, the ss voltage is clamped at 2.4v, ending the soft start charge cycle. hiccup mode when the converter enters a fault mode, the driver holds the high side and low side mosfets off for a finite period of time. provided the part is enabled, this time is set by the discharge of the ss capacitor. the discharge time is roughly 10 times the charge interval thereby giving the power supply plenty of time to cool during an over current fault. the driver off-time is pre- dominantly determined by the discharge time. restart will occur just like a normal soft start cycle. however, if a fault occurs during the soft start charge cycle, the fault latch is immediately set, turning off the high side and low side mosfets. the mosfets remain off during the remainder of the charge cycle and subse- quent discharge cycle of the ss capacitor. again, provided there are no external fault conditions, the fault latch will be reset when the ss voltage reaches 250 mv. over current protection the sp6120b over current protection scheme is designed to take advantage of three popular detection schemes: sense resistor, trace resis- tor or inductor sense. because the detection threshold is only 43mv, both trace resistor and inductor sense become attractive protection schemes. the inductor sense scheme adds no additional dc loss to the converter and is an excellent alternative to rdson based schemes;
11 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation 0v 0v 0a 0v 0v 0a continuous load current gh, gl v oltage discontinuous load current gh, gl v oltage time providing continuous current sensing and flex- ible mosfet selection. an internal, 10 s filter conditions the over current signal from tran- sients generated during load steps. in addition, because the over current inputs, isp and isn, are capable of rail to rail operation, the sp6120b provides excellent over current protection dur- ing conditions where v in approaches v out . zero crossing detection in some applications, it may be undesirable to have negative conduction current in the induc- tor. this situation happens when the ripple cur- rent in the inductor is higher than the load cur- rent. therefore, the sp6120b provides an option for ?iscontinuous?operation. if the program logic (see next section) is set for discontinuous mode, then the driver logic looks at the zero crossing comparator and the state of the lower gate driver. if the low side mosfet was ?n and v(isp)-v(isn) < 0 then the low side mosfet is immediately turned off and held off until the high side mosfet is turned ?n? when the high side mosfet turns ?n?, the driver logic is reset. the following figures show continuous and discontinuous operation for a converter with an nfet high side mosfet. discontinuous vs. continuous mode the discontinuous mode is used when better light load efficiency is desired, for example in portable applications. additionally, for power supply sequencing in some applications the dc- dc converter output is pre-charged to a voltage through a switch at start-up, and discontinuous operation would be required to prevent reverse inductor current from discharging the pre-charge voltage. the continuous mode is preferable for lower noise and emi applications since the discontinuous mode can cause ringing of the switch node voltage when it turns both switches off. another example where continuous mode could be required is one where the inductor has an extra winding used for an over-winding regu- lator and thus continuous conduction is neces- sary to produce this second output voltage. program logic the program pin (prog) of the sp6120b adds a new level of flexibility to the design of dc/dc converters. a 10 a current flows either into or out of the program pin depending on the initial potential presented to the pin. if no resistor is present, the program logic simply looks at the potential on the pin, sets the mode to ?ontinu- ous?and programs nfet or pfet high side drive accordingly. if the 68k ? resistor is present, the voltage drop across the resistor signals the sp6120b to put the driver logic in ?iscontinu- ous?mode. with one pin and a 68k ? resistor, the sp6120b can be configured for a variety of operating modes: over current protection: continued
12 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation 0v max dc load current min 0a output v oltage v out reset set v(v cc ) main loop 3% high latch on 0v v(v cc ) 3% low latch on . 3% high sync. 3% high 3% low sync. 3% low 1.25v cross. time e l b a t h t u r t c i g o l m a r g o r p n i p m a r g o r pt e f p r o t e f ne d o m d n g o t t r o h st e f ns u o u n i t n o c k 8 6 ? d n g o tt e f ns u o u n i t n o c s i d v o t t r o h s c c t e f ps u o u n i t n o c k 8 6 ? v o t c c t e f ps u o n i t n o c s i d the nfet/pfet programmability is for the high side mosfet. when designing dc/dc converters, it is not always obvious when to use an nfet with a charge pump or a simple pfet for the high side mosfet. often, the controller has to be changed, making performance evalua- tions difficult. this difficulty is worsened by the limited availability of true low voltage control- lers. in addition, by also programming the mode, continuous or discontinuous, switch mode power designs that are successful in bus applications can now find homes in portable applications. secondary loop (3% window comparator) dsp, microcontroller and microprocessor appli- cations have very strict supply voltage require- ments. in addition, the current requirements to these devices can change drastically. linear regulators, typically the workhorse for dc/dc step-down, do a great job managing accuracy and transient response at the expense of effi- ciency. on the other hand, pwm switching regulators typically do a great job managing efficiency at the expense of output ripple and line/load step response. the trick in pwm controller design is to emulate the transient re- sponse of the linear regulator. of course improving transient response should be transparent to the power supply designer. very often this is not the case. usually the very circuitry that improves the controllers transient response adversely interferes with the main pwm loop or complicates the board level design of the power converter. the sp6120b handles line/load transient re- sponse in a new way. first, a window compara- program logic: continued tor detects whether the output voltage is above or below the regulated value by 3%. then, a proprietary ?ipple & frequency independent algorithm synchronizes the output of the win- dow comparator with the peak and valley of the inductor current waveform. 3% low detection is synchronized with inductor current peak; 3% high detection is synchronized with the inductor current valley. however, in order to eliminate any additional loops, the current peak and valley are determined by the edges associated with the on-time in the main loop. the set pulse corre- sponding to the start of an on-time indicates a
13 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation gate driver test conditons 5v 90% 10% gh (gl) 2v 5v gh (gl) 2v non-overlap rise time f all time 90% 10% v(bst) 0v gh v oltage v(v cc ) 0v gl v oltage v(v cc = v in ) swn v oltage ~0v ~v(diode) v ~2v(v in ) bst v oltage ~v(v in ) time current valley and the reset pulse corresponding to the end of an on-time indicates a current peak. in effect, the main loop determines the status of the secondary loop. notice that the output voltage appears to coast toward the regulated value during periods where the main loop would be telling the drivers to switch. it is during this interval that the 3% window comparator has taken control away from the main loop. the main loop regains control only if the output voltage crosses through its regulated value. also notice where the 3% com- parator takes over. the output voltage is consid- ered ?igh?only if the trough of the ripple is above 3%. the output voltage is considered ?ow?only if the peak of the ripple is below 3%. by managing the secondary loop in this fashion, the sp6120b can improve the transient response of high performance power converters without causing strange disturbances in low to moderate performance systems. driver logic signals from the pwm latch (qpwm), fault latch (fault), program logic, zero crossing comparator, and 3% window comparators all flow into the driver logic. the following is a truth table for determining the state of the gh and gl voltages for given inputs: e l b a t h t u r t c i g o l r e v i r d t l u a f1 100000000 r o m w p q p m o c % 3 xx 11000000 t e f p / t e f nnpnpn pnpnp c s i d / t n o cx xx xc c dddd s s o r c o r e zx x xxxx0 0 1 1 h g01100 10 10 1 l g0 00 0 111100 the qpwm and 3% comparators are grouped together because 3% low is the same as qpwm = 1 and 3% high is the same as qpwm = 0. output drivers the driver stage consists of one high side, 4 ? driver, gh and one low side, 4 ? , nfet driver, gl. as previously stated, the high side driver can be configured to drive a pfet or an nfet high side switch. the high side driver can also be configured as a switch node referenced driver. due to voltage constraints, this mode is mandatory for 5v, single supply, high side nfet applica- tions. the following figure shows typical driver waveforms for the 5v, high side nfet design. as with all synchronous designs, care must be taken to ensure that the mosfets are properly chosen for non-overlap time, peak current capa- bility and efficiency. secondary loop (3% window comparator): continued
14 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation applications information inductor selection there are many factors to consider in selecting the inductor including cost, efficiency, size and emi. in a typical sp6120b circuit, the inductor is chosen primarily for value, saturation current and dc resistance. increasing the inductor value will decrease output voltage ripple, but degrade transient response. low inductor values pro- vide the smallest size, but cause large ripple currents, poor efficiency and more output ca- pacitance to smooth out the larger ripple cur- rent. the inductor must also be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. a good compro- mise between size, loss and cost is to set the inductor ripple current to be within 20% to 40% of the maximum output current. the switching frequency and the inductor oper- ating point determine the inductor value as follows: (max) (max) (max) ) ( out r s in out in out i k f v v v v l ? = where: f s = switching frequency k r = ratio of the ac inductor ripple current to the maximum output current the peak to peak inductor ripple current is: l f v v v v i s in out in out pp (max) (max) ) ( ? = once the required inductor value is selected, the proper selection of core material is based on peak inductor current and efficiency require- ments. the core material must be large enough not to saturate at the peak inductor current 2 (max) pp out peak i i i + = and provide low core loss at the high switching frequency. low cost powdered iron cores have a gradual saturation characteristic but can intro- duce considerable ac core loss, especially when the inductor value is relatively low and the ripple current is high. ferrite materials, on the other hand, are more expensive and have an abrupt saturation characteristic with the induc- tance dropping sharply when the peak design current is exceeded. nevertheless, they are pre- ferred at high switching frequencies because they present very low core loss and the design only needs to prevent saturation. in general, ferrite or molypermalloy materials are better choice for all but the most cost sensitive appli- cations. the power dissipated in the inductor is equal to the sum of the core and copper losses. to mini- mize copper losses, the winding resistance needs to be minimized, but this usually comes at the expense of a larger inductor. core losses have a more significant contribution at low output cur- rent where the copper losses are at a minimum, and can typically be neglected at higher output currents where the copper losses dominate. core loss information is usually available from the magnetic vendor. the copper loss in the inductor can be calculated using the following equation: winding rms l cu l r i p 2 ) ( ) ( = where i l(rms) is the rms inductor current that can be calculated as follows: i l(rms) = i out(max) 1 + 1 ( i pp ) 2 3 i out(max) output capacitor selection the required esr (equivalent series resis- tance) and capacitance drive the selection of the type and quantity of the output capacitors. the esr must be small enough that both the resis- tive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage. during an output load transient, the output capacitor must supply all the addi- tional current demanded by the load until the sp6120b adjusts the inductor current to the new value. therefore the capacitance must be large
15 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation enough so that the output voltage is held up while the inductor current ramps up or down to the value corresponding to the new load current. additionally, the esr in the output capacitor causes a step in the output voltage equal to the esr value multiplied by the change in load current. because of the fast transient response and inherent 100% and 0% duty cycle capabil- ity provided by the sp6120b when exposed to output load transient, the output capacitor is typically chosen for esr, not for capacitance value. the output capacitor? esr, combined with the inductor ripple current, is typically the main contributor to output voltage ripple. the maxi- mum allowable esr required to maintain a specified output voltage ripple can be calculated by: pp out esr i v r ? where: ? v out = peak to peak output voltage ripple i pp = peak to peak inductor ripple current the total output ripple is a combination of the esr and the output capacitance value and can be calculated as follows: ? v out = ( i pp (1 ?d) ) 2 + (i pp r esr ) 2 c out f s where: f s = switching frequency d = duty cycle c out = output capacitance value recommended capacitors that can be used ef- fectively in sp6120b applications are: low- esr aluminum electrolytic capacitors, os-con capacitors that provide a very high performance/ size ratio for electrolytic capacitors and low- esr tantalum capacitors. avx tps series and kemet t510 surface mount capacitors are popu- lar tantalum capacitors that work well in sp6120b applications. poscap from sanyo is a solid electrolytic chip capacitor that has low esr and high capacitance. for the same esr value, poscap has lower profile compared with tantalum capacitor. input capacitor selection the input capacitor should be selected for ripple current rating, capacitance and voltage rating. the input capacitor must meet the ripple current requirement imposed by the switching current. in continuous conduction mode, the source cur- rent of the high-side mosfet is approximately a square wave of duty cycle v out /v in . most of this current is supplied by the input bypass capacitors. the rms value of input capacitor current is determined at the maximum output current and under the assumption that the peak to peak inductor ripple current is low, it is given by: i cin(rms) = i out(max) d(1 - d) the worse case occurs when the duty cycle d is 50% and gives an rms current value equal to i out /2. select input capacitors with adequate ripple current rating to ensure reliable opera- tion. the power dissipated in the input capacitor is: ) ( 2 ) ( cin esr rms cin cin r i p = this can become a significant part of power losses in a converter and hurt the overall energy transfer efficiency. the input voltage ripple primarily depends on the input capacitor esr and capacitance. ignor- ing the inductor ripple current, the input voltage ripple can be determined by: 2 ) ( ) ( (max) ) ( in in s out in out max out cin esr out in v c f v v v i r i v ? + = ? the capacitor type suitable for the output ca- pacitors can also be used for the input capaci- tors. however, exercise extra caution when tan- talum capacitors are considered. tantalum ca- pacitors are known for catastrophic failure when exposed to surge current, and input capacitors
16 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation are prone to such surge current when power supplies are connected ?ive?to low impedance power sources. certain tantalum capacitors, such as avx tps series, are surge tested. for ge- neric tantalum capacitors, use 2:1 voltage derat- ing to protect the input capacitors from surge fall-out. mosfet selection the losses associated with mosfets can be divided into conduction and switching losses. conduction losses are related to the on resis- tance of mosfets, and increase with the load current. switching losses occur on each on/off transition when the mosfets experience both high current and voltage. since the bottom mosfet switches current from/to a paralleled diode (either its own body diode or a schottky diode), the voltage across the mosfet is no more than 1v during switching transition. as a result, its switching losses are negligible. the switching losses are difficult to quantify due to all the variables affecting turn on/off time. how- ever, the following equation provides an ap- proximation on the switching losses associated with the top mosfet driven by sp6120b. s out in rss sh f i v c p (max) (max) (max) 12 = where c rss = reverse transfer capacitance of the top mosfet switching losses need to be taken into account for high switching frequency, since they are directly proportional to switching frequency. the conduction losses associated with top and bottom mosfets are determined by: d i r p out on ds ch 2 (max) ) ( (max) = ) 1 ( 2 (max) ) ( (max) d i r p out on ds cl ? = where p ch(max) = conduction losses of the high side mosfet p cl(max) = conduction losses of the low side mosfet r ds(on) = drain to source on resistance. the total power losses of the top mosfet are the sum of switching and conduction losses. for synchronous buck converters of efficiency over 90%, allow no more than 4% power losses for high or low side mosfets. for input voltages of 3.3v and 5v, conduction losses often domi- nate switching losses. therefore, lowering the r ds(on) of the mosfets always improves efficiency even though it gives rise to higher switching losses due to increased c rss . top and bottom mosfets experience unequal conduction losses if their on time is unequal. for applications running at large or small duty cycle, it makes sense to use different top and bottom mosfets. alternatively, parallel multiple mosfets to conduct large duty factor. r ds(on) varies greatly with the gate driver volt- age. the mosfet vendors often specify r ds(on) on multiple gate to source voltages (v gs ), as well as provide typical curve of r ds(on) versus v gs . for 5v input, use the r ds(on) specified at 4.5v v gs . at the time of this publication, ven- dors, such as fairchild, siliconix and interna- tional rectifier, have started to specify r ds(on) at v gs less than 3v. this has provided necessary data for designs in which these mosfets are driven with 3.3v and made it possible to use sp6120b in 3.3v only applications. thermal calculation must be conducted to en- sure the mosfet can handle the maximum load current. the junction temperature of the mosfet, determined as follows, must stay below the maximum rating. ja mo sfet a j r p t t (max) (max) ( max) + = where t a(max) = maximum ambient temperature p mosfet(max) = maximum power dissipa- tion of the mosfet r ja = junction to ambient thermal resistance. r ja of the device depends greatly on the board layout, as well as device package. significant thermal improvement can be achieved in the maximum power dissipation through the proper design of copper mounting pads on the circuit board. for example, in a so-8 package, placing
17 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation two 0.04 square inches copper pad directly under the package, without occupying addi- tional board sp ace, can increase the maximum power from approximately 1 to 1.2w. for dpak package, enla rging the tap mounting pad to 1 square inches reduces the r ja from 96 c/w to 40 c/w. schottky diode selection when paralleled with the bottom mosfet, an optional schottky diode can improve efficiency and reduce noises. without this schottky diode, the body diode of the bottom mosfet con- ducts the current during the non-overlap time when both mosfets are turned off. unfortu- nately, the body diode has high forward voltage and reverse recovery problem. the reverse re- covery of the body diode causes additional switching noises when the diode turns off. the schottky diode alleviates these noises and addi- tionally improves efficiency thanks to its low forward voltage. the reverse voltage across the diode is equal to input voltage, and the diode must be able to handle the peak current equal to the maximum load current. the power dissipation of the schottky diode is determined by p diode = 2v f i out t nol f s where t nol = non-overlap time between gh and gl. v f = forward voltage of the schottky diode. sp6120b c2 c1 r1 comp figure 18. the rc network connected to the comp pin provides a pole and a zero to control loop. loop compensation design the goal of loop compensation is to manipulate loop frequency response such that its gain crosses over 0db at a slope of ?0db/dec. the sp6120b has a transconductance error amplifier and re- quires the compensation network to be con- nected between the comp pin and ground, as shown in figure 18. the first step of compensation design is to pick the loop crossover frequency. high crossover frequency is desirable for fast transient response, but often jeopardize the system stability. since the sp6120b is equipped with 3% window comparator that takes over the control loop on transient, the crossover frequency can be se- lected primarily to the satisfaction of system stability. crossover frequency should be higher than the esr zero but less than 1/5 of the switching frequency. the esr zero is contrib- uted by the esr associated with the output capacitors and can be determined by: f z(esr) = 1 2 c out r esr crossover frequency of 20khz is a sound first try if low esr tantalum capacitors or poscaps are used at the output. the next step is to calcu- late the complex conjugate poles contributed by the lc output filter, f p(lc) = 1 2 lc out the open loop gain of the whole system can be divided into the gain of the error amplifier, pwm modulator, buck converter, and feedback resistor divider. in order to crossover at the selected frequency fco, the gain of the error amplifier has to compensate for the attenuation caused by the rest of the loop at this frequency. in the rc network shown in figure 18, the product of r1 and the error amplifier transconductance determines this gain. there- fore, r1 can be determined from the following equation that takes into account the typical error amplifier transconductance, reference voltage and pwm ramp built into the sp6120b. r 1 = 1300v out f co f z (esr) v in f p(lc) 2
18 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation current sense the sp6120b allows sensing current using the inductor, pcb trace or current-sense resistor. inductor-sense utilizes the voltage drop across the esr of the inductor, while pcb trace and current-sense resistor introduce additional re- sistance in series with the inductor. the resis- tance of the sense element determines the overcurrent protection threshold as follows, i lim = 43mv r sen r sen = current-sense resistance which can be implemented as esr of the inductor, trace or discrete resistor. the maximum power dissipation on the current- sense element is: sen out sen r i p 2 (max) = for the inductor-sense scheme shown in the application circuit, r s and c s are used to repli- cate the signal across the esr of the inductor. r s and c s can be looked at as a low pass filter whose output represents the dc differential voltage between the switch node and the output. at steady state, this voltage happens to be the output current times the esr of the inductor. in addition, if the following relationship is satisfied, l = r s c s esr the output of the rscs filter represents the exact voltage across the esr, including the ripple. since the sp6120b? hiccup overcurrent pro- tection scheme is intended to safeguard sus- tained overload conditions, the dc portion of the current signal is more of interest. therefore, designing the r s c s time constant higher than l/ esr provides reliable current sense against any premature triggering due to noise or any tran- sient conditions. pick rs between 10k and 100k, and cs can be determined by: c s = 2 l1 esr r s here the time constant of r s c s is twice the value of l/esr. in some applications, it may be desirable to extend the current sense capability of a given r sen element (usually the inductor esr) be- in figure 18, r1 and c1 provides a zero f z1 which needs to be placed at or below f p(lc) . if f z1 is made equal to f p(lc) for convenience, the value of c1 can be calculated as c 1 = 1 2 f p(lc) r 1 the optional c2 generates a pole f p1 with r1 to cut down high frequency noise for reliable op- eration. this pole should be placed one decade higher than the crossover frequency to avoid erosion of phase margin. therefore, the value of the c2 can be derived from c 2 = 1 20 f co r 1 figure 19 illustrates the overall loop frequency response and frequency of each pole and zero. to fine-tune the compensation, it is necessary to physically measure the frequency response us- ing a network analyzer. figure 19. frequency response of a stable system and its error amplifier.
19 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation yond the limit set by the 43mv threshold. a straight forward way to do this would be to add a resistor r s2 in parallel with c s , creating a voltage divider with r s . this changes the rela- tionship with r s and c s to be c s = 2 l1 esr r s //r s2 using a voltage divider across the inductor, the new relationship becomes: i lim = 43mv r s + r s2 esr r s2 to calculate r s2 , the formula becomes r s2 = r s / ( i lim esr ?1 ) 43mv r s c s l v ou t s wn r s2 esr isp isn figures 21(a), a voltage divider connected to the v fb pin programs the output voltageand 21(b), a simple circuit using one external voltage reference programs the output voltages to less than 1.25v. r1 r2 r2 r1 r3 ab v ref v fb v fb v out < 1.25v v out > 1.25v sp6120b sp6120b figure 20: current sensing output voltage programming as shown in figure 21(a), the voltage divider connecting to the v fb pin programs the output voltage according to v out = 1.25( 1 + r 1 ) r 2 where 1.25v is the internal reference voltage. select r2 in the range of 10k to 100k, and r1 can be calculated using r 1 = r 2 (v out ? 1.25) 1.25 for output voltage less than 1.25v, a simple circuit shown in figure 21(b) can be used in which v ref is an external voltage reference greater than 1.25v. for simplicity, use the same resistor value for r1 and r2, then r3 is deter- mined as follows, r 3 = (v ref ? 1.25)r 1 2.5 ?v out
20 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation layout guideline pcb layout plays a critical role in proper func- tion of the converters and emi control. in switch mode power supplies, loops carrying high di/dt give rise to emi and ground bounces. the goal of layout optimization is to identify these loops and minimize them. it is also crucial on how to connect the controller ground such that its op- eration is not affected by noise. the following guideline should be followed to ensure proper operation. 1. a ground plane is recommended for mini- mizing noises, copper losses and maximizing heat dissipation. 2. connect the ground of feedback divider, com- pensation components, oscillator resistor and soft-start capacitor to the gnd pin of the ic. then connect this pin as close as possible to the ground of the output capacitor. 3. the v cc bypass capacitor should be right next to the vcc and gnd pin. 4. the traces connecting to feedback resistor and current sense components should be short and far away from the switch node, and switch- ing components. 5. connect the pgnd pin close to the source of the bottom mosfet, and the swn pin to the source of the top mosfet. minimize the trace between gh/gl and the gates of the mosfets. all of these requirements reduce the impedance driving the mosfets. this is especially important for the bottom mosfet that tends to turn on through its miller capaci- tor when the switch node swings high. 6. minimize the loop composed of input capaci- tors, top/bottom mosfets and schottky di- ode, this loop carries high di/dt current. also increase the trace width to reduce copper losses. 7. maximize the trace width of the loop con- necting the inductor, output capacitors, schottky diode and bottom mosfet.
21 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation seating plane a2 a a1 b see detail ? b b seaing plane l1 l 1 detail a 2 3 c b section b-b e1 e d index area d 2 x 2 e1 12 e symbol min nom max a-- 1.2 a1 0.05 - 0.15 a2 0.8 1 1.05 b 0.19 - 0.3 c 0.09 - 0.2 d 4.9 5 5.1 e e1 4.3 4.4 4.5 e ?1 0o 4o 8o ?2 ?3 l 0.45 0.6 0.75 l1 note: dimensions in (mm) 16 pin tssop jedec mo-153 (ab) variation 6.40 bsc 0.65 bsc 12o ref 12o ref 1.00 ref package: 16 pin tssop
22 date: 11/29/04 sp6120b low voltage, anyfet tm , synchronous, buck controller ?copyright 2004 sipex corporation corporation analog excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others. sipex corporation headquarters and sales office 22 linnell circle billerica, ma 01821 tel: (978) 667-8700 fax: (978) 670-9001 e-mail: sales@sipex.com ordering information model operating temperature range package type sp6120bcy ............................................. 0?c to +70?c ........................................ 16-pin tssop sp6120bcy/tr ....................................... 0?c to +70?c ....................................... 16-pin tssop sp6120bey ............................................ -40?c to +85?c ...................................... 16-pin tssop sp6120bey/tr ...................................... -40?c to +85?c ..................................... 16-pin tssop available in lead free packaging. to order add "-l" suffix to part number. example: sp6120bey/tr = standard; SP6120BEY-L/tr = lead free /tr = tape and reel pack quantity is 1500 for tssop. click here to order samples

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