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copyright ? cirrus logic, inc. 2009 (all rights reserved) http://www.cirrus.com 3.3 v stereo audio dac with 2 v rms line output features ? multi-bit delta-sigma modulator ? 106 db a-wt dynamic range ? -93 db thd+n ? single-ended ground centered analog architecture ? no dc-blocking capacitors required ? integrated step-up/inverting charge pump ? filtered line-level outputs ? selectable 1 or 2 v rms full-scale output ? low clock-jitter sensitivity ? low-latency digital filtering ? supports sample rates up to 192 khz ? 24-bit resolution ? +3.3 v charge pump and core logic, +3.3 v analog, and +0.9 to 3.3 v interface power supplies ? low power consumption ? 24-pin qfn, lead-free assembly description the cs4353 is a complete stereo digital-to-analog sys- tem including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-em- phasis, analog filtering, and on-chip 2 v rms line-level driver from a 3.3 v supply. the advantages of this architecture include ideal differ- ential linearity, no distorti on mechanisms due to resistor matching errors, no linearity drift over time and temper- ature, high tolerance to clo ck jitter, and a minimal set of external components. the cs4353 is available in a 24-pin qfn package in commercial (-40c to +85c) grade. the cdb4353 customer demonstration board is also available for de- vice evaluation and implementation suggestions. please see ?ordering information? on page 25 for com- plete details. these features are ideal fo r cost-sensitive, 2-channel audio systems including video game consoles, dvd players and recorders, a/v receivers, set-top boxes, digital tvs, mini-compone nt systems, and mixing consoles. pcm serial audio port level shifter serial audio input multibit ? modulator interpolation filters digital core logic and charge pump supply (vcp) +3.3 v left channel right channel hardware control power-on reset hardware control reset auto speed mode detect analog supply (va) +3.3 v inverting step-up +va_h -va_h interface supply (vl) +0.9 v to +3.3 v ground-centered, 2 vrms line level outputs dac pseudo diff. input jun '09 ds803f1 cs4353
2 ds803f1 cs4353 table of contents 1. pin descriptions .......................................................................................................... ................... 4 2. characteristics and specificat ions .......... ................. ................ ................ ................ ........... 6 recommended operating conditions .................................................................................... 6 absolute maximum ratings ...................................................................................................... .. 6 dac analog characteristics .................................................................................................... 7 combined interpolation & on-chip analog filter response .......... ................ .............. 8 switching specifications - serial audio inte rface ............... ................ ................ ........... 9 digital interface characteristics ....................................................................................... 10 internal power-on reset threshold voltages ................ ................. ................ ............ 10 dc electrical characteristics .............................................................................................. 11 3. typical connection diagram ................................................................................................. .. 12 4. applications ............................................................................................................... .................... 13 4.1.1 ground-centered outputs ................................................................................................. ..... 13 4.1.2 full-scale output amplitu de control ..................................................................................... .13 4.1.3 pseudo-differential outputs ............................................................................................. ...... 13 4.9.1 power-up sequences ...................................................................................................... ...... 19 4.9.1.1 external reset power-up sequence .......... ................ ................. ................ ............ 19 4.9.1.2 internal power-on rese t power-up sequence .......................................................... 19 4.9.2 power-down sequences .................................................................................................... ... 19 4.9.2.1 external reset power- down sequence ..... ................ ................. ................ ............ 19 4.9.2.2 internal power-on rese t power-down sequence ...................................................... 19 4.10.1 capacitor placement .... ................................................................................................ ....... 20 5. digital filter response plots ................ ................ ................ ................ ................ .............. .. 21 6. parameter definitions ...................................................................................................... .......... 23 7. package dimensions ......................................................................................................... ........... 24 8. ordering information ....................................................................................................... ......... 25 9. revision history ........................................................................................................... ................. 25 ds803f1 3 cs4353 list of figures figure 1.serial input timing .................................................................................................. ...................... 9 figure 2.power-on reset threshol d sequence .................................................................................... .... 10 figure 3.typical connection diagram .................... ....................................................................... ............ 12 figure 4.stereo pseudo-dif ferential output .................................................................................... ........... 13 figure 5.i2s, up to 24-bit data ...................... ......................................................................... .................... 15 figure 6.left-justified up to 24-bit data ..................................................................................... ................ 15 figure 7.de-emphasis curve, fs = 44.1 khz ..................................................................................... ....... 16 figure 8.internal power-on reset circuit ...................................................................................... ............ 16 figure 9.initialization and power-down sequence diagram ..................................................................... 18 figure 10.single- speed stopband rejection ..................................................................................... ........ 21 figure 11.single-speed transition band ........................................................................................ ........... 21 figure 12.single- speed transition band (detail) ............................................................................... ........ 21 figure 13.single-speed passband ripple ........................................................................................ ......... 21 figure 14.double-speed stopband rejection ..................................................................................... ...... 21 figure 15.double-spe ed transition band ........................................................................................ ......... 21 figure 16.double-spe ed transition band (detail) ............................................................................... ...... 22 figure 17.double-speed passband ripple ........................................................................................ ....... 22 figure 18.quad-speed stopband rejection ....................................................................................... ....... 22 figure 19.quad-speed transition band .......................................................................................... .......... 22 figure 20.quad-speed transition band (detail) ................................................................................. ....... 22 figure 21.quad-speed passband ripple .......................................................................................... ........ 22 list of tables table 1. digital i/o pin characteristics ...................................................................................... ............... 11 table 2. cs4353 operational mode auto-detect ...... ............................................................................ .... 14 table 3. single-speed mode standa rd frequencies ............................................................................... .. 14 table 4. double-speed mode standa rd frequencies ............................................................................... 14 table 5. quad-speed mode standard frequencies ................................................................................. .14 table 6. digital interface form at ............................................................................................. .................. 15 4 ds803f1 cs4353 1. pin descriptions pin name pin # pin description sclk 1 serial clock ( input ) - serial clock for the serial audio interface. mclk 2 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. vl 3 serial audio interface power ( input ) - positive power for the serial audio interface dgnd 4 digital ground ( input ) - ground reference for the digital section. flyp+ flyp- 7 5 step-up charge pump cap positive/negative nodes (output) - positive and negative nodes for the step-up charge pump?s flying capacitor. vcp 6 charge pump and digital core logic power ( input ) - positive power supply for the step-up and invert- ing charge pumps as well as the digital core logic sections. vfilt+ 8 step-up charge pump filter connection (output) - power supply from the step-up charge pump that provides the positive rail for the output amplifiers flyn+ flyn- 9 11 inverting charge pump cap positive/negative nodes (output) - positive and negative nodes for the inverting charge pump?s flying capacitor. cpgnd 10 charge pump ground ( input ) - ground reference for the charge pump section. vfilt- 12 inverting charge pump filter connection (output) - power supply from the inverting charge pump that provides the negative rail fo r the output amplifiers. aoutb aouta 13 15 analog outputs ( output ) - the full-scale analog line output level is specified in the analog characteris- tics table. aout_ref 14 pseudo diff. analog output reference ( input ) - ground reference for the analog output amplifiers. this pin must be at the same nominal dc voltage as the agnd pin. agnd 16 analog ground ( input ) - ground reference for the low voltage analog section. 8 7 6 5 4 3 2 1 9 10 11 12 19 20 21 22 23 24 13 14 15 16 17 18 top-down (through package) view 24-pin qfn package sdin lrck i2s /lj dem 1_2vrms reset flyp+ vfilt+ flyn+ cpgnd flyn- sclk mclk vl dgnd flyp- vbias va agnd aout_ref aoutb thermal pad vcp vfilt- aouta ds803f1 5 cs4353 va 17 low voltage analog power ( input ) - positive power supply for the analog section. vbias 18 positive voltage reference ( output ) - positive reference voltage for the internal dac. reset 19 reset ( input ) - optional connection for an external rese t control. the device enters a powered-down state when this pin is set low (gnd) or when the vcp supply falls below the v off threshold (see see ? internal power-on reset threshold voltages ? on page 10. ). this pin should be set high (vl) during nor- mal operation. 1_2vrms 20 1 or 2 v rms select ( input ) - selects the analog output full-scale voltage. setting this pin low (gnd) selects 1 v rms , while setting it high (vl) selects 2 v rms . dem 21 de-emphasis ( input ) - selects the standard 50 s/15 s digital de-emphasis filter response for 44.1 khz sample rates when enabled. i2s /lj 22 digital interface format ( input ) - selects the serial audio interface format. setting this pin low (gnd) selects i2s, while setting it hi gh (vl) selects left-justified. lrck 23 left / right clock ( input ) - determines which channel, left or right , is currently active on the serial audio data line. sdin 24 serial audio data input ( input ) - input for two?s complement serial audio data. thermal pad - thermal relief pad - this pad may be soldered to the board, however it must be electrically isolated from all board connections. 6 ds803f1 cs4353 2. characteristics a nd specifications recommended operating conditions agnd = dngd = cpgnd = 0 v; all voltages with respect to ground. notes: 1. vcp and va must be supplied with the same nominal vo ltage. additional current dr aw will occur if the sup- ply voltages applied to vcp and va differ by more than 0.5 v. absolute maximum ratings agnd = dngd = cpgnd = 0 v; all voltages with respect to ground. warning: operation at or beyond these limit s may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameters symbol min typ max units dc power supply charge pump and digital core power (note 1) low voltage analog power (note 1) interface power vcp va vl 3.13 3.13 0.85 3.3 3.3 0.9 to 3.3 3.47 3.47 3.47 v v v ambient operating temperature (power applied) t a -40 - +85 c parameters symbol min max units dc power supply charge pump and digital core logic power low voltage analog power supply voltage difference interface power vcp va |vcp - va| vl -0.3 -0.3 - -0.3 3.63 3.63 0.5 3.63 v v v v input current, any pin except supplies i in -10ma digital input voltage digital interface v in-l -0.3 v l + 0.4 v analog input voltage aout_ref v in-a -0.3 0.5 v ambient operating temperature (power applied) t a -55 +125 c storage temperature t stg -65 +150 c ds803f1 7 cs4353 dac analog characteristics test conditions (unless otherwise specified): t a = 25 c; vcp = va = 3.3 v; aout_ref = agnd = dgnd = cpgnd = 0 v; vbias, vfilt+/-, and flyp/n+/- capacitors as shown in figure 3 on page 12 ; input test signal is a 997 hz sine wave at 0 dbfs; measurement bandwidth 10 hz to 20 khz. notes: 2. measured at the output of the ex ternal lpf on aoutx as shown in figure 3 on page 12 . 3. one-half lsb of triangular pdf dither is added to data. 4. measured with the specified minimum ac-load resistance present on the aoutx pins. 5. measured between the aoutx and aout_ref pins. 6. external impedance between the aoutx pin and the lo ad will lower the voltage delivered to the load. 7. v pp is the controlling specification. v rms specification valid for sine wave signals only. note that for sine wave signals: 8. measured with aout_ref connecte d directly to ground. external impedance between aout_ref and ground will lower the aout_ref rejection. 1_2vrms = 0 1_2vrms = 1 parameter symbol min typ max min typ max unit dynamic performance, fs = 48, 96, and 192 khz (notes 2 , 3, 4 ) dynamic range 24-bit a-weighted unweighted 16-bit a-weighted unweighted 94 91 - - 100 97 92 89 - - - - 100 97 - - 106 103 98 95 - - - - db db db db total harmonic distortion + noise 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - - -93 -77 -37 -93 -75 -29 -87 -71 -31 - - - - - - - - - - -93 -83 -43 -93 -75 -35 -87 -77 -37 - - - db db db db db db idle channel noise / signal-to-noise ratio (a-wt) - 100 - - 106 - db interchannel isolation (1 khz) - 115 - - 115 - db analog output (note 5 ) full scale aoutx output voltage (notes 4 , 6 , 7 ) 1.021.081.132.042.152.26v rms 2.89 3.05 3.20 5.78 6.09 6.40 v pp max current draw from an aoutx pin i outmax -575- -575- a interchannel gain mismatch - 0.1 - - 0.1 - db output offset - 5 8 - 5 8 mv gain drift - 100 - - 100 - ppm/c output impedance z out -100- -100- ac-load resistance r l 5- -5- -k load capacitance c l - - 1000 - - 1000 pf aout_ref rejection (notes 8 , 9 )aor-40- -40-db analog reference input aout_ref input voltage (note 10) --0.2--0.2vpp v rms v pp 22 ---------- = 8 ds803f1 cs4353 9. sdin = 0. aout_ref input test signal is a 60 hz, 50 mvpp sine wave. measured by applying the test signal into the aout_ref pin and measuring the re sulting output amplitude on the aoutx pin. spec- ification calculated by: 10. applying a dc voltage on the aout_ref pin w ill cause a dc offset on the dac output. see section 4.1.3 for more information. combined interpolat ion & on-chip analog filter response the filter characteristics have been normalized to the sa mple rate (fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by fs. notes: 11. response is clock-dependent and will scale with fs. 12. for single- and double-speed mode, the meas urement bandwidth is from stopband to 3 fs. for quad-speed mode, the measurement bandwidth is from stopband to 1.34 fs. 13. de-emphasis is available only in single-speed mode. 14. amplitude vs. frequency plots of this data are available in ?digital filter response plots? on page 21 . parameter min typ max unit single-speed mode - 48 khz passband (note 11) to -0.01 db corner to -3 db corner 0 0 - - .454 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband 0.547 - - fs stopband attenuation (note 12) 102 - - db total group delay (fs = sample rate) - 9.4/fs - s intra-channel phase deviation - - 0.56/fs s inter-channel phase deviation - - 0 s de-emphasis error (note 13) (relative to 1 khz) fs = 44.1 khz - - 0.14 db double-speed mode - 96 khz passband (note 11) to -0.01 db corner to -3 db corner 0 0 - - .430 .499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .583 - - fs stopband attenuation (note 12) 80 - - db total group delay (fs = sample rate) - 4.6/fs - s intra-channel phase deviation - - 0.03/fs s inter-channel phase deviation - - 0 s quad-speed mode - 192 khz passband (note 11) to -0.01 db corner to -3 db corner 0 0 - - .105 .490 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .635 - - fs stopband attenuation (note 12) 90 - - db total group delay (fs = sample rate) - 4.7/fs - s high-pass filter characteristics passband (note 11) to -0.05 db corner to -3 db corner 9.00x10 -5 9.74x10 -6 - - - - fs fs passband ripple - - 0.01 db phase deviation @ 20 hz - - 1.34 deg filter settling time (input signal goes to 95% of its final value) - 5x10 4 /fs - s aor db 20 log 10 aout _ ref aout _ ref aoutx ? --------------------------------------------------------- ?? ?? ? = ds803f1 9 cs4353 switching specifications - seri al audio interface parameters symbol min max units mclk frequency 2.048 51.2 mhz mclk duty cycle 45 55 % input sample rate (auto selection) single-speed mode double-speed mode quad-speed mode fs fs fs 8 84 170 54 108 216 khz khz khz lrck duty cycle 40 60 % sclk pulse width low t sclkl 20 - ns sclk pulse width high t sclkh 20 - ns sclk period single-speed mode - s double-speed mode - s quad-speed mode - s sclk rising to lrck edge delay t slrd 20 - ns sclk rising to lrck edge setup time t slrs 20 - ns sdin valid to sclk rising setup time t sdlrs 20 - ns sclk rising to sdin hold time t sdh 20 - ns sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck figure 1. serial input timing 1 128 () fs --------------------- - 1 64 () fs ------------------ 1 64 () fs ------------------ 10 ds803f1 cs4353 digital interface characteristics test conditions (unless otherwise specified): agnd = dgnd = cpgnd = 0 v; all voltages with respect to ground. internal power-on re set threshold voltages test conditions (unless otherwise specified): agnd = dgnd = cpgnd = 0 v; all voltages with respect to ground. figure 2. power-on reset threshold sequence parameters symbol min typ max units high-level input voltage 1.2 v < vl 3.3 v 0.9 v vl 1.2 v v ih v ih 0.7xvl 0.9xvl - - - - v v low-level input voltage 1.2 v < vl 3.3 v 0.9 v vl 1.2 v v il v il - - - - 0.3xvl 0.1xvl v v input leakage current i in --10 a input capacitance - 8 - pf parameters symbol min typ max units internal reset asserted at power-on v on1 -1.00- v internal reset released at power-on v on2 -2.36- v internal reset asserted at power-off v off -2.22- v vcp v on2 v on1 v off dgnd hi lo no power reset undefined reset active dac ready reset active reset (internal) ds803f1 11 cs4353 dc electrical characteristics test conditions (unless otherwise specified): vcp = va = vl = 3.3 v; agnd = dgnd = cpgnd = 0 v; sdin = 0; all voltages with respect to ground. notes: 15. current consumption increases with increasing samp le rate and increasing mclk frequency. typical values are based on fs = 48 khz and mclk = 12.288 mhz. maximum values are based on highest sample rate and highest mclk frequency; see switching specifications - serial audio interface . vari- ance between speed modes is small. 16. power-down is defined as reset pin = low with all clock and data lines held static low. all digital inputs have a weak pull-down (approximately 50 k ) which is only present during reset. opposing this pull- down will slightly increase the power-down current. 17. valid with the recommended capacitor value on vbias as shown in the typical connection diagram in section 3 . 18. typical voltage shown for ?initialization state?, see section 4.8 . typical voltage may be up to 1.5 v lower during normal operation. 2.1 digital i/o pin characteristics input and output levels and associat ed power supply voltage are shown in table 1 . logic levels should not exceed the corresponding power supply voltage. table 1. digital i/o pin characteristics parameters symbol min typ max units power supplies power supply current (note 15) normal operation power-down, all supplies (note 16) i vcp i va i vl i pd - - - - 36 2.4 0.1 65 43 3 0.2 - ma ma ma a power dissipation (all supplies) normal operation, 1_2vrms = 0 (note 15) power-down (note 16) - - 127 1 152 - mw mw power supply rejection ratio (note 17) (1 khz) (60 hz) psrr - - 60 60 - - db db dc output voltages pin voltage flyp+ to flyp- vfilt+ to gnd (note 18) flyn+ to flyn- gnd to vfilt- (note 18) va to vbias - - - - - 3.3 6.6 6.6 6.6 2.1 - - - - - v v v v v pin name power supply i/o driver receiver reset vl input - 0.9 v - 3.3 v, with hysteresis mclk input - 0.9 v - 3.3 v lrck input - 0.9 v - 3.3 v sclk input - 0.9 v - 3.3 v sdin input - 0.9 v - 3.3 v dem input - 0.9 v - 3.3 v i2s /lj input - 0.9 v - 3.3 v 1_2vrms input - 0.9 v - 3.3 v 12 ds803f1 cs4353 3. typical connection diagram vl +0.9 v to +3.3 v reset lrck mclk sclk aout_ref sdin vfilt- aouta v a 562 2.2 nf r ext r ext line level out left & right i2s/lj dem 1_2vrms vfilt+ digital audio processor hardware control values shown are for fc = 130 khz. capacitors must be c0g or equivalent. 562 2.2 nf aoutb vbias flyn- flyn+ 0.1 f 0.1 f 2.2 f flyp- flyp+ 2.2 f 0.1 f 0.1 f +3.3 v 0.1 f v c p note 1: c p g n d d g n d a g nd 22 f 2.2 f 2.2 f 2.2 f note 1 3 1 2 23 24 22 19 21 20 10 4 16 18 17 6 12 11 9 13 14 15 5 7 8 + + + + + note 2 note 2: connect reset to vl if internal power-on reset is used. + cs4353 figure 3. typical connection diagram ds803f1 13 cs4353 4. applications 4.1 line outputs 4.1.1 ground-centered outputs an on-chip charge pump creates both positive and n egative high-voltage supplies, which allows the full- scale output swing to be centered around ground. this eliminates the need for large dc-blocking capac- itors which create audible pops at power-on, allows the cs4353 to deliver a larger full-scale output at low- er supply voltages, and provides improved bandwidth frequency response. 4.1.2 full-scale output amplitude control the full-scale output voltage amplitude is selected via the 1_2vrms pin. when the pin is connected to vl, the full-scale output voltage at the aoutx pins is approximately 2 v rms . when the pin is connected to gnd, the full-scale output voltage at the aoutx pins is approximately 1 v rms . additional impedance between the aoutx pin and the load will lower th e voltage delivered to the load. see the dac analog characteristics table for the complete specificati ons of the full-scale output voltage. 4.1.3 pseudo-differential outputs the cs4353 implements a pseudo-differential output stage. the aout_ref input is intended to be used as a pseudo-differential reference signal. this featur e provides common mode noise rejection with single- ended signals. figure 4 shows a basic diagram outlining the inte rnal implementation of the pseudo-differ- ential output stage, including a recommended stereo pseudo-differential output topology. if pseudo-differ- ential output functionality is not required, simply connect the aout_ref pin to ground next to the cs4353. if a split-ground design is used, the ao ut_ref pin should be connected to agnd. see the ab- solute maximum ratings table for the maximum allowable voltag e on the aout_ref pin. applying a dc voltage on the aout_ref pin will ca use a dc offset on the dac output. internal left dac signal aouta aout_ref // // left output gnd (pseudo-differential traces) aoutb // right output (pseudo-differential traces) internal right dac signal psuedo-differential output improves common mode rejection, reducing external system noise figure 4. stereo pseudo-differential output 14 ds803f1 cs4353 4.2 sample rate range/operational mode detect the cs4353 operates in one of thr ee operational modes. th e device will auto-detect the correct mode when the input sample rate (fs), defined by the lrck frequency, falls with in one of the ranges illustrated in table 2 . sample rates outside the specified range for each mode are not supported. in addition to a valid lrck frequency, a valid serial clock (sclk) and mast er clock (mclk) must also be applied to the device for speed mode auto-detection; see figure 9 . table 2. cs4353 operational mode auto-detect 4.3 system clocking the device requires external generation of the master (mclk), left/right (lrck) and serial (sclk) clocks. the left/right clock, defined also as the input sample rate (fs), must be synch ronously derived from the mclk signal according to specified ratios. the specif ied ratios of mclk to lrck, along with several stan- dard audio sample rates and the required mclk fr equency, are illustrated in tables 3 - 5 . refer to section 4.4 for the required sclk timing associated with the selected digital interface format and to ?switching specifications - serial audio interface? on page 9 for the maximum allowed clock frequencies. table 3. single-speed mode standard frequencies table 4. double-speed mode standard frequencies table 5. quad-speed mode standard frequencies input sample rate (fs) mode 8 khz - 54 khz single-speed mode 84 khz - 108 khz double-speed mode 170 khz - 216 khz quad-speed mode sample rate (khz) mclk (mhz) 256x 384x 512x 768x 1024x 32 8.1920 12.2880 16. 3840 24.5760 32.7680 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 sample rate (khz) mclk (mhz) 128x 192x 256x 384x 512x 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24. 5760 36.8640 49.1520 sample rate (khz) mclk (mhz) 128x 192x 256x 176.4 22.5792 33.8688 45.1584 192 24.5760 36.8640 49.1520 ds803f1 15 cs4353 4.4 digital interface format the device will accept audio samples in either i2s or left-justified digita l interface formats , as illustrated in table 6 . the desired format is selected via the i2s /lj pin. for an illustration of th e required relationship between the lrck, sclk and sdin, see figures 5 - 6 . for all formats, sdin is valid on the rising edge of sclk. also, sclk must have at least 32 cycles per lr ck period in the left-justified format. for more information about serial audio formats, refer to cirrus logic application note an282: the 2-chan- nel serial audio interface: a tutorial , available at http://www.cirrus.com . table 6. digital interface format figure 5. i2s, up to 24-bit data figure 6. left-justi fied up to 24-bit data 4.5 internal high-pass filter the device includes an internal digital high-pass filter. this filt er prevents a constant digital offset from cre- ating a dc voltage on the analog output pins. the filter?s corner frequency is well below the audio band; see the combined interpolation & on-chip analog filter response table for filter specifications. i2s /lj description figure 0 i2s, up to 24-bit data 5 1 left-justified, up to 24-bit data 6 lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb lsb lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 lsb msb lsb 16 ds803f1 cs4353 4.6 de-emphasis control the device includes on-chip digital de-emphasis. figure 7 shows the de-emphasis curve for fs equal to 44.1 khz. the frequency response of the de-emphasi s curve scales with changes in the sample rate, fs. the de-emphasis error will increase fo r sample rates other than 44.1 khz. when the dem pin is connected to vl, the 44.1 khz de-emphasis filter is activated. when the dem pin is connected to gnd, the de-emphas is filter is turned off. note: de-emphasis is only available in single-speed mode. 4.7 internal power-on reset the cs4353 features an internal power-on reset (por) circuit. the por circuit allows the reset pin to be connected to vl during power-up and power-down sequenc es if the external reset function is not needed. this circuit monitors the vcp supply and automatically asserts or releases an internal reset of the dac?s digital circuitry when the supply reaches defined thresholds (see ?internal power-on reset threshold volt- ages? on page 10 ). no external clocks are required for the por circuit to function. figure 8. internal power-on reset circuit when power is first applied, the por circuit monitors the vcp supply voltage to determine when it reaches a defined threshold, v on1 . at this time, the por circuit asserts the internal reset low, resetting all of the digital circuitry. once the vcp supply reaches the secondary threshold, v on2 , the por circuit releases the internal reset. note: for correct operation of the internal por circuit, the voltage on vl must rise before or simulta- neously with vcp. when power is removed and the vcp voltage reaches a defined threshold, v off , the por circuit asserts the internal reset low, resetting all of the digital circuitry. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 7. de-emphasis curve, fs = 44.1 khz reset (external) power-on reset circuit vcp dgnd reset (internal) ds803f1 17 cs4353 4.8 initialization when power is first applied, the dac enters a reset (l ow power) state at the beginning of the initialization sequence. in this state, the aoutx pins are we akly pulled to ground and vbias is connected to va. the device will remain in th e reset state until the reset pin is brought hi gh. once the reset pin is high, the internal digital circuitry is re set and the dac enters a power-down st ate until mclk is applied. alterna- tively, if no external rese t control is requ ired, the internal power-on rese t can be used by tying the reset pin to vl (see section 4.7 ). once mclk is valid, the device enters an initialization state in which the charge pump powers up and charg- es the capacitors for both the positive and negative high-voltage supplies. once lrck and sclk are valid, the number of mclk c ycles is counted relative to the lrck period to de- termine the mclk/lrck frequency rati o. next, the device enters the pow er-up state in which the interpo- lation and decimation filters and delta-sigma modula tors are turned on, the internal voltage reference, vbias, powers up to normal operation, the analog output pull-down resistors are removed, and power is applied to the output amplifiers. after this power-up state sequence is complete, no rmal operation begins and analog output is generated. if valid mclk, lrck, and sclk ar e applied to the dac before reset is set high, the total time from re- set being set high to the analog audio output from aoutx is less than 50 ms. see figure 9 for a diagram of the device?s states and transition conditions. 18 ds803f1 cs4353 user: apply power user: apply mclk mclk/lrck ratio detection user: apply lrck and sclk reset state power-down state initialization state power-up state outputs grounded normal operation state mute state valid mclk/lrck ratio or user: reset set high reset tied high (if using por) user: change mclk/lrck ratio outputs muted analog output generated user: reset set low user: change mclk/lrck ratio valid mclk/lrck ratio or remove mclk figure 9. initialization and power-down sequence diagram ds803f1 19 cs4353 4.9 recommended power-up and power-down sequences 4.9.1 power-up sequences 4.9.1.1 external reset power-up sequence follow the power-up sequence below if the external reset pin is used: 1. hold reset low while the power supplies are turned on. 2. set the i2s /lj, 1_2vrms, and dem configurat ion pins to the desired state. 3. provide the correct mclk, lrck, and sclk signals locked to the appropriate frequencies as discussed in section 4.3 . 4. after the power supplies, co nfiguration pins, and clock si gnals are stable, bring reset high. the device will initiate the po wer-up sequence seen in figure 9 . the sequence will co mplete and audio will be output from aoutx within 50 ms after reset is set high. 4.9.1.2 internal power-on reset power-up sequence follow the power-up sequence below if the internal power-on reset is used: 1. hold reset high (connected to vl) while the power supplies are turned on. the power-on reset circuitry will function as described in section 4.7 . 2. set the i2s /lj, 1_2vrms, and dem configurat ion pins to the desired state. 3. after the power supplies and configuration pins are stable, provide the correct mclk, lrck, and sclk signals to progress from the ?power-down state? in the power-up sequence seen in figure 9 . the sequence will complete and audi o will be output from the aoutx pins within 50 ms after valid clocks are applied. 4.9.2 power-down sequences 4.9.2.1 external reset power-down sequence follow the power-down sequence below if the external reset pin is used: 1. for minimal pops, set the input digital data to zero for at least 8192 consecutive samples. 2. bring reset low. 3. remove the power supply voltages. 4.9.2.2 internal power-on reset power-down sequence follow the power-down sequence below if the internal power-on reset is used: 1. for minimal pops, set the input digital data to zero for at least 8192 consecutive samples. 2. remove the mclk signal without applying any glitched pulses to the mclk pin. 3. remove the power supply voltages. note: a glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum mclk signal duty cycle specification and the nominal frequency of the input mclk signal. a transient may occur on the analog outputs if the mc lk signal duty cycle s pecification is violated when the mclk signal is removed during normal operation; see ?switching specifications - serial audio interface? on page 9 . 20 ds803f1 cs4353 4.10 grounding and power supply arrangements as with any high-resolution converter, the cs4353 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. figure 3 shows the recommended power ar- rangements, with vcp, va, and vl connected to cle an supplies. it is strongly recommended that a single ground plane be used, with the dgnd, cpgnd, and agnd pins all connected to this common plane. should it be necessary to split the ground planes, the dgnd and cpgnd pins should be connected to the digital ground plane and the agnd pin should be connected to the analog ground plane. in this configura- tion, it is critical that the digita l and analog ground planes be tied together with a low-impedance connection, ideally a strip of copper on the printed circui t board, at a single point near the cs4353. all signals, especially clocks, should be kept away from the vbias pin in order to avoid unwanted coupling into the dac. 4.10.1 capacitor placement decoupling capacitors should be placed as close to the device as possible, with the low-value ceramic capacitor being the closest. to further minimize imp edance, these capacitors should be located on the same pcb layer as the device. if desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin. see dc electrical characteristics for the voltage present across pin pairs. this is useful for choosing appropriate capacitor voltage ratings and ori- entation if electrolytic capacitors are used. the cdb4353 evaluation board demonstrates the optimum layout and power supply arrangements. ds803f1 21 cs4353 5. digital filter respon se plots 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 10. single-speed stopband rejectio n figure 11. single-speed transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 12. single-speed transition band (detail) figure 13. single-speed passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 14. double-speed stopband rejectio n figure 15. double-speed transition band 22 ds803f1 cs4353 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 16. double-speed transition band (d etail) figure 17. double-speed passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 18. quad-speed stopband rejection figure 19. quad-speed transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 20. quad-speed transition band (det ail) figure 21. quad-s peed passband ripple ds803f1 23 cs4353 6. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion comp onents. expressed in decibels. dynamic range the ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noi se measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the re sulting measurement to refer the measurement to full scale. this technique ensures that t he distortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering society, aes17- 1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right chan nels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in deci- bels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain drift the change in gain value with temperature. units in ppm/c. 24 ds803f1 cs4353 7. package dimensions notes: 1. dimensioning and tolerance per asme y 14.5m-1994. 2. dimensioning lead width applie s to the metallized terminal and is measured betw een 0.15 mm and 0.30 mm from the terminal tip. inches millimeters note dim min nom max min nom max a - - 0.03937 - - 1.00 1 a1 0.00000 - 0.00197 0.00 - 0.05 1 b 0.00787 0.00984 0.01181 0.20 0.25 0.30 1 , 2 e 0.01772 0.01969 0.02165 0.45 0.50 0.55 1 d 0.15748 bsc 4.00 bsc 1 d2 0.10433 0.10630 0.10827 2.65 2.70 2.75 1 e 0.15748 bsc 4.00 bsc 1 e2 0.10433 0.10630 0.10827 2.65 2.70 2.75 1 l 0.01181 0.01575 0.01969 0.30 0.40 0.50 1 controlling dimension is millimeters parameter symbol min typ max units junction to ambient thermal impedance 2 layer board 4 layer board ja ja - - 68 28 - - c/watt c/watt pin #1 corner l a a1 e b d2 e2 d 1.00 ref 1.00 ref pin #1 identifier laser marking e top view side view bottom view 24l qfn (4.00 mm body ) package drawing ds803f1 25 cs4353 8. ordering information 9. revision history release changes pp1 ? updated interchannel isolation specification in the dac analog characteristics specification table. ? updated minimum quad-speed mode sclk period in the switching specifications - serial audio interface table. ? updated power supply current and power dissipation specifications in the dc electrical characteristics table. ? updated the flyn+ to flyn- dc voltage in the dc electrical characteristics table. ? added ?sdin = 0? to the test conditions in the dc electrical characteristics table. ? updated section 4.9.1.1 on page 19 . ? updated output impedance specification in the dac analog characteristics specification table. pp2 ? removed automotive grade. f1 ? added note 2 and reference to note 4 in the dynamic performance section of the dac analog characteristics table. ? changed ?additional? to ?external? in note 6 and 8 on page 7 . ? updated full scale output specification in the dac analog characteristics table. ? updated von2 and voff specifications in the internal power-on reset threshold voltages table. ? added hpf data to combined interpolation & on-chip analog filter response table. ? added section 4.5 internal high-pass filter . product description package pb-free grade temp range container order # cs4353 3.3 v stereo audio dac with 2 v rms line output 24-pin qfn yes commercial -40 to +85 c rail cs4353-cnz tape & reel CS4353-CNZR cdb4353 cs4353 evaluation board - - - - cdb4353 26 ds803f1 cs4353 contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com. important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishi ng this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirru s products are not designed, au thorized or warranted for use in products surgically implan ted into the body, automotive safety or security devices, life support products or other crit- ical applications. in clusion of cirrus products in such ap plications is understood to be fully at the cus tomer?s risk and cir- rus disclaims and makes no warranty, expres s, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or custom- er?s customer uses or permits the use of cirrus products in critical applications, customer agrees , by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including at- torneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. |
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