View MCD212_1763735.PDF datasheet online --- IC-ON-LINE

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advance information MCD212 video decoder and system controller (with jtag) order this document by MCD212/d rev. 0 coming through loud and clear. MCD212 video decoder and system controller
how to reach us: usa / europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmfax0@email.sps.mot.com t ouchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 MCD212/d
MCD212 i motorola ! $"# #! !

1.1 introduction 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 features 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 block diagram 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 differences between the mcd211 and the MCD212 13 . . . . . . . . . . . . . . .

2.1 introduction 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 pin function description 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 system interface 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 dynamic ram interface 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 video interface 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 jtag test signals 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 miscellaneous signals 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 pin types 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 reset and halt generation 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 reset mechanism 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 vdsc initialization sequence 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 memory swapping 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 address decoding 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 data acknowledge generation 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 bus error generation 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 interrupt generation 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? motorola, inc., 1995
MCD212 ii motorola
4.1 dram configuration 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 dram access and arbitration 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 dram timing 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 dram deselect 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 dram implementation 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 image formats 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 ntsc/pal 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 resolution 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 horizontal resolution 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 vertical resolution 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 timing 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 software 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 ica control 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 dca control 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 ica/dca initialization 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 ica/dca instructions 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4.1 h80hbf clut color register 063 510 . . . . . . . . . . . . 5.4.4.2 hc0 image coding method register 511 . . . . . . . . . . 5.4.4.3 hc1 transparency control register 512 . . . . . . . . 5.4.4.4 hc2 plane order register 512 . . . . . . . . . . . . . . . . . . . . 5.4.4.5 hc3 clut bank register 513 . . . . . . . . . . . . . . . . . . . . . . . 5.4.4.6 hc4hc6 transparent color register 513 . . . . . . . 5.4.4.7 hc7hc9 mask color register 513 . . . . . . . . . . . . . . . . . 5.4.4.8 hca, hcb delta yuv absolute start value register 514 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4.9 hcd cursor position register 514 . . . . . . . . . . . . . . . . 5.4.4.10 hce cursor control register 515 . . . . . . . . . . . . . . . 5.4.4.11 hcf cursor pattern register 516 . . . . . . . . . . . . . . . . 5.4.4.12 hc0hd7 region control register 07 516 . . . . . . . . 5.4.4.13 hc8 backdrop color register 517 . . . . . . . . . . . . . . . . 5.4.4.14 hd9, hda mosaic pixel hold factor register 518 . 5.4.4.15 hdbhdc weight factor register 518 . . . . . . . . . . . . .
MCD212 iii motorola
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5.5 bitmap 519 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 effect of standard bit 519 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 effect on vertical timing 519 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 effect on horizontal timing 519 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 video synchronization 520 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 bitmap file 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 runlength file 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 runlength 7bit clut files 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 runlength 3bit clut files 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 mosaic file 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 pixel output 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 delta yuv decoder 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 clut decoder 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 direct rgb555 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 decoding combinations 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 backdrop 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 cursor 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 planes 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 pixel hold 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 regions 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 transparency 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 overlay and mixing 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCD212 iv motorola 9.1 register map 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 control registers csr1w and csr2w 92 . . . . . . . . . . . . . . . . . . 9.1.2 status registers csr1r and csr2r 93 . . . . . . . . . . . . . . . . . . . . . 9.1.3 display command registers dcr1 and dcr2 94 . . . . . . . . . . . . 9.1.4 display decoder registers ddr1 and ddr2 96 . . . . . . . . . . . . . 9.1.5 video start registers vsr1 and vsr2 97 . . . . . . . . . . . . . . . . . . . 9.1.6 dca pointers dcp1 and dcp2 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 pin function table 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 pin configuration 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1 absolute maximum ratings 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 dc electrical characteristics 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 ac characteristics 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a.1 delta yuv encoding a1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a.2 delta coding a1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCD212 v motorola
fig. page no. title no. 11 system block diagram 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 internal block diagram 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 reset and halt timing chart 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 clk2 clocking and resetting 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 memory swapping timing chart 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 bus error timing 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 dram access 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 dram cycles 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 dram timing 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 dram banks validation/devalidation 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 four video planes of the displayed image 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 example of normal and double resolution pixels 52 . . . . . . . . . . . . . . . . . . . . . . . . . . 53 line display of interlace versus noninterlace modes 53 . . . . . . . . . . . . . . . . . . . . . . . 54 hsync and blank timing 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 vsync and blank timing 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 csync timing in the 50 hz (fd = 0), noninterlace mode (sm = 0) 55 . . . . . . . . . . 57 csync timing in the 60 hz (fd = 1), noninterlace mode (sm = 0) 55 . . . . . . . . . . 58 csync timing in the 50 hz (fd = 0), interlace mode (sm = 1) 56 . . . . . . . . . . . . . . . 59 csync timing in the 60 hz (fd = 1), interlace mode (sm = 1) 56 . . . . . . . . . . . . . . . 510 cursor position 514 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 cursor pattern diagram 516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 vdsc in slave mode with an external pll for clock generation 520 . . . . . . . . . . . . . 513 vdsc in slave mode with an external clock 520 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 bitmap serialization in 8 bits/pixel 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 bitmap serialization in 4 bits/pixel 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 runlength format in 7 bits/pixel 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 runlength format in 3 bits/pixel 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 data structure of dyuv decoder input and output pixelpair 72 . . . . . . . . . . . . . . . . 72 clut organization 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 data structure of input clut pixel 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 data structure of rgb555 input and output pixel 74 . . . . . . . . . . . . . . . . . . . . . . . . . .
MCD212 vi motorola
fig. page no. title no. 81 pixel hold example for n = 3 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 example showing overlapping and nonoverlapping regions 82 . . . . . . . . . . . . . . . 83 implicit control of region flags (nr = 1) 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 explicit control of region flags (nr = 0) 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 plane order 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 overlay and mixing e one color component 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 clock timing 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 video timing 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 cpu read cycle timing 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 cpu write cycle timing 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 system timing 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 dram timing 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 reset and halt timing 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCD212 vii motorola

table page no. title no. 31 address map 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 dtack delay for rom 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 address map of the dram banks 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 memory address distribution 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 cas1 and cas2 assertion 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 implementing 256k x 4 dram 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 implementing 1m x 4 dram 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 implementing 256k x 16 dram 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 normal fullscreen display resolution 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 horizontal resolution 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 scan modes 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 vertical resolution in the noninterlace mode 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 horizontal synchronization timing 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 vertical synchronization timing (in lines) 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 vertical synchronization timing (in lines) 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 ica pointer addresses 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ica1/dca1 and ica2/dca2 modes 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 possible dca1/dca2 fetches per line 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 ica control instructions 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 dca control instructions 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 register map 510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 clut color register 063 e address h80 hbf 510 . . . . . . . . . . . . . . . . . . . . . . . . . 515 clut ram addresses 511 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 image coding method register address hc0 511 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 cm1x, cm2x: coding method for plane a, b 511 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 transparency control register address hc1 512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 transparency control register address hc1 512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 plane order register address hc2 512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 plane order 513 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 clut bank register address hc3 513 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 bank select 513 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 transparent color register address hc4 hc6 513 . . . . . . . . . . . . . . . . . . . . . . . . .
MCD212 viii motorola
table page no. title no. 525 mask color register address hc7 hc9 513 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 delta yuv absolute start value register address hca hcb 514 . . . . . . . . . . . . . 527 cursor position register address hcd 514 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 cursor control register address hce 515 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 cursor color 515 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 cursor pattern register address hcf 516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 region control register address hd0 hd7 516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 operation control codes 517 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 background color register address hd8 517 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 color of background plane 518 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 mosaic pixel hold factor register address hd9, hda 518 . . . . . . . . . . . . . . . . . . . . 536 weight factor register address hdb hdc 518 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 bitmap width for bitmap files 519 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 synchronization modes 520 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 file type of display 1 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 file type of display 2 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 mosaic factor of display 1 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mosaic factor of display 2 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 output modes of channel 1 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 output modes of channel 2 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 dequantizer 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 display modes for plane a 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 display modes for plane b 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 possible combinations of display modes 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 possible cursor and background colors 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 register summary 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 register bitmap 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 control register 1 write, 4ffff0 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 dtack delay 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 control register 2 write, 4fffe0 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 status register csr1r read, 4ffff1 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 status register csr2r read, 4fffe1 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCD212 ix motorola
table page no. title no. 98 display command register dcr1 write, 4ffff2 94 . . . . . . . . . . . . . . . . . . . . . . . . . 99 crystal frequency 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 scan mode 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911 channel 1 color mode 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912 ica1/dca1 enable 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 display command register dcr2 write, 4fffe2 95 . . . . . . . . . . . . . . . . . . . . . . . . . 914 channel 2 color mode 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 ica1/dca1 enable 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916 display decoder register 1 write, 4fff8 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917 channel 1 mosaic factor 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 channel 1 display file type 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919 display decoder register 2 write, 4fffe8 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920 channel 2 mosaic factor 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 channel 2 display file type 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922 video start register 1 write, 4ffff4 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 video start register 2 write, 4fffe4 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924 display control pointer 1 write, 4ffffa 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 display control pointer 2 write, 4fffea 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a1 16bit quantization table a2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters can and do vary in different applications. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer.
MCD212 x motorola
MCD212 11 motorola
the video decoder and system controller with jtag (vdsc/jtag) is a cmos device integrating a 680x0 family system controller and video graphics decoder, see figure 11 below. the MCD212 is a programmable, multiscan video device that can function as either a master or a slave. it is functionally equivalent to the mcd211 with the addition of jtag testing. the MCD212 is a dropin replacement for the mcd211 if the jtag functionality is not required. it can directly drive up to 5m bytes 1 of memory and provides chipselect signals for system rom and peripherals. the onchip dram controller can support up to 4m bytes dram and controls access to the unspecialized system or video dram. the cpu can access any memory location, even during active video display lines, thereby boosting system performance. the video image is made up of four separate video planes: the cursor, two graphics planes (a and b), and one background plane. the video decoder receives two independent video channels from the video dram. each channel has a realtime file decoder permitting the display of normal, runlength, and mosaic compressed files. the resulting files can contain dyuv, clut, or direct rgb data. after decoding the resulting planes, a and b can be combined with a cursor and background allowing for visual effects like dissolves, mosaics, partial updates, etc., under software control. the resulting dis- play is available in red, green, and blue components, each being eight bits in length. the display resolution is programmable up to 768 x 560. 68000 bus vdsc dac rgb video dram figure 11. system block diagram 1. in this document a word is defined as 16 bits and a longword as 32 bits. hexadecimal figures are indicated by an h in front.
MCD212 12 motorola
system interface: ? direct interface for 680x0 bus compatible devices ? 1m byte rom control ? 1k byte i/o control ? reset sequencer, including rom shadowing ? watchdog timer dram interface: ? 4m byte dram direct drive ? 256k x 4, 1m x 4, and 256k x 16 dram types can be used video interface: ? up to 768 x 560 screen resolution ? capability to display runlength coded files ? mosaic effect ? 256entry color look up table (clut) ? two delta yuv decoders ? cursor shape, color, and blink control ? overlaying of four video planes ? special effects via weight control, priority control, etc. ? dynamic programmable registers and clut reload in retrace period ? digital rgb output (8 bits per component) ? synchro generator for 50 and 60 hz scan ? synchronization with external video general: ? cmos technology ? 160pin quad flat pack plastic package
MCD212 13 motorola
rstout dtack cs lds uds csrom berr halt host i/f d15 d0 a22 a1 r/w int csio as a23 dtacksel tdi jtag test i/f tms tck tdo ica1/dca1 control display file decoder 1 ica2/dca2 control display file decoder 2 clk rstin clk2 clk2 v ss v dd misc. ica2/dca2 instructions visual effects real time decoder ica2/dca2 instructions ma9 ma0 md15 md0 lwr uwr cas1 dram control cas2 ras vsa vsd csync hsync display control vsync m/s blank figure 12. internal block diagram r(7:0) g(7:0) b(7:0)

there are two differences between the parts: 1. jtag testing has been added for automated board testing. the additional pins required to do this were v ss pins on the mcd211. hence, the MCD212 can be put in place of an mcd211 and will function identically. the functionality of the r/w , lds , uds , a1 a22, ras pins have been en- hanced. (see chapter 2 for the names of the new pins and the changes in functionality.) 2. also, the processor interface timing has been improved to allow operation with higher speed pro- cessors. this is detailed in section 11.3.
MCD212 21 motorola

aactiveo and ainactiveo or aassertedo and anegatedo are referred to in this user manual independent of whether the signal is active in the high (logic 1) state or the low (logic 0) state. the definition of the active level of each signal may be found in the individual pin descriptions.

mnemonic type name and function a1 a22 i system address lines. provides address for access from the system bus. must be stable when uds and/or lds are asserted. d0 d15 i/o bidirectional data bus, threestate. used to transfer data between system bus and vdsc. must be stable when uds or lds is asserted during write access. driven by vdsc during read cycles. d0 is the least significant bit. uds i upper data strobe. active low. when asserted, uds indicates that data is being addressed on d8 to d15. lds i lower data strobe. active low. when asserted, lds indicates that data is being addressed on d0 to d7. r/w i read/write. this input indicates transfer on the system bus. when low, indicates data is to be written into vdsc controlled resources or internal registers. when high, indicates a read is taking place. cs i chip select. active low. when asserted, indicates data transfer between system bus and vdsc controlled resources is enabled. validates address decode for system access. dtack i/o data transfer acknowledge signal. active low, threestate. asserted by vdsc when the system bus cycle, concerning vdsc controlled resources, can be continued. this pin must be pulled up externally. rstout o reset output. active low, open drain. asserted by the vdsc reset sequencer during the reset procedure. this pin must be pulled up externally. halt o halt line output. active low, open drain. asserted by the vdsc reset sequencer during the reset procedure. this pin must be pulled up externally. berr o bus error output. active low, threestate. asserted, when enabled, by the vdsc watchdog timer circuit if uds or lds is still asserted at the end of the timeout period. this pin must be pulled up externally.
MCD212 22 motorola csrom o chip select rom output. active low. asserted by an access on the system bus in the rom address area, and when uds and/or lds are asserted. csio o chip select i/o output. active low. asserted by an access on the system bus in the i/o area, and when uds and/or lds are asserted. int o interrupt request output. active low, threestate. used to generate interrupts to the cpu. this pin must be pulled up externally. mnemonic type name and function ma0 ma9 o memory address lines. multiplexed row/column address line outputs for dram control. md0 md15 i/o bidirectional memory data bus, threestate. used to transfer data between dram bus and vdsc. stable when lwr and/or uwr is asserted during a write cycle. driven by vdsc during read cycles. md0 is the least significant bit. ras o row address strobe. active low. validates the dram row address on the falling edge. cas1 i/o column address strobe for memory bank 1. active low, threestate. validates the dram column address on the falling edge. input during reset sequence to select/deselect memory bank 1. active high validates bank inputs. cas2 i/o column address strobe for memory bank 2. active low, threestate. validates the dram column address on the falling edge. input during reset sequence to select/deselect memory bank 2. active high validates bank inputs. uwr o write signal for dram. active low. it is asserted when writing md8 md15 to the dram. lwr o write signal for dram. active low. it is asserted when writing md0 md7 to the dram.
mnemonic type name and function r0 r7 o red color output (r7 = msb, r0 = lsb). threestate. g0 g7 o green color output (g7 = msb, g0 = lsb). threestate. b0 b7 o blue color output (b7 = msb, b0 = lsb). threestate. oe i output enable. active high. it disables threestate of rgb output. vsync i/o vertical synchronization. active low. in master mode, this output is used as vertical synchronization signal for monitor. in slave tv mode it becomes a vertical synchronization input. hsync o horizontal synchronization. active low. this output is used as a horizontal synchronization signal. csync o composite synchronization. active low. this output is used as a composite synchronization signal.
MCD212 23 motorola blank o blanking output. active low. it is asserted during vertical and horizontal blanking periods and high the rest of the time. vsd o video select for digital video. active low. this signal is synchronous to the digital video output. vsa o video select for analog video. active low. this signal is a clk2 clock cycle delayed version of vsd and synchronous to analog video after clocked d/a conversion. m/s i master/slave tv mode selection. when high, the vdsc generates the video timing. when low the vertical synchronization can be slaved to an external video timing.
mnemonic type name and function tck i jtag test clock input. provides the clock for the test logic defined by ieee std. 1149.11990. 100 k w internal pullup. tms i jtag test mode select input. the signal decoded by the tap controller to control test operations, defined by ieee std. 1149.11990. 100 k w internal pullup. tdi i jtag test data input. pin at which serial test instructions and data are received by the test logic, defined by ieee std. 1149.11990. 100 k w internal pullup. tdo ot jtag test data output. threestate. serial output for test instructions and data from the test logic defined by ieee std. 1149.11990. a23 ot system address line (threestated in functional mode). during jtag extest, a23 may drive system address line a23 offchip. as ot system address strobe (threestated in functional mode). during jtag extest, as may drive the system address strobe line as offchip. dtacksel i selects advance time of the falling edge of dtack before data (read) is valid on pins d0 d15. for designs using 68000/6807016 or 68340/34116 series processors, tie dtacksel low; for 68340/34125 designs, tie dtacksel high.
mnemonic type name and function clk i external clock input. rstin i reset input. active low. schmitt trigger. initiates a reset sequence. clk2 o clk/2 clock output. frequency is clk frequency divided by 2. clk2 o clk/2 clock output. frequency is clk frequency divided by 2. inverse of clk2. v dd i power supply pins (5 v). v ss i power and signal ground pins. note: all the pins are ttl compatible, except for clk and rstin , which use cmos levels.
MCD212 24 motorola
cmos input :clk cmos schmitt input :rstin ttl input :all inputs except clk, rstin 6 ma output :d0 d15, rstout , halt , berr , int , md0 md15, ma0 ma9, lwr , uwr , r0 r7, g0 g7, b0 b7, blank , csync , hsync , vsync , vsd , clk2, clk2 12 ma output :csio , csrom 16 ma output :ras , cas1 , cas2
MCD212 31 motorola the vdsc performs several 680x0 system control functions.
when the rstin pin is released, the timing chain counts eight video frames (= 8 x 312 x 112 x 16 clk cycles) in the default internal configuration at power on before the rstout (reset output) pin is re- leased, i.e., 160 ms with a 28 mhz crystal, 150 ms with a 30 mhz crystal, or 148 ms with a 30.2097 mhz crystal. the halt pin is released one video line later. at reset, vdsc registers are configured in the state indicated in section 3.2. rstin rstout = system reset halt t > 100 ms 1 video line power on figure 31. reset and halt timing chart the following bits in these control registers are reset by the reset input: image coding method register: (hco): bits 0, 1, 2, 3, 8, 9, 10, 11, 18 (plane a and b off, external video disabled) cursor control register: (hce): bit 23 (cursor disabled) background color register: (hd8): bits 0, 1, 2, 3 (black backdrop) the following bits in internal registers are reset by the reset input: csr1w: di1, dd1, dd2, td, dd, st, be csr2w: di2 dcr1: de, cf, fd, sm, cm1, ic1, dc1 dcr2: cm2, ic2, dc2 ddr1: mf1, mf2, ft1, ft2 ddr2: mf1, mf2, ft1, ft2
MCD212 32 motorola the result of a reset will be a constant black level at the rgb outputs and no video synchronization output. the active low reset pin must be connected to the system reset signal. the rstin also has an effect on the clock output clk2 (see figure 32). two different waveforms for clk2 are possible. it can be seen that clk2 is present during and after reset. clk rstin clk2 or clk2 figure 32. clk2 clocking and resetting clk2 is clocked by the positive edge of clk. its phase after reset is related to the rising edge of rstin . clk2 is always the inverse of clk2.

in order to have a proper startup, register csr1w must be initialized to the dram used. display and control data must be loaded in dram. register dcr1 must be initialized to the required display mode at a rising edge of the dabit (csr1r register). at a falling edge of the dabit (csr1r register), the debit (dcr1 register) must be set. now video synchronization is generated. on the next rising edge of the dabit, the ic1 bit (dcr1 register) and ic2bit (dcr2 register) must be set and on the next falling edge of the dabit the dc1bit (dcr1 register) and dc2bit (dcr2 register) must be set. now the rgb outputs will generate a picture.
after rstin is released the first four 680x0 word accesses are counted. if cs is asserted at such a word access, a chip select to the rom is given. the 680x0 first four accesses correspond to the ssp (system stack pointer) and the pc (program counter). the ssp and pc must be located at address h400000 and h400004 which are decoded during the swapping. address h0 to h7 are normally decoded afterwards. rtsin u/lds address access type h0 h2 h4 h6 pc rom rom rom rom rom or ram rom figure 33. memory swapping timing chart
MCD212 33 motorola
the vdsc is connected to the system bus via 22 address lines and upper and lower data strobes. the address decoding is validated by cs . table 31. address map h000000 h3fffff dram (4m byte) h400000 h4ffbff system rom (1m byte) h4ffc00 h4fffdf system i/o (1k byte) h4fffe0 h4fffef channel 2 internal registers h4ffff0 h4fffff channel 1 internal registers note:the system rom decoding asserts the csrom pin that is not sensitive to the r/w signal. this allows the use of static ram in the rom mapping area. the system i/o decoding asserts the csio pin.

a data transfer is initiated by an upper and/or lower data strobe (u/lds ) from the system. a data transfer is acknowledged by the vdsc via dtack . a data transfer is terminated by u/lds becoming inactive followed by dtack becoming inactive. the vdsc generates the data acknowledge (dtack ) depending on the addressed area: ? access to the dram is acknowledged as soon as it is certain that data can be read or written by the system. ? access to the system rom is acknowledged after a programmable number of clock or clk cycles. the dtack delay is controlled by control register csr1w. if u/lds becomes inactive before dtack is generated by the vdsc, dtack will not be generated. table 32. dtack delay for rom dd dd1 dd2 clk cycles 0 x x 11 12 1 0 0 3 4 1 0 1 5 6 1 1 0 7 8 1 1 1 9 10 note: access to the system i/o device (csio pin) is not acknowledged by the vdsc but by the addressed device.
MCD212 34 motorola
the berr signal is asserted if enabled by writing a 1 in the be (bus error) bit of the control register csr1w and if a data transfer is not acknowledged for at least one entire video line (approximately 64 m s) after selection. the be flag bit is then set in the csr2r register. the berr pin is released as soon as the cpu releases uds and lds . the be flag is reset when the cpu reads the csr2r status register. u/lds berr be flag bit read csr2r t > 1 video line dtack no dtack figure 34. bus error timing

the vdsc can generate interrupts to the cpu by asserting its int pin. the following conditions can generate an interrupt: ? the ica1/dca1 controller fetches an interrupt instruction. then, the it1 bit of the csr2r register is set. if the di1 bit in the csr1w register is reset to 0, the it1 bit of the csr2r register can generate an interrupt on the int pin. ? the ica2/dca2 controller fetches an interrupt instruction. then, the it2 bit of the csr2r register is set. if the di2 bit in the csr2w register is reset to 0, the it2 bit of the csr2r register can generate an interrupt on the int pin. int = not((not(di1) and it1) or (not(di2) and it2)) the it1 bit and it2 bit are reset after the cpu reads the csr2r register. the int pin is inactive when both it1 and it2 are reset (see equation above).
MCD212 41 motorola the vdsc has an onchip dynamic ram (dram) controller. it supports several dram configurations and performs dram arbitration, address multiplexing, timing generation, and refresh.

the dram types the vdsc can drive are 256k x 4, 1m x 4 and 256k x 16. they always form a 16bit data bus. the devices can be configured in one or two banks. six configurations are possible: ? 4 devices 256k x 4 (512k byte) ? 8 devices 256k x 4 (1m byte) ? 4 devices 1m x 4 (2m byte) ? 8 devices 1m x 4 (4m byte) ? 1 device 256k x16 (512k byte) ? 2 devices 256k x16 (1m byte) the td (type of device) bit of the csr1w register selects either 256k x 4, 256k x 16 (td = 0), or 1m x 4 (td = 1) dram type. the selection between one or two banks is done by fixing the cas1 and cas2 pins to a logical level during reset. cas1 corresponds to bank 1 and cas2 corresponds to bank 2. see table 41 for the address map of the dram banks. no dtack is generated for addresses outside a certain configura- tion.
MCD212 42 motorola table 41. address map of the dram banks address range a22 a21 a20 a19 a18 td = 0 td = 1 h000000 h03ffff 0 0 0 0 0 bank 1 bank 1 h040000 h07ffff 0 0 0 0 1 bank 2 bank 1 h080000 h0bffff 0 0 0 1 0 bank 1 h0c0000 h0fffff 0 0 0 1 1 bank 1 h100000 h13ffff 0 0 1 0 0 bank 2 h140000 h17ffff 0 0 1 0 1 bank 2 h180000 h1bffff 0 0 1 1 0 bank 2 h1c0000 h1fffff 0 0 1 1 1 bank 2 h200000 h23ffff 0 1 0 0 0 bank 1 bank 1 h240000 h27ffff 0 1 0 0 1 bank 2 bank 1 h280000 h2bffff 0 1 0 1 0 bank 1 h2c0000 h2fffff 0 1 0 1 1 bank 1 h300000 h33ffff 0 1 1 0 0 bank 2 h340000 h37ffff 0 1 1 0 1 bank 2 h380000 h3bffff 0 1 1 1 0 bank 2 h3c0000 h3fffff 0 1 1 1 1 bank 2

the vdsc allows the dram to be used simultaneously as both video and system memory so that a cpu can access any location of the entire memory space even during active video display time. additionally, the dram bus can be accessed by several masters and an arbitration scheme is imple- mented to provide each master with a guaranteed access time. the various masters are: ? the system bus (cpu or dma cycles) ? display decoder 1 ? display decoder 2 ? ica/dca controller 1 ? ica/dca controller 2 ? the dram refresh controller the dram access consists of consecutive display periods of 32 clk cycles, which are subdivided into four slots (see figure 41). the ch#1 slot is used by a video related function of channel 1 (display decoder 1 or ica/dca controller 1). the ch#2 slot is used by a video related function of channel 2 (display decoder 2 or ica/dca decoder 2). the dram refresh controller uses the ch#1 and ch#2 slots for ras only refresh with two dram rows per slot. the system slots are available for a dram access from the system bus (e.g., cpu or dma cycles) once every 16 clk periods. 16 cycles 16 cycles 1 display period (32 cycles) next display period ch#1 ch#2 ch#1 ch#2 sys. sys. sys. sys. figure 41. dram access
MCD212 43 motorola eleven clk periods are used for accessing ch#1 or ch#2 data, as shown in figure 43. this repre- sents four dram accesses for data. these four 16bit words can represent varying amounts of pixel data in plane #1 or plane #2. for example, when using rgb555 data type, the four accesses repre- sent color information for four pixels. (note: only plane 2 is available with rgb555 data; therefore, one complete display period contains color information for eight pixels.) the remaining five clk peri- ods are used for one dram access for system data. when no video or refresh functions are required, the access to dram is freerunning with no display periods, so that a system bus access can be accepted at any time. examples of this are after a stop instruction in ica/dca or during runlength files. the selection between display, ica, dca, and refresh is done according to figure 42, the time domain of a video frame. rf display rf dca ica freerun video field vert. res video line 1 1 horiz. res/8 + 1 0 to 8 notes: 1. rf is the refresh time area. eight dram rows are refreshed per video line. 2. ica and dca only exist if enabled. 3. the freerun area starts when the ica/dca is completed or when an ica/dca stop instruction is encountered. 4. if the display is not enabled, the entire area is freerun except the refresh areas. 5. each number is the number of display periods (32 clk cycles). 6. horizontal resolution is the number of pixels in normal resolution. figure 42. dram cycles example: the ica time is at the beginning of each vertical field as shown in figure 42. if there are no ica instructions to execute, then this is freerun time. there is one display period when eight row addresses can be refreshed. then, to calculate the maximum number of display periods in the display area, divide the normal resolution by 8 and add 1 (i.e., 384/8 = 48). then there is one display period for refresh. next is the dca time if it has been enabled. the number of pixel periods of the dca is programmed in the dcr register, with 8 (= 64 bytes) being the maximum. the rest of the video line time is then available as freerun time.
MCD212 44 motorola
the dram timing is based on the clk clock (see figure 43). clk ras cas1 cas2 uwr lwr md0 md15 write md0 md15 read ?? ?? ??? ??? ??? ??? ?? ?? ?? ?? system ch#1 or ch#2 row col row col col col col ma0 ma9 figure 43. dram timing in the ch#1/ch#2 slot a burst of four words are read in fast page mode. if a page break occurs, the burst is incomplete. in the system slot a random read or write is possible. the memory address bus (ma) is multiplexed in order to present the row address on ras falling edge and the column address on cas1 or cas2 falling edge. the correspondence between memory ad- dress bus, ma0 ma9 and system address a1 a22 is indicated in table 42. cas1 and cas2 function as bank select signals (see table 43). table 42. memory address distribution ma0 ma1 ma2 ma3 ma4 ma5 ma6 ma7 ma8 ma9 ras a11 a12 a13 a14 a15 a16 a17 a18 ax a19 cas a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 ax = a10 for td = 0 (256k x 4, 256k x 16) ax = a18 for td = 1 (1m x 4) table 43. cas1 and cas2 assertion td = 0 cas1 asserted if validated and a18 = 0, a19 = 0, a20 = 0, a22 = 0 cas2 asserted if validated and a18 = 1, a19 = 0, a20 = 0, a22 = 0 td = 1 cas1 asserted if validated and a20 = 0, a22 = 0 cas2 asserted if validated and a20 = 1, a22 = 0
MCD212 45 motorola
during the reset period, banks can be devalidated if their corresponding cas pin is grounded. no dtack is generated for devalidated banks. a pullup is needed to validate banks. ?? ?? ?? 10k gnd casx devalidation of banks casx ?? ?? ?? + 22k validation of banks figure 44. dram banks validation/devalidation
tables 44 thru 46 show how the 256k x 4, 1m x 4, and 256k x 16 type drams are connected to the vdsc. table 44. implementing 256k x 4 dram bank 1 bank 2 dram 1 dram 2 dram 3 dram 4 dram 5 dram 6 dram 7 dram 8 md0 md3 d0 d3 d0 d3 md4 md7 d0 d3 d0 d3 md8 md11 d0 d3 d0 d3 md12 md15 d0 d3 d0 d3 ma0 ma8 a0 a8 a0 a8 a0 a8 a0 a8 a0 a8 a0 a8 a0 a8 a0 a8 lwr w w w w uwr w w w w ras ras ras ras ras ras ras ras ras cas1 cas /oe cas /oe cas /oe cas /oe cas2 cas /oe cas /oe cas /oe cas /oe
MCD212 46 motorola table 45. implementing 1m x 4 dram bank 1 bank 2 dram 1 dram 2 dram 3 dram 4 dram 5 dram 6 dram 7 dram 8 md0 md3 d0 d3 d0 d3 md4 md7 d0 d3 d0 d3 md8 md11 d0 d3 d0 d3 md12 md15 d0 d3 d0 d3 ma0 ma9 a0 a9 a0 a9 a0 a9 a0 a9 a0 a9 a0 a9 a0 a9 a0 a9 lwr w w w w uwr w w w w ras ras ras ras ras ras ras ras ras cas1 cas /oe cas /oe cas /oe cas /oe cas2 cas /oe cas /oe cas /oe cas /oe table 46. implementing 256k x 16 dram bank 1 dram 1 bank 2 dram 2 md0 md15 d0 d15 d0 d15 ma0 ma8 a0 a8 a0 a8 lwr lw lw uwr uw uw ras ras ras cas1 cas /oe cas2 cas /oe
MCD212 51 motorola the vdsc is programmable on a linebyline (dca) and/or fieldbyfield (ica) basis. the image displayed by the vdsc is made up of four distinct, programmable graphics planes, as indicated in figure 51. the foremost is the cursor plane, behind which are two video planes (a and b), and behind them is a background plane. the data for plane a is handled by ch#1, while ch#2 handles the b plane data. the order in which graphics planes a and b are displayed is controllable via the plane order register (hc2) through ch#1. ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? background/external video graphics plane b cursor plane graphics plane a figure 51. four video planes of the displayed image the vdsc is programmable for several predefined modes of display and contains two video start address registers (vsr1 and vsr2) to locate the video displays within the dram address space. the display logic reads words from the video display area and sends them to the display file decoder which serializes the data, either nibble per nibble or byte per byte. this programmability and flexibility allows the vdsc to do various special effects such as subscreens, windowing, mosaics, overlay and mixing, and transparency, among others.
the vdsc supports ntsc monitor, ntsc tv, and pal tv formats as well as providing a means to display images in one format that were created in the other. this compatibility feature allows this part to be used throughout the world. also, interlace and noninterlace displays are supported. ntsc is the north american and japanese standard for broadcast tv. the display is made up of 525 horizontal lines, counted in the vertical direction, displayed 30 times in one second. ntsc monitor is a littleused standard in north america for instudio use on monitors. it is also made up of 525 horizontal lines. pal is the european standard for broadcast tv. its display is made up of 625 horizontal lines, counted in the vertical direction, but only displayed 25 times each second. both systems allow for an image (or frame) to be made up of two fields, an odd and an even field. the field rate is twice the frame rate (60 hz for ntsc and 50 hz for pal). although each frame is made up of 525/625 lines, only 480/560 are visible on the screen.
MCD212 52 motorola
the normal fullscreen resolution of the vdsc is shown in table 51. table 51. normal fullscreen display resolution display number of pixels horizontally number of pixels vertically ntsc monitors 360 240 ntsc tvs 384 240 pal tvs 384 280 in addition to normal resolution, the vdsc provides both double resolution and high resolution modes. double resolution is defined as twice the normal resolution in the horizontal direction, whereas high resolution is defined as twice the resolution in both horizontal and vertical directions. although most tvs are not capable of clearly displaying single pixels in double resolution mode, this mode is useful in two areas: ? where double resolution pixel pairs can give increased positional accuracy. ? where a single pixel's reduced display quality does not reduce the identifiability of the graphic object or character (i.e., kanji characters). normal resolution (single pixels) double resolution (pixel pairs) double resolution (single pixels) figure 52. example of normal and double resolution pixels the horizontal resolution can be different between the two graphics planes (a and b) but both are controlled by various factors; the cf (crystal frequency) bit in the dcr1 register, the st (standard) bit in the csr1w register, the cm1(color mode 1) bit in the dcr1 register, the cm2 (color mode 2) bit in the dcr2 register, and the frequency of the crystal. the effects of the various bits on the resolu- tion are shown in table 52. table 52. horizontal resolution frequency pixels/line active line display cf st frequency (mhz) cm = 0 cm = 1 active line ( m s) display system 0 x 28 360 720 51.4 ntsc monitor 1 0 30/30.2097 384 768 51.2/50.84 pal/ntsc tv 1 1 30/30.2097 360 720 48/47.67 pal/ntsc tv
MCD212 53 motorola

the vertical resolution is dependent on the sm (scan mode) bit of the dcr1 register, the fd (frame duration) bit which is also in the dcr1 register, and the st (standard) bit which is in the csr1w register. the sm bit controls the scan mode of the vdsc by selecting between the interlace mode and the noninterlace mode as described in table 53 and shown in figure 53. table 53. scan modes sm scan mode description 0 noninterlace mode. one image is composed of one field. 1 interlace mode. one image is composed of two fields. noninterlace mode interlace mode line 1 line 2 line 3 line n line 1 line 3 line n1 line 5 line 2 line 4 line 6 line n line 1 line 3 line n1 line 5 line 2 line 4 line 6 line n odd field + even field = total image image ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 53. line display of interlace versus noninterlace modes the fd bit and the st bit only affect the display in the noninterlace mode. they are shown in table 54. table 54. vertical resolution in the noninterlace mode fd st # of video lines frame duration (ms) image frequency (hz) display type 0 0 280 18 50 pal 1 1 240 15.3 50 pal 1 x 240 15.3 60 ntsc
MCD212 54 motorola the following tables and figures depict the horizontal and vertical timing for the hsync , vsync , csync , and blank signals in the master mode. hsync blank a b c de a: total horizontal line duration b: active horizontal line duration 1 cycle = 16 clk periods 1 cycle = 571.43 ns (clk = 28 mhz ntsc monitor) 1 cycle = 533.33 ns (clk = 30 mhz pal tv) 1 cycle 529.63 ns (clk = 30.2097 mhz ntsc tv) notes: figure 54. hsync and blank timing table 55. horizontal synchronization timing cf=0 clk= 28 mhz cf = 1 st=0 clk = 30 mhz clk = 30 2097 mhz cf = 1 st=1 clk = 30 mhz clk = 30 2097 mhz cf = 0 (cycles) 28 mh z ( m s) st = 0 (cycles) 30 mh z ( m s) 30 . 2097 mh z ( m s) st = 1 (cycles) 30 mh z ( m s) 30 . 2097 mh z ( m s) a 112 64.0 120 64.0 63.56 120 64.0 63.56 b 90 51.43 96 51.2 50.84 90 48.0 47.67 c 19 10.9 20 10.7 10.59 23 12.3 12.18 d 3 1.71 4 2.13 2.12 7 3.7 4.77 e 8 4.57 9 4.8 4.77 9 4.8 4.77 g 4 2.29 4 2.13 2.12 4 2.13 2.12 h 8 4.57 9 4.8 4.77 9 4.8 4.77 vsync blank j k l mp notes: j = total vertical display period k = active vertical display p = vertical sync width figure 55. vsync and blank timing
MCD212 55 motorola table 56. vertical synchronization timing (in lines)* 50 hz (fd = 0) 60 h (fd 1) st = 0 st = 1 60 hz (fd = 1) j 312 312 262 k 280 240 240 l 26 46 18 m 6 26 4 p 2.5 2.5 3 * noninterlace mode (sm = 0) table 57. vertical synchronization timing (in lines) 50 hz (fd = 0) 60 hz (fd = 1) odd field (pa = 1) even field (pa = 0) odd field even field st = 0 st = 1 st = 0 st =1 odd field (pa = 1) even field (pa = 0) j 312.5 312.5 312.5 312.5 262.5 262.5 k 280 240 280 240 240 240 l 26 46 26.5 46.5 18 18.5 m 6.5 26.5 6 26.5 4.5 4 p 2.5 2.5 2.5 2.5 3 3 * interlace mode (sm = 1) notes: to determine the time from the number of display lines, simply multiply the number of lines by the total line width (not the active display width). for instance, in an ntsc system with a 63.56 m s (from table 55) line width, the total vertical display time for an interlace display is: 63.56 m s x 262.5 lines = 16.6845 ms or the display rate is: 59.94 hz. vsync p csync 31031131212345 figure 56. csync timing in the 50 hz (fd = 0), noninterlace mode (sm = 0) vsync p csync 26026126212345 figure 57. csync timing in the 60 hz (fd = 1), noninterlace mode (sm = 0)
MCD212 56 motorola vsync p csync (odd field) 623 624 625 1 2 3 4 5 310 311 312 313 314 315 316 317 csync (even field) 318 a a/2 gh figure 58. csync timing in the 50 hz (fd = 0), interlace mode (sm = 1) vsync p csync (odd field) 523 524 525 1 2 3 4 5 260 261 262 263 264 265 266 267 csync (even field) 268 figure 59. csync timing in the 60 hz (fd = 1), interlace mode (sm = 1) the vdsc offers the possibility to fetch control information during vertical and horizontal retrace peri- ods from the image control area (ica) and dynamic control area (dca), respectively. each video channel has its associated ica and dca. for channel 1 this is ica1 and dca1, and for channel 2 this is ica2 and dca2. ica/dca control is identical and independent for both channels.
ica control consists of fetching longword instructions during the vertical retrace period. the ica pointers are indicated in table 58. table 58. ica pointer addresses ni l interlace noninterlace odd field (pa = 1) even field (pa = 0) channel 1 (ica1) h400 h400 h404 channel 2 (ica2) h200400 h200400 h200404 note: odd and even fields are indicated by the pa bit in the csr1r register.
MCD212 57 motorola the possible number of ica fetches is equal to the lines during vertical retrace times the display line width expressed in long words. example: the number of crystal periods needed for a longword access depends on the type of data being fetched. however, for example, if each access required five crystal periods then the following num- bers would apply. from table 55: the total number of (16 clk period) cycles = 120 per line. so, there are 120 x 16 = 1920 crystal periods. from table 56: the number of lines in vertical blanking is 262 240 = 22 lines for the noninter- lace mode. therefore, there are: 22 x 1920 = 42,240 crystal periods during vertical blanking and 42,240/16 = 2640 memory fetches. the video start register is also used as an ica pointer after a areload vsro instruction to perform indirect ica addressing during ica instruction fetches to allow for linking blocks of instructions. all areload vsro instructions must contain an address with a0 = 0, a1 = 0, and a2 = 0. each block ending with a areload vsro instruction must contain an even number of instructions including the areload vsro instruction, except for the first block.
the instruction fetch takes place in the horizontal retrace period. the dca size is 64 bytes/line. the dca is completely independent of the bit map or display file areas. the dca pointer (dcp) points to the first line of the dca. the second dca line is pointed to automatically by dcp + 64 bytes. the dcp can be changed at any time by the areload dcp and stopo instruction. this allows for linking blocks of instructions on a linebyline basis.
the ica and dca are enabled by the de bit in the dcr1 register. the ic and dc bits of the dcr register control three possible ica/dca modes. table 59. ica1/dca1 and ica2/dca2 modes ica1/dca1 modes ica2/dca2 modes de ic1 dc1 ica1 dca1 de ic2 dc2 ica2 dca2 1 0 x no no 1 0 x no no 1 1 0 yes no 1 1 0 yes no 1 1 1 yes yes 1 1 1 yes yes 0 x x no no 0 x x no no when ic and dc are set to 1, the number of possible dca fetches can be limited by the line retrace duration as indicated in the following tables.
MCD212 58 motorola table 510. possible dca1/dca2 fetches per line possible dca1 fetches per line possible dca2 fetches per line ic1 dc1 cf dca1 (in bytes) ic2 dc2 cf dca2 (in bytes) 0 x x 0 0 x x 0 1 0 x 0 1 0 x 0 1 1 0 32 1 1 0 32 1 1 1 64 1 1 1 64 note: an automatic stop instruction is performed at the end of the available area (when the effective dca is larger than indicated). the allocated memory size is always 64 bytes even if the possible number of fetches is lower.
ica/dca instructions are contained in the system ram. they are longword aligned and longword wide. the most significant byte indicates which register or registers are updated by the information contained in the other bytes. the instructions can be divided into two groups. the instructions from the first group affect the control of the instruction fetches, the display parameters, and interrupt generation (see table 511). the instructions from the second group affect the video decoder and visual effects part (see chapter 11). the control of the instructions fetches and display parameters can also be affected by the system (cpu). none of the registers can be read by the system. table 511. ica control instructions instruction (bit 31 0) acronym action 0000 stop stop the control sequence. the instruction fetches are stopped until the next field. 0001 nop no operation. 0010 pp pppp pppp pppp pppp pp reload dcp reload the dcp register and its associated address counter with the specified pointer (p). 0011 pp pppp pppp pppp pppp pp reload dcp and stop reload the dcp register and its associated address counter with the specified pointer (p) and stop control fetches as stop instruction. 0100 pp pppp pppp pppp pppp pppp reload vsr reload ica pointer. it functions as a jump instruction. it does not affect the vsr pointer. 0101 pp pppp pppp pppp pppp pppp reload vsr and stop reload the vsr register and the video address counter with the specified pointer and stop the control fetches as stop instruction. 0110 interrupt set it bit in csr register. 0111 1 0b cdef reload display parameters b = cm c = mf1 d = mf2 e = ft1 f = ft2
MCD212 59 motorola table 512. dca control instructions instruction (bit 31 0) acronym action 0000 stop stop the control sequence. the instruction fetches are stopped until the next field. 0001 nop no operation. 0010 pp pppp pppp pppp pppp pp reload dcp no operation. 0011 pp pppp pppp pppp pppp pp reload dcp and stop reload the dcp register and its associated address counter with the specified pointer (p) and stop control fetches as stop instruction. 0100 pp pppp pppp pppp pppp pppp reload vsr reload the vsr register and the video address counter with the specified pointer. 0101 pp pppp pppp pppp pppp pppp reload vsr and stop reload the vsr register and the video address counter with the specified pointer and stop the control fetches as stop instruction. 0110 interrupt set it bit in csr register. 0111 1 0b cdef reload display parameters b = cm c = mf1 d = mf2 e = ft1 f = ft2 via several internal registers, the clut and the cursorram, it is possible to program the realtime decoder of the vdsc and to perform visual effects. during the vertical and horizontal retrace periods, the vdsc can load abovementioned registers/rams. each instruction consists of a longword. the most significant byte indicates the register involved; the remaining three bytes contain control data. the instructions are transferred via ch#1 or ch#2, which are byte wide with the most significant byte first.
MCD212 510 motorola table 513. register map channel no. address (h) register name 1+2 80 to bf clut color 0 63 1 c0 image coding method 1 c1 transparency control 1 c2 plane order 1+2 c3 clut bank 1 c4 transparent color for plane a e c5 reserved 2 c6 transparent color for plane b 1 c7 mask color for plane a e c8 reserved 2 c9 mask color for plane b 1 ca dyuv abs. start value for plane a 2 cb dyuv abs. start value for plane b e cc reserved 1 cd cursor position 1 ce cursor control 1 cf cursor pattern 1+2 d0 to d7 region control 0 7 1 d8 backdrop color 1 d9 mosaic pixel hold for plane a 2 da mosaic pixel hold for plane b 1 db weight factor for plane a 2 dc weight factor for plane b e dd to ff reserved
programmable via ch#1 and ch#2. table 514. clut color register 0 63 e address h80 hbf 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r7 r6 r5 r4 r3 r2 e e g7 g6 g5 g4 g3 g2 e e b7 b6 b5 b4 b3 b2 e e r7 r2, g7 g2, and b7 b2 contain the colordata of one pixel. only the 6 msbs per byte are implemented. the clut ram is addressable in two steps. first, one of the four clut banks must be selected via the clut bank register (address a7, a6). second, the address within the bank is given by selecting a clut register h80 hbf.
MCD212 511 motorola table 515. clut ram addresses clut bank clut 0 63 clut address (h) 0 00 (reg. 80) 3f (reg. bf) 00 3f 1 00 (reg. 80) 3f (reg. bf) 40 7f 2 00 (reg. 80) 3f (reg. bf) 80 bf 3 00 (reg. 80) 3f (reg. bf) c0 ff
programmable via ch#1. table 516. image coding method register e address hc0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e cs e e nr ev e e e e e e c m 23 c m 22 c m 21 c m 20 e e e e c m 13 c m 12 c m 11 c m 10 cs: clut select for dual 7bit cluts: 0 = clut bank 0 and 1 1 = clut bank 2 and 3 nr: number of region flags: 0 = one region flag is used 1 = two region flags are used ev: external video enable: 0 = disabled 1 = enabled table 517. cm1x, cm2x: coding method for plane a, b input channel mode resolution cm 23 cm 22 cm 21 cm 20 cm 13 cm 12 cm 11 cm 10 ch#1 off e e e e e 0 0 0 0 ch#2 off e 0 0 0 0 e e e e ch#1 clut8 normal e e e e 0 0 0 1 ch#1 clut7 normal e e e e 0 0 1 1 ch#1 clut7+7 normal e e e e 0 1 0 0 ch#1 dyuv normal e e e e 0 1 0 1 ch#1 clut4 double e e e e 1 0 1 1 ch#1 + ch#2 rgb555 normal 0 0 0 1 e e e e ch#2 clut7 normal 0 0 1 1 e e e e ch#2 dyuv normal 0 1 0 1 e e e e ch#2 clut4 double 1 0 1 1 e e e e
MCD212 512 motorola

programmable via ch#1. table 518. transparency control register e address hc1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mx e e e e e e e e e e e tb3 tb2 tb1 tb0 e e e e ta3 ta2 ta1 ta0 mx: disable mixing: 0 = mix 1 = no mix table 519. transparency control register e address hc1 ta3 tb3 ta2 tb2 ta1 tb1 ta0 tb0 pixel is transparent if: 0 0 0 0 always (plane disabled) 0 0 0 1 color key = true 0 0 1 0 transparency bit = 1 0 0 1 1 region flag 0 = true 0 1 0 0 region flag 1 = true 0 1 0 1 region flag 0 or color key = true 0 1 1 0 region flag 1 or color key = true 0 1 1 1 n.u. 1 0 0 0 never (no transparent area) 1 0 0 1 color key = false 1 0 1 0 transparency bit = 0 1 0 1 1 region flag 0 = false 1 1 0 0 region flag 1 = false 1 1 0 1 region flag 0 or color key = false 1 1 1 0 region flag 1 or color key = false 1 1 1 1 n.u. note: ta, tb = select transparency mechanism for plane a, b individually.
programmable via ch#1. table 520. plane order register e address hc2 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e e e e e e e e e e e e e e e e e e e e e o3 o2 o1
MCD212 513 motorola table 521. plane order o3 o2 o1 plane order 0 0 0 plane a in front of plane b 0 0 1 plane b in front of plane a note: all other values are not used. programmable via ch#1 and ch#2 independently. table 522. clut bank register e address hc3 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e e e e e e e e e e e e e e e e e e e e e e a7 a6 table 523. bank select a7 a6 bank select 0 0 bank 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 note: only banks 2 and 3 are programmable (a7 = 1) via ch#2. hc4: programmable via ch#1 for plane a. hc5: reserved. hc6: programmable via ch#2 for plane b. table 524. transparent color register e address hc4 hc6 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r7 r6 r5 r4 r3 r2 e e g7 g6 g5 g4 g3 g2 e e b7 b6 b5 b4 b3 b2 e e transparent color is only defined for the clut mode: clut8, clut7, clut7 + 7, and clut4.

hc7: programmable via ch#1 for plane a. hc8: reserved. hc9: programmable via ch#2 for plane b. table 525. mask color register e address hc7 hc9 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r7 r6 r5 r4 r3 r2 e e g7 g6 g5 g4 g3 g2 e e b7 b6 b5 b4 b3 b2 e e mask color is only defined for the clut mode: clut8, clut7, clut7 + 7, and clut4.
MCD212 514 motorola

hca: programmable via ch#1 for plane a. hcb: programmable via ch#2 for plane b. table 526. delta yuv absolute start value register e address hca hcb 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 y7 y6 y5 y4 y3 y2 y1 y0 u7 u6 u5 u4 u3 u2 u1 u0 v7 v6 v5 v4 v3 v2 v1 v0 hca: yuv start value for plane a. hcb: yuv start value for plane b. y,u,v = absolute y,u,v start value. programmable via ch#1. table 527. cursor position register e address hcd 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e e y9 y8 y7 y6 y5 y4 y3 y2 y1 y0 e e x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 y9 y0: cursor yposition: y9 = msb y0 = lsb x9 x0: cursor xposition in double resolution: x9 = msb x0 = lsb x y figure 510. cursor position the cursor origin is always the top lefthand corner of the fullscreen display.
MCD212 515 motorola
programmable via ch#1. table 528. cursor control register e address hce 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en bl kc co n2 co n1 co n0 co f2 co f1 co f0 cu w e e e e e e e e e e e y r g b en: cursor enable: 0 = cursor disable (transparent) 1 = cursor enabled blkc: blink type: 0 = on/off 1 = on/complement con2 con0: period of the cursor on: period = 12 * (convalue) * (fieldperiod) cof2 cof0: period of the cursor off: period = 12 * (cofvalue) * (fieldperiod) if cof = 0 the cursor is on indefinitely. table 529. cursor color y r g b cursor color 0 0 0 0 black 0 0 0 1 halfbrightness blue 0 0 1 0 halfbrightness green 0 0 1 1 halfbrightness cyan 0 1 0 0 halfbrightness red 0 1 0 1 halfbrightness magenta 0 1 1 0 halfbrightness yellow 0 1 1 1 halfbrightness white 1 0 0 0 black 1 0 0 1 blue 1 0 1 0 green 1 0 1 1 cyan 1 1 0 0 red 1 1 0 1 magenta 1 1 1 0 yellow 1 1 1 1 white cuw: cursor resolution: 0 = normal resolution for horizontal direction 1 = double resolution for horizontal direction
MCD212 516 motorola
programmable via ch#1. table 530. cursor pattern register e address hcf 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e e e e ad 3 ad 2 ad 1 ad 0 cp 15 cp 14 cp 13 cp 12 cp 11 cp 10 cp 9 cp 8 cp 7 cp 6 cp 5 cp 4 cp 3 cp 2 cp 1 cp 0 ad3 ad0: y address register cp15 cp0: line pattern register: cp15 is the leftmost pixel. cp0 is the rightmost pixel. ad 0 hex f hex cp15 cp0 figure 511. cursor pattern diagram
programmable via ch#1 and ch#2. in case the registers are loaded simultaneously from both channels, then ch#1 has the first priority. at that moment ch#2 will be ignored. if the region control is not used, then the operation code op3 op0 of the region control register d0 and d4 must be 0000. this means the end of the region control for the line. table 531. region control register e address hd0 hd7 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 op 3 op 2 op 1 op 0 e e e rf wf 5 wf 4 wf 3 wf 2 wf 1 wf 0 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 op3 op2 op1 op0: operation control
MCD212 517 motorola table 532. operation control codes op3 op2 op1 op0 operation control 0 0 0 0 end of region control for the line 0 0 0 1 n.u. 0 0 1 0 n.u. 0 0 1 1 n.u. 0 1 0 0 change weight of plane a. new weightvalue is wf50 0 1 0 1 n.u. 0 1 1 0 change weight of plane b. new weightvalue is wf5 wf0 0 1 1 1 n.u. 1 0 0 0 reset region flag 1 0 0 1 set region flag 1 0 1 0 n.u. 1 0 1 1 n.u. 1 1 0 0 reset region flag and change weight of plane a 1 1 0 1 set region flag and change weight of plane a 1 1 1 0 reset region flag and change weight of plane b 1 1 1 1 set region flag and change weight of plane b rf: region flag to be changed: 0 = region flag 0 1 = region flag 1 the rf bit is only valid if the nr bit in register coh is 0. wf5 wf0: next new weight factor value x9 x0: xposition: distance from the lefthand edge of display, in double resolution.
programmable via ch#1. table 533. background color register e address hd8 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e e e e e e e e e e e e e e e e e e e e y r g b y r g b: color of backdrop plane
MCD212 518 motorola table 534. color of background plane y r g b color of background 0 0 0 0 black 0 0 0 1 halfbrightness blue 0 0 1 0 halfbrightness green 0 0 1 1 halfbrightness cyan 0 1 0 0 halfbrightness red 0 1 0 1 halfbrightness magenta 0 1 1 0 halfbrightness yellow 0 1 1 1 halfbrightness white 1 0 0 0 black 1 0 0 1 blue 1 0 1 0 green 1 0 1 1 cyan 1 1 0 0 red 1 1 0 1 magenta 1 1 1 0 yellow 1 1 1 1 white !
hd9: programmable via ch#1 for plane a. hda: programmable via ch#2 for plane b. table 535. mosaic pixel hold factor register e address hd9, hda 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en e e e e e e e e e e e e e e e z7 z6 z5 z4 z3 z2 z1 z0 en: pixel hold enable: 0 = mosaic off 1 = mosaic on z7 z0: number of pixels to be held: 0 = reserved 1 = normal usage 2255 = mosaic effect the pixel hold factor is effective at both normal and double resolution. hdb: programmable via ch#1 for plane a. hdc: programmable via ch#2 for plane b. table 536. weight factor register e address hdb hdc 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en e e e e e e e e e e e e e e e e e w5 w4 w3 w2 w1 w0 w5 w0: weight factor value: w5 = msb w0 = lsb
MCD212 519 motorola for bitmap files, the width of the bitmap is related to that of the display line, but not necessarily the same (see table 537). for mosaic files, the width of the bitmap is divided by the mosaic factor. for runlength files, the bitmap width is not related to the display width. the video start pointer (vsr) points to the first pixel in a bitmap. in case of interlace mode this is the first pixel of the odd field. the bitmap of the even field follows the one of the odd field. if no reload of the vsr is performed the first pixel of a line is consecutive to the last pixel of the previous line for all file types. if in the dca, a reload of the vsr is performed, the vsr will point to the first pixel of the following line. in the next frame, the reloaded vsr points to the first pixel of the (odd) frame. table 537. bitmap width for bitmap files cf st cm horizontal resolution (pixels) bitmap width (bytes) 0 0 0 360 360 0 0 1 720 360 0 1 0 360 384 0 1 1 720 384 1 0 0 384 384 1 0 1 768 384 1 1 0 360 360 1 1 1 720 360

" !" the vertical action of the st bit is to display images created with a 60 hz system in a 50 hz system and is possible only in 50 hz mode (fd = 0). if st is set to 1, the vertical display area and blanking area have 40 lines less, 20 less at the top and 20 less at the bottom. the vertical resolution becomes 240 lines. " !# " the action is to display images created with a 28 mhz system in a 30 mhz system and vice versa. in the 28 mhz mode, if st = 1, the horizontal resolution is unchanged (360 pixels) but the number of pixel fetches continue to 384. this allows the use of a 384 pixels bitmap file or the detection of the zero code (end of line) in a runlength line (see section 6.2). if st = 0, the resolution and the width of the bitmap are 360 pixels. in the 30 mhz mode, if st = 1, the horizontal resolution and the width of the bitmap are decreased from 384 to 360 pixels. twelve pixels are masked on either side of the screen, giving a centered image. the horizontal display area is reduced by 24 pixels. this allows for the display of a 360pixel bitmap. the blank pin now has a zero state during the masking area of 2 x 12 pixels. n.b.: the explanation above concerns normal resolution display. with double resolution display all the widths must be doubled.
MCD212 520 motorola

if the de (display enable) bit in the dcr1 register is set, the vdsc generates video synchronization at outputs hsync , vsync , csync and blank . if de is reset, the hsync , vsync, and csync outputs are high and the blank output is low. the vdsc may work in master or in slave tv mode. selection of the mode is done with the m/s pin. if the m/s (master/slave) pin is pulled up, then the master mode is selected. if this pin is pulled down then the slave tv mode is selected. table 538. synchronization modes m/s synchro mode hsync csync vsync 1 master out out out 0 slave tv out out in in the master mode, the hsync , csync, and vsync signals are generated as output. in the slave tv mode, hsync and csync are generated as output, the vsync pin is in the input mode and must receive an external vsync signal. an even frame is displayed if the falling edge of the vsync input falls in the range from 1/4 to 3/4 between two successive falling edges of the hsync output. an odd frame is displayed if the falling edge of vsync falls outside this range. hsync is input to the phase comperator of an external phaselock loop oscillator supplying clk. the other input of the phase comparator is an external hsync signal. vsync ext. video subsystem external pll hsync hsync clk vdsc figure 512. vdsc in slave mode with an external pll for clock generation vsync ext. video subsystem hsync clk vdsc figure 513. vdsc in slave mode with an external clock
MCD212 61 motorola
the vdsc contains two identical and independent display file decoders, one for channel 1 (plane a) and one for channel 2 (plane b). each can handle three types of files: ? normal file or bitmap file: each pixel has its own address. ? runlength file: consecutive identical pixels (bytes or associated nibbles) are grouped in the same block of information. ? mosaic file: as with a normal file but with resolution divided by a mosaic factor. the vdsc is in charge of duplicating each pixel according to the mosaic factor (2, 4, 8, or 16). the initialization of the file type is made with the ft1 ft2 bits of the ddr1 and ddr2 register: table 61. file type of display 1 ft 1 ft 2 display 1 file type 0 x bitmap 1 0 runlength 1 1 mosaic note: file type of display 1 is indicated in ddr1 register. table 62. file type of display 2 ft 1 ft 2 display 1 file type 0 x bitmap 1 0 runlength 1 1 mosaic note: file type of display 2 is indicated in ddr2 register.
the pixel data are packed in the memory. four words are fetched per memory access. these words are always page aligned in the dram. the first pixel of a line can be any of the eight bytes in the first access. each word that the vdsc fetches in the memory for display is serialized according to figures 61 and 62.
MCD212 62 motorola 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7654321076543210 1st byte 2nd byte memory data bus md15 md0 pixel 1 pixel 2 figure 61. bitmap serialization in 8 bits/pixel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1st nibble memory data bus md15 md0 2nd nibble 3rd nibble 4th nibble bit bit bit bit bit bit bit bit 32 1 0 32 1 0 32 1 0 32 1 0 pixel 1 pixel 2 pixel 3 pixel 4 figure 62. bitmap serialization in 4 bits/pixel

the runlength coding technique permits file compression by grouping into one block consecutive pixels that have the same color. the vdsc uses either a 7 or a 3bit color look up table (clut) to provide either 1 out of 128 colors or 1 out of 8 different colors. the runlength compression is applied to each video line independently of the others. the runlength file is organized as a list of information about pixels without any notion of width or height as in bitmap files. (refer to section 7.2, clut de- coder.) runlength 7bit clut files are either a single byte (for a single pixel) or two bytes (for a run of pixels on a single line) in length. a 0 in the first bit indicates a single pixel clut address whereas a 1 in the first bit indicates a run of pixels on the present line. the run only extends to the end of the line and does not continue to the next line. the second byte indicates the number of identical pixels to be reproduced on the current line. a 0 in the second byte indicates that this color is to be repeated to the end of the line. a 1 is forbidden in the second byte. the eight bits allowed for 2 to 255 identical bits to be repeated or with a 0, the rest of the line will have the same pixel repeated. every line must finish with a azerolengtho run (n = 0), which means that at a minimum, the last two pixels of the line are identical. figure 63 shows the format for both. single pixel multiple pixels 0 1 7bit clut address 7bit clut address 76 0 15 14 8 7 0 note: n = 0 means aduplicate this pixel to the end of the lineo. n = 1 is forbidden. n = number of identical pixels (8 bits) figure 63. runlength format in 7 bits/pixel
MCD212 63 motorola the runlength 3bit clut files are similar to the 7bit files except that instead of a single pixel, this format specifies pixel pairs. also, instead of 7bit clut addresses only 3 bits plus a 0 in the msb are used to generate a 4bit clut. pixel pair multiple pixel pairs 0 1 3bit clut 3bit clut 76 0 15 14 8 7 0 note: n = 0 means aduplicate this pixel to the end of the lineo. n = 1 is forbidden. 4 1 32 3bit clut 0 3bit clut 12 11 10 n = number of identical pixel pairs (8 bits) first pixel first pixel second pixel second pixel figure 64. runlength format in 3 bits/pixel if the number of pixel pairs indicated is greater than the number of remaining pixels in the line, then only the number of pixels necessary to complete the line is displayed.
the mosaic technique consists of changing the resolution of the screen by duplicating pixels by a mosaic factor, n. the mosaic file is then effectively compressed by the factor n. the vdsc automati- cally duplicates the pixels. the mosaic factor is indicated in the ddr1 and ddr2 register. table 63. mosaic factor of display 1 mf1 mf2 mosaic factor 0 0 2 0 1 4 1 0 8 1 1 16 note: bits indicated in ddr1 register. table 64. mosaic factor of display 2 mf 1 mf 2 mosaic factor 0 0 2 0 1 4 1 0 8 1 1 16 note: bits indicated in ddr2 register. the mosaic file works at the byte level. in 4 bits/pixel mode, the pixels are duplicated by groups of two.
MCD212 64 motorola

the video channels 1 and 2 are enabled by the debit in the dcr1 register. the video channels can be in different modes (see tables 65 and 66). table 65. output modes of channel 1 de cm 1 bits/pixel frequency resolution 1 1 4 clk/2 double note: bits indicated in dcr1 register. table 66. output modes of channel 2 de cm 2 bits/pixel frequency resolution 1 1 4 clk/2 double note: bits indicated in dcr1 register.
MCD212 71 motorola
to decode the pixel streams entering via channel 1 and channel 2, several decoders are available: one delta yuv decoder per channel, one color look up table (clut) to be shared by both channels, and direct rgb to be generated via both channels. the decoded pixel streams represent the two graphics planes: a and b. the cursor and backdrop are programmed via channel 1. yuv stands for luminance (y) and color difference (u and v). the u and v components are horizon- tally subsampled by a factor of two and transmitted alternatively every other pixel. the missing u and v components are interpolated using linear interpolation. the human eye is much less sensitive to color variation than variations in luminance, therefore any error due to interpolation will not be de- tected. the last missing u or v component of a line is found by repeating the last u or v component. the y component ranges from 0 to 255. the u and v components are signed but are given an offset of 128 to make them positive. the u and v components then range from 1 to 255. the expected ranges for r, g, and b are from 0 to 255. to avoid wraparound for values outside this range, output limiters are implemented. the absolute y, u, and v components are decoded to r, g, and b using the following equations: r = lim[ trunc{ ( y*256 + 351*(v 128) ) / 256 } ] g = lim[ trunc{ ( y*256)(86*(u 128) + 179*(v 128)) ) / 256 } ] b = lim[ trunc{ ( y*256 + 444*(u 128) ) / 256 } ] trunc{x} = greatest integer less than or equal to x lim[x] = 0 if x < 0 = 255 if x > 255 = x else delta yuv (dyuv) coding is particularly useful for the reproduction of high quality natural images. these images typically have a high degree of correlation between adjacent pixels. this correlation is used in delta yuv decoding by only coding the difference between adjacent pixels rather than their absolute value; this is the delta. this difference is coded in 4 bits, using a nonuniform 16level fixed quantizer. the vdsc executes the opposite operation, using the values in table 71.
MCD212 72 motorola table 71. dequantizer input output 0 0 1 1 2 4 3 9 4 16 5 27 6 44 7 79 8 128 9 177 10 212 11 229 12 240 13 247 14 252 15 255 the output of the dequantizer is added to the previous absolute value to obtain a new absolute value. the operation mentioned above applies for y, u, and v. decoding delta yuv comprises dyuv to yuv decoding and yuv to rgb decoding (matrixing). (for an explanation of delta yuv encoding, see appendix a.) delta decoding is initialized before the beginning of each display line by using programmable absolute start values for y, u, and v. these initial values for each line are loaded via the display control pro- gram. (see section 5.4.5.8.) since the human eye is less sensitive to variations in color than to changes in intensity, the color data is subsampled by a factor of two. this means that for each pixel there is a y value, but a u and v value for every other pixel. this allows for a certain amount of data compression with no perceived loss of image quality. the data is stored as the yuv for the first pixel and then the y data for the second pixel and the uv data for the third pixel. the u and v data for the second pixel is interpolated from the first and third. the data structure of the input and output of the dyuv decoder is given in figure 71. all calculations are performed using 8 bits, however only the most significant 7 bits of r, g, and b are given as output. d u i 15 43 0 12 11 87 d y i d v i d y i + 1 where i = pixel location figure 71. data structure of dyuv decoder input and output pixelpair dyuv decoding of coded pixeldata entering via channel 1 results in plane a and dyuv decoding of coded pixeldata entering via channel 2 results in plane b.
MCD212 73 motorola
color look up table (clut) decoding is a method of compressing display files. instead of using 24 bits of storage for each pixel, a table of colors is set up. then, the pixel data that is stored in memory is not the actual color values, but rather a pointer to a specific color in the look up table. the vdsc supports clut8 (256 colors), clut7 (128 colors), clut7+7 (2 x 128 colors), clut4 (16 colors), and clut3 (8 colors e used for runlength files). pixeldecoding via a clut is useful for applications in which a limited number of different colors is required (e.g., computer graphics and bit mapped text). the clut technique allows storing a maximum of 256 different colors in rgb, where each component has 6bit accuracy (rgb666). this gives a total of 2**18 (262144) possible colors. to comply with rgb777, one lsb of 0 is added. the clut is divided into four banks (banks 0 to 3), see figure 72, with each bank having 64 entries. the colors for the clut are loaded via the clut color registers (h80 hbf) after the appropriate bank has been selected via the clut bank register (hc3). after the colors have been stored, using the control mechanism, the required color can be obtained by addressing it. write (loading) read (decoding) ch#1 ch#2 bs 11 10 01 00 clut bank 3 63 0 clut bank 2 clut bank 1 clut bank 0 63 0 63 0 63 0 clut8 clut7 clut4 255 127 0 0 0 channel 1 plane a channel 2 plane b or channel 1 plane a channel 1 plane a 15 plane a/ch#2 15 plane a/ch#1 0 where bs = bank select (set in clut bank register hc3). 0 127 figure 72. clut organization controldata entered via channel 1 can load banks 0 to 3. controldata entered via channel 2 can load banks 2 and 3. the address is always in the range 0 63: clut 0 63. to be able to address all 256 entries, a clut bank selection is used. this clut bank selection is independent for both channels; so it is possible to simultaneously (i.e., in the same line) load colors to banks 0 and 1 via channel 1 and to load colors to banks 2 and 3 via channel 2. it is not possible to simultaneously load colors to banks 2 and 3 via both channels. pixeldata entering via channel 1 can address all banks. pixeldata entering via channel 2 can ad- dress banks 2 and 3 only. depending on the number of bits that can be used to address colors, differ- ent coding methods are distinguished: clut8 (256 colors), clut7 (128 colors), clut7+7 (2 x 128 colors), clut4 (16 colors). see figure 73 for the pixel representation. clut7+7 means that 7 ad- dress bits are available to address either banks 0 and 1 or banks 2 and 3, depending on what banks are selected. clut8 and clut7+7 are not available for channel 2. when channel 1 uses clut8 or clut7+7, channel 2 has no clut mode.
MCD212 74 motorola clut8 clut7 or clut7+7 clut4 76543210 x6543210 3 2 1 0xxxx msb lsb msb lsb lsb msb figure 73. data structure of input clut pixel clut4 can only be used in double resolution mode (768 pixels/line).
direct rgb555 (r, g, and b in 5 bits each) is intended mainly for computer graphic images. it passes the pixel data of both channels directly to plane b. to comply with rgb777, two lsbs of 0 are added. to control rgb555 pixel transparency, a transparency bit (t) is used. figure 74 shows the data struc- ture of an rgb555 pixel. input output 15 tr4r3r2r1r0 g0 g1 g2 g3 g4 b0 b1 b2 b3 b4 r4 r3 r2 r1 r0 0 0 0 0 0 0 00 0 g0 g1 g2 g3 g4 b0 b1 b2 b3 b4 msb lsb 0 figure 74. data structure of rgb555 input and output pixel
MCD212 75 motorola
the available display modes for planes a and b are not identical, see tables 72 and 73. not every combination of display modes of plane a and plane b is possible. the combination of coding methods is restricted according to table 74. table 72. display modes for plane a channel coding method cm1 resolution ch1 off x x ch1 clut8 0 normal ch1 clut7+7 0 normal ch1 clut7 0 normal ch1 clut4 1 double ch1 dyuv 0 normal table 73. display modes for plane b channel coding method cm1 resolution ch2 off x x ch2 clut7 0 normal ch2 clut4 1 double ch2 dyuv 0 normal ch1 + 2 rgb555 0 normal table 74. possible combinations of display modes plane a plane b off clut8 clut7+7 clut7 clut4 dyuv off y y y y y y clut7 y n n y y y clut4 y n n y y y dyuv y y y y y y rgb555 y n n n n n y = possible combination n = not possible
MCD212 76 motorola
the backdrop plane can have 16 different colors, see table 75. this bd plane is positioned behind the cursor and planes a and b. the color is programmed by writing via ch1 to register hd8. the possible colors are listed in table 75 along with the complimentary colors which can be used for the cursor. table 75. possible cursor and background colors cursor background y r g b color complementary color y r g b 0 0 0 0 black grey 0 1 1 1 0 0 0 1 hb blue hb yellow 0 1 1 0 0 0 1 0 hb green hb magenta 0 1 0 1 0 0 1 1 hb cyan hb red 0 1 0 0 0 1 0 0 hb red hb cyan 0 0 1 1 0 1 0 1 hb magenta hb green 0 0 1 0 0 1 1 0 hb yellow hb blue 0 0 0 1 0 1 1 1 grey black 0 0 0 0 1 0 0 0 black white 1 1 1 1 1 0 0 1 blue yellow 1 1 1 0 1 0 1 0 green magenta 1 1 0 1 1 0 1 1 cyan red 1 1 0 0 1 1 0 0 red cyan 1 0 1 1 1 1 0 1 magenta green 1 0 1 0 1 1 1 0 yellow blue 1 0 0 1 1 1 1 1 white black 1 0 0 0 note: hb = half brightness. full brightness = level 230, half = level 122, black = level 16.
the cursor is shown in the cursor plane. the dimension of the cursor plane is 16 x 16 pixels. a 1 in the cursor plane activates the cursor color for that pixel, while a 0 sets it to transparency. the resolu- tion of the cursor can be switched between normal resolution and double resolution. the cursor has one color. the cursor plane can be enabled or disabled. the cursor color is set by programming the cursor control register via ch#1 at location hce. along with setting the color, the cursor enable, the on/off period, and cursor resolution can be programmed via this same register. the cursor can be set to blink with programmable on and off periods. both periods can be specified by three bits. the on/off periods equal multiples of 12 times the tv field period (200 ms in 60 hz system; 240 ms in 50 hz system). if on and off periods are both set to 0, then the cursor is on indefinitely. the blink type may be aon/offo or anormal color/complementary coloro. the cursor position is related to the position of the upperleft pixel in the cursor plane and is pro- grammed via ch#1 in the cursor position register at location hcd. the xposition of this pixel is speci- fied by the number of double resolution pixels between this pixel and the left border of the full screen display. the yposition is specified by the number of lines between this pixel and the upper part of the full screen display. cursor control and position can be programmed during horizontal and/or vertical retrace periods. the cursor pattern is programmed via ch#1 at location hcf.
MCD212 81 motorola
the realtime decoder provides four planes, represented in rgb components. these planes are: ? cursor ? image plane a ? image plane b ? backdrop the two image planes can originate from four types of coding: ? off ? direct rgb555 ? clut ? dyuv here off means a black image (level 16, where 235 is the nominal peak white level). the cursor and backdrop each consist of one color, both of which are programmable. the visual effects combine the separate planes into one final image. the pixel hold allows plane a and/or plane b to be viewed at reduced resolution. the pixel hold func- tion operates after the pixel codes have been decoded to rgb. therefore, it can be used for all images, independent of their coding method, either by dyuv, clut, or rgb. both image planes con- tain such a pixelhold mechanism that can act independently of the other plane. every nth pixel rgb value is held for that pixel and the next n1 pixels, where n is the pixel hold factor. this produces a mosaictype effect on the image. see figure 81 for an example. before pixel hold: p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p0 p0 p0 p3 p3 p3 p6 p6 p6 p9 after pixel hold (n = 3): figure 81. pixel hold example for n = 3
MCD212 82 motorola the pixel hold function causes a amosaico or agranulationo effect in the horizontal direction (i.e., the resolution is lowered without the image size changing). the pixel hold factor is programmed via the mosaic pixel hold factor register located at location hd9 for plane a and hda for plane b. plane a is programmed via ch#1 and plane b is programmed via ch#2. the pixel hold factor can be any value from 2 to 255. the pixel hold factor is effective at both normal resolution and double resolution according to the resolution.
within the image planes, regions can be defined by means of two region flags, called flag rf0 and flag rf1. two region flags allow regions to overlap (see figure 82). these flags can be set and reset by eight region control registers. these registers are loaded during the horizontal and vertical retrace periods, using the control mechanism. rf0 rf0 rf1 figure 82. example showing overlapping and nonoverlapping regions the region control registers 0 7 can control the two region flags in two modes. in the first mode, registers 0 3 are linked to region flag 0 and registers 4 7 are linked to region flag 1 (see figure 83). in the second mode, the eight registers are explicitly linked to a region flag (see figure 84). the first mode allows the two region flags to be changed at the same position. the selection of the mode used is done in the aimage coding method registero by the nr bit. rf0: rf1: region control register horizontal position 0 x0 x1 123 x3 x2 4567 x7 x6 x5 x4 region control register horizontal position constraint: x4 < x5 < x6 < x7 constraint: x0 < x1 < x2 < x3 figure 83. implicit control of region flags (nr = 1) region control register 0123 4 56 7 x0 x1 x3 x2 x7 x6 x5 x4 constraint: x0 < x1 < x2 < x3 < x4 < x5 < x6 < x7 horizontal position region flag rf0/ rf1 rf0/ rf1 rf0/ rf1 rf0/ rf1 rf0/ rf1 rf0/ rf1 rf0/ rf1 rf0/ rf1 figure 84. explicit control of region flags (nr = 0)
MCD212 83 motorola the region control registers are examined on their specified horizontal position sequentially. depend- ing on the mode, this sequence ranges from 0 to 7 or from 0 to 3 and from 4 to 7. when a match between the specified horizontal position and the actual horizontal pixel count is found, the corre- sponding command is executed. this command can set/reset the corresponding or specified region flag, change one of the two weight factors, or end the region control for the line (no further registers are examined). so for all registers to be noticed, the position sequence stored in the region control registers has to be ascending (see figures 83 and 84). the horizontal position is specified with respect to the double rate clock (maximally 768 pixels per line). the region flags are automatically reset before the start of each line. transparency of planes can be obtained by: ? disabling ? regions ? color key ? transparency bit the image planes (a/b) and the cursor can be made transparent by disabling them. parts of both image planes can be made transparent depending on the state of one of the two region flags. for both image planes a color key is available for clut decoded images. the state of the color key is determined on a pixel basis. every clut decoded pixel is compared to an in rgb666 specified color; the socalled transparent color. if all bits match or if the corresponding mask bit is true, the color key is true. a transparency bit is available from every direct rgb555 coded pixel.
the four planes must be combined into one image. this is achieved by overlay and mixing. overlay means that only one plane at a time is shown. this is done by giving the planes an order and by using transparency, a plane can only be seen if it is not transparent and all higher order planes are transpar- ent. the order is from high to low cursor, plane a/plane b, backdrop. the order of a and b can be selected a in front of b or b in front of a (see figure 85). background/external video graphics plane b cursor plane graphics plane a figure 85. plane order it is also possible to overlay external video as an alternative for backdrop. this is done by using an external switch operated by the vdsc pin vsd or vsa . the vsd signal is synchronous to the digital output, whereas vsa is delayed one clk2 clock cycle to counteract for a delay caused by a clocked dac. vsd and vsa are active if enabled by the evbit of the aimage coding method registero and when the backdrop is shown.
MCD212 84 motorola mixing is applied to image planes a and b. they are weighted and added (see figure 86). the weighting and adding is done preserving the black level (level 16): ab = lim[ (a ) 16) * weight_a/64 + (b) 16) * weight_b/64 + 16 ] when the result exceeds level 255, the result is fixed at 255. when the result is less than level 0, the result is fixed at 0. planes a and b are made transparent for overlay by making them black. + plane a black (16) mux a x bl_a weight_a (0 63) plane b black (16) bl_b mux x b mux mux dac cur cursor backdrop weight_b (0 63) ab (0 255) vdsc vsd vsa bd external video analog switch figure 86. overlay and mixing e one color component weight factors are programmed via the weight registers. the weight factors can be dynamically changed by the region control registers at the position they indicate. backdrop and cursor can be overlaid on the combined planes a and b. during horizontal and vertical blanking of the video a constant level is set on each component. for 50 hz display this level is 16 and for 60 hz display 0.
MCD212 91 motorola
this section describes the internal registers of the vdsc. below is a chart that describes the registers that affect video plane 1 and plane 2. table 91 shows the various registers and which bits in those registers can be read or written. table 91. register summary channel 1 csr1r status register 1 read h4ffff1 csr1w control register 1 write h4ffff0 dcr1 display command register 1 write h4ffff2 vsr1 video start register 1 write h4ffff4 ddr1 display decoder register 1 write h4ffff8 dcp1 dca pointer 1 write h4ffffa channel 2 csr2r status register 2 read h4fffe1 csr2w control register 2 write h4fffe0 dcr2 display command register 2 write h4fffe2 vsr2 video start register 2 write h4fffe4 ddr2 display decoder register 2 write h4fffe8 dcp2 dca pointer 2 write h4fffea
MCD212 92 motorola
table 92. register bitmap name 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 csr1r x x x x x x x da x pa x x x x x csr2r x x x x x x x x x x x x it1 it2 be csr1w di1 x x x x dd1 dd2 x x td x dd x st be csr2w di2 x x x x x x x x x x x x x x dcr1 de cf fd sm cm1 0 ic1 dc1 x x * * * * * dcr2 x x x x cm2 0 ic2 dc2 x x * * * * * ddr1 x x x x mf1 mf2 ft1 ft2 x x * * * * * ddr2 x x x x mf1 mf2 ft1 ft2 x x * * * * * vsr1 * * * * * * * * * * * * * * * vsr2 * * * * * * * * * * * * * * * dcp1 * * * * * * * * * * * * * x x dcp2 * * * * * * * * * * * * * x x these registers control the system related functions of the vdsc. they are reset to 0 during the initial- ization sequence. this is the default configuration. csr1w (write, 4ffff0) table 93. control register 1 e write, 4ffff0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 di1 e e e e e dd1 dd2 e e td e dd e st be di1 (disable interrupts) when set to 1, disables the propagation to the int pin for the it1 bit (see status register). this bit does not disable the it1 bit. dd1 dd2 (dtack delay) active when dd = 1. these two bits permit four different delays for the dtack generation when the cpu accesses the system rom. table 94. dtack delay dd dd1 dd2 clk cycles 0 x x 11 12 1 0 0 3 4 1 0 1 5 6 1 1 0 7 8 1 1 1 9 10 td (type of dram) to be 0 for 256k x 4 and 256k x 16 devices and 1 for 1m x 4 devices. dd dtack delay for the rom. see dd1 dd2.
MCD212 93 motorola st (standard bit) when set to 1, this bit permits a resolution modification in order to display images which don't have the resolution indicated by the dcr1 register. when set to 1, the effect is: vertical resolution: in 50 hz mode (fd = 0), the resolution is shortened by 20 lines at the top and 20 lines at the bottom. images created in a 60 hz system are then directly usable in a 50 hz system. horizontal resolution: ? in 28 mhz, the bit map file is 384 pixels wide instead of 360 pixels. the horizontal resolution is unchanged, but it is possible to display bitmap, runlength or mosaic coded images created with a 30 mhz or 30.2097 mhz system. ? in 30 mhz or 30.2097 mhz, the horizontal resolution is decreased from 384 pixels to 360 pixels, 12 pixels are masked on either side of the screen. be (bus error) when set to 1, this bit activates the watchdog timer and enables the berr generation. csr2w (write, 4fffe0) table 95. control register 2 e write, 4fffe0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 di2 e e e e e e e e e e e e e e e di2 (disable interrupts) when set to 1, disables the propagation to the int pin for the it2 bit (see status register). this bit does not disable the it2 bit.
these registers are read as a byte and contain the status of the vdsc. csr1r (read, 4ffff1) table 96. status register csr1r e read, 4ffff1 7 6 5 4 3 2 1 0 da e pa e e e e e da (display active) this bit is the vertical display active information. when high, it indicates that the display controller is fetching information from the video memory. it does not change on each horizontal retrace. pa (parity) this bit indicates the frame parity when the scan mode is in interlace or interlace field repeat mode. it is 1 for the odd frame and 0 for the even frame.
MCD212 94 motorola csr2r (read, 4fffe1) table 97. status register csr2r e read, 4fffe1 7 6 5 4 3 2 1 0 e e e e e it1 it2 be it1 (interrupt1) this bit can be set to 1 by the ica/dca mechanism to generate an interrupt to the cpu. at the same time, the int pin goes low, if the di1 bit is set to 1 in the csr1 register. the it1 bit and the int pin will be reset automatically when the cpu reads the status register. it2 (interrupt2) this bit can be set to 1 by the ica/dca mechanism to generate an interrupt to the cpu. at the same time, the int pin goes low, if the di2 bit is set to 1 in the csr2 register. the it2 bit and the int pin will be reset automatically when the cpu reads the status register. be (bus error) this bit is set to 1 when a bus error condition has been gener- ated by the watchdog timer. this bit is automatically reset after a status read operation.

the display command registers group control bits for the display and six msbs of the video start address. the eight msbs are reset to 0 after the reset sequence. dcr1 (write, 4ffff2) table 98. display command register dcr1 e write, 4ffff2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 de cf fd sm cm1 0 ic1 dc1 e e a21 a20 a19 a18 a17 a16 de (display enable) enables display access to dram and enables synchro- nization outputs when set to 1. cf (crystal frequency) must be programmed as a function of the crystal oscilla- tor frequency as follows. table 99. crystal frequency cf frequency in mhz 0 28 1 30, 30.2097 fd (frame duration) when reset to 0, a 50 hz scan is generated. when set to 1, a 60 hz scan frequency is generated. sm (scan mode) this bit is used to select the scan mode.
MCD212 95 motorola table 910. scan mode sm scan mode 0 noninterlace 1 interlace cm1 (color mode of channel 1) this bit controls the pixel output mode. table 911. channel 1 color mode cm1 bits/pixel pixel frequency 1 4 clk/2 ic1 dc1 (ica1 dca1) these two bits enable the ica1 and dca1 mechanisms. table 912. ica1/dca1 enable ic1 dc1 ica1 dca1 0 x no no 1 0 yes no 1 1 yes yes a21 a16 most significant bits of the video start address, acting in conjunction with the vsr. dcr2 (write, 4fffe2) table 913. display command register dcr2 e write, 4fffe2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e e e e cm2 0 ic2 dc2 e e a21 a20 a19 a18 a17 a16 cm2 (color mode of channel 2) this bit controls the pixel output mode. table 914. channel 2 color mode cm2 bits/pixel pixel frequency 0 8 clk/4 1 4 clk/2 ic2 dc2 (ica2 dca2) these two bits enable the ica2 and dca2 mechanisms. table 915. ica1/dca1 enable ic2 dc2 ica2 dca2 0 x no no 1 0 yes no 1 1 yes yes a21 a16 most significant bits of the video start address, acting in conjunction with the vsr.
MCD212 96 motorola
these registers contain control bits for the display, files to be displayed, and the six msb bits of the dca pointer. all the bits, except the six lsbs, are reset to 0 after the reset sequence. ddr1 (write, 4ffff8) table 916. display decoder register 1 e write, 4ffff8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e e e e mf1 mf2 ft1 ft2 e e a21 a20 a19 a18 a17 a16 mf1 mf2 (mosaic factor) set the horizontal mosaic factor: table 917. channel 1 mosiac factor mf1 mf2 mosaic factor 0 0 2 0 1 4 1 0 8 1 1 16 ft1 ft2 (file type) indicate the type of file to be displayed: table 918. channel 1 display file type ft1 ft2 display file type 0 x bitmap 1 0 runlength 1 1 mosaic a21 a16 most significant bits of the dca1 pointer. ddr2 (write,4fffe8) table 919. display decoder register 2 e write, 4fffe8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e e e e mf1 mf2 ft1 ft2 e e a21 a20 a19 a18 a17 a16
MCD212 97 motorola mf1 mf2 (mosaic factor) set the horizontal mosaic factor : table 920. channel 2 mosiac factor mf1 mf2 mosaic factor 0 0 2 0 1 4 1 0 8 1 1 16 ft1 ft2 (file type) indicate the type of file to be displayed: table 921. channel 2 display file type ft1 ft2 display file type 0 x bitmap 1 0 runlength 1 1 mosaic a21 a16 most significant bits of the dca2 pointer.

these 16bit registers plus some bits in dcr1[5:0]/dcr2[5:0] give a 22bit video start register ad- dress that points to the first byte of the display area that can be located anywhere in the dram. horizontal or vertical rolling subscreens can be implemented anytime by the areload vsr and stopo ica or dca instruction. the vsr is also used as an ica pointer with the areload vsro instruction, which allows indirect addressing inside ica. vsr1 (write, 4ffff4) table 922. video start register 1 e write, 4ffff4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 vsr2 (write, 4fffe4) table 923. video start register 2 e write, 4fffe4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
MCD212 98 motorola

these 14bit registers plus some bits in ddr1[5:0]/ddr2[5:0] give a 20bit dca pointer that points to the first longword of the dca. the dca can thus be located anywhere in the dram and the dca pointer is always longword aligned. dcp1 (write, 4ffffa) table 924. display control pointer 1 e write, 4ffffa 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 e e dcp2 (write, 4fffea) table 925. display control pointer 2 e write, 4fffea 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 e e
MCD212 101 motorola

pin function pin function pin function pin function pin function 1 v ss 33 d14 65 a1 97 md4 129 b3 2 rstout 34 d15 66 v ss 98 md3 130 v dd 3 v dd 35 dtack 67 a23 99 dtacksel 131 b4 4 cs 36 v dd 68 ma9 100 v dd 132 b5 5 gnd 37 r/w 69 ma8 101 md2 133 b6 6 rstin 38 lds 70 ma7 102 md1 134 b7 7 halt 39 uds 71 ma6 103 md0 135 g0 8 int 40 v ss 72 ma5 104 v ss 136 v ss 9 v dd 41 v dd 73 ma4 105 ras 137 g1 10 csrom 42 a22 74 md15 106 m/s 138 g2 11 tdo 43 a21 75 md14 107 cas1 139 v ss 12 tdi 44 a20 76 md13 108 oe 140 v dd 13 csio 45 a19 77 v ss 109 cas2 141 g3 14 berr 46 a18 78 md12 110 gnd 142 g4 15 d0 47 a17 79 md11 111 v ss 143 g5 16 d1 48 a16 80 v dd 112 v dd 144 g6 17 v ss 49 a15 81 md10 113 tck 145 tms 18 d2 50 a14 82 ma3 114 v ss 146 g7 19 d3 51 v ss 83 ma2 115 clk 147 r0 20 d4 52 a13 84 ma1 116 clk2 148 v dd 21 d5 53 a12 85 as 117 clk2 149 r1 22 d6 54 a11 86 ma0 118 v ss 150 r2 23 d7 55 a10 87 lwr 119 v dd 151 r3 24 v ss 56 a9 88 uwr 120 nc 152 r4 25 d8 57 a8 89 v ss 121 vsync 153 v ss 26 d9 58 a7 90 md9 122 hsync 154 r5 27 v dd 59 a6 91 md8 123 blank 155 r6 28 d10 60 a5 92 md7 124 v dd 156 v ss 29 d11 61 v dd 93 md6 125 b0 157 r7 30 d12 62 a4 94 md5 126 b1 158 vsd 31 d13 63 a3 95 v dd 127 b2 159 vsa 32 v ss 64 a2 96 v ss 128 v ss 160 csync
MCD212 102 motorola

??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ??????????????????????????? ?? ?? ? ? ? ? ?? ?? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ? ? ? ? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ? ? ? ? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ? ? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ? ? ? ? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ? ? ? ? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ?? ?? ? ? ? ? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? md10 rstout v dd cs gnd rstin halt int v dd csrom csio berr d0 d1 v ss d2 d3 d4 d5 d6 d7 v ss d8 d9 v dd d10 d11 d12 d13 v ss d14 d15 dtack v dd r/w lds uds v ss ma3 ma2 ma1 ma0 lwr uwr v ss md9 md8 md7 md6 md5 v dd v ss md4 md3 dtacksel* v dd md2 md1 md0 v ss ras m/s cas1 oe cas2 gnd v ss v dd tck* v ss clk clk2 clk2 v ss v dd nc 120 v ss v ss a22 a21 a20 a19 v ss a18 v dd a17 a16 a15 a14 v dd a13 a12 v ss a11 a10 a9 a8 a7 a6 a5 v dd a4 a3 a2 a1 md15 md14 md13 md12 md11 csync vsa vsd r7 r6 r4 r3 r2 r1 v ss v dd r0 g7 g6 g5 v dd g4 g3 blank g2 g1 g0 v dd v ss b7 b6 b5 b4 v dd b3 hsync b2 b1 b0 vsync 40 41 1 160 121 81 80 v ss r5 v ss v ss ma9 ma8 ma6 ma5 ma4 ma7 tms* as * a23* tdo* tdi* MCD212 160 qfp top view note: pin differences between the mcd211 and MCD212 are denoted with *.
MCD212 111 motorola

parameter symbol min max unit supply voltage v dd 0.5 + 7.0 v input voltage v i 1.5 v dd + 1.5 v output voltage v o 0.5 v dd + 0.5 v output current i o e 25 ma power dissipation p d e 1200 mw operating temperature t opr 0 + 70 c storage temperature t stg 65 + 150 c test conditions: v ss = 0 v, t a = 70 c.
MCD212 112 motorola
v dd = 5 v 10%, v ss = 0 v, t a = 0 70 c parameter symbol conditions min max unit operating supply current i dd v i = v dd or v ss clk at 30.3 mhz e 220 ma input voltage (cmos input) v ih v il 0.7 v dd e e 0.3 v dd v input voltage (ttl input) v ih v il v dd = 4.5 v v dd = 5.5 v v dd = 5.5 v 2.0 2.2 e e e 0.8 v cmos schmitt trigger input voltage v t+ v t v dd = 4.5 v 5.5 v 2.0 1.5 3.4 2.6 v hysteresis e schmitt cmos v dd = 4.5 v 5.5 v 0.11 v dd 0.18 v dd v input leakage current i li v i = v dd or v ss * 1 1 m a output voltage (4 ma output type) v oh v ol i o = 4 ma, v dd = 4.5 v i o = 4 ma, v dd = 4.5 v 3.7 e e 0.4 v output voltage (8 ma output type) v oh v ol i o = 8 ma, v dd = 4.5 v i o = 8 ma, v dd = 4.5 v 3.7 e e 0.4 v output leakage current i oz 5 5 m a input capacitance c in v dd = v i = 0 v e 10 pf output capacitance c out e 12.5 pf * leakage current is in addition to input current generated in pullup resistors when the input is held low. (tdi, tms, tck have 100 k w pullups).
conditions: v dd = 5 v ( 10%) t a = 0 70 c v ol = 0.8 v, v oh = 2.2 v c load (dtack , int ) =130 pf , r load (dtack , int ) = 1 k w c load (d0 d15, rstout , halt , berr ) = 130 pf c load (ma0 ma9, ras , cas1 , cas2 ) = 100 pf c load (csio , csrom , md0 md15) = 50 pf c load (clk2, clk2 , hsync , vsync , csync , blank , uwr , lwr ro r7, g0 g7, b0 b7, vsa , vsd ) = 75 pf timing no. parameter min max unit note 1 clk period 32 e ns 2 clk high time 13 e ns 3 clk low time 13 e ns 4 clk high to clk2 0 25 ns 5 clk high to clk2 0 25 ns 6 clk2 low to clk2 high 5 6 ns 7 clk2 low to r0 r7, g0 g7, b0 b7, vsync , hsync , csync , blank 5 4 26 ns 8 clk2 high to r0 r7, g0 g7, b0 b7 5 27 ns 9 clk2 high to vsync , hsync , csync , blank 5 26 ns 10 clk2 low to vsd , vsa 5 25 ns
MCD212 113 motorola timing (continued) no. note unit max min parameter 11 clk2 high to vsd , vsa 5 25 ns 12 oe low to r0 r7, g0 g7, b0 b7 threestate 5 23 ns 13 oe high to r0 r7, g0 g7, b0 b7 active 5 23 ns 14 address to u/lds low (read) 0 e ns 15 u/lds high to address invalid (read) 5 e ns 16 u/lds low to r/w high (read) e 25 ns 17 u/lds low to cs low (read) e 25 ns 18 u/lds high to r/w hold (read) 5 e ns 19 u/lds low to dtack low (dram read) 235 320 ns 1 20 u/lds low to dtack low (register read) 75 135 ns 1 21 21a u/lds high to dtack high (threestate) dtack active high time 0 tbd 43 tbd ns 22 22a dtack low to data valid (read) pin 99 low dtack low to data valid (read) pin 99 high e e 40 32 ns 2 23 23a u/lds high to data invalid (read) u/lds high to data threestate (read) 0 e e 40 ns 24 address to u/lds low (write) 0 e ns 25 u/lds high to address invalid (write) 0 e ns 26 26a u/lds low to r/w low (write) u/lds low to cs low (write) e e 25 25 ns 27 u/lds high to r/w high (write) 0 e ns 28 data valid to u/lds low (write) 0 e ns 29 u/lds high to data invalid (write) 0 e ns 30 30a u/lds low to dtack low (dram write) u/lds low to dtack low (register write) 45 75 105 135 ns 1 1 31 u/lds high to dtack threestate (write) 0 43 ns 32 u/lds low to csrom or csio low e 17 ns 33 u/lds high to csrom or csio high e 13 ns 34 u/lds low to dtack for rom low 11 + d 43 + d ns 3 35 u/lds high to dtack for rom high 0 50 ns 36 ras high pulse duration (t rp ) 65 e ns 37 ras low pulse duration (t ras ) 90 e ns 38 cas high pulse duration (t cp ) 20 e ns 39 cas low pulse duration (t cas ) 30 e ns 40 cas high to ras low delay (t crp ) 50 e ns 41 ras low to cas low delay (t rcd ) 60 e ns notes: 1. these figures are valid for freerun. if video is enabled the max delay increases with a maximum of 16 clk periods. 2. this timing is switchable using pin 99 and is valid for video channel and dram accesses pin 99 low 40 ns (max) advance (68000/070/340/34116) pin 99 high 32 ns (max) advance (68340/34125) timing of dtack for rom accesses is unchanged. 3. the delay d is the delay mentioned in the delay times table and depends on the clk frequency and the programmed value dd, dd1, dd2.
MCD212 114 motorola timing (continued) no. note unit max min parameter 42 cas low to ras high delay (t rsh ) 25 e ns 42 cas low to ras high delay (t rsh ) 25 e ns 43 ras low to cas high delay (t csh ) 95 e ns 43 ras low to cas high delay (t csh ) 95 e ns 44 ras low to column address delay (t rad ) 30 e ns 45 row address setup time (t asr ) 15 e ns 46 row address hold time (t rah ) 30 e ns 47 column address setup time (t asc ) 20 e ns 48 column address hold time (t cah ) 25 e ns 49 data setup time to cas low (t ds ) 100 e ns 50 data hold time to cas low (t dh ) 40 e ns 51 read setup time to cas low (t rcs ) 75 e ns 52 read hold time to cas high (t rch ) 35 e ns 53 write setup time to cas low (t wcs ) 70 e ns 54 write hold time to cas low (t wch ) 75 e ns 55 ras low to data valid (t rac ) e 90 ns 56 cas low to data valid (t cac ) e 21 ns 57 column address to data valid (t aa ) ras cycle time cas cycle time 150 50 45 45 ns 58 cas high to data invalid (t off ) 0 e ns 59 refresh period 1m (t rfsh ) 9 e ns 60 refresh period 256k x 4 and 256k x 16 (t rfsh ) 5 e ns 61 rstin low to rstout /halt low 75 140 ns 62 rstin low time 2 e ns 63 rstin high to rstout high 150 160 ns 64 rstout high to halt high 59 64 ns 65 u/lds high to berr high tbd tbd ns 66 dtacksel to dtack delay active tbd tbd ns 67 dtack low to data invalid (write) tbd tbd ns delay times dd0 dd1 dd2 clk = 28 mhz clk = 30 mhz clk = 30.2097 mhz ui dd0 dd1 dd2 min max min max min max units 0 x x 400 470 375 445 370 440 ns 1 0 0 115 185 110 175 105 170 ns 1 0 1 185 260 175 240 170 235 ns 1 1 0 260 330 240 310 235 305 ns 1 1 1 330 400 310 375 305 370 ns
MCD212 115 motorola clk clk2 clk2 1 3 2 4 6 5 figure 111. clock timing clk2 7 14 15 8 9 10 clk2 oe video* vsd vsa * video: r0 r7, g0 g7, b0 b7, vsync , hsync , blank 11 figure 112. video timing
MCD212 116 motorola 14 15 16 18 17 19 20 21 22 23 a1 a22 r/w cs u/lds dtack d0 d15 figure 113. cpu read cycle timing 25 26 27 26a 30 31 29 24 28 a1 a22 r/w cs d0 d15 u/lds dtack figure 114. cpu write cycle timing 32 33 35 34 u/lds csrom csio dtack for rom figure 115. system timing
MCD212 117 motorola row col row col col col col ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 36 37 41 42 44 40 43 38 39 47 48 46 45 51 53 52 54 49 50 56 58 55 57 cas1 cas2 ma0 ma9 uwr /lwr md0 md15 write md0 md15 read system ch#1/ch#2 ras figure 116. dram timing 62 rstin rstout halt 63 61 64 figure 117. reset and halt timing
MCD212 118 motorola
MCD212 121 motorola
the vdsc is a surface mounting component and is housed in a 160pin plastic quad flat package (qfp).
MCD212 122 motorola min min max max millimeters inches dim a b c d e f g h j k l m n p q r s t u v w x y z 27.90 27.90 3.35 0.22 3.20 0.22 0.25 0.11 0.70 5 0.11 0 0.13 31.00 0.13 0 31.00 0.40 28.10 28.10 3.85 0.38 3.50 0.33 0.35 0.23 0.90 16 0.19 7 0.30 31.40 e e 31.40 e 1.098 1.098 0.132 0.009 0.126 0.009 0.010 0.004 0.028 5 0.004 0 0.005 1.220 0.005 0 1.220 0.016 1.106 1.106 0.152 0.015 0.138 0.013 0.012 0.009 0.035 16 0.007 7 0.012 1.236 e e 1.236 e 0.650 bsc 25.35 ref 0.325 bsc 1.60 ref 1.33 ref 1.33 ref 0.0256 bsc 0.998 ref 0.0130 bsc 0.063 ref 0.052 ref 0.052 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, b- and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. p detail a -a,b,d- k -h- datum plane x q r t u w detail c j f base metal d n detail b view rotated 90 clockwise 0.10 (0.004) 160 40 41 80 81 120 121 1 detail c detail b l v z b -b- y -d- a s c h e -c- seating plane g m m -h- datum plane detail a l -a- c 0.20 (0.008) ab d ab 0.05 (0.002) h 0.20 (0.008) ab d 0.20 (0.008) h ab d 0.20 (0.008) c ab d 0.50 (0.008) ab m m s s s s s s s s m m 0.13 (0.005) c a b s d s m quad flat pack (qfp) case 100701
MCD212 a1 motorola

the MCD212 does not do the encoding of any image but this section is included as an informational reference to the process of image coding using the delta yuv (dyuv) process. natural images are particularly well suited to dyuv encoding since there is usually little difference in the color or intensity of adjacent pixels. this makes for a very efficient coding of an image. the process to produce a normal resolution dyuv image (384 x 240) begins with a high resolution rgb image (768 x 480). the process to change from rgb to yuv uses the equations below: y = 0.299 * r + 0.587 * g + 0.114 * b u = 0.564 * (b y) v = 0.713 * (r y) the normalized, eightbit values of the components are obtained from the following equations: |y| = 219 * y + 16 |u| = 224 * u + 128 |v| = 224 * v + 128 in order to solve aliasing problems, the image is filtered, typically with a fir filter to maintain the cor- rect phase and then is subsampled by a factor of two in both the horizontal and vertical directions for the y component. for the u and v components, the subsampling is by a factor of two in the vertical direction, but by a factor of four in the horizontal direction since the human eye is less sensitive to changes in color as opposed to changes in luminance.
the yuv components are now delta coded in the horizontal direction only. an initial 24bit absolute value of the first pixel is used as the starting value (8 bits for each component). the yuv component of each sample for the rest of the line is coded using a 16level quantizer (shown in table a1).
MCD212 a2 motorola table a1. 16bit quantization table input difference code output difference 0 0 0 1 .... 2 (254 ... 255) 1 1 3 .... 6 (250 ... 253) 2 4 7 .... 12 (244 ... 249) 3 9 13 ... 21 (235 ... 243) 4 16 22 ... 35 (221 ... 234) 5 27 36 ... 61 (195 ... 220) 6 44 62 ... 99 (157 ... 194) 7 79 100 ... 156 (100 ... 156) 8 128 157 ... 194 (62 ... 99) 9 177 195 ... 220 (36 ... 61) 10 212 221 ... 234 (22 ... 35) 11 229 235 ... 243 (13 ... 21) 12 240 244 ... 249 (7 ... 12) 13 247 250 ... 253 (3 ... 6) 14 252 254 ... 255 (1 ... 2) 15 255 example: assume that the first seven pixels of the line (expressed as rgb) are as follows: 0,0,0 16,0,0 0,128,255 128,64,68 232,240,12 0,255,0 0,0,255 converting to yuv gives: 16,128,128 20,126,135 105,203,63 88,120,156 197,29,141 144,54,35 41,240,110 then the absolute value of the first pixel (8 bits) is sent for each of the components (shown in hex): h10,h80,h80 then the delta between the first and second pixels is calculated as 4bit data from the table above (in hex): h2,hf,h3 then the delta of the y component is calculated based on the difference from the last calculated value and the desired value (the u and v are skipped): h7 next the delta for all components is calculated: hd,hd,h4 and so on for the rest of the pixels: h8 h9,h9,h8 h9 in the MCD212, the data is reconstructed as follows: the first pixel is given by the absolute value: 16,128,128
MCD212 a3 motorola the second is calculated using the output difference column from the table above: 20,127,137 then the rest are calculated in the same way: 99 90,118,153 218 139,39,25 60 therefore the data for the seven pixels would be stored on disk as follows (in hex): h10,h80,h80,hf2,h37,hdd,h48,h99,h89
MCD212 a4 motorola

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