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hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t 1st 512m ddr sdram hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 0.6/may. 02 1
rev. 0.6/may. 02 2 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t revision history 1. rev 0.2 (jul. 01) 1) preliminary i dd specification defined 2. rev 0.3 (feb. 02) 1) thz/tlz specification defined 2) idd4w specificatio n changed from 250ma to 200ma 3) tis/tih at ddr200 changed from 1.2ns to 1.1ns 3. rev 0.4 (feb. 02) 1) tck max ot ddr2666a/b, ddr2000 changed 15ns to 12ns 2) twr spec. at ddr200 changed 20ns to 15ns 3) idd0 spec. changed from 90ma to 100ma at ddr266a/b and 85ma to 95ma at ddr200 4) tqhs at ddr200 changed from 1ns to 0.75ns 4. rev 0.5 (may. 02) 1) idd spec. updated 2) input leakage current changed from +/-5ua to +/-2ua 5. rev 0.6 (may. 02) 1) idd spec.(idd2 q, idd7a) updated
description the hynix hy5du12422(l)t, hy5du12822(l)t and hy5du 121622(l)t are a 536,870,912-bit cmos double data rate(ddr) synchronous dram, ideally su ited for the main memory applications which requires large memory density and high bandwidth. the hynix 512mb ddr sdrams offer fully synchronous operations referenced to both rising and falling edges of the clock. while all addresses and control inputs are latched on the rising edges of the ck (falling edges of the /ck), data, data strobes and write data masks inputs are samp led on both risi ng and falling edg es of it. the data paths are inter- nally pipelined and 2-bit prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with sstl_2. features ?v dd , v ddq = 2.5v +/- 0.2v ? all inputs and outputs are compatible with sstl_2 interface ? fully differential clock inputs (ck, /ck) operation ? double data rate interface ? source synchronous - data transaction aligned to bidirectional data strobe (dqs) ? x16 device has two bytewide data strobes (udqs, ldqs) per each x8 i/o ? data outputs on dqs edges when read (edged dq) data inputs on dqs cent ers when write (centered dq) ? on chip dll align dq and dqs transition with ck transition ? dm mask write data-in at the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latc hed on the rising edges of the clock ? programmable /cas latency 1.5 / 2 / 2.5 supported ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? internal four bank operations with single pulsed /ras ? auto refresh and self refresh supported ? tras lock out function supported ? 8192 refresh cycles / 64ms ? jedec standard 400mil 66pin tsop-ii with 0.65mm pin pitch ? full and half strength dr iver option controlled by emrs ordering information part no. configuration power hy5du12422t-x* 128mx4 standard hy5du12422lt-x* 128mx4 low power hy5du12822t-x* 64mx8 standard hy5du12822lt-x* 64mx8 low power hy5du121622t-x* 32mx16 standard hy5du121622lt-x* 32mx16 low power hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t rev. 0.6/may. 02 3 operating frequency * x means speed grade ** jedec specification compliant grade cl2 cl2.5 remark** - k 133mhz 133mhz ddr266a - h 125mhz 133mhz ddr266b - l 100mhz 125mhz ddr200 preliminary
rev. 0.6/may. 02 4 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t pin configuration 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 nc vddq ldqs nc vdd nc ldm /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 nc vssq udqs nc vref vss udm /ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc nc vddq nc nc vdd nc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc nc vssq dqs nc vref vss dm /ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc nc vddq nc nc vdd nc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc nc vssq dqs nc vref vss dm /ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss x16 x8 x4 x4 x8 x16 400mil x 875mil 66pin tsop -ii 0.65mm pin pitch row and column address table items 128mx4 64mx8 32mx16 organization 32m x 4 x 4banks 16m x 8 x 4banks 8m x 16 x 4banks row address a0 - a12 a0 - a12 a0 - a12 column address a0-a9, a11, a12 a0-a9, a11 a0-a9 bank address ba0, ba1 ba0, ba1 ba0, ba1 auto precharge flag a10 a10 a10 refresh 8k 8k 8k
rev. 0.6/may. 02 5 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t pin description pin type description ck, /ck input clock: ck and /ck are differential clock in puts. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of /ck. output (read) data is referenced to the crossings of ck and /ck (both directions of crossing). cke input clock enable: cke high activates, and c ke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all banks idle), or active power down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit, and for output disable. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, /ck and cke are disabled during power down. input buffers, excluding cke are disabled during self refresh. cke is an sstl_2 input, but will detect an lvcmos low level after vdd is applied. /cs input chip select : enables or disables all inputs except ck, /ck, cke, dqs and dm. all com- mands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. a0 ~ a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one loca- tion out of the memory array in the respec tive bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op code during a mode register set com- mand. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). /ras, /cas, / we input command inputs: /ras, /cas and /we (along with /cs) define the command being entered. dm (ldm,udm) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. for the x16, ldm corresponds to the data on dq0-q7; udm corre- sponds to the data on dq8-q15. dqs (ldqs,udqs) i/o data strobe: output with read data, input wi th write data. edge aligned with read data, centered in write data. used to capture write data. for the x16, ldqs corresponds to the data on dq0-q7; udqs corresponds to the data on dq8-q15. dq i/o data input / output pin : data bus v dd /v ss supply power supply for internal circuits and input buffers. v ddq /v ssq supply power supply for output buffers for noise immunity. v ref supply reference voltage for inputs for sstl interface. nc nc no connection.
rev. 0.6/may. 02 6 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t command decoder clk /clk cke /cs /ras /cas /we dm address buffer a0~a12 bank control 32mx4/bank0 column decoder column address counter sense amp 2-bit prefetch unit 32mx4/bank1 32mx4/bank2 32mx4/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver dqs clk /clk ds write data register 2-bit prefetch unit ds dq [0:3] 84 4 8 clk_dll ba0, ba1 functional block diagram (128mx4) 4banks x 32mbit x 4 i/o double data rate synchronous dram
rev. 0.6/may. 02 7 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t command decoder clk /clk cke /cs /ras /cas /we dm address buffer a0~a12 bank control 16mx8/bank0 column decoder column address counter sense amp 2-bit prefetch unit 16mx8/bank1 16mx8/bank2 16mx8/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver dqs clk /clk ds write data register 2-bit prefetch unit ds dq [0:7] 16 8 8 16 clk_dll ba0,ba1 functional block diagram (64mx8) 4banks x 16mbit x 8 i/o double data rate synchronous dram
rev. 0.6/may. 02 8 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t command decoder clk /clk cke /cs /ras /cas /we ldm address buffer a0~a12 bank control 8mx16/bank0 column decoder column address counter sense amp 2-bit prefetch unit 8mx16/bank1 8mx16/bank2 8mx16/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver ldqs, udqs clk /clk ldqs udqs write data register 2-bit prefetch unit ds dq[0:15] 32 16 16 32 clk_dll ba0, ba1 udm functional block diagram (32mx16) 4banks x 8mbit x 16 i/o double data rate synchronous dram
rev. 0.6/may. 02 9 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t simplified command truth table command cken-1 cken cs ras cas we addr a10/ ap ba note extended mode register set h x llll op code 1,2 mode register set h x llll op code 1,2 device deselect hx hxxx x1 no operation l h h h bank active h x l l h h ra v 1 read h x lhlhca l v 1 read with autoprecharge h1,3 write hxlhllca l v 1 write with autoprecharge h1,4 precharge all banks hxllhlx hx1,5 precharge selected bank lv1 read burst stop h x l h h l x 1 auto refresh h h l l l h x 1 self refresh entryh l lllh x 1 exit l h hxxx 1 lhhh precharge power down mode entry h l hxxx x 1 lhhh 1 exit l h hxxx 1 lhhh 1 active power down mode entry h l hxxx x 1 lvvv 1 exit l h x 1 note : 1. ldm/udm states are don?t care. refer to below write mask truth table. 2. op code(operand code) consists of a0~a12 and ba0~ba1 used for mode register setting duing extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs command can be issued after trp period from prechagre command. 3. if a read with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+trp). 4. if a write with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+1+tdpl+trp). last data-in to prechage delay(tdpl) which is also called write recovery tim e (twr) is needed to guarantee that the last data has been completely written. 5. if a10/ap is high when precharge command being issued, ba0/ba1 are ignored and all banks are selected to be precharged. ( h=logic high level, l=logic low level, x= don?t care, v=valid data input, op code=operand code, nop=no operation )
rev. 0.6/may. 02 10 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t write mask truth table function cken-1 cken /cs, /ras, /cas, /we dm addr a10/ ap ba note data write h x x l x 1 data-in mask h x x h x 1 note : 1. write mask command masks burst write data with reference to ldqs/udqs(data strobes) and it is not related with read data. in case of x16 data i/o, ldm and udm control lower byte(dq0~7) and upper byte(dq8~15) respectively.
rev. 0.6/may. 02 11 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t operation command truth table-i current state /cs /ras /cas /we address command action idle h x x x x dsel nop or power down 3 lhhh x nop nop or power down 3 l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4 l h l l ba, ca, ap write/writeap illegal 4 l l h h ba, ra act row activation l l h l ba, ap pre/pall nop l l l h x aref/sref auto refresh or self refresh 5 l l l l opcode mrs mode register set row active h x x x x dsel nop lhhh x nop nop l h h l x bst illegal 4 l h l h ba, ca, ap read/readap begin read : optional ap 6 l h l l ba, ca, ap write/writeap begin write : optional ap 6 l l h h ba, ra act illegal 4 l l h l ba, ap pre/pall precharge 7 l l l h x aref/sref illegal 11 llllopcode mrs illegal 11 read h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst terminate burst l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap illegal l l h h ba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge l l l h x aref/sref illegal 11 llllopcode mrs illegal 11 write h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst illegal 4 l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap term burst, new write:optional ap
rev. 0.6/may. 02 12 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t operation command truth table-ii current state /cs /ras /cas /we address command action write l l h h ba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge l l l h x aref/sref illegal 11 llllopcode mrs illegal 11 read with autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall illegal 4,10 l l l h x aref/sref illegal 11 llllopcode mrs illegal 11 write autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall illegal 4,10 l l l h x aref/sref illegal 11 llllopcode mrs illegal 11 pre- charge h x x x x dsel nop-enter idle after trp l h h h x nop nop-enter idle after trp l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall nop-enter idle after trp l l l h x aref/sref illegal 11 llllopcode mrs illegal 11
rev. 0.6/may. 02 13 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t operation command truth table-iii current state /cs /ras /cas /we address command action row activating h x x x x dsel nop - enter row act after trcd l h h h x nop nop - enter row act after trcd l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 l l h h ba, ra act illegal 4,9,10 l l h l ba, ap pre/pall illegal 4,10 l l l h x aref/sref illegal 11 llllopcode mrs illegal 11 write recover- ing h x x x x dsel nop - enter row act after twr l h h h x nop nop - enter row act after twr l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal l h l l ba, ca, ap write/writeap illegal l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall illegal 4,11 l l l h x aref/sref illegal 11 llllopcode mrs illegal 11 write recover- ing with autopre- charge h x x x x dsel nop - enter precharge after tdpl l h h h x nop nop - enter precharge after tdpl l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,8,10 l h l l ba, ca, ap write/writeap illegal 4,10 l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall illegal 4,11 l l l h x aref/sref illegal 11 llllopcode mrs illegal 11 refresh- ing h x x x x dsel nop - enter idle after trc l h h h x nop nop - enter idle after trc l h h l x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11
rev. 0.6/may. 02 14 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t operation command truth table-iv note : 1. h - logic high level, l - logic low level, x - don?t care, v - valid data input, ba - bank address, ap - autoprecharge address, ca - column address, ra - row address, nop - no operation. 2. all entries assume that cke was active (high level) during the preceding clock cycle. 3. if both banks are idle and cke is inactive(low level), then in power down mode. 4. illegal to bank in specified state. function may be legal in the bank indicated by bank address(ba) depending on the state o f that bank. 5. if both banks are idle and cke is inac tive(low level), then self refresh mode. 6. illegal if trcd is not met. 7. illegal if tras is not met. 8. must satisfy bus conten tion, bus turn around, and/or write recovery requirements. 9. illegal if trrd is not met. 10. illegal for single bank, but legal for other banks in multi-bank devices. 11. illegal for all banks. current state /cs /ras /cas /we address command action write l h l l ba, ca, ap write/writeap illegal 11 l l h h ba, ra act illegal 11 l l h l ba, ap pre/pall illegal 11 l l l h x aref/sref illegal 11 llllopcode mrs illegal 11 mode register accessing h x x x x dsel nop - enter idle after tmrd l h h h x nop nop - enter idle after tmrd l h h l x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11 l h l l ba, ca, ap write/writeap illegal 11 l l h h ba, ra act illegal 11 l l h l ba, ap pre/pall illegal 11 l l l h x aref/sref illegal 11 llllopcode mrs illegal 11
rev. 0.6/may. 02 15 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t cke function truth table note : when cke=l, all dq and dqs must be in hi-z state. 1. cke and /cs must be kept high for a minimum of 200 stable input clocks before issuing any command. 2. all command can be stored after 2 clocks from low to high transition of cke. 3. illegal if ck is suspended or stopped during the power down mode. 4. self refresh can be entered only from the all banks idle state. 5. disabling ck may cause malfunction of any bank which is in active state. current state cken- 1 cken /cs /ras /cas /we /add action self refresh 1 h xxxxxx invalid l hhxxxxexit self refresh, enter idle after tsrex l h l h h h x exit self refresh, enter idle after tsrex l h l h h l x illegal l h l h l x x illegal l hl lxxx illegal l lxxxxx nop, conti nue self refresh power down 2 h xxxxxx invalid l hhxxxx exit power down, enter idle l h l h h h x exit power down, enter idle l h l h h l x illegal l h l h l x x illegal l hl lxxx illegal l lxxxxxnop, conti nue power down mode all banks idle 4 h hxxxxxsee operation command truth table hllllhx enter self refresh h lhxxxx exit power down h l l h h h x exit power down h l l h h l x illegal h l l h l x x illegal h l l l h x x illegal hlllllx illegal l lxxxxx nop any state other than above h hxxxxxsee operation command truth table h lxxxxx illegal 5 l hxxxxx invalid l lxxxxx invalid
rev. 0.6/may. 02 16 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t simplified state diagram mrs sref srex pden pdex act aref pdex pden bst read write write writeap writeap read readap readap pre(pall) pre(pall) pre(pall) command input automatic sequence idle auto refresh pre- charge power-up power applied mode register set power down write with autopre- charge power down write read with autopre- charge bank active read self refresh
rev. 0.6/may. 02 17 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t power-up sequence and device initialization ddr sdrams must be powered up and initialized in a pred efined manner. operational procedures other than those specified may result in undefined operation. power must fi rst be applied to vdd, then to vddq, and finally to vref (and to the system vtt). vtt must be applied afte r vddq to avoid device latch-up, which may cause permanent dam- age to the device. vref can be applied anytime after vdd q, but is expected to be nominally coincident with vtt. except for cke, inputs are not recognized as valid until afte r vref is applied. cke is an sstl_2 input, but will detect an lvcmos low level after vdd is applied. maintaining an lvcmos low level on cke during power-up is required to guarantee that the dq and dqs outputs will be in the high-z state, where they will remain until driven in normal operation (by a read access). after all power supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200us delay prior to applying an executable command. once the 200us delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharg e all command should be applied. next a extended mode register set command should be issued for the ex tended mode register, to enable the dll, then a mode register set command should be issued for the mode regi ster, to reset the dll, and to program the operating parameters. 200 clock cycles are requir ed between the dll reset a nd any command. during the 200 cycles of ck, for dll locking, executable commands ar e disallowed (a deselect or nop comm and must be applie d). after the 200 clock cycles, a precharge all command should be applied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set com- mand for the mode register, with the reset dll bit deactivat ed (i.e. to program operating parameters without resetting the dll) must be performed. fo llowing these cycles, the ddr sdram is ready for normal operation. 1. apply power - vdd, vddq, vtt, vref in the followi ng power up sequencing and attempt to maintain cke at lvcmos low state. (all the ot her input pins may be undefined.) ? vdd and vddq are driven from a single power converter output. ? vtt is limited to 1.44v (reflecting vddq(max)/ 2 + 50mv vref variation + 40mv vtt variation. ? vref tracks vddq/2. ? a minimum resistance of 42 ohms (22 oh m series resistor + 22 ohm parallel resistor - 5% tolerance) limits the input current from the vtt supply into any pin. ? if the above criteria cannot be met by the system design, then the follow ing sequencing and voltage relationship must be adhered to during power up. 2. start clock and maintain stable clock for a minimum of 200usec. 3. after stable power and clock, apply nop condition and take cke high. 4. issue extended mode register set (emrs) to enable dll. 5. issue mode register set (mrs) to reset dll and set device to idle state with bit a8=high. (an additional 200 cycles of clock are required for locking dll) 6. issue precharge commands for all banks of the device. voltage description sequencing voltage relationship to avoid latch-up vddq after or with vdd < vdd + 0.3v vtt after or with vddq < vddq + 0.3v vref after or with vddq < vddq + 0.3v
rev. 0.6/may. 02 18 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t 7. issue 2 or more auto refresh commands. 8. issue a mode register set command to init ialize the mode register with bit a8 = low power-up sequence /clk clk vdd dqs dq?s mrs aref pre nop mrs emrs pre nop code code code code code code code code code vddq vref cke cmd ba0,ba1 a10 addr dm ? ???? ? ? ?? ? ? ? ?? ? ? ?? ? ? ?? ? ? tvtd t=200usec tmrd 200 cycles of ck* trp trfc power up vdd and ck stable precharge all emrs set mrs set reset dll (with a8=h) precharge all 2 or more auto refresh mrs set (with a8=l) *200 cycles of ck are required (for dll locking) before any executable command can be applied. vtt trp tis tih
rev. 0.6/may. 02 19 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t mode register set (mrs) the mode register is used to store the various operating m odes such as /cas latency, addressing mode, burst length, burst type, test mode, dll reset. the mode register is programed via mrs command. th is command is issued by the low signals of /ras, /cas, /c s, /we and ba0. this command can be issued only when all banks are in idle state and cke must be high at least one cycle before the mode regi ster set command can be issued. two cycles are required to write the data in mode register. during the mrs cycle, any command cannot be issued. once mode register field is determined, the information will be held until resetted by another mrs command. ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 rfu dr tm cas latency bt burst length a2 a1 a0 burst length sequential interleave 0 0 0 reserved reserved 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved a3 burst type 0 sequential 1 interleave a6 a5 a4 cas latency 000 reserved 001 reserved 010 2 011 reserved 100 reserved 101 reserved 110 2.5 111 reserved a7 te s t mode 0normal 1test a8 dll reset 0no 1yes ba0 mrs type 0mrs 1emrs
rev. 0.6/may. 02 20 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t burst definition burst length & type read and write accesses to the ddr s dram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locati ons that can be accessed for a given read or write com- mand. burst lengths of 2, 4 or 8 loca tions are available for both the sequ ential and the interleaved burst types. reserved states should not be used, as unknown operati on or incompatibility with future versions may result. when a read or write command is issued, a block of column s equal to the burst length is effectively selected. all accesses for that burst take place within this block, mean ing that the burst wraps withi n the block if a boundary is reached. the block is uniquely selected by a1-ai when the burs t length is set to two, by a2 -ai when the burst length is set to four and by a3 -ai when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. accesses within a given burst may be programmed to be either se quential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by t he burst length, the burst type and the starting column address, as shown in burst definitionon table burst length starting address (a2,a1,a0) sequential interleave 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 0, 1, 2, 3, 4, 5, 6, 7 7, 6, 5, 4, 3, 2, 1, 0
rev. 0.6/may. 02 21 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t cas latency the read latency or cas latency is the delay in clock cycles between the registration of a read command and the availability of the first burst of outp ut data. the laten cy can be programmed 2 or 2.5 clocks. if a read command is registered at clock edge n, and the la tency is m clocks, the data is available nominally coincident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. dll reset the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon return- ing to normal operation after having disabled the dll for th e purpose of debug or evaluation. the dll is automatically disabled when entering self refresh operation and is automa tically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before an any command can be issued. output driver impedance control the normal drive strength for all outputs is specified to be sstl_2, class ii. hynix also supports a half strength driver option, intended for lighter load and/or point-to-point envi ronments. selection of the half strength driver option will reduce the output drive st rength by 50% of that of the fu ll strength driver. i-v curves for both the full strength driver and the half strength driver are included in this document.
rev. 0.6/may. 02 22 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t extended mode register set (emrs) the extended mode register controls functions beyond those controlled by the mode register; these additional func- tions include dll enable/disable, output dr iver strength selection(optional). thes e functions are controlled via the bits shown below. the extended mode register is programmed via the mode register set command ( ba0=1 and ba1=0) and will retain the stored inform ation until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before in itiating any subsequent operat ion. violating either of these requirements will result in unspecified operation. ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 rfu* 0** ds dll a0 dll enable 0 enable 1diable ba0 mrs type 0mrs 1emrs a1 output driver impedance control 0 full strength driver 1 half strength driver * all bits in rfu address fields must be programmed to zero, all other states are reserved for future usage ** this part do not support /qfc function, a2 must be programmed to zero.
rev. 0.6/may. 02 23 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v ddq must not exceed the level of v dd . 2. v il (min) is acceptable -1.5v ac pulse width with < 5ns of duration. 3. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak to peak noise on vref may not exceed +/- 2% of the dc value. dc characteristics i (ta=0 to 70c, voltage referenced to v ss = 0v) note : 1. vin = 0 to 3.6v, all other pins are not tested under vin =0v. 2. dout is disabled, vout=0 to 2.7v parameter symbol rating unit ambient temperature t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -0.5 ~ 3.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 1w soldering temperature t time t solder 260 t 10 o c t sec parameter symbol min typ. max unit note power supply voltage v dd 2.3 2.5 2.7 v power supply voltage v ddq 2.3 2.5 2.7 v 1 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v 2 termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref 0.49*vddq 0.5*vddq 0.51*vddq v 3 parameter symbol min. max unit note input leakage current i li -2 2 ua 1 output leakage current i lo -5 5 ua 2 output high voltage v oh v tt + 0.76 - v i oh = -15.2ma output low voltage v ol -v tt - 0.76 v i ol = +15.2ma
rev. 0.6/may. 02 24 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t dc characteristics ii (ta=0 to 70c, voltage referenced to v ss = 0v) 128mx4 parameter symbol test condition speed unit note -k -h -l operating current idd0 one bank; active - precharge ; trc=trc(min); tck=tck(min) ; dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 110 110 100 ma operating current i dd1 one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle 130 130 120 ma precharge power down standby current i dd2p all banks idle; power down mode; cke=low, tck=tck(min) 776 ma idle standby current i dd2n vin>=vih(min) or vin==vih(min); all banks idle; cke>=vih(min); addresses and other control inputs stable, vin=vref for dq, dqs and dm 32 ma active power down standby current i dd3p one bank active; power down mode; cke=low, tck=tck(min) 10 ma active standby current i dd3n /cs=high; cke=high; one bank; active-precharge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 40 ma operating current i dd4r burst=2; reads; continuous burst; one bank active; address and control inputs c hanging once per clock cycle; tck=tck(min); iout=0ma 180 180 150 ma operating current i dd4w burst=2; writes; continuous burst; one bank active; address and control inputs c hanging once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle 200 200 180 auto refresh current i dd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; distributed refresh 300 300 260 self refresh current i dd6 cke =< 0.2v; external clock on; tck=tck(min) normal 5 ma low power 2.5 ma operating current - four bank operation i dd7 four bank interleaving with bl=4, refer to the following page for detailed test condition 380 380 350 ma random read current i dd7a 4banks active read with ac tivate every 20ns, ap(auto precharge) read every 20ns, bl=4, trcd=3, iout=0 ma, 100% dq, dm and dqs inputs changing twice per clock cycle; 100% addresses changi ng once per clock cycle 380 380 350 ma
rev. 0.6/may. 02 25 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t dc characteristics ii (ta=0 to 70c, voltage referenced to v ss = 0v) 64mx8 parameter symbol test condition speed unit note -k -h -l operating current idd0 one bank; active - precharge ; trc=trc(min); tck=tck(min) ; dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 110 110 100 ma operating current i dd1 one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle 130 130 120 ma precharge power down standby current i dd2p all banks idle; power down mode; cke=low, tck=tck(min) 776 ma idle standby current i dd2n vin>=vih(min) or vin==vih(min); all banks idle; cke>=vih(min); addresses and other control inputs stable, vin=vref for dq, dqs and dm 32 ma active power down standby current i dd3p one bank active; power down mode; cke=low, tck=tck(min) 10 ma active standby current i dd3n /cs=high; cke=high; one bank; active-precharge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 40 ma operating current i dd4r burst=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); iout=0ma 190 190 160 ma operating current i dd4w burst=2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle 210 210 190 auto refresh current i dd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; distributed refresh 300 300 260 self refresh current i dd6 cke =< 0.2v; external clock on; tck=tck(min) normal 5 ma low power 2.5 ma operating current - four bank operation i dd7 four bank interleaving with bl=4, refer to the following page for detailed test condition 380 380 350 ma random read current i dd7a 4banks active read with ac tivate every 20ns, ap(auto precharge) read every 20ns, bl=4, trcd=3, iout=0 ma, 100% dq, dm and dqs inputs changing twice per clock cycle; 100% addresses changi ng once per clock cycle 380 380 350 ma
rev. 0.6/may. 02 26 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t dc characteristics ii (ta=0 to 70c, voltage referenced to v ss = 0v) 32mx16 parameter symbol test condition speed unit note -k -h -l operating current idd0 one bank; active - precharge ; trc=trc(min); tck=tck(min) ; dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 110 110 100 operating current i dd1 one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle 130 130 120 ma precharge power down standby current i dd2p all banks idle; power down mode; cke=low, tck=tck(min) 776 ma idle standby current i dd2n vin>=vih(min) or vin==vih(min); all banks idle; cke>=vih(min); addresses and other control inputs stable, vin=vref for dq, dqs and dm 32 ma active power down standby current i dd3p one bank active; power down mode; cke=low, tck=tck(min) 10 ma active standby current i dd3n /cs=high; cke=high; one bank; active-precharge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 40 ma operating current i dd4r burst=2; reads; continuous burst; one bank active; address and control inputs c hanging once per clock cycle; tck=tck(min); iout=0ma 200 200 170 ma operating current i dd4w burst=2; writes; continuous burst; one bank active; address and control inputs c hanging once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle 220 220 200 auto refresh current i dd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; distributed refresh 300 300 260 self refresh current i dd6 cke =< 0.2v; external clock on; tck=tck(min) normal 5 ma low power 2.5 ma operating current - four bank operation i dd7 four bank interleaving with bl=4, refer to the following page for detailed test condition 390 390 350 ma random read current i dd7a 4banks active read with ac tivate every 20ns, ap(auto precharge) read every 20ns, bl=4, trcd=3, iout=0 ma, 100% dq, dm and dqs inputs changing twice per clock cycle; 100% addresses changi ng once per clock cycle 390 390 350 ma
rev. 0.6/may. 02 27 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t detailed test conditions for ddr sdram idd1 & idd7 idd1 : operating current: one bank operation 1. typical case : vdd = 2.5v, t=25 o c 2. worst case : vdd = 2.7v, t= 10 o c 3. only one bank is accessed with trc(min), burst mode, address and control inputs on nop edge are changing once per clock cycle. lout = 0ma 4. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=4, trcd = 2*tck, tras = 5*tck read : a0 n r0 n n p0 n a0 n - repeat the sa me timing with random address changing 50% of data changing at every burst - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5 , bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl=2, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing 50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop idd7 : operating current: four bank operation 1. typical case : vdd = 2.5v, t=25 o c 2. worst case : vdd = 2.7v, t= 10 o c 3. four banks are being interleaved with trc(min), bu rst mode, address and control inputs on nop edge are not changing. lout = 0ma 4. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=4 , trrd = 2*tck, trcd= 3*tc k, read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 a0 r3 a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5, bl=4, trrd = 2*tck, trcd = 3*tck read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl2=2, bl=4, trrd = 2*tck, trcd = 3*tck read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop
rev. 0.6/may. 02 28 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t ac operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. vid is the magnitude of the difference between the input level on ck and the input on /ck. 2. the value of vix is expected to equal 0.5*v ddq of the trans mitting device and must track variations in the dc level of the same. ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) parameter symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals v il(ac) v ref - 0.31 v input differential voltage, ck and /ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and /ck inputs v ix(ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v 2 parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.31 v ac input low level voltage (v il , max) v ref - 0.31 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t )50w series resistor (r s )25w output load capacitance for access time measurement (c l )30 pf
rev. 0.6/may. 02 29 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t ac characteristics (ac operating conditions unless otherwise noted) parameter symbol -k(ddr266a) -h(ddr266b) -l(ddr200) unit note min max min max min max row cycle time t rc 65 - 65 - 70 - ns auto refresh row cycle time t rfc 75 - 75 - 80 - ns row active time t ras 45 120k 45 120k 50 120k ns active to read with auto precharge delay t rap trcd or trpmin - trcd or trpmin - trcd or trpmin -ns16 row address to column address delay t rcd 20 - 20 - 20 - ns row active to row active delay t rrd 15 - 15 - 15 - ns column address to column address delay t ccd 1-1-1-ck row precharge time t rp 20 - 20 - 20 - ns write recovery time t wr 15 - 15 - 20 - ns write to read command delay t wtr 1-1-1-ck auto precharge write recovery + precharge time t dal 5-5-4-ck15 system clock cycle time cl = 2.5 t ck 7.5 12 7.5 12 8 12 ns cl = 2 7.5 12 10 12 10 12 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew t ac -0.75 0.75 -0.75 0.75 -0.8 0.8 ns dqs-out edge to clock edge skew t dqsck -0.75 0.75 -0.75 0.75 -0.8 0.8 ns dqs-out edge to data-out edge skew t dqsq -0.5-0.5-0.6ns data-out hold time from dqs t qh t hpmin -t qhs - t hpmin -t qhs - t hpmin -t qhs -ns1, 10 clock half period t hp t ch/l min - t ch/l min - t ch/l min -ns1,9 data hold skew factor t qhs -0.75-0.75-0.75ns10 valid data output window t dv t qh -t dqsq t qh -t dqsq t qh -t dqsq ns data-out high-impedance window from ck, /ck t hz -0.7 0.75 -0.7 0.75 -0.8 0.8 ns data-out low-impedance window from ck, /ck t lz -0.7 0.75 -0.7 0.75 -0.8 0.8 ns input setup time (fast slew rate) t is 0.9 - 0.9 - 1.1 - ns 2,3,5,6 input hold time (fast slew rate) t ih 0.9 - 0.9 - 1.1 - ns 2,3,5,6 input setup time (slow slew rate) t is 1.0 - 1.0 - 1.1 - ns 2,4,5,6
rev. 0.6/may. 02 30 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t note : 1. this calculation accounts for tdqsq(max), the pul se width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the clock : a0~a12, ba0~ba1, cke, /cs, /ras, /cas, /we. 3. for command/address input slew rate >=1.0v/ns 4. for command/address input slew rate >=0.5v/ns and <1.0v/ns this derating table is used to increase tis/tih in case where the input slew-rate is below 0.5v/ns. input setup / hold slew-rate derating table. 5. ck, /ck slew rates are >=1.0v/ns 6. these parameters guarantee device timing, but they are not neces sarily tested on each device, and they may be guaranteed by design or tester correlation. 7. data latched at both rising and falling edges of data strobes(ldqs/udqs) : dq, ldm/udm. 8. minimum of 200 cycles of stable input clocks after self refresh exit command, where cke is held high, is required to complete self refresh exit and lock the internal dll circuit of ddr sdram. input hold time (slow slew rate) t ih 1.0 - 1.0 - 1.1 - ns 2,4,5,6 input pulse width t ipw 2.2 2.2 - ns 6 write dqs high level width t dqsh 0.35 - 0.35 - 0.35 - ck write dqs low level width t dqsl 0.35 - 0.35 - 0.35 - ck clock to first ri sing edge of dqs-in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 ck data-in setup time to dqs-in (dq & dm) t ds 0.5 - 0.5 - 0.6 - ns 6,7, 11~13 data-in hold time to dqs-in (dq & dm) t dh 0.5 - 0.5 - 0.6 - ns 6,7, 11~13 dq & dm input pulse width t dipw 1.75 - 1.75 - 2 - ns read dqs preamble time t rpre 0.9 1.1 0.9 1.1 0.9 1.1 ck read dqs postamble time t rpst 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs preamble setup time t wpres 0-0-0-ck write dqs preamble hold time t wpreh 0.25 - 0.25 - 0.25 - ck write dqs postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 ck mode register set delay t mrd 2-2-2-ck exit self refresh to any execute command t xsc 200 - 200 - 200 - ck 8 average periodic refresh interval t refi -7.8-7.8-7.8us input setup / hold slew-rate delta tis delta tih v/ns ps ps 0.5 0 0 0.4 +50 0 0.3 +100 0 parameter symbol -k(ddr266a) -h(ddr266b) -l(ddr200) unit note min max min max min max
rev. 0.6/may. 02 31 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t 9. min (tcl, tch) refers to the smaller of the actual clock lo w time and the actual clock high ti me as provided to the device (i .e. this value can be greater than the minimum specification limits for tcl and tch). 10. thp = minimum half clock period for any gi ven cycle and is defined by clock high or cl ock low (tch, tcl). tqhs consists of tdqsqmax, the pulse width distortion of on- chip clock circuits, data pin to pin ske w and output pattern effects and p-channel t o n-channel variation of the output drivers. 11. this derating table is used to increase tds/tdh in case where the input slew-rate is below 0.5v/ns. input setup / hold slew-rate derating table. 12. i/o setup/hold plateau derating. this derating table is used to increase tds/tdh in case where the input level is flat below vref +/-310mv for a duration of up to 2ns. 13. i/o setup/hold delta inverse slew rate derating. this derati ng table is used to increase tds/tdh in case where the dq and dqs slew rates differ. the delta inverse slew rate is calculated as (1/slewrate1)-(1/slewrate2). for example, if slew rate 1 = 0.5v/ns and slew rate2 = 0.4v/n then the delta inverse slew rate = -0.5ns/v. 14. dqs, dm and dq input slew rate is spec ified to prevent double clocking of data and preserve setup and hold times. signal tra n- sitions through the dc region must be monotonic. 15. tdal = (tdpl / tck ) + (trp / tck ). for each of the terms above, if not already an integer, round to the next highest integ er. tck is equal to the actual system clock cycle time. example: for ddr266b at cl=2.5 and tck = 7.5 ns, tdal = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) round up each non-integer to the next highest integer: = (2) + (3), tdal = 5 clocks 16. for the parts which do not has internal ras lockout circuit, ac tive to read with auto precharge delay should be tras - bl/2 x tck. input setup / hold slew-rate delta tds delta tdh v/ns ps ps 0.5 0 0 0.4 +75 +75 0.3 +150 +150 i/o input level delta tds delta tdh mv ps ps +280 +50 +50 (1/slewrate1)-(1/slewrate2) delta tds delta tdh ns/v ps ps 000 +/-0.25 +50 +50 +/- 0.5 +100 +100
rev. 0.6/may. 02 32 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t capacitance (t a =25 o c, f=100mhz ) note : 1. vdd = min. to max., vddq = 2.3v to 2.7v, v o dc = vddq/2, v o peak-to-peak = 0.2v 2. pins not under test are tied to gnd. 3. these values are guaranteed by desi gn and are tested on a sample basis only. output load circuit parameter pin symbol min max unit input clock capacitance ck, /ck c i1 2.0 3.0 pf delta input clock capacitance ck, /ck delta c i1 -0.25pf input capacitance all other input-only pins c i1 2.0 3.0 pf delta input capacitance all other input-only pins delta c i2 -0.5pf input / output capacitanc dq, dqs, dm c io 4.0 5.0 pf delta input / output capacitance dq, dqs, dm delta c io -0.5pf v ref v tt r t =50 ? zo=50 ? c l =30pf output
rev. 0.6/may. 02 33 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t output drive characteristics (full strength driver) evaluation conditions: typical 25 o c (tambient), vddq=2.5v, typical process minimum 70 o c (tambient), vddq=2.3v, slow slow process maximum 0 o c (tambient), vddq=2.7v, fast fast process voltage pull down current (ma) pull up current (ma) nominal low nominal high minimum maximum nominal low nominal high minimum maximum 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9 2.1 62.8 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2
rev. 0.6/may. 02 34 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t output drive characteristics (full strength driver ) 0 20 40 60 80 100 120 140 160 00.511.522.5 maxi mum nominal high nominal low mi ni mum pull down characteristics iout (ma) vout to v ssq (v) -220 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 maxi mum nominal high nominal low mi ni mum pull up characteristics iout (ma) v ddq to vout (v)
rev. 0.6/may. 02 35 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t output drive characteristics (half strength driver) evaluation conditions: typical 25 o c (tambient), vddq=2.5v, typical process minimum 70 o c (tambient), vddq=2.3v, slow slow process maximum 0 o c (tambient), vddq=2.7v, fast fast process voltage pull down current (ma) pull up current (ma) nominal low nominal high minimum maximum nominal low nominal high minimum maximum 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -7.8 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.9 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7
rev. 0.6/may. 02 36 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t output drive characteristics (half strength driver) 0 20 40 60 80 100 00.511.522.5 maxi mum nominal high nominal low mi ni mum pull down characteristics iout (ma) vout to v ssq (v) -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 maxi mum nominal high nominal low mi ni mum pull up characteristics iout (ma) v ddq to vout (v)
rev. 0.6/may. 02 37 hy5du12422(l)t hy5du12822(l)t hy5du121622(l)t package information 400mil 66pin thin small outline package 10.26 (0.404) 10.05 (0.396) 11.94 (0.470) 11.79 (0.462) 22.33 (0.879) 22.12 (0.871) 1.194 (0.0470) 0.991 (0.0390) 0.65 (0.0256) bsc 0.35 (0.0138) 0.25 (0.0098) 0.15 (0.0059) 0.05 (0.0020) base plane seating plane 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) 0 ~ 5 deg. unit : mm(inch)

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