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features ? supply voltage 4.5v to 5.5v operating temperature range ?40c to +85c minimal external circuitry requirements, no rf components on the pc board except matching to the receiver antenna high sensitivity, especi ally at low data rates sensitivity reduction possib le even while receiving fully integrated vco low power consumption due to configurable self-polling with a programmable time frame check single-ended rf input for easy matching to / 4 antenna or printed antenna on pcb low-cost solution due to high integration level esd protection according to mil-std 883 (4 kv hbm) except pin pout (2 kv hbm) high image frequency suppre ssion due to 1 mhz if in conjunction with a saw front-end filter. up to 40 db is thereby achievable with newer saws programmable output port for sensitivity selection or for controlling external periphery communication to the microcontroller possib le via a single, bi-d irectional data line power management (polling) is also possible by means of a separate pin via the microcontroller 1. description the ata3745 is a multi-chip pll receiver device supplied in an so20 package. it has been specially developed for the demands of rf low-cost data transmission systems with low data rates from 1 kbaud to 10 kbaud in manchester or bi-phase code. the receiver is well-suited to operate with atmel?s pll rf transmitter ata2745. it can be used in the frequency receiving range of f 0 = 310 mhz to 440 mhz for ask data trans- mission. all the statements made below refer to 433.92 mhz and 315 mhz applications. the main applications of the ata3745 are in the areas of outside temperature meter- ing, socket control, garage door openers, consumption metering, light/fan or air-conditioning control, jalousies, wire less keyboards, and various other consumer market applications. uhf ask/fsk receiver ata3745 4901b?rke?11/07
2 4901b?rke?11/07 ata3745 figure 1-1. system block diagram figure 1-2. block diagram micro- controller pll 1 li cell keys encoder atarx9x uhf ask/fsk remote control receiver uhf ask/fsk remote control transmitter ata2745 ata3745 lna vco pll xto power amp. vco antenna demod data interf. 1 to 3 xto antenna 4th order polling circuit and control logic standby logic sensitivity reduction f :64 if amp if amp demodulator and data filter rssi limiter out dem_out lna clk enable dvcc mode test data v s fe lpf 3 mhz lpf 3 mhz ask lnagnd lna_in mixvcc dgnd agnd avcc cdem lfvcc xto lf lfgnd vco xto 50 k ? pout
3 4901b?rke?11/07 ata3745 2. pin configuration figure 2-1. pinning so20 16 15 12 11 14 13 20 19 18 17 5 6 9 10 7 8 1 2 3 4 nc ask cdem avcc agnd dgnd mixvcc nc lnagnd lna_in data enabl e test pout mode dvcc xto lfvcc lfgnd lf table 2-1. pin description pin symbol function 1 nc not connected 2 ask ask high 3 cdem lower cut-off frequency data filter 4 avcc analog power supply 5 agnd analog ground 6 dgnd digital ground 7 mixvcc power supply mixer 8 lnagnd high-frequency ground lna and mixer 9 lna_in rf input 10 nc not connected 11 lfvcc power supply vco 12 lf loop filter 13 lfgnd ground vco 14 xto crystal oscillator 15 dvcc digital power supply 16 mode selecting 433.92 mhz/315 mhz. low: 4. 90625 mhz (usa), high: 6.76438 mhz (europe) 17 pout programmable output port 18 test test pin, during operation at gnd 19 enable enables the polling mode. low: polling mode off (sleep mode). high: polling mode on (active mode) 20 data data output/configuration input
4 4901b?rke?11/07 ata3745 3. rf front end the rf front end of the receiver is a heterodyne configuration that c onverts the input signal into a 1-mhz if signal. as shown in the bloc k diagram, the front end consists of an lna (low noise amplifier), lo (local oscilla tor), a mixer and an rf amplifier. the lo generates the carrier frequency for the mixer via a pll synthesizer. the xto (crystal oscillator) generates the reference frequency f xto . the vco (voltage-controlled oscillator) generates the drive voltage frequency f lo for the mixer. f lo is dependent on the voltage at pin lf. f lo is divided by a factor of 64. the divided frequency is compared to f xto by the phase fre- quency detector. the current output of the phas e frequency detector is connected to a passive loop filter and thereby generates the control voltage v lf for the vco. by means of that config- uration, v lf is controlled such that f lo / 64 is equal to f xto . if f lo is determined, f xto can be calculated using the following formula: the xto is a one-pin oscillator th at operates at the series reso nance of the quartz crystal. fig- ure 3-1 shows the proper layout, with the crystal connected to gnd via a capacitor cl. the value of that capacitor is recommended by the crystal supplier. the value of cl should be opti- mized for the individual board layout to achieve the exact value of f xto and thereby of f lo . when designing the system in terms of receiving bandwidth, the accuracy of the crystal and xto must be considered. figure 3-1. pll peripherals the passive loop filter connected to pin lf is designed for a loop bandwidth of b loop = 100 khz. this value for b loop exhibits the best possible noise performance of the lo. figure 3-1 shows the appropriate loop filter co mponents to achieve the desired loop band- width. if the filter components are changed for any reason, please note that the maximum capacitive load at pin lf is limited. if the capacitive load is exceeded, a bit check may no longer be possible since f lo cannot settle in time before the bit check starts to evaluate the incoming data stream. therefore, self polling also does not work in that case. f lo is determined by the rf input frequency f rf and the if frequency f if using the following for- mula: f xto f lo 64 ------- - = xto lfvcc lf lfgnd dvcc v s v s c l c 9 r 1 820 ? 4.7 nf c 10 1 nf f lo f rf f if ? =
5 4901b?rke?11/07 ata3745 to determine f lo , the construction of the if filter must be considered at this point. the nominal if frequency is f if = 1 mhz. to achieve a good accuracy of the filter?s corner frequencies, the filter is tuned by the crystal frequency f xto . this means that there is a fixed relation between f if and f lo that depends on the logic level at pin mode. this is described by the following formu- las: the relation is designed to achieve the nominal if frequency of f if = 1 mhz for most applica- tions. for applications where f rf = 315 mhz, the mode must be set to ?0?. in the case of f rf = 433.92 mhz, the mode must be set to ?1?. for other rf frequencies, f if is not equal to 1mhz. f if is then dependent on the logical level at pin mode and on f rf . table 3-1 summa- rizes the different conditions. the rf input either from an antenna or from a generator must be transformed to the rf input pin lna_in. the input impedance of that pin is provided in the electrical parameters. the par- asitic board inductances and capacitances also influence the input matching. the rf receiver ata3745 exhibits its highest sensitivity at the best signal-to-noise ratio (snr) in the lna. hence, noise matching is the best choice for designing the transformation network. a good practice when designing the network is to start with power matching. from that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. if a saw is implemented into the input network, a mirror frequency suppression of ? p ref = 40 db can be achieved. there are saws available that exhibit a notch at ? f=2mhz. these saws work best for an intermediate frequency of if = 1 mhz. the selectivity of the receiver is also improved by using a saw. in typical automotive applications, a saw is used. figure 3-2 on page 6 shows a typical input matching network for f rf = 315 mhz and f rf = 433.92 mhz using a saw. figure 3-3 on page 6 illustrates an input matching to 50 ? without a saw. the input matching networks shown in figure 3-3 on page 6 are the reference networks for the parameters given in the section ?electrical characteri stics? on page 23 . table 3-1. calculation of lo and if frequency conditions local oscillator frequency intermediate frequency f rf = 315 mhz, mode = 0 f lo = 314 mhz f if = 1 mhz f rf = 433.92 mhz, mode = 1 f lo = 432.92 mhz f if = 1 mhz 300 mhz < f rf < 365 mhz, mode = 0 365 mhz < f rf < 450 mhz, mode = 1 mode 0 (usa) f if f lo 314 --------- - == mode 1 (europe) f if f lo 432.92 ----------------- - == f lo f rf 1 1 314 --------- - + ------------------- = f if f lo 314 --------- - = f lo f rf 1 1 432.92 ----------------- - + --------------------------- - = f if f lo 432.92 ----------------- - =
6 4901b?rke?11/07 ata3745 figure 3-2. input matching network with saw filter figure 3-3. input matching network without saw filter please note that for all coupling conditions (see figure 3-2 and figure 3-3 ), the bond wire inductivity of the lna ground is compensated. c3 forms a series resonance circuit together with the bond wire. l = 25 nh is a feed inductor to establish a dc path. its value is not critical but must be large enough not to detune the series resonance circuit. for cost reduction, this inductor can be easily printed on the pcb. this configuration improves the sensitivity of the receiver by about 1 db to 2 db. c 17 c 2 rf in f rf = 433.92 mhz 8.2 pf c 3 25 nh l l 3 27 nh l 2 33 nh 8.2 pf lna_in ata3745 lnagnd out_gnd case_gnd b3555 out in_gnd in 7, 8 3, 4 5 6 1 2 9 8 c 16 22 pf 100 pf toko ? ll2012 f27nj toko ? ll2012 f33nj c 17 c 2 rf in f rf = 315 mhz 10 pf c 3 25 nh l l 3 47 nh l 2 82 nh 22 pf lna_in ata3745 lnagnd out_gnd case_gnd b3551 out in_gnd in 7, 8 3, 4 5 6 1 2 9 8 c 16 47 pf 100 pf toko ? ll2012 f47nj toko ? ll2012 f82nj rf in f rf = 433.92 mhz 3.3 pf 100 pf 22 nh toko ? ll2012 f22nj 25 nh 15 pf lna_in ata3745 lnagnd 9 8 rf in f rf = 315 mhz 3.3 pf 100 pf 39 nh toko ? ll2012 f39nj 25 nh 33 pf lna_in ata3745 lnagnd 9 8
7 4901b?rke?11/07 ata3745 4. analog signal processing 4.1 if amplifier the signals coming from the rf front end are filtered by the fully integrated 4th-order if filter. the if center frequency is f if = 1 mhz for applications where f rf =315mhz or f rf = 433.92 mhz is used. for other rf input frequencies, refer to table 3-1 on page 5 to determine the center frequency. the receiver ata3745 employs an if bandwidth of b if = 600 khz. this ic can be used together with the ata2745. saw transmitters exhibit much higher transmit frequency toler- ances compared to pll transmitters. generally, it is necessary to use b if = 600 khz together with such transmitters. 4.2 rssi amplifier the subsequent rssi amplifier enhances the output signal of the if amplifier before it is fed into the demodulator. the dynamic range of this amplifier is ? r rssi = 60 db. if the rssi ampli- fier is operated within its linear range, the bes t signal-to-noise ratio (snr) is maintained in ask mode. if the dynamic range is exceeded by the tr ansmitter signal, t he snr is defined by the ratio of the maximum rssi output voltage and the rssi output voltage due to a disturber. the dynamic range of the rssi amplifier is exceeded if the rf input signal is about 60 db higher compared to the rf in put signal at full sensitivity. since different rf input networks may exhibit s lightly different values for the lna gain, the sensitivity values given in the electrical charac teristics refer to a spec ific input matching. this matching is illustrated in figure 3-3 on page 6 and exhibits the best possible sensitivity. 4.3 demodulator and data filter the signal coming from the rssi amplifier is converted into the raw data signal by the ask demodulator. in ask mode, an automatic threshold control (atc) circuit is employed to set the detection ref- erence voltage to a value where a good snr is achieved. this circuit also implies the effective suppression of any kind of in-band noise signals or competing transmitters. if the snr exceeds 10 db, the data signal can be detected properly. the output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. the data filter improv es the snr as its band-pass can be adapted to the characteristics of the data signal. the data filter consists of a 1st-order high-pass and a 1st-order low-pass filter. the high-pass filter cut-off frequency is defi ned by an external capacitor connected to pin cdem. the cut-off frequency of the high-pass filter is defined by the following formula: in self-polling mode, the data filter must settle very ra pidly to achieve a low current consump- tion. therefore, cdem cannot be increased to very high values if self polling is used. on the other hand, cdem must be large enough to meet the data filter requirements according to the data signal. recommended values for cdem are given in the section ?electrical characteris- tics? on page 23 . f cu_df 1 2 30 k ? cdem ------------------------------------------------------------- =
8 4901b?rke?11/07 ata3745 the cut-off frequency of the low-pass filter is defined by the selected baud rate range (br_range). br_range is defined in the opmode register (refer to ?configuration of the receiver? on page 18 ). br_range must be set in accordance to the used baud rate. the ata3745 is designed to operate with data encoding where the dc level of the data signal is 50%. this is valid for manchester and bi-phase encoding. if other modulation schemes are used, the dc level should always remain within the range of v dc_min = 33% and v dc_max = 66%. the sensitivity may be reduced by up to 1.5 db in that condition. each br_range is also defined by a mi nimum and a maximum edge-to-edge time (t ee_sig ). these limits are defined in the section ?electrical characteristics? on page 23 . they should not be exceeded to maintain full sensitivity of the receiver. 4.4 receiving characteristics the rf receiver ata3745 can be operated with and without a saw front end filter. the selec- tivity with and without a saw fron t-end filter is illustrated in figure 4-1 . this example relates to ask mode of the ata3745. note that the mirror frequency is reduced by 40 db . the plots are printed relative to the maximum sensitivity. if a saw filter is used, an insertion loss of about 4 db must be considered. when designing the system in terms of receiving bandwidth, the lo deviation must be consid- ered as it also determines the if center frequency. the total lo deviation is calculated to be the sum of the deviation of the crystal and the xto deviation of the ata3745. low-cost crys- tals are specified to be within 100 ppm. the xto deviation of the ata3745 is an additional deviation due to the xto circuit. this deviation is specified to be 50 ppm. if a crystal of 100 ppm is used, the total deviation is 150 ppm in that case. note that the receiving band- width and the if-filt er bandwidth are equ ivalent in ask mode. figure 4-1. receiving freque ncy response -100.0 -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 df ( mhz ) dp (db) without saw with saw
9 4901b?rke?11/07 ata3745 5. polling circuit and control logic the receiver is designed to consume less t han 1 ma while being sensitive to signals from a corresponding trans mitter. this is achieved via the pollin g circuit. this circuit enables the sig- nal path periodically for a short time. during this time, the bit check logic verifies the presence of a valid transmitter signal. only if a valid si gnal is detected does the receiver remain active and transfer the data to the connected microcontroller. if there is no valid signal present, the receiver is in sleep mode most of the time, resu lting in low current cons umption. this condition is called polling mode. a connected microcon troller is disabled during that time. all relevant parameters of the polling logic can be configured by the connected microcontrol- ler. this flexibility enables the us er to meet the specifications in terms of current consumption, system response time, data rate, etc. regarding the number of connection wires to the microcontroller, the receiver is very flexible. it can be either operated by a single bi-directional line to save ports to the connected micro- controller, or it can be operated by up to three uni-directional ports. 5.1 basic clock cycle of the digital circuitry the complete timing of the digital circuitry and the analog filtering is derived from one clock. figure 5-1 shows how this clock cycle t clk is derived from the cryst al oscillator (xto) in com- bination with a divider. the divi sion factor is controlled by the logical state at pin mode. as described in ?rf front end? on page 4 , the frequency of the crystal oscillator (f xto ) is defined by the rf input signal (f rfin ) which also defines the operatin g frequency of the local oscillator (f lo ). figure 5-1. generation of the basic clock cycle pin mode can now be set in accordance with the desired clock cycle t clk . t clk controls the fol- lowing application-rele vant parameters: timing of the polling circuit including bit check timing of analog and digital signal processing timing of register programming frequency of the reset marker if filter center frequency (f if0 ) 16 mode l: usa (:10) h: europe (:14) xto divider :14/10 dvcc xto f xto t clk 15 14
10 4901b?rke?11/07 ata3745 most applications are dominated by two transmission frequencies: f send = 315 mhz is mainly used in the usa, f send = 433.92 mhz in europe. in order to ease the usage of all t clk -depen- dent parameters, the electrical characteristics display three conditions for each parameter. usa applications (f xto = 4.90625 mhz, mode = l, t clk = 2.0383 s) european applications (f xto = 6.76438 mhz, mode = h, t clk = 2.0697 s) other applications (t clk is dependent on f xto and on the logical state of pin mode. the electrical characteristic is given as a function of t clk ). the clock cycle of some function blocks depends on the selected baud rate range (br_range) which is defined in the opmode register. this clock cycle t xclk is defined by the following formulas for further reference: 5.2 polling mode according to figure 3-2 on page 6 , the receiver stays in polling mode in a continuous cycle of three different modes. in sleep mode, the signal processing circuitry is disabled for the time period t sleep while consuming low current of i s =i soff . during the start-up period, t startup , all sig- nal processing circuits are enabled and settled. in the following bit check mode, the incoming data stream is analyzed bit by bit looking for a valid transmitter signal. if no valid signal is present, the receiver is set back to sleep mode after the period t bitcheck . this period varies check by check as it is a statisti cal process. an average value for t bitcheck is given in the sec- tion ?electrical characteristics? on page 23 . during t startup and t bitcheck the current consumption is i s =i son . the average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: during t sleep and t startup , the receiver is not sensitive to a transmitter signal. to guarantee the reception of a transmitted command, the transmitter must start the telegram with an adequate preburst. the required length of the preburst is dependent on the polling parameters t sleep , t startup , t bitcheck and the startup time of a connected microcontroller (t start_c ). t bitcheck thus depends on the actual bit rate and the number of bits (n bitcheck ) to be tested. the following formula indicates how to calculate the preburst length. t preburst t sleep + t startup + t bitcheck + t start_ c br_range = br_range0: t xclk = 8 t clk br_range1: t xclk = 4 t clk br_range2: t xclk = 2 t clk br_range3: t xclk = 1 t clk i spoll i soff t sleep i son t startup t bitcheck + () + t sleep t startup t bitcheck ++ ------------------------------------------------------------------------------------------------------------ =
11 4901b?rke?11/07 ata3745 5.2.1 sleep mode the length of period t sleep is defined by the 5-bit word sl eep of the opmode register, the extension factor x sleep described in table 5-8 on page 20 , and the basic clock cycle t clk . it is calculated to be: in us and european applications, the maximum value of t sleep is about 60 ms if x sleep is set to 1. the time resolution is about 2 ms in that case. the sleep time can be extended to almost half a second by setting x sleep to 8. x sleep can be set to 8 by bit x sleepstd or by bit x sleeptemp , resulting in a different mode of action as described below: x sleepstd = 1 implies the standard extension fact or. the sleep time is always extended. x sleeptemp = 1 implies the temporary extension factor. the extended sleep time is used as long as every bit check is ok. if t he bit check fails once, this bit is set back to 0 automatically, resulting in a regular sleep time. this functionality can be used to save current in presence of a modulated disturber similar to an expected transmitter signal. the connected microcontroller is rarely activated in that condition. if the disturber disappears, the receiver switches back to regular polling and is again sensitive to appropriate transmitter signals. table 5-6 on page 19 shows how the highest register value of sleep sets the receiver to a per- manent sleep condition. the receiv er remains in that condition until another value for sleep is programmed into the opmode register. this function is desirable where several devices share a single data line. t sleep sleep x sleep 1024 t clk =
12 4901b?rke?11/07 ata3745 figure 5-2. polling mode flow chart figure 5-3. timing diagram for a completely successful bit check bit-check mode: the incoming data stream is analyzed. if the timing indicates a valid transmitter signal, the receiver is set to receiving mode. otherwise it is set to sleep mode. t bit-check i s = i son start-up mode: the signal processing circuits are enabled. after the start-up time (t startup ) all circuits are in stable condition and ready to receive. t startup i s = i son receiving mode: the receiver is turned on permanently and passes the data stream to the connected microcontroller. it can be set to sleep mode through an off command via pin data or enable i s = i son sleep mode: all circuits for signal processing are disabled. only xto and polling logic are enabled. t sleep = sleep x sleep 1024 t clk i s = i son bit check ok ? 5-bit word defined by sleep0 to sleep4 in opmode register sleep: is defined by the selected baud-rate range and t clk . the baud-rate range is defined by baud0 and baud1 in the opmode register. t startup : basic clock cycle defined by f xto and pin mode t clk : if the bit check fails, the average time period for that check depends on the selected baud-rate range and on t clk . the baud-rate range is defined by baud0 and baud1 in the opmode register. if the bit check is ok, t bit-check depends on the number of bits to be checked (n bit-check ) and on the utilized data rate. depends on the result of the bit check. x bit-check : extension factor defined by x sleeptemp according to table 5-7 x sleep : off command yes no enable ic data dem_out bit check receiving mode polling mode (number of checked bits: 3) bit check ok 1/2 bit 1/2 bit 1/2 bit 1/2 bit 1/2 bit 1/2 bit
13 4901b?rke?11/07 ata3745 5.3 bit check mode in bit check mode, the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. this is done by subsequent time frame checks where the distances between 2 sign al edges are continuously compared to a programmable time window. the maximum count of this edge-to-edge test, before the receiver switches to receiving mode, is also programmable. 5.3.1 configuring the bit check assuming a modulation scheme that contains 2 edges per bit, two time frame checks verify one bit. this is valid for manchester, bi-phas e and most other modulation schemes. the max- imum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable n bitcheck in the opmode register. this implies 0, 6, 12 and 18 edge-to-edge checks respectively. if n bitcheck is set to a higher value, the receiver is less likely to switch to the receiving mode due to noise. in the presence of a valid transmitter signal, the bit check takes less time if n bitcheck is set to a lower value. in polling mode, the bit check time is not dependent on n bitcheck . figure 5-3 on page 12 shows an example where 3 bits are tested successfully and the data signal is trans- ferred to pin data. figure 5-4 shows that the time window for the bit check is defined by two separate time limits. if the edge-to-edge time t ee is in between the lo wer bit check limit t lim_min and the upper bit check limit t lim_max , the check will be continued. if t ee is smaller than t lim_min or t ee exceeds t lim_max , the bit check will be terminated and the receiver switches to sleep mode. figure 5-4. valid time window for bit check for best noise immunity it is recommended to use a low span between t lim_min and t lim_max . this is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. a ?11111...? or a ?10101...? sequence in manchester or bi-phase is a good choice in this regard. a good compromise between rece iver sensitivity and susceptibilit y to noise is a time window of 25% regarding the expected edge-to-edge time t ee . using preburst patterns that contain vari- ous edge-to-edge time periods, the bit check limits must be programmed according to the required span. the bit check limits are determined by means of the formulas below: t lim_min = lim_min t xclk t lim_max = (lim_max ? 1) t xclk lim_min and lim_max are defined by a 5-bit word each within the limit register. using the above formulas, lim_min and lim_max can be determined according to the required t lim_min , t lim_max and t xclk . the time resolution when defining t lim_min and t lim_max is t xclk . the minimum edge-to-edge time t ee (t data_l_min , t data_h_min ) is defined in section ?receiving mode? on page 15 . due to this, the lower limit should be set to lim_min 10. the maximum value of the upper limit is lim_max = 63. 1/f sig t ee t lim_max t lim_min dem_out
14 4901b?rke?11/07 ata3745 figure 5-5 , figure 5-6 and figure 5-7 illustrate the bit check for the default bit check limits lim_min = 14 and lim_max = 24. when the ic is enabled, the signal processing circuits are enabled during t startup . the output of the demodulator (dem_out) is undefined during that period. when the bit check becom es active, the bit check count er is clocked with the cycle t xclk . figure 5-5 shows how the bit check proceeds if th e bit-check counter value cv_lim is within the limits defined by lim_min and lim_max at the occurrence of a signal edge. in figure 5-7 , the bit check fails as the value cv_lim is lower than the limit lim_min. the bit check also fails if cv_lim reaches lim_max. this is illustrated in figure 5-8 on page 15 . figure 5-5. timing diagram during bit check figure 5-6. timing diagram for failed bit check (condition: cv_lim < lim_min) figure 5-7. timing diagram for failed bit check (condition: cv_lim lim_max) enable ic bit check counter dem_out bit check (lim_min = 14, lim_max = 24) bit check ok bit check ok 78 56 3 4 12 34 15 13 14 1112 910 12 78 56 34 1718 15 16 13 14 1112 910 12 78 56 34 12 0 1/2 bit 1/2 bit 1/2 bit t startup t xclk enable ic bit check counter dem_out bit check sleep mode 0 startup mode (lim_min = 14, lim_max = 24) bit check failed (cv_lim_ < lim_min) 8 67 4 5 1112 910 23 1 56 34 12 0 1/2 bit bit check mode enable ic bit check counter dem_out bit check sleep mode 0 start up mode (lim_min = 14, lim_max = 24) bit check failed (cv_lim_ lim_max) 23 24 21 22 19 20 8 67 4 5 17 18 15 16 13 14 1112 910 23 71 56 34 12 0 1/2 bit bit check mode
15 4901b?rke?11/07 ata3745 5.3.2 duration of the bit check if no transmitter signal is present during the bi t check, the output of the demodulator delivers random signals. the bit check is a statistical process and t bitcheck varies for each check. therefore, an average value for t bitcheck is given in the section ?electrical characteristics? on page 23 . t bitcheck depends on the selected baud rate range and on t clk . a higher baud rate range causes a lower value for t bitcheck resulting in lower current consumption in polling mode. in the presence of a valid transmitter signal, t bitcheck is dependant on the frequency of that sig- nal, f sig and the count of the checked bits, n bitcheck . a higher value for n bitcheck thereby results in a longer period for t bitcheck requiring a higher value for the transmitter preburst t preburst . 5.4 receiving mode if the bit check has been successful for all bits specified by n bitcheck , the receiver switches to receiving mode. as seen in figure 5-4 on page 13 , the internal data signal is switched to pin data in that case. a connected microcontroller can be woken up by the negative edge at pin data. the receiver stays in that condition until it is switched back to polling mode explicitly. 5.4.1 digital signal processing the data from the demodulator (dem_out) is di gitally processed in different ways and as a result converted into the output signal data. this processing depends on the selected baud rate range (br_range). figure 5-8 illustrates how dem_out is sy nchronized by the extended clock cycle t xclk . this clock is also used for the bit check counter. data can change its state only after t xclk elapsed. the edge-to-edge time period t ee of the data signal, as a result, is always an integral multiple of t xclk . the minimum time period between two edges of the data signal is limited to t ee t data_min . this implies an efficient suppression of spikes at the data output. at the same time, it limits the maximum frequency of edges at data. this eases the interrupt handling of a connected microcontroller. t data_min is to some extent affected by the preceding edge-to-edge time inter- val t ee as illustrated in figure 5-9 on page 16 . if t ee is in between the specified bit check limits, the following level is frozen for the time period t data_min = tmin1; if t ee is outside the bit check limits, t data_min = tmin2 is the relevant stable time period. the maximum time period for data to be low is limited to t data_l_max . this function ensures a finite response time during programming or switching off the receiver via pin data. t data_l_max is thereby longer than the maximum time period indicated by the transmitter data stream. figure 5-10 on page 16 gives an example where dem_out remains low after the receiver has switched to receiving mode. figure 5-8. synchronization of the demodulator output data clock bit check counter dem_out t xclk t ee
16 4901b?rke?11/07 ata3745 figure 5-9. debouncing of the demodulator output figure 5-10. steady l state limited data output pattern after transmission after the end of a data transmission, the receiver remains active and random noise pulses appear at pin data. the edge-to-edge time period t ee of the majority of these noise pulses is equal to or slightly higher than t data_min . 5.4.2 switching the receiver back to sleep mode the receiver can be set back to polli ng mode via pin data or via pin enable. when using pin data, this pin must be pulled to low for the period t1 by the connected micro- controller. figure 5-11 on page 17 illustrates the timing of the off command (see also figure 5-15 on page 22 ). the minimum value of t1 depends on the br_range. the maximum value for t1 is not limited, but it is recommended not to exceed the specified value to prevent erasing the reset marker. this item is explained in more detail in ?configuration of the receiver? on page 18 . setting the receiver to sleep mode via data is achieved by programming bit 1 of the opmode register to ?1?. only one synchronous pulse (t3) is issued. the duration of the off command is determined by the sum of t1, t2 and t10. after the off command, the sleep time t sleep elapses. note that the capacitive load at pin data is limited. the resulting time constant t together with an optional external pull-up resistor should not be exceeded, to ensure proper operation. if the receiver is set to polling mode via pin enable, an "l" pulse (t doze ) must be issued at that pin. figure 5-12 on page 17 illustrates the timing of that command. after the positive edge of this pulse, the sleep time t sleep elapses. the receiver remains in sleep mode as long as enable is held to "l". if the receiver is polled exclusively by a microcontroller, t sleep can be programmed to ?0? to enable an instantaneous response time. this command is the faster option than via pin data, at the cost of an additional connection to the microcontroller. data dem_out lim_min cv_lim < lim_max t ee t ee t min1 cv_lim < lim_min or cv_lim lim_max t min2 enable ic data dem_out bit check t data_l_max receiving mode sleep mode bit-check mode t min2
17 4901b?rke?11/07 ata3745 figure 5-11. timing diagram of the off command via pin data figure 5-12. timing diagram of the off command via pin enable serial bi-directional data line out1 (microcontroller) data (ata3745) t sleep t7 t10 bit 1 ("1") (start bit) off command x x receiving mode start-up mode t 1 t 2 t 5 t 4 t 3 x x enable serial bi-directional data line data (ata3745) t off t doze t sleep startup mode receiving mode x x x x
18 4901b?rke?11/07 ata3745 5.5 configuration of the receiver the ata3745 receiver is configured via two 12-bit ram registers called opmode and limit. the registers can be programmed by means of the bi-directional data port. if the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (rm). the receiver must be reprogrammed in that case. after a power-on reset (por), the registers are set to default mode. if the receiver is operated in default mode, there is no need to program the registers. table 5-2 shows the structure of the registers. table 5-1 shows the effect of bit 1 and bit 2 in programming the registers: bit 1 defines if the receiver is set back to polling mode via the off command (see ?receiving mode? on page 15 ), or if it is programmed. bit 2 represents the reg- ister address. it selects the appropriate register to be programmed. table 5-3 on page 19 and the following illustrate the effect of the individual configuration words. the default configuration is highlighted for each word. br_range sets the appropriate baud rate range. at the same time it defines xlim. xlim is used to define the bit check limits t lim_min and t lim_max as shown in table 5-3 on page 19 . pout can be used to control the sensitivity of th e receiver. in that app lication, pout is set to ?1? to reduce the sensitivity. this implies that t he receiver operates with full sensitivity after a por. table 5-1. effect of bit 1 and bit 2 in programming the registers bit 1 bit 2 action 1 x the receiver is set back to polling mode (off command) 0 1 the opmode register is programmed 0 0 the limit register is programmed table 5-2. effect of the configuration words within the registers bit1 bit2 bit2 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit12 bit13 bit14 off command 1 opmode register 0 1 br_range n bitcheck v pout sleep x sleep 0 1 baud1 baud0 bitchk1 bitchk0 pout sleep4 sleep3 sleep2 sleep1 sleep0 x sleep std x sleep temp (default)001000 1 0110 0 limit register 0 0 lim_min lim_max 0 0 lim_min5 lim_min4 lim_min3 lim_min2 lim_min1 lim_min0 lim_max5 lim_max4 lim_max3 lim_max2 lim_max1 lim_max0 (default)001110 0 1100 0
19 4901b?rke?11/07 ata3745 table 5-3. effect of the configuration word br_range br_range baud rate range/extension factor for bit check limits (xlim) baud1 baud0 00 br_range0 (application usa/europe: br_range0 = 1.0 kbaud to 1.8 kbaud) (default) xlim = 8 (default) 01 br_range1 (application usa/europe: br _range1 = 1.8 kbaud to 3.2 kbaud) xlim = 4 10 br_range2 (application usa/europe: br _range2 = 3.2 kbaud to 5.6 kbaud) xlim = 2 11 br_range3 (application usa/europe: br_range3 = 5.6 kbaud to 10 kbaud) xlim = 1 table 5-4. effect of the configuration word n bitcheck n bitcheck number of bits to be checked bitchk1 bitchk0 00 0 01 3 1 0 6 (default) 11 9 table 5-5. effect of the configuration bit vpout vpout level of the multi-purpose output port pout pout 0 0 (default) 11 table 5-6. effect of the configuration word sleep sleep start value for sleep counter (t sleep = sleep x sleep 1024 t clk ) sleep4 sleep3 sleep 2 sleep1 sleep0 0 0 0 0 0 0 (receiver is continuously polling until a valid signal occurs) 00001 1 (t sleep 2 ms for x sleep = 1 in us/european applications) 00010 2 00011 3 . . . . . . . . . . . . . . . . . . 01011 11 (usa: t sleep = 22.96 ms, europe: t sleep = 23.31 ms) (default) . . . . . . . . . . . . . . . . . . 11101 29 11110 30 1 1 1 1 1 31 (permanent sleep mode)
20 4901b?rke?11/07 ata3745 table 5-7. effect of the configuration word x sleep x sleep extension factor for sleep time (t sleep = sleep x sleep 1024 t clk ) x sleepstd x sleeptemp 0 0 1 (default) 01 8 (x sleep is reset to 1 if bit check fails once) 10 8 (x sleep is set permanently) 11 8 (x sleep is set permanently) table 5-8. effect of the configuration word lim_min lim_min lower limit value for bit check lim_min < 10 is not applicable (t lim_min = lim_min xlim t clk ) 001010 10 001011 11 001100 12 001101 13 001110 14 (default) (usa: t lim_min = 228 s, europe: t lim_min = 232 s) . . . . . . . . . . . . . . . . . . . . . 111101 61 111110 62 111111 63 table 5-9. effect of the configuration word lim_max lim_max upper limit value for bit check lim_max < 12 is not applicable (t lim_max = (lim_max ? 1) xlim t clk ) 001100 12 001101 13 001110 14 . . . . . . . . . . . . . . . . . . . . . 011000 24 (default) (usa: t lim_max = 375 s, europe: t lim_max = 381 s) . . . . . . . . . . . . . . . . . . . . . 111101 61 111110 62 111111 63
21 4901b?rke?11/07 ata3745 5.5.1 conservation of the register information the ata3745 has integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the ram register information. according to figure 5-13 , a power-on reset (por) is generated if the supply voltage v s drops below the threshold voltage v threset . the default parameters are programmed into the config- uration registers in that condition. once v s exceeds v threset , the por is canceled after the minimum reset period t rst . a por is also generated when the supply voltage of the receiver is turned on. to indicate that condition, the receiver displays a reset marker (rm) at pin data after a reset. the rm is represented by the fixed frequency f rm at a 50% duty cycle. rm can be canceled via an "l" pulse t1 at pin data. the rm implies the follo wing characteristics: f rm is lower than the lowest feasible frequency of a data signal. by this means, rm cannot be misinterpreted by the connected microcontroller. if the receiver is set back to polling mode vi a pin data, rm cannot be canceled by accident if t1 is applied accord ing to the proposal in ?programming the configuration register? on page 22 . by means of that mechanism, the receiver cannot lose its register information without commu- nicating that condition via the reset marker rm. figure 5-13. generation of the power-on reset figure 5-14. timing of the register programming por data (ata3745) x t rst v threset v s 1/f rm serial bi-directional data line out1 (microcontroller) data (ata3745) bit 2 ("1") (register select) bit 13 ("0") (poll 8) bit 14 ("1") (poll 8r) bit 1 ("0") (start bit) programming frame x x start-up mode receiving mode t 1 t 2 t 5 t sleep t 9 t 8 t 7 t 6 t 4 t 3 x x
22 4901b?rke?11/07 ata3745 5.5.2 programming the c onfiguration register the configuration registers are programmed serially via the bi-directional data line according to figure 5-14 on page 21 and figure 5-15 . figure 5-15. one-wire connection to a microcontroller to start programming, the serial data line data is pulled by the microcontroller to ?l? for the time period t1. when data has been released, the receiver becomes the master device. when the programming delay period t2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t3. after each of these pulses, a programming window occurs. the delay until the program window starts is dete rmined by t4, the duration is defined by t5. within the programming window, the individual bi ts are set. if the microcontroller pulls down pin data for the time period t7 during t5, the corresponding bit is set to ?0?. if no programming pulse t7 is issued, this bit is set to ?1?. all 14 bits are subsequently programmed in this way. the time frame to program a bit is defined by t6. bit 14 is followed by the equivalent time window t9. during this window, the equivalent acknowledge pulse t8 (e_ack) occurs if the mode word just programmed is equivalent to the mode word that was already stored in that register. e_ack should be used to verify that the mode word was correctly transferred to the register. the register must be programmed twice in that case. programming of a register is possible both during sleep and active mode of the receiver. dur- ing programming, the lna, lo, low-pass filter, if amplifier and the demodulator are disabled. the programming start pulse t1 initiates the programming of the configuration registers. if bit 1 is set to ?1?, it represents the off command, setting the receiver back to polling mode at the same time. for the length of the programming start pulse t1, the following convention should be considered: t1(min) < t1 < 1535 t clk : [t1(min) is the minimum specified value for the relevant br_range] programming (or the off command) is initiated if the receiver is not in reset mode. if the receiver is in reset mode, programming (or the off command) is not initiated, and the reset marker rm is still present at pin data. this peri od is generally used to switch the receiver to polling mode. in a reset condition, rm is not canceled by accident. t1 > 5632 t clk programming (or the off command) is initiated in any case. rm is cancelled if present. this period is used if the connected microcontroller detected rm. if a configuration register is pro- grammed, this time period for t1 can generally be used. note that the capacitive load at pin data is limited. the resulting time constant t together with an optional external pull-up resistor may not be exceeded to ensure proper operation. bi-directional data line internal pull-up resistor data (ata3745) data i / o ata3745 out1 (microcontroller) microcontroller
23 4901b?rke?11/07 ata3745 6. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min. max. unit supply voltage v s 6v power dissipation p tot 450 mw junction temperature t j 150 c storage temperature t stg ?55 +125 c ambient temperature t amb ?40 +85 c maximum input level, input matched to 50 ? p in_max 10 dbm 7. thermal resistance parameters symbol value unit junction ambient r thja 100 k/w 8. electrical characteristics all parameters refer to gnd, v s = 5v, t amb = 25c, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. the possible operating range refer to different circuit conditions: v s = 4.5v to 5.5v, t amb = ?40c to +85c parameters test conditions symbol min. typ. max. unit current consumption sleep mode (xto and polling logic active) is off 190 350 a ic active (startup, bit check, or receiving mode) pin data = h is on 7.0 8.6 ma lna mixer third-order intercept point lna/mixer/if amplifier input matched according to figure 3-3 on page 6 iip3 ?28 dbm lo spurious emission at rf in input matched according to figure 3-3 on page 6 , required according to i-ets 300220 is lorf ?73 ?57 dbm noise figure lna and mixer (dsb) input matching according to figure 3-3 on page 6 nf 7 db lna_in input impedance at 433.92 mhz at 315 mhz zi lna_in 1.0 || 1.56 1.3 || 1.0 k ? || pf k ? || pf 1 db compression point (lna, mixer, if amplifier) input matched according to figure 3-3 on page 6 , referred to rf in ip 1db ?40 dbm maximum input level input matched according to figure 3-3 on page 6 , ber 10 -3 , ask mode p in_max ?23 dbm
24 4901b?rke?11/07 ata3745 local oscillator operating frequency range vco f vco 309 439 mhz loop bandwidth of the pll for best lo noise (design parameter) r1 = 820 ? c9 = 4.7 nf c10 = 1 nf b loop 100 khz capacitive load at pin lf the capacitive load at pin lf is limited if bit check is used. the limitation therefore also applies to self polling. c lf_tot 10 nf xto operating frequency xto crystal frequency, appropriate load capacitance must be connected to xtal 6.764375 mhz 4.90625 mhz f xto 6.764375 ?50 ppm 4.90625 ?50 ppm 6.764375 4.90625 6.764375 +50 ppm 4.90625 +50 ppm mhz mhz series resonance resistor of the crystal f xto = 6.764 mhz 4.906 mhz r s 150 220 ? ? static capacitance at pin xt0 c xt0 6.5 pf analog signal processing input sensitivity ask 600-khz if filter input matched according to figure 5-1 ask (level of carrier) ber 10 -3 , b = 600 khz f in = 433.92 mhz/315 mhz t = 25 c, v s = 5v f if = 1 mhz p ref_ask br_range0 ?106 ?110 ?113.5 dbm br_range1 ?104.5 ?108.5 ?112 dbm br_range2 ?104 ?108 ?111.5 dbm br_range3 ?102 ?106 ?109.5 dbm sensitivity variation ask for full operating range including if filter compared to t amb =25 c, v s = 5v 600-khz version f in = 433.92 mhz/315 mhz f if = 0.81 mhz to 1.19 mhz f if = 0.75 mhz to 1.25 mhz p ask = p ref_ask + ? p ref ? p ref +3 +5 db db snr to suppress in-band noise signals ask mode snr ask 11 db dynamic range rssi ampl. ? r rssi 60 db lower cut-off frequency of the data filter cdem = 33 nf f cu_df 0.11 0.16 0.20 khz 8. electrical characteristics (continued) all parameters refer to gnd, v s = 5v, t amb = 25c, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. the possible operating range refer to different circuit conditions: v s = 4.5v to 5.5v, t amb = ?40c to +85c parameters test conditions symbol min. typ. max. unit f cu_df 1 2 30k ? cdem ----------------------------------------------------------- =
25 4901b?rke?11/07 ata3745 recommended cdem for best performance ask mode br_range0 (default) br_range1 br_range2 br_range3 cdem 39 22 12 8.2 nf nf nf nf maximum edge-to-edge time period of the input data signal fo r full sensitivity br_range0 (default) br_range1 br_range2 br_range3 t ee_sig 1000 560 320 180 s s s s minimum edge-to-edge time period of the input data signal fo r full sensitivity br_range0 (default) br_range1 br_range2 br_range3 t ee_sig 270 156 89 50 s s s s threshold voltage for reset v threset 1.95 2.8 3.75 v digital ports data output - saturation voltage low - internal pull-up resistor - maximum time constant - maximum capacitive load i ol = 1 ma = c l (r pup //r ext ) without external pull-up resistor r ext = 5 k ? v oi r pup c l c l 39 0.08 50 0.3 61 2.5 41 540 v k ? s pf pf pout output - saturation voltage low - saturation voltage high i pout = 1 ma i pout = ?1 ma v ol v oh v s ?0.3v 0.08 v s ? 0.14v 0.3 v v ask input - high-level input voltage ask v ih 0.8 v s v enable input - low-level input voltage - high-level input voltage idle mode active mode v il v ih 0.8 v s 0.2 v s v v mode input - low-level input voltage - high-level input voltage division factor = 10 division factor = 14 v il v ih 0.8 v s 0.2 v s v v test input - low-level input voltage test input must always be set to low v il 0.2 v s v 8. electrical characteristics (continued) all parameters refer to gnd, v s = 5v, t amb = 25c, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. the possible operating range refer to different circuit conditions: v s = 4.5v to 5.5v, t amb = ?40c to +85c parameters test conditions symbol min. typ. max. unit
26 4901b?rke?11/07 ata3745 9. electrical characteristics all parameters refer to gnd, v s = 5v, t amb = 25c, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. the possible operating range refer to different circuit conditions: v s = 4.5v to 5.5v, t amb = ?40c to +85c parameter test condition symbol 6.76438-mhz oscillator (mode 1) 4.90625-mhz oscillator (mode 0) variable oscillator unit min. typ. max. min. typ. max. min. typ. max. basic clock cycle of the digital circuitry basic clock cycle mode = 0 (usa) mode = 1 (europe) t clk 2.0697 2.0383 1 / (f xto /10) 1/(f xto /14) s s extended basic clock cycle br_range0 br_range1 br_range2 br_range3 t xclk 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 8 t clk 4 t clk 2 t clk 1 t clk s s s s polling mode sleep time sleep and x sleep are defined in the opmode register t sleep sleep x sleep 1024 2.0697 sleep x sleep 1024 2.0383 sleep x sleep 1024 t clk ms start-up time br_range0 br_range1 br_range2 br_range3 t startup 1855 1061 1061 663 1827 1045 1045 653 896.5 512.5 512.5 320.5 t clk s s s s time for bit check average bit check time while polling br_range0 br_range1 br_range2 br_range3 t bitcheck 0.45 0.24 0.14 0.14 0.47 0.26 0.16 0.15 ms ms ms ms bit check time for a valid input signal f sig n bitcheck = 0 n bitcheck = 3 n bitcheck = 6 n bitcheck = 9 t bitcheck 3/f sig 6/f sig 9/f sig 3.5 / f sig 6.5 / f sig 9.5 / f sig 3/f sig 6/f sig 9/f sig 3.5 / f sig 6.5 / f sig 9.5 / f sig t xclk 3.5 / f sig 6.5 / f sig 9.5 / f sig ms ms ms ms receiving mode intermediate frequency mode = 0 (usa) mode = 1 (europe) f if 1.0 1.0 f xto 64 / 314 f xto 64 / 432.92 mhz mhz baud rate range br_range0 br_range1 br_range2 br_range3 br_range 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 br_range0 2 ms / t clk br_range1 2 ms / t clk br_range2 2 ms / t clk br_range3 2 ms / t clk kbaud kbaud kbaud kbaud minimum time period between edges at pin data ( figure 5-9 on page 16 ) br_range0 br_range1 br_range2 br_range3 t data_min tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 149 182 75 91 37.3 45.5 18.6 22.8 147 179 73 90 36.7 44.8 18.3 22.4 9 t xclk 11 t xcl 9 t xclk 11 t xclk 9 t xclk 11 t xclk 9 t xclk 11 t xclk s s s s s s s s maximum low period at data ( figure 5-10 on page 16 ) br_range0 br_range1 br_range2 br_range3 t data_l_max 2169 1085 542 271 2136 1068 534 267 131 t xclk 131 t xclk 131 t xclk 131 t xclk s s s s
27 4901b?rke?11/07 ata3745 off command at pin enable ( figure 5-12 on page 17 ) t doze 3.1 3.05 1.5 t clk s configuration of the receiver frequency of the reset marker ( figure 5-13 on page 21 ) f rm 117.9 119.8 hz programming start pulse ( figure 5-11 on page 17 , figure 5-14 on page 21 ) br_range0 br_range1 br_range2 br_range3 after por t1 2188 1104 561 290 11656 3176 3176 3176 3176 2155 1087 553 286 11479 3128 3128 3128 3128 1057 t clk 533 t clk 271 t clk 140 t clk 5632 t clk 1535 t clk 1535 t clk 1535 t clk 1535 t clk s programming delay period ( figure 5-11 on page 17 , figure 5-14 on page 21 ) t2 795 798 783 786 384.5 t clk 385.5 t clk s synchron- ization pulse ( figure 5-11 on page 17 , figure 5-14 on page 21 ) t3 265 261 128 t clk s delay until the program window starts ( figure 5-11 on page 17 , figure 5-14 on page 21 ) t4 131 129 63.5 t clk s programming window ( figure 5-11 on page 17 , figure 5-14 on page 21 ) t5 530 522 256 t clk s time frame of a bit ( figure 5-14 on page 21 ) t6 1060 1044 512 t clk s 9. electrical characteristics all parameters refer to gnd, v s = 5v, t amb = 25c, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. the possible operating range refer to different circuit conditions: v s = 4.5v to 5.5v, t amb = ?40c to +85c parameter test condition symbol 6.76438-mhz oscillator (mode 1) 4.90625-mhz oscillator (mode 0) variable oscillator unit min. typ. max. min. typ. max. min. typ. max. 1 4096 t clk ---------------------------------
28 4901b?rke?11/07 ata3745 programming pulse ( figure 5-11 on page 17 , figure 5-14 on page 21 ) t7 133 529 131 521 64 t clk 256 t clk s equivalent acknowledge pulse: e_ack ( figure 5-14 on page 21 ) t8 265 261 128 t clk s equivalent time window ( figure 5-14 on page 21 ) t9 534 526 258 t clk s off bit programming window ( figure 5-11 on page 17 ) t10 930 916 449.5 t clk s 9. electrical characteristics all parameters refer to gnd, v s = 5v, t amb = 25c, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. the possible operating range refer to different circuit conditions: v s = 4.5v to 5.5v, t amb = ?40c to +85c parameter test condition symbol 6.76438-mhz oscillator (mode 1) 4.90625-mhz oscillator (mode 0) variable oscillator unit min. typ. max. min. typ. max. min. typ. max.
29 4901b?rke?11/07 ata3745 11. package information 12. revision history 10. ordering information extended type number package remarks ata3745p3-tgqy so20 taped and reeled, pb-free technical drawings according to din specifications package so20 dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 20 11 110 please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4901b-rke-11/07 ? put datasheet in the newest template
4901b?rke?11/07 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en-yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support auto_control@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2007 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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