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? 2000 microchip technology inc. advance information ds30325a-page 1 pic16f7x devices included in this data sheet: microcontroller core features: ? high-performance risc cpu only 35 single word instructions to learn all single cycle instructions except for program branches which are two cycle operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle up to 8k x 14 words of flash program memory, up to 368 x 8 bytes of data memory (ram) pinout compatible to the pic16c73b/74b/76/77 pinout compatible to the pic16f873/874/876/877 interrupt capability (up to 12 sources) eight level deep hardware stack direct, indirect and relative addressing modes power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code protection power saving sleep mode selectable oscillator options low power, high speed cmos flash technology fully static design in-circuit serial programming ? (icsp) via two pins processor read access to program memory wide operating voltage range: 2.0v to 5.5v high sink/source current: 25 ma industrial temperature range low power consumption: - < 2 ma typical @ 5v, 4 mhz -20 a typical @ 3v, 32 khz -< 1 a typical standby current pin diagram peripheral features: timer0: 8-bit timer/counter with 8-bit prescaler timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler two capture, compare, pwm modules - capture is 16-bit, max. resolution is 12.5 ns - compare is 16-bit, max. resolution is 200 ns - pwm max. resolution is 10-bit 8-bit multi-channel analog-to-digital converter synchronous serial port (ssp) with spi ? (master mode) and i 2 c ? (slave) universal synchronous asynchronous receiver transmitter (usart/sci) parallel slave port (psp) 8-bits wide, with external rd , wr and cs controls (40/44-pin only) brown-out detection circuitry for brown-out reset (bor) pic16f73 pic16f74 pic16f76 pic16f77 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/an4/ss re0/rd /an5 re1/wr /an6 re2/cs /an7 v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic16f77/74 pdip 28/40-pin 8-bit cmos flash microcontrollers
pic16f7x ds30325a-page 2 advance information ? 2000 microchip technology inc. pin diagrams pic16f76/73 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/an4/ss v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 44 8 7 6 5 4 3 2 1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 pic16f77 ra4/t0cki ra5/an4/ss re0/rd /an5 osc1/clkin osc2/clkout rc0/t1oso/t1ck1 nc re1/wr /an6 re2/cs /an7 v dd v ss rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr /v pp nc rb7 rb6 rb5 rb4 nc nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic16f77 37 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr /v pp nc rb7 rb6 rb5 rb4 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 nc nc rc0/t1oso/t1cki osc2/clkout osc1/clkin v ss v dd re2/an7/cs re1/an6/wr re0/an5/rd ra5/an4/ss ra4/t0cki rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3 plcc qfp dip, soic, ssop pic16f74 pic16f74
? 2000 microchip technology inc. advance information ds30325a-page 3 pic16f7x key features picmicro? mid-range reference manual (ds33023) pic16f73 pic16f74 pic16f76 pic16f77 operating frequency dc - 20 mhz dc - 20 mhz dc - 20 mhz dc - 20 mhz resets (and delays) por, bor (pwrt, ost) por, bor (pwrt, ost) por, bor (pwrt, ost) por, bor (pwrt, ost) flash program memory (14-bit words, 100 e/w cycles) 4k 4k 8k 8k data memory (bytes) 192 192 368 368 interrupts 11 12 11 12 i/o ports ports a,b,c ports a,b,c,d,e ports a,b,c ports a,b,c,d,e timers 3333 capture/compare/pwm modules 2 2 2 2 serial communications ssp, usart ssp, usart ssp, usart ssp, usart parallel communications ? psp ? psp 8-bit analog-to-digital module 5 input channels 8 input channels 5 input channels 8 input channels instruction set 35 instructions 35 instructions 35 instructions 35 instructions
pic16f7x ds30325a-page 4 advance information ? 2000 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................... 5 2.0 memory organization ......................................................................................................... ......................................... 11 3.0 i/o ports................................................................................................................... .................................................... 29 4.0 reading program memory...................................................................................................... ..................................... 41 5.0 timer0 module ............................................................................................................... .............................................. 45 6.0 timer1 module ............................................................................................................... .............................................. 49 7.0 timer2 module ............................................................................................................... .............................................. 53 8.0 capture/compare/pwm modules ................................................................................................. ............................... 55 9.0 synchronous serial port (ssp) module........................................................................................ ............................... 61 10.0 universal synchronous asynchronous receiver transmitter (usart) ............................................................ .......... 73 11.0 analog-to-digital converter (a/d) module ................................................................................... ................................ 89 12.0 special features of the cpu ................................................................................................ ....................................... 95 13.0 instruction set summary .................................................................................................... ....................................... 111 14.0 development support ........................................................................................................ ........................................ 119 15.0 electrical characteristics ................................................................................................. .......................................... 125 16.0 dc and ac characteristics graphs and tables ................................................................................ ........................ 147 17.0 packaging information ...................................................................................................... ......................................... 149 appendix a: revision history .................................................................................................... ..................................................... 157 appendix b: device differences.................................................................................................. ................................................... 157 appendix c: conversion considerations .......................................................................................... ............................................. 157 index .......................................................................................................................... ........................................................................ 159 on-line support................................................................................................................ ................................................................. 165 reader response ................................................................................................................ .............................................................. 166 pic16f7x product identification system ......................................................................................... .................................................. 167 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro - chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be re fined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 786- 7578. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchip ? s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) the microchip corporate literature center; u.s. fax: (480) 786-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de lit- erature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
? 2000 microchip technology inc. advance information ds30325a-page 5 pic16f7x 1.0 device overview this document contains device specific information. additional information may be found in the picmicro ? mid-range reference manual (ds33023), which may be obtained from your local microchip sales represen- tative or downloaded from the microchip web site. the reference manual should be considered a comple- mentary document to this data sheet, and is highly rec- ommended reading for a better understanding of the device architecture and operation of the peripheral modules. there are four devices (pic16f73, pic16f74, pic16f76 and pic16f77) covered by this data sheet. the pic16f76/73 devices are available in 28-pin pack- ages and the pic16f77/74 devices are available in 40-pin packages. the 28-pin devices do not have a parallel slave port implemented. the following two figures are device block diagrams sorted by pin number; 28-pin for figure 1-1 and 40-pin for figure 1-2. the 28-pin and 40-pin pinouts are listed in table 1-1 and table 1-2, respectively. figure 1-1: pic16f73 and pic16f76 block diagram flash program memory 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss porta portb portc ra4/t0cki ra5/an4/ss rb0/int rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt 8 8 brown-out reset note 1: higher order bits are from the status register. usart ccp1,2 synchronous 8-bit a/d timer0 timer1 timer2 serial port ra3/an3/v ref ra2/an2/ ra1/an1 ra0/an0 8 3 rb1 rb2 rb3/pgm rb4 rb5 rb6/pgc rb7/pgd device program flash data memory pic16f73 4k 192 bytes pic16f76 8k 368 bytes
pic16f7x ds30325a-page 6 advance information ? 2000 microchip technology inc. figure 1-2: pic16f74 and pic16f77 block diagram flash program memory 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss porta portb portc portd porte ra4/t0cki ra5/an4/ss rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt re0/an5/rd re1/an6/wr re2/an7/cs 8 8 brown-out reset note 1: higher order bits are from the status register. usart ccp1,2 synchronous 8-bit a/d timer0 timer1 timer2 serial port ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 parallel slave port 8 3 rb0/int rb1 rb2 rb3/pgm rb4 rb5 rb6/pgc rb7/pgd device program flash data memory pic16f74 4k 192 bytes pic16f77 8k 368 bytes rd0/psp0 rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7
? 2000 microchip technology inc. advance information ds30325a-page 7 pic16f7x table 1-1: pic16f73 and pic16f76 pinout description pin name dip pin# ssop soic pin# i/o/p type buffer type description osc1/clkin 9 9 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clkout 10 10 o ? oscillator crystal output. connects to crystal or resonator in crys- tal oscillator mode. in rc mode, the osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 1 i/p st master clear (reset) input or programming voltage input or high voltage test mode control. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 2 2 i/o ttl ra0 can also be analog input0. ra1/an1 3 3 i/o ttl ra1 can also be analog input1. ra2/an2 4 4 i/o ttl ra2 can also be analog input2. ra3/an3/v ref 5 5 i/o ttl ra3 can also be analog input3 or analog reference voltage. ra4/t0cki 6 6 i/o st ra4 can also be the clock input to the timer0 module. output is open drain type. ra5/ss/ an4 7 7 i/o ttl ra5 can also be analog input4 or the slave select for the synchronous serial port. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 21 21 i/o ttl/st (1) rb0 can also be the external interrupt pin. rb1 22 22 i/o ttl rb2 23 23 i/o ttl rb3 24 24 i/o ttl rb4 25 25 i/o ttl interrupt-on-change pin. rb5 26 26 i/o ttl interrupt-on-change pin. rb6 27 27 i/o ttl/st (2) interrupt-on-change pin or serial programming clock. rb7 28 28 i/o ttl/st (2) interrupt-on-change pin or serial programming data. portc is a bi-directional i/o port. rc0/t1oso/t1cki 11 11 i/o st rc0 can also be the timer1 oscillator output or timer1 clock input. rc1/t1osi/ccp2 12 12 i/o st rc1 can also be the timer1 oscillator input or capture2 input/ compare2 output/pwm2 output. rc2/ccp1 13 13 i/o st rc2 can also be the capture1 input/compare1 output/pwm1 output. rc3/sck/scl 14 14 i/o st rc3 can also be the synchronous serial clock input/output for both spi and i 2 c modes. rc4/sdi/sda 15 15 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 16 16 i/o st rc5 can also be the spi data out (spi mode). rc6/tx/ck 17 17 i/o st rc6 can also be the usart asynchronous transmit or synchronous clock. rc7/rx/dt 18 18 i/o st rc7 can also be the usart asynchronous receive or synchronous data. v ss 8, 19 8, 19 p ? ground reference for logic and i/o pins. v dd 20 20 p ? positive supply for logic and i/o pins. legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured in rc oscillator mode and a cmos input otherwise.
pic16f7x ds30325a-page 8 advance information ? 2000 microchip technology inc. table 1-2: pic16f74 and pic16f77 pinout description pin name dip pin# plcc pin# qfp pin# i/o/p type buffer type description osc1/clkin 13 14 30 i st/cmos (4) oscillator crystal input/external clock source input. osc2/clkout 14 15 31 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 2 18 i/p st master clear (reset) input or programming voltage input or high voltage test mode control. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 2 3 19 i/o ttl ra0 can also be analog input0. ra1/an1 3 4 20 i/o ttl ra1 can also be analog input1. ra2/an2 4 5 21 i/o ttl ra2 can also be analog input2. ra3/an3/v ref 5 6 22 i/o ttl ra3 can also be analog input3 or analog reference voltage. ra4/t0cki 6 7 23 i/o st ra4 can also be the clock input to the timer0 timer/ counter. output is open drain type. ra5/ss/ an4 7 8 24 i/o ttl ra5 can also be analog input4 or the slave select for the synchronous serial port. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 33 36 8 i/o ttl/st (1) rb0 can also be the external interrupt pin. rb1 34 37 9 i/o ttl rb2 35 38 10 i/o ttl rb3 36 39 11 i/o ttl rb4 37 41 14 i/o ttl interrupt-on-change pin. rb5 38 42 15 i/o ttl interrupt-on-change pin. rb6 39 43 16 i/o ttl/st (2) interrupt-on-change pin or serial programming clock. rb7 40 44 17 i/o ttl/st (2) interrupt-on-change pin or serial programming data. portc is a bi-directional i/o port. rc0/t1oso/t1cki 15 16 32 i/o st rc0 can also be the timer1 oscillator output or a timer1 clock input. rc1/t1osi/ccp2 16 18 35 i/o st rc1 can also be the timer1 oscillator input or capture2 input/compare2 output/pwm2 output. rc2/ccp1 17 19 36 i/o st rc2 can also be the capture1 input/compare1 output/ pwm1 output. rc3/sck/scl 18 20 37 i/o st rc3 can also be the synchronous serial clock input/output for both spi and i 2 c modes. rc4/sdi/sda 23 25 42 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 24 26 43 i/o st rc5 can also be the spi data out (spi mode). rc6/tx/ck 25 27 44 i/o st rc6 can also be the usart asynchronous transmit or synchronous clock. rc7/rx/dt 26 29 1 i/o st rc7 can also be the usart asynchronous receive or synchronous data. legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as an external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when configured in rc oscillator mode and a cmos input otherwise.
? 2000 microchip technology inc. advance information ds30325a-page 9 pic16f7x portd is a bi-directional i/o port or parallel slave port when interfacing to a microprocessor bus. rd0/psp0 19 21 38 i/o st/ttl (3) rd1/psp1 20 22 39 i/o st/ttl (3) rd2/psp2 21 23 40 i/o st/ttl (3) rd3/psp3 22 24 41 i/o st/ttl (3) rd4/psp4 27 30 2 i/o st/ttl (3) rd5/psp5 28 31 3 i/o st/ttl (3) rd6/psp6 29 32 4 i/o st/ttl (3) rd7/psp7 30 33 5 i/o st/ttl (3) porte is a bi-directional i/o port. re0/rd /an5 8925i/o st/ttl (3) re0 can also be read control for the parallel slave port, or analog input5. re1/wr /an6 91026i/o st/ttl (3) re1 can also be write control for the parallel slave port, or analog input6. re2/cs /an7 10 11 27 i/o st/ttl (3) re2 can also be select control for the parallel slave port, or analog input7. v ss 12,31 13,34 6,29 p ? ground reference for logic and i/o pins. v dd 11,32 12,35 7,28 p ? positive supply for logic and i/o pins. nc ? 1,17,28, 40 12,13, 33,34 ? these pins are not internally connected. these pins should be left unconnected. table 1-2: pic16f74 and pic16f77 pinout description (continued) pin name dip pin# plcc pin# qfp pin# i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as an external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when configured in rc oscillator mode and a cmos input otherwise.
pic16f7x ds30325a-page 10 advance information ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. advance information ds30325a-page 11 pic16f7x 2.0 memory organization there are two memory blocks in each of these picmicro ? mcus. the program memory and data memory have separate buses so that concurrent access can occur and is detailed in this section. the program memory can be read internally by user code (see section 4.0). additional information on device memory may be found in the picmicro ? mid-range reference manual, (ds33023). 2.1 program memory organization the pic16f7x devices have a 13-bit program counter capable of addressing an 8k x 14 program memory space. the pic16f77/76 devices have 8k x 14 words of flash program memory and the pic16f73/74 devices have 4k x 14. accessing a location above the physically implemented address will cause a wrap- around. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 2-1: pic16f77/76 program memory map and stack figure 2-2: pic16f74/73 program memory map and stack pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw 1fffh stack level 2 program memory page 0 page 1 page 2 page 3 07ffh 0800h 0fffh 1000h 17ffh 1800h pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw 1fffh stack level 2 program memory page 0 page 1 07ffh 0800h 0fffh 1000h
pic16f7x ds30325a-page 12 advance information ? 2000 microchip technology inc. 2.2 data memory organization the data memory is partitioned into multiple banks, which contain the general purpose registers and the special function registers. bits rp1 (status<6>) and rp0 (status<5>) are the bank select bits. each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers, implemented as static ram. all implemented banks contain special function registers. some frequently used special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 general purpose register file the register file can be accessed either directly, or indi- rectly, through the file select register fsr. rp1:rp0 bank 00 0 01 1 10 2 11 3
? 2000 microchip technology inc. advance information ds30325a-page 13 pic16f7x figure 2-3: pic16f77/76 register file map indirect addr.(*) tmr0 pcl status fsr porta portb portc pclath intcon pir1 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con option_reg pcl status fsr trisa trisb trisc pclath intcon pie1 pcon pr2 sspstat 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 unimplemented data memory locations, read as ? 0 ? . * not a physical register. note 1: these registers are not implemented on 28-pin devices. file address indirect addr.(*) indirect addr.(*) pcl status fsr pclath intcon pcl status fsr pclath intcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 10ch 10dh 10eh 10fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11ah 11bh 11ch 11dh 11eh 11fh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh 18ch 18dh 18eh 18fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19ah 19bh 19ch 19dh 19eh 19fh 120h 1a0h 17fh 1ffh bank 2 bank 3 indirect addr.(*) portd (1) porte (1) trisd (1) trise (1) tmr0 option_reg pir2 pie2 rcsta txreg rcreg ccpr2l ccpr2h ccp2con adres adcon0 txsta spbrg adcon1 general purpose register general purpose register general purpose register general purpose register 1efh 1f0h accesses 70h - 7fh efh f0h accesses 70h-7fh 16fh 170h accesses 70h-7fh general purpose register general purpose register trisb portb 96 bytes 80 bytes 80 bytes 80 bytes 16 bytes 16 bytes pmdata pmadr pmcon1 pmdath pmadrh file address file address file address sspadd
pic16f7x ds30325a-page 14 advance information ? 2000 microchip technology inc. figure 2-4: pic16f74/73 register file map indirect addr.(*) tmr0 pcl status fsr porta portb portc pclath intcon pir1 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con option_reg pcl status fsr trisa trisb trisc pclath intcon pie1 pcon pr2 sspstat 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 file address indirect addr.(*) indirect addr.(*) pcl status fsr pclath intcon pcl status fsr pclath intcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh 17fh 1ffh bank 2 bank 3 indirect addr.(*) portd (1) porte (1) trisd (1) trise (1) tmr0 option_reg pir2 pie2 rcsta txreg rcreg ccpr2l ccpr2h ccp2con adres adcon0 txsta spbrg adcon1 general purpose register general purpose register 1efh 1f0h accesses a0h - ffh 16fh 170h accesses 20h-7fh trisb portb 96 bytes 96 bytes 10ch 10dh 10eh 10fh 110h 18ch 18dh 18eh 18fh 190h pmdata pmadr pmcon1 pmdath pmadrh unimplemented data memory locations, read as ? 0 ? . * not a physical register. note 1: these registers are not implemented on 28-pin devices. 120h 1a0h file address file address file address sspadd
? 2000 microchip technology inc. advance information ds30325a-page 15 pic16f7x 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in table 2-1. the special function registers can be classified into two sets: core (cpu) and peripheral. those registers associated with the core functions are described in detail in this section. those related to the operation of the peripheral features are described in detail in the peripheral feature section. table 2-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) bank 0 00h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 module ? s register xxxx xxxx uuuu uuuu 02h (4) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 03h (4) status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 04h (4) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta ? ? porta data latch when written: porta pins when read --0x 0000 --0u 0000 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h (5) portd portd data latch when written: portd pins when read xxxx xxxx uuuu uuuu 09h (5) porte ? ? ? ? ? re2 re1 re0 ---- -xxx ---- -uuu 0ah (1,4) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (4) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (3) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ? ccp2if ---- ---0 ---- ---0 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 module ? s register 0000 0000 0000 0000 12h t2con ? toutps3 toutps2 toutps toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit data register 0000 0000 0000 0000 1ah rcreg usart receive data register 0000 0000 0000 0000 1bh ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 1eh adres a/d result register byte xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/ done ? adon 0000 00-0 0000 00-0 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. shaded locations are unimplemented, read as ? 0 ? . note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the 28-pin devices; always maintain these bits clear. 4: these registers can be addressed from any bank. 5: portd, porte, trisd, and trise are not physically implemented on the 28-pin devices, read as ? 0 ? . 6: this bit always reads as a ? 1 ? .
pic16f7x ds30325a-page 16 advance information ? 2000 microchip technology inc. bank 1 80h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option_ reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (4) pcl program counter ? s (pc) least significant byte 0000 0000 0000 0000 83h (4) status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 84h (4) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa ? ? porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h (5) trisd portd data direction register 1111 1111 1111 1111 89h (5) trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 8ah (1,4) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh (4) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 pspie (3) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ? ccp2ie ---- ---0 ---- ---0 8eh pcon ? ? ? ? ? ? por bor ---- --qq ---- --uu 8fh ? unimplemented ? ? 90h ? unimplemented ? ? 91h ? unimplemented ? ? 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat smp cke d/a psr/w ua bf 0000 0000 0000 0000 95h ? unimplemented ? ? 96h ? unimplemented ? ? 97h ? unimplemented ? ? 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 9ah ? unimplemented ? ? 9bh ? unimplemented ? ? 9ch ? unimplemented ? ? 9dh ? unimplemented ? ? 9eh ? unimplemented ? ? 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. shaded locations are unimplemented, read as ? 0 ? . note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the 28-pin devices; always maintain these bits clear. 4: these registers can be addressed from any bank. 5: portd, porte, trisd, and trise are not physically implemented on the 28-pin devices, read as ? 0 ? . 6: this bit always reads as a ? 1 ? .
? 2000 microchip technology inc. advance information ds30325a-page 17 pic16f7x bank 2 100h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 101h tmr0 timer0 module ? s register xxxx xxxx uuuu uuuu 102h (4) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 103h (4) status irp rp1 rp0 to pd z dc c 0001 1xxx 000q quuu 104h (4) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 105h ? unimplemented ? ? 106h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 107h ? unimplemented ? ? 108h ? unimplemented ? ? 109h ? unimplemented ? ? 10ah (1,4) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 10bh (4) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 10ch pmdata data register low byte xxxx xxxx uuuu uuuu 10dh pmadr address register low byte xxxx xxxx uuuu uuuu 10eh pmdath ? ? data register high byte xxxx xxxx uuuu uuuu 10fh pmadrh ? ? ? address register high byte xxxx xxxx uuuu uuuu bank 3 180h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 181h option_ reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 182h (4) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 183h (4) status irp rp1 rp0 to pd z dc c 0001 1xxx 000q quuu 184h (4) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 185h ? unimplemented ? ? 186h trisb portb data direction register 1111 1111 1111 1111 187h ? unimplemented ? ? 188h ? unimplemented ? ? 189h ? unimplemented ? ? 18ah (1,4) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 18bh (4) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 18ch pmcon1 ? (6) ? ? ? ? ? ? rd 1--- ---0 1--- ---0 18dh ? unimplemented ? ? 18eh ? reserved maintain clear 0000 0000 0000 0000 18fh ? reserved maintain clear 0000 0000 0000 0000 table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. shaded locations are unimplemented, read as ? 0 ? . note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the 28-pin devices; always maintain these bits clear. 4: these registers can be addressed from any bank. 5: portd, porte, trisd, and trise are not physically implemented on the 28-pin devices, read as ? 0 ? . 6: this bit always reads as a ? 1 ? .
pic16f7x ds30325a-page 18 advance information ? 2000 microchip technology inc. 2.2.2.1 status register the status register contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc, or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable, therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect the z, c, or dc bits from the status register. for other instructions not affecting any status bits, see the "instruction set summary." register 2-1: status register (address 03h, 83h, 103h, 183h) note 1: the c and dc bits operate as a borrow and digit borrow bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdc c bit 7 bit 0 bit 7 irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) bit 6-5 rp1:rp0 : register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit ( addwf , addlw, sublw, subwf instructions) (for borrow the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0 c: carry/borrow bit ( addwf, addlw, sublw, subwf instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow , the polarity is reversed. a subtraction is executed by adding the two ? s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2000 microchip technology inc. advance information ds30325a-page 19 pic16f7x 2.2.2.2 option_reg register the option_reg register is a readable and writable register, which contains various control bits to configure the tmr0 prescaler/wdt postscaler (single assign- able register known also as the prescaler), the external int interrupt, tmr0 and the weak pull-ups on portb. register 2-2: option_reg register (address 81h, 181h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5 t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0 : prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
pic16f7x ds30325a-page 20 advance information ? 2000 microchip technology inc. 2.2.2.3 intcon register the intcon register is a readable and writable regis- ter, which contains various enable and flag bits for the tmr0 register overflow, rb port change and external rb0/int pin interrupts. register 2-3: intcon register (address 0bh, 8bh, 10bh, 18bh) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif bit 7 bit 0 bit 7 gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6 peie : peripheral interrupt enable bit 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts bit 5 t0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 inte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3 rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 t0if : tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0 rbif : rb port change interrupt flag bit a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2000 microchip technology inc. advance information ds30325a-page 21 pic16f7x 2.2.2.4 pie1 register the pie1 register contains the individual enable bits for the peripheral interrupts. register 2-4: pie1 register (address 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 bit 7 pspie (1) : parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6 adie : a/d converter interrupt enable bit 1 = enables the a/d converter interrupt 0 = disables the a/d converter interrupt bit 5 rcie : usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie : usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2 ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt note 1: pspie is reserved on 28-pin devices; always maintain this bit clear. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16f7x ds30325a-page 22 advance information ? 2000 microchip technology inc. 2.2.2.5 pir1 register the pir1 register contains the individual flag bits for the peripheral interrupts. register 2-5: pir1 register (address 0ch) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate interrupt bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 bit 7 pspif (1) : parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6 adif : a/d converter interrupt flag bit 1 = an a/d conversion completed 0 = the a/d conversion is not complete bit 5 rcif : usart receive interrupt flag bit 1 = the usart receive buffer is full 0 = the usart receive buffer is empty bit 4 txif : usart transmit interrupt flag bit 1 = the usart transmit buffer is empty 0 = the usart transmit buffer is full bit 3 sspif : synchronous serial port (ssp) interrupt flag 1 = the ssp interrupt condition has occurred, and must be cleared in software before returning from the interrupt service routine. the conditions that will set this bit are: spi a transmission/reception has taken place. i 2 c slave a transmission/reception has taken place. i 2 c master a transmission/reception has taken place. the initiated start condition was completed by the ssp module. the initiated stop condition was completed by the ssp module. the initiated restart condition was completed by the ssp module. the initiated acknowledge condition was completed by the ssp module. a start condition occurred while the ssp module was idle (multi-master system). a stop condition occurred while the ssp module was idle (multi-master system). 0 = no ssp interrupt condition has occurred. bit 2 ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1 tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if : tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow note 1: pspif is reserved on 28-pin devices; always maintain this bit clear. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2000 microchip technology inc. advance information ds30325a-page 23 pic16f7x 2.2.2.6 pie2 register the pie2 register contains the individual enable bits for the ccp2 peripheral interrupt. register 2-6: pie2 register (address 8dh) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? ccp2ie bit 7 bit 0 bit 7-1 unimplemented: read as ? 0 ? bit 0 ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16f7x ds30325a-page 24 advance information ? 2000 microchip technology inc. 2.2.2.7 pir2 register the pir2 register contains the flag bits for the ccp2 interrupt. . register 2-7: pir2 register (address 0dh) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? ccp2if bit 7 bit 0 bit 7-1 unimplemented: read as '0' bit 0 ccp2if : ccp2 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2000 microchip technology inc. advance information ds30325a-page 25 pic16f7x 2.2.2.8 pcon register the power control (pcon) register contains flag bits to allow differentiation between a power-on reset (por), a brown-out reset (bor), a watchdog reset (wdt) and an external mclr reset. register 2-8: pcon register (address 8eh) note: bor is unknown on por. it must be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. the bor status bit is a don ? t care and is not predictable if the brown-out circuit is disabled (by clear- ing the boden bit in the configuration word). u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-1 ? ? ? ? ? ? por bor bit 7 bit 0 bit 7-2 unimplemented: read as '0' bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16f7x ds30325a-page 26 advance information ? 2000 microchip technology inc. 2.3 pcl and pclath the program counter (pc) is 13-bits wide. the low byte comes from the pcl register, which is a readable and writable register. the upper bits (pc<12:8>) are not readable, but are indirectly writable through the pclath register. on any reset, the upper bits of the pc will be cleared. figure 2-5 shows the two situations for the loading of the pc. the upper example in the fig- ure shows how the pc is loaded on a write to pcl (pclath<4:0> pch). the lower example in the fig- ure shows how the pc is loaded during a call or goto instruction (pclath<4:3> pch). figure 2-5: loading of pc in different situations 2.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256 byte block). refer to the application note, ?implementing a table read" (an556). 2.3.2 stack the pic16f7x family has an 8-level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed, or an interrupt causes a branch. the stack is poped in the event of a return,retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 2.4 program memory paging pic16f7x devices are capable of addressing a contin- uous 8k word block of program memory. the call and goto instructions provide only 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction, the upper 2 bits of the address are provided by pclath<4:3>. when doing a call or goto instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. if a return from a call instruction (or interrupt) is exe- cuted, the entire 13-bit pc is popped off the stack. therefore, manipulation of the pclath<4:3> bits are not required for the return instructions (which pops the address from the stack). example 2-1 shows the calling of a subroutine in page 1 of the program memory. this example assumes that pclath is saved and restored by the interrupt service routine (if interrupts are used). example 2-1: call of a subroutine in page 1 from page 0 org 0x500 bcf pclath,4 bsf pclath,3 ;select page 1 (800h-fffh) call sub1_p1 ;call subroutine in : ;page 1 (800h-fffh) : org 0x900 ;page 1 (800h-fffh) sub1_p1 : ;called subroutine : ;page 1 (800h-fffh) : return ;return to call subroutine ;in page 0 (000h-7ffh) pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu goto,call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw and retfie instructions or the vectoring to an interrupt address. note: the contents of the pclath are unchanged after a return or retfie instruction is executed. the user must setup the pclath for any subsequent calls or gotos .
? 2000 microchip technology inc. advance information ds30325a-page 27 pic16f7x 2.5 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf reg- ister. any instruction using the indf register actually accesses the register pointed to by the file select reg- ister, fsr. reading the indf register itself indirectly (fsr = ? 0 ? ) will read 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 2-6. a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-2. example 2-2: indirect addressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue : ;yes continue figure 2-6: direct/indirect addressing note 1: for register file map detail see figure 2-3. data memory (1) indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h 7fh 00h 17fh 100h 1ffh 180h
pic16f7x ds30325a-page 28 advance information ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. advance information ds30325a-page 29 pic16f7x 3.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the picmicro ? mid-range reference manual, (ds33023). 3.1 porta and the trisa register porta is a 6-bit wide, bi-directional port. the corre- sponding data direction register is trisa. setting a trisa bit (=1) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisa bit (=0) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/t0cki pin is a schmitt trigger input and an open drain output. all other porta pins have ttl input levels and full cmos output drivers. other porta pins are multiplexed with analog inputs and analog v ref input. the operation of each pin is selected by clearing/setting the control bits in the adcon1 register (a/d control register1). the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set, when using them as analog inputs. example 3-1: initializing porta bcf status, rp0 ; bcf status, rp1 ; bank0 clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0x06 ; configure all pins movwf adcon1 ; as digital inputs movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ; trisa<7:6> are always ; read as ?0?. figure 3-1: block diagram of ra3:ra0 and ra5 pins figure 3-2: block diagram of ra4/ t0cki pin note: on a power-on reset, these pins are con- figured as analog inputs and read as '0'. data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris latch rd tris rd port v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . analog input mode ttl input buffer to a/d converter data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input q d q ck q d q ck en qd en note 1: i/o pin has protection diodes to v ss only.
pic16f7x ds30325a-page 30 advance information ? 2000 microchip technology inc. table 3-1: porta functions table 3-2: summary of registers associated with porta name bit# buffer function ra0/an0 bit0 ttl input/output or analog input. ra1/an1 bit1 ttl input/output or analog input. ra2/an2 bit2 ttl input/output or analog input. ra3/an3/v ref bit3 ttl input/output or analog input or v ref. ra4/t0cki bit4 st input/output or external clock input for timer0. output is open drain type. ra5/ss /an4 bit5 ttl input/output or slave select input for synchronous serial port or analog input. legend: ttl = ttl input, st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 05h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta. note: when using the ssp module in spi slave mode and ss enabled, the a/d converter must be set to one of the following modes where pcfg2:pcfg0 = 100, 101, 11x .
? 2000 microchip technology inc. advance information ds30325a-page 31 pic16f7x 3.2 portb and the trisb register portb is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (=1) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisb bit (=0) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option_reg<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are dis- abled on a power-on reset. figure 3-3: block diagram of rb3:rb0 pins four of portb ? s pins, rb7:rb4, have an interrupt-on- change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt- on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ? mismatch ? outputs of rb7:rb4 are or ? ed together to generate the rb port change interrupt with flag bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. this interrupt on mismatch feature, together with soft- ware configureable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. refer to the embedded control handbook, ? implementing wake-up on key stroke ? (an552). rb0/int is an external interrupt input pin and is config- ured using the intedg bit (option_reg<6>). rb0/int is discussed in detail in section 12.10.1. figure 3-4: block diagram of rb7:rb4 pins data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int i/o pin (1) ttl input buffer schmitt trigger buffer tris latch note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). data latch from other rbpu (2) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer pin (1) st buffer rb7:rb6 in serial programming mode q3 q1 note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>).
pic16f7x ds30325a-page 32 advance information ? 2000 microchip technology inc. table 3-3: portb functions table 3-4: summary of registers associated with portb name bit# buffer function rb0/int bit0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up. rb1 bit1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit2 ttl input/output pin. internal software programmable weak pull-up. rb3 bit3 ttl input/output pin. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming clock. rb7 bit7 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h, 106h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h, 186h trisb portb data direction register 1111 1111 1111 1111 81h, 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
? 2000 microchip technology inc. advance information ds30325a-page 33 pic16f7x 3.3 portc and the trisc register portc is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisc. setting a trisc bit (=1) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisc bit (=0) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). portc is multiplexed with several peripheral functions (table 3-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-modify- write instructions ( bsf, bcf, xorwf ) with trisc as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings. figure 3-5: portc block diagram (peripheral output override) table 3-5: portc functions table 3-6: summary of registers associated with portc port/peripheral select (2) data bus wr port wr tris rd data latch tris latch rd tris schmitt trigger q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss port peripheral oe (3) peripheral input note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data and peripheral output. 3: peripheral oe (output enable) is only activated if peripheral select is active. i/o pin (1) name bit# buffer type function rc0/t1oso/t1cki bit0 st input/output port pin or timer1 oscillator output/timer1 clock input. rc1/t1osi/ccp2 bit1 st input/output port pin or timer1 oscillator input or capture2 input/ compare2 output/pwm2 output. rc2/ccp1 bit2 st input/output port pin or capture1 input/compare1 output/pwm1 output. rc3/sck/scl bit3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit5 st input/output port pin or synchronous serial port data output. rc6/tx/ck bit6 st input/output port pin or usart asynchronous transmit or synchronous clock. rc7/rx/dt bit7 st input/output port pin or usart asynchronous receive or synchronous data. legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged
pic16f7x ds30325a-page 34 advance information ? 2000 microchip technology inc. 3.4 portd and trisd registers this section is not applicable to the pic16f73 or pic16f76. portd is an 8-bit port with schmitt trigger input buff- ers. each pin is individually configureable as an input or output. portd can be configured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit pspmode (trise<4>). in this mode, the input buffers are ttl. figure 3-6: portd block diagram (in i/o port mode) table 3-7: portd functions table 3-8: summary of registers associated with portd data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer i/o pin (1) note 1: i/o pins have protection diodes to vdd and vss. q d ck q d ck en qd en name bit# buffer type function rd0/psp0 bit0 st/ttl (1) input/output port pin or parallel slave port bit0 rd1/psp1 bit1 st/ttl (1) input/output port pin or parallel slave port bit1 rd2/psp2 bit2 st/ttl (1) input/output port pin or parallel slave port bit2 rd3/psp3 bit3 st/ttl (1) input/output port pin or parallel slave port bit3 rd4/psp4 bit4 st/ttl (1) input/output port pin or parallel slave port bit4 rd5/psp5 bit5 st/ttl (1) input/output port pin or parallel slave port bit5 rd6/psp6 bit6 st/ttl (1) input/output port pin or parallel slave port bit6 rd7/psp7 bit7 st/ttl (1) input/output port pin or parallel slave port bit7 legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffer when in parallel slave port mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu 88h trisd portd data direction register 1111 1111 1111 1111 89h trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by portd.
? 2000 microchip technology inc. advance information ds30325a-page 35 pic16f7x 3.5 porte and trise register this section is not applicable to the pic16f73 or pic16f76. porte has three pins, re0/rd /an5, re1/wr /an6 and re2/cs /an7, which are individually configureable as inputs or outputs. these pins have schmitt trigger input buffers. i/o porte becomes control inputs for the micropro- cessor port when bit pspmode (trise<4>) is set. in this mode, the user must make sure that the trise<2:0> bits are set (pins are configured as digital inputs). ensure adcon1 is configured for digital i/o. in this mode, the input buffers are ttl. register 3-1 shows the trise register, which also con- trols the parallel slave port operation. porte pins are multiplexed with analog inputs. when selected as an analog input, these pins will read as ? 0 ? s. trise controls the direction of the re pins, even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. figure 3-7: porte block diagram (in i/o port mode) note: on a power-on reset, these pins are con- figured as analog inputs and read as ? 0 ? . data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer q d ck q d ck en qd en i/o pin (1) note 1: i/o pins have protection diodes to vdd and vss.
pic16f7x ds30325a-page 36 advance information ? 2000 microchip technology inc. register 3-1: trise register (address 89h) r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode ? bit2 bit1 bit0 bit 7 bit 0 bit 7 parallel slave port status/control bits ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6 obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov : input buffer overflow detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3 unimplemented : read as '0' bit 2 porte data direction bits bit2 : direction control bit for pin re2/cs /an7 1 = input 0 = output bit 1 bit1 : direction control bit for pin re1/wr /an6 1 = input 0 = output bit 0 bit0 : direction control bit for pin re0/rd /an5 1 = input 0 = output legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2000 microchip technology inc. advance information ds30325a-page 37 pic16f7x table 3-9: porte functions table 3-10: summary of registers associated with porte name bit# buffer type function re0/rd /an5 bit0 st/ttl (1) input/output port pin or read control input in parallel slave port mode or analog input: rd 1 =idle 0 = read operation. contents of portd register output to portd i/o pins (if chip selected). re1/wr /an6 bit1 st/ttl (1) input/output port pin or write control input in parallel slave port mode or analog input: wr 1 =idle 0 = write operation. value of portd i/o pins latched into portd register (if chip selected). re2/cs /an7 bit2 st/ttl (1) input/output port pin or chip select control input in parallel slave port mode or analog input: cs 1 = device is not selected 0 = device is selected legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 09h porte ? ? ? ? ? re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by porte.
pic16f7x ds30325a-page 38 advance information ? 2000 microchip technology inc. 3.6 parallel slave port the parallel slave port is not implemented on the pic16f73 or pic16f76. portd operates as an 8-bit wide parallel slave port, or microprocessor port when control bit pspmode (trise<4>) is set. in slave mode, it is asynchronously readable and writable by the external world through rd control input pin re0/rd and wr control input pin re1/wr . it can directly interface to an 8-bit microprocessor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd to be the rd input, re1/wr to be the wr input and re2/cs to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (set). the a/d port config- uration bits pcfg3:pcfg0 (adcon1<3:0>) must be set to configure pins re2:re0 as digital i/o. there are actually two 8-bit latches. one for data out- put and one for data input. the user writes 8-bit data to the portd data latch and reads data from the port pin latch (note that they have the same address). in this mode, the trisd register is ignored, since the external device is controlling the direction of data flow. a write to the psp occurs when both the cs and wr lines are first detected low. when either the cs or wr lines become high (level triggered), the input buffer full (ibf) status flag bit (trise<7>) is set on the q4 clock cycle, following the next q2 cycle, to signal the write is complete (figure 3-9). the interrupt flag bit pspif (pir1<7>) is also set on the same q4 clock cycle. ibf can only be cleared by reading the portd input latch. the input buffer overflow (ibov) status flag bit (trise<5>) is set if a second write to the psp is attempted when the previous byte has not been read out of the buffer. a read from the psp occurs when both the cs and rd lines are first detected low. the output buffer full (obf) status flag bit (trise<6>) is cleared immedi- ately (figure 3-10) indicating that the portd latch is waiting to be read by the external bus. when either the cs or rd pin becomes high (level triggered), the inter- rupt flag bit pspif is set on the q4 clock cycle, follow- ing the next q2 cycle, indicating that the read is complete. obf remains low until data is written to portd by the user firmware. when not in psp mode, the ibf and obf bits are held clear. however, if flag bit ibov was previously set, it must be cleared in firmware. an interrupt is generated and latched into flag bit pspif when a read or write operation is completed. pspif must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit pspie (pie1<7>). figure 3-8: portd and porte block diagram (parallel slave port) data bus wr port rd rdx q d ck en qd en port pin one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr note: i/o pin has protection diodes to v dd and v ss . ttl ttl ttl ttl
? 2000 microchip technology inc. advance information ds30325a-page 39 pic16f7x figure 3-9: parallel slave port write waveforms figure 3-10: parallel slave port read waveforms table 3-11: registers associated with parallel slave port q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0> q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0> address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd port data latch when written: port pins when read xxxx xxxx uuuu uuuu 09h porte ? ? ? ? ? re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the parallel slave port. note 1: bits pspie and pspif are reserved on the pic16f73/76; always maintain these bits clear.
pic16f7x ds30325a-page 40 advance information ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. advance information ds30325a-page 41 pic16f7x 4.0 reading program memory the flash program memory is readable during nor- mal operation over the entire v dd range. it is indirectly addressed through special function registers (sfr). up to 14-bit numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ascii, etc. executing a program memory location con- taining data that forms an invalid instruction results in a nop . there are five sfrs used to read the program and memory. these registers are: pmcon1 pmdata pmdath pmadr pmadrh the program memory allows word reads. program memory access allows for checksum calculation and reading calibration tables. when interfacing to the program memory block, the pmdath:pmdata registers form a two byte word, which holds the 14-bit data for reads. the pmadrh:pmadr registers form a two byte word, which holds the 13-bit address of the flash location being accessed. these devices can have up to 8k words of program flash, with an address range from 0h to 3fffh. the unused upper bits in both the pmdath and pmadrh registers are not implemented and read as ? 0 ? s ? . 4.1 pmadr the address registers can address up to a maximum of 8k words of program flash. when selecting a program address value, the msbyte of the address is written to the pmadrh register and the lsbyte is written to the pmadr register. the upper msbits of pmadrh must always be clear. 4.2 pmcon1 register pmcon1 is the control register for memory accesses. the control bit rd initiates read operations. this bit cannot be cleared, only set, in software. it is cleared in hardware at the completion of the read operation. register 4-1: pmcon1 register (address 18ch) r-1 u-0 u-0 u-0 u-x u-0 u-0 r/s-0 ? ? ? ? ? ? ? rd bit 7 bit 0 bit 7 reserved: read as ? 1 ? bit 6-1 unimplemented : read as '0' bit 0 rd : read control bit 1 = initiates a flash read, rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = does not initiate a flash read legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16f7x ds30325a-page 42 advance information ? 2000 microchip technology inc. 4.3 reading the flash program memory a program memory location may be read by writing two bytes of the address to the pmadr and pmadrh reg- isters and then setting control bit rd (pmcon1<0>). once the read control bit is set, the microcontroller will use the next two instruction cycles to read the data. the data is available in the pmdata and pmdath regis- ters after the second nop instruction. therefore, it can be read as two bytes in the following instructions. the pmdata and pmdath registers will hold this value until another read operation. example 4-1: flash program read bsf status, rp1 ; bcf status, rp0 ; bank 2 movf addrh, w ; movwf pmadrh ; msbyte of program address to read movf addrl, w ; movwf pmadr ; lsbyte of program address to read bsf status, rp0 ; bank 3 required bsf pmcon1, rd ; eeprom read sequence nop ; memory is read in the next two cycles after bsf pmcon1,rd nop ; bcf status, rp0 ; bank 2 movf pmdata, w ; w = lsbyte of program pmdata movf pmdath, w ; w = msbyte of program pmdata
? 2000 microchip technology inc. advance information ds30325a-page 43 pic16f7x 4.4 operation during code protect flash program memory has its own code protect mechanism. external read and write operations are disabled if this mechanism is enabled. the microcontroller can read and execute instructions out of the internal flash program memory, regardless of the state of the code protect configuration bits. table 4-1: registers associated with program flash addressnamebit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 value on: por, bor value on all other resets 10dh pmadr address register low byte xxxx xxxx uuuu uuuu 10fh pmadrh ? ? ? address register high byte xxxx xxxx uuuu uuuu 10ch pmdata data register low byte xxxx xxxx uuuu uuuu 10eh pmdath ? ? data register high byte xxxx xxxx uuuu uuuu 18ch pmcon1 ? (1) ? ? ? ? ? ? rd 1--- ---0 1--- ---0 legend: x = unknown, u = unchanged, r = reserved, - = unimplemented read as ? 0 ? . shaded cells are not used during flash access. note 1: this bit always reads as a ? 1 ? .
pic16f7x ds30325a-page 44 advance information ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. advance information ds30325a-page 45 pic16f7x 5.0 timer0 module the timer0 module timer/counter has the following features: 8-bit timer/counter readable and writable 8-bit software programmable prescaler internal or external clock select interrupt on overflow from ffh to 00h edge select for external clock figure 5-1 is a block diagram of the timer0 module and the prescaler shared with the wdt. additional information on the timer0 module is avail- able in the picmicro ? mid-range mcu family refer- ence manual (ds33023). timer mode is selected by clearing bit t0cs (option_reg<5>). in timer mode, the timer0 mod- ule will increment every instruction cycle (without pres- caler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option_reg<5>). in counter mode, timer0 will increment, either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit t0se (option_reg<4>). clearing bit t0se selects the ris- ing edge. restrictions on the external clock input are discussed in detail in section 5.2. the prescaler is mutually exclusively shared between the timer0 module and the watchdog timer. the pres- caler is not readable or writable. section 5.3 details the operation of the prescaler. 5.1 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt ser- vice routine, before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep, since the timer is shut off during sleep. figure 5-1: block diagram of the timer0/wdt prescaler ra4/t0cki t0se pin m u x clkout (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option_reg<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set flag bit t0if on overflow 8 psa t0cs prescaler
pic16f7x ds30325a-page 46 advance information ? 2000 microchip technology inc. 5.2 using timer0 with an external clock when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki, with the internal phase clocks, is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t0cki to be high for at least 2tosc (and a small rc delay of 20 ns) and low for at least 2tosc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. 5.3 pre scaler there is only one prescaler available, which is mutually exclusively shared between the timer0 module and the watchdog timer. a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. this prescaler is not readable or writable (see figure 5-1). the psa and ps2:ps0 bits (option_reg<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the prescaler is not readable or writable. register 5-1: option_reg register note: writing to tmr0 when the prescaler is assigned to timer0, will clear the prescaler count but will not change the prescaler assignment. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu bit 6 intedg bit 5 t0cs: tmr0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se: tmr0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0 : prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate note: to avoid an unintended device reset, the instruction sequence shown in the picmicro ? mid-range mcu family reference manual (ds33023) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled.
? 2000 microchip technology inc. advance information ds30325a-page 47 pic16f7x table 5-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 01h,101h tmr0 timer0 module ? s register xxxx xxxx uuuu uuuu 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0.
pic16f7x ds30325a-page 48 advance information ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. advance information ds30325a-page 49 pic16f7x 6.0 timer1 module the timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (tmr1h and tmr1l), which are readable and writable. the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clearing tmr1 interrupt enable bit tmr1ie (pie1<0>). timer1 can operate in one of two modes: as a timer as a counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con<0>). timer1 also has an internal ? reset input ? . this reset can be generated by either of the two ccp modules (section 8.0). register 6-1 shows the timer1 control register. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi/ccp2 and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored and these pins read as ? 0 ? . additional information on timer modules is available in the picmicro ? mid-range mcu family reference manual (ds33023). register 6-1: t1con: timer1 control register (address 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen : timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut off (the oscillator inverter is turned off to eliminate power drain) bit 2 t1sync : timer1 external clock input synchronization control bit tmr1cs = 1 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0 this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1 tmr1cs : timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on : timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16f7x ds30325a-page 50 advance information ? 2000 microchip technology inc. 6.1 timer1 operation in timer mode timer mode is selected by clearing the tmr1cs (t1con<1>) bit. in this mode, the input clock to the timer is f osc /4. the synchronize control bit t1sync (t1con<2>) has no effect, since the internal clock is always in sync. 6.2 timer1 counter operation timer1 may operate in asynchronous or synchronous mode, depending on the setting of the tmr1cs bit. when timer1 is being incremented via an external source, increments occur on a rising edge. after timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment. figure 6-1: timer1 incrementing edge 6.3 timer1 operation in synchronized counter mode counter mode is selected by setting bit tmr1cs. in this mode, the timer increments on every rising edge of clock input on pin rc1/t1osi/ccp2, when bit t1oscen is set, or on pin rc0/t1oso/t1cki, when bit t1oscen is cleared. if t1sync is cleared, then the external clock input is synchronized with internal phase clocks. the synchro- nization is done after the prescaler stage. the pres- caler stage is an asynchronous ripple counter. in this configuration, during sleep mode, timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off. the prescaler however, will continue to increment. figure 6-2: timer1 block diagram t1cki (default high) t1cki (default low) note: arrows indicate counter increments. tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 q clock t1oscen enable oscillator (1) fosc/4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 rc0/t1oso/t1cki rc1/t1osi/ccp2 (2) note 1: when the t1oscen bit is cleared, the inverter is turned off. this eliminates power drain. 2: for the pic16f73/76, the schmitt trigger is not implemented in external clock mode. set flag bit tmr1if on overflow tmr1 (2)
? 2000 microchip technology inc. advance information ds30325a-page 51 pic16f7x 6.4 timer1 operation in asynchronous counter mode if control bit t1sync (t1con<2>) is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in soft- ware are needed to read/write the timer (section 6.4.1). in asynchronous counter mode, timer1 can not be used as a time base for capture or compare operations. 6.4.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l, while the timer is running from an external asynchronous clock, will guarantee a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write conten- tion may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the timer register. reading the 16-bit value requires some care. exam- ples 12-2 and 12-3 in the picmicro ? mid-range mcu family reference manual (ds33023) show how to read and write timer1 when it is running in asynchro- nous mode. 6.5 timer1 oscillator a crystal oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for use with a 32 khz crystal. table 6-1 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must provide a software time delay to ensure proper oscillator start-up. table 6-1: capacitor selection for the timer1 oscillator 6.6 resetting timer1 using a ccp trigger output if the ccp1 or ccp2 module is configured in compare mode to generate a ? special event trigger ? (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1. timer1 must be configured for either timer or synchro- nized counter mode, to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a spe- cial event trigger from ccp1 or ccp2, the write will take precedence. in this mode of operation, the ccprxh:ccprxl regis- ter pair effectively becomes the period register for timer1. 6.7 resetting of timer1 register pair (tmr1h, tmr1l) tmr1h and tmr1l registers are not reset to 00h on a por, or any other reset, except by the ccp1 and ccp2 special event triggers. t1con register is reset to 00h on a power-on reset or a brown-out reset, which shuts off the timer and leaves a 1:1 prescale. in all other resets, the register is unaffected. 6.8 timer1 prescaler the prescaler counter is cleared on writes to the tmr1h or tmr1l registers. osc type freq c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf these values are for design guidance only. crystals tested: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm note 1: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. note: the special event triggers from the ccp1 and ccp2 modules will not set interrupt flag bit tmr1if (pir1<0>).
pic16f7x ds30325a-page 52 advance information ? 2000 microchip technology inc. table 6-2: registers associated with timer1 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer1 module. note 1: bits pspie and pspif are reserved on the pic16f73/76; always maintain these bits clear.
? 2000 microchip technology inc. advance information ds30325a-page 53 pic16f7x 7.0 timer2 module timer2 is an 8-bit timer with a prescaler and a postscaler. it can be used as the pwm time base for the pwm mode of the ccp module(s). the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, (pir1<1>)). timer2 can be shut off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. register 7-1 shows the timer2 control register. additional information on timer modules is available in the picmicro ? mid-range mcu family reference manual (ds33023). 7.1 timer2 prescaler and postscaler the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (por, mclr reset, wdt reset or bor) tmr2 is not cleared when t2con is written. 7.2 output of tmr2 the output of tmr2 (before the postscaler) is fed to the ssp module, which optionally uses it to generate shift clock. figure 7-1: timer2 block diagram register 7-1: t2con: timer2 control register (address 12h) comparator tmr2 sets flag tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. to t2outps3: t2outps0 t2ckps1: t2ckps0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-3 toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 0010 = 1:3 postscale 1111 = 1:16 postscale bit 2 tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16f7x ds30325a-page 54 advance information ? 2000 microchip technology inc. table 7-1: registers associated with timer2 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 11h tmr2 timer2 module ? s register 0000 0000 0000 0000 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer2 module. note 1: bits pspie and pspif are reserved on the pic16f73/76; always maintain these bits clear.
? 2000 microchip technology inc. advance information ds30325a-page 55 pic16f7x 8.0 capture/compare/pwm modules each capture/compare/pwm (ccp) module contains a 16-bit register which can operate as a: 16-bit capture register 16-bit compare register pwm master/slave duty cycle register both the ccp1 and ccp2 modules are identical in operation, with the exception being the operation of the special event trigger. table 8-1 and table 8-2 show the resources and interactions of the ccp module(s). in the following sections, the operation of a ccp module is described with respect to ccp1. ccp2 operates the same as ccp1, except where noted. 8.1 ccp1 module capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. the special event trigger is generated by a compare match and will reset timer1. 8.2 ccp2 module capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp2con register controls the operation of ccp2. the special event trigger is generated by a compare match and will reset timer1 and start an a/d conversion (if the a/d module is enabled). additional information on ccp modules is available in the picmicro ? mid-range mcu family reference manual (ds33023) and in application note 594, ? using the ccp modules ? (ds00594). table 8-1: ccp mode - timer resources required table 8-2: interaction of two ccp modules ccp mode timer resource capture compare pwm timer1 timer1 timer2 ccpx mode ccpy mode interaction capture capture same tmr1 time base. capture compare the compare should be configured for the special event trigger, which clears tmr1. compare compare the compare(s) should be configured for the special event trigger, which clears tmr1. pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt). pwm capture none. pwm compare none.
pic16f7x ds30325a-page 56 advance information ? 2000 microchip technology inc. register 8-1: ccp1con register/ccp2con register (address: 17h/1dh) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ccpxx ccpxy ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5-4 ccpxx:ccpxy : pwm least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm disabled (resets ccpx module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccpxif bit is set) 1001 = compare mode, clear output on match (ccpxif bit is set) 1010 = compare mode, generate software interrupt on match (ccpxif bit is set, ccpx pin is unaffected) 1011 = compare mode, trigger special event (ccpxif bit is set, ccpx pin is unaffected); ccp1 resets tmr1; ccp2 resets tmr1 and starts an a/d conversion (if a/d module is enabled) 11xx = pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2000 microchip technology inc. advance information ds30325a-page 57 pic16f7x 8.3 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rc2/ccp1. an event is defined as one of the fol- lowing and is configured by ccpxcon<3:0>: every falling edge every rising edge every 4th rising edge every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit ccp1if (pir1<2>) is set. the interrupt flag must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value is overwritten by the new captured value. 8.3.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be config- ured as an input by setting the trisc<2> bit. figure 8-1: capture mode operation block diagram 8.3.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 8.3.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the flag bit ccp1if following any such change in operating mode. 8.3.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 8-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the ? false ? interrupt. example 8-1: changing between capture prescalers clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ; the new prescaler ; move value and ccp on movwf ccp1con ;load ccp1con with this ; value note: if the rc2/ccp1 pin is configured as an output, a write to the port can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) capture enable q ? s ccp1con<3:0> rc2/ccp1 prescaler 1, 4, 16 and edge detect pin
pic16f7x ds30325a-page 58 advance information ? 2000 microchip technology inc. 8.4 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc2/ccp1 pin is: driven high driven low remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp1con<3:0>). at the same time, interrupt flag bit ccp1if is set. figure 8-2: compare mode operation block diagram 8.4.1 ccp pin configuration the user must configure the rc2/ccp1 pin as an out- put by clearing the trisc<2> bit. 8.4.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 8.4.3 software interrupt mode when generate software interrupt mode is chosen, the ccp1 pin is not affected. the ccpif bit is set causing a ccp interrupt (if enabled). 8.4.4 special event trigger in this mode, an internal hardware trigger is generated, which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special event trigger output of ccp2 resets the tmr1 register pair and starts an a/d conversion (if the a/d module is enabled). 8.5 pwm mode (pwm) in pulse width modulation mode, the ccpx pin pro- duces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 8-3 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 8.5.3. figure 8-3: simplified pwm block diagram note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the portc i/o data latch. ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<2>) match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable pin special event trigger will: reset timer1, but not set interrupt flag bit tmr1if (pir1<0>), and set bit go/done (adcon0<2>). note: the special event trigger from the ccp1 and ccp2 modules will not set interrupt flag bit tmr1if (pir1<0>). note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time base.
? 2000 microchip technology inc. advance information ds30325a-page 59 pic16f7x a pwm output (figure 8-4) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 8-4: pwm output 8.5.1 pwm period the pwm period is specified by writing to the pr2 reg- ister. the pwm period can be calculated using the fol- lowing formula: pwm period = [(pr2) + 1] ? 4 t osc (tmr2 prescale value) pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) the pwm duty cycle is latched from ccpr1l into ccpr1h 8.5.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) tosc (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2 con- catenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. maximum pwm resolution (bits) for a given pwm frequency: 8.5.3 set-up for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 8-3: example pwm frequencies and resolutions at 20 mhz note: the timer2 postscaler (see section 8.3) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different fre- quency than the pwm output. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 tmr2 reset tmr2 reset note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. log ( f pwm log(2) f osc ) bits = resolution pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 5.5
pic16f7x ds30325a-page 60 advance information ? 2000 microchip technology inc. table 8-4: registers associated with capture, compare, and timer1 table 8-5: registers associated with pwm and timer2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ? ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ? ccp2ie ---- ---0 ---- ---0 87h trisc portc data direction register 1111 1111 1111 1111 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1c kps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as ? 0 ? . shaded cells are not used by capture and timer1. note 1: the psp is not implemented on the pic16f73/76; always maintain these bits clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ? ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ? ccp2ie ---- ---0 ---- ---0 87h trisc portc data direction register 1111 1111 1111 1111 11h tmr2 timer2 module ? s register 0000 0000 0000 0000 92h pr2 timer2 module ? s period register 1111 1111 1111 1111 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as ? 0 ? . shaded cells are not used by pwm and timer2. note 1: bits pspie and pspif are reserved on the pic16f73/76; always maintain these bits clear.
? 2000 microchip technology inc. advance information ds30325a-page 61 pic16f7x 9.0 synchronous serial port (ssp) module 9.1 ssp module overview the synchronous serial port (ssp) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the ssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) an overview of i 2 c operations and additional informa- tion on the ssp module can be found in the picmicro ? mid-range mcu family reference manual (ds33023). refer to application note an578, ? use of the ssp module in the i 2 c multi-master environment. ? 9.2 spi mode this section contains register definitions and opera- tional characteristics of the spi module. additional information on the spi module can be found in the picmicro ? mid-range mcu family reference man- ual (ds33023a). spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. to accom- plish communication, typically three pins are used: serial data out (sdo) rc5/sdo serial data in (sdi) rc4/sdi/sda serial clock (sck) rc3/sck/scl additionally, a fourth pin may be used when in a slave mode of operation: slave select (ss ) ra5/ss /an4 when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits in the sspcon register (sspcon<5:0>) and sspstat<7:6>. these control bits allow the fol- lowing to be specified: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only)
pic16f7x ds30325a-page 62 advance information ? 2000 microchip technology inc. register 9-1: sspstat: sync serial port status register (address 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: spi data input sample phase spi master mo de: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time (microwire ? ) spi slave mo de: smp must be cleared when spi is used in slave mode i 2 c mo de: this bit must be maintained clear bit 6 cke : spi clock edge select (figure 9-2, figure 9-3, and figure 9-4) spi mo de: ckp = 0 1 = data transmitted on rising edge of sck (microwire ? alternate) 0 = data transmitted on falling edge of sck ckp = 1 1 = data transmitted on falling edge of sck (microwire ? default) 0 = data transmitted on rising edge of sck i 2 c mo de: this bit must be maintained clear bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p : stop bit (i 2 c mode only) this bit is cleared when the ssp module is disabled, or when the start bit is detected last. sspen is cleared. 1 = indicates that a stop bit has been detected last (this bit is ? 0 ? on reset) 0 = stop bit was not detected last bit 3 s : start bit (i 2 c mode only) this bit is cleared when the ssp module is disabled, or when the stop bit is detected last. sspen is cleared. 1 = indicates that a start bit has been detected last (this bit is ? 0 ? on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or ack bit. 1 = read 0 = write bit 1 ua : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf : buffer full status bit receive (spi and i 2 c modes): 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit (i 2 c mode only): 1 = transmit in progress, sspbuf is full 0 = transmit complete, sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2000 microchip technology inc. advance information ds30325a-page 63 pic16f7x register 9-2: sspcon: sync serial port control register (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol : write collision detect bit 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov : receive overflow indicator bit in spi mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 0 = no overflow in i 2 c mode: 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a "don ? t care" in transmit mode. sspov must be cleared in software in either mode. 0 = no overflow bit 5 sspen : synchronous serial port enable bit in spi mode: 1 = enables serial port and configures sck, sdo, and sdi as serial port pins 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and configures the sda and scl pins as serial port pins 0 = disables serial port and configures these pins as i/o port pins in both modes, when enabled, these pins must be properly configured as input or output. bit 4 ckp : clock polarity select bit in spi mode: 1 = idle state for clock is a high level (microwire ? default) 0 = idle state for clock is a low level (microwire ? alternate) in i 2 c mode: sck release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) bit 3-0 sspm3:sspm0 : synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin. 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1011 = i 2 c firmware controlled master mode (slave idle) 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16f7x ds30325a-page 64 advance information ? 2000 microchip technology inc. figure 9-1: ssp block diagram (spi mode) to enable the serial port, ssp enable bit, sspen (sspcon<5>) must be set. to reset or reconfigure spi mode, clear bit sspen, re-initialize the sspcon reg- ister, and then set bit sspen. this configures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port function, they must have their data direction bits (in the trisc register) appro- priately programmed. that is: sdi must have trisc<4> set sdo must have trisc<5> cleared sck (master mode) must have trisc<3> cleared sck (slave mode) must have trisc<3> set ss must have trisa<5> set and adcon must be configured such that ra5 is a digital i/o . read write internal data bus rc4/sdi/sda rc5/sdo ra5/ss/an4 rc3/sck/ sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t cy prescaler 4, 16, 64 trisc<3> 2 edge select 2 4 scl note 1: when the spi is in slave mode with ss pin control enabled, (sspcon<3:0> = 0100 ) the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke = '1', then the ss pin control must be enabled.
? 2000 microchip technology inc. advance information ds30325a-page 65 pic16f7x figure 9-2: spi mode timing, master mode figure 9-3: spi mode timing (slave mode with cke = 0) figure 9-4: spi mode timing (slave mode with cke = 1) sck (ckp = 0, sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sdi (smp = 1) sck (ckp = 0, sck (ckp = 1, sck (ckp = 1, sdo bit7 bit7 bit0 bit0 cke = 0) cke = 1) cke = 0) cke = 1) sck (ckp = 0) sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck (ckp = 1) sdo bit7 bit0 ss (optional) sck (ckp = 0) sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck (ckp = 1) sdo bit7 bit0 ss
pic16f7x ds30325a-page 66 advance information ? 2000 microchip technology inc. table 9-1: registers associated with spi operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh. 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 94h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the ssp in spi mode. note 1: bits pspie and pspif are reserved on the pic16f73/76; always maintain these bits clear.
? 2000 microchip technology inc. advance information ds30325a-page 67 pic16f7x 9.3 ssp i 2 c operation the ssp module in i 2 c mode, fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facil- itate firmware implementations of the master functions. the ssp module implements the standard mode speci- fications as well as 7-bit and 10-bit addressing. two pins are used for data transfer. these are the rc3/ sck/scl pin, which is the clock (scl), and the rc4/ sdi/sda pin, which is the data (sda). the user must configure these pins as inputs or outputs through the trisc<4:3> bits. the ssp module functions are enabled by setting ssp enable bit sspen (sspcon<5>). figure 9-5: ssp block diagram (i 2 c mode) the ssp module has five registers for i 2 c operation. these are the: ssp control register (sspcon) ssp status register (sspstat) serial receive/transmit buffer (sspbuf) ssp shift register (sspsr) - not directly accessible ssp address register (sspadd) the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: i 2 c slave mode (7-bit address) i 2 c slave mode (10-bit address) i 2 c slave mode (7-bit address), with start and stop bit interrupts enabled to support firmware master mode i 2 c slave mode (10-bit address), with start and stop bit interrupts enabled to support firmware master mode i 2 c start and stop bit interrupts enabled to support firmware master mode, slave is idle selection of any i 2 c mode, with the sspen bit set, forces the scl and sda pins to be open drain, pro- vided these pins are programmed to inputs by setting the appropriate trisc bits. pull-up resistors must be provided externally to the scl and sda pins for proper operation of the i 2 c module. additional information on ssp i 2 c operation can be found in the picmicro ? mid-range mcu family ref- erence manual (ds33023a). 9.3.1 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the ssp module will override the input state with the output data when required (slave-transmitter). when an address is matched, or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse, and then load the sspbuf register with the received value currently in the sspsr register. there are certain conditions that will cause the ssp module not to give this ack pulse. they include (either or both): a) the buffer full bit bf (sspstat<0>) was set before the transfer was received. b) the overflow bit sspov (sspcon<6>) was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. table 9-2 shows what happens when a data transfer byte is received, given the status of bits bf and sspov. the shaded cells show the condition where user software did not properly clear the overflow condi- tion. flag bit bf is cleared by reading the sspbuf reg- ister while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirements of the ssp module, are shown in timing parameter #100 and parameter #101. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/scl rc4/ shift clock msb sdi/ lsb sda
pic16f7x ds30325a-page 68 advance information ? 2000 microchip technology inc. 9.3.1.1 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condi- tion, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register. b) the buffer full bit, bf is set. c) an ack pulse is generated. d) ssp interrupt flag bit, sspif (pir1<3>) is set (interrupt is generated if enabled) - on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave (figure 9-7). the five most sig- nificant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the sec- ond address byte. for a 10-bit address, the first byte would equal ? 1111 0 a9 a8 0 ? , where a9 and a8 are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7 - 9 for slave-transmitter: 1. receive first (high) byte of address (bits sspif, bf, and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the first (high) byte of address, if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif. table 9-2: data transfer received byte actions status bits as data transfer is received sspsr sspbuf generate ack pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 yes yes yes 10 no no yes 11 no no yes 0 1 no no yes note: shaded cells show the conditions where the user software did not properly clear the overflow condition.
? 2000 microchip technology inc. advance information ds30325a-page 69 pic16f7x 9.3.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte overflow condition exists, then no acknowledge (ack ) pulse is given. an overflow condition is defined as either bit bf (sspstat<0>) is set, or bit sspov (sspcon<6>) is set. this is an error condition due to the user ? s firmware. an ssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in soft- ware. the sspstat register is used to determine the status of the byte. figure 9-6: i 2 c waveforms for reception (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w =0 receiving address sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon<6>) ack ack is not sent.
pic16f7x ds30325a-page 70 advance information ? 2000 microchip technology inc. 9.3.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit, and pin rc3/sck/scl is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr regis- ter. then, pin rc3/sck/scl should be enabled by set- ting bit ckp (sspcon<4>). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretch- ing the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 9-7). an ssp interrupt is generated for each data transfer byte. flag bit sspif must be cleared in software, and the sspstat register is used to determine the status of the byte. flag bit sspif is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the ack pulse from the master- receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not ack ), then the data transfer is complete. when the ack is latched by the slave, the slave logic is reset (resets sspstat register) and the slave then monitors for another occur- rence of the start bit. if the sda line was low (ack ), the transmit data must be loaded into the sspbuf reg- ister, which also loads the sspsr register. then pin rc3/sck/scl should be enabled by setting bit ckp. figure 9-7: i 2 c waveforms for transmission (7-bit address) sda scl sspif (pir1<3>) bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written-to before the ckp bit can be set)
? 2000 microchip technology inc. advance information ds30325a-page 71 pic16f7x 9.3.2 master mode master mode of operation is supported in firmware using interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. the stop (p) and start (s) bits will toggle based on the start and stop condi- tions. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle and both the s and p bits are clear. in master mode, the scl and sda lines are manipu- lated by clearing the corresponding trisc<4:3> bit(s). the output level is always low, irrespective of the value(s) in portc<4:3>. so when transmitting data, a ? 1 ? data bit must have the trisc<4> bit set (input) and a ? 0 ? data bit must have the trisc<4> bit cleared (out- put). the same scenario is true for the scl line with the trisc<3> bit. pull-up resistors must be provided externally to the scl and sda pins for proper opera- tion of the i 2 c module. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt will occur if enabled): start condition stop condition data transfer byte transmitted/received master mode of operation can be done with either the slave mode idle (sspm3:sspm0 = 1011 ), or with the slave active. when both master and slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. 9.3.3 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions, allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. the stop (p) and start (s) bits will toggle based on the start and stop conditions. control of the i 2 c bus may be taken when bit p (sspstat<4>) is set, or the bus is idle and both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored to see if the signal level is the expected output level. this check only needs to be done when a high level is output. if a high level is expected and a low level is present, the device needs to release the sda and scl lines (set trisc<4:3>). there are two stages where this arbitration can be lost, these are: address transfer data transfer when the slave logic is enabled, the slave continues to receive. if arbitration was lost during the address trans- fer stage, communication to the device may be in progress. if addressed, an ack pulse will be gener- ated. if arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. table 9-3: registers associated with i 2 c operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat smp (2) cke (2) d/a psr/w ua bf 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ? . shaded cells are not used by ssp module in i 2 c mode. note 1: pspif and pspie are reserved on the pic16f73/76; always maintain these bits clear. 2: maintain these bits clear in i 2 c mode.
pic16f7x ds30325a-page 72 advance information ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. advance information ds30325a-page 73 pic16f7x 10.0 universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also known as a serial com- munications interface or sci.) the usart can be con- figured as a full duplex asynchronous system that can communicate with peripheral devices, such as crt ter- minals and personal computers, or it can be configured as a half duplex synchronous system that can commu- nicate with peripheral devices, such as a/d or d/a inte- grated circuits, serial eeproms, etc. the usart can be configured in the following modes: asynchronous (full duplex) synchronous - master (half duplex) synchronous - slave (half duplex) bit spen (rcsta<7>) and bits trisc<7:6> have to be set in order to configure pins rc6/tx/ck and rc7/rx/dt as the universal synchronous asynchro- nous receiver transmitter. register 10-1: txsta: transmit status and control register (address 98h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync ? brgh trmt tx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode: don ? t care synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4 sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as '0' bit 2 brgh : high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode bit 1 trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data. can be parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16f7x ds30325a-page 74 advance information ? 2000 microchip technology inc. register 10-2: rcsta: receive status and control register (address 18h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r-0 r-0 r-x spen rx9 sren cren ? ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rc7/rx/dt and rc6/tx/ck pins as serial port pins) 0 = serial port disabled bit 6 rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren : single receive enable bit asynchronous mode: don ? t care synchronous mode - master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode - slave: don ? t care bit 4 cren : continuous receive enable bit asynchronous mode: 1 = enables continuous receive 0 = disables continuous receive synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 unimplemented: read as '0' bit 2 ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data can be parity bit (parity to be calculated by firmware) legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2000 microchip technology inc. advance information ds30325a-page 75 pic16f7x 10.1 usart baud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. in asynchronous mode, bit brgh (txsta<2>) also controls the baud rate. in synchronous mode, bit brgh is ignored. table 10-1 shows the formula for computation of the baud rate for different usart modes which only apply in master mode (internal clock). given the desired baud rate and fosc, the nearest inte- ger value for the spbrg register can be calculated using the formula in table 10-1. from this, the error in baud rate can be determined. it may be advantageous to use the high baud rate (brgh = 1), even for slower baud clocks. this is because the f osc /(16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before output- ting the new baud rate. 10.1.1 sampling the data on the rc7/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. table 10-1: baud rate formula table 10-2: registers associated with baud rate generator sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64(x+1)) (synchronous) baud rate = f osc /(4(x+1)) baud rate= f osc /(16(x+1)) n/a x = value in spbrg (0 to 255) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used by the brg.
pic16f7x ds30325a-page 76 advance information ? 2000 microchip technology inc. - table 10-3: baud rates for asynchronous mode (brgh = 0) baud rate (k) f osc = 20 mhz f osc = 16 mhz f osc = 10 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 - - - - - - - - - 1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129 2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64 9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15 19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7 28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4 33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4 57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2 high 1.221 - 255 0.977 - 255 0.610 - 255 low 312.500 - 0 250.000 - 0 156.250 - 0 baud rate (k) f osc = 4 mhz f osc = 3.6864 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 0.300 0 207 0.301 0.33 185 1.2 1.202 0.17 51 1.216 1.33 46 2.4 2.404 0.17 25 2.432 1.33 22 9.6 8.929 6.99 6 9.322 2.90 5 19.2 20.833 8.51 2 18.643 2.90 2 28.8 31.250 8.51 1 - - - 33.6 - - - - - - 57.6 62.500 8.51 0 55.930 2.90 0 high 0.244 - 255 0.218 - 255 low 62.500 - 0 55.930 - 0 table 10-4: baud rates for asynchronous mode (brgh = 1) baud rate (k) f osc = 20 mhz f osc = 16 mhz f osc = 10 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3--------- 1.2--------- 2.4 - - - - - - 2.441 1.71 255 9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64 19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31 28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21 33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18 57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10 high 4.883 - 255 3.906 - 255 2.441 - 255 low 1250.000 - 0 1000.000 0 625.000 - 0 baud rate (k) f osc = 4 mhz f osc = 3.6864 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 - - - - - - 1.2 1.202 0.17 207 1.203 0.25 185 2.4 2.404 0.17 103 2.406 0.25 92 9.6 9.615 0.16 25 9.727 1.32 22 19.2 19.231 0.16 12 18.643 2.90 11 28.8 27.798 3.55 8 27.965 2.90 7 33.6 35.714 6.29 6 31.960 4.88 6 57.6 62.500 8.51 3 55.930 2.90 3 high 0.977 - 255 0.874 - 255 low 250.000 - 0 273.722 - 0
? 2000 microchip technology inc. advance information ds30325a-page 77 pic16f7x 10.2 usart asynchronous mode in this mode, the usart uses standard non-return-to- zero (nrz) format (one start bit, eight or nine data bits, and one stop bit). the most common data format is 8-bits. an on-chip, dedicated, 8-bit baud rate gener- ator can be used to derive standard baud rate frequen- cies from the oscillator. the usart transmits and receives the lsb first. the usart ? s transmitter and receiver are functionally independent, but use the same data format and baud rate. the baud rate gener- ator produces a clock either x16 or x64 of the bit shift rate, depending on bit brgh (txsta<2>). parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). asynchro- nous mode is stopped during sleep. asynchronous mode is selected by clearing bit sync (txsta<4>). the usart asynchronous module consists of the fol- lowing important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 10.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 10-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and flag bit txif (pir1<4>) is set. this interrupt can be enabled/disabled by setting/clearing enable bit txie (pie1<4>). flag bit txif will be set, regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. status bit trmt is a read only bit, which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr reg- ister is empty. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data and the baud rate generator (brg) has produced a shift clock (figure 10-2). the transmission can also be started by first loading the txreg register and then setting enable bit txen. normally, when transmission is first started, the tsr register is empty. at that point, transfer to the txreg register will result in an immedi- ate transfer to tsr, resulting in an empty txreg. a back-to-back transfer is thus possible (figure 10-3). clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmitter. as a result, the rc6/tx/ck pin will revert to hi-impedance. in order to select 9-bit transmission, transmit bit tx9 (txsta<6>) should be set and the ninth bit should be written to tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg reg- ister. this is because a data write to the txreg regis- ter can result in an immediate transfer of the data to the tsr register (if the tsr is empty). in such a case, an incorrect ninth data bit may be loaded in the tsr register. figure 10-1: usart transmit block diagram note 1: the tsr register is not mapped in data memory, so it is not available to the user. 2: flag bit txif is set when enable bit txen is set. txif is cleared by loading txreg. txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8 ? ? ?
pic16f7x ds30325a-page 78 advance information ? 2000 microchip technology inc. steps to follow when setting up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh. (section 10.1) 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set transmit bit tx9. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts trans- mission). 8. if using interrupts, ensure that gie and pie in the intcon register are set. figure 10-2: asynchronous master transmission figure 10-3: asynchronous master transmission (back to back) table 10-5: registers associated with asynchronous transmission address name b it 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous transmission. note 1: bits pspie and pspif are reserved on the pic16f73/76; always maintain these bits clear. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions.
? 2000 microchip technology inc. advance information ds30325a-page 79 pic16f7x 10.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 10-4. the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter oper- ates at the bit rate, or at f osc . once asynchronous mode is selected, reception is enabled by setting bit cren (rcsta<4>). the heart of the receiver is the receive (serial) shift reg- ister (rsr). after sampling the stop bit, the received data in the rsr is transferred to the rcreg register (if it is empty). if the transfer is complete, flag bit rcif (pir1<5>) is set. the actual interrupt can be enabled/ disabled by setting/clearing enable bit rcie (pie1<5>). flag bit rcif is a read only bit which is cleared by the hardware. it is cleared when the rcreg register has been read and is empty. the rcreg is a double buffered register (i.e., it is a two deep fifo). it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting to the rsr register. on the detection of the stop bit of the third byte, if the rcreg register is still full, the overrun error bit oerr (rcsta<1>) will be set. the word in the rsr will be lost. the rcreg reg- ister can be read twice to retrieve the two bytes in the fifo. overrun bit oerr has to be cleared in software. this is done by resetting the receive logic (cren is cleared and then set). if bit oerr is set, transfers from the rsr register to the rcreg register are inhibited and no further data will be received, therefore, it is essential to clear error bit oerr if it is set. framing error bit ferr (rcsta<2>) is set if a stop bit is detected as clear. bit ferr and the 9th receive bit are buffered the same way as the receive data. reading the rcreg will load bits rx9d and ferr with new values, therefore, it is essential for the user to read the rcsta register before reading rcreg register, in order not to lose the old ferr and rx9d information. figure 10-4: usart receive block diagram figure 10-5: asynchronous reception x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 stop start (8) 7 1 0 rx9 ? ? ? f osc 64 16 or start bit bit7/8 bit1 bit0 bit7/8 bit0 stop bit start bit start bit bit7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. an overrun error indicates an error in user firmware.
pic16f7x ds30325a-page 80 advance information ? 2000 microchip technology inc. steps to follow when setting up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh (section 10.1). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit rcie. 4. if 9-bit reception is desired, then set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie is set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. 10. if using interrupts, ensure that gie and pie in the intcon register are set. table 10-6: registers associated with asynchronous reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous reception. note 1: bits pspie and pspif are reserved on the pic16f73/76 devices; always maintain these bits clear.
? 2000 microchip technology inc. advance information ds30325a-page 81 pic16f7x figure 10-6: usart receive block diagram table 10-7: registers associated with asynchronous reception x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 stop start (8) 7 1 0 rx9 ? ? ? 8 f osc 64 16 or address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous reception. note 1: bits pspie and pspif are reserved on the pic16f73/76 devices; always maintain these bits clear.
pic16f7x ds30325a-page 82 advance information ? 2000 microchip technology inc. 10.3 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta<4>). in addition, enable bit spen (rcsta<7>) is set in order to configure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit csrc (txsta<7>). 10.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 10-6. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one tcycle), the txreg is empty and inter- rupt bit txif (pir1<4>) is set. the interrupt can be enabled/disabled by setting/clearing enable bit txie (pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. trmt is a read only bit which is set when the tsr is empty. no inter- rupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory, so it is not available to the user. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data. the first data bit will be shifted out on the next available rising edge of the clock on the ck line. data out is sta- ble around the falling edge of the synchronous clock (figure 10-7). the transmission can also be started by first loading the txreg register and then setting bit txen (figure 10-8). this is advantageous when slow baud rates are selected, since the brg is kept in reset when bits txen, cren and sren are clear. setting enable bit txen will start the brg, creating a shift clock immediately. normally, when transmission is first started, the tsr register is empty, so a transfer to the txreg register will result in an immediate transfer to tsr resulting in an empty txreg. back-to-back transfers are possible. clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmitter. the dt and ck pins will revert to hi- impedance. if either bit cren or bit sren is set during a transmission, the transmission is aborted and the dt pin reverts to a hi-impedance state (for a reception). the ck pin will remain an output if bit csrc is set (internal clock). the transmitter logic, however, is not reset, although it is disconnected from the pins. in order to reset the transmitter, the user has to clear bit txen. if bit sren is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit sren will be cleared and the serial port will revert back to transmitting, since bit txen is still set. the dt line will immediately switch from hi- impedance receive mode to transmit and start driving. to avoid this, bit txen should be cleared. in order to select 9-bit transmission, the tx9 (txsta<6>) bit should be set and the ninth bit should be written to bit tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg register. this is because a data write to the txreg can result in an immediate transfer of the data to the tsr register (if the tsr is empty). if the tsr was empty and the txreg was written before writing the ? new ? tx9d, the ? present ? value of bit tx9d is loaded. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate (section 10.1). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that gie and pie in the intcon register are set.
? 2000 microchip technology inc. advance information ds30325a-page 83 pic16f7x table 10-8: registers associated with synchronous master transmission figure 10-7: synchronous transmission figure 10-8: synchronous transmission (through txen) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous master transmission. note 1: bits pspie and pspif are reserved on the pic16f73/76 devices; always maintain these bits clear. bit 0 bit 1 bit 7 word 1 q1q2 q3q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2 q3q4 q3q4 q1q2 q3q4 q1q2 q3q4 q1q2 q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit (interrupt flag) trmt txen bit ? 1 ? ? 1 ? note: sync master mode; spbrg = ? 0 ? . continuous transmission of two 8-bit words. word 2 trmt bit write word1 write word2 rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit0 bit1 bit2 bit6 bit7 txen bit
pic16f7x ds30325a-page 84 advance information ? 2000 microchip technology inc. 10.3.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either enable bit sren (rcsta<5>), or enable bit cren (rcsta<4>). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, then only a single word is received. if enable bit cren is set, the reception is con- tinuous until cren is cleared. if both bits are set, cren takes precedence. after clocking the last bit, the received data in the receive shift register (rsr) is transferred to the rcreg register (if it is empty). when the transfer is complete, interrupt flag bit rcif (pir1<5>) is set. the actual interrupt can be enabled/ disabled by setting/clearing enable bit rcie (pie1<5>). flag bit rcif is a read only bit, which is reset by the hardware. in this case, it is reset when the rcreg reg- ister has been read and is empty. the rcreg is a dou- ble buffered register (i.e., it is a two deep fifo). it is possible for two bytes of data to be received and trans- ferred to the rcreg fifo and a third byte to begin shift- ing into the rsr register. on the clocking of the last bit of the third byte, if the rcreg register is still full, then overrun error bit oerr (rcsta<1>) is set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. bit oerr has to be cleared in software (by clearing bit cren). if bit oerr is set, transfers from the rsr to the rcreg are inhibited, so it is essential to clear bit oerr if it is set. the ninth receive bit is buffered the same way as the receive data. reading the rcreg register will load bit rx9d with a new value, therefore, it is essential for the user to read the rcsta register before reading rcreg, in order not to lose the old rx9d information. steps to follow when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate (section 10.1). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, then set enable bit rcie. 5. if 9-bit reception is desired, then set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception set bit cren. 7. interrupt flag bit rcif will be set when reception is complete and an interrupt will be generated if enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. 11. if using interrupts, ensure that gie and pie in the intcon register are set. table 10-9: registers associated with synchronous master reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous master reception. note 1: bits pspie and pspif are reserved on the pic16f73/76 devices; always maintain these bits clear.
? 2000 microchip technology inc. advance information ds30325a-page 85 pic16f7x figure 10-9: synchronous reception (master mode, sren) cren bit rc7/rx/dt pin rc6/tx/ck pin write to bit sren sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with bit sren = ? 1 ? and bit brg = ? 0 ? . q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 ? 0 ? q1 q2 q3 q4
pic16f7x ds30325a-page 86 advance information ? 2000 microchip technology inc. 10.4 usart synchronous slave mode synchronous slave mode differs from the master mode, in the fact that the shift clock is supplied exter- nally at the rc6/tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit csrc (txsta<7>). 10.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit txif will now be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep and if the global interrupt is enabled, the program will branch to the inter- rupt vector (0004h). steps to follow when setting up a synchronous slave transmission: 1. enable the synchronous slave serial port by set- ting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that gie and pie in the intcon register are set. 10.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode. bit sren is a ? don't care ? in slave mode. if receive is enabled by setting bit cren prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr register will transfer the data to the rcreg register and if enable bit rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). steps to follow when setting up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is com- plete and an interrupt will be generated, if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren. 9. if using interrupts, ensure that gie and pie in the intcon register are set.
? 2000 microchip technology inc. advance information ds30325a-page 87 pic16f7x table 10-10: registers associated with synchronous slave transmission table 10-11: registers associated with synchronous slave reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous slave transmission. note 1: bits pspie and pspif are reserved on the pic16f73/76 devices; always maintain these bits clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous slave reception. note 1: bits pspie and pspif are reserved on the pic16f73/76 devices, always maintain these bits clear.
pic16f7x ds30325a-page 88 advance information ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. advance information ds30325a-page 89 pic16f7x 11.0 analog-to-digital converter (a/d) module the 8-bit analog-to-digital (a/d) converter module has five inputs for the pic16f73/76 and eight for the pic16f74/77. the a/d allows conversion of an analog input signal to a corresponding 8-bit digital number. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. the analog reference voltage is software selectable to either the device ? s positive supply voltage (v dd ), or the voltage level on the ra3/an3/v ref pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d ? s internal rc oscillator. the a/d module has three registers. these registers are: a/d result register (adres) a/d control register 0 (adcon0) a/d control register 1 (adcon1) the adcon0 register, shown in register 11-1, con- trols the operation of the a/d module. the adcon1 register, shown in register 11-2, configures the func- tions of the port pins. the port pins can be configured as analog inputs (ra3 can also be a voltage reference), or as digital i/o. additional information on using the a/d module can be found in the picmicro ? mid-range mcu family ref- erence manual (ds33023) and in application note, an546. register 11-1: adcon0 register (address 1fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done ? adon bit 7 bit 0 bit 7-6 adcs1:adcs0: a/d conversion clock select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from the internal a/d module rc oscillator) bit 5-3 chs2:chs0 : analog channel select bits 000 = channel 0, (ra0/an0) 001 = channel 1, (ra1/an1) 010 = channel 2, (ra2/an2) 011 = channel 3, (ra3/an3) 100 = channel 4, (ra5/an4) 101 = channel 5, (re0/an5) (1) 110 = channel 6, (re1/an6) (1) 111 = channel 7, (re2/an7) (1) bit 2 go/done : a/d conversion status bit if adon = 1: 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 = a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conversion is complete) bit 1 unimplemented : read as '0' bit 0 adon : a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shutoff and consumes no operating current note 1: a/d channels 5, 6 and 7 are implemented on the pic16f74/77 only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16f7x ds30325a-page 90 advance information ? 2000 microchip technology inc. register 11-2: adcon1 register (address 9fh) u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7-3 unimplemented : read as '0' bit 2-0 pcfg2:pcfg0 : a/d port configuration control bits note 1: re0, re1 and re2 are implemented on the pic16f74/77 only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown a = analog input d = digital i/o pcfg2:pcfg0 ra0 ra1 ra2 ra5 ra3 re0 (1) re1 (1) re2 (1) v ref 000 aaaaaaaav dd 001 aaaav ref aaara3 010 aaaaadddv dd 011 aaaav ref dddra3 100 aaddadddv dd 101 aaddv ref dddra3 11x ddddddddv dd
? 2000 microchip technology inc. advance information ds30325a-page 91 pic16f7x the following steps should be followed for doing an a/d conversion: 1. configure the a/d module: configure analog pins / voltage reference / and digital i/o (adcon1) select a/d input channel (adcon0) select a/d conversion clock (adcon0) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set peie bit set gie bit 3. wait the required acquisition time. 4. start conversion: set go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared (interrupts disabled) or waiting for the a/d interrupt 6. read a/d result register (adres), clear bit adif if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2t ad is required before next acquisition starts. figure 11-1: a/d block diagram (input voltage) v in v ref (reference voltage) v dd pcfg2:pcfg0 chs2:chs0 000 or 010 or 100 or 001 or 011 or 101 re2/an7 (1) re1/an6 (1) re0/an5 (1) ra5/an4 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 111 110 101 100 011 010 001 000 a/d converter note 1: not available on pic16f73/76. 11x
pic16f7x ds30325a-page 92 advance information ? 2000 microchip technology inc. 11.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 11-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), figure 11-2. the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for ana- log sources is 10 k ? . after the analog input channel is selected (changed), the acquisition must pass before the conversion can be started. to calculate the minimum acquisition time, t acq , see the picmicro ? mid-range mcu family reference manual (ds33023a). in general, however, given a max of 10k ? and at a temperature of 100 c, t acq will be no more than 16sec. figure 11-2: analog input model table 11-1: t ad vs. maximum device operating frequencies (standard devices (c)) c pin va r s anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd = 51.2 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions ad clock source (t ad ) maximum device frequency operation adcs1:adcs0 max. 2t osc 00 1.25 mhz 8t osc 01 5 mhz 32t osc 10 20 mhz rc (1, 2, 3) 11 (note 1) note 1: the rc source has a typical t ad time of 4 s but can vary between 2-6 s. 2: when the device frequencies are greater than 1 mhz, the rc a/d conversion clock source is only recommended for sleep operation. 3: for extended voltage devices (lc), please refer to the electrical specifications section.
? 2000 microchip technology inc. advance information ds30325a-page 93 pic16f7x 11.2 s electing the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 9.0t ad per 8-bit conversion. the source of the a/d conversion clock is software selectable. the four possible options for t ad are: 2t osc 8t osc 32t osc internal rc oscillator (2-6 s) for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 s. 11.3 configuring analog port pins the adcon1, trisa and trise registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their correspond- ing tris bits set (input). if the tris bit is cleared (out- put), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. 11.4 a/d conversions clearing the go/done bit during a conversion will abort the current conversion. the adres register will not be updated with the partially completed a/d con- version sample. that is, the adres register will con- tinue to contain the value of the last completed conversion (or the last value written to the adres reg- ister). after the a/d conversion is aborted, a 2t ad wait is required before the next acquisition is started. after this 2t ad wait, an acquisition is automatically started on the selected channel. the go/done bit can then be set to start the conversion. 11.5 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs1:adcs0 = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all digital switching noise from the conversion. when the conver- sion is completed, the go/done bit will be cleared, and the result loaded into the adres register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d mod- ule will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conver- sion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 11.6 effects of a reset a device reset forces all registers to their reset state. the a/d module is disabled and any conversion in progress is aborted. all a/d input pins are configured as analog inputs. the adres register will contain unknown data after a power-on reset. 11.7 use of the ccp trigger an a/d conversion can be started by the ? special event trigger ? of the ccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be pro- grammed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion, and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving the adres to the desired location). the appropriate analog input channel must be selected and the minimum acquisition done before the ? special event trigger ? sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the ? special event trigger ? will be ignored by the a/d module, but will still reset the timer1 counter. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an ana- log input. analog levels on a digitally configured input will not affect the conver- sion accuracy. 2: analog levels on any pin that is defined as a digital input, but not as an analog input, may cause the input buffer to consume current that is out of the devices specifica- tion. note: the go/done bit should not be set in the same instruction that turns on the a/d. note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs1:adcs0 = 11 ). to perform an a/d conversion in sleep, ensure the sleep instruction immediately follows the instruc- tion that sets the go/done bit.
pic16f7x ds30325a-page 94 advance information ? 2000 microchip technology inc. table 11-2: summary of a/d registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ? ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ? ccp2ie ---- ---0 ---- ---0 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done ? adon 0000 00-0 0000 00-0 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 05h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 09h porte (2) ? ? ? ? ? re2 re1 re0 ---- -xxx ---- -uuu 89h trise (2) ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used for a/d conversion. note 1: bits pspie and pspif are reserved on the pic16f73/76; always maintain these bits clear. 2: these registers are reserved on the pic16f73/76.
? 2000 microchip technology inc. advance information ds30325a-page 95 pic16f7x 12.0 special features of the cpu these devices have a host of features intended to max- imize system reliability, minimize cost through elimina- tion of external components, provide power saving operating modes and offer code protection. these are: oscillator selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) sleep code protection id locations in-circuit serial programming these devices have a watchdog timer, which can be shut off only through configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nomi- nal) on power-up only. it is designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up, or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options. additional information on special features is available in the picmicro ? mid-range reference manual, (ds33023). 12.1 configuration bits the configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. these bits are mapped in pro- gram memory location 2007h. the user will note that address 2007h is beyond the user program memory space, which can be accessed only during programming.
pic16f7x ds30325a-page 96 advance information ? 2000 microchip technology inc. register 12-1: configuration word ? ? ? ? ? ? ? boden ? cp0 pwrte wdte f0sc1 f0sc0 register: config address 2007h erased value: 3fffh bit13 bit0 bit 13-7: unimplemented: read as ? 1 ? bit 6: boden : brown-out reset enable bit (1) 1 = bor enabled 0 = bor disabled bit 5: unimplemented: read as ? 1 ? bit 4 cp0: flash program memory code protection bit 1 = code protection off 0 = all memory locations code protected bit 3: pwrte : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enabling brown-out reset automatically enables power-up timer (pwrt), regardless of the value of bit pwrte . ensure the power-up timer is enabled any time brown-out reset is enabled.
? 2000 microchip technology inc. advance information ds30325a-page 97 pic16f7x 12.2 oscillator configurations 12.2.1 oscillator types the pic16f7x can be operated in four different oscil- lator modes. the user can program two configuration bits (fosc1 and fosc0) to select one of these four modes: lp low power crystal xt crystal/resonator hs high speed crystal/resonator rc resistor/capacitor 12.2.2 crystal oscillator/ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 12-1). the pic16f7x oscillator design requires the use of a paral- lel cut crystal. use of a series cut crystal may give a fre- quency out of the crystal manufacturers specifications. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1/clkin pin (figure 12-2). see table 15-1 for valid external clock frequencies. figure 12-1: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 12-2: external clock input operation (hs, xt or lp osc configuration) table 12-1: ceramic resonators note 1: see table 12-1 and table 12-2 for recom- mended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen. c1 (1) c2(1) xtal osc2 osc1 rf(3) sleep to logic pic16f7x rs (2) internal ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these values are for design guidance only. see notes at bottom of page. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors. osc1 osc2 open clock from ext. system pic16f7x
pic16f7x ds30325a-page 98 advance information ? 2000 microchip technology inc. table 12-2: capacitor selection for crystal oscillator 12.2.3 rc oscillator for timing insensitive applications, the ? rc ? device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c compo- nents used. figure 12-3 shows how the r/c combina- tion is connected to the pic16f7x. figure 12-3: rc oscillator mode osc type crystal freq cap. range c1 cap. range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes at bottom of page. crystals used 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm note 1: higher capacitance increases the stability of oscillator, but also increases the start- up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external compo- nents. 3: rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. 4: when migrating from other picmicro devices, oscillator performance should be verified. osc2/clkout c ext r ext pic16f7x osc1 f osc /4 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20pf
? 2000 microchip technology inc. advance information ds30325a-page 99 pic16f7x 12.3 reset the pic16f7x differentiates between various kinds of reset: power-on reset (por) mclr reset during normal operation mclr reset during sleep wdt reset (during normal operation) wdt wake-up (during sleep) brown-out reset (bor) some registers are not affected in any reset condi- tion. their status is unknown on por and unchanged in any other reset. most other registers are reset to a ? reset state ? on power-on reset (por), on the mclr and wdt reset, on mclr reset during sleep, and brown-out reset (bor). they are not affected by a wdt wake-up, which is viewed as the resumption of normal operation. the to and pd bits are set or cleared differently in different reset situa- tions, as indicated in table 12-4. these bits are used in software to determine the nature of the reset. see table 12-6 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 12-4. these devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. figure 12-4: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clkin pin. brown-out reset boden (1)
pic16f7x ds30325a-page 100 advance information ? 2000 microchip technology inc. 12.4 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.2v - 1.7v). to take advantage of the por, tie the mclr pin directly (or through a resistor) to v dd . this will eliminate exter- nal rc components usually needed to create a power- on reset. a maximum rise time for v dd is specified. see electrical specifications for details. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. brown-out reset may be used to meet the start-up conditions. for additional information, refer to application note, an007, ? power-up trouble shoot- ing ? , (ds00007). 12.5 power-up timer (pwrt) the power-up timer provides a fixed 72 ms nominal time-out on power-up only from the por. the power- up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrt ? s time delay allows v dd to rise to an accept- able level. a configuration bit is provided to enable/ disable the pwrt. the power-up time delay will vary from chip to chip due to v dd , temperature and process variation. see dc parameters for details (t pwrt , parameter #33). 12.6 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycles (from osc1 input) delay after the pwrt delay is over (if enabled). this helps to ensure that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 12.7 brown-out reset (bor) the configuration bit, boden, can enable or disable the brown-out reset circuit. if v dd falls below v bor (parameter d005, about 4v) for longer than t bor (parameter #35, about 100 s), the brown-out situation will reset the device. if v dd falls below v bor for less than t bor , a reset may not occur. once the brown-out occurs, the device will remain in brown-out reset until v dd rises above v bor . the power-up timer then keeps the device in reset for t pwrt (parameter #33, about 72ms). if v dd should fall below v bor during t pwrt , the brown-out reset pro- cess will restart when v dd rises above v bor , with the power-up timer reset. the power-up timer is always enabled when the brown-out reset circuit is enabled, regardless of the state of the pwrt configuration bit. 12.8 time-out sequence on power-up, the time-out sequence is as follows: the pwrt delay starts (if enabled) when a por reset occurs. then ost starts counting 1024 oscillator cycles when pwrt ends (lp, xt, hs). when the ost ends, the device comes out of reset. if mclr is kept low long enough, the time-outs will expire. bringing mclr high will begin execution imme- diately. this is useful for testing purposes or to synchro- nize more than one pic16f7x device operating in parallel. table 12-5 shows the reset conditions for the status, pcon and pc registers, while table 12-6 shows the reset conditions for all the registers. 12.9 power control/status register (pcon) the power control/status register, pcon, has up to two bits depending upon the device. bit0 is brown-out reset status bit, bor . bit bor is unknown on a power-on reset. it must then be set by the user and checked on subsequent resets to see if bit bor cleared, indicating a brown-out reset occurred. when the brown-out reset is disabled, the state of the bor bit is unpredictable and therefore, not valid at any time. bit1 is por (power-on reset status bit). it is cleared on a power-on reset and unaffected otherwise. the user must set this bit following a power-on reset.
? 2000 microchip technology inc. advance information ds30325a-page 101 pic16f7x table 12-3: time-out in various situations table 12-4: status bits and their significance table 12-5: reset condition for special registers oscillator configuration power-up brown-out wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp 72 ms + 1024t osc 1024t osc 72 ms + 1024t osc 1024t osc rc 72 ms ? 72 ms ? por bor to pd 0x11 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 0001 1uuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h).
pic16f7x ds30325a-page 102 advance information ? 2000 microchip technology inc. table 12-6: initialization conditions for all registers register devices power-on reset, brown-out reset mclr reset, wdt reset wake-up via wdt or interrupt w 73747677 xxxx xxxx uuuu uuuu uuuu uuuu indf 73 74 76 77 n/a n/a n/a tmr0 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu pcl 73747677 0000h 0000h pc + 1 (2) status 73 74 76 77 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 73747677 xxxx xxxx uuuu uuuu uuuu uuuu porta 73747677 --0x 0000 --0u 0000 --uu uuuu portb 73747677 xxxx xxxx uuuu uuuu uuuu uuuu portc 73747677 xxxx xxxx uuuu uuuu uuuu uuuu portd 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu porte 73 74 76 77 ---- -xxx ---- -uuu ---- -uuu pclath 73 74 76 77 ---0 0000 ---0 0000 ---u uuuu intcon 73 74 76 77 0000 000x 0000 000u uuuu uuuu (1) pir1 73 74 76 77 r000 0000 r000 0000 ruuu uuuu (1) 73 74 76 77 0000 0000 0000 0000 uuuu uuuu (1) pir2 73 74 76 77 ---- ---0 ---- ---0 ---- ---u (1) tmr1l 73747677 xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 73747677 xxxx xxxx uuuu uuuu uuuu uuuu t1con 73747677 --00 0000 --uu uuuu --uu uuuu tmr2 73 74 76 77 0000 0000 0000 0000 uuuu uuuu t2con 73747677 -000 0000 -000 0000 -uuu uuuu sspbuf 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu sspcon 73 74 76 77 0000 0000 0000 0000 uuuu uuuu ccpr1l 73747677 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h 73747677 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 73 74 76 77 --00 0000 --00 0000 --uu uuuu rcsta 73 74 76 77 0000 -00x 0000 -00x uuuu -uuu txreg 73747677 0000 0000 0000 0000 uuuu uuuu rcreg 73 74 76 77 0000 0000 0000 0000 uuuu uuuu ccpr2l 73747677 xxxx xxxx uuuu uuuu uuuu uuuu ccpr2h 73747677 xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 73 74 76 77 0000 0000 0000 0000 uuuu uuuu adres 73747677 xxxx xxxx uuuu uuuu uuuu uuuu adcon0 73 74 76 77 0000 00-0 0000 00-0 uuuu uu-u option_reg 73 74 76 77 1111 1111 1111 1111 uuuu uuuu trisa 73747677 --11 1111 --11 1111 --uu uuuu trisb 73747677 1111 1111 1111 1111 uuuu uuuu trisc 73747677 1111 1111 1111 1111 uuuu uuuu trisd 73 74 76 77 1111 1111 1111 1111 uuuu uuuu trise 73 74 76 77 0000 -111 0000 -111 uuuu -uuu pie1 73 74 76 77 r000 0000 r000 0000 ruuu uuuu 73 74 76 77 0000 0000 0000 0000 uuuu uuuu pie2 73 74 76 77 ---- ---0 ---- ---0 ---- ---u legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition, r = reserved maintain clear. note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 12-5 for reset value for specific condition.
? 2000 microchip technology inc. advance information ds30325a-page 103 pic16f7x figure 12-5: time-out sequence on power-up (mclr tied to v dd ) pcon 73 74 76 77 ---- --qq ---- --uu ---- --uu pr2 73747677 1111 1111 1111 1111 1111 1111 sspstat 73 74 76 77 --00 0000 --00 0000 --uu uuuu sspadd 73747677 0000 0000 0000 0000 uuuu uuuu txsta 73747677 0000 -010 0000 -010 uuuu -uuu spbrg 73 74 76 77 0000 0000 0000 0000 uuuu uuuu adcon1 73 74 76 77 ---- -000 ---- -000 ---- -uuu pmdata 73 74 76 77 0--- 0000 0--- 0000 u--- uuuu pmadr 73747677 xxxx xxxx uuuu uuuu uuuu uuuu pmdath 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu pmadrh 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu pmcon1 73 74 76 77 1--- ---0 1--- ---0 1--- ---u table 12-6: initialization conditions for all registers (continued) register devices power-on reset, brown-out reset mclr reset, wdt reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition, r = reserved maintain clear. note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 12-5 for reset value for specific condition. t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset
pic16f7x ds30325a-page 104 advance information ? 2000 microchip technology inc. figure 12-6: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 12-7: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 12-8: slow rise time (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost
? 2000 microchip technology inc. advance information ds30325a-page 105 pic16f7x 12.10 interrupts the pic16f7x family has up to 12 sources of interrupt. the interrupt control register (intcon) records individ- ual interrupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all un-masked interrupts, or disables (if cleared) all interrupts. when bit gie is enabled, and an interrupt ? s flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in vari- ous registers. individual interrupt bits are set regardless of the status of the gie bit. the gie bit is cleared on reset. the ? return from interrupt ? instruction, retfie , exits the interrupt routine, as well as sets the gie bit, which re-enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flags are contained in the spe- cial function registers, pir1 and pir2. the corre- sponding interrupt enable bits are contained in special function registers, pie1 and pie2, and the peripheral interrupt enable bit is contained in special function register intcon. when an interrupt is responded to, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs. the latency is the same for one or two cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, peie bit, or the gie bit. figure 12-9: interrupt logic note: individual interrupt flag bits are set, regard- less of the status of their corresponding mask bit or the gie bit. pspif pspie adif adie rcif rcie txif txie sspif sspie ccp1if ccp1ie tmr2if tmr2ie tmr1if tmr1ie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu ccp2ie ccp2if the following table shows which devices have which interrupts. device t0if intf rbif pspif adif rcif txif sspif ccp1if tmr2if tmr1if ccp2if pic16f76/73 yes yes yes - yes yes yes yes yes yes yes yes pic16f77/74 yes yes yes yes yes yes yes yes yes yes yes yes
pic16f7x ds30325a-page 106 advance information ? 2000 microchip technology inc. 12.10.1 int interrupt external interrupt on the rb0/int pin is edge triggered, either rising, if bit intedg (option_reg<6>) is set, or falling, if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service routine before re-enabling this interrupt. the int inter- rupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global interrupt enable bit gie decides whether or not the pro- cessor branches to the interrupt vector following wake- up. see section 12.13 for details on sleep mode. 12.10.2 tmr0 interrupt an overflow (ffh 00h) in the tmr0 register will set flag bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>). (section 5.0) 12.10.3 portb intcon change an input change on portb<7:4> sets flag bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<4>). (section 3.2) 12.11 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt (i.e., w register and status register). this will have to be implemented in software. for the pic16f73/74 devices, the register w_temp must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i.e., if w_temp is defined at 0x20 in bank 0, it must also be defined at 0xa0 in bank 1.). the registers, pclath_temp and status_temp, are only defined in bank 0. since the upper 16 bytes of each bank are common in the pic16f76/77 devices, temporary holding registers w_temp, status_temp and pclath_temp should be placed in here. these 16 locations don ? t require banking and therefore, make it easier for con- text save and restore. the same code shown in example 12-1 can be used. example 12-1: saving status, w, and pclath registers in ram movwf w_temp ;copy w to temp register swapf status,w ;swap status to be saved into w clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register movf pclath, w ;only required if using pages 1, 2 and/or 3 movwf pclath_temp ;save pclath into w clrf pclath ;page zero, regardless of current page : :(isr) ;insert user code here : movf pclath_temp, w ;restore pclath movwf pclath ;move w into pclath swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
? 2000 microchip technology inc. advance information ds30325a-page 107 pic16f7x 12.12 watchdog timer (wdt) the watchdog timer is as a free running on-chip rc oscillator which does not require any external compo- nents. this rc oscillator is separate from the rc oscil- lator of the osc1/clkin pin. that means that the wdt will run, even if the clock on the osc1/clkin and osc2/clkout pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the status regis- ter will be cleared upon a watchdog timer time-out. the wdt can be permanently disabled by clearing configuration bit wdte (section 12.1). wdt time-out period values may be found in the elec- trical specifications section under parameter #31. val- ues for the wdt prescaler (actually a postscaler, but shared with the timer0 prescaler) may be assigned using the option_reg register. . figure 12-10: watchdog timer block diagram table 12-7: summary of watchdog timer registers note: the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset condition. note: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. from tmr0 clock source (figure 5-1) to tmr0 (figure 5-1) postscaler wdt timer wdt enable bit 0 1 m u x psa 8 - to - 1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option_reg register. 8 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h config. bits (1) boden (1) ? cp0 pwrte (1) wdte fosc1 fosc0 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see register 12-1 for operation of these bits.
pic16f7x ds30325a-page 108 advance information ? 2000 microchip technology inc. 12.13 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (status<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d and disable external clocks. pull all i/o pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should also be considered. the mclr pin must be at a logic high level (v ihmc ). 12.13.1 wake-up from sleep the device can wake up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change or a peripheral interrupt. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a "wake-up". the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred and caused wake-up. the following peripheral interrupts can wake the device from sleep: 1. psp read or write (pic16f74/77 only). 2. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 3. ccp capture mode interrupt. 4. special event trigger (timer1 in asynchronous mode using an external clock). 5. ssp (start/stop) bit detect interrupt. 6. ssp transmit or receive in slave mode (spi/i 2 c). 7. usart rx or tx (synchronous slave mode). 8. a/d conversion (when a/d clock source is rc). other peripherals cannot generate interrupts since dur- ing sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 12.13.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction.
? 2000 microchip technology inc. advance information ds30325a-page 109 pic16f7x figure 12-11: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = ? 1 ? assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = ? 0 ? , execution will continue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference.
pic16f7x ds30325a-page 110 advance information ? 2000 microchip technology inc. 12.14 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 12.15 id locations four memory locations (2000h - 2003h) are designated as id locations, where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are read- able and writable during program/verify. it is recom- mended that only the 4 least significant bits of the id location are used. 12.16 in-circuit serial programming pic16f7x microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firm- ware to be programmed. for complete details of serial programming, please refer to the in-circuit serial programming (icsp ? ) guide, (ds30277).
? 2000 microchip technology inc. advance information ds30325a-page 111 pic16f7x 13.0 instruction set summary each pic16f7x instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the oper- ation of the instruction. the pic16f7x instruction set summary in table 13-2 lists byte-oriented , bit-ori- ented , and literal and control operations. table 13-1 shows the opcode field descriptions. for byte-oriented instructions, ? f ? represents a file reg- ister designator and ? d ? represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ? d ? is zero, the result is placed in the w register. if ? d ? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ? b ? represents a bit field designator which selects the number of the bit affected by the operation, while ? f ? represents the address of the file in which the bit is located. for literal and control operations, ? k ? represents an eight or eleven bit constant or literal value. table 13-1: opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: byte-oriented operations bit-oriented operations literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop . one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 s. table 13-2 lists the instructions recognized by the mpasm assembler. figure 13-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 13-1: general format for instructions a description of each instruction is available in the picmicro ? mid-range reference manual, (ds33023). field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1 ) the assembler will generate code with x = 0 . it is the recommended form of use for compat- ibility with all microchip software tools. d destination select; d = 0 : store result in w, d = 1: store result in file register f. default is d = 1 pc program counter to time-out bit pd power-down bit note: to maintain upward compatibility with future pic16f7x products, do not use the option and tris instructions. byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16f7x ds30325a-page 112 advance information ? 2000 microchip technology inc. table 13-2: pic16f7x instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to ,pd z to ,pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ? . 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . note: additional information on the mid-range instruction set is available in the picmicro ? mid-range mcu family reference manual (ds33023).
? 2000 microchip technology inc. advance information ds30325a-page 113 pic16f7x 13.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k (w) status affected: c, dc, z description: the contents of the w register are added to the eight bit literal ? k ? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d [0,1] operation: (w) + (f) (destination) status affected: c, dc, z description: add the contents of the w register with register ? f ? . if ? d ? is 0, the result is stored in the w register. if ? d ? is 1, the result is stored back in reg- ister ? f ? . andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) (w) status affected: z description: the contents of w register are and ? ed with the eight bit literal 'k'. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d [0,1] operation: (w) .and. (f) (destination) status affected: z description: and the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 (f) status affected: none description: bit 'b' in register 'f' is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 (f) status affected: none description: bit 'b' in register 'f' is set.
pic16f7x ds30325a-page 114 advance information ? 2000 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit ? b ? in register ? f ? is ? 0 ? , the next instruction is executed. if bit ? b ? is ? 1 ? , then the next instruc- tion is discarded and a nop is exe- cuted instead making this a 2t cy instruction. btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit ? b ? in register ? f ? is ? 1 ? , the next instruction is executed. if bit ? b ? , in register ? f ? , is ? 0 ? , the next instruction is discarded, and a nop is executed instead, making this a 2t cy instruction. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc) + 1 tos, k pc<10:0>, (pclath<4:3>) pc<12:11> status affected: none description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immedi- ate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h (f) 1 z status affected: z description: the contents of register ? f ? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w) 1 z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt prescaler, 1 to 1 pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set.
? 2000 microchip technology inc. advance information ds30325a-page 115 pic16f7x comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d [0,1] operation: (f) (destination) status affected: z description: the contents of register ? f ? are complemented. if ? d ? is 0, the result is stored in w. if ? d ? is 1, the result is stored back in register ? f ? . decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination) status affected: z description: decrement register ? f ? . if ? d ? is 0, the result is stored in the w regis- ter. if ? d ? is 1, the result is stored back in register ? f ? . decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination); skip if result = 0 status affected: none description: the contents of register ? f ? are decremented. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in reg- ister ? f ? . if the result is 1, the next instruc- tion is executed. if the result is 0, then a nop is executed instead making it a 2t cy instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k pc<10:0> pclath<4:3> pc<12:11> status affected: none description: goto is an unconditional branch. the eleven bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination) status affected: z description: the contents of register ? f ? are incremented. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in reg- ister ? f ? . incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination), skip if result = 0 status affected: none description: the contents of register ? f ? are incremented. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in regis- ter ? f ? . if the result is 1, the next instruc- tion is executed. if the result is 0, a nop is executed instead making it a 2t cy instruction.
pic16f7x ds30325a-page 116 advance information ? 2000 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k (w) status affected: z description: the contents of the w register are or ? ed with the eight bit literal 'k'. the result is placed in the w reg- ister. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d [0,1] operation: (w) .or. (f) (destination) status affected: z description: inclusive or the w register with register 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in regis- ter 'f'. movf move f syntax: [ label ] movf f,d operands: 0 f 127 d [0,1] operation: (f) (destination) status affected: z description: the contents of register f are moved to a destination dependant upon the status of d. if d = 0, des- tination is w register. if d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none description: the eight bit literal 'k' is loaded into w register. the don ? t cares will assemble as 0 ? s. movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) (f) status affected: none description: move data from w register to reg- ister 'f'. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation.
? 2000 microchip technology inc. advance information ds30325a-page 117 pic16f7x retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos pc, 1 gie status affected: none retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none description: the w register is loaded with the eight bit literal ? k ? . the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. return return from subroutine syntax: [ label ] return operands: none operation: tos pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register ? f ? are rotated one bit to the left through the carry flag. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is stored back in register ? f ? . rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register ? f ? are rotated one bit to the right through the carry flag. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in reg- ister ? f ? . sleep syntax: [ label ]sleep operands: none operation: 00h wdt, 0 wdt prescaler, 1 to , 0 pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. register f c register f c
pic16f7x ds30325a-page 118 advance information ? 2000 microchip technology inc. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ( w) status affected: c, dc, z description: the w register is subtracted (2 ? s complement method) from the eight bit literal 'k'. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d [0,1] operation: (f) - (w) ( destination) status affected: c, dc, z description: subtract (2 ? s complement method) w register from register 'f'. if 'd' is 0, the result is stored in the w regis- ter. if 'd' is 1, the result is stored back in register 'f'. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d [0,1] operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) status affected: none description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0, the result is placed in w regis- ter. if 'd' is 1, the result is placed in register 'f'. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z description: the contents of the w register are xor ? ed with the eight bit lit- eral 'k'. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d [0,1] operation: (w) .xor. (f) ( destination) status affected: z description: exclusive or the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'.
? 2000 microchip technology inc. advance information ds30325a-page 119 pic16f7x 14.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm assembler - mplab-c17 and mplab-c18 c compilers - mplink/mplib linker/librarian simulators - mplab-sim software simulator emulators - mplab-ice real-time in-circuit emulator - icepic ? in-circuit debugger - mplab-icd for pic16f87x device programmers -pro mate ? ii universal programmer - picstart ? plus entry-level prototype programmer low-cost demonstration boards - picdem-1 - picdem-2 - picdem-3 - picdem-17 -k ee l oq ? 14.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows ? -based applica- tion which contains: multiple functionality -editor - simulator - programmer (sold separately) - emulator (sold separately) a full featured editor a project manager customizable tool bar and key mapping a status bar on-line help mplab allows you to: edit your source files (either assembly or ? c ? ) one touch assemble (or compile) and download to picmicro tools (automatically updates all project information) debug using: - source files - absolute listing file - object code the ability to use mplab with microchip ? s simulator, mplab-sim, allows a consistent platform and the abil- ity to easily switch from the cost-effective simulator to the full featured emulator with minimal retraining. 14.2 mpasm assembler mpasm is a full featured universal macro assembler for all picmicro mcu ? s. it can produce absolute code directly in the form of hex files for device program- mers, or it can generate relocatable objects for mplink. mpasm has a command line interface and a windows shell and can be used as a standalone application on a windows 3.x or greater system. mpasm generates relocatable object files, intel standard hex files, map files to detail memory usage and symbol reference, an absolute lst file which contains source lines and gen- erated machine code, and a cod file for mplab debugging. mpasm features include: mpasm and mplink are integrated into mplab projects. mpasm allows user defined macros to be created for streamlined assembly. mpasm allows conditional assembly for multi pur- pose source files. mpasm directives allow complete control over the assembly process. 14.3 mplab-c17 and mplab-c18 c compilers the mplab-c17 and mplab-c18 code development systems are complete ansi ? c ? compilers and inte- grated development environments for microchip ? s pic17cxxx and pic18cxxx family of microcontrol- lers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic16f7x ds30325a-page 120 advance information ? 2000 microchip technology inc. 14.4 mplink/mplib linker/librarian mplink is a relocatable linker for mpasm and mplab-c17 and mplab-c18. it can link relocatable objects from assembly or c source files along with pre- compiled libraries using directives from a linker script. mplib is a librarian for pre-compiled code to be used with mplink. when a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. this allows large libraries to be used efficiently in many dif- ferent applications. mplib manages the creation and modification of library files. mplink features include: mplink works with mpasm and mplab-c17 and mplab-c18. mplink allows all memory areas to be defined as sections to provide link-time flexibility. mplib features include: mplib makes linking easier because single librar- ies can be included instead of many smaller files. mplib helps keep code maintainable by grouping related modules together. mplib commands allow libraries to be created and modules to be added, listed, replaced, deleted, or extracted. 14.5 mplab-sim software simulator the mplab-sim software simulator allows code development in a pc host environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file or user-defined key press to any of the pins. the execution can be performed in single step, execute until break, or trace mode. mplab-sim fully supports symbolic debugging using mplab-c17 and mplab-c18 and mpasm. the soft- ware simulator offers the flexibility to develop and debug code outside of the laboratory environment mak- ing it an excellent multi-project software development tool. 14.6 mplab-ice high performance universal in-circuit emulator with mplab ide the mplab-ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). software control of mplab-ice is provided by the mplab integrated development environment (ide), which allows editing, ? make ? and download, and source debugging from a single environment. interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. the universal architecture of the mplab-ice allows expansion to support new picmicro microcon- trollers. the mplab-ice emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive development tools. the pc platform and microsoft ? windows 3.x/95/98 environment were chosen to best make these features available to you, the end user. mplab-ice 2000 is a full-featured emulator system with enhanced trace, trigger, and data monitoring fea- tures. both systems use the same processor modules and will operate across the full operating speed range of the picmicro mcu. 14.7 icepic icepic is a low-cost in-circuit emulation solution for the microchip technology pic16c5x, pic16c6x, pic16c7x, and pic16cxxx families of 8-bit one-time- programmable (otp) microcontrollers. the modular system can support different subsets of pic16c5x or pic16cxxx products through the use of interchange- able personality modules or daughter boards. the emulator is capable of emulating without target applica- tion circuitry being present. 14.8 mplab-icd in-circuit debugger microchip ? s in-circuit debugger, mplab-icd, is a pow- erful, low-cost run-time development tool. this tool is based on the flash pic16f877 and can be used to develop for this and other picmicro microcontrollers from the pic16cxxx family. mplab-icd utilizes the in-circuit debugging capability built into the pic16f87x. this feature, along with microchip ? s in-cir- cuit serial programming protocol, offers cost-effective in-circuit flash programming and debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. the mplab-icd is also a programmer for the flash pic16f87x family.
? 2000 microchip technology inc. advance information ds30325a-page 121 pic16f7x 14.9 pro mate ii universal programmer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii is ce compliant. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode the pro mate ii can read, verify or program picmicro devices. it can also set code-protect bits in this mode. 14.10 picstart plus entry level development system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and efficient. picstart plus supports all picmicro devices with up to 40 pins. larger pin count devices such as the pic16c92x, and pic17c76x may be supported with an adapter socket. picstart plus is ce compliant. 14.11 picdem-1 low-cost picmicro demonstration board the picdem-1 is a simple board which demonstrates the capabilities of several of microchip ? s microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample microcontrollers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test firm- ware. the user can also connect the picdem-1 board to the mplab-ice emulator and download the firmware to the emulator for testing. additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 14.12 picdem-2 low-cost pic16cxx demonstration board the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-plus, and easily test firmware. the mplab-ice emulator may also be used with the picdem-2 board to test firmware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 14.13 picdem-3 low-cost pic16cxxx demonstration board the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test firmware. the mplab-ice emulator may also be used with the picdem-3 board to test firm- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals.
pic16f7x ds30325a-page 122 advance information ? 2000 microchip technology inc. 14.14 picdem-17 the picdem-17 is an evaluation board that demon- strates the capabilities of several microchip microcon- trollers, including pic17c752, pic17c756, pic17c762, and pic17c766. all necessary hardware is included to run basic demo programs, which are sup- plied on a 3.5-inch disk. a programmed sample is included, and the user may erase it and program it with the other sample programs using the pro mate ii or picstart plus device programmers and easily debug and test the sample code. in addition, picdem-17 sup- ports down-loading of programs to and executing out of external flash memory on board. the picdem-17 is also usable with the mplab-ice or picmaster emu- lator, and all of the sample programs can be run and modified using either emulator. additionally, a gener- ous prototype area is available for user hardware. 14.15 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
? 2000 microchip technology inc. advance information ds30325a-page 123 pic16f7x table 14-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment mplab ? c17 compiler mplab ? c18 compiler mpasm/mplink emulators mplab ? -ice ** icepic ? low-cost in-circuit emulator debugger mplab ? -icd in-circuit debugger * * programmers picstart ? plus low-cost universal dev. kit ** pro mate ? ii universal programmer ** demo boards and eval kits picdem-1 ? picdem-2 ? ? picdem-3 picdem-14a picdem-17 k ee l oq ? evaluation kit k ee l oq transponder kit microid ? programmer ? s kit 125 khz microid developer ? s kit 125 khz anticollision microid developer ? s kit 13.56 mhz anticollision microid developer ? s kit mcp2510 can developer ? s kit * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? -icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77 ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
pic16f7x ds30325a-page 124 advance information ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. advance information ds30325a-page 125 pic16f7x 15.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ............... .-55 to +125 c storage temperature ............................................................................................................ .................. -65 c to +150 c voltage on any pin with respect to v ss (except v dd , mclr . and ra4) ......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ............................................................................................................ -0.3 to +6.5v voltage on mclr with respect to v ss (note 2)...............................................................................................0 to +13.5v voltage on ra4 with respect to vss ............................................................................................. ......................0 to +12v total power dissipation (note 1)............................................................................................... .................................1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta, portb, and porte (combined) (note 3) ...................................................200 ma maximum current sourced by porta, portb, and porte (combined) (note 3) ..............................................200 ma maximum current sunk by portc and portd (combined) (note 3) ..................................................................20 0 ma maximum current sourced by portc and portd (combined) (note 3).............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd - v oh ) x i oh } + (v o l x i ol ) 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a ? low ? level to the mclr pin, rather than pulling this pin directly to v ss . 3: portd and porte are not implemented on the pic16f73/76 devices. ? notice: stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16f7x ds30325a-page 126 advance information ? 2000 microchip technology inc. figure 15-1: pic16f7x voltage-frequency graph figure 15-2: pic16lf7x voltage-frequency graph frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 20 mhz 5.0 v 3.5 v 3.0 v 2.5 v 16 mhz frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 5.0 v 3.5 v 3.0 v 2.5 v f max = (12 mhz/v) (v ddappmin - 2.5 v) + 4 mhz note 1: v ddappmin is the minimum voltage of the picmicro ? device in the application. 4 mhz 10 mhz note 2: f max has a maximum frequency of 10mhz.
? 2000 microchip technology inc. advance information ds30325a-page 127 pic16f7x 15.1 dc characteristics pic16lf73/74/76/77 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial pic16f73/74/76/77 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial param no. sym characteristic min typ ? max units conditions d001 v dd supply voltage pic16lf7x 2.0 - 5.5 v all osc configurations (dc - 10 mhz) d001 d001a pic16f7x 4.0 v bor * - - 5.5 5.5 v v all configurations bor enabled (note 7) d002* v dr ram data retention voltage (note 1) -1.5-v d003 v por v dd start voltage to ensure internal power-on reset signal -v ss - v see section on power-on reset for details d004* sv dd v dd rise rate to ensure internal power-on reset signal 0.05 - - v/ms see section on power-on reset for details d005 v bor brown-out reset voltage 3.65 4.0 4.35 v boden bit in configuration word enabled d010 i dd supply current (note 2, 5) d010a pic16lf7x - - 0.6 20 2.0 35 ma a xt, rc osc configuration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc configuration f osc = 32 khz, v dd = 3.0v, wdt disabled d010 d013 pic16f7x - - 1.6 7 4 15 ma ma xt, rc osc configuration f osc = 4 mhz, v dd = 5.5v (note 4) hs osc configuration f osc = 20 mhz, v dd = 5.5v d015* di bor brown-out reset current (note 6) - 85 200 a bor enabled v dd = 5.0v legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 a to the specification. this value is from character- ization and is for design guidance only. this is not tested. 6: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached.
pic16f7x ds30325a-page 128 advance information ? 2000 microchip technology inc. d020 i pd power-down current (note 3, 5) d021 pic16lf7x - - 7.5 0.9 30 5 a a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, -40 c to +85 c d020 d021 pic16f7x - - 10.5 1.5 42 19 a a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -40 c to +85 c d023* di bor brown-out reset current (note 6) - 85 200 a bor enabled v dd = 5.0v pic16lf73/74/76/77 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial pic16f73/74/76/77 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial param no. sym characteristic min typ ? max units conditions legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 a to the specification. this value is from character- ization and is for design guidance only. this is not tested. 6: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached.
? 2000 microchip technology inc. advance information ds30325a-page 129 pic16f7x 15.2 d c characteristics: pic16f73/74/76/77 (industrial) pic16lf73/74/76/77 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial and operating voltage v dd range as described in dc spec section 15.1 and section 15.2. param no. sym characteristic min typ ? max units conditions v il input low voltage i/o ports d030 with ttl buffer v ss - 0.15v dd v for entire v dd range d030a v ss -0.8vv4.5v v dd 5.5v d031 with schmitt trigger buffer v ss -0.2v dd v d032 mclr , osc1 (in rc mode) v ss -0.2v dd v d033 osc1 (in xt and lp mode) v ss -0.3vv (note 1) osc1 (in hs mode) v ss -0.3v dd v (note 1) ports rc3 and rc4 d034 with schmitt trigger buffer v ss -0.3v dd v for entire v dd range v ih input high voltage i/o ports - d040 with ttl buffer 2.0 - v dd v4.5v v dd 5.5v d040a 0.25v dd + 0.8v -v dd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr 0.8v dd -v dd v d042a osc1 (in xt and lp mode) 1.6v - v dd v (note 1) osc1 (in hs mode) 0.7v dd -v dd v (note 1) d043 osc1 (in rc mode) 0.9v dd -v dd v ports rc3 and rc4 d044 with schmitt trigger buffer 0.7v dd -v dd v for entire v dd range d070 i purb portb weak pull-up current 50 250 400 av dd = 5v, v pin = v ss i il input leakage current (notes 2, 3) d060 i/o ports - - 1 avss v pin v dd , pin at hi-impedance d061 mclr , ra4/t0cki - - 5 avss v pin v dd d063 osc1 - - 5 avss v pin v dd , xt, hs and lp osc configuration v ol output low voltage d080 i/o ports - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d083 osc2/clkout (rc osc config) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c v oh output high voltage d090 i/o ports (note 3) v dd - 0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d092 osc2/clkout (rc osc config) v dd - 0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d150* v od open-drain high voltage --12vra4 pin legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16f7x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
pic16f7x ds30325a-page 130 advance information ? 2000 microchip technology inc. capacitive loading specs on output pins d100 c osc2 osc2 pin - - 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins and osc2 (in rc mode) - - 50 pf d102 c b scl, sda in i 2 c mode --400pf program flash memory d130 e p endurance - - 100 e/w 25 c at 5v d131 v pr v dd for read 2.0 - 5.5 v dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial and operating voltage v dd range as described in dc spec section 15.1 and section 15.2. param no. sym characteristic min typ ? max units conditions legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16f7x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
? 2000 microchip technology inc. advance information ds30325a-page 131 pic16f7x 15.3 timing parameter symbology the timing parameter symbols have been created fol- lowing one of the following formats: figure 15-3: load conditions 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 ? c l = 50 pf for all pins except osc2, but including portd and porte outputs as ports 15 pf for osc2 output note: portd and porte are not implemented on the pic16f73/76 devices. load condition 1 load condition 2
pic16f7x ds30325a-page 132 advance information ? 2000 microchip technology inc. figure 15-4: external clock timing osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 table 15-1: external clock timing requirements parameter no. sym characteristic min typ ? max units conditions f osc external clkin frequency (note 1) dc ? 1 mhz xt osc mode dc ? 20 mhz hs osc mode dc ? 32 khz lp osc mode oscillator frequency (note 1) dc ? 4 mhz rc osc mode 0.1 ? 4mhzxt osc mode 4 5 ? ? 20 200 mhz khz hs osc mode lp osc mode 1 t osc external clkin period (note 1) 1000 ?? ns xt osc mode 50 ?? ns hs osc mode 5 ?? ms lp osc mode oscillator period (note 1) 250 ?? ns rc osc mode 250 ? 10,000 ns xt osc mode 50 ? 250 ns hs osc mode 5 ?? ms lp osc mode 2 t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3 tos l, tos h external clock in (osc1) high or low time 500 ?? ns xt oscillator 2.5 ?? ms lp oscillator 15 ?? ns hs oscillator 4 to s r , to sf external clock in (osc1) rise or fall time ? ? 25 ns xt oscillator ? ? 50 ns lp oscillator ?? 15 ns hs oscillator legend: ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices.
? 2000 microchip technology inc. advance information ds30325a-page 133 pic16f7x figure 15-5: clkout and i/o timing table 15-2: clkout and i/o timing requirements note: refer to figure 15-3 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param no. sym characteristic min typ ? max units conditions 10* tosh2ckl osc1 to clkout ? 75 200 ns (note 1) 11* tosh2ckh osc1 to clkout ? 75 200 ns (note 1) 12* tckr clkout rise time ? 35 100 ns (note 1) 13* tckf clkout fall time ? 35 100 ns (note 1) 14* tckl2iov clkout to port out valid ?? 0.5t cy + 20 ns (note 1) 15* tiov2ckh port in valid before clkout t osc + 200 ?? ns (note 1) 16* tckh2ioi port in hold after clkout 0 ?? ns (note 1) 17* tosh2iov osc1 (q1 cycle) to port out valid ? 100 255 ns 18* tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) standard ( f ) 100 ?? ns extended ( lf ) 200 ?? ns 19* tiov2osh port input valid to osc1 (i/o in setup time) 0 ?? ns 20* tior port output rise time standard ( f ) ? 10 40 ns extended ( lf ) ?? 145 ns 21* tiof port output fall time standard ( f ) ? 10 40 ns extended ( lf ) ?? 145 ns 22 ?? * tinp int pin high or low time tcy ?? ns 23 ?? * trbp rb7:rb4 change int high or low time tcy ?? ns legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events, not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc .
pic16f7x ds30325a-page 134 advance information ? 2000 microchip technology inc. figure 15-6: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 15-7: brown-out reset timing table 15-3: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 15-3 for load conditions. v dd v bor 35 parameter no. sym characteristic min typ ? max units conditions 30 tmcl mclr pulse width (low) 2 ?? sv dd = 5v, -40 c to +85 c 31* twdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40 c to +85 c 32 tost oscillation start-up timer period ? 1024 t osc ?? t osc = osc1 period 33* tpwrt power-up timer period 28 72 132 ms v dd = 5v, -40 c to +85 c 34 tioz i/o hi-impedance from mclr low or watchdog timer reset ?? 2.1 s 35 t bor brown-out reset pulse width 100 ?? sv dd v bor (d005) legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
? 2000 microchip technology inc. advance information ds30325a-page 135 pic16f7x figure 15-8: timer0 and timer1 external clock timings table 15-4: timer0 and timer1 external clock requirements note: refer to figure 15-3 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1 param no. sym characteristic min typ ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ?? ns must also meet parameter 42 with prescaler 10 ?? ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ?? ns must also meet parameter 42 with prescaler 10 ?? ns 42* tt0p t0cki period no prescaler t cy + 40 ?? ns with prescaler greater of: 20 or t cy + 40 n ?? ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ?? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 standard( f )15 ?? ns extended( lf )25 ?? ns asynchronous standard( f )30 ?? ns extended( lf )50 ?? ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ?? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 standard( f )15 ?? ns extended( lf )25 ?? ns asynchronous standard( f )30 ?? ns extended( lf )50 ?? ns 47* tt1p t1cki input period synchronous standard( f ) greater of: 30 or t cy + 40 n ?? ns n = prescale value (1, 2, 4, 8) extended( lf ) greater of: 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous standard( f )60 ?? ns extended( lf ) 100 ?? ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ? 200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2tosc ? 7tosc ? legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16f7x ds30325a-page 136 advance information ? 2000 microchip technology inc. figure 15-9: capture/compare/pwm timings (ccp1 and ccp2) table 15-5: capture/compare/pwm requirements (ccp1 and ccp2) note: refer to figure 15-3 for load conditions. and rc2/ccp1 (capture mode) 50 51 52 53 54 rc1/t1osi/ccp2 and rc2/ccp1 (compare or pwm mode) rc1/t1osi/ccp2 param no. sym characteristic min typ ? max units conditions 50* tccl ccp1 and ccp2 input low time no prescaler 0.5t cy + 20 ?? ns with prescaler standard( f )10 ?? ns extended( lf )20 ?? ns 51* tcch ccp1 and ccp2 input high time no prescaler 0.5t cy + 20 ?? ns with prescaler standard( f )10 ?? ns extended( lf )20 ?? ns 52* tccp ccp1 and ccp2 input period 3t cy + 40 n ?? ns n = prescale value (1,4 or 16) 53* tccr ccp1 and ccp2 output rise time standard( f ) ? 10 25 ns extended( lf ) ? 25 50 ns 54* tccf ccp1 and ccp2 output fall time standard( f ) ? 10 25 ns extended( lf ) ? 25 45 ns legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
? 2000 microchip technology inc. advance information ds30325a-page 137 pic16f7x figure 15-10: parallel slave port timing (pic16f74/77 devices only) table 15-6: parallel slave port requirements (pic16f74/77 devices only) note: refer to figure 15-3 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65 parameter no. sym characteristic min typ ? max units conditions 62 tdtv2wrh data in valid before wr or cs (setup time) 20 25 ? ? ? ? ns ns extended range only 63* twrh2dti wr or cs to data in invalid (hold time) standard( f )20 ?? ns extended( lf )35 ?? ns 64 trdl2dtv rd and cs to data out valid ? ? ? ? 80 90 ns ns extended range only 65 trdh2dti rd or cs to data out invalid 10 ? 30 ns legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16f7x ds30325a-page 138 advance information ? 2000 microchip technology inc. figure 15-11: spi master mode timing (cke = 0, smp = 0) figure 15-12: spi master mode timing (cke = 1, smp = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 note: refer to figure 15-3 for load conditions. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb note: refer to figure 15-3 for load conditions.
? 2000 microchip technology inc. advance information ds30325a-page 139 pic16f7x figure 15-13: spi slave mode timing (cke = 0) figure 15-14: spi slave mode timing (cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 note: refer to figure 15-3 for load conditions. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 note: refer to figure 15-3 for load conditions.
pic16f7x ds30325a-page 140 advance information ? 2000 microchip technology inc. table 15-7: spi mode requirements figure 15-15: i 2 c bus start/stop bits timing param no. sym characteristic min typ ? max units conditions 70* tssl2sch, tssl2scl ss to sck or sck input t cy ?? ns 71* tsch sck input high time (slave mode) t cy + 20 ?? ns 72* tscl sck input low time (slave mode) t cy + 20 ?? ns 73* tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ?? ns 74* tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ?? ns 75* tdor sdo data output rise time standard( f ) extended( lf ) ? ? 10 25 25 50 ns ns 76* tdof sdo data output fall time ? 10 25 ns 77* tssh2doz ss to sdo output hi-impedance 10 ? 50 ns 78* tscr sck output rise time (master mode) standard( f ) extended( lf ) ? ? 10 25 25 50 ns ns 79* tscf sck output fall time (master mode) ? 10 25 ns 80* tsch2dov, tscl2dov sdo data output valid after sck edge standard( f ) extended( lf ) ? ? ? ? 50 145 ns ns 81* tdov2sch, tdov2scl sdo data output setup to sck edge t cy ?? ns 82* tssl2dov sdo data output valid after ss edge ?? 50 ns 83* tsch2ssh, tscl2ssh ss after sck edge 1.5t cy + 40 ?? ns legend: * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note : refer to figure 15-3 for load conditions. 91 92 93 scl sda start condition stop condition 90
? 2000 microchip technology inc. advance information ds30325a-page 141 pic16f7x table 15-8: i 2 c bus start/stop bits requirements figure 15-16: i 2 c bus data timing param no. sym characteristic min typ max units conditions 90* t su : sta start condition 100 khz mode 4700 ?? ns only relevant for repeated start condition setup time 400 khz mode 600 ?? 91* t hd : sta start condition 100 khz mode 4000 ?? ns after this period the first clock pulse is generated hold time 400 khz mode 600 ?? 92* t su : sto stop condition 100 khz mode 4700 ?? ns setup time 400 khz mode 600 ?? 93 t hd : sto stop condition 100 khz mode 4000 ?? ns hold time 400 khz mode 600 ?? * these parameters are characterized but not tested. note: refer to figure 15-3 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16f7x ds30325a-page 142 advance information ? 2000 microchip technology inc. table 15-9: i 2 c bus data requirements param. no. sym characteristic min max units conditions 100* t high clock high time 100 khz mode 4.0 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ? 101* t low clock low time 100 khz mode 4.7 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ? 102* t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10-400 pf 103* t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10-400 pf 90* t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91* t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period the first clock pulse is generated 400 khz mode 0.6 ? s 106* t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107* t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92* t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109* t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ?? ns 110* t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s cb bus capacitive loading ? 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c-bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement tsu:dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released.
? 2000 microchip technology inc. advance information ds30325a-page 143 pic16f7x figure 15-17: usart synchronous transmission (master/slave) timing table 15-10: usart synchronous transmission requirements figure 15-18: usart synchronous receive (master/slave) timing table 15-11: usart synchronous receive requirements note: refer to figure 15-3 for load conditions. 121 121 122 rc6/tx/ck rc7/rx/dt pin pin 120 param no. sym characteristic min typ ? max units conditions 120 tckh2dtv sync xmit (master & slave) clock high to data out valid standard( f ) ?? 80 ns extended( lf ) ?? 100 ns 121 tckrf clock out rise time and fall time (master mode) standard( f ) ?? 45 ns extended( lf ) ?? 50 ns 122 tdtrf data out rise time and fall time standard( f ) ?? 45 ns extended( lf ) ?? 50 ns ? : data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 15-3 for load conditions. 125 126 rc6/tx/ck rc7/rx/dt pin pin parameter no. sym characteristic min typ ? max units conditions 125 tdtv2ckl sync rcv (master & slave) data setup before ck (dt setup time) 15 ?? ns 126 tckl2dtl data hold after ck (dt hold time) 15 ?? ns ? : data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16f7x ds30325a-page 144 advance information ? 2000 microchip technology inc. table 15-12: a/d converter characteristics: pic16f7x (industrial) pic16lf7x (industrial) param no. sym characteristic min typ ? max units conditions a01 n r resolution pic16f7x ?? 8 bits bit v ref = v dd = 5.12v, v ss v ain v ref pic16lf7x ?? 8 bits bit v ref = v dd = 2.0v a02 e abs total absolute error ?? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error ?? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error ?? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a05 e fs full scale error ?? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error ?? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 ? monotonicity (note 3) ? guaranteed ?? v ss v ain v ref a20 v ref reference voltage 2.0v ? v dd + 0.3 v a25 v ain analog input voltage v ss - 0.3 ? v ref + 0.3 v a30 z ain recommended impedance of analog voltage source ?? 10.0 k ? a40 i ad a/d conversion current (v dd ) pic16f7x ? 180 ? a average current con- sumption when a/d is on (note 1) . pic16lf7x ? 90 ? a a50 i ref v ref input current (note 2) 10 ? ? ? 1000 10 a a during v ain acquisition. based on differential of v hold to v ain to charge c hold , see section 12.1. during a/d conversion cycle. * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from the ra3 pin or the v dd pin, whichever is selected as a reference input. 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes.
? 2000 microchip technology inc. advance information ds30325a-page 145 pic16f7x figure 15-19: a/d conversion timing table 15-13: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 134 param no. sym characteristic min typ ? max units conditions 130 t ad a/d clock period pic16f7x 1.6 ?? st osc based, v ref 3.0v pic16lf7x 2.0 ?? st osc based, 2.0v v ref 5.5v pic16f7x 2.0 4.0 6.0 s a/d rc mode pic16lf7x 3.0 6.0 9.0 s a/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) 9 ? 9t ad 132 t acq acquisition time 5* ?? s the minimum time is the amplifier settling time. this may be used if the ? new ? input voltage has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start ? t osc /2 ?? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 135 t swc switching from convert sample time 1.5 ? ? t ad * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 12.1 for min. conditions.
pic16f7x ds30325a-page 146 advance information ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. advance information ds30325a-page 147 pic16f7x 16.0 dc and ac characteristics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested . in some graphs or tables, the data presented are out- side specified operating range (i.e., outside specified v dd range). this is for information only and devices are ensured to operate properly only within the speci- fied range. the data presented in this section is a statistical sum- mary of data collected on units from different lots over a period of time and matrix samples. ? typical ? repre- sents the mean of the distribution at 25 c. ? max ? or ? min ? represents (mean + 3 ) or (mean - 3 ), respectively, where is standard deviation over the whole tempera- ture range. graphs and tables not available at this time.
pic16f7x ds30325a-page 148 advance information ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. advance information ds30325a-page 149 pic16f7x 17.0 packaging information 17.1 package marking information 28-lead soic yywwnnn example xxxxxxxxxxxxxxxxx yywwnnn 28-lead pdip (skinny dip) example xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx 0017hat pic16f77-i/sp xxxxxxxxxxxxxxxxxxxx 0010saa pic16f76-i/so legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ? 01 ? ) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer specific information. * standard marking consists of microchip part number, year code, week code, and traceability code. for marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. 28-lead ssop yywwnnn example xxxxxxxxxxxx xxxxxxxxxxxx 0010sbp pic16f73-i/ss
pic16f7x ds30325a-page 150 advance information ? 2000 microchip technology inc. package marking information (cont ? d) xxxxxxxxxxxxxxxxxx yywwnnn 40-lead pdip example 44-lead tqfp xxxxxxxxxx yywwnnn xxxxxxxxxx example 44-lead plcc example xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn xxxxxxxxxx xxxxxxxxxx pic16f77-i/p 0012saa i/pt 0011hat pic16f77- 0003sat pic16f77-i/l
? 2000 microchip technology inc. advance information ds30325a-page 151 pic16f7x 17.2 28-lead skinny plastic dual in-line (sp) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb e p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. significant characteristic
pic16f7x ds30325a-page 152 advance information ? 2000 microchip technology inc. 17.3 28-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle top 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c 45 h a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic
? 2000 microchip technology inc. advance information ds30325a-page 153 pic16f7x 17.4 28-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-150 drawing no. c04-073 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 10.34 10.20 10.06 .407 .402 .396 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.10 7.85 7.59 .319 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters* inches units 2 1 d p n b e1 e l c a2 a1 a significant characteristic
pic16f7x ds30325a-page 154 advance information ? 2000 microchip technology inc. 17.5 40-lead plastic dual in-line (p) ? 600 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 17.27 16.51 15.75 .680 .650 .620 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.27 0.76 .070 .050 .030 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.05 .135 .130 .120 l tip to seating plane 52.45 52.26 51.94 2.065 2.058 2.045 d overall length 14.22 13.84 13.46 .560 .545 .530 e1 molded package width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 4.06 3.81 3.56 .160 .150 .140 a2 molded package thickness 4.83 4.45 4.06 .190 .175 .160 a top to seating plane 2.54 .100 p pitch 40 40 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 1 2 d n e1 c eb e p l b b1 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: mo-011 drawing no. c04-016 significant characteristic
? 2000 microchip technology inc. advance information ds30325a-page 155 pic16f7x 17.6 44-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-076 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) a a1 a2 e e1 #leads=n1 p b d1 d n 1 2 c l units inches millimeters* dimension limits min nom max min nom max number of pins n 44 44 pitch p .031 0.80 overall height a .039 .043 .047 1.00 1.10 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .463 .472 .482 11.75 12.00 12.25 overall length d .463 .472 .482 11.75 12.00 12.25 molded package width e1 .390 .394 .398 9.90 10.00 10.10 molded package length d1 .390 .394 .398 9.90 10.00 10.10 pins per side n1 11 11 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .012 .015 .017 0.30 0.38 0.44 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 ch x 45 significant characteristic
pic16f7x ds30325a-page 156 advance information ? 2000 microchip technology inc. 17.7 44-lead plastic leaded chip carrier (l) ? square (plcc) ch2 x 45 ch1 x 45 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.53 0.51 0.33 .021 .020 .013 b 0.81 0.74 0.66 .032 .029 .026 b1 upper lead width 0.33 0.27 0.20 .013 .011 .008 c lead thickness 11 11 n1 pins per side 16.00 15.75 14.99 .630 .620 .590 d2 footprint length 16.00 15.75 14.99 .630 .620 .590 e2 footprint width 16.66 16.59 16.51 .656 .653 .650 d1 molded package length 16.66 16.59 16.51 .656 .653 .650 e1 molded package width 17.65 17.53 17.40 .695 .690 .685 d overall length 17.65 17.53 17.40 .695 .690 .685 e overall width 0.25 0.13 0.00 .010 .005 .000 ch2 corner chamfer (others) 1.27 1.14 1.02 .050 .045 .040 ch1 corner chamfer 1 0.86 0.74 0.61 .034 .029 .024 a3 side 1 chamfer height 0.51 .020 a1 standoff a2 molded package thickness 4.57 4.39 4.19 .180 .173 .165 a overall height 1.27 .050 p pitch 44 44 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 c e2 2 d d1 n #leads=n1 e e1 1 p a3 a 35 b1 b d2 a1 .145 .153 .160 3.68 3.87 4.06 .028 .035 0.71 0.89 lower lead width * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: mo-047 drawing no. c04-048 significant characteristic
? 2000 microchip technology inc. advance information ds30325a-page 157 pic16f7x appendix a: revision history appendix b: device differences the differences between the devices in this data sheet are listed in table b-1. appendix c: conversion considerations considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in table c-1. version date revision description a 2000 this is a new data sheet. however, these devices are similar to the pic16c7x devices found in the pic16c7x data sheet (ds30390) or the pic16f87x devices (ds30292). table b-1: device differences difference pic16f76/73 pic16f77/74 a/d 5 channels, 8-bits 8 channels, 8-bits parallel slave port no yes packages 28-pin pdip, 28-pin soic, 28-pin ssop 40-pin pdip, 44-pin tqfp, 44-pin plcc table c-1: conversion considerations characteristic pic16c7x pic16f87x pic16f7x pins 28/40 28/40 28/40 timers 3 3 3 interrupts 11 or 12 13 or 14 11 or 12 communication psp, usart, ssp (spi, i 2 c slave) psp, usart, ssp (spi, i 2 c master/slave) psp, usart, ssp (spi, i 2 c slave) frequency 20 mhz 20 mhz 20 mhz a/d 8-bit 10-bit 8-bit ccp 2 2 2 program memory 4k, 8k eprom 4k, 8k flash (1,000 e/w cycles) 4k, 8k flash (100 e/w cycles) ram 192, 368 bytes 192, 368 bytes 192, 368 bytes eeprom data none 128, 256 bytes none other ? in-circuit debugger, low voltage programming ?
pic16f7x ds30325a-page 158 advance information ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. advance information ds30325a-page 159 pic16f7x index a a/d ..................................................................................... 89 adcon0 register ...................................................... 89 adcon1 register ...................................................... 90 analog input model block diagram ............................ 92 analog port pins ...................................... 7, 8, 9, 37, 38 analog-to-digital converter ........................................ 89 block diagram ............................................................ 91 configuring analog port pins ..................................... 93 configuring the interrupt ............................................ 91 configuring the module .............................................. 91 conversion clock ....................................................... 93 conversions ............................................................... 93 converter characteristics ........................................ 144 effects of a reset .................................................... 93 faster conversion - lower resolution tradeoff ........ 93 internal sampling switch (rss) impedance ............... 92 operation during sleep ........................................... 93 sampling requirements ............................................. 92 source impedance ..................................................... 92 timing diagram ........................................................ 145 using the ccp trigger ............................................... 93 absolute maximum ratings ............................................. 125 ack .............................................................................. 67, 69 adres register .......................................................... 15, 89 analog port pins. see a/d application notes an552 (implementing wake-up on key strokes using pic16f7x) ................................................................. 31 an556 (table reading using pic16cxx .................. 26 an578 (use of the ssp module in the i 2 c multi-master environment) .............................................................. 61 architecture pic16f73/pic16f76 block diagram ........................... 5 pic16f74/pic16f77 block diagram ........................... 6 assembler mpasm assembler .................................................. 119 b banking, data memory ...................................................... 12 bf ................................................................................ 62, 67 block diagrams a/d ............................................................................. 91 analog input model .................................................... 92 capture ...................................................................... 57 compare .................................................................... 58 i 2 c mode .................................................................... 67 pwm .......................................................................... 58 ssp in i 2 c mode ........................................................ 67 ssp in spi mode ....................................................... 64 timer0/wdt prescaler .............................................. 45 timer2 ........................................................................ 53 usart receive ......................................................... 79 usart transmit ........................................................ 77 bor. see brown-out reset brgh bit ............................................................................ 75 brown-out reset (bor) ............................... 95, 99, 101, 102 buffer full status bit, bf .................................................... 62 c capture/compare/pwm capture block diagram ................................................... 57 ccp1con register ........................................... 56 ccp1if .............................................................. 57 mode ................................................................. 57 prescaler ........................................................... 57 ccp timer resources ............................................... 55 compare block diagram ................................................... 58 mode ................................................................. 58 software interrupt mode .................................... 58 special event trigger ........................................ 58 special trigger output of ccp1 ........................ 58 special trigger output of ccp2 ........................ 58 interaction of two ccp modules ............................... 55 section ....................................................................... 55 special event trigger and a/d conversions ............. 58 capture/compare/pwm (ccp) ccp1 rc2/ccp1 pin ................................................. 7, 8 ccp2 rc1/t1osi/ccp2 pin ..................................... 7, 8 pwm block diagram ................................................. 58 pwm mode ................................................................ 58 ccp1con ......................................................................... 17 ccp2con ......................................................................... 17 ccpr1h register .................................................. 15, 17, 55 ccpr1l register ........................................................ 17, 55 ccpr2h register ........................................................ 15, 17 ccpr2l register ........................................................ 15, 17 ccpxm0 bit ........................................................................ 56 ccpxm1 bit ........................................................................ 56 ccpxm2 bit ........................................................................ 56 ccpxm3 bit ........................................................................ 56 ccpxx bit .......................................................................... 56 ccpxy bit .......................................................................... 56 cke ................................................................................... 62 ckp ................................................................................... 63 clock polarity select bit, ckp ............................................ 63 code examples call of a subroutine in page 1 from page 0 .............. 26 indirect addressing .................................................... 27 code protection ......................................................... 95, 110 computed goto ............................................................... 26 configuration bits .............................................................. 95 conversion considerations .............................................. 157 d d/a ..................................................................................... 62 data memory ..................................................................... 12 bank select (rp1:rp0 bits) ...................................... 12 general purpose registers ....................................... 12 register file map ................................................ 13, 14 special function registers ........................................ 15 data/address bit, d/a ........................................................ 62 dc characteristics ........................................................... 127 development support ...................................................... 119 device differences ........................................................... 157 device overview .................................................................. 5 direct addressing .............................................................. 27 e electrical characteristics ................................................. 125 errata ................................................................................... 4 external clock input (ra4/t0cki). see timer0 external interrupt input (rb0/int). see interrupt sources
pic16f7x ds30325a-page 160 advance information ? 2000 microchip technology inc. f firmware instructions ....................................................... 111 fsr register .................................................... 15, 16, 17, 27 i i/o ports ............................................................................. 29 i 2 c addressing ................................................................. 68 block diagram ............................................................ 67 i 2 c operation ............................................................. 67 master mode .............................................................. 71 mode .......................................................................... 67 mode selection .......................................................... 67 multi-master mode ..................................................... 71 reception ................................................................... 69 reception timing diagram ........................................ 69 scl and sda pins ..................................................... 67 slave mode ................................................................ 67 transmission .............................................................. 70 i 2 c (ssp module) timing diagram, data .............................................. 141 timing diagram, start/stop bits ............................... 140 id locations ............................................................... 95, 110 in-circuit serial programming (icsp) ........................ 95, 110 indf ................................................................................... 17 indf register ........................................................ 15, 16, 27 indirect addressing ............................................................ 27 fsr register ............................................................. 12 instruction format ............................................................ 111 instruction set .................................................................. 111 addlw .................................................................... 113 addwf .................................................................... 113 andlw .................................................................... 113 andwf .................................................................... 113 bcf .......................................................................... 113 bsf .......................................................................... 113 btfsc ..................................................................... 114 btfss ..................................................................... 114 call ........................................................................ 114 clrf ........................................................................ 114 clrw ...................................................................... 114 clrwdt .................................................................. 114 comf ...................................................................... 115 decf ....................................................................... 115 decfsz ................................................................... 115 goto ...................................................................... 115 incf ......................................................................... 115 incfsz .................................................................... 115 iorlw ..................................................................... 116 iorwf ..................................................................... 116 movf ....................................................................... 116 movlw ................................................................... 116 movwf ................................................................... 116 nop ......................................................................... 116 retfie .................................................................... 117 retlw .................................................................... 117 return .................................................................. 117 rlf .......................................................................... 117 rrf .......................................................................... 117 sleep ..................................................................... 117 sublw .................................................................... 118 subwf .................................................................... 118 swapf .................................................................... 118 xorlw .................................................................... 118 xorwf .................................................................... 118 summary table ....................................................... 112 int interrupt (rb0/int). see interrupt sources intcon ............................................................................. 17 intcon register ............................................................... 20 gie bit ....................................................................... 20 inte bit ......................................................... 20, 21, 22 intf bit ..................................................................... 20 rbif bit ......................................................... 20, 21, 31 t0ie bit ...................................................................... 20 internal sampling switch (rss) impedance ....................... 92 interrupt sources ....................................................... 95, 105 block diagram ......................................................... 105 interrupt on change (rb7:rb4 ) ............................... 31 rb0/int pin, external ...................................... 7, 8, 106 tmr0 overflow ........................................................ 106 usart receive/transmit complete ......................... 73 interrupts synchronous serial port interrupt .............................. 22 interrupts, context saving during .................................... 106 interrupts, enable bits global interrupt enable (gie bit) ....................... 20, 105 interrupt on change (rb7:rb4) enable (rbie bit) . 106 rb0/int enable (inte bit) ............................ 20, 21, 22 tmr0 overflow enable (t0ie bit) ............................. 20 interrupts, flag bits interrupt on change (rb7:rb4) flag (rbif bit) . 20, 21, 31, 106 rb0/int flag (intf bit) ............................................ 20 tmr0 overflow flag (t0if bit) ................................ 106 k keeloq ? evaluation and programming tools ................ 122 l loading of pc .................................................................... 26 m master clear (mclr ) ....................................................... 7, 8 mclr reset, normal operation ................ 99, 101, 102 mclr reset, sleep ................................. 99, 101, 102 memory organization data memory ............................................................. 12 program memory ....................................................... 11 mplab integrated development environment software . 119 o opcode field descriptions ............................................ 111 option ............................................................................. 17 option_reg register ..................................................... 19 intedg bit ................................................................ 19 ps2:ps0 bits ............................................................. 19 psa bit ................................................................ 19, 20 rbpu bit ................................................................... 19 t0cs bit .................................................................... 19 t0se bit .................................................................... 19 osc1/clkin pin ............................................................. 7, 8 osc2/clkout pin ......................................................... 7, 8 oscillator configuration ............................................... 95, 97 hs ...................................................................... 97, 101 lp ...................................................................... 97, 101 rc ............................................................... 97, 98, 101 xt ...................................................................... 97, 101 oscillator, wdt ................................................................ 107 output of tmr2 ................................................................. 53
? 2000 microchip technology inc. advance information ds30325a-page 161 pic16f7x p p ......................................................................................... 62 packaging ........................................................................ 149 paging, program memory ............................................ 11, 26 parallel slave port (psp) ......................................... 9, 34, 38 block diagram ............................................................ 38 re0/rd /an5 pin .............................................. 9, 37, 38 re1/wr /an6 pin ............................................. 9, 37, 38 re2/cs /an7 pin .............................................. 9, 37, 38 read waveforms ....................................................... 39 select (pspmode bit) .................................. 34, 35, 38 write waveforms ....................................................... 39 pcfg0 bit .......................................................................... 90 pcfg1 bit .......................................................................... 90 pcfg2 bit .......................................................................... 90 pcl register .................................................... 15, 16, 17, 26 pclath register ............................................ 15, 16, 17, 26 pcon register .................................................... 17, 25, 100 por bit ...................................................................... 25 pic16f76 pinout description ............................................... 7 picdem-1 low-cost picmicro demo board ................... 121 picdem-2 low-cost pic16cxx demo board ................ 121 picdem-3 low-cost pic16cxxx demo board .............. 121 picstart ? plus entry level development system ...... 121 pie1 register ............................................................... 17, 21 pie2 register ............................................................... 17, 23 pinout descriptions pic16f73/pic16f76 .................................................... 7 pic16f74/pic16f77 .................................................... 8 pir1 register ..................................................................... 22 pir2 register ..................................................................... 24 pop ................................................................................... 26 por. see power-on reset porta ....................................................................... 7, 8, 17 analog port pins ...................................................... 7, 8 initialization ................................................................ 29 porta register ........................................................ 29 ra3 ra0 and ra5 port pins ..................................... 29 ra4/t0cki pin ................................................... 7, 8, 29 ra5/ss /an4 pin ...................................................... 7, 8 trisa register .......................................................... 29 porta register ................................................................ 15 portb ....................................................................... 7, 8, 17 portb register ........................................................ 31 pull-up enable (rbpu bit) ......................................... 19 rb0/int edge select (intedg bit) ........................... 19 rb0/int pin, external ...................................... 7, 8, 106 rb3:rb0 port pins .................................................... 31 rb7:rb4 interrupt on change ................................. 106 rb7:rb4 interrupt on change enable (rbie bit) .... 106 rb7:rb4 interrupt on change flag (rbif bit) ... 20, 21, 31, 106 rb7:rb4 port pins .................................................... 31 trisb register .......................................................... 31 portb register ................................................................ 15 portc ...................................................................... 7, 8, 17 block diagram ............................................................ 33 portc register ........................................................ 33 rc0/t1oso/t1cki pin ........................................... 7, 8 rc1/t1osi/ccp2 pin .............................................. 7, 8 rc2/ccp1 pin ......................................................... 7, 8 rc3/sck/scl pin ................................................... 7, 8 rc4/sdi/sda pin .................................................... 7, 8 rc5/sdo pin ........................................................... 7, 8 rc6/tx/ck pin .................................................. 7, 8, 74 rc7/rx/dt pin ........................................... 7, 8, 74, 75 trisc register ................................................... 33, 73 portc register ................................................................ 15 portd .................................................................... 9, 17, 38 block diagram ........................................................... 34 parallel slave port (psp) function ............................ 34 portd register ........................................................ 34 trisd register ......................................................... 34 portd register ................................................................ 15 porte .......................................................................... 9, 17 analog port pins .............................................. 9, 37, 38 block diagram ........................................................... 35 input buffer full status (ibf bit) ................................ 36 input buffer overflow (ibov bit) ................................ 36 porte register ........................................................ 35 psp mode select (pspmode bit) ................ 34, 35, 38 re0/rd /an5 pin ............................................. 9, 37, 38 re1/wr /an6 pin ............................................ 9, 37, 38 re2/cs /an7 pin ............................................. 9, 37, 38 trise register .......................................................... 35 porte register ................................................................ 15 postscaler, wdt assignment (psa bit) .......................................... 19, 20 rate select (ps2:ps0 bits) ....................................... 19 power-down mode. see sleep power-on reset (por) ........................ 95, 99, 100, 101, 102 oscillator start-up timer (ost) ......................... 95, 100 por status (por bit) ............................................... 25 power control (pcon) register .............................. 100 power-down (pd bit) ................................................. 99 power-up timer (pwrt) ................................... 95, 100 time-out (to bit) ................................................. 18, 99 time-out sequence on power-up .................... 103, 104 pr2 .................................................................................... 17 pr2 register ............................................................... 16, 53 prescaler, timer0 assignment (psa bit) .......................................... 19, 20 rate select (ps2:ps0 bits) ....................................... 19 pro mate ? ii universal programmer ........................... 121 program counter reset conditions ..................................................... 101 program memory ............................................................... 11 interrupt vector .......................................................... 11 paging ................................................................. 11, 26 program memory map ............................................... 11 reset vector .............................................................. 11 program verification ........................................................ 110 programming pin (vpp) ................................................... 7, 8 programming, device instructions ................................... 111 push ................................................................................. 26 r r/w .................................................................................... 62 r/w bit ................................................................... 68, 69, 70 ram. see data memory rcreg .............................................................................. 17 rcsta register .......................................................... 17, 74 oerr bit ................................................................... 74 spen bit .................................................................... 73 sren bit ................................................................... 74 read/write bit information, r/w ........................................ 62 receive overflow indicator bit, sspov ............................. 63 register file ....................................................................... 12 register file map ......................................................... 13, 14
pic16f7x ds30325a-page 162 advance information ? 2000 microchip technology inc. registers fsr summary ............................................................ 17 indf summary ............................................................ 17 intcon summary ............................................................ 17 option summary ............................................................ 17 pcl summary ............................................................ 17 pclath summary ............................................................ 17 portb summary ............................................................ 17 sspstat ................................................................... 62 status summary ............................................................ 17 summary .................................................................... 15 tmr0 summary ............................................................ 17 trisb summary ............................................................ 17 reset ......................................................................... 95, 99 reset block diagram ............................................................ 99 brown-out reset (bor). see brown-out reset (bor) mclr reset. see mclr power-on reset (por). see power-on reset (por) reset conditions for all registers ........................... 102 reset conditions for pcon register ....................... 101 reset conditions for program counter .................... 101 reset conditions for status register ................... 101 wdt reset. see watchdog timer (wdt) revision history ............................................................... 157 s s ......................................................................................... 62 sci. see usart scl .................................................................................... 67 serial communication interface. see usart slave mode scl ............................................................................ 67 sda ............................................................................ 67 sleep .................................................................. 95, 99, 108 smp ................................................................................... 62 software simulator (mplab-sim) .................................... 120 spbrg ............................................................................... 17 spbrg register ................................................................ 16 special features of the cpu .............................................. 95 special function registers ................................................ 15 pic16f73 ................................................................... 15 pic16f74 ................................................................... 15 speed, operating ................................................................. 1 spi block diagram ............................................................ 64 master mode timing .................................................. 65 serial clock ................................................................ 61 serial data in ............................................................. 61 serial data out .......................................................... 61 slave mode timing .................................................... 65 slave mode timing diagram ...................................... 65 slave select ............................................................... 61 spi mode ................................................................... 61 sspcon .................................................................... 63 sspstat ................................................................... 62 spi clock edge select bit, cke ........................................ 62 spi data input sample phase select bit, smp ................. 62 ssp module overview ....................................................... 61 ra5/ss /an4 pin ...................................................... 7, 8 rc3/sck/scl pin ................................................... 7, 8 rc4/sdi/sda pin .................................................... 7, 8 rc5/sdo pin ........................................................... 7, 8 section ....................................................................... 61 sspcon ................................................................... 63 sspstat .................................................................. 62 sspadd register .............................................................. 17 sspbuf ............................................................................ 17 sspbuf register .............................................................. 15 sspcon ............................................................................ 63 sspcon register ............................................................. 15 sspen ............................................................................... 63 sspif ................................................................................ 22 sspm3:sspm0 ................................................................. 63 sspov ........................................................................ 63, 67 sspstat register ................................................ 16, 17, 62 stack .................................................................................. 26 overflows ................................................................... 26 underflow .................................................................. 26 start bit, s .......................................................................... 62 status register ........................................................ 17, 18 dc bit .................................................................. 18, 36 irp bit ....................................................................... 18 pd bit ........................................................................ 99 to bit .................................................................. 18, 99 z bit ..................................................................... 18, 36 stop bit, p .......................................................................... 62 synchronous serial port enable bit, sspen ..................... 63 synchronous serial port interrupt ...................................... 22 synchronous serial port mode select bits, sspm3:sspm0 . 63 synchronous serial port module ....................................... 61 synchronous serial port status register .......................... 62 t t1ckps0 bit ...................................................................... 49 t1ckps1 bit ...................................................................... 49 t1con ............................................................................... 17 t1con register .......................................................... 17, 49 t1oscen bit ..................................................................... 49 t1sync bit ........................................................................ 49 t2ckps0 bit ...................................................................... 53 t2ckps1 bit ...................................................................... 53 t2con register .......................................................... 17, 53 t ad ..................................................................................... 93 timer0 clock source edge select (t0se bit) ....................... 19 clock source select (t0cs bit) ................................. 19 overflow enable (t0ie bit) ........................................ 20 overflow flag (t0if bit) ........................................... 106 overflow interrupt .................................................... 106 ra4/t0cki pin, external clock ............................... 7, 8 timer1 ................................................................................ 49 rc0/t1oso/t1cki pin ........................................... 7, 8 rc1/t1osi/ccp2 pin ............................................. 7, 8 timers timer0 external clock ................................................... 46 interrupt ............................................................. 45 prescaler ........................................................... 46 prescaler block diagram ................................... 45
? 2000 microchip technology inc. advance information ds30325a-page 163 pic16f7x section ............................................................... 45 t0cki ................................................................. 46 timer1 asynchronous counter mode ............................ 51 capacitor selection ............................................ 51 operation in timer mode ................................... 50 oscillator ............................................................ 51 prescaler ............................................................ 51 resetting of timer1 registers ........................... 51 resetting timer1 using a ccp trigger output .. 51 synchronized counter mode ............................. 50 t1con ............................................................... 49 tmr1h .............................................................. 51 tmr1l ............................................................... 51 timer2 block diagram ................................................... 53 postscaler .......................................................... 53 prescaler ............................................................ 53 t2con ............................................................... 53 timing diagrams brown-out reset ...................................................... 134 capture/compare/pwm ........................................... 136 clkout and i/o ...................................................... 133 i 2 c reception (7-bit address) .................................... 69 power-up timer ....................................................... 134 reset ........................................................................ 134 spi master mode ....................................................... 65 spi slave mode (cke = 1) ........................................ 65 spi slave mode timing (cke = 0) ............................ 65 start-up timer .......................................................... 134 time-out sequence on power-up .................... 103, 104 timer0 ...................................................................... 135 timer1 ...................................................................... 135 usart asynchronous master transmission ............. 78 usart asynchronous reception .............................. 79 usart synchronous receive ................................. 143 usart synchronous reception ................................ 85 usart synchronous transmission .................. 83, 143 wake-up from sleep via interrupt .......................... 109 watchdog timer ....................................................... 134 timing diagrams and specifications a/d conversion ........................................................ 145 i 2 c bus data ............................................................ 141 i 2 c bus start/stop bits ............................................. 140 tmr0 ................................................................................. 17 tmr0 register ................................................................... 15 tmr1cs bit ....................................................................... 49 tmr1h ............................................................................... 17 tmr1h register ................................................................ 15 tmr1l ............................................................................... 17 tmr1l register ................................................................. 15 tmr1on bit ....................................................................... 49 tmr2 ................................................................................. 17 tmr2 register ................................................................... 15 tmr2on bit ....................................................................... 53 toutps0 bit ...................................................................... 53 toutps1 bit ...................................................................... 53 toutps2 bit ...................................................................... 53 toutps3 bit ...................................................................... 53 trisa ................................................................................ 17 trisa register .................................................................. 16 trisb ................................................................................ 17 trisb register .................................................................. 16 trisc ................................................................................ 17 trisc register .................................................................. 16 trisd ................................................................................ 17 trisd register .................................................................. 16 trise ................................................................................ 17 trise register ............................................................ 16, 35 ibf bit ........................................................................ 36 ibov bit ..................................................................... 36 pspmode bit ............................................... 34, 35, 38 txreg .............................................................................. 17 txsta ............................................................................... 17 txsta register ................................................................. 73 sync bit ............................................................. 73, 74 trmt bit ................................................................... 73 tx9 bit ....................................................................... 73 tx9d bit .................................................................... 73 txen bit .............................................................. 73, 89 u ua ...................................................................................... 62 universal synchronous asynchronous receiver transmitter. see usart update address bit, ua ..................................................... 62 usart .............................................................................. 73 asynchronous mode .................................................. 77 receive block diagram ..................................... 81 asynchronous receiver ............................................. 79 asynchronous reception ........................................... 80 asynchronous transmitter ......................................... 77 baud rate generator (brg) ..................................... 75 baud rate formula ........................................... 75 baud rates, asynchronous mode (brgh=0) ... 76 sampling ........................................................... 75 mode select (sync bit) ...................................... 73, 74 overrun error (oerr bit) .......................................... 74 rc6/tx/ck pin ........................................................ 7, 8 rc7/rx/dt pin ....................................................... 7, 8 rcsta register ........................................................ 74 receive block diagram ............................................. 79 serial port enable (spen bit) ................................... 73 single receive enable (sren bit) ............................ 74 synchronous master mode ........................................ 82 synchronous master reception ................................ 84 synchronous master transmission ........................... 82 synchronous slave mode .......................................... 86 transmit block diagram ............................................ 77 transmit data, 9th bit (tx9d) ................................... 73 transmit enable (txen bit) ................................ 73, 89 transmit enable, nine-bit (tx9 bit) ........................... 73 transmit shift register status (trmt bit) ................ 73 txsta register ......................................................... 73 w wake-up from sleep ................................................ 95, 108 interrupts ......................................................... 101, 102 mclr reset ............................................................ 102 timing diagram ....................................................... 109 wdt reset .............................................................. 102 watchdog timer (wdt) ............................................. 95, 107 block diagram ......................................................... 107 enable (wdte bit) .................................................. 107 postscaler. see postscaler, wdt programming considerations .................................. 107 rc oscillator ........................................................... 107 time-out period ....................................................... 107 wdt reset, normal operation .................. 99, 101, 102 wdt reset, sleep .................................. 99, 101, 102 wcol ................................................................................ 63
pic16f7x ds30325a-page 164 advance information ? 2000 microchip technology inc. write collision detect bit, wcol ....................................... 63 www, on-line support ....................................................... 4
? 2000 microchip technology inc. advance information ds30325a-page 165 pic16f7x on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user ? s guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmicro, picstart, picmaster, pro mate and mplab are registered trademarks of microchip technology incorpo- rated in the u.s.a. and other countries. flex rom, microid and fuzzy lab are trademarks and sqtp is a ser- vice mark of microchip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. 000815
pic16f7x ds30325a-page 166 advance information ? 2000 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30325a pic16f7x 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products?
? 2000 microchip technology inc. advance information ds30325a-page 167 pic16f7x pic16f7x product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. sales and support part no. x /xx xxx pattern package temperature range device device pic16f7x (1) , pic16f7xt (1) ; v dd range 4.0v to 5.5v pic16lf7x (1) , pic16lf7xt (1) ; v dd range 2.0v to 5.5v temperature range i = -40 c to +85 c (industrial) package pt = tqfp (thin quad flatpack) so = soic sp = skinny plastic dip p=pdip l=plcc ss = ssop pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic16f77-i/p 301 = commercial temp., pdip package, normal v dd limits, qtp pattern #301. b) pic16lf76-i/so = industrial temp., soic package, 200 khz, extended v dd limits. c) pic16f74-i/p = industrial temp., pdip pack- age, normal v dd limits. note 1: f = cmos flash lf = low power cmos flash t = in tape and reel - soic, plcc, ssop, tqfp packages only . data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
information contained in this publication regarding device applications and the like is intended through suggestion only and ma y be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is give n and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under an y intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. a ll rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds30325a-page 168 advance information ? 2000 microchip technology inc. all rights reserved. ? 2001 microchip technology incorporated. printed in the usa. 3/01 printed on recycled paper. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7966 fax: 480-786-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3838 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 dayton two prestige place, suite 130 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific china - beijing microchip technology beijing office unit 915 new china hong kong manhattan bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - shanghai microchip technology shanghai office room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 hong kong microchip asia pacific rm 2101, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o ? shaugnessey road bangalore, 560 027, india tel: 91-80-207-2165 fax: 91-80-207-2171 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d ? activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 9/01/00 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company ? s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.
? 2000 microchip technology inc. advance information ds30325a-page 1 pic16f7x 1.0 device overview............................................................................................................. ............................................... 5 2.0 memory organization ......................................................................................................... ......................................... 11 3.0 i/o ports................................................................................................................... .................................................... 29 4.0 reading program memory...................................................................................................... ..................................... 41 5.0 timer0 module............................................................................................................... .............................................. 45 6.0 timer1 module............................................................................................................... .............................................. 49 7.0 timer2 module............................................................................................................... .............................................. 53 8.0 capture/compare/pwm modules................................................................................................. ............................... 55 9.0 synchronous serial port (ssp) module........................................................................................ ............................... 61 10.0 universal synchronous asynchronous receiver transmitter (usart) ............................................................ .......... 73 11.0 analog-to-digital converter (a/d) module ................................................................................... ................................ 89 12.0 special features of the cpu ................................................................................................ ....................................... 95 13.0 instruction set summary .................................................................................................... ....................................... 111 14.0 development support ........................................................................................................ ........................................ 119 15.0 electrical characteristics ................................................................................................. .......................................... 125 16.0 dc and ac characteristics graphs and tables ................................................................................ ........................ 147 17.0 packaging information ...................................................................................................... ......................................... 149 revision history 157 device differences 157 conversion considerations 157 ............................................................................................................................... .................................................. on-line support165 ............................................................................................................................... .............................................. reader response166 ............................................................................................................................... ............ pic16f7x product identification system167
pic16f7x ds30325a-page 2 advance information ? 2000 microchip technology inc.

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