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  preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs7666 digital color-space processor for ccd cameras features l itu-601 compliant image formatting l itu-656 and smpte-125/m transport l provides separate href and vref (or alternately hsync and vsync) signals l i 2 c control interface l limited secondary i 2 c bus master l automatic white balance l programmable gamma correction l programmable interpolation l programmable luma gain and saturation control l fully programmable color separation matrix coefficients l supports up to 1440, active pixels per line, with no limitation on vertical size l pin and software compatible with the cs7665 l programmable "color killer" circuit l highly integrated for low part count cameras description the cs7666 is a low-power digital color-space proces- sor for ccd cameras. it provides all necessary digital image processing for standard four-color interline trans- fer ccd imagers. the cs7666 processes the magenta, yellow, cyan, and green (mycg) ccd imager data into ycrcb formatted component digital video. internal pro- cessing includes color separation, automatic white balance, user programmable gamma correction, pro- grammable scaling (interpolation), and output formatting. also, a special "color killer" circuit eliminates false colors during saturation. the digital output of the cs7666 can be configured to comply with the itu-601, itu-656 and smpte-125/m standards. additionally, href and vref (or hsync and vsync) output pins are provided to support older analog video encoders and the current zv-port definition. the cs7666 is designed to work directly with the cs7615 ccd imager analog processor, and is a drop in replacement for the cs7665. ordering information CS7666-KQ 0 to 70 c 64-pin tqfp (10 mm x 10 mm x 1.4 mm) i deformatter color separation and anitaliasing white balance awb control gamma correction scaler output formatter i 2 c interface register pll and output block clock driver timing ycrcb vref/vsync href/hsync xtal primary i 2 c bus secondary i 2 c bus ccd data data jul 98 ds302pp1
cs7666 2 ds302pp1 table of contents characteristics and specifications ................................................... 3 digital characteristics.................................................................... 3 switching characteristics ............................................................. 3 power consumption ........................................................................... 3 control port characteristics ..................................................... 4 recommended operating characteristics............................... 5 absolute maximum ratings .............................................................. 5 general description .................................................................................. 6 overview ..................................................................................................... 6 the 640 pixel horizontal line ..................................................................... 7 embedded itu-656 eav and sav timing ............................................... 10 individual timing and synchronization signals ........................................ 11 hrefout/hsync ................................................................................... 11 vrefout/vsync ................................................................................... 11 digital output formats .............................................................................. 11 internal horizontal scaler ......................................................................... 14 clkin and clkin2x input timing ........................................................... 14 clkout ................................................................................................... 15 internal processing ................................................................................ 15 input data format and chroma separator ............................................... 15 color saturation control ........................................................................... 15 white balance and gamma correction .................................................... 15 chroma kill ............................................................................................... 16 internal filters ........................................................................................... 16 internal register structure and user interface ..................... 16 operating cs7666 in normal i2c configuration (three-byte mode) ....... 16 station address .................................................................................. 17 write operations in three-byte mode ................................................ 17 address set operation ....................................................................... 17 read operations in three-byte mode ............................................... 17 operating cs7666 in four-byte i2c configuration ............................ 17 write operations in four-byte mode .................................................. 18 read operations in four-byte mode ................................................. 18 initializing slave devices on secondary i2c bus from an eprom .......... 19 controlling the configuration process ...................................................... 19 reserved registers and test pins ........................................................... 20 pin descriptions ......................................................................................... 34 power supply connection ........................................................................ 34 input data and clocks .............................................................................. 35 i2c serial control ..................................................................................... 35 digital video outputs and clocking .......................................................... 36 miscellaneous ........................................................................................... 38 definitions ..................................................................................................... 39 package dimensions .................................................................................. 40
cs7666 ds302pp1 3 characteristics and specifications digital characteristics (t a = 25 c; v dd = 5 v; c l = 30 pf; input levels: logic 0 = 0 v, logic 1 = v dd .) switching characteristics (t a = 25 c; v dd = 5 v; c l = 30 pf; input levels: logic 0 = 0 v, logic 1 = v dd .) notes: 1. clkin, f clk , is f clk2x /2 in non-interpolated mode and f clk2x * 2/5 in interpolated mode. power consumption (t a = 25 c; v dd = 5 v; c l = no load; input levels: logic 0 = 0 v, logic 1 = v dd .) specifications are subject to change without notice parameter symbol min typ max unit logic inputs high-level input voltage v ih v dd - 0.8 - - v low-level input voltage v il --0.8v input leakage current i in - - 10.0 a input pin capacitance c di -10-pf input clamp voltage - -0.7 - v logic outputs high-level output voltage @ i oh = 2ma v oh v dd - 0.4 - - v low-level output voltage @ i ol = 2ma v ol 0.4 - - v high-z leakage current i z - - 10.0 a parameter symbol min typ max unit digital input clkin2x frequency range (note 1) f clk2x --30mhz input data setup time, di[9:0] t s1 5--ns input data hold time, di[9:0] t h1 5--ns digital output channel a/b digital data output clock interleaved data parallel data f clkout - - - - 30 15 mhz mhz channel a/b output hold time t oh -0-ns channel a/b output propagation delay t pd -1.95ns digital output rise time with 30 pf load t r -15-ns digital output fall time with 30 pf load t f -15-ns parameter symbol min typ max unit normal mode i dd - 80 100 ma low power mode i dd -716ma
cs7666 4 ds302pp1 control port characteristics (t a = 25 c; v dd = 5 v; input levels: logic 0 = 0 v, logic 1 = v dd .) parameter symbol min max unit scl clock frequency f scl -400khz bus free time between transmissions t buf 1.3 - s start condition hold time t hdst 0.6 - s clock pulse width high low t high t low 0.6 1.3 - - s s setup time for repeat start condition t sust 0.6 - s sdain hold time from scl falling t hdd 0-s sdain setup time from scl rising t sud 0.1 - s sdain and scl rise time t r -1.0s sdain and scl fall time t f -0.3s setup time for stop condition t susp 0.6 - s clkin2x clkin mosaic input data di[9:0] t h2 t s2 t h1 t s1 clkout output data doa[9:0] dob[9:0] t pd t oh input timing diagram output timing diagram t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl i 2 c timing diagram
cs7666 ds302pp1 5 recommended operating characteristics absolute maximum ratings warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min typ max unit power supply voltage v dd 4.5 5.0 5.5 v ground to ground voltage differential - - 10 mv digital input rise/fall time - - 10 ns clkin level setup to clkin2x rising (non-interpolated) t s2 8--ns clkin level hold after clkin2x rising (non-interpolated) t h2 8--ns digital input voltage range 0 - v dd v operating temperature range t a 0-70 c parameter symbol min max unit power supply voltage v dd -0.3 7.0 v digital input voltage range gnd - 0.3 v dd + 0.3 v forced digital output current - 50 ma sustained digital output voltage gnd - 0.3 v dd + 0.3 v output short circuit current - - ma operating temperature range t a 070c lead solder temperature (10 s duration) - +260 c storage temperature range -65 +160 c
cs7666 6 ds302pp1 general description overview the cs7666 forms the heart of a four chip digital ccd camera. the four chips include the ccd im- ager, the cs7615 ccd digitizer, the cs7666 color space processor, and a vertical drive interface-chip for the ccd imager. most four-phase ccd imag- ers (and their associated vertical drives) can be used with the cs7615 digitizer and the cs7666 processor to form a simple and cost-effective ycrcb output format digital camera. the cs7615 and cs7666 together support imager formats rang- ing from 175175 pixels up to 1000x1000 pixels. timing control is located in the cs7615 analog processor, while the cs7666 synchronizes itself by decoding the timing cues embedded in the cs7615 data stream. alternately, the cs7666 accepts hori- zontal and vertical timing signals on pin inputs. the block diagram in figure 1 illustrates a typical system interconnect. the cs7666 is a ccd camera color separation and color-space processor designed to process the four- color mosaic ccd imager data into itu-601 com- pliant 4:2:2 ycrcb digital component video. the cs7666 timing control is based on the built-in crys- tal oscillator or on the master clock provided by the cs7615, and provides formatted component digital video compliant with smpte-125 and itu-656 transport protocols. the cs7666 provides color separation of standard mycg chroma block data from industry standard four-color ccd imagers. gamma correction and white balance adjustment functions are also includ- ed in the cs7666. the ycrcb (luminance and chrominace) data is output at the scaled ccd pixel rate in 20-bit format, or at twice the scaled pixel rate in 10-bit format (see discussion on digital out- put formats). the ycrcb output data from the cs7666 conforms to the itu-656 parallel compo- nent digital video recommendation with embedded synchronization (see embedded eav and sav discussion). external horizontal and vertical syn- chronization signals are also provided to support itu-601 interfaces, as well as the pc-card zoom- video standard being used in notebook computers. the cs7666 incorporates an internal horizontal scaler which may be turned on to increase the hori- zontal pixel count of the popular 360 (cif) and 512 horizontal pixel per line imagers. the most com- ccd bias vertical drive timing cds/adc video codec +18v to +12v i 2 c bus 6 6 2 +5v cs7666 512x480 cs7615 ccd image processor cs4954 i 2 c i 2 c figure 1. typical 4-chip digital ccd camera figure 2. cs7666 block diagram deformatter color separation and anitaliasing white balance awb control gamma correction scaler output formatter i 2 c interface register pll and output block clock driver timing ycrcb vref/vsync href/hsync xtal primary i 2 c bus secondary i 2 c bus ccd data data
cs7666 ds302pp1 7 mon target resolutions for the scaler are 640 and 720 pixels per line (square and rectangular pixel formats), but it is possible to provide generic scal- ing of m/n where m and n are values from 1 to 31. the cs7615 and cs7666 chip set supports a wide range of imager formats while providing an output format that follows the itu-601 component digi- tal video recommendation. the itu-601 docu- ment primarily specifies horizontal resolutions of 720 active horizontal pixels (which is required for broadcast television compatibility). however, many of todays digital video receivers are capable of operating with a wide range of video image for- mats. even though these digital video receivers al- low image formats not specified in the itu- 601/656 recommendation, all of these receivers ex- pect the basic itu-601/656 protocol to be followed in terms of data sequence and timing cues. this is the case with the cs7666, where all output formats follow the itu-601/656 recommendation even if the image formats differ in horizontal and vertical pixel dimensions. the 640 pixel horizontal line the following discussion assumes that a 512 hori- zontal pixel class imager has been selected for the camera, the cs7615 has been programmed to pro- vide 512 active pixels and 112 inactive pixels, and that the internal 4:5 horizontal scaler has been en- abled (scaler mode 1). many other imager/scaler combinations are possible, but the digital video for- mat would not be significantly different than the 640x480 case described. transmitted during each active line are 1280 mul- tiplexed luminance and chrominance values (640 luminance, 320 chrominance cr, and 320 chromi- nance cb values). eight of the remaining 280 inter- face clock intervals are used to transmit synchronizing information. the first of these 1560 interface clock intervals is designated line 0 word 0 for the purpose of reference only. the 1560 sample words per total line are therefore numbered 0 through 1559. intervals 0 through 1279, inclusive, contain video data. the interface clock intervals occurring during dig- ital blanking are designated 1280 through 1559. in- tervals 1280 through 1283 are reserved for the end- active-video (eav) timing reference. intervals 1556 through 1559 are reserved for the start-of-ac- tive-video (sav) timing reference. figure 3 indi- cates the values of the timing reference signals (f, v, h) for an entire frame of interlaced video. please note the scan lines are numbered 1 through 525 consecutively in the time domain (spatially they are interlaced). table 1 defines the 1560 samples of a single scan line of video.
cs7666 8 ds302pp1 vertical blanking vertical blanking horizontal blanking horizontal blanking active video field 1 active video field 2 eav h=1 sav h=0 640 779 0 639 f=1 lines 266 to 3 f=0 lines 4 to 265 lines 1 to 19 v=1 lines 20 to 263 v=0 lines 264 to 282 v=1 lines 283 to 525 v=0 figure 3. horizontal and vertical timing states (640480 resolution)
cs7666 ds302pp1 9 word data content pixel notes 1280 1111 1111 640 eav 1281 0000 0000 eav 1282 0000 0000 eav 1283 1fv1 p3p2p1p0 641 eav 1284 1000 0000 642 fro pixels 642 to 777 cr = cb = 80h y = 10h 1285 0001 0000 1286 1000 0000 1287 0001 0000 643 1552 1000 0000 776 1553 0001 0000 1554 1000 0000 1555 0001 0000 777 1556 1111 1111 778 sav 1557 0000 0000 sav 1558 0000 0000 sav 1559 1fv0 p3p2p1p0 779 sav 0 cb0 0 start of digital video 1 y0 for vblank line 1 to 19 and 264 to 283 cr = cb = 80h y = 10h 2cr0 3y1 1 4cb2 2 5y2 6cr2 7y3 3 2n cbn n for active pixels 20 through 263 and 283 to 525 for n=even from pix- els 0 to 638 2n + 1 yn 2n + 3 crn yn+1 n+1 1272 cb636 636 1273 y636 1274 cr636 1275 y637 637 1276 cb638 638 1277 y638 1278 cr638 1279 y639 end of digital video table 1. detail of scan line for 640x480 image
cs7666 10 ds302pp1 embedded itu-656 eav and sav timing the lines in figure 3 are numbered 1 through 525. video data is not present on lines 1 to 19 or 264 to 282, which constitute the vertical blanking periods. the vertical blanking is in full line increments, where y samples are set to 10h, while cb and cr samples are set to 80h. the interval starting with eav and ending with sav is the digital horizontal synchronization, which occurs on every line. it is implicit that the timing reference signals are contiguous with the video data and continue through the vertical blanking interval. each timing reference signal consists of the four-word sequence in table 2. the first three words are a preamble, followed by a fourth word indicating a) even field (field 2) identification, b) state of vertical blanking, and c) state of horizontal blanking. table 1 details the timing reference format. the protected bit states are dependent on the f, v, and h bits accord- ing to table 3. protected state bits - in tables 3 and 4, h, v, and f bits provide all the necessary timing and state in- formation. bits 0 to 3 provide error detection and correction information. the protection bits allow for correction of single-bit errors and detection of two-bit errors. the f or field bit indicates which of the interlaced fields is active, the first/odd field which contains 262 lines, or the second/even field which contains 263 lines. value description first byte ffh fixed second byte 00h fixed third byte 00h fixed fourth byte xyh see table 3 table 2. timing reference signal bit position word 1281 and 1556 word 1281 and 1557 word 1282 and 1558 word 1283 and 1589 description 7 1001fixed 6 1 0 0 f f = 0 during field 1/oddf = 1 during field 2/even 5 1 0 0 v v = 0 during active videov = 1 during vertical blanking 4 1 0 0 h h = 1 at end of active videoh = 0 at start of active video 3 1 0 0 p3 see protected bits state table 4 2 1 0 0 p2 see protected bits state table 4 1 1 0 0 p1 see protected bits state table 4 0 1 0 0 p0 see protected bits state table 4 table 3. eav and sav timing reference signal detail. bit 7 bit 6 (f) bit 5 (v) bit 4 (h) bit 3 (p3) bit 2 (p2) bit 1 (p1) bit 0 (p0) 10000000 10011101 10101011 10110110 11000111 11011010 11101100 11110001 table 4. eav and sav protected bit states detail.
cs7666 ds302pp1 11 individual timing and synchronization signals in addition to the embedded eav and sav timing signals, the cs7666 provides individual synchroni- zation output signals which are employed by many video encoder circuits. these synchronization sig- nals are typically used to interface the itu-656 dig- ital video stream to other components and subsystems. the individual synchronization sig- nals include hrefout and vrefout. hrefout/hsync hrefout is an active-high signal indicating when active pixel data is being transmitted on doa[9:0] or dob[9:0]. hrefout is low when non-active picture data is being transmitted during horizontal blanking. depending on the mode of op- eration, the hrefout signal follows either the hrefin signal or the href defined by the eav and sav code. the hrefout pin may also be configured to pro- vide a hsync output that provides an active low pulse for 64 pixel clocks whose falling edge occurs 16 pixel clocks after the end of active video for ntsc (12 clocks for pal) as per the itu-r bt.601 specification. hsync is chosen by setting the operation control register ii (07h) hs_sel bit (bit 0) to a value of 1. this pin may be inverted by setting the h_inv bit (register 07h bit2) to a value of 1. the hsync signal may be delayed by 0, 0.5, 1, or 1.5 pixel clocks by setting h_sft[1-0] appropriately (register 07h bits 5 and 4.) vrefout/vsync vrefout is an output signal that is active high when the cs7666 is putting out active video lines. the active-low portion of this signal defines the vertical blanking period. if the vs_sel bit in reg- ister 07h is set, this output pin produces a vertical sync signal that is compatible with current pal or ntsc analog systems. see figure 4. this signal is active for 3 line times in ntsc mode (bit 5 of reg- ister 04h = 0) and 2.5 line times in pal mode (bit5 of register 04h = 1.) this line may be inverted by setting the v_inv bit (register 07h) to a value of 1. alternately, when the zv mode bit in register 06h is set, this output behaves as a vsync signal ap- propriate for zv ports. in the zv mode, the vsync signal is active-high during the first six horizontal line periods of every field. the transition in vsync signal lags the href signals rising edge during odd fields and leads the rising edge of href during even fields. digital output formats the cs7666 outputs data in a 20-bit wide format at the output pixel clock rate. alternately, the data can be multiplexed in a 10-bit format at a 2x output pix- el clock rate. figures 5 and 6 detail the clock and data relationships. the output data transitions on the falling edge of the clock such that the rising edge of the clock can be used to latch the data into subsequent circuitry. the cs7666 delivers 4:2:2 component digital vid- eo output data in ycrcb format. the data conforms to the itu-r bt.656 specification. the y compo- nent range is 16-235 (8-bit data) and the cr and cb component ranges are 16-240 (8-bit data). howev- er, by setting clip_off (register 07h bit 6) to a value of 1, the output data can be extended to a range of 1-254 (8-bit data). only 00 and ff are re- stricted to allow digital timing codes. the digital outputs can be configured for 10-bit in- terleaved y and crcb data, or for 20-bit parallel operation. the interl bit of the operational con- trol register 06h determines which output format is active. logic 0 places the cs7666 in interleave mode with output data on channel "a." logic 1 places the cs7666 in non-interleaved mode where luminance data is output on channel "a" and chrominance data is output on channel "b."
cs7666 12 ds302pp1 hsync vsync vref 3h 6h 9h 525 1 2 3 4 5 6 7 8 9 10 vsync zv mode line ntsc vertical timing (odd field) hsync vsync vref 3h 9h 263 264 265 266 267 268 269 270 271 272 273 vsync zv mode line ntsc vertical timing (even field) hsync vsync vref 624 625 1 2 3 4 5 6 7 23 vsync zv mode line pal vertical timing (odd field) hsync vsync vref 311 312 313 314 315 316 317 318 319 336 vsync zv mode line pal vertical timing (even field) 6h 2.5h 6h 24h 25h 6h 2.5h figure 4. vertical timing
cs7666 ds302pp1 13 24.5454mhz clkout do [9-0] line 3 pixel 776 to line 4 pixel 3 do [9-0] line 263 pixel 638 to line 264 pixel 645 do [9-0] line 525 pixel 638 to line 1 pixel 645 cb638 y638 cr638 y639 ffh 00h 00h 9dh 80h 10h 80h 10h 80h 10h eav ffh 00h 00h f1h 80h 10h 80h 10h 80h 10h 80h 10h 80h 10h eav ffh 00h 00h abh 80h 10h 80h 10h 80h 10h 80h 10h 80h 10h sav a a a note: eav, sav, and blanking data values are based on the 8 msb's of the output data, the two lsbs are considered fractional. figure 5. 2x pixel clock, 10-bit interleaved output format for 640x480 image format. 12.2727mhz clkout href do [9-0] do [9-0] 10h y0 y1 y2 y3 y4 y633 y634 y635 y636 y637 y638 y639 10h 80h cb0 cr0 cb2 cr2 cb4 cb632 cr634 cb634 cr636 cb636 cr638 cb638 80h a b note: eav, sav, and blanking data values are based on the 8 msb's of the output data, the two lsbs are considered fractional. figure 6. 1x pixel clock, 20-bit parallel output format for 640x480 image format.
cs7666 14 ds302pp1 in 20-bit wide mode, the luminance information is output on doa[9:0] and the chrominance informa- tion is output on dob[9:0]. the cs7666 supports both 8-bit and 10-bit opera- tion as per the itu-656 recommendation. the itu- 656 recommendation defines the primary data path as 8-bits wide with two additional fractional bits that can be used to form a 10-bit data path. if only 8-bits of output data are used, the two lsbs, doa1 and doa0 (dob1, dob0) are not used. however, doa[9:2] (dob[9:2]) are connected exactly the same as in a 10-bit system. this is essential to properly pass the image data and synchronization signals to the next component. internal horizontal scaler the internal horizontal scaler is used to bridge be- tween common ccd imager formats and computer or television formats. in the cs7665 compatibility mode (default after reset) a 4:5 data rate scaler is selected by setting the interp pin (pin 54 on the cs7666) to a logical one. the 4:5 scaler will con- vert a standard 512 horizontal pixel width ccd im- ager used for cam-corders into the vga 640x480 format. the cs7615 (if that device is used in the system) must also have its interp pin set high. when the cs7666 is in the native cs7666 mode (true_7666 in register 04h set to 1), the interp pin is ignored and the internal scaling ratio is pro- grammed by the user. the cs7615 must have its interp pin tied to ground. several pre-defined scaler modes may be selected by writing a 3-bit value to bits 0-2 of register 04h. these default scaling modes are described in table 7. if the custom bit (bit 3 of register 04h) is set to a 1, then the scaling ratio is determined by the m and n values contained in the scaler control registers (2dh - 2fh.) clkin and clkin2x input timing the clkin, pin 55, will always require a primary pixel rate clock source. ccd manufacturers gener- ally specify a pixel clock frequency that is compat- parallel interl = 1 interleaved interl = 0 doa[9:0] 10-bit luminance data interleaved 10-bit luminance data and 10-bit chrominance data dob[9:0] 10-bit chrominance data 0 clkout pixel rate 2x pixel rate table 5. interl controlled output formats register 04h bit 4 pin 54 operation scaling ratio 0 0 cs7665 mode 1:1 0 1 cs7665 mode 4:5 1 x cs7666 mode programmable table 6. interp pin (pin 54) mode ccd format ccd clock (mhz) output format input clock (mhz) scaling ratio 000 ccd ? input clock same as ccd (30 mhz max.) 1:1 001 512x480 9.818 640x480 24.5454 4:5 010 512x480 9.346 720x480 27.000 9:13 011 512x576 9.281 720x480 27.000 11:16 100 362x480 6.75 640x480 24.5454 11:20 101 362x480 6.75 720x480 27.000 1:2 362x576 6.75 720x576 27.000 110 512x576 9.563 720x576 27.000 17:24 111 512x480 9.000 720x480 27.000 2:3 512x576 9.000 720x576 27.000 table 7. default scaling modes (register 04h)
cs7666 ds302pp1 15 ible with one of the analog encoders that can be used with a given imager. if an analog encoder is used in the camera to generate an analog output, the pixel clock frequency expected by the encoder must be matched precisely. however, digital dis- play systems, such as those based on vga graphics adapter cards and zoom video systems, are gener- ally not sensitive to pixel clock frequency, and will tolerate a wide range of pixel and frame rates. specific pixel-rate clock frequencies for analog en- coders include 14.31818 mhz for 768h imagers, the primary itu-601 13.5 mhz for 720h imagers, and down to 12.272727 mhz clock rates for 640h vga format imagers. in cs7665 compatibility mode (register 04h bit 4 = 0), the clkin2x, pin 56, will either require a 2.5x ccd pixel rate clock when the internal 4:5 scaler is enabled (interp pin high) or a 2x times the ccd pixel rate clock in non-interpolation mode (interp pin low). the clkin2x pin is used as a crystal input pin when the cs7666 is in native mode (register 04h bit4 = 1). clkout clkout follows the output data rate as described in the digital output formats section. in the non- interleaved mode the clock output is at the output luma sample rate whereas in the interleaved mode the clock output is at 2x the output luma sample rate. internal processing the internal operation of the cs7666 can be sepa- rated into several distinct blocks. the following section provides an overview of how these blocks operate and interact. input data format and chroma separator the cs7666 accepts up to 10-bit mycg image data from a ccd digitizer such as the cs7615. suitable ccd analog processing unit. the cs7666 internally converts the four-color ccd mycg in- terlaced image data into the various color space for- mats. these include rgb and yuv, as well as ycrcb. the individual image adjustments are per- formed in the most appropriate color space repre- sentation. ultimately the image is converted to ycrcb format for outputting data. color saturation control color saturation control is via the red saturation and the blue saturation control register addresses 0ah and 0bh. white balance and gamma correction the red and blue color balances can be adjusted through the i 2 c control port. during the awb (au- tomatic white balance) sequence the red level is ad- justed to minimize the (y-r) difference component; similarly the blue level is adjusted to minimize the (y-b) color difference component. an automatic white balance is initiated by writing a 1 to register 05h bit 1. for manual control, the red balance is accessed through register 08h, and the blue balance is accessed through register 09h. gamma correction is provided to offset the non-lin- ear illumination profile of the display device. sep- arate 256 entry tables are supplied for red, green, and blue. each entry is 8-bits. the gamma table is programmed through register 0ch. the write for- mat is similar to the write format described in the normal i 2 c operation section later in this docu- ment. the first byte contains the cs7666 device address and write bit, the second byte contains the cs7666 gamma table register address (0ch), the third byte determines which gamma ram to up- date (red, green, and blue), the next 256 bytes con- tain the gamma table entries. the blue gamma ram is selected by setting regis- ter 0ch bit 0 to a one; the green gamma ram is se- lected by setting register 0ch bit 1 to a one; and the red gamma ram is selected by setting register 0ch bit2 to a one. any, or all of the gamma rams may be selected . the most common implementation is
cs7666 16 ds302pp1 to write the same gamma table to all 3 rams by setting bits 0-2 high. the gamma table itself is loaded from low to high. the first byte after the ram selection byte will correspond to the value used when the input data is 00h, the 256th byte after the ram selection byte will correspond to the val- ue used when the input data is ffh. the gamma table is read in a similar manner. how- ever, certain restrictions are made to reads. first, the gamma rams may only be read one at a time (ram selection byte = 01,02,04 only) and, second, the gamma table may only be read when gamma correction is disabled (register 05 bit2 = 0). chroma kill as the brightness of an image increases, the green, yellow, cyan, and magenta pixels within the ccd array will saturate at different intensity levels. as a result, a highly illuminated object or light source may start to look cyan. to overcome this effect, an internal chroma killer circuit compares the luma and chroma values of each pixel to a set of pro- grammable thresholds. if the pixels luma value is greater than the y_thr value (register 27h) and its cr and cb values are between the cr_thr_h , cr_thr_l , cb_thr_h, and cb_thr_l threshold values respectively, then that pixel will lose its chroma value (become white.) these thresholds are stored in registers 27h - 2ch. internal filters the cs7666 has an internal low-pass chroma filter to reduce the effects of color aliasing. this filter is enabled by writing a value of 0 to bit 4 of register 05h. the cs7666 also contains a luma peaking fil- ter to enhance the edges of blurred images. this fil- ter is enabled by setting register 05h bit 3 to a value of 0. internal register structure and user interface the user interface describes the users external view of the cs7666 and the basic control opera- tions. these areas include digital data output modes and organization, timing and synchronization sig- nals, i 2 c interface, and miscellaneous controls. the cs7666 has two i 2 c ports: (1) a slave i 2 c port called the primary i 2 c port, and (2) a secondary i 2 c port with limited i 2 c master capabilities. the pri- mary i 2 c port allows an external controller to con- trol the cs7666. it is assumed the external controller will also directly control any other i 2 c slave devices on the camera board. this is the nor- mal i 2 c operation mode of cs7666. the secondary i 2 c port, on the other hand, may be used to control all the other slave devices on a camera board through the cs7666 only. this feature is useful when the external i 2 c controller is used to control multiple cameras. when used in this configuration the 4bytemode pin (pin 1) of the cs7666 must be tied high and the device is operated in four-byte mode. operating cs7666 in normal i 2 c configuration (three-byte mode) in normal mode, the cs7666 is connected as a slave device to an external i 2 c controller through the primary i 2 c port. the connection is done via a two-wire serial bus. other i 2 c devices on the cam- era may also share the same serial bus. the external controller communicates with the i 2 c devices by sending and receiving short packets of 8-bit words in accordance with the i 2 c protocol. the packets contain the station address of the target device, the desired register address, and data. there are three packet formats: write format, address set format, and read format. each packet is addressed to a device by the station ad- dress. the lsb of the station address is the r/w (data direction) bit. this bit is set low in the write and address set packets, and it is set
cs7666 ds302pp1 17 high for read packets. the master can read and write to non-existent registers within the selected device. write operations will have no effect; read operations will return a value of 00h. station address each device on the i 2 c bus has a unique 7-bit ad- dress. an eighth bit, the r/w bit, determines if the current data transfer writes data to the slave device or reads data from the slave device. it is common to represent the station address and r/w bit as two 8- bit station addresses, one address for write accesses and another address for read accesses. we will fol- low this practice. the cs7666 default station ad- dress is 34h for writes and 35h for reads. the station address can be changed by writing a new station address to register ffh. the value written to this register does not include the r/w bit. for ex- ample. the default station address (34h write / 35h read) will be stored as 1ah in register ffh. write operations in three-byte mode the write format consists of a three-byte packet. the first byte is the station address with the data di- rection bit set low to indicate a write. the second byte is the device register address (0..255). the third byte is the register data (0..255). no addition- al bytes are allowed. address set operation the address set format consists of a two-byte packet which sets the address of a subsequent read operation. the first byte of the station ad- dress with the lsb (data direction bit) set low to indicate a write operation. the second byte is the register address (0..255). the address set for- mat is the same as the write format, without the register data (third byte). read operations in three-byte mode the read operation may consist of two or more bytes. the first byte is the station address with the lsb (data direction bit) set high indicating a read operation. the addressed device then sends one or more bytes back from the register last addressed by the previous write operation or the previous ad- dress set operation. operating cs7666 in four-byte i 2 c config- uration in this configuration the external controller talks only to the cs7666 through the primary i 2 c inter- face. all the other slave devices on the camera external eprom secondary i 2 c primary i 2 c cs7615 cs7666 controller cs4954 figure 7. i 2 c configuration showing primary and secondary i 2 c busses. to other sub-systems byte sequence write format packet detail first byte station address with lsb set low second byte device register address (0..255) third byte register data (0..255) table 8. write format packet byte sequence address set format packet details first byte station address with lsb set low second byte device register address (0..255) table 9. address set format packet operation byte sequence read format packet details first byte station address with lsb set high; source device then returns one byte of register data (0..255) second byte returned data from cs7666 table 10. read format packet.
cs7666 18 ds302pp1 board are tied to the secondary i 2 c port of the cs7666. write and read packets only are de- fined in four-byte mode. independent address set operations to slave devices on the secondary i 2 c bus is not allowed in four-byte mode. four-byte mode is active when the 4bytemode pin (pin 1) is logic high. write operations in four-byte mode all write operations from an external controller, through the cs7666, to any slave device must use the four-byte mode; this includes writing to the cs7666 itself. the external controller sends a four- byte write command to the cs7666 which ini- tiates a write operation to the destination slave device and sets the i2cbusy bit in the status reg- ister (01h). the i2cbusy bit is cleared when the write operation on the secondary bus is complete. the external controller can poll the status register to check if the cs7666 has completed the com- mand. the cs7666 has a one command buffer which al- lows the external controller to queue one additional command while the current command is still being executed. if more than one command is sent before the i2cbusy bit is cleared, the cs7666 saves only the last command and executes it after the current one is completed. commands that involve writing or reading only to cs7666 registers are not put in the queue but are executed immediately without af- fecting any transactions occurring on the master i 2 c interface. any attempt by the external i 2 c controller to write to the cs7666 registers while the cs7666 is busy initializing from an external eeprom will be ig- nored. however, reads from the cs7666 are al- lowed during this time. if, during a read or write operation to a slave device, the cs7666 fails to receive an acknowledge bit the execution of the command is aborted and the nodev bit in the status register is set high. this bit remains set unless it is explicitly cleared by writing to it or a new command is written to cs7666. read operations in four-byte mode the read operation in four-byte mode first re- quires a three-byte read-trigger packet to the cs7666. the first byte is the station address of the cs7666 with the lsb set low. the second byte is the target slave devices station address with the lsb (data direction bit) set high. the third byte is the register address (0..255). the read-trigger packet initiates a read operation by the cs7666 from the target slave de- vice on the secondary i 2 c bus. the status register in the cs7666 may be checked to see if the read op- eration has been completed. the i2cbusy bit in status register 01h is set to zero when the operation is completed. on completion of a read cycle from the target de- vice, the cs7666 places the data read into the slave data hold register at address 19h. the external controller can read this data through the primary i 2 c port. this requires first performing an ad- dress set operation to set the address to 19h and byte sequence write format packet detail first byte station address of cs7666 with lsb set low second byte station address of target slave device with lsb set low third byte device register address (0..255) fourth byte register data (0..255) table 11. four-byte write format packet byte sequence read-trigger format packet details first byte cs7666 station address with lsb set low second byte target device station address with lsb set high third byte device register address (0..255) table 12. read-trigger packet in four-byte mode
cs7666 ds302pp1 19 then sending a one-byte station address indicating read to the cs7666. the data from register 19h is then returned by the cs7666. initializing slave devices on secondary i 2 c bus from an eprom an eprom may be attached to the secondary i 2 c bus for initialization purposes. resetting the cs7666 initiates a download of register values from the eprom into any of the slave devices on the secondary i 2 c bus. the eprom is assumed to be at station address a0h. if during initialization, the cs7666 does not receive an acknowledge bit from the eprom, all transactions with the eprom are aborted and the nodev status bit is set in status register at address 01h. the data within the eprom is formatted in three- byte packets that represent the destination address, register address, and data. after reading a packet, the cs7666 initiates an i 2 c bus cycle using the first byte as the device station address, the second byte as the device register address, and the third byte as the data being written to the device. if an acknowl- edge is received from the target device, the cs7666 will fetch the next 3 bytes from the eprom and re- peat the process. the only exception being the gamma table whose entire 256 bytes is transferred in one i 2 c write cycle. this process will continue until the total number of packets read equals the value in the eeprom count register (registers 1ah and 1bh), a halt command is executed, or no ac- knowledge is received from the target device. while the cs7666 is downloading from the eprom, the initact bit (register 01h bit3) is set in the status register of cs7666. all attempts to write to cs7666 registers by an external controller will be ignored during this time. controlling the configuration process the simplest configuration would consist of an eprom with one configuration file. in this case, the first commands in the eprom should write the total number of packets in the eeprom. this data is written to the eeprom count high and low byte registers (registers 1ah and 1bh). subsequent bytes would contain all the necessary data to con- figure the camera. this data will be read in a se- quential fashion. if, however, multiple configurations are desired, the eeprom may be programmed with multiple sets of data, and the cs7666 programmed to select one of 8 configurations. the cs7666 incorporates 3 commands to handle multiple configurations: skip, jump, and halt. the skip command tells the cs7666 to skip to the address within the eeprom specified by the con- figuration control registers (30h - 3fh). the con- figuration control registers are used in pairs to provide a 11-bit eeprom address. the configura- tion index register determines which two of the 8 pairs will be used. the configuration index register is loaded auto- matically after reset by the cs7666. the cs7666 will attempt a read cycle from the parallel i/o port of a crystal cs495x series video encoder or saa8574 i 2 c port expander from philips semi- conductors. if the read cycle is successful, the con- figuration index register will contain the state of the lower 3 bits of the parallel i/o port. if both the byte sequence write format packet detail first byte station address of cs7666 with lsb set low second byte station address of cs7666 with lsb set low third byte slave data hold reg. address 19h table 13. address set for slave data hold register in four-byte mode byte sequence read format packet details first byte cs7666 station address with lsb set high. second byte returned data from register 19h of cs7666 table 14. read format packet.
cs7666 20 ds302pp1 saa8574 and a cs495x series part are present, the cs495x series part i/o port value will be used. a set of shunts or dip switches attached to the i/o port provides a convenient way to select up to 8 configurations. the skip command is executed by writing a 1 to bit 1 of the eeprom control register (42h). the jump is similar to the skip command. the user loads a jump address into the jump control registers (40h and 41h) and then executes the jump command by setting bit 2 of the eeprom control register (42h) to a 1. the jump command may be used to reduce the amount of required ee- prom space by allowing multiple configurations to share common data. for example, three configu- rations may be necessary to adjust for three differ- ent ccd timings, but they may all share a common gamma table. the halt command is used to stop the execution of the boot state machine. when all necessary data has been read from the eeprom, writing a 1 to bit 0 (halt) of the eeprom control register will safely stop the boot process. the total number of packets that may be stored in the external eeprom is 2k/3 or 682 3-byte com- mands. gamma table packets contain 259bytes. a typical map of the eprom table is shown in fig- ure 8. the only exception to this organization is data for the cs7666 gamma table. the data for the gamma table is organized as shown in figure 9. reserved registers and test pins to ensure proper operation of the cs7666, connect scanmode (pin 53) and scanenable (pin 64) to ground, and connect testpinb (pin 60) and transp (pin 61) to vdd. registers 23h - 26h must be set to a value of ffh after reset. all other reserved registers may be left in their de- fault states. cs7666 station address[7] +w 1ah (addrs of low byte count) count value cs7666 station address[7] +w 1bh (addrs of high byte count) count value dest. station address + w dest. device address data value dest. station address + w eprom block 000 (binary) address 00h figure 8. map of eprom table for initialization of registers cs7666 station address[7] +w 0ch (gamma reg. addrs) data = select rgb ram data [gamma loc 00h] data [gamma loc 01h] data [gamma loc ffh] figure 9. map of eprom table for storing gamma ram initialization data.
cs7666 ds302pp1 21 master reset register (00h) mr setting bit mr0 to logic high will initiate a cs7666 master reset equivalent to executing an ex- ternal reset using the reset pin. all registers will be placed in their default state, and the down- load of any external eprom present on the secondary i 2 c bus will be initiated. the bit is self- cleared. status register (01h) evnfld logic high indicates even field of interline-transfer ccd. logic low indicates odd field of inter- line-transfer ccd. this bit provides a course means of synchronizing to the field rate. nodev logic high indicates that the addressed slave device on the secondary i 2 c bus did not respond. i2cbusy logic high indicates that the cs7666 secondary i 2 c master is busy accessing the addressed slave device. initact logic high indicates the cs7666 master is busy initializing registers from the external i 2 c eprom on the secondary i 2 c bus (if present). hizenb pin 63 status. interp pin 54 status. p4byte pin 1 status. pin i/o control (02h) pllout logic high enables the pll clock output to the cs7615 (pin 51). this pin was a nc on the cs7665. fieldout logic high changes field (pin 62) from an input to an output pin. default is input. uv_enb logic high replaces field with a u/v clock. digital gain register (03h) dg[4:0] controls the digital gain applied to the y (luminance) signal after the rgb to ycrcb converter block. the range of gains are from 0 to 31/8 in increments of 1/8. a gain of 0, indicates no bright- ness. 76543210 res res res res res res res mr reserved w 76543210 res p4byte interp hizenb initact i2cbusy nodev evnfld reservedrrrrrrr 76543210 res res res res res uv_enb fieldout pllout reserved r/w r/w r/w 76543210 res res res dg4 dg3 dg2 dg1 dg0 reserved r/w
cs7666 22 ds302pp1 scaler control (04h) mode[2:0] selects 1 of 8 pre-defined scaling ratios. custom when set, scaler uses custom values held in registers 2dh-2fh. true_7666 when set, pin 54 is ignored and the cs7666 is in native mode. the default is cs7665 compat- ibility mode. (pin 54 selects 5:4 scaler.) pal logic 1 selects pal timing for href and vref. default is ntsc. feature control register (05h) awb the automatic white balance procedure is initiated by pointing to a white scene and setting this bit high. the bit will return a logic high while the awb procedure is in progress. setting this bit low will have no effect. this bit will always be read as a 0 when the awb is not in progress. gamon the gamma correction from the gamma ram look up table is applied to the video signal in r-g- b space when this bit is set high. the gamma ram is a fully user programmable, 256 entry look up table. lumoff setting lumoff bit high disables the luma peaking filter. chroff setting the chroff bit high disables the chroma low-pass filter for minimizing color aliasing. 76543210 res res pal true_7666 custom mode2 mode1 mode0 reserved r/w r/w r/w r/w 76543210 res res res chroff lumoff gamon awb res reserved r/w r/w r/w r/w reserved
cs7666 ds302pp1 23 operational control register (06h) oblu logic high causes the first line after vref of the odd field to be processed as a blue line. logic low causes the first line of the odd field to be processed as a red line. eblu logic high causes the first line after vref of the even field to be processed as a blue line. logic low causes the first line of the even field to be processed as a red line. pospix logic 1 causes the first pixel of the first line to be treated as a positive pixel in the color sep- aration block. logic 0 causes the first pixel to be treated as a negative pixel. try toggling this bit if the colors appear reversed. oe the output enable bit operates in conjunction with the external output enable pin, as illustrat- ed in table 15. inref logic 1 causes cs7666 to accept href input and vref input pins as the reference inputs signals. eav and sav codes in the ccd data stream are ignored. logic 0 causes the internal de-formatter to decode and follow the embedded eav and sav codes sent from the ccd dig- itizer (as with the cs7615). interl logic 0 places the digital outputs in interleaved mode with alternate y and crcb data on the do [a0..a9 ] 10-bit output. logic 1 places the digital outputs in parallel mode with y data on do [a0..a9 ] and crcb on the do [b0..b9] outputs. zv a logic 1 causes vrefout pin to output a vsync signal compatible with zv port specifica- tions as well as many composite video encoders. 7654 3210 res zv interl inref oe pospix eblu oblu reserved r/w r/w r/w r/w r/w r/w r/w oe bit oe pin digital outputs 0 0 enabled 0 1 high-z 1 0 high-z 1 1 enabled table 15. oe pin and bit operation
cs7666 24 ds302pp1 operational control register ii (07h) hs_sel logic 1 causes hsync to be output on pin 31. logic low causes href (horizontal blank) to be output on pin 31. vs_sel l.ogic 1 causes vsync to be output on pin 30. logic low causes vref (vertical blank) to be output on pin 30. h_inv logic 1 inverts the polarity of pin 31. v_inv logic 1inverts the polarity of pin 30. h_sft[1:0] shifts the the signal on pin 30 from 0 to 3 clock cycles. clip_off when set, excludes only 00 and ff from output data. otherwise itu bt test_aa this bit is reserved for test purposes and may be set as a 1 or a 0. red balance register (08h) rb[7:0] the red balance register controls the red contribution to the r-y chrominance signal. when the register value is 00h, the red contribution is minimized; when the register value is ffh, the red contribution is maximized. when the awb correction is in progress, this register value is adjusted such that the absolute magnitude of the r-y signal is minimized. blue balance register (09h) bb[7:0] the blue balance register controls the blue contribution to the b-y chrominance signal. when the register value is 00h, the blue contribution is minimized; when the register value is ffh, the blue contribution is maximized. when the awb correction is in progress, this register value is adjusted such that the absolute magnitude of the b-y signal is minimized. red saturation register (0ah) rs[7:0] the red saturation register value controls the amplitude of the r-y chrominance signal. when the register value is 00h, the amplitude of the r-y is minimized; when the register value is ffh, the amplitude of the r-y is maximized. 76543210 test_aa clip_off h_sft1 h_sft0 v_inv h_inv vs_sel hs_sel r/w r/w r/w r/w r/w r/w r/w 76543210 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 r/w 76543210 bb7 bb6 bb5 bb4 bb3 bb2 bb1 bb0 r/w 76543210 rs7 rs6 rs5 rs4 rs3 rs2 rs1 rs0 r/w
cs7666 ds302pp1 25 blue saturation register (0bh) bs[7:0] the blue saturation register value controls the amplitude of the b-y chrominance signal. when the register value is 00h, the amplitude of the b-y is minimized; when the register value is ffh, the amplitude of the b-y is maximized. gamma correction register (0ch) writing to the gamma register (0ch) selects the r, g, and/or b ram. continuing data writes without sending a stop bit after the register write results in writes to the ram locations starting with 00h and continuing to ffh. reads from register 0ch function in a similar way. note: all three gamma rams may be selected for simultaneous writes, but read should be done one ram table at a time. gc0 logic 1 selects blue gamma ram for subsequent access. gc1 logic 1 selects green gamma ram for subsequent ram access. gc2 logic 1 selects red gamma ram for subsequent ram access. gc[0:7] provide r/w access to ram after gamma ram table has been selected. test control a register (0eh) this register is reserved test control b register (0fh) this register is reserved. yr coefficient register (10h) color separation and color space conversion coefficient. crr coefficient register (11h) color separation and color space conversion coefficient. 76543210 bs7 bs6 bs5 bs4 bs3 bs2 bs1 bs0 r/w 76543210 gc7 gc6 gc5 gc4 gc3 gc2 gc1 gc0 r/w 76543210 yr7 yr6 yr5 yr4 yr3 yr2 yr1 yr0 r/w 76543210 crr7 crr6 crr5 crr4 crr3 crr2 crr1 crr0 r/w
cs7666 26 ds302pp1 cbr coefficient register (12h) color separation and color space conversion coefficient. yg coefficient register (13h) color separation and color space conversion coefficient. crg coefficient register (14h) color separation and color space conversion coefficient. cbg coefficient register (15h) color separation and color space conversion coefficient. yb coefficient register (16h) color separation and color space conversion coefficient. crb coefficient register (17h) color separation and color space conversion coefficient. 76543210 cbr7 cbr6 cbr5 cbr4 cbr3 cbr2 cbr1 cbr0 r/w 76543210 yg7 yg6 yg5 yg4 yg3 yg2 yg1 yg0 r/w 76543210 crg7 crg6 crg5 crg4 crg3 crg2 crg1 crg0 r/w 76543210 cbg7 cbg6 cbg5 cbg4 cbg3 cbg2 cbg1 cbg0 r/w 76543210 yb7 yb6 yb5 yb4 yb3 yb2 yb1 yb0 r/w 76543210 crb7 crb6 crb5 crb4 crb3 crb2 crb1 crb0 r/w
cs7666 ds302pp1 27 cbb coefficient register (18h) color separation and color space conversion coefficient. slave data hold register (19h) when an external i 2 c controller initiates a register read from a slave device on the secondary i 2 c bus through cs7666, the returned data is placed in this register. the external controller may then read the data from the slave data hold register. this register is read only. eprom count low byte register (1ah) lower byte of the number of triple-bytes to be read from eprom upon reset of cs7666. this register is read only. eprom count high byte register (1bh) upper byte of the number of triple-bytes to be read from eprom upon reset of cs7666. this register is read only. version (major) register (1ch) the major version register (device id) in the cs7666 is assigned the value feh. this register is read only. version (minor) register (1dh) the minor version register in cs7666 rev a. is assigned the value 00h. with each minor revision the value is in- creased by 1. this register is read only. low power register (20h) pd setting bit pd to 1 will place the cs7666 in low power mode. test enable register (21h) this register is reserved. reserved register (22h) this register is reserved and returns a valud of 00 when read. test_aa1 (23h) this register is reserved and must be set to ffh for normal operation. test_aa2 (24h) this register is reserved and must be set to ffh for normal operation 76543210 cbb7 cbb6 cbb5 cbb4 cbb3 cbb2 cbb1 cbb0 r/w 76543210 res res res res res res res pd reserved r/w
cs7666 28 ds302pp1 test_aa3 (25h) this register is reserved and must be set to ffh for normal operation test_aa4 (26h) this register is reserved and must be set to ffh for normal operation flare control 1 (27h) y_thr[9:2] flare control filter y threshold bits 9-2 (msb). (bits 1 and 0 set to 0.) flare control 2 (28h) cr_l [9:2] flare control filter cr low threshold bits 9-2 (msb). flare control 3 (29h) cb_l [9:2] flare control filter cb low threshold bits 9-2 (msb). (bits 1 and 0 set to 0.) flare control 4 (2ah) cr_h [9:2] flare control filter cr high threshold bits 9-2 (msb). flare control 5 (2bh) cb_h [9:2] flare control filter cb high threshold bits 9-2 (msb). (bits 1 and 0 set to 0.) 76543210 y_thr9 y_thr8 y_thr7 y_thr6 y_thr5 y_thr4 y_thr3 y_thr2 r/w 76543210 cr_l9 cr_l8 cr_l7 cr_l6 cr_l5 cr_l4 cr_l3 cr_l2 r/w 76543210 cb_l9 cb_l8 cb_l7 cb_l6 cb_l5 cb_l4 cb_l3 cb_l2 r/w 76543210 cr_h9 cr_h cr_h7 cr_h6 cr_h5 cr_h4 cr_h3 cr_h2 r/w 76543210 cb_h9 cb_h8 cb_h7 cb_h6 cb_h5 cb_h4 cb_h3 cb_h2 r/w
cs7666 ds302pp1 29 flare control 6 (2ch) cr_l [1:0] flare control filter cr low threshold bits 1 and 0. cb_l [1:0] flare control filter cb low threshold bits 1 and 0. cr_h [1:0] flare control filter cr high threshold bits 1 and 0. cb_h [1:0] flare control filter cb high threshold bits 1 and 0. scaler control 1 (2dh) pll_m [4:0] this is the pll m value when the custom bit (bit 3 register 04h) is set. bypass [1:0] see pll section. scaler control 2 (2eh) pll_n [4:0] this is the pll n value when the custom bit (bit 3 register 04h) is set. half sets the internal pll reference clock to 1/2 the input clock. scaler control 3 (2fh) offset [7:0] this value controls the offset fo the internal scaler. configuration control 0 (30h) this register contains the 3 msbs of the eeprom address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 00h. 76543210 cb_h1 cb_h0 cr_h1 cr_h0 cb_l1 cb_l0 cr_l1 cr_l0 r/w r/w r/w r/w 76543210 bypass1 bypass0 res pll_m4 pll_m3 pll_m2 pll_m1 pll_m0 r/w reserved r/w 76543210 half res res pll_n4 pll_n3 pll_n2 pll_n1 pll_n0 r/w reserved r/w 76543210 offset7 offset6 offset5 offset4 offset3 offset2 offset1 offset0 r/w 76543210 res res res res res skp010 skp09 skp08 reserved r/w
cs7666 30 ds302pp1 configuration control 1 (31h) this register contains the 8 lsbs of the eeprom start address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 00h. configuration control 2 (32h) this register contains the 3 msbs of the eeprom address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 01h. configuration control 3 (33h) this register contains the 8 lsbs of the eeprom start address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 01h. configuration control 4 (34h) this register contains the 3 msbs of the eeprom address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 02h. configuration control 5 (35h) this register contains the 8 lsbs of the eeprom start address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 02h. configuration control 6 (36h) this register contains the 3 msbs of the eeprom address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 03h. 76543210 skp07 skp06 skp05 skp04 skp03 skp02 skp01 skp00 r/w 76543210 res res res res res skp110 skp19 skp18 reserved r/w 76543210 skp17 skp16 skp15 skp14 skp13 skp12 skp11 skp10 r/w 76543210 res res res res res skp210 skp29 skp28 reserved r/w 76543210 skp27 skp26 skp25 skp24 skp23 skp22 skp21 skp20 r/w 76543210 res res res res res skp310 skp39 skp38 reserved r/w
cs7666 ds302pp1 31 configuration control 7 (37h) this register contains the 8 lsbs of the eeprom start address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 03h. configuration control 8 (38h) this register contains the 3 msbs of the eeprom address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 04h. configuration control 9 (39h) this register contains the 8 lsbs of the eeprom start address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 04h. configuration control 10 (3ah) this register contains the 3 msbs of the eeprom address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 05h. configuration control 11 (3bh) this register contains the 8 lsbs of the eeprom start address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 05h. configuration control 12 (3ch) this register contains the 3 msbs of the eeprom address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 06h. 76543210 skp37 skp36 skp35 skp34 skp33 skp32 skp31 skp30 r/w 76543210 res res res res res skp410 skp49 skp48 reserved r/w 76543210 skp47 skp46 skp45 skp44 skp43 skp42 skp41 skp40 r/w 76543210 res res res res res skp510 skp59 skp58 reserved r/w 76543210 skp57 skp56 skp55 skp54 skp53 skp52 skp51 skp50 r/w 76543210 res res res res res skp610 skp69 skp68 reserved r/w
cs7666 32 ds302pp1 configuration control 13 (3dh) this register contains the 8 lsbs of the eeprom start address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 06h. configuration control 14 (3eh) this register contains the 3 msbs of the eeprom address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 07h. configuration control 15 (3fh) this register contains the 8 lsbs of the eeprom start address used when the skip bit is set (bit1 register 42h) and the configuration index register (43h) is set to 07h. jump control 0 (40h) this register contains the 3 msbs of the eeprom address used when the jump bit is set (bit2 register 42h). jump control 1 (41h) this register contains the 8 lsbs of the eeprom start address used when the jump bit is set (bit2 register 42h). 76543210 skp67 skp66 skp65 skp64 skp63 skp62 skp61 skp60 r/w 76543210 res res res res res skp710 skp79 skp78 reserved r/w 76543210 skp77 skp76 skp75 skp74 skp73 skp72 skp71 skp70 r/w 76543210 res res res res res jmp10 jmp9 jpm8 reserved r/w 76543210 jmp7 jmp6 jmp5 jmp4 jmp3 jmp2 jmp1 jpm0 r/w
cs7666 ds302pp1 33 eeprom control (42h) state machine commands for loading eeprom data after reset. (see extended eprom configuration) halt writing a 1 to this bit stops the reading of eeprom data. skip writing a 1 to this bit forces the next eeprom read cycle to occur at the address held in the configuration control (n) register, where "n" is the value held in the configuration index regis- ter (43h) jump writing a 1 to this bit forces the next eeprom access to occur at the address held in registers 40h and 40h. configuration index register (43h) this contains the dip switch status at reset. (see extended eprom configuration) the value of this register selects the appropriate configuration register when the skip command is executed. reserved registers (44h - feh) these registers are reserved and return a value of 00h when read. station address register (ffh) cs7666 station address, 7 msbs (the lsb of the complete 8-bit station address is determined by the lsb which acts as a read/write direction bit). 76543210 res res res res res jump skip halt r/w 76543210 res res res res res sw2 sw1 sw0 reserved r/w 76543210 res sa6 sa5 sa4 sa3 sa2 sa1 sa0 reserved r/w
cs7666 34 ds302pp1 pin descriptions power supply connection vdd - power supply, pins 11, 22, 26, 41, 58. positive digital supplies. nominally +5 volts. pin 58 is an analog supply pin used for the internal pll but may be connected to the digital supply pins under most circumstances. gnd - digital ground, pins 10, 21, 27, 40, 50, 57. digital ground supplies. pin 57 is an analog ground pin used for the internal pll but may be connected to the digital ground pins under most circumstances. clkin2x clkin interp scanmode xtal_out clk_grg gnd iset sclsec sdasec di0(lsb) di1 di2 di3 di4 vdd gnd di5 di6 di7 di8 di9(msb) reset vrefin hrefin vrefout hrefout scl sda gnd vdd dob0(lsb) 41 43 45 47 33 35 37 39 7 5 3 1 15 13 11 9 gnd vdd clkout testpinb doa0(lsb) dob9(msb) dob8 dob7 dob6 dob5 dob4 dob3 doa2 gnd vdd doa1 doa6 doa5 doa4 doa3 4bytemode doa9(msb) doa8 doa7 transp field oe scanenable gnd vdd dob2 dob1 17 19 21 23 25 27 29 31 63 61 59 57 55 53 51 49 8 6 4 2 16 14 12 10 18 20 22 24 26 28 30 32 42 44 46 48 34 36 38 40 64 62 60 58 56 54 52 50 64-pin tqfp top view
cs7666 ds302pp1 35 input data and clocks di[9:0] - digital mosaic inputs. cmos level mosaic coded ccd input data from ccd digitizer clkin - mosaic input data clock, pin 55. main system input clock, used to strobe incoming digital ccd mosaic data. the clkin frequency is the mosaic input data rate. clkin2x - mosaic input data interpolation clock, pin 56. mosaic input data interpolation clock or crystal oscillator input. twice the clkin input in cs7665 compatibility mode (non-interpolated output data ... see interp description). twice the 5/4 output rate clock when internal 5 to 4 horizontal data rate scaler is in operation (cs7665 compatibility mode.) in cs7666 native mode, this pin operates as the crystal oscillator input pin. the required crystal frequency is 2 x (scaler ratio) x (input data rate). for example a 512x492 pixel imager running at 9.818 mhz and scaled by a factor of 5:4 would require 2 x (5/4) x (9.818) = 24.54 mhz. clk_grg - ccd sample clock, pin 51. this clock is scaled by the internal pll and is equal to the clkin2x frequency divided by the scaling ratio. this clock is intended to connect to the cs7615 master clock pin (pin 32). xtal_out C crystal oscillator output, pin 52. when using the internal crystal oscillator, connect the external crystal to the xtal_out and clkin2x pins. hrefin - horizontal input timing reference, pin 32. active low horizontal input timing reference. used to synchronize the output timing signals with the incoming mosaic data and timing. when used with ccd digitizers like the cs7615 which imbed the necessary timing signals in the data stream, the hrefin signal is not needed. vrefin - vertical input timing reference, pin 33. active low vertical input timing reference. used to synchronize the output timing signals with the incoming mosaic data and timing. when used with ccd digitizers like the cs7615 which embed the necessary timing signals in the data stream, the vrefin signal is not needed. i 2 c serial control sda - primary i 2 c data bus, pin 28. primary i 2 c data bus. used with scl to read and write the internal register set. scl - primary i 2 c clock, pin 29. primary i 2 c clock. used with sda to read and write the internal register set.
cs7666 36 ds302pp1 sdasec - secondary i 2 c data bus, pin 47. secondary i 2 c data bus with limited bus mastering capabilities. used with sclsec to read and write i 2 c devices located on the secondary bus. various devices can be isolated by the cs7666 from the primary i 2 c bus. the cs7666 will start reading i 2 c eprom devices at addresses a0h after reset . it will download the eprom contents into the specified registers inside the secondary bus devices as well as any cs7666 registers specified in the eprom entries. devices are typically connected to either the primary or the secondary i 2 c bus. however, the two busses may be connected together when system design requires the use of eprom initialization while at the same allowing direct access to all the camera devices from the external i 2 c controller. sclsec - secondary i 2 c clock, pin 48. secondary i 2 c clock with limited bus mastering capabilities. used with sdasec to read and write i 2 c devices located on the secondary bus. various devices can be isolated by the cs7666 from the primary i 2 c bus. the cs7666 will start reading i 2 c eprom devices at addresses a0h after reset , and download the eprom contents into the specified secondary bus registers, as well as any cs7666 registers specified in the eprom entries. devices are typically connected to either the primary or the secondary i 2 c bus. however, the two busses may be connected together when system design requires the use of eprom initialization while at the same time allowing direct access to all the camera devices from the external i 2 c controller. 4bytemode - four-byte mode i 2 c operation enable, pin 1. places cs7666 in the four-byte mode for i 2 c transactions on the primary i 2 c bus. active high. digital video outputs and clocking doa[9:0] - "a" channel digital output bits. cmos level 10-bit digital video output channel "a." either ycrcb interleaved digital video output data, or y component digital video data is available at this port according to the state of bit 5 in register 06h. doa0(lsb) is the least significant bit of channel "a"; doa9(msb) is the most significant bit of channel "a." dob[9:0] - "b" channel digital output bits. cmos level 10-bit digital video output channel "b." either logic "0" in interleaved digital video output data mode, or crcb component digital video data is available at this port according to the state of bit 5 in register 06h. dob0(lsb) is the least significant bit of channel "b;" dob9(msb) is the most significant bit of channel "b."
cs7666 ds302pp1 37 clkout - digital output data clock, pin 59. digital output clock for both channel "a" and channel "b." output data transitions on the falling edge of clkout and can be latched on the rising edge. in the non-interleaved output mode, the clkout rate is equal to the input mosaic pixel rate multiplied by the scaling ratio currently in use with y data available on channel "a" and crcb output data on channel "b." in interleaved output mode, the clkout rate is equal to twice the input mosaic pixel rate multiplied by the current scaling ratio with y and crcb output data available on channel "a". interp - digital video horizontal data rate scaler enable, pin 54. cmos input enabling the internal 4:5 horizontal data rate scaler when the cs7666 is in cs7665 compatibility mode (default.) requires that clkin2 be supplied with a 5/2 rate clock relative to the clkin clock input which is the incoming ccd mosaic data. this pin control is active logic high. this pin is ignored in cs7666 native mode. hrefout - horizontal reference output, pin 30. cmos output providing href, or alternatively hsync horizontal blanking signal. vrefout - vertical reference output, pin 31. cmos output providing a vref, or alternatively vsync vertical blanking signal. field - odd/even field indicator, pin 62. cmos input/output. as an input, the field pin synchronizes the eav/sav timing codes embedded in the output video datastream. as an output, the field indicator changes according to the embedded eav/sav timing codes in the input video datastream or the hrefin and vrefin inputs. odd fields are indicated with logic low, and even fields are indicated with logic high. alternately, the field pin can be configured as a u/v clock. oe - output enable, pin 63. cmos input used to place all output pins in a high-z mode. this control works in conjunction with the oe bit (bit 3)in register 06h. output mode mosaic data rate clkin clkin2 channel a channel "b clkout horizontal pixels interleaved, scaler disabled 9.818 mhz 9.818 mhz 19.63 mhz ycrcb logic "0 19.63 mhz 512 interleaved, scaler enabled 9.818 mhz 9.818 mhz 24.54 mhz ycrcb logic "0 24.54 mhz 640 parallel, scaler disabled 9.818 mhz 9.818 mhz 19.63 mhz y crcb 9.818 mhz 512 parallel, scaler enabled 9.818 mhz 9.818 mhz 24.54 mhz y crcb 12.27 mhz 640 table 16. example 512x492 imager output options (4:5 scaling ratio chosen)
cs7666 38 ds302pp1 miscellaneous reset - master external reset control, pin 34. cmos input which initiates a complete power-on reset, where all registers are reset to their defaults, and the secondary i 2 c bus attempts to load any eprom configuration information. this pin operates in conjunction with bit 0 of register 00h. reset is an active logic low input. iset C pll bias , pin 49. connect this pin to analog gnd (pin 57) through a 6,000 ohm 1% resistor. scanmode - test pin, pin 53. test pin, connect to gnd. testpinb - test pin, pin 60. test pin, connect to vdd. transp - test pin, pin 61. test pin, connect to vdd. scanenable - test pin, pin 64. test pin, connect to gnd.
cs7666 ds302pp1 39 definitions color space a color space is a mathematical representation of a set of colors. three fundamental color models are rgb (used in color computer graphics and color television), yiq, yuv, or ycrcb (used in broadcast and television systems), and cmyk (used in color printing). rgb color space the red, green, and blue (rgb) is widely used throughout computer graphics and imaging. red, green, and blue are three primary additive colors where the individual components are added together to form the desired color. yuv color space the yuv color space is the basic color space used by the pal (phase alternation line), ntsc (national television system committee), and secam (sequential couleur avec memoire or sequential color with memory) composite color video standards. the format conveys intensity in the y component and color information in the u and v components. in an 8-bit system, where rgb range from code 0 to code 255, y has a range of code 0 to code 255. the u component ranges over code 0 112 codes, and the v component ranges over code 0 157. ycrcb color space the ycrcb color space was developed as part of recommendation itu-601 during the development of a world-wide digital component video standard. ycrcb are scaled and offset versions of yuv color space. y is defined to have a nominal range of code 16 to code 235; cr and cb are defined to have a range of code 16 to code 240, with code equal to the zero level. mycg colors standard "color" ccd imagers employ integrated filter dots over the individual pixels. typically, four color filters are used, magenta, yellow, cyan, and green. chroma block a group of four adjacent ccd pixel with integrated mycg filter dots. these four pixels are generally formed with two pixels on one horizontal scan line, and two physically just below on the next scan line. there can also be some slight horizontal shift of the pixels to smooth the image. the chroma block is generally processed using a "color separator" into yuv, ycrcb, or rgb color space before any image processing.
cs7666 40 ds302pp1 package dimensions inches millimeters dim min max min max a 0.000 0.063 0.00 1.60 a1 0.002 0.006 0.05 0.15 b 0.007 0.011 0.17 0.27 d 0.461 0.484 11.70 12.30 d1 0.390 0.398 9.90 10.10 e 0.461 0.484 11.70 12.30 e1 0.390 0.398 9.90 10.10 e 0.016 0.024 0.40 0.60 l 0.018 0.030 0.45 0.75 0.000 7.000 0.00 7.00 64l tqfp package drawing e1 e d1 d 1 e l b a1 a
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