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the information in this document is subject to change without notice. mos integrated circuit m m m m pd98401a atm sar chip 1997 document no. s12100ej3v0ds00 (3rd edition) date published february 1999 n cp(k) printed in japan data sheet the mark shows major revised points. description the m pd98401a (neascot-s15 tm ) is a high-performance sar chip that segments and reassembles atm cells. this chip can interface with an atm network when it is included in a workstation, computer, front-end processor, network hub, or router. the m pd98401a conforms to the atm forum recommendation, and provides the functions of the aal-5 sar sublayer and atm layer. the m pd98401a is compatible with its predecessor, m pd98401, in terms of hardware and software. functions are explained in detail in the following users manual. be sure to read this manual when designing your system. m m m m pd98401a users manual: s12054e features ? conforms to atm forum ? aal-5 sar sublayer and atm layer functions ? hardware support of aal-5 processing ? processing of non-aal-5 traffic (aal-3/4 cell, oam cell, rm cell) by software with raw cell processing function ? hardware support of comparison/generation of crc-10 for non-aal-5 traffic ? supports up to 32k virtual channels (vc) ? provided with 16 traffic shapers that carry out transmission scheduling (control of average rate/peak rate) so as to set different transmission rate for each vc ? interface and commands for controlling phy device ? employs utopia interface as cell data interface with phy device - octet-level handshake - cell-level handshake ? 32-bit general-purpose bus interface ? high-speed dmac (supports 1-, 2-, 4-, 8-, 12-, and 16-word burst) ? jtag boundary scan test function (ieee1149.1) ? cmos technology ? +5 v single power source remark in this document, an active low pin is indicated by _b (_b after a pin name).
data sheet s12100ej3v0ds00 2 m m m m pd98401a ordering information part number package m pd98401agd-mml 208-pin plastic qfp (fine pitch) (28 28 mm) system configuration m pd98401a m pd98402a pmd atm interface card control memory bus interface reception transmission atm network i/o bus block diagram system port dma controller and host interface receive data fifo reception controller transmission controller sequencer transmit data fifo (10 cells) phy interface reception block control memory interface phy interface transmission block phy device transmission block control memory phy device reception block
data sheet s12100ej3v0ds00 3 m m m m pd98401a pin configuration rx7-rx0 rclk renbl_b rsoc empty_b/rxclav tx7-tx0 tclk tenbl_b tsoc full_b/txclav phrw_b phoe_b phce_b phint_b ad31-ad0 par3-par0 oe_b size2-size0 dr/w_b attn_b gnt_b rdy_b abrt_b err_b sr/w_b v dd sel_b asel_b clk rst_b intr_b cd31-cd0 cpar3-cpar0 ca17-cad cwe_b coe_b cbe_b3-cbe_b0 initd dbmd dbvc dbml dbmf dbmr jdo jdi jck jms jrst_b trf_b v dd gnd phy interface bus interface master slave power supply test pin (fixed to low level) jtag boundary scan interface bus monitoring control memory interface
data sheet s12100ej3v0ds00 4 m m m m pd98401a pin configuration (top view) 208-pin plastic qfp (fine pitch) (28 28 mm) v dd dbvc dbmr gnd v dd jrst_b jms jdi jdo gnd v dd jck gnd v dd dbmf dbml dbmd gnd v dd trf_b intid coe_b cwe_b cbe_b0 cbe_b1 v dd gnd cbe_b2 cbe_b3 ca0 ca1 ca2 ca3 gnd v dd ca4 ca5 ca6 ca7 ca8 ca9 ca10 gnd v dd ca11 ca12 ca13 ca14 ca15 ca16 ca17 v dd 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 gnd gnd cpar0 cpar1 cpar2 cpar3 gnd cd0 cd1 cd2 cd3 cd4 cd5 cd6 v dd gnd cd7 cd8 cd9 cd10 cd11 cd12 cd13 cd14 cd15 gnd v dd cd16 cd17 cd18 cd19 cd20 v dd gnd cd21 cd22 cd23 cd24 cd25 cd26 cd27 gnd v dd cd28 cd29 cd30 cd31 phrw_b phoe_b phint_b gnd gnd 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 gnd gnd ad31 ad30 ad29 ad28 ad27 gnd ad26 ad25 ad24 ad23 ad22 gnd v dd ad21 ad20 ad19 ad18 ad17 gnd ad16 ad15 ad14 ad13 gnd v dd ad12 rst_b v dd gnd clk gnd v dd ad11 ad10 ad9 ad8 ad7 gnd v dd ad6 ad5 ad4 ad3 ad2 ad1 ad0 par3 par2 gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 v dd par1 par0 oe_b size2 v dd gnd size1 size0 dr/w_b attn_b gnd_b rdy_b abrt_b err_b sr/w_b sel_b asel_b intr_b v dd gnd rx7 rx6 rx5 rx4 v dd gnd rx3 rx2 rx1 rx0 rclk renbl_b rsoc empty_b/rxclav full_b/txclav tsoc tenbl_b gnd tclk gnd v dd tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 phce_b v dd 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 pd98401agd-mml m
data sheet s12100ej3v0ds00 5 m m m m pd98401a pin names abrt_b : abort phce_b : phy chip enable ad31_ad0 : address/data phint_b : phy interrupt asel_b : slave address select phoe_b : phy output enable attn_b : attention/burst frame phrw_b : phy read/write ca17-ca0 : control memory address rclk : receive clock cbe_b3_cbe_b0 : local port byte enable rdy_b : target ready cd31-cd0 : control memory data renbl_b : receive enable clk : clock rsoc : receive start cell coe_b : control memory output enable rst_b : reset cpar3-cpar0 : control memory parity rx7-rx0 : receive data bus cwe_b : control memory write enable sle_b : slave select dbmd : dma bus monitor data size2-size0 : burst size dbmf : dma bus monitor first sr/w_b : slave read/write dbml : dma bus monitor last tclk : transmit clock dbvc : dma bus monitor vc tenbl_b : transmit enable dbmr : dma bus monitor remaining tsoc : transmit start of cell dr/w_b : dma read/write trf_b : delay select empty_b/rxclav : phy output buffer empty tx7-tx0 : transmit data bus err_b : error v dd : power supply full_b/txclav : phy buffer ful gnd : ground gnt_b : grant initd : initialization disable intr_b : interrupt jck : jtag test pin jdi : jtag test pin jdo : jtag test pin jms : jtag test pin jrst_b : jtag test pin oe_b : output enable par3-par0 : bus parity
data sheet s12100ej3v0ds00 6 m m m m pd98401a contents 1. pin function ................................................................................................................ ..................... 7 1.1 phy device interface pin ................................................................................................... .......... 7 1.2 bus interface pins ......................................................................................................... ............... 9 1.3 bus monitor pins ........................................................................................................... ............. 12 1.4 control memory interface pins.............................................................................................. .... 13 1.5 jtag boundary scan pins .................................................................................................... .... 14 1.6 test pin................................................................................................................... ..................... 14 1.7 power supply and ground pins............................................................................................... .14 1.8 pin status during and after reset .......................................................................................... .. 15 2. differences from m m m m pd98401.................................................................................................... 16 2.1 additional functions....................................................................................................... ........... 16 2.2 differences from m m m m pd98401 (neascot-s10 tm )........................................................................ 16 3. electrical specifications .................................................................................................. .... 17 4. package drawings ............................................................................................................ .......... 33 5. recommended soldering conditions.................................................................................. 34
data sheet s12100ej3v0ds00 7 m m m m pd98401a 1. pin function the m pd98401a is housed in a package having 208 pins, of which 152 pins are function pins and 56 pins are v dd and gnd pins. 1.1 phy device interface pin phy device interfaces include a utopia interface through which the m pd98401a transfers atm cells with a phy device, and a phy control interface by which the m pd98401a controls the phy device. (1) utopia interface (1/2) pin name pin no. i/o i/o level function rx7-rx4 rx3-rx0 74 - 77 80 - 83 i ttl receive data bus. rx7 through rx0 constitute an 8-bit input bus which inputs data received from a network in byte format from a phy device. the m pd98401a loads data in at the rising edge of rclk. rsoc 86 i ttl receive start cell. the rsoc signal is input in synchronization with the first byte of the cell data from a phy device. this signal remains high while the first byte of the header is input to rx7 through rx0. renbl_b 85 o cmos receive enable. the renbl_b signal indicates to a phy device that the m pd98401a is ready to receive data in the next clock cycle. this si gnal goes high during and after reset. empty_b/ rxclav 87 i ttl phy output buffer empty/rx cell available. this signal notifies the m pd98401a that there is no cell data to be transferred in the receive fifo and that no receive data can be supplied to the phy device. when the utopia interface is in the octet-level handshake mode, this signal serves as empty_b, indicating that the data on rx7 through rx0 are invalid in the current clock cycle. in the cell-level handshake mode, it serves as rxclav, indicating that there is no cell to be supplied next after the transfer of the current cell is completed. rclk 84 o cmos receive clock. this is a synchronization clock used to transfer cell data with the phy cell device at the recieve side. the system clock i nput to the clk pin is output from this pin as is, immediately after reset. tx7-tx0 95 - 102 o cmos transmit data bus. tx7 through tx0 constitute an 8-bit output bus which outputs transmit data in byte format to a phy device. the m pd98401a outputs data at the rising edge of tclk. tsoc 89 o cmos transmit start of cell. the tsoc signal is output in synchronization with the first byte of transmit cell data.
data sheet s12100ej3v0ds00 8 m m m m pd98401a (2/2) pin name pin no. i/o i/o level function tenbl_b 90 o cmos transmit enable. the tenbl_b signal indicates to a phy device that data has been output to tx7 through tx0 in the current clock cycle. this si gnal remains high during reset and after reset. full_b/ txclav 88 i ttl phy buffer full/tx cell available. the full_b signal notifies the m pd98401a that the input buffer of the phy device is full and that the device can receive no more data. when the utopia interface is in the octet-level handshake mode, the phy device inputs an inactive level to receive cell of data. in the cell- level handshake mode, this signal indicates that the phy device can receive all the next one cell of data after the current cell has been completely transferred tclk 92 o cmos transmit clock. this is a synchronization clock used to transfer cell data with the phy device at the transmission side. the system clock i nput to the clk pin is output from this pin as is. (2) phy device control interface pin name pin no. i/o i/o level function phrw_b 109 o cmos phy read/write. the m pd98401a indicates the direction in which the phy device is controlled, by using phrw_b. this signal goes low after reset. 1: read 0: write phoe_b 108 o cmos phy output enable. the m pd98401a enables output from the phy device by making phoe_b low phce_b 103 o cmos phy chip enable. the m pd98401a makes phce_b low to access a phy device. this signal goes high after reset. phint_b 107 i ttl phy interrupt. this is an interrupt input signal from a phy device. the phy device indicates to the m pd98401a that it has an interrupt source, by inputting a low level to phint_b. this signal goes high after reset.
data sheet s12100ej3v0ds00 9 m m m m pd98401a 1.2 bus interface pins the bus interface is a general-purpose bus interface compatible with most generally used i/o buses (such as pci, s bus, gio, and ap bus). (1/3) pin name pin no. i/o i/o level function ad31-ad27 ad26-ad22 ad21-ad17 ad16-ad13 ad12 ad11-ad7 ad6-ad0 3 - 7 9 - 13 16 - 20 22 - 25 28 35 - 39 42 - 48 i/o 3-state ttl in cmos out address/data. ad31 through ad0 constitute a 32-bit address/data bus. these pins are i/o pins multiplexing an address bus and a data bus. at the first clock of input/output, ad31 through ad0 transfer an address. they transfer data at the second clock and onward. the ad bus goes into a high-impedance state when the m pd98401a does not access the bus. par3 par2 par1 par0 49 50 54 55 i/o 3-state ttl in cmos out bus parity. par pins indicate the parity of ad31 through ad0. a parity check mode is set by gmr. enabling or disabling parity, odd or even parity, and word or byte parity can be specified. if byte parity is specified, par3 indicates the parity of ad31 through ad24, and par0 indicates the parity of ad7 through ad0. if word parity is specified, par3 serves as an input/output pin. it serves as an output pin when an address is output and when data is written, and as an input pin when data is read. when the m pd98401a does not access the bus, par3 through par0 go into a high-impedance state. pull up these pins when they are not used. oe_b 56 i ttl output enable. when this pin is low, the m pd98401a uses ad31 through ad0 and par3 through par0 as 3-state i/o pins. these pins go into a high- impedance state while a high level is being input to oe_b. this pin is an option pin. fix this pin to low level in a system where it is not necessary to forcibly set the bus of the m pd98401a in a high- impedance state by controlling this pin. size2 size1 size0 57 60 61 o cmos burst size. size2 through size0 indicate the size of the current dma transfer. these pins are used to interface a bus (such as s bus) requiring clear burst size. size2 size1 size0 function 0 0 0 1-word transfer 0 0 1 2-word burst 0 1 0 4-word burst 0 1 1 8-word burst 1 0 0 16-word burst 1 0 1 12-word burst 1 1 0 undefined 1 1 1 reception side byte alignment
data sheet s12100ej3v0ds00 10 m m m m pd98401a (2/3) pin name pin no. i/o i/o level function dr/w_b 62 o cmos dma read/write. dr/w_b indicates the direction of dma access. 1: read access 0: write access this pin is set to 1 after reset. attn_b 63 o cmos attention/burst frame (dma request). the m pd98401a makes the attn_b signal low when it performs a dma operation. the attn_b signal becomes inactive at the rising edge of clk when the data to be transferred by means of dma has decreased to 1 word. gnt_b 64 i ttl grant. the gnt_b signal inputs a low level when the bus arbiter grants the m pd98401a use of the bus in response to a dma request from the m pd98401a. the m pd98401a recognizes that it has been granted use of the bus and starts dma operation when the gnt_b signal goes low (active). make sure that the gnt_b signal falls at least one system clock cycle after the rising of the attn_b si gnal. the gnt_b signal must be returned to the high (inactive) level before the m pd98401a makes the attn_b signal low (active) to issue the next dma cycle r equest. rdy_b 65 i ttl target ready. rdy_b indicates to the m pd98401a in the dma cycle that the target device is ready for input/output. during the dma read operation of the m pd98401a, the rdy_b signal is made low if valid data is on ad31 through ad0. during the dma write operation of the m pd98401a, the rdy_b signal is made low if the target device is ready for receiving data. the sampling timing of the rdy_b and abrt_b signals of the m pd98401a can be advanced by one clock (early mode) by using an internal register (gmr register). abrt_b 66 i ttl abort. abrt_b is used to abort the dma transfer cycle. if this si gnal goes low while data is being transferred in the dma cycle, dma transfer is aborted in that cycle, and the attn_b signal is briefly deasserted inactive. after that, the m pd98401a asserts the attn_b signal active again, and resumes burst transfer from the data at which the dma transfer was aborted. while a low level is input to abrt_b, the rdy_b signal is ignored. the user can advance the sampling timing of the rdy_b and abrt_b signals of the m pd98401a by one clock (early mode) by using an internal register (gmr register). pull up this pin when it is not used. err_b 67 i ttl error. this pin is used by a device that manages the bus to stop the operation of the m pd98401a when occurrence of an error is detected on the system bus. when a low level is input to this pin, the m pd98401a stops all bus operations, sets the system bus error bit (bit 25) of the gsr register (when not masked), and generates an interrupt. pull up this pin when it is not used.
data sheet s12100ej3v0ds00 11 m m m m pd98401a (3/3) pin name pin no. i/o i/o level function sr/w_b 68 i ttl slave read/write. the sr/w_b signal determines the direction in which the slave is accessed. 1: read access 2: write access sel_b 69 i ttl slave select. this signal goes low (active) when the m pd98401a is accessed as a slave. the sel_b signal must goes low as soon as or after the asel_b signal has gone low. an inactive period of at least 2 system clock cycles must be inserted betw een when the sel_b signal has become inactive and when it becomes active again. asel_b 70 i ttl slave address select. the asel_b signal is used to select the direct address register of the m pd98401a. when a low level is input to asel_b, the m pd98401a samples the ad bus at the first rising edge of clk. clk 32 i ttl clock. this pin inputs the system clock. i nput a clock in a range of 8 to 33 mhz. rst_b 29 i ttl reset. the rst_b signal initializes the m pd98401a (on starting, etc.). after reset, the m pd98401a can start normal operation. when a low level is input to rst_b, the internal state machine and registers of the m pd98401a are reset, and all 3-state signals go into a high- impedance state. the reset input is asynchronous. when this signal is input during operation, the operating status at that time is lost. hold rst_b low at least for the duration of one clock. after reset, do not access the m pd98401a for at least 20 clock cycles. intr_b 71 o nch open- drain output interrupt. this is an open-drain signal and must be pulled up. intr_b informs the cpu that the interrupt bit (unmasked) of the gsr register is set.
data sheet s12100ej3v0ds00 12 m m m m pd98401a 1.3 bus monitor pins the bus monitor pins indicate the type of data under dma transfer. these five pins are enabled when the bme bit of the gmr register is set to 1; they go into a high-impedance state when the bme bit is 0. pin name pin no. i/o i/o level function dbmd 192 o 3-state cmos dma bus monitor data. this pin indicates that the payload of an aal-5 cell is under dma transfer. this pin is enabled when the bme bit of the gmr register is set to 1, and goes into a high-impedance state when the bme bit is 0. the dbmd signal changes in synchronization with the falling of the attn_b signal. the high level of this signal indicates that the payload of an all-5 packet transmit/receive cell is under dma transfer, and low level indicates that the other data is being transferred. dbml 193 o 3-state cmos dma bus monitor last. if one-word data currently under dma transfer satisfies any of the following conditions, this pin goes high in synchronization with output of the data. last 1 word of last cell of aal-5 packet 1-word data to be written to last word of receive buffer last 1-word data of last cell of receive packet in which max. number of segments error has occurred when this pin is low, it indicates that the data is other than above. this pin is enabled when the bme bit of the gmr register is set to 1; it goes into a high-impedance state when the bit is 0. dbmf 194 o 3-state cmos dma bus monitor first. this pin indicates that the data under dma transfer is the start cell of a receive aal-5 packet. this pin is enabled when the bme bit of the gmr register is set to 1; it goes into a high-impedance state when the bit is 0. this pin goes high in synchronization with the last word data of the first cell of an aal-5 packet. dbmr 206 o 3-state cmos dma bus monitor remaining. this pin indicates that the number of cells remaining in the transmit buffer is equal to, or has dropped below the value assigned to the rcs register. this pin is enabled when the bme bit of the gmr register is set to 1; it goes into a high-impedance state when the bit is 0. dbvc 206 o 3-state cmos dma bus monitor vc. this pin indicates that the data currently being transferred by dma is that of the vc for which the vcp bit in the receive vc table is set to 1. this pin is asserted active in synchronization with the falling of attn_b. it is enabled when the bme bit of the gmr register is set to 1, and goes into a high-impedance state when the bit is 0.
data sheet s12100ej3v0ds00 13 m m m m pd98401a 1.4 control memory interface pins these pins constitute an interface through which the m pd98401a accesses an external control memory and a phy device. a 18-bit address bus and a 32-bit data bus are used. the control memory of the host is accessed only via this interface. pin name pin no. i/o i/o level function cd31-cd28 cd27-cd21 cd20-cd16 cd15-cd7 cd6-cd0 110-113 116-122 125-129 132-140 143-149 i/o 3-state ttl in, cmos out control memory data. cd31 through cd0 are 3-state i/o pins and constitute a 32-bit data bus which is used to transfer data with the control memory or a phy device. cpar3- cpar0 151-154 i/o ttl in, cmos out control memory parity. cpar3 through cpar0 indicate the parity of cd31 through cd0 in 8- bit units. in the read cycle, the m pd98401a che cks the parity (when enabled). in the write cycle, cpar3 thr ough cpar0 output the parity. pull up these pins when they are not used. ca17-c11 ca10-ca4 ca3-ca0 158-164 167-173 176-179 o cmos control memory address. ca17 through ca0 constitute an 18-bit address bus. they output an address to the control memory or a phy device during read/write operation. cwe_b 186 o cmos control memory write enable. cwe_b signal indicates the direction in which the control memory is accessed. 1: read access 2: write access coe_b 187 o cmos control memory output enable coe_b enables or disables data output of the control memory. cbe_b3 cbe_b2 cbe_b1 cbe_b0 180 181 184 185 o cmos local port byte enable. cbe_b3 through cbe_b0 indicate the byte on the control port to be read or written. initd 188 i ttl initialization disable. the initd signal is used to disable automatic initialization of the control memory during chip test. during normal operation other than test, directly connect initd to gnd.
data sheet s12100ej3v0ds00 14 m m m m pd98401a 1.5 jtag boundary scan pins pin name pin no. i/o i/o level function jdi 201 i ttl jtag test data input. the jdi pin is used to input data to the jtag boundary scan circuit register. normally, fix this pin to high or low level. jdo 200 o 3-state cmos jtag test data output. the jdo pin is used to output data from the jtag boundary scan circuit register. it changes output at the falling edge of the clock input to the jck pin. normally, leave this pin open. jck 197 i ttl jtag test clock. this pin is used to supply a clock to the jtag boundary scan circuit register. normally, fix this pin to a high or low level. jms 202 i ttl jtag test mode select. normally, fix this pin to a high or low level. jrst_b 203 i ttl jtag test reset. this pin initializes the jtag boundary scan circuit register. normally, fix this pin to a low level. 1.6 test pin pin name pin no. i/o i/o level function trf_b 189 i ttl this pin is used to test the internal circuitry of the chip. 0: normal operation 1: test normally, directly connect this pin to ground and fix it to a low level. 1.7 power supply and ground pins pin name pin no. i/o function v dd 15, 27, 30, 34, 41, 53, 58, 72, 78, 94, 104, 114, 124, 130, 142, 157, 165, 174, 183, 190, 195, 198, 204, 208 ? power supply (24 pins) these 24 v dd pins supply a voltage of +5 v 5% to the chip. gnd 1, 2, 8, 14, 21, 26, 31, 33, 40, 51, 52, 59, 73, 79, 91, 93, 105 ,106, 115, 123, 131, 141, 150, 155, 156, 166, 175, 182, 191, 196, 199, 205 ? ground (32 pins) connect these pins to ground.
data sheet s12100ej3v0ds00 15 m m m m pd98401a 1.8 pin status during and after reset pin during reset after reset ad0-ad31 hi-z (input mode) hi-z (input mode) par0-par3 hi-z (input mode) hi-z (input mode) size0-size2 0 0 dr/w_b 1 1 attn_b 1 1 intr_b 1 (however, pulled up) 1 (however, pulled up) ca17-ca0 0 0 cd0-cd31 all 0 (output mode) all 0 (output mode) cwe_b 1 1 coe_b 1 1 (repetition of high/low) cbe_b3-cbe_b0 all 1 all 1 phrw_b 0 0 phoe_b 1 1 phce_b 1 1 rclk clk output clk output renbl_b 1 0 tx0-tx7 all 0 all 0 tclk clk output clk output tenbl_b 1 1 tsoc 0 0 jdo hi-z (3-state) hi-z (3-state) dbmd hi-z hi-z dbml hi-z hi-z dbmf hi-z hi-z dbmr hi-z hi-z dbvc hi-z hi-z
data sheet s12100ej3v0ds00 16 m m m m pd98401a 2. differences from m m m m pd98401 2.1 additional functions the m pd98401a is compatible with the m pd98401 in terms of hardware and software. however, the m pd98401a has the following additional functions as compared with the m pd98401. all the additional functions are enabled by the setting of the gmr register. (1) dma 12-word burst cycle (2) byte alignment transfer function of receive data buffer (3) bus monitor pin (4) mode to insert idle cell for transmission rate adjustment (5) new scheduling function aggregate mode (6) receive packet size indication (cell units/length mode added) (7) cell-level support of utopia interface (8) aal-3/4 traffic assist function (9) jtag boundary scan support 2.2 differences from m m m m pd98401 (neascot-s10 tm ) (1) increased receive fifo size m pd98401 : 10 cells m pd98401a : 23 cells (2) cell processing of pti field (1 xx ) m pd98401 : receives cells other than those of oam f5 pattern (101, 100) as user data cells. m pd98401a : processes as raw cell of 1 xx pattern. stores in pool 0. (3) changing transmission mode of unassigned cell the m pd98401 starts transmitting unassigned cells immediately after power application and continues transmitting the unassigned cells while there is no active transmission vc. it also has a function to stop transmitting unassigned cells while there is not an active vc, by using the uce bit of the gmr register. the m pd98401a deletes this uce bit function, makes the tenbl_b signal inactive on power application and when there is no active vc, and does not transmit unassigned cells. the m pd98401a transmits unassigned cells only when there is an active vc and when the unassigned cell generator function is enabled.
data sheet s12100ej3v0ds00 17 m m m m pd98401a 3. electrical specifications an asterisk (*) mark indicates portion which have been revised from m pd98401. absolute maximum ratings parameter symbol condition ratings unit supply voltage v dd - 0.5 to +6.5 v input voltage v i - 0.5 to v dd +0.5 v * output current i o1 note 1 24 ma * i o2 note 2 36 ma * operating ambient temperature t a 0 to +80 c storage temperature t stg - 65 to +150 c caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the product(s). be sure to use the product(s) within the ratings. * dc characteristics (t a = 0 to +80 c, v dd = 5 v 5 %) parameter symbol condition min. typ. max. unit low level input voltage v il - 0.5 +0.8 v high level input voltage v ih1 except pins rst_b or clk +2.2 v dd + 0.5 v v ih2 pins rst_b or clk +3.3 v dd + 0.5 v high level output voltage v oh1 note 1 i oh = - 4.0 ma v dd 0.7 v v oh2 note 2 i oh = - 6.0 ma v dd 0.7 v low level output voltage v ol1 note 1 i ol = 8.0 ma 0.4 v v ol2 note 2 i ol = 12.0 ma 0.4 v supply current i dd normal operation 350 500 ma input leakage current i li v i = v dd or gnd - 10 +10 m a output leakage current i oz vo = v dd or gnd - 10 +10 m a notes 1. i o1 , v oh1 and v ol1 apply to the following pins: cd31 - cd0, cpar3 - cpar0, ca17 - ca0, cbe_b3 - cbe_b0, cwe_b, coe_b, rclk, renbl_b, tsoc, tenbl_b, tclk, tx7 - tx0, phce_b, phoe_b, phrw_b, jdo 2. i o2 , v oh2 and v ol2 apply to the following pins: ad31 - ad0, par3 - par0, size2 - size0, dr/w, attn_b, intr_b, dbmd, dbml, dbmf, dbmr, dbvc
data sheet s12100ej3v0ds00 18 m m m m pd98401a capacitance (t a = 25 c, v dd = 0 v, f = 1 mhz) parameter symbol condition min. typ. max. unit output capacitance c o f = 1 mhz 7 10 pf input capacitance c i f = 1 mhz 7 10 pf i/o capacitance c io f = 1 mhz 7 10 pf ac characteristics (t a = 0 to +80 c, v dd = 5 v 5 %) ac test condition test point v dd 0 v 2.5 v 2.5 v * load condition d.u.t (device to be tested) c l = 50 pf clk input parameter symbol condition min. typ. max. unit clk cycle time t cyclk 30 125 ns * clk high level width t clkh 11 ns * clk low level width t clkl 11 ns * clk rise time t r 4ns * clk fall time t f 4ns t cyclk clk t clkh t f t r t clkl
data sheet s12100ej3v0ds00 19 m m m m pd98401a phy interface (1/2) (1) transmission operation parameter symbol condition min. typ. max. unit tclk - ? t x delay time t dtx 318ns tclk - ? tsoc delay time t dtsoc 318ns tclk - ? tembl_b delay time t dten 318ns * full_b setup time t sfull 8ns full_b hold time t hfull 1ns h1 h2 h3 h4 p1 p2 p3 p4 p5 p6 p7 p8 p9 t dtx t dtsoc t dtsoc t dten t hfull t sfull t dten tclk h4-h1 p9-p1 : atm header : payload data tx7-tx0 tsoc tenbl_b full_b ?0h invalid
data sheet s12100ej3v0ds00 20 m m m m pd98401a phy interface (2/2) (2) reception operation parameter symbol condition min. typ. max. unit * r x setup time t srx 8ns r x hold time t hrx 1ns * rsoc setup time t srsoc 8ns rsoc hold time t hrsoc 1ns rclk - ? renbl_b delay time t dren 318ns * empty_b setup time t sempt 8ns empty_b hold time t hempt 1ns h1 h2 h3 h4 h5 p1 p2 p3 p4 p5 p6 p7 t srx t hrx t srsoc t hrsoc t dren t dren t sempt t hempt rclk h4-h1 p7-p1 : atm header : payload data rx7-rx0 rsoc renbl_b empty_b invalid invalid
data sheet s12100ej3v0ds00 21 m m m m pd98401a host slave access (1/2) (1) write parameter symbol condition min. typ. max. unit asel_b setup time t sasel 8ns asel_b hold time t hasel 3ns sel_b setup time t ssel 8ns sel_b hold time t hsel 1t cyclk +3 ns address setup time t sdadd 8ns address hold time t hdadd 3ns data setup time t sddat 8ns data hold time t hddat 3ns par setup time t spar1 8ns par hold time t hpar1 3ns sr/w_b setup time t ssrw 8ns sr/w_b hold time t hsrw 3ns write timing address data (input) (input) t sasel t ssel t sdadd t ssrw t spar1 t hpar1 t hpar1 t spar1 t hsrw t sddat t hdadd t hddat t hsel t hasel clk asel_b sel_b ad31-ad0 sr/w_b par3-par0
data sheet s12100ej3v0ds00 22 m m m m pd98401a host slave access (2/2) (2) read parameter symbol condition min. typ. max. unit asel_b setup time t sasel 8ns asel_b hold time t hasel 3ns sel_b setup time t ssel 8ns sel_b hold time t hsel 1t cyclk +3 ns address setup time t sdadd 8ns address hold time t hdadd 3ns * clk - ? data delay time t dddat 20 ns clk - ? data floating time t fddat 318ns par setup time t spar1 8ns par hold time t hpar1 3ns * clk - ? par delay time t dpar1 20 ns clk - ? par floating time t fpar1 318ns sr/w_b setup time t ssrw 8ns sr/w_b hold time t hsrw 3ns read timing address (input) (input) (output) t sasel t ssel t sdadd t hdadd t fddat t dddat t dpar1 t hsel t hasel t ssrw t spar1 t hsrw t hpar1 t fpar1 clk asel_b sel_b ad31-ad0 sr/w_b par3-par0 data (output)
data sheet s12100ej3v0ds00 23 m m m m pd98401a dma access (1/2) (1) write parameter symbol condition min. typ. max. unit clk - ? attn_b delay time t dattn 18 ns gnt_b setup time t sgnt 8ns gnt_b hold time t hgnt 3ns clk - ? dr/w_b delay time t ddrw 318ns clk - ? size delay time t dsize 318ns * clk - ? address delay time t dsadd 20 ns clk - ? address/data floating time t fsadd 318ns * clk - ? par delay time t dpar2 20 ns clk - ? par floating time t fpar2 318ns * rdy_b setup time t srdy 8ns rdy_b hold time t hrdy 3ns write timing ( example: 2 word burst) data 1 (output) (output) hi-z t dattn t ddrw t dsize t hrdy t dpar2 t fpar2 t dpar2 t srdy t hrdy t srdy t dattn t ddrw t dsize t dsadd t fsadd t fsadd t hgnt t sgnt data 0 (output) clk attn_b gnt_b dr/w_b size2-size0 par3-par0 ad31-ad0 rdy_b (normal mode) rdy_b (early mode) (output) (output) address (output)
data sheet s12100ej3v0ds00 24 m m m m pd98401a dma access (2/2) (2) read parameter symbol condition min. typ. max. unit clk - ? attn b_delay time t dattn 18 ns gnt_b setup time t sgnt 8ns gnt_b hold time t hgnt 3ns clk - ? dr/w_b delay time t ddrw 318ns clk - ? size delay time t dsize 318ns * clk - ? address delay time t dsadd 20 ns clk - ? address/data floating time t fsadd 318ns * clk - ? par delay time t dpar2 20 ns * rdy_b setup time t srdy 8ns rdy_b hold time t hrdy 3ns data setup time t ssdat 8ns data hold time t hsdat 3ns par setup time t spar2 8ns par hold time t hpar2 3ns read timing (example: 2 word burst) address (output) hi-z t dattn t ddrw t dsize t hrdy t hpar2 t spar2 t dpar2 t srdy t hrdy t srdy t dattn t ddrw t dsize t dsadd t fsadd t ssdat t hsdat t hgnt t sgnt clk attn_b gnt_b dr/w_b size2-size0 par3-par0 ad31-ad0 rdy_b (normal mode) rdy_b (early mode) data 1 (input) (input) (input) (output) data 0 (input)
data sheet s12100ej3v0ds00 25 m m m m pd98401a signals abrt b, err b, and oe_b parameter symbol condition min. typ. max. unit * abrt_b setup time t sabrt 8ns abrt_b hold time t habrt 3ns * err_b setup time t serr 8ns err_b hold time t herr 3ns * oe_b ? ad, par output definition time t dadoe 18 ns * oe_b - ? ad, par hi-z definition time t fadoe 18 ns dma abort/err b timing t habrt t sabrt t herr t serr clk attn_b gnt_b abrt_b err_b oe_b timing data 0 (output) data 0 (output) t fadoe hi-z t dadoe oe_b ad31-ad0 par3-par0
data sheet s12100ej3v0ds00 26 m m m m pd98401a bus monitoring signal parameter symbol condition min. typ. max. unit * clk - ? dbmd delay time t ddbmd 18 ns * clk - ? dbml delay time t ddbml 19 ns * clk - ? dbmf delay time t ddbmf 19 ns * clk - ? dbmr delay time t ddbmr 18 ns bus monitoring signal timing t ddbmd t ddbmr t ddbml t ddbml t ddbmf t ddbmf clk attn_b dbmd dbml dbmf dbmr
data sheet s12100ej3v0ds00 27 m m m m pd98401a control memory access (1/2) (1) write parameter symbol condition min. typ. max. unit * ca ? cwe_b setup time t scwe 0ns * cbe_b ? cwe_b setup time t scwe2 0ns * cwe_b low level width t cwel 1t clkh - 2ns * cwe_b -? cd floating time t fcd 01t clkl +10 ns * cwe_b -? coe_b delay time t dcoe 0ns * ca hold time (vs. cwe_b - )t hca 0ns cbe_b hold time (vs. cwe_b - )t hcbe 0ns cd output time (vs. cwe_b - )t scd 8ns cwe_b -? cpar floating time t fcpar 01t clkl +10 ns cpar output time (vs. cwe_b - )t scpar 8ns write timing t scwe2 t hcbe t hca t scwe t dcoe t cwel t scd t fcd t scpar t fcpar clk cbe_b3-cbe_b0 ca17-ca0 cwe_b coe_b cd31-cd0 cpar3-cpar0 (output) (output)
data sheet s12100ej3v0ds00 28 m m m m pd98401a control memory access (2/2) (2) read parameter symbol condition min. typ. max. unit * cd delay enable time (vs. cbe_b ) t dcdcb 1t cyclk - 15 ns * cd delay enable time (vs. ca) t dcdca 1t cyclk - 15 ns * cd delay enable time (vs. coe_b ) t dcdco 1t cyclk - 15 ns * cd hold time (vs. cbe_b - )t hcdcb 0ns * cd hold time (vs. ca) t hcdca 0ns * cd hold time (vs. coe_b - )t hcdco 0ns * cpar hold enable time (vs. cbe_b ) t dcpcb 1t cyclk - 15 ns * cpar hold enable time (vs. ca) t dcpca 1t cyclk - 15 ns * cpar hold enable time (vs. coe_ b )t dcpco 1t cyclk - 15 ns * cpar hold time (vs. cbe_b - )t hcpcb 0ns * cpar hold time (vs. ca) t hcpca 0ns * cpar hold time (vs. coe_b - )t hcpco 0ns read timing t dcdcb t dcdca t dcdco t hcdcb t hcdca t hcdco t hcpco t hcpca t hcpcb t dcpco t dcpca t dcpcb ? clk cbe_b3-cbe_b0 ca17-ca0 (input) (input) cwe_b coe_b cd31-cd0 cpar3-cpar0
data sheet s12100ej3v0ds00 29 m m m m pd98401a phy status access (1/2) (1) write parameter symbol condition min. typ. max. unit clk - ? ca delay time t dpca 20 ns * clk - ? phrw_b delay time t dphrw 20 ns * clk - ? phce_b delay time t dphce 20 ns clk - ? cd delay time t dpcd 20 ns phce_b - ? cd floating time t fpcd 1t cyclk - 10 1t cyclk +10 ns write timing t dpca t dpca 1 clock 1 clock 4 clocks t dphce ? (output) t dpcd t fpcd t dphce t dphrw clk ca17-ca0 phrw_b phce_b phoe_b cd31-cd0 t dphrw
data sheet s12100ej3v0ds00 30 m m m m pd98401a phy status access (2/2) (2) read parameter symbol condition min. typ. max. unit cd setup time t spcd 0ns cd hold time t hpoecd 0ns clk - ? ca delay time t dpca 20 ns * clk - ? phrw_b delay time t dphrw 20 ns * clk - ? phce_b delay time t dphce 20 ns * clk - ? phoe_b delay time t dphoe 20 ns read timing t dpca t dphce t dphce t dphoe t spcd t dphoe t hpoecd t dpca t dphrw (input) 1 clock 6 clocks 4 clocks 5 clocks clk ca17-ca0 phrw_b phce_b phoe_b cd31-cd0
data sheet s12100ej3v0ds00 31 m m m m pd98401a jtag boundary scan parameter symbol condition min. typ. max. unit jck cycle time t cyjck 100 ns jck high-level width t jckh 40 ns jck low-level width t jckl 40 ns jms setup time t sjms 10 ns jms hold time t hjms 10 ns jdi setup time t sjdi 10 ns jdi hold time t hjdi 10 ns capture_dr data input setup time t sjin 15 ns * capture_dr data input hold time t hjin 15 ns * jck ? up date_dr output delay time t djout 25 ns jck ? jdo delay time t djdo 20 ns jrst_b low-level width t jrstl 1t cyjck ns jtag boundary scan timing t cyjck t sjms t hjms t sjdi t djdo t hjdi t sjin t djout t hjin t jckl t jrstl t jckh jck jrst_b jms jdi jdo all input all output
data sheet s12100ej3v0ds00 32 m m m m pd98401a others parameter symbol condition min. typ. max. unit sel_b recovery time t rvsel 2t cyclk sel_b - ? gnt_b recovery time t rvsm 1t cyclk rdy_b - ? sel_b recovery time t rvms rdy_b mode in normal operation 1 t cyclk phint_b setup time t sphi 8ns phint_b hold time t hphi 1ns rst_b input pulse width t rstl 1t cyclk rst_b - ? sel_b recovery time t rstsl 20 t cyclk other timing t rvms t rvsel t rstl t rstsl t rvsm t hphi t sphi clk sel_b gnt_b rst_b rdy_b sel_b phint_b
data sheet s12100ej3v0ds00 33 m m m m pd98401a 4. package drawings 208-pin plastic qfp (fine pitch) (28x28) item millimeters f g 1.25 1.25 b c 28.0 0.2 28.0 0.2 h 0.22 i 0.10 s 3.8 max. k 1.3 0.2 l 0.5 0.2 m 0.17 n 0.10 p 3.2 0.1 + 0.05 - 0.04 j 0.5 (t.p.) p208gd-50-lml, mml, sml-6 + 0.03 - 0.07 r5 5 j i ns s detail of lead end q 0.4 0.1 m note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 1 208 52 53 156 157 105 104 c a b q r h k m l d p g f s a 30.6 0.2 d 30.6 0.2
data sheet s12100ej3v0ds00 34 m m m m pd98401a 5. recommended soldering conditions solder the product under the following recommended conditions. for details of the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for soldering methods and soldering conditions other than those recommended, consult nec. surface mount type m m m m pd98401agd-mml: 208-pin plastic qfp (fine pitch) (28 x 28 mm) soldering method soldering conditions symbol of recommended condition infrared reflow package peak temperature: 235 c, time: 30 seconds max. (210 c min.), number of times: 2 max., number of days: 7 note (afterwards, prebaking is necessary at 125 c for 36 hours.) ir35-367-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per side of device) - note the number of days during which the product can be stored at 25 c, 65 % rh max. after the dry pack has been opened.
data sheet s12100ej3v0ds00 35 m m m m pd98401a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m m m m pd98401a neascot-s10 and neascot-s15 are trademarks of nec corporation. the export of this product from japan is prohibited without governmental license. to export or re-export this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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