ma31750 - application note 11 1/6 1.0 introduction this application note presents a possible solution for a bus arbiter in a multiple-controller ma31750 system. such an arbiter can be used to arbitrate between the primary ma31750 system and 1 or more other bus masters. these bus masters can be other ma31750 systems, dma controllers such as the ma31753, or external interfaces. 2.0 processor considerations when designing a bus arbiter for an nma31750 system, the following points need to be taken into account: 2.1 lockn pull-ups the lockn signals should be pulled up because they go tristate when the processor is degranted. pull-ups are not shown in the arbiters that are described in the next sections, but they must be incorporated. 2.2 protected cycles the processor internally latches grantn on as falling to ensure that, when grantn is removed, the processor continues driving the busses, strobes and control signals until the cycle has completed. however, on the first external cycle after being granted, or the first external cycle after an internal cycle, this latch has not yet been clocked, and there is a danger, when removing grantn during these types of cycles, that the processor stops driving whilst strobes are still active. to prevent this from happening, these cycles must be protected from being degranted, or if grant is taken off during a protected cycle, it must be reasserted before as falling. 2.3 grantn timing the processor samples grantn on falling clkout, so an arbiter should not allow set-up and hold times to be violated. this can be achieved by latching out the grantn signals off the falling edge of clkout of the relevant system. in addition, note that as grantn falls to drive the address bus and strobes, the as can rise off a falling clk edge. this can erode the address set-up time to as rising. if this affects the system, then grantn must be asserted low to drive the address bus valid and provide the set-up time before the clk falling edge (and the as rising edge). 2.4 tclk timing if the ma31750 is degranted for long periods, a problem can occur: if after degranting the processor, the tclk falling edge is close to the falling clk edge at the end of the machine cycle, and then grant is not returned to that system until after another falling edge of tclk, a cycle may be aborted. (the time-out circuitry is disabled a short time after the end of the degranted cycle. if a tclk falling edge occurs between the end of the cycle and the disabling of the time-out circuit, then the time-out count remains active. this problem can occur irrespective of the state of dton.) this can be prevented by synchronising tclk to clk to ensure that tclk only changes during clkout high. this can be achieved by putting tclk through a d-type that is clocked by clkout from the same system (to be safe, 2 d-types should be used to prevent metastability problems). this is not shown in the next sections. 3.0 2 channel synchronous bus arbiter the following is an explanation of a bus arbiter that arbitrates between 2 systems, one of which is the default system (system1), but the other having priority over the first (system2). only the request from system2 is monitored - if it is asserted then grant is given to system2, otherwise grant is given to system1. the lock signals are also monitored to ensure that either system can keep grant during atomic instructions which should not be interrupted. both systems and the arbiter run off the same clock. an example of such a scheme would be an ma31750 system which gets the bus by default, and a dma controller which has priority over the processor. 3.1 bus arbitration logic the circuit is shown in figure 1. falling clkout is used to latch in requests and latch out grants to ensure sufficient set- up and hold time of grantn to clkout falling (see section 2.3). if the latched request changes state (and lockn is inactive), the active grant will be deasserted. although grant may be taken away immediately, no grant is given until activity on the bus has finished. the signal presetn, which prevents a new grant being assigned, is generated from as or active asserted with no grants (active comes from the cycle protect logic described in section 3.2). note that the arbitration logic can be overridden by protect, the other signal from the cycle protect logic (section 3.2), which keeps grant on or reassigns grant to the last system granted. 3.2 cycle protect logic the circuit is shown in figure 2. the cycle protect logic detects activity on the bus by sampling as on clkout falling. if as is sampled low, the cycle is inactive and the active signal is deasserted (low). active high inhibits granting i.e. grants can only be asserted on inactive cycles. this circuit also detects the first external cycle following inactivity on the bus, and from this it generates the signal protect which lasts until as falling i.e. until the end of the cycle to be protected. this signal is used to prevent degranting of either system if that system is executing the first external cycle. protecting this cycle from degranting is important for the correct operation of the processor (see section 2.2). note that the protected cycle can be either the first external cycle after grant has been asserted, or an external cycle following a granted internal cycle. it can happen that grant is taken off system1 while it is performing internal cycles but just as it is about to perform an external cycle. as soon as as goes high, the presetn signal, which is generated from as high with no grants, is asserted and prevents granting of system2. at the same time, the protect signal will become asserted and will reassign grant to system1 until the cycle is complete. AN3729 ma31750 - bus arbiter application note replaces july 2000 version, AN3729-3.0 AN3729-3.1 july 2002
ma31750 - application note 11 2/6 figure 1: 2 channel synchronous bus arbitration logic figure 2: synchronous cycle protect logic figure 3: 2 channel asynchronous bus arbitration logic d clk qb q pre lockn2 lockn1 reqn2 d clk q pre presetn grantn2 grantn1 gntn2 gntn1 lgnt1 d clk q p rotect clkout1 presetn d clk q pre protect lgnt2 clkout2 d clk clr qb q d clk q vcc protect as d clk q pre as as active clkout1 d clk qb q pre d clk q pre lockn2 lockn1 reqn2 d clk q pre presetn protect grantn2 grantn1 gntn2 gntn1 lgnt2 lgnt1 presetn p rotect clkout1 gntn2 gntn1 lgnt2 lgnt1 gntn2 gntn1 active as presetn
ma31750 - application note 11 3/6 4.0 2 channel asynchronous bus arbiter this section describes a bus arbiter that is required to arbitrate between 2 systems having separate asynchronous clocks e.g. a processor with an external interface. 4.1 bus arbitration logic the bus arbitration logic is shown in figure 3 (the grant latch and preset logic are the same as in figure 1). it is similar to the synchronous case except for the addition of another d- type clocked by clkout2 falling to synchronise grantn2 to system2. 4.2 asynchronous cycle protect logic the cycle protect logic is similar to the synchronous case, but now the clkout signals from both system1 and system2 are used to detect activity on the bus. the circuit is shown in figure 4. note that the latched grant signals lgnt1 and lgnt2 from the arbitration logic are used to select the clock from the system that was last granted. 5.0 3 channel synchronous bus arbiter this section describes a 3 channel synchronous bus arbiter where system1 is again the default system, system2 has priority over system1 and system3 has priority over both of the other 2 systems (e.g. a processor and 2 dma controllers). 5.1 bus arbitration logic figure 5 shows the bus arbitration logic which is simply an extension of the 2 channel case. 5.2 cycle protect logic this is exactly the same as for the 2 channel synchronous bus arbiter (figure 2). 6.0 3 channel asynchronous bus arbiter this section describes a bus arbiter that is required to arbitrate between 3 systems having separate asynchronous clocks e.g. a processor with 2 external interfaces. 6.1 bus arbitration logic the bus arbitration logic is shown in figure 6 (the grant latch and the preset logic are the same as in figure 5). it is similar to the synchronous case except for the addition of 2 d- types clocked by clkout2 and clkout3 falling to synchronise grantn2 and grantn3 to systems 2 and 3 respectively. 6.2 asynchronous cycle protect logic the cycle protect logic is similar to figure 4, but now the clkout signals from all 3 systems are used to detect activity on the bus. the circuit is shown in figure 7. 6.3 waveforms figure 8 shows typical waveforms for the 3 channel asynchronous arbiter described above. the sequence of events is as follows: 1) system 3 executes an external cycle during which it deasserts reqn3. 2) grantn3 is deasserted when reqn3 high is latched. 3) active goes low followed by grantn1 being asserted. 4) system1 executes 2 external cycles followed by an internal cycle, reqn2 is asserted during the internal cycle. 5) reqn2 low is latched and grantn1 is deasserted. 6) system 1 executes another external cycle so protect is asserted and grantn1 reasserted. 7) grantn1 is deasserted at the end of this cycle. 8) when active has gone low, grantn2 is asserted. 9) system 2 starts executing external cycles, starting with a protected cycle. figure 4: 2 channel asysnchronous cycle protect logic clkout1 clkout2 d clk clr q d clk q pre d clk clr qb q vcc protect d clk clr q lgnt1 lgnt2 as as as as active
ma31750 - application note 11 4/6 figure 6: 3 channel asynchronous bus arbitration logic figure 5: 3 channel synchronous bus arbitration logic d clk qb q pre lockn2 reqn2 d clk qb q pre protect grantn2 gntn2 gntn1 lgnt2 lgnt1 grantn3 d clk q pre d clk q pre presetn grantn1 d clk q pre lgnt3 lockn1 lockn3 reqn3 gntn3 presetn presetn protect protect lockn1 lockn2 clkout1 as gntn1 gntn2 presetn gntn3 active gntn3 gntn2 gntn1 lgnt3 lgnt2 lgnt1 grantn2 grantn3 grantn1 d clk qb q pre lockn2 reqn2 d clk qb q pre protect gntn2 gntn1 lgnt2 lgnt1 presetn d clk q pre lgnt3 lockn1 lockn3 reqn3 gntn3 d clk q d clk q protect lockn1 lockn2 clkout1 d clk q pre presetn presetn d clk q pre clkout3 clkout2 protect
ma31750 - application note 11 5/6 figure 7: 3 channel asynchronous cycle protect logic figure 8: typical waveforms for 2 channel asynchronous arbiter clkout1 clkout2 d clk clr q d clk clr qb q vcc protect lgnt1 lgnt2 d clk clr q d clk clr q clkout3 lgnt3 d clk q pre as as as as as active as reqn2 grantn1 grantn2 protect presetn active clkout2 clkout1 clkout3 grantn3 reqn3
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